1 /* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */
3 * Copyright 2004 Olivier Houchard.
4 * Copyright 2003 Wasabi Systems, Inc.
7 * Written by Steve C. Woodford for Wasabi Systems, Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
39 * Copyright (c) 2002-2003 Wasabi Systems, Inc.
40 * Copyright (c) 2001 Richard Earnshaw
41 * Copyright (c) 2001-2002 Christopher Gilbert
42 * All rights reserved.
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. The name of the company nor the name of the author may be used to
50 * endorse or promote products derived from this software without specific
51 * prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
66 * Copyright (c) 1999 The NetBSD Foundation, Inc.
67 * All rights reserved.
69 * This code is derived from software contributed to The NetBSD Foundation
70 * by Charles M. Hannum.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
81 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
82 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
83 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
84 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
85 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
86 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
87 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
88 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
89 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
90 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
91 * POSSIBILITY OF SUCH DAMAGE.
95 * Copyright (c) 1994-1998 Mark Brinicombe.
96 * Copyright (c) 1994 Brini.
97 * All rights reserved.
99 * This code is derived from software written for Brini by Mark Brinicombe
101 * Redistribution and use in source and binary forms, with or without
102 * modification, are permitted provided that the following conditions
104 * 1. Redistributions of source code must retain the above copyright
105 * notice, this list of conditions and the following disclaimer.
106 * 2. Redistributions in binary form must reproduce the above copyright
107 * notice, this list of conditions and the following disclaimer in the
108 * documentation and/or other materials provided with the distribution.
109 * 3. All advertising materials mentioning features or use of this software
110 * must display the following acknowledgement:
111 * This product includes software developed by Mark Brinicombe.
112 * 4. The name of the author may not be used to endorse or promote products
113 * derived from this software without specific prior written permission.
115 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
116 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
117 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
118 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
119 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
120 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
121 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
122 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
123 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
125 * RiscBSD kernel project
129 * Machine dependent vm stuff
135 * Special compilation symbols
136 * PMAP_DEBUG - Build in pmap_debug_level code
138 * Note that pmap_mapdev() and pmap_unmapdev() are implemented in arm/devmap.c
140 /* Include header files */
144 #include <sys/cdefs.h>
145 __FBSDID("$FreeBSD$");
146 #include <sys/param.h>
147 #include <sys/systm.h>
148 #include <sys/kernel.h>
150 #include <sys/lock.h>
151 #include <sys/proc.h>
152 #include <sys/malloc.h>
153 #include <sys/msgbuf.h>
154 #include <sys/mutex.h>
155 #include <sys/vmmeter.h>
156 #include <sys/mman.h>
157 #include <sys/rwlock.h>
159 #include <sys/sched.h>
162 #include <vm/vm_param.h>
165 #include <vm/vm_kern.h>
166 #include <vm/vm_object.h>
167 #include <vm/vm_map.h>
168 #include <vm/vm_page.h>
169 #include <vm/vm_pageout.h>
170 #include <vm/vm_phys.h>
171 #include <vm/vm_pagequeue.h>
172 #include <vm/vm_extern.h>
174 #include <machine/md_var.h>
175 #include <machine/cpu.h>
176 #include <machine/cpufunc.h>
177 #include <machine/pcb.h>
180 #define PDEBUG(_lev_,_stat_) \
181 if (pmap_debug_level >= (_lev_)) \
183 #define dprintf printf
185 int pmap_debug_level = 0;
187 #else /* PMAP_DEBUG */
188 #define PDEBUG(_lev_,_stat_) /* Nothing */
189 #define dprintf(x, arg...)
190 #define PMAP_INLINE __inline
191 #endif /* PMAP_DEBUG */
193 extern struct pv_addr systempage;
195 extern int last_fault_code;
198 * Internal function prototypes
200 static void pmap_free_pv_entry (pv_entry_t);
201 static pv_entry_t pmap_get_pv_entry(void);
203 static int pmap_enter_locked(pmap_t, vm_offset_t, vm_page_t,
205 static vm_paddr_t pmap_extract_locked(pmap_t pmap, vm_offset_t va);
206 static void pmap_fix_cache(struct vm_page *, pmap_t, vm_offset_t);
207 static void pmap_alloc_l1(pmap_t);
208 static void pmap_free_l1(pmap_t);
210 static int pmap_clearbit(struct vm_page *, u_int);
212 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t);
213 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t);
214 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int);
215 static vm_offset_t kernel_pt_lookup(vm_paddr_t);
217 static MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1");
219 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
220 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
221 vm_offset_t pmap_curmaxkvaddr;
222 vm_paddr_t kernel_l1pa;
224 vm_offset_t kernel_vm_end = 0;
226 vm_offset_t vm_max_kernel_address;
228 struct pmap kernel_pmap_store;
230 static pt_entry_t *csrc_pte, *cdst_pte;
231 static vm_offset_t csrcp, cdstp, qmap_addr;
232 static struct mtx cmtx, qmap_mtx;
234 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *);
236 * These routines are called when the CPU type is identified to set up
237 * the PTE prototypes, cache modes, etc.
239 * The variables are always here, just in case LKMs need to reference
240 * them (though, they shouldn't).
243 pt_entry_t pte_l1_s_cache_mode;
244 pt_entry_t pte_l1_s_cache_mode_pt;
245 pt_entry_t pte_l1_s_cache_mask;
247 pt_entry_t pte_l2_l_cache_mode;
248 pt_entry_t pte_l2_l_cache_mode_pt;
249 pt_entry_t pte_l2_l_cache_mask;
251 pt_entry_t pte_l2_s_cache_mode;
252 pt_entry_t pte_l2_s_cache_mode_pt;
253 pt_entry_t pte_l2_s_cache_mask;
255 pt_entry_t pte_l2_s_prot_u;
256 pt_entry_t pte_l2_s_prot_w;
257 pt_entry_t pte_l2_s_prot_mask;
259 pt_entry_t pte_l1_s_proto;
260 pt_entry_t pte_l1_c_proto;
261 pt_entry_t pte_l2_s_proto;
263 void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t);
264 void (*pmap_copy_page_offs_func)(vm_paddr_t a_phys,
265 vm_offset_t a_offs, vm_paddr_t b_phys, vm_offset_t b_offs,
267 void (*pmap_zero_page_func)(vm_paddr_t, int, int);
272 static caddr_t crashdumpmap;
274 extern void bcopy_page(vm_offset_t, vm_offset_t);
275 extern void bzero_page(vm_offset_t);
277 extern vm_offset_t alloc_firstaddr;
282 * Metadata for L1 translation tables.
285 /* Entry on the L1 Table list */
286 SLIST_ENTRY(l1_ttable) l1_link;
288 /* Entry on the L1 Least Recently Used list */
289 TAILQ_ENTRY(l1_ttable) l1_lru;
291 /* Track how many domains are allocated from this L1 */
292 volatile u_int l1_domain_use_count;
295 * A free-list of domain numbers for this L1.
296 * We avoid using ffs() and a bitmap to track domains since ffs()
299 u_int8_t l1_domain_first;
300 u_int8_t l1_domain_free[PMAP_DOMAINS];
302 /* Physical address of this L1 page table */
303 vm_paddr_t l1_physaddr;
305 /* KVA of this L1 page table */
310 * Convert a virtual address into its L1 table index. That is, the
311 * index used to locate the L2 descriptor table pointer in an L1 table.
312 * This is basically used to index l1->l1_kva[].
314 * Each L2 descriptor table represents 1MB of VA space.
316 #define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT)
319 * L1 Page Tables are tracked using a Least Recently Used list.
320 * - New L1s are allocated from the HEAD.
321 * - Freed L1s are added to the TAIl.
322 * - Recently accessed L1s (where an 'access' is some change to one of
323 * the userland pmaps which owns this L1) are moved to the TAIL.
325 static TAILQ_HEAD(, l1_ttable) l1_lru_list;
327 * A list of all L1 tables
329 static SLIST_HEAD(, l1_ttable) l1_list;
330 static struct mtx l1_lru_lock;
333 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots.
335 * This is normally 16MB worth L2 page descriptors for any given pmap.
336 * Reference counts are maintained for L2 descriptors so they can be
340 /* The number of L2 page descriptors allocated to this l2_dtable */
343 /* List of L2 page descriptors */
345 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */
346 vm_paddr_t l2b_phys; /* Physical address of same */
347 u_short l2b_l1idx; /* This L2 table's L1 index */
348 u_short l2b_occupancy; /* How many active descriptors */
349 } l2_bucket[L2_BUCKET_SIZE];
352 /* pmap_kenter_internal flags */
353 #define KENTER_CACHE 0x1
354 #define KENTER_USER 0x2
357 * Given an L1 table index, calculate the corresponding l2_dtable index
358 * and bucket index within the l2_dtable.
360 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \
362 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1))
365 * Given a virtual address, this macro returns the
366 * virtual address required to drop into the next L2 bucket.
368 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE)
371 * We try to map the page tables write-through, if possible. However, not
372 * all CPUs have a write-through cache mode, so on those we have to sync
373 * the cache when we frob page tables.
375 * We try to evaluate this at compile time, if possible. However, it's
376 * not always possible to do that, hence this run-time var.
378 int pmap_needs_pte_sync;
381 * Macro to determine if a mapping might be resident in the
382 * instruction cache and/or TLB
384 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC))
387 * Macro to determine if a mapping might be resident in the
388 * data cache and/or TLB
390 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0)
392 #ifndef PMAP_SHPGPERPROC
393 #define PMAP_SHPGPERPROC 200
396 #define pmap_is_current(pm) ((pm) == kernel_pmap || \
397 curproc->p_vmspace->vm_map.pmap == (pm))
398 static uma_zone_t pvzone = NULL;
400 static uma_zone_t l2table_zone;
401 static vm_offset_t pmap_kernel_l2dtable_kva;
402 static vm_offset_t pmap_kernel_l2ptp_kva;
403 static vm_paddr_t pmap_kernel_l2ptp_phys;
404 static int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0;
405 static struct rwlock pvh_global_lock;
407 void pmap_copy_page_offs_generic(vm_paddr_t a_phys, vm_offset_t a_offs,
408 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt);
409 #if ARM_MMU_XSCALE == 1
410 void pmap_copy_page_offs_xscale(vm_paddr_t a_phys, vm_offset_t a_offs,
411 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt);
415 * This list exists for the benefit of pmap_map_chunk(). It keeps track
416 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can
417 * find them as necessary.
419 * Note that the data on this list MUST remain valid after initarm() returns,
420 * as pmap_bootstrap() uses it to contruct L2 table metadata.
422 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list);
425 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt)
430 l1->l1_domain_use_count = 0;
431 l1->l1_domain_first = 0;
433 for (i = 0; i < PMAP_DOMAINS; i++)
434 l1->l1_domain_free[i] = i + 1;
437 * Copy the kernel's L1 entries to each new L1.
439 if (l1pt != kernel_pmap->pm_l1->l1_kva)
440 memcpy(l1pt, kernel_pmap->pm_l1->l1_kva, L1_TABLE_SIZE);
442 if ((l1->l1_physaddr = pmap_extract(kernel_pmap, (vm_offset_t)l1pt)) == 0)
443 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt);
444 SLIST_INSERT_HEAD(&l1_list, l1, l1_link);
445 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
449 kernel_pt_lookup(vm_paddr_t pa)
453 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) {
460 #if ARM_MMU_GENERIC != 0
462 pmap_pte_init_generic(void)
465 pte_l1_s_cache_mode = L1_S_B|L1_S_C;
466 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic;
468 pte_l2_l_cache_mode = L2_B|L2_C;
469 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic;
471 pte_l2_s_cache_mode = L2_B|L2_C;
472 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic;
475 * If we have a write-through cache, set B and C. If
476 * we have a write-back cache, then we assume setting
477 * only C will make those pages write-through.
479 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) {
480 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
481 pte_l2_l_cache_mode_pt = L2_B|L2_C;
482 pte_l2_s_cache_mode_pt = L2_B|L2_C;
484 pte_l1_s_cache_mode_pt = L1_S_C;
485 pte_l2_l_cache_mode_pt = L2_C;
486 pte_l2_s_cache_mode_pt = L2_C;
489 pte_l2_s_prot_u = L2_S_PROT_U_generic;
490 pte_l2_s_prot_w = L2_S_PROT_W_generic;
491 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic;
493 pte_l1_s_proto = L1_S_PROTO_generic;
494 pte_l1_c_proto = L1_C_PROTO_generic;
495 pte_l2_s_proto = L2_S_PROTO_generic;
497 pmap_copy_page_func = pmap_copy_page_generic;
498 pmap_copy_page_offs_func = pmap_copy_page_offs_generic;
499 pmap_zero_page_func = pmap_zero_page_generic;
502 #endif /* ARM_MMU_GENERIC != 0 */
504 #if ARM_MMU_XSCALE == 1
505 #if (ARM_NMMUS > 1) || defined (CPU_XSCALE_CORE3)
506 static u_int xscale_use_minidata;
510 pmap_pte_init_xscale(void)
513 int write_through = 0;
515 pte_l1_s_cache_mode = L1_S_B|L1_S_C|L1_S_XSCALE_P;
516 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale;
518 pte_l2_l_cache_mode = L2_B|L2_C;
519 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale;
521 pte_l2_s_cache_mode = L2_B|L2_C;
522 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale;
524 pte_l1_s_cache_mode_pt = L1_S_C;
525 pte_l2_l_cache_mode_pt = L2_C;
526 pte_l2_s_cache_mode_pt = L2_C;
527 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE
529 * The XScale core has an enhanced mode where writes that
530 * miss the cache cause a cache line to be allocated. This
531 * is significantly faster than the traditional, write-through
532 * behavior of this case.
534 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X);
535 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X);
536 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X);
537 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */
538 #ifdef XSCALE_CACHE_WRITE_THROUGH
540 * Some versions of the XScale core have various bugs in
541 * their cache units, the work-around for which is to run
542 * the cache in write-through mode. Unfortunately, this
543 * has a major (negative) impact on performance. So, we
544 * go ahead and run fast-and-loose, in the hopes that we
545 * don't line up the planets in a way that will trip the
548 * However, we give you the option to be slow-but-correct.
551 #elif defined(XSCALE_CACHE_WRITE_BACK)
552 /* force write back cache mode */
554 #elif defined(CPU_XSCALE_PXA2X0)
556 * Intel PXA2[15]0 processors are known to have a bug in
557 * write-back cache on revision 4 and earlier (stepping
558 * A[01] and B[012]). Fixed for C0 and later.
564 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK);
566 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) {
567 if ((id & CPU_ID_REVISION_MASK) < 5) {
568 /* write through for stepping A0-1 and B0-2 */
573 #endif /* XSCALE_CACHE_WRITE_THROUGH */
576 pte_l1_s_cache_mode = L1_S_C;
577 pte_l2_l_cache_mode = L2_C;
578 pte_l2_s_cache_mode = L2_C;
582 xscale_use_minidata = 1;
585 pte_l2_s_prot_u = L2_S_PROT_U_xscale;
586 pte_l2_s_prot_w = L2_S_PROT_W_xscale;
587 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale;
589 pte_l1_s_proto = L1_S_PROTO_xscale;
590 pte_l1_c_proto = L1_C_PROTO_xscale;
591 pte_l2_s_proto = L2_S_PROTO_xscale;
593 #ifdef CPU_XSCALE_CORE3
594 pmap_copy_page_func = pmap_copy_page_generic;
595 pmap_copy_page_offs_func = pmap_copy_page_offs_generic;
596 pmap_zero_page_func = pmap_zero_page_generic;
597 xscale_use_minidata = 0;
598 /* Make sure it is L2-cachable */
599 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_T);
600 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode &~ L1_S_XSCALE_P;
601 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_T) ;
602 pte_l2_l_cache_mode_pt = pte_l1_s_cache_mode;
603 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_T);
604 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode;
607 pmap_copy_page_func = pmap_copy_page_xscale;
608 pmap_copy_page_offs_func = pmap_copy_page_offs_xscale;
609 pmap_zero_page_func = pmap_zero_page_xscale;
613 * Disable ECC protection of page table access, for now.
615 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
616 auxctl &= ~XSCALE_AUXCTL_P;
617 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
621 * xscale_setup_minidata:
623 * Set up the mini-data cache clean area. We require the
624 * caller to allocate the right amount of physically and
625 * virtually contiguous space.
627 extern vm_offset_t xscale_minidata_clean_addr;
628 extern vm_size_t xscale_minidata_clean_size; /* already initialized */
630 xscale_setup_minidata(vm_offset_t l1pt, vm_offset_t va, vm_paddr_t pa)
632 pd_entry_t *pde = (pd_entry_t *) l1pt;
637 xscale_minidata_clean_addr = va;
639 /* Round it to page size. */
640 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME;
643 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) {
644 pte = (pt_entry_t *) kernel_pt_lookup(
645 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
647 panic("xscale_setup_minidata: can't find L2 table for "
648 "VA 0x%08x", (u_int32_t) va);
649 pte[l2pte_index(va)] =
650 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
651 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X);
655 * Configure the mini-data cache for write-back with
656 * read/write-allocate.
658 * NOTE: In order to reconfigure the mini-data cache, we must
659 * make sure it contains no valid data! In order to do that,
660 * we must issue a global data cache invalidate command!
662 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED!
663 * THIS IS VERY IMPORTANT!
666 /* Invalidate data and mini-data. */
667 __asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
668 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
669 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA;
670 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
675 * Allocate an L1 translation table for the specified pmap.
676 * This is called at pmap creation time.
679 pmap_alloc_l1(pmap_t pm)
681 struct l1_ttable *l1;
685 * Remove the L1 at the head of the LRU list
687 mtx_lock(&l1_lru_lock);
688 l1 = TAILQ_FIRST(&l1_lru_list);
689 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
692 * Pick the first available domain number, and update
693 * the link to the next number.
695 domain = l1->l1_domain_first;
696 l1->l1_domain_first = l1->l1_domain_free[domain];
699 * If there are still free domain numbers in this L1,
700 * put it back on the TAIL of the LRU list.
702 if (++l1->l1_domain_use_count < PMAP_DOMAINS)
703 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
705 mtx_unlock(&l1_lru_lock);
708 * Fix up the relevant bits in the pmap structure
711 pm->pm_domain = domain + 1;
715 * Free an L1 translation table.
716 * This is called at pmap destruction time.
719 pmap_free_l1(pmap_t pm)
721 struct l1_ttable *l1 = pm->pm_l1;
723 mtx_lock(&l1_lru_lock);
726 * If this L1 is currently on the LRU list, remove it.
728 if (l1->l1_domain_use_count < PMAP_DOMAINS)
729 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
732 * Free up the domain number which was allocated to the pmap
734 l1->l1_domain_free[pm->pm_domain - 1] = l1->l1_domain_first;
735 l1->l1_domain_first = pm->pm_domain - 1;
736 l1->l1_domain_use_count--;
739 * The L1 now must have at least 1 free domain, so add
740 * it back to the LRU list. If the use count is zero,
741 * put it at the head of the list, otherwise it goes
744 if (l1->l1_domain_use_count == 0) {
745 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru);
747 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
749 mtx_unlock(&l1_lru_lock);
753 * Returns a pointer to the L2 bucket associated with the specified pmap
754 * and VA, or NULL if no L2 bucket exists for the address.
756 static PMAP_INLINE struct l2_bucket *
757 pmap_get_l2_bucket(pmap_t pm, vm_offset_t va)
759 struct l2_dtable *l2;
760 struct l2_bucket *l2b;
765 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL ||
766 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL)
773 * Returns a pointer to the L2 bucket associated with the specified pmap
776 * If no L2 bucket exists, perform the necessary allocations to put an L2
777 * bucket/page table in place.
779 * Note that if a new L2 bucket/page was allocated, the caller *must*
780 * increment the bucket occupancy counter appropriately *before*
781 * releasing the pmap's lock to ensure no other thread or cpu deallocates
782 * the bucket/page in the meantime.
784 static struct l2_bucket *
785 pmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va)
787 struct l2_dtable *l2;
788 struct l2_bucket *l2b;
793 PMAP_ASSERT_LOCKED(pm);
794 rw_assert(&pvh_global_lock, RA_WLOCKED);
795 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
797 * No mapping at this address, as there is
798 * no entry in the L1 table.
799 * Need to allocate a new l2_dtable.
802 rw_wunlock(&pvh_global_lock);
803 if ((l2 = uma_zalloc(l2table_zone, M_NOWAIT)) == NULL) {
804 rw_wlock(&pvh_global_lock);
808 rw_wlock(&pvh_global_lock);
810 if (pm->pm_l2[L2_IDX(l1idx)] != NULL) {
812 * Someone already allocated the l2_dtable while
813 * we were doing the same.
815 uma_zfree(l2table_zone, l2);
816 l2 = pm->pm_l2[L2_IDX(l1idx)];
818 bzero(l2, sizeof(*l2));
820 * Link it into the parent pmap
822 pm->pm_l2[L2_IDX(l1idx)] = l2;
826 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
829 * Fetch pointer to the L2 page table associated with the address.
831 if (l2b->l2b_kva == NULL) {
835 * No L2 page table has been allocated. Chances are, this
836 * is because we just allocated the l2_dtable, above.
840 rw_wunlock(&pvh_global_lock);
841 ptep = uma_zalloc(l2zone, M_NOWAIT);
842 rw_wlock(&pvh_global_lock);
844 if (l2b->l2b_kva != NULL) {
845 /* We lost the race. */
847 uma_zfree(l2zone, ptep);
850 l2b->l2b_phys = vtophys(ptep);
853 * Oops, no more L2 page tables available at this
854 * time. We may need to deallocate the l2_dtable
855 * if we allocated a new one above.
858 if (l2->l2_occupancy == 0) {
859 pm->pm_l2[L2_IDX(l1idx)] = NULL;
860 uma_zfree(l2table_zone, l2);
866 l2b->l2b_l1idx = l1idx;
872 static PMAP_INLINE void
873 #ifndef PMAP_INCLUDE_PTE_SYNC
874 pmap_free_l2_ptp(pt_entry_t *l2)
876 pmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2)
879 #ifdef PMAP_INCLUDE_PTE_SYNC
881 * Note: With a write-back cache, we may need to sync this
882 * L2 table before re-using it.
883 * This is because it may have belonged to a non-current
884 * pmap, in which case the cache syncs would have been
885 * skipped when the pages were being unmapped. If the
886 * L2 table were then to be immediately re-allocated to
887 * the *current* pmap, it may well contain stale mappings
888 * which have not yet been cleared by a cache write-back
889 * and so would still be visible to the mmu.
892 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
894 uma_zfree(l2zone, l2);
897 * One or more mappings in the specified L2 descriptor table have just been
900 * Garbage collect the metadata and descriptor table itself if necessary.
902 * The pmap lock must be acquired when this is called (not necessary
903 * for the kernel pmap).
906 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count)
908 struct l2_dtable *l2;
909 pd_entry_t *pl1pd, l1pd;
915 * Update the bucket's reference count according to how many
916 * PTEs the caller has just invalidated.
918 l2b->l2b_occupancy -= count;
923 * Level 2 page tables allocated to the kernel pmap are never freed
924 * as that would require checking all Level 1 page tables and
925 * removing any references to the Level 2 page table. See also the
926 * comment elsewhere about never freeing bootstrap L2 descriptors.
928 * We make do with just invalidating the mapping in the L2 table.
930 * This isn't really a big deal in practice and, in fact, leads
931 * to a performance win over time as we don't need to continually
934 if (l2b->l2b_occupancy > 0 || pm == kernel_pmap)
938 * There are no more valid mappings in this level 2 page table.
939 * Go ahead and NULL-out the pointer in the bucket, then
940 * free the page table.
942 l1idx = l2b->l2b_l1idx;
946 pl1pd = &pm->pm_l1->l1_kva[l1idx];
949 * If the L1 slot matches the pmap's domain
950 * number, then invalidate it.
952 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK);
953 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) {
959 * Release the L2 descriptor table back to the pool cache.
961 #ifndef PMAP_INCLUDE_PTE_SYNC
962 pmap_free_l2_ptp(ptep);
964 pmap_free_l2_ptp(!pmap_is_current(pm), ptep);
968 * Update the reference count in the associated l2_dtable
970 l2 = pm->pm_l2[L2_IDX(l1idx)];
971 if (--l2->l2_occupancy > 0)
975 * There are no more valid mappings in any of the Level 1
976 * slots managed by this l2_dtable. Go ahead and NULL-out
977 * the pointer in the parent pmap and free the l2_dtable.
979 pm->pm_l2[L2_IDX(l1idx)] = NULL;
980 uma_zfree(l2table_zone, l2);
984 * Pool cache constructors for L2 descriptor tables, metadata and pmap
988 pmap_l2ptp_ctor(void *mem, int size, void *arg, int flags)
990 #ifndef PMAP_INCLUDE_PTE_SYNC
991 struct l2_bucket *l2b;
992 pt_entry_t *ptep, pte;
994 vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK;
997 * The mappings for these page tables were initially made using
998 * pmap_kenter() by the pool subsystem. Therefore, the cache-
999 * mode will not be right for page table mappings. To avoid
1000 * polluting the pmap_kenter() code with a special case for
1001 * page tables, we simply fix up the cache-mode here if it's not
1004 l2b = pmap_get_l2_bucket(kernel_pmap, va);
1005 ptep = &l2b->l2b_kva[l2pte_index(va)];
1008 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
1010 * Page tables must have the cache-mode set to
1013 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
1015 cpu_tlb_flushD_SE(va);
1019 memset(mem, 0, L2_TABLE_SIZE_REAL);
1020 PTE_SYNC_RANGE(mem, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
1025 * A bunch of routines to conditionally flush the caches/TLB depending
1026 * on whether the specified pmap actually needs to be flushed at any
1029 static PMAP_INLINE void
1030 pmap_tlb_flushID_SE(pmap_t pm, vm_offset_t va)
1033 if (pmap_is_current(pm))
1034 cpu_tlb_flushID_SE(va);
1037 static PMAP_INLINE void
1038 pmap_tlb_flushD_SE(pmap_t pm, vm_offset_t va)
1041 if (pmap_is_current(pm))
1042 cpu_tlb_flushD_SE(va);
1045 static PMAP_INLINE void
1046 pmap_tlb_flushID(pmap_t pm)
1049 if (pmap_is_current(pm))
1052 static PMAP_INLINE void
1053 pmap_tlb_flushD(pmap_t pm)
1056 if (pmap_is_current(pm))
1061 pmap_has_valid_mapping(pmap_t pm, vm_offset_t va)
1066 if (pmap_get_pde_pte(pm, va, &pde, &ptep) &&
1067 ptep && ((*ptep & L2_TYPE_MASK) != L2_TYPE_INV))
1073 static PMAP_INLINE void
1074 pmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len)
1078 CTR4(KTR_PMAP, "pmap_dcache_wbinv_range: pmap %p is_kernel %d va 0x%08x"
1079 " len 0x%x ", pm, pm == kernel_pmap, va, len);
1081 if (pmap_is_current(pm) || pm == kernel_pmap) {
1082 rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len);
1084 if (pmap_has_valid_mapping(pm, va)) {
1085 cpu_idcache_wbinv_range(va, rest);
1086 cpu_l2cache_wbinv_range(va, rest);
1090 rest = MIN(PAGE_SIZE, len);
1095 static PMAP_INLINE void
1096 pmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len, boolean_t do_inv,
1101 CTR4(KTR_PMAP, "pmap_dcache_wb_range: pmap %p is_kernel %d va 0x%08x "
1102 "len 0x%x ", pm, pm == kernel_pmap, va, len);
1103 CTR2(KTR_PMAP, " do_inv %d rd_only %d", do_inv, rd_only);
1105 if (pmap_is_current(pm)) {
1106 rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len);
1108 if (pmap_has_valid_mapping(pm, va)) {
1109 if (do_inv && rd_only) {
1110 cpu_dcache_inv_range(va, rest);
1111 cpu_l2cache_inv_range(va, rest);
1112 } else if (do_inv) {
1113 cpu_dcache_wbinv_range(va, rest);
1114 cpu_l2cache_wbinv_range(va, rest);
1115 } else if (!rd_only) {
1116 cpu_dcache_wb_range(va, rest);
1117 cpu_l2cache_wb_range(va, rest);
1123 rest = MIN(PAGE_SIZE, len);
1128 static PMAP_INLINE void
1129 pmap_idcache_wbinv_all(pmap_t pm)
1132 if (pmap_is_current(pm)) {
1133 cpu_idcache_wbinv_all();
1134 cpu_l2cache_wbinv_all();
1139 static PMAP_INLINE void
1140 pmap_dcache_wbinv_all(pmap_t pm)
1143 if (pmap_is_current(pm)) {
1144 cpu_dcache_wbinv_all();
1145 cpu_l2cache_wbinv_all();
1153 * Make sure the pte is written out to RAM.
1154 * We need to do this for one of two cases:
1155 * - We're dealing with the kernel pmap
1156 * - There is no pmap active in the cache/tlb.
1157 * - The specified pmap is 'active' in the cache/tlb.
1159 #ifdef PMAP_INCLUDE_PTE_SYNC
1160 #define PTE_SYNC_CURRENT(pm, ptep) \
1162 if (PMAP_NEEDS_PTE_SYNC && \
1163 pmap_is_current(pm)) \
1165 } while (/*CONSTCOND*/0)
1167 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */
1171 * cacheable == -1 means we must make the entry uncacheable, 1 means
1174 static __inline void
1175 pmap_set_cache_entry(pv_entry_t pv, pmap_t pm, vm_offset_t va, int cacheable)
1177 struct l2_bucket *l2b;
1178 pt_entry_t *ptep, pte;
1180 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
1181 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
1183 if (cacheable == 1) {
1184 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode;
1185 if (l2pte_valid(pte)) {
1186 if (PV_BEEN_EXECD(pv->pv_flags)) {
1187 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va);
1188 } else if (PV_BEEN_REFD(pv->pv_flags)) {
1189 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va);
1193 pte = *ptep &~ L2_S_CACHE_MASK;
1194 if ((va != pv->pv_va || pm != pv->pv_pmap) &&
1196 if (PV_BEEN_EXECD(pv->pv_flags)) {
1197 pmap_idcache_wbinv_range(pv->pv_pmap,
1198 pv->pv_va, PAGE_SIZE);
1199 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va);
1200 } else if (PV_BEEN_REFD(pv->pv_flags)) {
1201 pmap_dcache_wb_range(pv->pv_pmap,
1202 pv->pv_va, PAGE_SIZE, TRUE,
1203 (pv->pv_flags & PVF_WRITE) == 0);
1204 pmap_tlb_flushD_SE(pv->pv_pmap,
1210 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
1214 pmap_fix_cache(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1217 int writable = 0, kwritable = 0, uwritable = 0;
1218 int entries = 0, kentries = 0, uentries = 0;
1219 struct pv_entry *pv;
1221 rw_assert(&pvh_global_lock, RA_WLOCKED);
1223 /* the cache gets written back/invalidated on context switch.
1224 * therefore, if a user page shares an entry in the same page or
1225 * with the kernel map and at least one is writable, then the
1226 * cache entry must be set write-through.
1229 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1230 /* generate a count of the pv_entry uses */
1231 if (pv->pv_flags & PVF_WRITE) {
1232 if (pv->pv_pmap == kernel_pmap)
1234 else if (pv->pv_pmap == pm)
1238 if (pv->pv_pmap == kernel_pmap)
1241 if (pv->pv_pmap == pm)
1247 * check if the user duplicate mapping has
1250 if ((pm != kernel_pmap) && (((uentries > 1) && uwritable) ||
1254 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1255 /* check for user uncachable conditions - order is important */
1256 if (pm != kernel_pmap &&
1257 (pv->pv_pmap == pm || pv->pv_pmap == kernel_pmap)) {
1259 if ((uentries > 1 && uwritable) || uwritable > 1) {
1261 /* user duplicate mapping */
1262 if (pv->pv_pmap != kernel_pmap)
1263 pv->pv_flags |= PVF_MWC;
1265 if (!(pv->pv_flags & PVF_NC)) {
1266 pv->pv_flags |= PVF_NC;
1267 pmap_set_cache_entry(pv, pm, va, -1);
1270 } else /* no longer a duplicate user */
1271 pv->pv_flags &= ~PVF_MWC;
1275 * check for kernel uncachable conditions
1276 * kernel writable or kernel readable with writable user entry
1278 if ((kwritable && (entries || kentries > 1)) ||
1280 ((kwritable != writable) && kentries &&
1281 (pv->pv_pmap == kernel_pmap ||
1282 (pv->pv_flags & PVF_WRITE) ||
1283 (pv->pv_flags & PVF_MWC)))) {
1285 if (!(pv->pv_flags & PVF_NC)) {
1286 pv->pv_flags |= PVF_NC;
1287 pmap_set_cache_entry(pv, pm, va, -1);
1292 /* kernel and user are cachable */
1293 if ((pm == kernel_pmap) && !(pv->pv_flags & PVF_MWC) &&
1294 (pv->pv_flags & PVF_NC)) {
1296 pv->pv_flags &= ~PVF_NC;
1297 if (pg->md.pv_memattr != VM_MEMATTR_UNCACHEABLE)
1298 pmap_set_cache_entry(pv, pm, va, 1);
1301 /* user is no longer sharable and writable */
1302 if (pm != kernel_pmap &&
1303 (pv->pv_pmap == pm || pv->pv_pmap == kernel_pmap) &&
1304 !pmwc && (pv->pv_flags & PVF_NC)) {
1306 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1307 if (pg->md.pv_memattr != VM_MEMATTR_UNCACHEABLE)
1308 pmap_set_cache_entry(pv, pm, va, 1);
1312 if ((kwritable == 0) && (writable == 0)) {
1313 pg->md.pvh_attrs &= ~PVF_MOD;
1314 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1320 * Modify pte bits for all ptes corresponding to the given physical address.
1321 * We use `maskbits' rather than `clearbits' because we're always passing
1322 * constants and the latter would require an extra inversion at run-time.
1325 pmap_clearbit(struct vm_page *pg, u_int maskbits)
1327 struct l2_bucket *l2b;
1328 struct pv_entry *pv;
1329 pt_entry_t *ptep, npte, opte;
1335 rw_wlock(&pvh_global_lock);
1337 if (maskbits & PVF_WRITE)
1338 maskbits |= PVF_MOD;
1340 * Clear saved attributes (modify, reference)
1342 pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF));
1344 if (TAILQ_EMPTY(&pg->md.pv_list)) {
1345 rw_wunlock(&pvh_global_lock);
1350 * Loop over all current mappings setting/clearing as appropos
1352 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1355 oflags = pv->pv_flags;
1357 if (!(oflags & maskbits)) {
1358 if ((maskbits & PVF_WRITE) && (pv->pv_flags & PVF_NC)) {
1359 if (pg->md.pv_memattr !=
1360 VM_MEMATTR_UNCACHEABLE) {
1362 l2b = pmap_get_l2_bucket(pm, va);
1363 ptep = &l2b->l2b_kva[l2pte_index(va)];
1364 *ptep |= pte_l2_s_cache_mode;
1368 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1372 pv->pv_flags &= ~maskbits;
1376 l2b = pmap_get_l2_bucket(pm, va);
1378 ptep = &l2b->l2b_kva[l2pte_index(va)];
1379 npte = opte = *ptep;
1381 if (maskbits & (PVF_WRITE|PVF_MOD)) {
1382 if ((pv->pv_flags & PVF_NC)) {
1384 * Entry is not cacheable:
1386 * Don't turn caching on again if this is a
1387 * modified emulation. This would be
1388 * inconsistent with the settings created by
1389 * pmap_fix_cache(). Otherwise, it's safe
1390 * to re-enable caching.
1392 * There's no need to call pmap_fix_cache()
1393 * here: all pages are losing their write
1396 if (maskbits & PVF_WRITE) {
1397 if (pg->md.pv_memattr !=
1398 VM_MEMATTR_UNCACHEABLE)
1399 npte |= pte_l2_s_cache_mode;
1400 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1403 if (opte & L2_S_PROT_W) {
1406 * Entry is writable/cacheable: check if pmap
1407 * is current if it is flush it, otherwise it
1408 * won't be in the cache
1410 if (PV_BEEN_EXECD(oflags))
1411 pmap_idcache_wbinv_range(pm, pv->pv_va,
1414 if (PV_BEEN_REFD(oflags))
1415 pmap_dcache_wb_range(pm, pv->pv_va,
1417 (maskbits & PVF_REF) ? TRUE : FALSE,
1421 /* make the pte read only */
1422 npte &= ~L2_S_PROT_W;
1425 if (maskbits & PVF_REF) {
1426 if ((pv->pv_flags & PVF_NC) == 0 &&
1427 (maskbits & (PVF_WRITE|PVF_MOD)) == 0) {
1429 * Check npte here; we may have already
1430 * done the wbinv above, and the validity
1431 * of the PTE is the same for opte and
1434 if (npte & L2_S_PROT_W) {
1435 if (PV_BEEN_EXECD(oflags))
1436 pmap_idcache_wbinv_range(pm,
1437 pv->pv_va, PAGE_SIZE);
1439 if (PV_BEEN_REFD(oflags))
1440 pmap_dcache_wb_range(pm,
1441 pv->pv_va, PAGE_SIZE,
1444 if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) {
1445 /* XXXJRT need idcache_inv_range */
1446 if (PV_BEEN_EXECD(oflags))
1447 pmap_idcache_wbinv_range(pm,
1448 pv->pv_va, PAGE_SIZE);
1450 if (PV_BEEN_REFD(oflags))
1451 pmap_dcache_wb_range(pm,
1452 pv->pv_va, PAGE_SIZE,
1458 * Make the PTE invalid so that we will take a
1459 * page fault the next time the mapping is
1462 npte &= ~L2_TYPE_MASK;
1463 npte |= L2_TYPE_INV;
1470 /* Flush the TLB entry if a current pmap. */
1471 if (PV_BEEN_EXECD(oflags))
1472 pmap_tlb_flushID_SE(pm, pv->pv_va);
1474 if (PV_BEEN_REFD(oflags))
1475 pmap_tlb_flushD_SE(pm, pv->pv_va);
1482 if (maskbits & PVF_WRITE)
1483 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1484 rw_wunlock(&pvh_global_lock);
1489 * main pv_entry manipulation functions:
1490 * pmap_enter_pv: enter a mapping onto a vm_page list
1491 * pmap_remove_pv: remove a mappiing from a vm_page list
1493 * NOTE: pmap_enter_pv expects to lock the pvh itself
1494 * pmap_remove_pv expects the caller to lock the pvh before calling
1498 * pmap_enter_pv: enter a mapping onto a vm_page's PV list
1500 * => caller should hold the proper lock on pvh_global_lock
1501 * => caller should have pmap locked
1502 * => we will (someday) gain the lock on the vm_page's PV list
1503 * => caller should adjust ptp's wire_count before calling
1504 * => caller should not adjust pmap's wire_count
1507 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm,
1508 vm_offset_t va, u_int flags)
1511 rw_assert(&pvh_global_lock, RA_WLOCKED);
1512 PMAP_ASSERT_LOCKED(pm);
1513 if (pg->md.pv_kva != 0) {
1514 pve->pv_pmap = kernel_pmap;
1515 pve->pv_va = pg->md.pv_kva;
1516 pve->pv_flags = PVF_WRITE | PVF_UNMAN;
1517 if (pm != kernel_pmap)
1518 PMAP_LOCK(kernel_pmap);
1519 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list);
1520 TAILQ_INSERT_HEAD(&kernel_pmap->pm_pvlist, pve, pv_plist);
1521 if (pm != kernel_pmap)
1522 PMAP_UNLOCK(kernel_pmap);
1524 if ((pve = pmap_get_pv_entry()) == NULL)
1525 panic("pmap_kenter_pv: no pv entries");
1529 pve->pv_flags = flags;
1530 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list);
1531 TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist);
1532 pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD);
1533 if (pve->pv_flags & PVF_WIRED)
1534 ++pm->pm_stats.wired_count;
1535 vm_page_aflag_set(pg, PGA_REFERENCED);
1540 * pmap_find_pv: Find a pv entry
1542 * => caller should hold lock on vm_page
1544 static PMAP_INLINE struct pv_entry *
1545 pmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1547 struct pv_entry *pv;
1549 rw_assert(&pvh_global_lock, RA_WLOCKED);
1550 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list)
1551 if (pm == pv->pv_pmap && va == pv->pv_va)
1557 * vector_page_setprot:
1559 * Manipulate the protection of the vector page.
1562 vector_page_setprot(int prot)
1564 struct l2_bucket *l2b;
1567 l2b = pmap_get_l2_bucket(kernel_pmap, vector_page);
1569 ptep = &l2b->l2b_kva[l2pte_index(vector_page)];
1571 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot);
1573 cpu_tlb_flushD_SE(vector_page);
1578 * pmap_remove_pv: try to remove a mapping from a pv_list
1580 * => caller should hold proper lock on pmap_main_lock
1581 * => pmap should be locked
1582 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1583 * => caller should adjust ptp's wire_count and free PTP if needed
1584 * => caller should NOT adjust pmap's wire_count
1585 * => we return the removed pve
1589 pmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve)
1592 struct pv_entry *pv;
1593 rw_assert(&pvh_global_lock, RA_WLOCKED);
1594 PMAP_ASSERT_LOCKED(pm);
1595 TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list);
1596 TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist);
1597 if (pve->pv_flags & PVF_WIRED)
1598 --pm->pm_stats.wired_count;
1599 if (pg->md.pvh_attrs & PVF_MOD)
1601 if (TAILQ_FIRST(&pg->md.pv_list) == NULL)
1602 pg->md.pvh_attrs &= ~PVF_REF;
1604 vm_page_aflag_set(pg, PGA_REFERENCED);
1605 if ((pve->pv_flags & PVF_NC) && ((pm == kernel_pmap) ||
1606 (pve->pv_flags & PVF_WRITE) || !(pve->pv_flags & PVF_MWC)))
1607 pmap_fix_cache(pg, pm, 0);
1608 else if (pve->pv_flags & PVF_WRITE) {
1609 TAILQ_FOREACH(pve, &pg->md.pv_list, pv_list)
1610 if (pve->pv_flags & PVF_WRITE)
1613 pg->md.pvh_attrs &= ~PVF_MOD;
1614 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1617 pv = TAILQ_FIRST(&pg->md.pv_list);
1618 if (pv != NULL && (pv->pv_flags & PVF_UNMAN) &&
1619 TAILQ_NEXT(pv, pv_list) == NULL) {
1621 pg->md.pv_kva = pv->pv_va;
1622 /* a recursive pmap_nuke_pv */
1623 TAILQ_REMOVE(&pg->md.pv_list, pv, pv_list);
1624 TAILQ_REMOVE(&pm->pm_pvlist, pv, pv_plist);
1625 if (pv->pv_flags & PVF_WIRED)
1626 --pm->pm_stats.wired_count;
1627 pg->md.pvh_attrs &= ~PVF_REF;
1628 pg->md.pvh_attrs &= ~PVF_MOD;
1629 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1630 pmap_free_pv_entry(pv);
1634 static struct pv_entry *
1635 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1637 struct pv_entry *pve;
1639 rw_assert(&pvh_global_lock, RA_WLOCKED);
1640 pve = TAILQ_FIRST(&pg->md.pv_list);
1643 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */
1644 pmap_nuke_pv(pg, pm, pve);
1647 pve = TAILQ_NEXT(pve, pv_list);
1650 if (pve == NULL && pg->md.pv_kva == va)
1653 return(pve); /* return removed pve */
1657 * pmap_modify_pv: Update pv flags
1659 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1660 * => caller should NOT adjust pmap's wire_count
1661 * => we return the old flags
1663 * Modify a physical-virtual mapping in the pv table
1666 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va,
1667 u_int clr_mask, u_int set_mask)
1669 struct pv_entry *npv;
1670 u_int flags, oflags;
1672 PMAP_ASSERT_LOCKED(pm);
1673 rw_assert(&pvh_global_lock, RA_WLOCKED);
1674 if ((npv = pmap_find_pv(pg, pm, va)) == NULL)
1678 * There is at least one VA mapping this page.
1681 if (clr_mask & (PVF_REF | PVF_MOD))
1682 pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD);
1684 oflags = npv->pv_flags;
1685 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask;
1687 if ((flags ^ oflags) & PVF_WIRED) {
1688 if (flags & PVF_WIRED)
1689 ++pm->pm_stats.wired_count;
1691 --pm->pm_stats.wired_count;
1694 if ((flags ^ oflags) & PVF_WRITE)
1695 pmap_fix_cache(pg, pm, 0);
1700 /* Function to set the debug level of the pmap code */
1703 pmap_debug(int level)
1705 pmap_debug_level = level;
1706 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
1708 #endif /* PMAP_DEBUG */
1711 pmap_pinit0(struct pmap *pmap)
1713 PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap));
1715 bcopy(kernel_pmap, pmap, sizeof(*pmap));
1716 bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx));
1717 PMAP_LOCK_INIT(pmap);
1721 * Initialize a vm_page's machine-dependent fields.
1724 pmap_page_init(vm_page_t m)
1727 TAILQ_INIT(&m->md.pv_list);
1728 m->md.pv_memattr = VM_MEMATTR_DEFAULT;
1729 m->md.pvh_attrs = 0;
1734 * Initialize the pmap module.
1735 * Called by vm_init, to initialize any structures that the pmap
1736 * system needs to map virtual memory.
1741 int shpgperproc = PMAP_SHPGPERPROC;
1743 l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor,
1744 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1745 l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable), NULL,
1746 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1749 * Initialize the PV entry allocator.
1751 pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL,
1752 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1753 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1754 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1755 uma_zone_reserve_kva(pvzone, pv_entry_max);
1756 pv_entry_high_water = 9 * (pv_entry_max / 10);
1759 * Now it is safe to enable pv_table recording.
1761 PDEBUG(1, printf("pmap_init: done!\n"));
1765 pmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user)
1767 struct l2_dtable *l2;
1768 struct l2_bucket *l2b;
1769 pd_entry_t *pl1pd, l1pd;
1770 pt_entry_t *ptep, pte;
1776 rw_wlock(&pvh_global_lock);
1780 * If there is no l2_dtable for this address, then the process
1781 * has no business accessing it.
1783 * Note: This will catch userland processes trying to access
1786 l2 = pm->pm_l2[L2_IDX(l1idx)];
1791 * Likewise if there is no L2 descriptor table
1793 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
1794 if (l2b->l2b_kva == NULL)
1798 * Check the PTE itself.
1800 ptep = &l2b->l2b_kva[l2pte_index(va)];
1806 * Catch a userland access to the vector page mapped at 0x0
1808 if (user && (pte & L2_S_PROT_U) == 0)
1810 if (va == vector_page)
1815 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) {
1817 * This looks like a good candidate for "page modified"
1820 struct pv_entry *pv;
1823 /* Extract the physical address of the page */
1824 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) {
1827 /* Get the current flags for this page. */
1829 pv = pmap_find_pv(pg, pm, va);
1835 * Do the flags say this page is writable? If not then it
1836 * is a genuine write fault. If yes then the write fault is
1837 * our fault as we did not reflect the write access in the
1838 * PTE. Now we know a write has occurred we can correct this
1839 * and also set the modified bit
1841 if ((pv->pv_flags & PVF_WRITE) == 0) {
1845 pg->md.pvh_attrs |= PVF_REF | PVF_MOD;
1847 pv->pv_flags |= PVF_REF | PVF_MOD;
1850 * Re-enable write permissions for the page. No need to call
1851 * pmap_fix_cache(), since this is just a
1852 * modified-emulation fault, and the PVF_WRITE bit isn't
1853 * changing. We've already set the cacheable bits based on
1854 * the assumption that we can write to this page.
1856 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W;
1860 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) {
1862 * This looks like a good candidate for "page referenced"
1865 struct pv_entry *pv;
1868 /* Extract the physical address of the page */
1869 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL)
1871 /* Get the current flags for this page. */
1873 pv = pmap_find_pv(pg, pm, va);
1877 pg->md.pvh_attrs |= PVF_REF;
1878 pv->pv_flags |= PVF_REF;
1881 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO;
1887 * We know there is a valid mapping here, so simply
1888 * fix up the L1 if necessary.
1890 pl1pd = &pm->pm_l1->l1_kva[l1idx];
1891 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO;
1892 if (*pl1pd != l1pd) {
1900 * If 'rv == 0' at this point, it generally indicates that there is a
1901 * stale TLB entry for the faulting address. This happens when two or
1902 * more processes are sharing an L1. Since we don't flush the TLB on
1903 * a context switch between such processes, we can take domain faults
1904 * for mappings which exist at the same VA in both processes. EVEN IF
1905 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for
1908 * This is extremely likely to happen if pmap_enter() updated the L1
1909 * entry for a recently entered mapping. In this case, the TLB is
1910 * flushed for the new mapping, but there may still be TLB entries for
1911 * other mappings belonging to other processes in the 1MB range
1912 * covered by the L1 entry.
1914 * Since 'rv == 0', we know that the L1 already contains the correct
1915 * value, so the fault must be due to a stale TLB entry.
1917 * Since we always need to flush the TLB anyway in the case where we
1918 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with
1919 * stale TLB entries dynamically.
1921 * However, the above condition can ONLY happen if the current L1 is
1922 * being shared. If it happens when the L1 is unshared, it indicates
1923 * that other parts of the pmap are not doing their job WRT managing
1926 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) {
1927 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n",
1928 pm, (u_long)va, ftype);
1929 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n",
1930 l2, l2b, ptep, pl1pd);
1931 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n",
1932 pte, l1pd, last_fault_code);
1939 cpu_tlb_flushID_SE(va);
1945 rw_wunlock(&pvh_global_lock);
1953 struct l2_bucket *l2b;
1954 struct l1_ttable *l1;
1956 pt_entry_t *ptep, pte;
1957 vm_offset_t va, eva;
1960 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0);
1962 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK);
1964 for (loop = 0; loop < needed; loop++, l1++) {
1965 /* Allocate a L1 page table */
1966 va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0,
1967 0xffffffff, L1_TABLE_SIZE, 0);
1970 panic("Cannot allocate L1 KVM");
1972 eva = va + L1_TABLE_SIZE;
1973 pl1pt = (pd_entry_t *)va;
1976 l2b = pmap_get_l2_bucket(kernel_pmap, va);
1977 ptep = &l2b->l2b_kva[l2pte_index(va)];
1979 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
1982 cpu_tlb_flushD_SE(va);
1986 pmap_init_l1(l1, pl1pt);
1991 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n",
1997 * This is used to stuff certain critical values into the PCB where they
1998 * can be accessed quickly from cpu_switch() et al.
2001 pmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb)
2003 struct l2_bucket *l2b;
2005 pcb->pcb_pagedir = pm->pm_l1->l1_physaddr;
2006 pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) |
2007 (DOMAIN_CLIENT << (pm->pm_domain * 2));
2009 if (vector_page < KERNBASE) {
2010 pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)];
2011 l2b = pmap_get_l2_bucket(pm, vector_page);
2012 pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO |
2013 L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL);
2015 pcb->pcb_pl1vec = NULL;
2019 pmap_activate(struct thread *td)
2024 pm = vmspace_pmap(td->td_proc->p_vmspace);
2028 pmap_set_pcb_pagedir(pm, pcb);
2030 if (td == curthread) {
2031 u_int cur_dacr, cur_ttb;
2033 __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb));
2034 __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr));
2036 cur_ttb &= ~(L1_TABLE_SIZE - 1);
2038 if (cur_ttb == (u_int)pcb->pcb_pagedir &&
2039 cur_dacr == pcb->pcb_dacr) {
2041 * No need to switch address spaces.
2049 * We MUST, I repeat, MUST fix up the L1 entry corresponding
2050 * to 'vector_page' in the incoming L1 table before switching
2051 * to it otherwise subsequent interrupts/exceptions (including
2052 * domain faults!) will jump into hyperspace.
2054 if (pcb->pcb_pl1vec) {
2056 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2058 * Don't need to PTE_SYNC() at this point since
2059 * cpu_setttb() is about to flush both the cache
2064 cpu_domains(pcb->pcb_dacr);
2065 cpu_setttb(pcb->pcb_pagedir);
2071 pmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va)
2073 pd_entry_t *pdep, pde;
2074 pt_entry_t *ptep, pte;
2079 * Make sure the descriptor itself has the correct cache mode
2081 pdep = &kl1[L1_IDX(va)];
2084 if (l1pte_section_p(pde)) {
2085 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) {
2086 *pdep = (pde & ~L1_S_CACHE_MASK) |
2087 pte_l1_s_cache_mode_pt;
2089 cpu_dcache_wbinv_range((vm_offset_t)pdep,
2091 cpu_l2cache_wbinv_range((vm_offset_t)pdep,
2096 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2097 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2099 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep);
2101 ptep = &ptep[l2pte_index(va)];
2103 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
2104 *ptep = (pte & ~L2_S_CACHE_MASK) |
2105 pte_l2_s_cache_mode_pt;
2107 cpu_dcache_wbinv_range((vm_offset_t)ptep,
2109 cpu_l2cache_wbinv_range((vm_offset_t)ptep,
2119 pmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap,
2122 vm_offset_t va = *availp;
2123 struct l2_bucket *l2b;
2126 l2b = pmap_get_l2_bucket(kernel_pmap, va);
2128 panic("pmap_alloc_specials: no l2b for 0x%x", va);
2130 *ptep = &l2b->l2b_kva[l2pte_index(va)];
2134 *availp = va + (PAGE_SIZE * pages);
2138 * Bootstrap the system enough to run with virtual memory.
2140 * On the arm this is called after mapping has already been enabled
2141 * and just syncs the pmap module with what has already been done.
2142 * [We can't call it easily with mapping off since the kernel is not
2143 * mapped with PA == VA, hence we would have to relocate every address
2144 * from the linked base (virtual) address "KERNBASE" to the actual
2145 * (physical) address starting relative to 0]
2147 #define PMAP_STATIC_L2_SIZE 16
2149 pmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt)
2151 static struct l1_ttable static_l1;
2152 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE];
2153 struct l1_ttable *l1 = &static_l1;
2154 struct l2_dtable *l2;
2155 struct l2_bucket *l2b;
2157 pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va;
2159 pt_entry_t *qmap_pte;
2163 int l1idx, l2idx, l2next = 0;
2165 PDEBUG(1, printf("firstaddr = %08x, lastaddr = %08x\n",
2166 firstaddr, vm_max_kernel_address));
2168 virtual_avail = firstaddr;
2169 kernel_pmap->pm_l1 = l1;
2170 kernel_l1pa = l1pt->pv_pa;
2173 * Scan the L1 translation table created by initarm() and create
2174 * the required metadata for all valid mappings found in it.
2176 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) {
2177 pde = kernel_l1pt[l1idx];
2180 * We're only interested in Coarse mappings.
2181 * pmap_extract() can deal with section mappings without
2182 * recourse to checking L2 metadata.
2184 if ((pde & L1_TYPE_MASK) != L1_TYPE_C)
2188 * Lookup the KVA of this L2 descriptor table
2190 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2191 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2194 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx",
2195 (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa);
2199 * Fetch the associated L2 metadata structure.
2200 * Allocate a new one if necessary.
2202 if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) {
2203 if (l2next == PMAP_STATIC_L2_SIZE)
2204 panic("pmap_bootstrap: out of static L2s");
2205 kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 =
2206 &static_l2[l2next++];
2210 * One more L1 slot tracked...
2215 * Fill in the details of the L2 descriptor in the
2216 * appropriate bucket.
2218 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2219 l2b->l2b_kva = ptep;
2221 l2b->l2b_l1idx = l1idx;
2224 * Establish an initial occupancy count for this descriptor
2227 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
2229 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) {
2230 l2b->l2b_occupancy++;
2235 * Make sure the descriptor itself has the correct cache mode.
2236 * If not, fix it, but whine about the problem. Port-meisters
2237 * should consider this a clue to fix up their initarm()
2240 if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) {
2241 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2242 "L2 pte @ %p\n", ptep);
2248 * Ensure the primary (kernel) L1 has the correct cache mode for
2249 * a page table. Bitch if it is not correctly set.
2251 for (va = (vm_offset_t)kernel_l1pt;
2252 va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) {
2253 if (pmap_set_pt_cache_mode(kernel_l1pt, va))
2254 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2255 "primary L1 @ 0x%x\n", va);
2258 cpu_dcache_wbinv_all();
2259 cpu_l2cache_wbinv_all();
2263 PMAP_LOCK_INIT(kernel_pmap);
2264 CPU_FILL(&kernel_pmap->pm_active);
2265 kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL;
2266 TAILQ_INIT(&kernel_pmap->pm_pvlist);
2269 * Initialize the global pv list lock.
2271 rw_init_flags(&pvh_global_lock, "pmap pv global", RW_RECURSE);
2274 * Reserve some special page table entries/VA space for temporary
2277 pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte);
2278 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte);
2279 pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte);
2280 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte);
2281 pmap_alloc_specials(&virtual_avail, 1, &qmap_addr, &qmap_pte);
2282 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)qmap_pte);
2283 size = ((vm_max_kernel_address - pmap_curmaxkvaddr) + L1_S_OFFSET) /
2285 pmap_alloc_specials(&virtual_avail,
2286 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE,
2287 &pmap_kernel_l2ptp_kva, NULL);
2289 size = howmany(size, L2_BUCKET_SIZE);
2290 pmap_alloc_specials(&virtual_avail,
2291 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE,
2292 &pmap_kernel_l2dtable_kva, NULL);
2294 pmap_alloc_specials(&virtual_avail,
2295 1, (vm_offset_t*)&_tmppt, NULL);
2296 pmap_alloc_specials(&virtual_avail,
2297 MAXDUMPPGS, (vm_offset_t *)&crashdumpmap, NULL);
2298 SLIST_INIT(&l1_list);
2299 TAILQ_INIT(&l1_lru_list);
2300 mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF);
2301 pmap_init_l1(l1, kernel_l1pt);
2302 cpu_dcache_wbinv_all();
2303 cpu_l2cache_wbinv_all();
2305 virtual_avail = round_page(virtual_avail);
2306 virtual_end = vm_max_kernel_address;
2307 kernel_vm_end = pmap_curmaxkvaddr;
2308 mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF);
2309 mtx_init(&qmap_mtx, "quick mapping mtx", NULL, MTX_DEF);
2311 pmap_set_pcb_pagedir(kernel_pmap, thread0.td_pcb);
2314 /***************************************************
2315 * Pmap allocation/deallocation routines.
2316 ***************************************************/
2319 * Release any resources held by the given physical map.
2320 * Called when a pmap initialized by pmap_pinit is being released.
2321 * Should only be called if the map contains no valid mappings.
2324 pmap_release(pmap_t pmap)
2328 pmap_idcache_wbinv_all(pmap);
2329 cpu_l2cache_wbinv_all();
2330 pmap_tlb_flushID(pmap);
2332 if (vector_page < KERNBASE) {
2333 struct pcb *curpcb = PCPU_GET(curpcb);
2334 pcb = thread0.td_pcb;
2335 if (pmap_is_current(pmap)) {
2337 * Frob the L1 entry corresponding to the vector
2338 * page so that it contains the kernel pmap's domain
2339 * number. This will ensure pmap_remove() does not
2340 * pull the current vector page out from under us.
2343 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2344 cpu_domains(pcb->pcb_dacr);
2345 cpu_setttb(pcb->pcb_pagedir);
2348 pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE);
2350 * Make sure cpu_switch(), et al, DTRT. This is safe to do
2351 * since this process has no remaining mappings of its own.
2353 curpcb->pcb_pl1vec = pcb->pcb_pl1vec;
2354 curpcb->pcb_l1vec = pcb->pcb_l1vec;
2355 curpcb->pcb_dacr = pcb->pcb_dacr;
2356 curpcb->pcb_pagedir = pcb->pcb_pagedir;
2361 dprintf("pmap_release()\n");
2367 * Helper function for pmap_grow_l2_bucket()
2370 pmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap)
2372 struct l2_bucket *l2b;
2377 pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
2380 pa = VM_PAGE_TO_PHYS(pg);
2385 l2b = pmap_get_l2_bucket(kernel_pmap, va);
2387 ptep = &l2b->l2b_kva[l2pte_index(va)];
2388 *ptep = L2_S_PROTO | pa | cache_mode |
2389 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE);
2395 * This is the same as pmap_alloc_l2_bucket(), except that it is only
2396 * used by pmap_growkernel().
2398 static __inline struct l2_bucket *
2399 pmap_grow_l2_bucket(pmap_t pm, vm_offset_t va)
2401 struct l2_dtable *l2;
2402 struct l2_bucket *l2b;
2403 struct l1_ttable *l1;
2410 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
2412 * No mapping at this address, as there is
2413 * no entry in the L1 table.
2414 * Need to allocate a new l2_dtable.
2416 nva = pmap_kernel_l2dtable_kva;
2417 if ((nva & PAGE_MASK) == 0) {
2419 * Need to allocate a backing page
2421 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2425 l2 = (struct l2_dtable *)nva;
2426 nva += sizeof(struct l2_dtable);
2428 if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva &
2431 * The new l2_dtable straddles a page boundary.
2432 * Map in another page to cover it.
2434 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2438 pmap_kernel_l2dtable_kva = nva;
2441 * Link it into the parent pmap
2443 pm->pm_l2[L2_IDX(l1idx)] = l2;
2444 memset(l2, 0, sizeof(*l2));
2447 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2450 * Fetch pointer to the L2 page table associated with the address.
2452 if (l2b->l2b_kva == NULL) {
2456 * No L2 page table has been allocated. Chances are, this
2457 * is because we just allocated the l2_dtable, above.
2459 nva = pmap_kernel_l2ptp_kva;
2460 ptep = (pt_entry_t *)nva;
2461 if ((nva & PAGE_MASK) == 0) {
2463 * Need to allocate a backing page
2465 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt,
2466 &pmap_kernel_l2ptp_phys))
2468 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t));
2470 memset(ptep, 0, L2_TABLE_SIZE_REAL);
2472 l2b->l2b_kva = ptep;
2473 l2b->l2b_l1idx = l1idx;
2474 l2b->l2b_phys = pmap_kernel_l2ptp_phys;
2476 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL;
2477 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL;
2480 /* Distribute new L1 entry to all other L1s */
2481 SLIST_FOREACH(l1, &l1_list, l1_link) {
2482 pl1pd = &l1->l1_kva[L1_IDX(va)];
2483 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) |
2493 * grow the number of kernel page table entries, if needed
2496 pmap_growkernel(vm_offset_t addr)
2498 pmap_t kpm = kernel_pmap;
2500 if (addr <= pmap_curmaxkvaddr)
2501 return; /* we are OK */
2504 * whoops! we need to add kernel PTPs
2507 /* Map 1MB at a time */
2508 for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE)
2509 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr);
2512 * flush out the cache, expensive but growkernel will happen so
2515 cpu_dcache_wbinv_all();
2516 cpu_l2cache_wbinv_all();
2519 kernel_vm_end = pmap_curmaxkvaddr;
2524 * Remove all pages from specified address space
2525 * this aids process exit speeds. Also, this code
2526 * is special cased for current process only, but
2527 * can have the more generic (and slightly slower)
2528 * mode enabled. This is much faster than pmap_remove
2529 * in the case of running down an entire address space.
2532 pmap_remove_pages(pmap_t pmap)
2534 struct pv_entry *pv, *npv;
2535 struct l2_bucket *l2b = NULL;
2539 rw_wlock(&pvh_global_lock);
2541 cpu_idcache_wbinv_all();
2542 cpu_l2cache_wbinv_all();
2543 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) {
2544 if (pv->pv_flags & PVF_WIRED || pv->pv_flags & PVF_UNMAN) {
2545 /* Cannot remove wired or unmanaged pages now. */
2546 npv = TAILQ_NEXT(pv, pv_plist);
2549 pmap->pm_stats.resident_count--;
2550 l2b = pmap_get_l2_bucket(pmap, pv->pv_va);
2551 KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages"));
2552 pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
2553 m = PHYS_TO_VM_PAGE(*pt & L2_S_FRAME);
2554 KASSERT((vm_offset_t)m >= KERNBASE, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt));
2557 npv = TAILQ_NEXT(pv, pv_plist);
2558 pmap_nuke_pv(m, pmap, pv);
2559 if (TAILQ_EMPTY(&m->md.pv_list))
2560 vm_page_aflag_clear(m, PGA_WRITEABLE);
2561 pmap_free_pv_entry(pv);
2562 pmap_free_l2_bucket(pmap, l2b, 1);
2564 rw_wunlock(&pvh_global_lock);
2571 /***************************************************
2572 * Low level mapping routines.....
2573 ***************************************************/
2575 #ifdef ARM_HAVE_SUPERSECTIONS
2576 /* Map a super section into the KVA. */
2579 pmap_kenter_supersection(vm_offset_t va, uint64_t pa, int flags)
2581 pd_entry_t pd = L1_S_PROTO | L1_S_SUPERSEC | (pa & L1_SUP_FRAME) |
2582 (((pa >> 32) & 0xf) << 20) | L1_S_PROT(PTE_KERNEL,
2583 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
2584 struct l1_ttable *l1;
2585 vm_offset_t va0, va_end;
2587 KASSERT(((va | pa) & L1_SUP_OFFSET) == 0,
2588 ("Not a valid super section mapping"));
2589 if (flags & SECTION_CACHE)
2590 pd |= pte_l1_s_cache_mode;
2591 else if (flags & SECTION_PT)
2592 pd |= pte_l1_s_cache_mode_pt;
2593 va0 = va & L1_SUP_FRAME;
2594 va_end = va + L1_SUP_SIZE;
2595 SLIST_FOREACH(l1, &l1_list, l1_link) {
2597 for (; va < va_end; va += L1_S_SIZE) {
2598 l1->l1_kva[L1_IDX(va)] = pd;
2599 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2605 /* Map a section into the KVA. */
2608 pmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags)
2610 pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL,
2611 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
2612 struct l1_ttable *l1;
2614 KASSERT(((va | pa) & L1_S_OFFSET) == 0,
2615 ("Not a valid section mapping"));
2616 if (flags & SECTION_CACHE)
2617 pd |= pte_l1_s_cache_mode;
2618 else if (flags & SECTION_PT)
2619 pd |= pte_l1_s_cache_mode_pt;
2620 SLIST_FOREACH(l1, &l1_list, l1_link) {
2621 l1->l1_kva[L1_IDX(va)] = pd;
2622 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2627 * Make a temporary mapping for a physical address. This is only intended
2628 * to be used for panic dumps.
2631 pmap_kenter_temporary(vm_paddr_t pa, int i)
2635 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
2636 pmap_kenter(va, pa);
2637 return ((void *)crashdumpmap);
2641 * add a wired page to the kva
2642 * note that in order for the mapping to take effect -- you
2643 * should do a invltlb after doing the pmap_kenter...
2645 static PMAP_INLINE void
2646 pmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags)
2648 struct l2_bucket *l2b;
2651 struct pv_entry *pve;
2654 PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n",
2655 (uint32_t) va, (uint32_t) pa));
2658 l2b = pmap_get_l2_bucket(kernel_pmap, va);
2660 l2b = pmap_grow_l2_bucket(kernel_pmap, va);
2661 KASSERT(l2b != NULL, ("No L2 Bucket"));
2662 pte = &l2b->l2b_kva[l2pte_index(va)];
2664 PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n",
2665 (uint32_t) pte, opte, *pte));
2666 if (l2pte_valid(opte)) {
2670 l2b->l2b_occupancy++;
2672 *pte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL,
2673 VM_PROT_READ | VM_PROT_WRITE);
2674 if (flags & KENTER_CACHE)
2675 *pte |= pte_l2_s_cache_mode;
2676 if (flags & KENTER_USER)
2677 *pte |= L2_S_PROT_U;
2681 * A kernel mapping may not be the page's only mapping, so create a PV
2682 * entry to ensure proper caching.
2684 * The existence test for the pvzone is used to delay the recording of
2685 * kernel mappings until the VM system is fully initialized.
2687 * This expects the physical memory to have a vm_page_array entry.
2689 if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa)) != NULL) {
2690 rw_wlock(&pvh_global_lock);
2691 if (!TAILQ_EMPTY(&m->md.pv_list) || m->md.pv_kva != 0) {
2692 if ((pve = pmap_get_pv_entry()) == NULL)
2693 panic("pmap_kenter_internal: no pv entries");
2694 PMAP_LOCK(kernel_pmap);
2695 pmap_enter_pv(m, pve, kernel_pmap, va,
2696 PVF_WRITE | PVF_UNMAN);
2697 pmap_fix_cache(m, kernel_pmap, va);
2698 PMAP_UNLOCK(kernel_pmap);
2702 rw_wunlock(&pvh_global_lock);
2707 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2709 pmap_kenter_internal(va, pa, KENTER_CACHE);
2713 pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa)
2716 pmap_kenter_internal(va, pa, 0);
2720 pmap_kenter_device(vm_offset_t va, vm_size_t size, vm_paddr_t pa)
2724 KASSERT((size & PAGE_MASK) == 0,
2725 ("%s: device mapping not page-sized", __func__));
2729 pmap_kenter_internal(va, pa, 0);
2737 pmap_kremove_device(vm_offset_t va, vm_size_t size)
2741 KASSERT((size & PAGE_MASK) == 0,
2742 ("%s: device mapping not page-sized", __func__));
2753 pmap_kenter_user(vm_offset_t va, vm_paddr_t pa)
2756 pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER);
2758 * Call pmap_fault_fixup now, to make sure we'll have no exception
2759 * at the first use of the new address, or bad things will happen,
2760 * as we use one of these addresses in the exception handlers.
2762 pmap_fault_fixup(kernel_pmap, va, VM_PROT_READ|VM_PROT_WRITE, 1);
2766 pmap_kextract(vm_offset_t va)
2769 return (pmap_extract_locked(kernel_pmap, va));
2773 * remove a page from the kernel pagetables
2776 pmap_kremove(vm_offset_t va)
2778 struct l2_bucket *l2b;
2779 pt_entry_t *pte, opte;
2780 struct pv_entry *pve;
2784 l2b = pmap_get_l2_bucket(kernel_pmap, va);
2787 KASSERT(l2b != NULL, ("No L2 Bucket"));
2788 pte = &l2b->l2b_kva[l2pte_index(va)];
2790 if (l2pte_valid(opte)) {
2791 /* pa = vtophs(va) taken from pmap_extract() */
2792 if ((opte & L2_TYPE_MASK) == L2_TYPE_L)
2793 pa = (opte & L2_L_FRAME) | (va & L2_L_OFFSET);
2795 pa = (opte & L2_S_FRAME) | (va & L2_S_OFFSET);
2796 /* note: should never have to remove an allocation
2797 * before the pvzone is initialized.
2799 rw_wlock(&pvh_global_lock);
2800 PMAP_LOCK(kernel_pmap);
2801 if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa)) &&
2802 (pve = pmap_remove_pv(m, kernel_pmap, va)))
2803 pmap_free_pv_entry(pve);
2804 PMAP_UNLOCK(kernel_pmap);
2805 rw_wunlock(&pvh_global_lock);
2806 va = va & ~PAGE_MASK;
2807 cpu_dcache_wbinv_range(va, PAGE_SIZE);
2808 cpu_l2cache_wbinv_range(va, PAGE_SIZE);
2809 cpu_tlb_flushD_SE(va);
2817 * Used to map a range of physical addresses into kernel
2818 * virtual address space.
2820 * The value passed in '*virt' is a suggested virtual address for
2821 * the mapping. Architectures which can support a direct-mapped
2822 * physical to virtual region can return the appropriate address
2823 * within that region, leaving '*virt' unchanged. Other
2824 * architectures should map the pages starting at '*virt' and
2825 * update '*virt' with the first usable address after the mapped
2829 pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot)
2831 vm_offset_t sva = *virt;
2832 vm_offset_t va = sva;
2834 PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, "
2835 "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end,
2838 while (start < end) {
2839 pmap_kenter(va, start);
2848 pmap_wb_page(vm_page_t m)
2850 struct pv_entry *pv;
2852 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
2853 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, FALSE,
2854 (pv->pv_flags & PVF_WRITE) == 0);
2858 pmap_inv_page(vm_page_t m)
2860 struct pv_entry *pv;
2862 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
2863 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, TRUE, TRUE);
2866 * Add a list of wired pages to the kva
2867 * this routine is only used for temporary
2868 * kernel mappings that do not need to have
2869 * page modification or references recorded.
2870 * Note that old mappings are simply written
2871 * over. The page *must* be wired.
2874 pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
2878 for (i = 0; i < count; i++) {
2880 pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]),
2888 * this routine jerks page mappings from the
2889 * kernel -- it is meant only for temporary mappings.
2892 pmap_qremove(vm_offset_t va, int count)
2897 for (i = 0; i < count; i++) {
2900 pmap_inv_page(PHYS_TO_VM_PAGE(pa));
2909 * pmap_object_init_pt preloads the ptes for a given object
2910 * into the specified pmap. This eliminates the blast of soft
2911 * faults on process startup and immediately after an mmap.
2914 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
2915 vm_pindex_t pindex, vm_size_t size)
2918 VM_OBJECT_ASSERT_WLOCKED(object);
2919 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2920 ("pmap_object_init_pt: non-device object"));
2925 * pmap_is_prefaultable:
2927 * Return whether or not the specified virtual address is elgible
2931 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
2936 if (!pmap_get_pde_pte(pmap, addr, &pde, &pte))
2938 KASSERT(pte != NULL, ("Valid mapping but no pte ?"));
2945 * Fetch pointers to the PDE/PTE for the given pmap/VA pair.
2946 * Returns TRUE if the mapping exists, else FALSE.
2948 * NOTE: This function is only used by a couple of arm-specific modules.
2949 * It is not safe to take any pmap locks here, since we could be right
2950 * in the middle of debugging the pmap anyway...
2952 * It is possible for this routine to return FALSE even though a valid
2953 * mapping does exist. This is because we don't lock, so the metadata
2954 * state may be inconsistent.
2956 * NOTE: We can return a NULL *ptp in the case where the L1 pde is
2957 * a "section" mapping.
2960 pmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp)
2962 struct l2_dtable *l2;
2963 pd_entry_t *pl1pd, l1pd;
2967 if (pm->pm_l1 == NULL)
2971 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx];
2974 if (l1pte_section_p(l1pd)) {
2979 if (pm->pm_l2 == NULL)
2982 l2 = pm->pm_l2[L2_IDX(l1idx)];
2985 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
2989 *ptp = &ptep[l2pte_index(va)];
2994 * Routine: pmap_remove_all
2996 * Removes this physical page from
2997 * all physical maps in which it resides.
2998 * Reflects back modify bits to the pager.
3001 * Original versions of this routine were very
3002 * inefficient because they iteratively called
3003 * pmap_remove (slow...)
3006 pmap_remove_all(vm_page_t m)
3010 struct l2_bucket *l2b;
3011 boolean_t flush = FALSE;
3015 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3016 ("pmap_remove_all: page %p is not managed", m));
3017 if (TAILQ_EMPTY(&m->md.pv_list))
3019 rw_wlock(&pvh_global_lock);
3022 * XXX This call shouldn't exist. Iterating over the PV list twice,
3023 * once in pmap_clearbit() and again below, is both unnecessary and
3024 * inefficient. The below code should itself write back the cache
3025 * entry before it destroys the mapping.
3027 pmap_clearbit(m, PVF_WRITE);
3028 curpm = vmspace_pmap(curproc->p_vmspace);
3029 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3030 if (flush == FALSE && (pv->pv_pmap == curpm ||
3031 pv->pv_pmap == kernel_pmap))
3034 PMAP_LOCK(pv->pv_pmap);
3036 * Cached contents were written-back in pmap_clearbit(),
3037 * but we still have to invalidate the cache entry to make
3038 * sure stale data are not retrieved when another page will be
3039 * mapped under this virtual address.
3041 if (pmap_is_current(pv->pv_pmap)) {
3042 cpu_dcache_inv_range(pv->pv_va, PAGE_SIZE);
3043 if (pmap_has_valid_mapping(pv->pv_pmap, pv->pv_va))
3044 cpu_l2cache_inv_range(pv->pv_va, PAGE_SIZE);
3047 if (pv->pv_flags & PVF_UNMAN) {
3048 /* remove the pv entry, but do not remove the mapping
3049 * and remember this is a kernel mapped page
3051 m->md.pv_kva = pv->pv_va;
3053 /* remove the mapping and pv entry */
3054 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
3055 KASSERT(l2b != NULL, ("No l2 bucket"));
3056 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
3058 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
3059 pmap_free_l2_bucket(pv->pv_pmap, l2b, 1);
3060 pv->pv_pmap->pm_stats.resident_count--;
3061 flags |= pv->pv_flags;
3063 pmap_nuke_pv(m, pv->pv_pmap, pv);
3064 PMAP_UNLOCK(pv->pv_pmap);
3065 pmap_free_pv_entry(pv);
3069 if (PV_BEEN_EXECD(flags))
3070 pmap_tlb_flushID(curpm);
3072 pmap_tlb_flushD(curpm);
3074 vm_page_aflag_clear(m, PGA_WRITEABLE);
3075 rw_wunlock(&pvh_global_lock);
3080 * Set the physical protection on the
3081 * specified range of this map as requested.
3084 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3086 struct l2_bucket *l2b;
3087 pt_entry_t *ptep, pte;
3088 vm_offset_t next_bucket;
3092 CTR4(KTR_PMAP, "pmap_protect: pmap %p sva 0x%08x eva 0x%08x prot %x",
3093 pm, sva, eva, prot);
3095 if ((prot & VM_PROT_READ) == 0) {
3096 pmap_remove(pm, sva, eva);
3100 if (prot & VM_PROT_WRITE) {
3102 * If this is a read->write transition, just ignore it and let
3103 * vm_fault() take care of it later.
3108 rw_wlock(&pvh_global_lock);
3112 * OK, at this point, we know we're doing write-protect operation.
3113 * If the pmap is active, write-back the range.
3115 pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE);
3117 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1;
3121 next_bucket = L2_NEXT_BUCKET(sva);
3122 if (next_bucket > eva)
3125 l2b = pmap_get_l2_bucket(pm, sva);
3131 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3133 while (sva < next_bucket) {
3134 if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) {
3138 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
3139 pte &= ~L2_S_PROT_W;
3143 if (!(pg->oflags & VPO_UNMANAGED)) {
3144 f = pmap_modify_pv(pg, pm, sva,
3155 if (PV_BEEN_EXECD(f))
3156 pmap_tlb_flushID_SE(pm, sva);
3158 if (PV_BEEN_REFD(f))
3159 pmap_tlb_flushD_SE(pm, sva);
3169 if (PV_BEEN_EXECD(flags))
3170 pmap_tlb_flushID(pm);
3172 if (PV_BEEN_REFD(flags))
3173 pmap_tlb_flushD(pm);
3175 rw_wunlock(&pvh_global_lock);
3182 * Insert the given physical page (p) at
3183 * the specified virtual address (v) in the
3184 * target physical map with the protection requested.
3186 * If specified, the page will be wired down, meaning
3187 * that the related pte can not be reclaimed.
3189 * NB: This is the only routine which MAY NOT lazy-evaluate
3190 * or lose information. That is, this routine must actually
3191 * insert this page into the given map NOW.
3195 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3196 u_int flags, int8_t psind __unused)
3200 rw_wlock(&pvh_global_lock);
3202 rv = pmap_enter_locked(pmap, va, m, prot, flags);
3203 rw_wunlock(&pvh_global_lock);
3209 * The pvh global and pmap locks must be held.
3212 pmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3215 struct l2_bucket *l2b = NULL;
3216 struct vm_page *opg;
3217 struct pv_entry *pve = NULL;
3218 pt_entry_t *ptep, npte, opte;
3223 PMAP_ASSERT_LOCKED(pmap);
3224 rw_assert(&pvh_global_lock, RA_WLOCKED);
3225 if (va == vector_page) {
3226 pa = systempage.pv_pa;
3229 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3230 VM_OBJECT_ASSERT_LOCKED(m->object);
3231 pa = VM_PAGE_TO_PHYS(m);
3234 if (prot & VM_PROT_WRITE)
3235 nflags |= PVF_WRITE;
3236 if (prot & VM_PROT_EXECUTE)
3238 if ((flags & PMAP_ENTER_WIRED) != 0)
3239 nflags |= PVF_WIRED;
3240 PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, "
3241 "flags = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, flags));
3243 if (pmap == kernel_pmap) {
3244 l2b = pmap_get_l2_bucket(pmap, va);
3246 l2b = pmap_grow_l2_bucket(pmap, va);
3249 l2b = pmap_alloc_l2_bucket(pmap, va);
3251 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
3253 rw_wunlock(&pvh_global_lock);
3255 rw_wlock(&pvh_global_lock);
3259 return (KERN_RESOURCE_SHORTAGE);
3263 ptep = &l2b->l2b_kva[l2pte_index(va)];
3270 * There is already a mapping at this address.
3271 * If the physical address is different, lookup the
3274 if (l2pte_pa(opte) != pa)
3275 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte));
3281 if ((prot & (VM_PROT_ALL)) ||
3282 (!m || m->md.pvh_attrs & PVF_REF)) {
3284 * - The access type indicates that we don't need
3285 * to do referenced emulation.
3287 * - The physical page has already been referenced
3288 * so no need to re-do referenced emulation here.
3294 if (m && ((prot & VM_PROT_WRITE) != 0 ||
3295 (m->md.pvh_attrs & PVF_MOD))) {
3297 * This is a writable mapping, and the
3298 * page's mod state indicates it has
3299 * already been modified. Make it
3300 * writable from the outset.
3303 if (!(m->md.pvh_attrs & PVF_MOD))
3307 vm_page_aflag_set(m, PGA_REFERENCED);
3310 * Need to do page referenced emulation.
3312 npte |= L2_TYPE_INV;
3315 if (prot & VM_PROT_WRITE) {
3316 npte |= L2_S_PROT_W;
3318 (m->oflags & VPO_UNMANAGED) == 0)
3319 vm_page_aflag_set(m, PGA_WRITEABLE);
3321 if (m->md.pv_memattr != VM_MEMATTR_UNCACHEABLE)
3322 npte |= pte_l2_s_cache_mode;
3323 if (m && m == opg) {
3325 * We're changing the attrs of an existing mapping.
3327 oflags = pmap_modify_pv(m, pmap, va,
3328 PVF_WRITE | PVF_EXEC | PVF_WIRED |
3329 PVF_MOD | PVF_REF, nflags);
3332 * We may need to flush the cache if we're
3335 if (pmap_is_current(pmap) &&
3336 (oflags & PVF_NC) == 0 &&
3337 (opte & L2_S_PROT_W) != 0 &&
3338 (prot & VM_PROT_WRITE) == 0 &&
3339 (opte & L2_TYPE_MASK) != L2_TYPE_INV) {
3340 cpu_dcache_wb_range(va, PAGE_SIZE);
3341 cpu_l2cache_wb_range(va, PAGE_SIZE);
3345 * New mapping, or changing the backing page
3346 * of an existing mapping.
3350 * Replacing an existing mapping with a new one.
3351 * It is part of our managed memory so we
3352 * must remove it from the PV list
3354 if ((pve = pmap_remove_pv(opg, pmap, va))) {
3356 /* note for patch: the oflags/invalidation was moved
3357 * because PG_FICTITIOUS pages could free the pve
3359 oflags = pve->pv_flags;
3361 * If the old mapping was valid (ref/mod
3362 * emulation creates 'invalid' mappings
3363 * initially) then make sure to frob
3366 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) {
3367 if (PV_BEEN_EXECD(oflags)) {
3368 pmap_idcache_wbinv_range(pmap, va,
3371 if (PV_BEEN_REFD(oflags)) {
3372 pmap_dcache_wb_range(pmap, va,
3374 (oflags & PVF_WRITE) == 0);
3378 /* free/allocate a pv_entry for UNMANAGED pages if
3379 * this physical page is not/is already mapped.
3382 if (m && (m->oflags & VPO_UNMANAGED) &&
3384 TAILQ_EMPTY(&m->md.pv_list)) {
3385 pmap_free_pv_entry(pve);
3389 (!(m->oflags & VPO_UNMANAGED) || m->md.pv_kva ||
3390 !TAILQ_EMPTY(&m->md.pv_list)))
3391 pve = pmap_get_pv_entry();
3393 (!(m->oflags & VPO_UNMANAGED) || m->md.pv_kva ||
3394 !TAILQ_EMPTY(&m->md.pv_list)))
3395 pve = pmap_get_pv_entry();
3398 if ((m->oflags & VPO_UNMANAGED)) {
3399 if (!TAILQ_EMPTY(&m->md.pv_list) ||
3401 KASSERT(pve != NULL, ("No pv"));
3402 nflags |= PVF_UNMAN;
3403 pmap_enter_pv(m, pve, pmap, va, nflags);
3407 KASSERT(va < kmi.clean_sva ||
3408 va >= kmi.clean_eva,
3409 ("pmap_enter: managed mapping within the clean submap"));
3410 KASSERT(pve != NULL, ("No pv"));
3411 pmap_enter_pv(m, pve, pmap, va, nflags);
3416 * Make sure userland mappings get the right permissions
3418 if (pmap != kernel_pmap && va != vector_page) {
3419 npte |= L2_S_PROT_U;
3423 * Keep the stats up to date
3426 l2b->l2b_occupancy++;
3427 pmap->pm_stats.resident_count++;
3431 * If this is just a wiring change, the two PTEs will be
3432 * identical, so there's no need to update the page table.
3435 boolean_t is_cached = pmap_is_current(pmap);
3440 * We only need to frob the cache/tlb if this pmap
3444 if (L1_IDX(va) != L1_IDX(vector_page) &&
3445 l2pte_valid(npte)) {
3447 * This mapping is likely to be accessed as
3448 * soon as we return to userland. Fix up the
3449 * L1 entry to avoid taking another
3450 * page/domain fault.
3452 pd_entry_t *pl1pd, l1pd;
3454 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
3455 l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) |
3457 if (*pl1pd != l1pd) {
3464 if (PV_BEEN_EXECD(oflags))
3465 pmap_tlb_flushID_SE(pmap, va);
3466 else if (PV_BEEN_REFD(oflags))
3467 pmap_tlb_flushD_SE(pmap, va);
3471 pmap_fix_cache(m, pmap, va);
3473 return (KERN_SUCCESS);
3477 * Maps a sequence of resident pages belonging to the same object.
3478 * The sequence begins with the given page m_start. This page is
3479 * mapped at the given virtual address start. Each subsequent page is
3480 * mapped at a virtual address that is offset from start by the same
3481 * amount as the page is offset from m_start within the object. The
3482 * last page in the sequence is the page with the largest offset from
3483 * m_start that can be mapped at a virtual address less than the given
3484 * virtual address end. Not every virtual page between start and end
3485 * is mapped; only those for which a resident page exists with the
3486 * corresponding offset from m_start are mapped.
3489 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3490 vm_page_t m_start, vm_prot_t prot)
3493 vm_pindex_t diff, psize;
3495 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3497 psize = atop(end - start);
3499 rw_wlock(&pvh_global_lock);
3501 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3502 pmap_enter_locked(pmap, start + ptoa(diff), m, prot &
3503 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP);
3504 m = TAILQ_NEXT(m, listq);
3506 rw_wunlock(&pvh_global_lock);
3511 * this code makes some *MAJOR* assumptions:
3512 * 1. Current pmap & pmap exists.
3515 * 4. No page table pages.
3516 * but is *MUCH* faster than pmap_enter...
3520 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3523 rw_wlock(&pvh_global_lock);
3525 pmap_enter_locked(pmap, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
3526 PMAP_ENTER_NOSLEEP);
3527 rw_wunlock(&pvh_global_lock);
3532 * Clear the wired attribute from the mappings for the specified range of
3533 * addresses in the given pmap. Every valid mapping within that range
3534 * must have the wired attribute set. In contrast, invalid mappings
3535 * cannot have the wired attribute set, so they are ignored.
3537 * XXX Wired mappings of unmanaged pages cannot be counted by this pmap
3541 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3543 struct l2_bucket *l2b;
3544 pt_entry_t *ptep, pte;
3546 vm_offset_t next_bucket;
3549 rw_wlock(&pvh_global_lock);
3552 next_bucket = L2_NEXT_BUCKET(sva);
3553 if (next_bucket > eva)
3555 l2b = pmap_get_l2_bucket(pmap, sva);
3560 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; sva < next_bucket;
3561 sva += PAGE_SIZE, ptep++) {
3562 if ((pte = *ptep) == 0 ||
3563 (m = PHYS_TO_VM_PAGE(l2pte_pa(pte))) == NULL ||
3564 (m->oflags & VPO_UNMANAGED) != 0)
3566 pv = pmap_find_pv(m, pmap, sva);
3567 if ((pv->pv_flags & PVF_WIRED) == 0)
3568 panic("pmap_unwire: pv %p isn't wired", pv);
3569 pv->pv_flags &= ~PVF_WIRED;
3570 pmap->pm_stats.wired_count--;
3573 rw_wunlock(&pvh_global_lock);
3579 * Copy the range specified by src_addr/len
3580 * from the source map to the range dst_addr/len
3581 * in the destination map.
3583 * This routine is only advisory and need not do anything.
3586 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
3587 vm_size_t len, vm_offset_t src_addr)
3593 * Routine: pmap_extract
3595 * Extract the physical page address associated
3596 * with the given map/virtual_address pair.
3599 pmap_extract(pmap_t pmap, vm_offset_t va)
3604 pa = pmap_extract_locked(pmap, va);
3610 pmap_extract_locked(pmap_t pmap, vm_offset_t va)
3612 struct l2_dtable *l2;
3614 pt_entry_t *ptep, pte;
3618 if (pmap != kernel_pmap)
3619 PMAP_ASSERT_LOCKED(pmap);
3621 l1pd = pmap->pm_l1->l1_kva[l1idx];
3622 if (l1pte_section_p(l1pd)) {
3624 * These should only happen for the kernel pmap.
3626 KASSERT(pmap == kernel_pmap, ("unexpected section"));
3627 /* XXX: what to do about the bits > 32 ? */
3628 if (l1pd & L1_S_SUPERSEC)
3629 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3631 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3634 * Note that we can't rely on the validity of the L1
3635 * descriptor as an indication that a mapping exists.
3636 * We have to look it up in the L2 dtable.
3638 l2 = pmap->pm_l2[L2_IDX(l1idx)];
3640 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL)
3642 pte = ptep[l2pte_index(va)];
3645 if ((pte & L2_TYPE_MASK) == L2_TYPE_L)
3646 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3648 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3654 * Atomically extract and hold the physical page with the given
3655 * pmap and virtual address pair if that mapping permits the given
3660 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3662 struct l2_dtable *l2;
3664 pt_entry_t *ptep, pte;
3665 vm_paddr_t pa, paddr;
3673 l1pd = pmap->pm_l1->l1_kva[l1idx];
3674 if (l1pte_section_p(l1pd)) {
3676 * These should only happen for kernel_pmap
3678 KASSERT(pmap == kernel_pmap, ("huh"));
3679 /* XXX: what to do about the bits > 32 ? */
3680 if (l1pd & L1_S_SUPERSEC)
3681 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3683 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3684 if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr))
3686 if (l1pd & L1_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3687 m = PHYS_TO_VM_PAGE(pa);
3693 * Note that we can't rely on the validity of the L1
3694 * descriptor as an indication that a mapping exists.
3695 * We have to look it up in the L2 dtable.
3697 l2 = pmap->pm_l2[L2_IDX(l1idx)];
3700 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3705 ptep = &ptep[l2pte_index(va)];
3712 if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3713 if ((pte & L2_TYPE_MASK) == L2_TYPE_L)
3714 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3716 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3717 if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr))
3719 m = PHYS_TO_VM_PAGE(pa);
3725 PA_UNLOCK_COND(paddr);
3730 pmap_dump_kextract(vm_offset_t va, pt2_entry_t *pte2p)
3732 struct l2_dtable *l2;
3734 pt_entry_t *ptep, pte;
3739 l1pd = kernel_pmap->pm_l1->l1_kva[l1idx];
3740 if (l1pte_section_p(l1pd)) {
3741 if (l1pd & L1_S_SUPERSEC)
3742 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3744 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3745 pte = L2_S_PROTO | pa |
3746 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE);
3748 l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)];
3750 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3755 pte = ptep[l2pte_index(va)];
3760 if ((pte & L2_TYPE_MASK) == L2_TYPE_L)
3761 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3763 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3772 * Initialize a preallocated and zeroed pmap structure,
3773 * such as one in a vmspace structure.
3777 pmap_pinit(pmap_t pmap)
3779 PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap));
3781 pmap_alloc_l1(pmap);
3782 bzero(pmap->pm_l2, sizeof(pmap->pm_l2));
3784 CPU_ZERO(&pmap->pm_active);
3786 TAILQ_INIT(&pmap->pm_pvlist);
3787 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3788 pmap->pm_stats.resident_count = 1;
3789 if (vector_page < KERNBASE) {
3790 pmap_enter(pmap, vector_page, PHYS_TO_VM_PAGE(systempage.pv_pa),
3791 VM_PROT_READ, PMAP_ENTER_WIRED | VM_PROT_READ, 0);
3797 /***************************************************
3798 * page management routines.
3799 ***************************************************/
3803 pmap_free_pv_entry(pv_entry_t pv)
3806 uma_zfree(pvzone, pv);
3811 * get a new pv_entry, allocating a block from the system
3813 * the memory allocation is performed bypassing the malloc code
3814 * because of the possibility of allocations at interrupt time.
3817 pmap_get_pv_entry(void)
3819 pv_entry_t ret_value;
3822 if (pv_entry_count > pv_entry_high_water)
3823 pagedaemon_wakeup(0); /* XXX ARM NUMA */
3824 ret_value = uma_zalloc(pvzone, M_NOWAIT);
3829 * Remove the given range of addresses from the specified map.
3831 * It is assumed that the start and end are properly
3832 * rounded to the page size.
3834 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3
3836 pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva)
3838 struct l2_bucket *l2b;
3839 vm_offset_t next_bucket;
3842 u_int mappings, is_exec, is_refd;
3847 * we lock in the pmap => pv_head direction
3850 rw_wlock(&pvh_global_lock);
3855 * Do one L2 bucket's worth at a time.
3857 next_bucket = L2_NEXT_BUCKET(sva);
3858 if (next_bucket > eva)
3861 l2b = pmap_get_l2_bucket(pm, sva);
3867 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3870 while (sva < next_bucket) {
3879 * Nothing here, move along
3886 pm->pm_stats.resident_count--;
3892 * Update flags. In a number of circumstances,
3893 * we could cluster a lot of these and do a
3894 * number of sequential pages in one go.
3896 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) {
3897 struct pv_entry *pve;
3899 pve = pmap_remove_pv(pg, pm, sva);
3901 is_exec = PV_BEEN_EXECD(pve->pv_flags);
3902 is_refd = PV_BEEN_REFD(pve->pv_flags);
3903 pmap_free_pv_entry(pve);
3907 if (l2pte_valid(pte) && pmap_is_current(pm)) {
3908 if (total < PMAP_REMOVE_CLEAN_LIST_SIZE) {
3911 cpu_idcache_wbinv_range(sva,
3913 cpu_l2cache_wbinv_range(sva,
3915 cpu_tlb_flushID_SE(sva);
3916 } else if (is_refd) {
3917 cpu_dcache_wbinv_range(sva,
3919 cpu_l2cache_wbinv_range(sva,
3921 cpu_tlb_flushD_SE(sva);
3923 } else if (total == PMAP_REMOVE_CLEAN_LIST_SIZE) {
3924 /* flushall will also only get set for
3925 * for a current pmap
3927 cpu_idcache_wbinv_all();
3928 cpu_l2cache_wbinv_all();
3941 pmap_free_l2_bucket(pm, l2b, mappings);
3944 rw_wunlock(&pvh_global_lock);
3953 * Zero a given physical page by mapping it at a page hook point.
3954 * In doing the zero page op, the page we zero is mapped cachable, as with
3955 * StrongARM accesses to non-cached pages are non-burst making writing
3956 * _any_ bulk data very slow.
3958 #if ARM_MMU_GENERIC != 0 || defined(CPU_XSCALE_CORE3)
3960 pmap_zero_page_generic(vm_paddr_t phys, int off, int size)
3963 if (_arm_bzero && size >= _min_bzero_size &&
3964 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0)
3969 * Hook in the page, zero it, invalidate the TLB as needed.
3971 * Note the temporary zero-page mapping must be a non-cached page in
3972 * order to work without corruption when write-allocate is enabled.
3974 *cdst_pte = L2_S_PROTO | phys | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE);
3976 cpu_tlb_flushD_SE(cdstp);
3978 if (off || size != PAGE_SIZE)
3979 bzero((void *)(cdstp + off), size);
3985 #endif /* ARM_MMU_GENERIC != 0 */
3987 #if ARM_MMU_XSCALE == 1
3989 pmap_zero_page_xscale(vm_paddr_t phys, int off, int size)
3992 if (_arm_bzero && size >= _min_bzero_size &&
3993 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0)
3998 * Hook in the page, zero it, and purge the cache for that
3999 * zeroed page. Invalidate the TLB as needed.
4001 *cdst_pte = L2_S_PROTO | phys |
4002 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4003 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4005 cpu_tlb_flushD_SE(cdstp);
4007 if (off || size != PAGE_SIZE)
4008 bzero((void *)(cdstp + off), size);
4012 xscale_cache_clean_minidata();
4016 * Change the PTEs for the specified kernel mappings such that they
4017 * will use the mini data cache instead of the main data cache.
4020 pmap_use_minicache(vm_offset_t va, vm_size_t size)
4022 struct l2_bucket *l2b;
4023 pt_entry_t *ptep, *sptep, pte;
4024 vm_offset_t next_bucket, eva;
4026 #if (ARM_NMMUS > 1) || defined(CPU_XSCALE_CORE3)
4027 if (xscale_use_minidata == 0)
4034 next_bucket = L2_NEXT_BUCKET(va);
4035 if (next_bucket > eva)
4038 l2b = pmap_get_l2_bucket(kernel_pmap, va);
4040 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)];
4042 while (va < next_bucket) {
4044 if (!l2pte_minidata(pte)) {
4045 cpu_dcache_wbinv_range(va, PAGE_SIZE);
4046 cpu_tlb_flushD_SE(va);
4047 *ptep = pte & ~L2_B;
4052 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep));
4056 #endif /* ARM_MMU_XSCALE == 1 */
4059 * pmap_zero_page zeros the specified hardware page by mapping
4060 * the page into KVM and using bzero to clear its contents.
4063 pmap_zero_page(vm_page_t m)
4065 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), 0, PAGE_SIZE);
4070 * pmap_zero_page_area zeros the specified hardware page by mapping
4071 * the page into KVM and using bzero to clear its contents.
4073 * off and size may not cover an area beyond a single hardware page.
4076 pmap_zero_page_area(vm_page_t m, int off, int size)
4079 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), off, size);
4087 * This is a local function used to work out the best strategy to clean
4088 * a single page referenced by its entry in the PV table. It should be used by
4089 * pmap_copy_page, pmap_zero page and maybe some others later on.
4091 * Its policy is effectively:
4092 * o If there are no mappings, we don't bother doing anything with the cache.
4093 * o If there is one mapping, we clean just that page.
4094 * o If there are multiple mappings, we clean the entire cache.
4096 * So that some functions can be further optimised, it returns 0 if it didn't
4097 * clean the entire cache, or 1 if it did.
4099 * XXX One bug in this routine is that if the pv_entry has a single page
4100 * mapped at 0x00000000 a whole cache clean will be performed rather than
4101 * just the 1 page. Since this should not occur in everyday use and if it does
4102 * it will just result in not the most efficient clean for the page.
4104 * We don't yet use this function but may want to.
4107 pmap_clean_page(struct pv_entry *pv, boolean_t is_src)
4109 pmap_t pm, pm_to_clean = NULL;
4110 struct pv_entry *npv;
4111 u_int cache_needs_cleaning = 0;
4113 vm_offset_t page_to_clean = 0;
4116 /* nothing mapped in so nothing to flush */
4121 * Since we flush the cache each time we change to a different
4122 * user vmspace, we only need to flush the page if it is in the
4126 pm = vmspace_pmap(curproc->p_vmspace);
4130 for (npv = pv; npv; npv = TAILQ_NEXT(npv, pv_list)) {
4131 if (npv->pv_pmap == kernel_pmap || npv->pv_pmap == pm) {
4132 flags |= npv->pv_flags;
4134 * The page is mapped non-cacheable in
4135 * this map. No need to flush the cache.
4137 if (npv->pv_flags & PVF_NC) {
4139 if (cache_needs_cleaning)
4140 panic("pmap_clean_page: "
4141 "cache inconsistency");
4144 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0)
4146 if (cache_needs_cleaning) {
4150 page_to_clean = npv->pv_va;
4151 pm_to_clean = npv->pv_pmap;
4153 cache_needs_cleaning = 1;
4156 if (page_to_clean) {
4157 if (PV_BEEN_EXECD(flags))
4158 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean,
4161 pmap_dcache_wb_range(pm_to_clean, page_to_clean,
4162 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0);
4163 } else if (cache_needs_cleaning) {
4164 if (PV_BEEN_EXECD(flags))
4165 pmap_idcache_wbinv_all(pm);
4167 pmap_dcache_wbinv_all(pm);
4175 * pmap_copy_page copies the specified (machine independent)
4176 * page by mapping the page into virtual memory and using
4177 * bcopy to copy the page, one machine dependent page at a
4184 * Copy one physical page into another, by mapping the pages into
4185 * hook points. The same comment regarding cachability as in
4186 * pmap_zero_page also applies here.
4188 #if ARM_MMU_GENERIC != 0 || defined (CPU_XSCALE_CORE3)
4190 pmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst)
4193 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4197 * Clean the source page. Hold the source page's lock for
4198 * the duration of the copy so that no other mappings can
4199 * be created while we have a potentially aliased mapping.
4203 * XXX: Not needed while we call cpu_dcache_wbinv_all() in
4206 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4209 * Map the pages into the page hook points, copy them, and purge
4210 * the cache for the appropriate page. Invalidate the TLB
4214 *csrc_pte = L2_S_PROTO | src |
4215 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
4217 *cdst_pte = L2_S_PROTO | dst |
4218 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
4220 cpu_tlb_flushD_SE(csrcp);
4221 cpu_tlb_flushD_SE(cdstp);
4223 bcopy_page(csrcp, cdstp);
4225 cpu_dcache_inv_range(csrcp, PAGE_SIZE);
4226 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE);
4227 cpu_l2cache_inv_range(csrcp, PAGE_SIZE);
4228 cpu_l2cache_wbinv_range(cdstp, PAGE_SIZE);
4232 pmap_copy_page_offs_generic(vm_paddr_t a_phys, vm_offset_t a_offs,
4233 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt)
4237 *csrc_pte = L2_S_PROTO | a_phys |
4238 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
4240 *cdst_pte = L2_S_PROTO | b_phys |
4241 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
4243 cpu_tlb_flushD_SE(csrcp);
4244 cpu_tlb_flushD_SE(cdstp);
4246 bcopy((char *)csrcp + a_offs, (char *)cdstp + b_offs, cnt);
4248 cpu_dcache_inv_range(csrcp + a_offs, cnt);
4249 cpu_dcache_wbinv_range(cdstp + b_offs, cnt);
4250 cpu_l2cache_inv_range(csrcp + a_offs, cnt);
4251 cpu_l2cache_wbinv_range(cdstp + b_offs, cnt);
4253 #endif /* ARM_MMU_GENERIC != 0 */
4255 #if ARM_MMU_XSCALE == 1
4257 pmap_copy_page_xscale(vm_paddr_t src, vm_paddr_t dst)
4260 /* XXX: Only needed for pmap_clean_page(), which is commented out. */
4261 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4265 * Clean the source page. Hold the source page's lock for
4266 * the duration of the copy so that no other mappings can
4267 * be created while we have a potentially aliased mapping.
4271 * XXX: Not needed while we call cpu_dcache_wbinv_all() in
4274 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4277 * Map the pages into the page hook points, copy them, and purge
4278 * the cache for the appropriate page. Invalidate the TLB
4282 *csrc_pte = L2_S_PROTO | src |
4283 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
4284 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4286 *cdst_pte = L2_S_PROTO | dst |
4287 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4288 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4290 cpu_tlb_flushD_SE(csrcp);
4291 cpu_tlb_flushD_SE(cdstp);
4293 bcopy_page(csrcp, cdstp);
4295 xscale_cache_clean_minidata();
4299 pmap_copy_page_offs_xscale(vm_paddr_t a_phys, vm_offset_t a_offs,
4300 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt)
4304 *csrc_pte = L2_S_PROTO | a_phys |
4305 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
4306 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X);
4308 *cdst_pte = L2_S_PROTO | b_phys |
4309 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4310 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X);
4312 cpu_tlb_flushD_SE(csrcp);
4313 cpu_tlb_flushD_SE(cdstp);
4315 bcopy((char *)csrcp + a_offs, (char *)cdstp + b_offs, cnt);
4317 xscale_cache_clean_minidata();
4319 #endif /* ARM_MMU_XSCALE == 1 */
4322 pmap_copy_page(vm_page_t src, vm_page_t dst)
4325 cpu_dcache_wbinv_all();
4326 cpu_l2cache_wbinv_all();
4327 if (_arm_memcpy && PAGE_SIZE >= _min_memcpy_size &&
4328 _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst),
4329 (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0)
4331 pmap_copy_page_func(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst));
4335 * We have code to do unmapped I/O. However, it isn't quite right and
4336 * causes un-page-aligned I/O to devices to fail (most notably newfs
4337 * or fsck). We give up a little performance to not allow unmapped I/O
4338 * to gain stability.
4340 int unmapped_buf_allowed = 0;
4343 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4344 vm_offset_t b_offset, int xfersize)
4346 vm_page_t a_pg, b_pg;
4347 vm_offset_t a_pg_offset, b_pg_offset;
4350 cpu_dcache_wbinv_all();
4351 cpu_l2cache_wbinv_all();
4352 while (xfersize > 0) {
4353 a_pg = ma[a_offset >> PAGE_SHIFT];
4354 a_pg_offset = a_offset & PAGE_MASK;
4355 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4356 b_pg = mb[b_offset >> PAGE_SHIFT];
4357 b_pg_offset = b_offset & PAGE_MASK;
4358 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4359 pmap_copy_page_offs_func(VM_PAGE_TO_PHYS(a_pg), a_pg_offset,
4360 VM_PAGE_TO_PHYS(b_pg), b_pg_offset, cnt);
4368 pmap_quick_enter_page(vm_page_t m)
4371 * Don't bother with a PCPU pageframe, since we don't support
4372 * SMP for anything pre-armv7. Use pmap_kenter() to ensure
4373 * caching is handled correctly for multiple mappings of the
4374 * same physical page.
4377 mtx_assert(&qmap_mtx, MA_NOTOWNED);
4378 mtx_lock(&qmap_mtx);
4380 pmap_kenter(qmap_addr, VM_PAGE_TO_PHYS(m));
4386 pmap_quick_remove_page(vm_offset_t addr)
4388 KASSERT(addr == qmap_addr,
4389 ("pmap_quick_remove_page: invalid address"));
4390 mtx_assert(&qmap_mtx, MA_OWNED);
4392 mtx_unlock(&qmap_mtx);
4396 * this routine returns true if a physical page resides
4397 * in the given pmap.
4400 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4406 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4407 ("pmap_page_exists_quick: page %p is not managed", m));
4409 rw_wlock(&pvh_global_lock);
4410 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4411 if (pv->pv_pmap == pmap) {
4419 rw_wunlock(&pvh_global_lock);
4424 * pmap_page_wired_mappings:
4426 * Return the number of managed mappings to the given physical page
4430 pmap_page_wired_mappings(vm_page_t m)
4436 if ((m->oflags & VPO_UNMANAGED) != 0)
4438 rw_wlock(&pvh_global_lock);
4439 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
4440 if ((pv->pv_flags & PVF_WIRED) != 0)
4442 rw_wunlock(&pvh_global_lock);
4447 * This function is advisory.
4450 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4455 * pmap_ts_referenced:
4457 * Return the count of reference bits for a page, clearing all of them.
4460 pmap_ts_referenced(vm_page_t m)
4463 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4464 ("pmap_ts_referenced: page %p is not managed", m));
4465 return (pmap_clearbit(m, PVF_REF));
4470 pmap_is_modified(vm_page_t m)
4473 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4474 ("pmap_is_modified: page %p is not managed", m));
4475 if (m->md.pvh_attrs & PVF_MOD)
4483 * Clear the modify bits on the specified physical page.
4486 pmap_clear_modify(vm_page_t m)
4489 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4490 ("pmap_clear_modify: page %p is not managed", m));
4491 VM_OBJECT_ASSERT_WLOCKED(m->object);
4492 KASSERT(!vm_page_xbusied(m),
4493 ("pmap_clear_modify: page %p is exclusive busied", m));
4496 * If the page is not PGA_WRITEABLE, then no mappings can be modified.
4497 * If the object containing the page is locked and the page is not
4498 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
4500 if ((m->aflags & PGA_WRITEABLE) == 0)
4502 if (m->md.pvh_attrs & PVF_MOD)
4503 pmap_clearbit(m, PVF_MOD);
4508 * pmap_is_referenced:
4510 * Return whether or not the specified physical page was referenced
4511 * in any physical maps.
4514 pmap_is_referenced(vm_page_t m)
4517 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4518 ("pmap_is_referenced: page %p is not managed", m));
4519 return ((m->md.pvh_attrs & PVF_REF) != 0);
4524 * Clear the write and modified bits in each of the given page's mappings.
4527 pmap_remove_write(vm_page_t m)
4530 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4531 ("pmap_remove_write: page %p is not managed", m));
4534 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4535 * set by another thread while the object is locked. Thus,
4536 * if PGA_WRITEABLE is clear, no page table entries need updating.
4538 VM_OBJECT_ASSERT_WLOCKED(m->object);
4539 if (vm_page_xbusied(m) || (m->aflags & PGA_WRITEABLE) != 0)
4540 pmap_clearbit(m, PVF_WRITE);
4545 * perform the pmap work for mincore
4548 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
4550 struct l2_bucket *l2b;
4551 pt_entry_t *ptep, pte;
4559 l2b = pmap_get_l2_bucket(pmap, addr);
4564 ptep = &l2b->l2b_kva[l2pte_index(addr)];
4566 if (!l2pte_valid(pte)) {
4570 val = MINCORE_INCORE;
4571 if (pte & L2_S_PROT_W)
4572 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4575 m = PHYS_TO_VM_PAGE(pa);
4576 if (m != NULL && !(m->oflags & VPO_UNMANAGED))
4580 * The ARM pmap tries to maintain a per-mapping
4581 * reference bit. The trouble is that it's kept in
4582 * the PV entry, not the PTE, so it's costly to access
4583 * here. You would need to acquire the pvh global
4584 * lock, call pmap_find_pv(), and introduce a custom
4585 * version of vm_page_pa_tryrelock() that releases and
4586 * reacquires the pvh global lock. In the end, I
4587 * doubt it's worthwhile. This may falsely report
4588 * the given address as referenced.
4590 if ((m->md.pvh_attrs & PVF_REF) != 0)
4591 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4593 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
4594 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
4595 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
4596 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
4600 PA_UNLOCK_COND(*locked_pa);
4607 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
4613 * Increase the starting virtual address of the given mapping if a
4614 * different alignment might result in more superpage mappings.
4617 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
4618 vm_offset_t *addr, vm_size_t size)
4622 #define BOOTSTRAP_DEBUG
4627 * Create a single section mapping.
4630 pmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4631 int prot, int cache)
4633 pd_entry_t *pde = (pd_entry_t *) l1pt;
4636 KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2"));
4645 fl = pte_l1_s_cache_mode;
4649 fl = pte_l1_s_cache_mode_pt;
4653 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4654 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL);
4655 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4662 * Link the L2 page table specified by l2pv.pv_pa into the L1
4663 * page table at the slot for "va".
4666 pmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv)
4668 pd_entry_t *pde = (pd_entry_t *) l1pt, proto;
4669 u_int slot = va >> L1_S_SHIFT;
4671 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO;
4673 #ifdef VERBOSE_INIT_ARM
4674 printf("pmap_link_l2pt: pa=0x%x va=0x%x\n", l2pv->pv_pa, l2pv->pv_va);
4677 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000);
4679 PTE_SYNC(&pde[slot]);
4681 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list);
4689 * Create a single page mapping.
4692 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot,
4695 pd_entry_t *pde = (pd_entry_t *) l1pt;
4699 KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin"));
4708 fl = pte_l2_s_cache_mode;
4712 fl = pte_l2_s_cache_mode_pt;
4716 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4717 panic("pmap_map_entry: no L2 table for VA 0x%08x", va);
4719 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4722 panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va);
4724 pte[l2pte_index(va)] =
4725 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl;
4726 PTE_SYNC(&pte[l2pte_index(va)]);
4732 * Map a chunk of memory using the most efficient mappings
4733 * possible (section. large page, small page) into the
4734 * provided L1 and L2 tables at the specified virtual address.
4737 pmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4738 vm_size_t size, int prot, int cache)
4740 pd_entry_t *pde = (pd_entry_t *) l1pt;
4741 pt_entry_t *pte, f1, f2s, f2l;
4745 resid = roundup2(size, PAGE_SIZE);
4748 panic("pmap_map_chunk: no L1 table provided");
4750 #ifdef VERBOSE_INIT_ARM
4751 printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x "
4752 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache);
4764 f1 = pte_l1_s_cache_mode;
4765 f2l = pte_l2_l_cache_mode;
4766 f2s = pte_l2_s_cache_mode;
4770 f1 = pte_l1_s_cache_mode_pt;
4771 f2l = pte_l2_l_cache_mode_pt;
4772 f2s = pte_l2_s_cache_mode_pt;
4779 /* See if we can use a section mapping. */
4780 if (L1_S_MAPPABLE_P(va, pa, resid)) {
4781 #ifdef VERBOSE_INIT_ARM
4784 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4785 L1_S_PROT(PTE_KERNEL, prot) | f1 |
4786 L1_S_DOM(PMAP_DOMAIN_KERNEL);
4787 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4795 * Ok, we're going to use an L2 table. Make sure
4796 * one is actually in the corresponding L1 slot
4797 * for the current VA.
4799 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4800 panic("pmap_map_chunk: no L2 table for VA 0x%08x", va);
4802 pte = (pt_entry_t *) kernel_pt_lookup(
4803 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4805 panic("pmap_map_chunk: can't find L2 table for VA"
4807 /* See if we can use a L2 large page mapping. */
4808 if (L2_L_MAPPABLE_P(va, pa, resid)) {
4809 #ifdef VERBOSE_INIT_ARM
4812 for (i = 0; i < 16; i++) {
4813 pte[l2pte_index(va) + i] =
4815 L2_L_PROT(PTE_KERNEL, prot) | f2l;
4816 PTE_SYNC(&pte[l2pte_index(va) + i]);
4824 /* Use a small page mapping. */
4825 #ifdef VERBOSE_INIT_ARM
4828 pte[l2pte_index(va)] =
4829 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s;
4830 PTE_SYNC(&pte[l2pte_index(va)]);
4835 #ifdef VERBOSE_INIT_ARM
4843 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
4846 * Remember the memattr in a field that gets used to set the appropriate
4847 * bits in the PTEs as mappings are established.
4849 m->md.pv_memattr = ma;
4852 * It appears that this function can only be called before any mappings
4853 * for the page are established on ARM. If this ever changes, this code
4854 * will need to walk the pv_list and make each of the existing mappings
4855 * uncacheable, being careful to sync caches and PTEs (and maybe
4856 * invalidate TLB?) for any current mapping it modifies.
4858 if (m->md.pv_kva != 0 || TAILQ_FIRST(&m->md.pv_list) != NULL)
4859 panic("Can't change memattr on page with existing mappings");