1 /* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */
3 * Copyright 2004 Olivier Houchard.
4 * Copyright 2003 Wasabi Systems, Inc.
7 * Written by Steve C. Woodford for Wasabi Systems, Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
39 * Copyright (c) 2002-2003 Wasabi Systems, Inc.
40 * Copyright (c) 2001 Richard Earnshaw
41 * Copyright (c) 2001-2002 Christopher Gilbert
42 * All rights reserved.
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. The name of the company nor the name of the author may be used to
50 * endorse or promote products derived from this software without specific
51 * prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
66 * Copyright (c) 1999 The NetBSD Foundation, Inc.
67 * All rights reserved.
69 * This code is derived from software contributed to The NetBSD Foundation
70 * by Charles M. Hannum.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
81 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
82 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
83 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
84 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
85 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
86 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
87 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
88 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
89 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
90 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
91 * POSSIBILITY OF SUCH DAMAGE.
95 * Copyright (c) 1994-1998 Mark Brinicombe.
96 * Copyright (c) 1994 Brini.
97 * All rights reserved.
99 * This code is derived from software written for Brini by Mark Brinicombe
101 * Redistribution and use in source and binary forms, with or without
102 * modification, are permitted provided that the following conditions
104 * 1. Redistributions of source code must retain the above copyright
105 * notice, this list of conditions and the following disclaimer.
106 * 2. Redistributions in binary form must reproduce the above copyright
107 * notice, this list of conditions and the following disclaimer in the
108 * documentation and/or other materials provided with the distribution.
109 * 3. All advertising materials mentioning features or use of this software
110 * must display the following acknowledgement:
111 * This product includes software developed by Mark Brinicombe.
112 * 4. The name of the author may not be used to endorse or promote products
113 * derived from this software without specific prior written permission.
115 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
116 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
117 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
118 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
119 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
120 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
121 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
122 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
123 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
125 * RiscBSD kernel project
129 * Machine dependent vm stuff
135 * Special compilation symbols
136 * PMAP_DEBUG - Build in pmap_debug_level code
138 * Note that pmap_mapdev() and pmap_unmapdev() are implemented in arm/devmap.c
140 /* Include header files */
144 #include <sys/cdefs.h>
145 __FBSDID("$FreeBSD$");
146 #include <sys/param.h>
147 #include <sys/systm.h>
148 #include <sys/kernel.h>
150 #include <sys/lock.h>
151 #include <sys/proc.h>
152 #include <sys/malloc.h>
153 #include <sys/msgbuf.h>
154 #include <sys/mutex.h>
155 #include <sys/vmmeter.h>
156 #include <sys/mman.h>
157 #include <sys/rwlock.h>
159 #include <sys/sched.h>
162 #include <vm/vm_param.h>
165 #include <vm/vm_kern.h>
166 #include <vm/vm_object.h>
167 #include <vm/vm_map.h>
168 #include <vm/vm_page.h>
169 #include <vm/vm_pageout.h>
170 #include <vm/vm_phys.h>
171 #include <vm/vm_extern.h>
173 #include <machine/md_var.h>
174 #include <machine/cpu.h>
175 #include <machine/cpufunc.h>
176 #include <machine/pcb.h>
179 #define PDEBUG(_lev_,_stat_) \
180 if (pmap_debug_level >= (_lev_)) \
182 #define dprintf printf
184 int pmap_debug_level = 0;
186 #else /* PMAP_DEBUG */
187 #define PDEBUG(_lev_,_stat_) /* Nothing */
188 #define dprintf(x, arg...)
189 #define PMAP_INLINE __inline
190 #endif /* PMAP_DEBUG */
192 extern struct pv_addr systempage;
194 extern int last_fault_code;
197 * Internal function prototypes
199 static void pmap_free_pv_entry (pv_entry_t);
200 static pv_entry_t pmap_get_pv_entry(void);
202 static int pmap_enter_locked(pmap_t, vm_offset_t, vm_page_t,
204 static vm_paddr_t pmap_extract_locked(pmap_t pmap, vm_offset_t va);
205 static void pmap_fix_cache(struct vm_page *, pmap_t, vm_offset_t);
206 static void pmap_alloc_l1(pmap_t);
207 static void pmap_free_l1(pmap_t);
209 static int pmap_clearbit(struct vm_page *, u_int);
211 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t);
212 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t);
213 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int);
214 static vm_offset_t kernel_pt_lookup(vm_paddr_t);
216 static MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1");
218 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
219 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
220 vm_offset_t pmap_curmaxkvaddr;
221 vm_paddr_t kernel_l1pa;
223 vm_offset_t kernel_vm_end = 0;
225 vm_offset_t vm_max_kernel_address;
227 struct pmap kernel_pmap_store;
229 static pt_entry_t *csrc_pte, *cdst_pte;
230 static vm_offset_t csrcp, cdstp, qmap_addr;
231 static struct mtx cmtx, qmap_mtx;
233 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *);
235 * These routines are called when the CPU type is identified to set up
236 * the PTE prototypes, cache modes, etc.
238 * The variables are always here, just in case LKMs need to reference
239 * them (though, they shouldn't).
242 pt_entry_t pte_l1_s_cache_mode;
243 pt_entry_t pte_l1_s_cache_mode_pt;
244 pt_entry_t pte_l1_s_cache_mask;
246 pt_entry_t pte_l2_l_cache_mode;
247 pt_entry_t pte_l2_l_cache_mode_pt;
248 pt_entry_t pte_l2_l_cache_mask;
250 pt_entry_t pte_l2_s_cache_mode;
251 pt_entry_t pte_l2_s_cache_mode_pt;
252 pt_entry_t pte_l2_s_cache_mask;
254 pt_entry_t pte_l2_s_prot_u;
255 pt_entry_t pte_l2_s_prot_w;
256 pt_entry_t pte_l2_s_prot_mask;
258 pt_entry_t pte_l1_s_proto;
259 pt_entry_t pte_l1_c_proto;
260 pt_entry_t pte_l2_s_proto;
262 void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t);
263 void (*pmap_copy_page_offs_func)(vm_paddr_t a_phys,
264 vm_offset_t a_offs, vm_paddr_t b_phys, vm_offset_t b_offs,
266 void (*pmap_zero_page_func)(vm_paddr_t, int, int);
271 static caddr_t crashdumpmap;
273 extern void bcopy_page(vm_offset_t, vm_offset_t);
274 extern void bzero_page(vm_offset_t);
276 extern vm_offset_t alloc_firstaddr;
281 * Metadata for L1 translation tables.
284 /* Entry on the L1 Table list */
285 SLIST_ENTRY(l1_ttable) l1_link;
287 /* Entry on the L1 Least Recently Used list */
288 TAILQ_ENTRY(l1_ttable) l1_lru;
290 /* Track how many domains are allocated from this L1 */
291 volatile u_int l1_domain_use_count;
294 * A free-list of domain numbers for this L1.
295 * We avoid using ffs() and a bitmap to track domains since ffs()
298 u_int8_t l1_domain_first;
299 u_int8_t l1_domain_free[PMAP_DOMAINS];
301 /* Physical address of this L1 page table */
302 vm_paddr_t l1_physaddr;
304 /* KVA of this L1 page table */
309 * Convert a virtual address into its L1 table index. That is, the
310 * index used to locate the L2 descriptor table pointer in an L1 table.
311 * This is basically used to index l1->l1_kva[].
313 * Each L2 descriptor table represents 1MB of VA space.
315 #define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT)
318 * L1 Page Tables are tracked using a Least Recently Used list.
319 * - New L1s are allocated from the HEAD.
320 * - Freed L1s are added to the TAIl.
321 * - Recently accessed L1s (where an 'access' is some change to one of
322 * the userland pmaps which owns this L1) are moved to the TAIL.
324 static TAILQ_HEAD(, l1_ttable) l1_lru_list;
326 * A list of all L1 tables
328 static SLIST_HEAD(, l1_ttable) l1_list;
329 static struct mtx l1_lru_lock;
332 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots.
334 * This is normally 16MB worth L2 page descriptors for any given pmap.
335 * Reference counts are maintained for L2 descriptors so they can be
339 /* The number of L2 page descriptors allocated to this l2_dtable */
342 /* List of L2 page descriptors */
344 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */
345 vm_paddr_t l2b_phys; /* Physical address of same */
346 u_short l2b_l1idx; /* This L2 table's L1 index */
347 u_short l2b_occupancy; /* How many active descriptors */
348 } l2_bucket[L2_BUCKET_SIZE];
351 /* pmap_kenter_internal flags */
352 #define KENTER_CACHE 0x1
353 #define KENTER_USER 0x2
356 * Given an L1 table index, calculate the corresponding l2_dtable index
357 * and bucket index within the l2_dtable.
359 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \
361 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1))
364 * Given a virtual address, this macro returns the
365 * virtual address required to drop into the next L2 bucket.
367 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE)
370 * We try to map the page tables write-through, if possible. However, not
371 * all CPUs have a write-through cache mode, so on those we have to sync
372 * the cache when we frob page tables.
374 * We try to evaluate this at compile time, if possible. However, it's
375 * not always possible to do that, hence this run-time var.
377 int pmap_needs_pte_sync;
380 * Macro to determine if a mapping might be resident in the
381 * instruction cache and/or TLB
383 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC))
386 * Macro to determine if a mapping might be resident in the
387 * data cache and/or TLB
389 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0)
391 #ifndef PMAP_SHPGPERPROC
392 #define PMAP_SHPGPERPROC 200
395 #define pmap_is_current(pm) ((pm) == kernel_pmap || \
396 curproc->p_vmspace->vm_map.pmap == (pm))
397 static uma_zone_t pvzone = NULL;
399 static uma_zone_t l2table_zone;
400 static vm_offset_t pmap_kernel_l2dtable_kva;
401 static vm_offset_t pmap_kernel_l2ptp_kva;
402 static vm_paddr_t pmap_kernel_l2ptp_phys;
403 static int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0;
404 static struct rwlock pvh_global_lock;
406 void pmap_copy_page_offs_generic(vm_paddr_t a_phys, vm_offset_t a_offs,
407 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt);
408 #if ARM_MMU_XSCALE == 1
409 void pmap_copy_page_offs_xscale(vm_paddr_t a_phys, vm_offset_t a_offs,
410 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt);
414 * This list exists for the benefit of pmap_map_chunk(). It keeps track
415 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can
416 * find them as necessary.
418 * Note that the data on this list MUST remain valid after initarm() returns,
419 * as pmap_bootstrap() uses it to contruct L2 table metadata.
421 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list);
424 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt)
429 l1->l1_domain_use_count = 0;
430 l1->l1_domain_first = 0;
432 for (i = 0; i < PMAP_DOMAINS; i++)
433 l1->l1_domain_free[i] = i + 1;
436 * Copy the kernel's L1 entries to each new L1.
438 if (l1pt != kernel_pmap->pm_l1->l1_kva)
439 memcpy(l1pt, kernel_pmap->pm_l1->l1_kva, L1_TABLE_SIZE);
441 if ((l1->l1_physaddr = pmap_extract(kernel_pmap, (vm_offset_t)l1pt)) == 0)
442 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt);
443 SLIST_INSERT_HEAD(&l1_list, l1, l1_link);
444 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
448 kernel_pt_lookup(vm_paddr_t pa)
452 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) {
459 #if ARM_MMU_GENERIC != 0
461 pmap_pte_init_generic(void)
464 pte_l1_s_cache_mode = L1_S_B|L1_S_C;
465 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic;
467 pte_l2_l_cache_mode = L2_B|L2_C;
468 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic;
470 pte_l2_s_cache_mode = L2_B|L2_C;
471 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic;
474 * If we have a write-through cache, set B and C. If
475 * we have a write-back cache, then we assume setting
476 * only C will make those pages write-through.
478 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) {
479 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
480 pte_l2_l_cache_mode_pt = L2_B|L2_C;
481 pte_l2_s_cache_mode_pt = L2_B|L2_C;
483 pte_l1_s_cache_mode_pt = L1_S_C;
484 pte_l2_l_cache_mode_pt = L2_C;
485 pte_l2_s_cache_mode_pt = L2_C;
488 pte_l2_s_prot_u = L2_S_PROT_U_generic;
489 pte_l2_s_prot_w = L2_S_PROT_W_generic;
490 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic;
492 pte_l1_s_proto = L1_S_PROTO_generic;
493 pte_l1_c_proto = L1_C_PROTO_generic;
494 pte_l2_s_proto = L2_S_PROTO_generic;
496 pmap_copy_page_func = pmap_copy_page_generic;
497 pmap_copy_page_offs_func = pmap_copy_page_offs_generic;
498 pmap_zero_page_func = pmap_zero_page_generic;
501 #endif /* ARM_MMU_GENERIC != 0 */
503 #if ARM_MMU_XSCALE == 1
504 #if (ARM_NMMUS > 1) || defined (CPU_XSCALE_CORE3)
505 static u_int xscale_use_minidata;
509 pmap_pte_init_xscale(void)
512 int write_through = 0;
514 pte_l1_s_cache_mode = L1_S_B|L1_S_C|L1_S_XSCALE_P;
515 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale;
517 pte_l2_l_cache_mode = L2_B|L2_C;
518 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale;
520 pte_l2_s_cache_mode = L2_B|L2_C;
521 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale;
523 pte_l1_s_cache_mode_pt = L1_S_C;
524 pte_l2_l_cache_mode_pt = L2_C;
525 pte_l2_s_cache_mode_pt = L2_C;
526 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE
528 * The XScale core has an enhanced mode where writes that
529 * miss the cache cause a cache line to be allocated. This
530 * is significantly faster than the traditional, write-through
531 * behavior of this case.
533 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X);
534 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X);
535 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X);
536 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */
537 #ifdef XSCALE_CACHE_WRITE_THROUGH
539 * Some versions of the XScale core have various bugs in
540 * their cache units, the work-around for which is to run
541 * the cache in write-through mode. Unfortunately, this
542 * has a major (negative) impact on performance. So, we
543 * go ahead and run fast-and-loose, in the hopes that we
544 * don't line up the planets in a way that will trip the
547 * However, we give you the option to be slow-but-correct.
550 #elif defined(XSCALE_CACHE_WRITE_BACK)
551 /* force write back cache mode */
553 #elif defined(CPU_XSCALE_PXA2X0)
555 * Intel PXA2[15]0 processors are known to have a bug in
556 * write-back cache on revision 4 and earlier (stepping
557 * A[01] and B[012]). Fixed for C0 and later.
563 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK);
565 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) {
566 if ((id & CPU_ID_REVISION_MASK) < 5) {
567 /* write through for stepping A0-1 and B0-2 */
572 #endif /* XSCALE_CACHE_WRITE_THROUGH */
575 pte_l1_s_cache_mode = L1_S_C;
576 pte_l2_l_cache_mode = L2_C;
577 pte_l2_s_cache_mode = L2_C;
581 xscale_use_minidata = 1;
584 pte_l2_s_prot_u = L2_S_PROT_U_xscale;
585 pte_l2_s_prot_w = L2_S_PROT_W_xscale;
586 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale;
588 pte_l1_s_proto = L1_S_PROTO_xscale;
589 pte_l1_c_proto = L1_C_PROTO_xscale;
590 pte_l2_s_proto = L2_S_PROTO_xscale;
592 #ifdef CPU_XSCALE_CORE3
593 pmap_copy_page_func = pmap_copy_page_generic;
594 pmap_copy_page_offs_func = pmap_copy_page_offs_generic;
595 pmap_zero_page_func = pmap_zero_page_generic;
596 xscale_use_minidata = 0;
597 /* Make sure it is L2-cachable */
598 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_T);
599 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode &~ L1_S_XSCALE_P;
600 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_T) ;
601 pte_l2_l_cache_mode_pt = pte_l1_s_cache_mode;
602 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_T);
603 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode;
606 pmap_copy_page_func = pmap_copy_page_xscale;
607 pmap_copy_page_offs_func = pmap_copy_page_offs_xscale;
608 pmap_zero_page_func = pmap_zero_page_xscale;
612 * Disable ECC protection of page table access, for now.
614 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
615 auxctl &= ~XSCALE_AUXCTL_P;
616 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
620 * xscale_setup_minidata:
622 * Set up the mini-data cache clean area. We require the
623 * caller to allocate the right amount of physically and
624 * virtually contiguous space.
626 extern vm_offset_t xscale_minidata_clean_addr;
627 extern vm_size_t xscale_minidata_clean_size; /* already initialized */
629 xscale_setup_minidata(vm_offset_t l1pt, vm_offset_t va, vm_paddr_t pa)
631 pd_entry_t *pde = (pd_entry_t *) l1pt;
636 xscale_minidata_clean_addr = va;
638 /* Round it to page size. */
639 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME;
642 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) {
643 pte = (pt_entry_t *) kernel_pt_lookup(
644 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
646 panic("xscale_setup_minidata: can't find L2 table for "
647 "VA 0x%08x", (u_int32_t) va);
648 pte[l2pte_index(va)] =
649 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
650 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X);
654 * Configure the mini-data cache for write-back with
655 * read/write-allocate.
657 * NOTE: In order to reconfigure the mini-data cache, we must
658 * make sure it contains no valid data! In order to do that,
659 * we must issue a global data cache invalidate command!
661 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED!
662 * THIS IS VERY IMPORTANT!
665 /* Invalidate data and mini-data. */
666 __asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
667 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
668 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA;
669 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
674 * Allocate an L1 translation table for the specified pmap.
675 * This is called at pmap creation time.
678 pmap_alloc_l1(pmap_t pm)
680 struct l1_ttable *l1;
684 * Remove the L1 at the head of the LRU list
686 mtx_lock(&l1_lru_lock);
687 l1 = TAILQ_FIRST(&l1_lru_list);
688 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
691 * Pick the first available domain number, and update
692 * the link to the next number.
694 domain = l1->l1_domain_first;
695 l1->l1_domain_first = l1->l1_domain_free[domain];
698 * If there are still free domain numbers in this L1,
699 * put it back on the TAIL of the LRU list.
701 if (++l1->l1_domain_use_count < PMAP_DOMAINS)
702 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
704 mtx_unlock(&l1_lru_lock);
707 * Fix up the relevant bits in the pmap structure
710 pm->pm_domain = domain + 1;
714 * Free an L1 translation table.
715 * This is called at pmap destruction time.
718 pmap_free_l1(pmap_t pm)
720 struct l1_ttable *l1 = pm->pm_l1;
722 mtx_lock(&l1_lru_lock);
725 * If this L1 is currently on the LRU list, remove it.
727 if (l1->l1_domain_use_count < PMAP_DOMAINS)
728 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
731 * Free up the domain number which was allocated to the pmap
733 l1->l1_domain_free[pm->pm_domain - 1] = l1->l1_domain_first;
734 l1->l1_domain_first = pm->pm_domain - 1;
735 l1->l1_domain_use_count--;
738 * The L1 now must have at least 1 free domain, so add
739 * it back to the LRU list. If the use count is zero,
740 * put it at the head of the list, otherwise it goes
743 if (l1->l1_domain_use_count == 0) {
744 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru);
746 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
748 mtx_unlock(&l1_lru_lock);
752 * Returns a pointer to the L2 bucket associated with the specified pmap
753 * and VA, or NULL if no L2 bucket exists for the address.
755 static PMAP_INLINE struct l2_bucket *
756 pmap_get_l2_bucket(pmap_t pm, vm_offset_t va)
758 struct l2_dtable *l2;
759 struct l2_bucket *l2b;
764 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL ||
765 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL)
772 * Returns a pointer to the L2 bucket associated with the specified pmap
775 * If no L2 bucket exists, perform the necessary allocations to put an L2
776 * bucket/page table in place.
778 * Note that if a new L2 bucket/page was allocated, the caller *must*
779 * increment the bucket occupancy counter appropriately *before*
780 * releasing the pmap's lock to ensure no other thread or cpu deallocates
781 * the bucket/page in the meantime.
783 static struct l2_bucket *
784 pmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va)
786 struct l2_dtable *l2;
787 struct l2_bucket *l2b;
792 PMAP_ASSERT_LOCKED(pm);
793 rw_assert(&pvh_global_lock, RA_WLOCKED);
794 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
796 * No mapping at this address, as there is
797 * no entry in the L1 table.
798 * Need to allocate a new l2_dtable.
801 rw_wunlock(&pvh_global_lock);
802 if ((l2 = uma_zalloc(l2table_zone, M_NOWAIT)) == NULL) {
803 rw_wlock(&pvh_global_lock);
807 rw_wlock(&pvh_global_lock);
809 if (pm->pm_l2[L2_IDX(l1idx)] != NULL) {
811 * Someone already allocated the l2_dtable while
812 * we were doing the same.
814 uma_zfree(l2table_zone, l2);
815 l2 = pm->pm_l2[L2_IDX(l1idx)];
817 bzero(l2, sizeof(*l2));
819 * Link it into the parent pmap
821 pm->pm_l2[L2_IDX(l1idx)] = l2;
825 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
828 * Fetch pointer to the L2 page table associated with the address.
830 if (l2b->l2b_kva == NULL) {
834 * No L2 page table has been allocated. Chances are, this
835 * is because we just allocated the l2_dtable, above.
839 rw_wunlock(&pvh_global_lock);
840 ptep = uma_zalloc(l2zone, M_NOWAIT);
841 rw_wlock(&pvh_global_lock);
843 if (l2b->l2b_kva != NULL) {
844 /* We lost the race. */
846 uma_zfree(l2zone, ptep);
849 l2b->l2b_phys = vtophys(ptep);
852 * Oops, no more L2 page tables available at this
853 * time. We may need to deallocate the l2_dtable
854 * if we allocated a new one above.
857 if (l2->l2_occupancy == 0) {
858 pm->pm_l2[L2_IDX(l1idx)] = NULL;
859 uma_zfree(l2table_zone, l2);
865 l2b->l2b_l1idx = l1idx;
871 static PMAP_INLINE void
872 #ifndef PMAP_INCLUDE_PTE_SYNC
873 pmap_free_l2_ptp(pt_entry_t *l2)
875 pmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2)
878 #ifdef PMAP_INCLUDE_PTE_SYNC
880 * Note: With a write-back cache, we may need to sync this
881 * L2 table before re-using it.
882 * This is because it may have belonged to a non-current
883 * pmap, in which case the cache syncs would have been
884 * skipped when the pages were being unmapped. If the
885 * L2 table were then to be immediately re-allocated to
886 * the *current* pmap, it may well contain stale mappings
887 * which have not yet been cleared by a cache write-back
888 * and so would still be visible to the mmu.
891 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
893 uma_zfree(l2zone, l2);
896 * One or more mappings in the specified L2 descriptor table have just been
899 * Garbage collect the metadata and descriptor table itself if necessary.
901 * The pmap lock must be acquired when this is called (not necessary
902 * for the kernel pmap).
905 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count)
907 struct l2_dtable *l2;
908 pd_entry_t *pl1pd, l1pd;
914 * Update the bucket's reference count according to how many
915 * PTEs the caller has just invalidated.
917 l2b->l2b_occupancy -= count;
922 * Level 2 page tables allocated to the kernel pmap are never freed
923 * as that would require checking all Level 1 page tables and
924 * removing any references to the Level 2 page table. See also the
925 * comment elsewhere about never freeing bootstrap L2 descriptors.
927 * We make do with just invalidating the mapping in the L2 table.
929 * This isn't really a big deal in practice and, in fact, leads
930 * to a performance win over time as we don't need to continually
933 if (l2b->l2b_occupancy > 0 || pm == kernel_pmap)
937 * There are no more valid mappings in this level 2 page table.
938 * Go ahead and NULL-out the pointer in the bucket, then
939 * free the page table.
941 l1idx = l2b->l2b_l1idx;
945 pl1pd = &pm->pm_l1->l1_kva[l1idx];
948 * If the L1 slot matches the pmap's domain
949 * number, then invalidate it.
951 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK);
952 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) {
958 * Release the L2 descriptor table back to the pool cache.
960 #ifndef PMAP_INCLUDE_PTE_SYNC
961 pmap_free_l2_ptp(ptep);
963 pmap_free_l2_ptp(!pmap_is_current(pm), ptep);
967 * Update the reference count in the associated l2_dtable
969 l2 = pm->pm_l2[L2_IDX(l1idx)];
970 if (--l2->l2_occupancy > 0)
974 * There are no more valid mappings in any of the Level 1
975 * slots managed by this l2_dtable. Go ahead and NULL-out
976 * the pointer in the parent pmap and free the l2_dtable.
978 pm->pm_l2[L2_IDX(l1idx)] = NULL;
979 uma_zfree(l2table_zone, l2);
983 * Pool cache constructors for L2 descriptor tables, metadata and pmap
987 pmap_l2ptp_ctor(void *mem, int size, void *arg, int flags)
989 #ifndef PMAP_INCLUDE_PTE_SYNC
990 struct l2_bucket *l2b;
991 pt_entry_t *ptep, pte;
993 vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK;
996 * The mappings for these page tables were initially made using
997 * pmap_kenter() by the pool subsystem. Therefore, the cache-
998 * mode will not be right for page table mappings. To avoid
999 * polluting the pmap_kenter() code with a special case for
1000 * page tables, we simply fix up the cache-mode here if it's not
1003 l2b = pmap_get_l2_bucket(kernel_pmap, va);
1004 ptep = &l2b->l2b_kva[l2pte_index(va)];
1007 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
1009 * Page tables must have the cache-mode set to
1012 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
1014 cpu_tlb_flushD_SE(va);
1018 memset(mem, 0, L2_TABLE_SIZE_REAL);
1019 PTE_SYNC_RANGE(mem, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
1024 * A bunch of routines to conditionally flush the caches/TLB depending
1025 * on whether the specified pmap actually needs to be flushed at any
1028 static PMAP_INLINE void
1029 pmap_tlb_flushID_SE(pmap_t pm, vm_offset_t va)
1032 if (pmap_is_current(pm))
1033 cpu_tlb_flushID_SE(va);
1036 static PMAP_INLINE void
1037 pmap_tlb_flushD_SE(pmap_t pm, vm_offset_t va)
1040 if (pmap_is_current(pm))
1041 cpu_tlb_flushD_SE(va);
1044 static PMAP_INLINE void
1045 pmap_tlb_flushID(pmap_t pm)
1048 if (pmap_is_current(pm))
1051 static PMAP_INLINE void
1052 pmap_tlb_flushD(pmap_t pm)
1055 if (pmap_is_current(pm))
1060 pmap_has_valid_mapping(pmap_t pm, vm_offset_t va)
1065 if (pmap_get_pde_pte(pm, va, &pde, &ptep) &&
1066 ptep && ((*ptep & L2_TYPE_MASK) != L2_TYPE_INV))
1072 static PMAP_INLINE void
1073 pmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len)
1077 CTR4(KTR_PMAP, "pmap_dcache_wbinv_range: pmap %p is_kernel %d va 0x%08x"
1078 " len 0x%x ", pm, pm == kernel_pmap, va, len);
1080 if (pmap_is_current(pm) || pm == kernel_pmap) {
1081 rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len);
1083 if (pmap_has_valid_mapping(pm, va)) {
1084 cpu_idcache_wbinv_range(va, rest);
1085 cpu_l2cache_wbinv_range(va, rest);
1089 rest = MIN(PAGE_SIZE, len);
1094 static PMAP_INLINE void
1095 pmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len, boolean_t do_inv,
1100 CTR4(KTR_PMAP, "pmap_dcache_wb_range: pmap %p is_kernel %d va 0x%08x "
1101 "len 0x%x ", pm, pm == kernel_pmap, va, len);
1102 CTR2(KTR_PMAP, " do_inv %d rd_only %d", do_inv, rd_only);
1104 if (pmap_is_current(pm)) {
1105 rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len);
1107 if (pmap_has_valid_mapping(pm, va)) {
1108 if (do_inv && rd_only) {
1109 cpu_dcache_inv_range(va, rest);
1110 cpu_l2cache_inv_range(va, rest);
1111 } else if (do_inv) {
1112 cpu_dcache_wbinv_range(va, rest);
1113 cpu_l2cache_wbinv_range(va, rest);
1114 } else if (!rd_only) {
1115 cpu_dcache_wb_range(va, rest);
1116 cpu_l2cache_wb_range(va, rest);
1122 rest = MIN(PAGE_SIZE, len);
1127 static PMAP_INLINE void
1128 pmap_idcache_wbinv_all(pmap_t pm)
1131 if (pmap_is_current(pm)) {
1132 cpu_idcache_wbinv_all();
1133 cpu_l2cache_wbinv_all();
1138 static PMAP_INLINE void
1139 pmap_dcache_wbinv_all(pmap_t pm)
1142 if (pmap_is_current(pm)) {
1143 cpu_dcache_wbinv_all();
1144 cpu_l2cache_wbinv_all();
1152 * Make sure the pte is written out to RAM.
1153 * We need to do this for one of two cases:
1154 * - We're dealing with the kernel pmap
1155 * - There is no pmap active in the cache/tlb.
1156 * - The specified pmap is 'active' in the cache/tlb.
1158 #ifdef PMAP_INCLUDE_PTE_SYNC
1159 #define PTE_SYNC_CURRENT(pm, ptep) \
1161 if (PMAP_NEEDS_PTE_SYNC && \
1162 pmap_is_current(pm)) \
1164 } while (/*CONSTCOND*/0)
1166 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */
1170 * cacheable == -1 means we must make the entry uncacheable, 1 means
1173 static __inline void
1174 pmap_set_cache_entry(pv_entry_t pv, pmap_t pm, vm_offset_t va, int cacheable)
1176 struct l2_bucket *l2b;
1177 pt_entry_t *ptep, pte;
1179 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
1180 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
1182 if (cacheable == 1) {
1183 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode;
1184 if (l2pte_valid(pte)) {
1185 if (PV_BEEN_EXECD(pv->pv_flags)) {
1186 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va);
1187 } else if (PV_BEEN_REFD(pv->pv_flags)) {
1188 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va);
1192 pte = *ptep &~ L2_S_CACHE_MASK;
1193 if ((va != pv->pv_va || pm != pv->pv_pmap) &&
1195 if (PV_BEEN_EXECD(pv->pv_flags)) {
1196 pmap_idcache_wbinv_range(pv->pv_pmap,
1197 pv->pv_va, PAGE_SIZE);
1198 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va);
1199 } else if (PV_BEEN_REFD(pv->pv_flags)) {
1200 pmap_dcache_wb_range(pv->pv_pmap,
1201 pv->pv_va, PAGE_SIZE, TRUE,
1202 (pv->pv_flags & PVF_WRITE) == 0);
1203 pmap_tlb_flushD_SE(pv->pv_pmap,
1209 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
1213 pmap_fix_cache(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1216 int writable = 0, kwritable = 0, uwritable = 0;
1217 int entries = 0, kentries = 0, uentries = 0;
1218 struct pv_entry *pv;
1220 rw_assert(&pvh_global_lock, RA_WLOCKED);
1222 /* the cache gets written back/invalidated on context switch.
1223 * therefore, if a user page shares an entry in the same page or
1224 * with the kernel map and at least one is writable, then the
1225 * cache entry must be set write-through.
1228 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1229 /* generate a count of the pv_entry uses */
1230 if (pv->pv_flags & PVF_WRITE) {
1231 if (pv->pv_pmap == kernel_pmap)
1233 else if (pv->pv_pmap == pm)
1237 if (pv->pv_pmap == kernel_pmap)
1240 if (pv->pv_pmap == pm)
1246 * check if the user duplicate mapping has
1249 if ((pm != kernel_pmap) && (((uentries > 1) && uwritable) ||
1253 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1254 /* check for user uncachable conditions - order is important */
1255 if (pm != kernel_pmap &&
1256 (pv->pv_pmap == pm || pv->pv_pmap == kernel_pmap)) {
1258 if ((uentries > 1 && uwritable) || uwritable > 1) {
1260 /* user duplicate mapping */
1261 if (pv->pv_pmap != kernel_pmap)
1262 pv->pv_flags |= PVF_MWC;
1264 if (!(pv->pv_flags & PVF_NC)) {
1265 pv->pv_flags |= PVF_NC;
1266 pmap_set_cache_entry(pv, pm, va, -1);
1269 } else /* no longer a duplicate user */
1270 pv->pv_flags &= ~PVF_MWC;
1274 * check for kernel uncachable conditions
1275 * kernel writable or kernel readable with writable user entry
1277 if ((kwritable && (entries || kentries > 1)) ||
1279 ((kwritable != writable) && kentries &&
1280 (pv->pv_pmap == kernel_pmap ||
1281 (pv->pv_flags & PVF_WRITE) ||
1282 (pv->pv_flags & PVF_MWC)))) {
1284 if (!(pv->pv_flags & PVF_NC)) {
1285 pv->pv_flags |= PVF_NC;
1286 pmap_set_cache_entry(pv, pm, va, -1);
1291 /* kernel and user are cachable */
1292 if ((pm == kernel_pmap) && !(pv->pv_flags & PVF_MWC) &&
1293 (pv->pv_flags & PVF_NC)) {
1295 pv->pv_flags &= ~PVF_NC;
1296 if (pg->md.pv_memattr != VM_MEMATTR_UNCACHEABLE)
1297 pmap_set_cache_entry(pv, pm, va, 1);
1300 /* user is no longer sharable and writable */
1301 if (pm != kernel_pmap &&
1302 (pv->pv_pmap == pm || pv->pv_pmap == kernel_pmap) &&
1303 !pmwc && (pv->pv_flags & PVF_NC)) {
1305 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1306 if (pg->md.pv_memattr != VM_MEMATTR_UNCACHEABLE)
1307 pmap_set_cache_entry(pv, pm, va, 1);
1311 if ((kwritable == 0) && (writable == 0)) {
1312 pg->md.pvh_attrs &= ~PVF_MOD;
1313 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1319 * Modify pte bits for all ptes corresponding to the given physical address.
1320 * We use `maskbits' rather than `clearbits' because we're always passing
1321 * constants and the latter would require an extra inversion at run-time.
1324 pmap_clearbit(struct vm_page *pg, u_int maskbits)
1326 struct l2_bucket *l2b;
1327 struct pv_entry *pv;
1328 pt_entry_t *ptep, npte, opte;
1334 rw_wlock(&pvh_global_lock);
1336 if (maskbits & PVF_WRITE)
1337 maskbits |= PVF_MOD;
1339 * Clear saved attributes (modify, reference)
1341 pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF));
1343 if (TAILQ_EMPTY(&pg->md.pv_list)) {
1344 rw_wunlock(&pvh_global_lock);
1349 * Loop over all current mappings setting/clearing as appropos
1351 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1354 oflags = pv->pv_flags;
1356 if (!(oflags & maskbits)) {
1357 if ((maskbits & PVF_WRITE) && (pv->pv_flags & PVF_NC)) {
1358 if (pg->md.pv_memattr !=
1359 VM_MEMATTR_UNCACHEABLE) {
1361 l2b = pmap_get_l2_bucket(pm, va);
1362 ptep = &l2b->l2b_kva[l2pte_index(va)];
1363 *ptep |= pte_l2_s_cache_mode;
1367 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1371 pv->pv_flags &= ~maskbits;
1375 l2b = pmap_get_l2_bucket(pm, va);
1377 ptep = &l2b->l2b_kva[l2pte_index(va)];
1378 npte = opte = *ptep;
1380 if (maskbits & (PVF_WRITE|PVF_MOD)) {
1381 if ((pv->pv_flags & PVF_NC)) {
1383 * Entry is not cacheable:
1385 * Don't turn caching on again if this is a
1386 * modified emulation. This would be
1387 * inconsistent with the settings created by
1388 * pmap_fix_cache(). Otherwise, it's safe
1389 * to re-enable caching.
1391 * There's no need to call pmap_fix_cache()
1392 * here: all pages are losing their write
1395 if (maskbits & PVF_WRITE) {
1396 if (pg->md.pv_memattr !=
1397 VM_MEMATTR_UNCACHEABLE)
1398 npte |= pte_l2_s_cache_mode;
1399 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1402 if (opte & L2_S_PROT_W) {
1405 * Entry is writable/cacheable: check if pmap
1406 * is current if it is flush it, otherwise it
1407 * won't be in the cache
1409 if (PV_BEEN_EXECD(oflags))
1410 pmap_idcache_wbinv_range(pm, pv->pv_va,
1413 if (PV_BEEN_REFD(oflags))
1414 pmap_dcache_wb_range(pm, pv->pv_va,
1416 (maskbits & PVF_REF) ? TRUE : FALSE,
1420 /* make the pte read only */
1421 npte &= ~L2_S_PROT_W;
1424 if (maskbits & PVF_REF) {
1425 if ((pv->pv_flags & PVF_NC) == 0 &&
1426 (maskbits & (PVF_WRITE|PVF_MOD)) == 0) {
1428 * Check npte here; we may have already
1429 * done the wbinv above, and the validity
1430 * of the PTE is the same for opte and
1433 if (npte & L2_S_PROT_W) {
1434 if (PV_BEEN_EXECD(oflags))
1435 pmap_idcache_wbinv_range(pm,
1436 pv->pv_va, PAGE_SIZE);
1438 if (PV_BEEN_REFD(oflags))
1439 pmap_dcache_wb_range(pm,
1440 pv->pv_va, PAGE_SIZE,
1443 if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) {
1444 /* XXXJRT need idcache_inv_range */
1445 if (PV_BEEN_EXECD(oflags))
1446 pmap_idcache_wbinv_range(pm,
1447 pv->pv_va, PAGE_SIZE);
1449 if (PV_BEEN_REFD(oflags))
1450 pmap_dcache_wb_range(pm,
1451 pv->pv_va, PAGE_SIZE,
1457 * Make the PTE invalid so that we will take a
1458 * page fault the next time the mapping is
1461 npte &= ~L2_TYPE_MASK;
1462 npte |= L2_TYPE_INV;
1469 /* Flush the TLB entry if a current pmap. */
1470 if (PV_BEEN_EXECD(oflags))
1471 pmap_tlb_flushID_SE(pm, pv->pv_va);
1473 if (PV_BEEN_REFD(oflags))
1474 pmap_tlb_flushD_SE(pm, pv->pv_va);
1481 if (maskbits & PVF_WRITE)
1482 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1483 rw_wunlock(&pvh_global_lock);
1488 * main pv_entry manipulation functions:
1489 * pmap_enter_pv: enter a mapping onto a vm_page list
1490 * pmap_remove_pv: remove a mappiing from a vm_page list
1492 * NOTE: pmap_enter_pv expects to lock the pvh itself
1493 * pmap_remove_pv expects the caller to lock the pvh before calling
1497 * pmap_enter_pv: enter a mapping onto a vm_page's PV list
1499 * => caller should hold the proper lock on pvh_global_lock
1500 * => caller should have pmap locked
1501 * => we will (someday) gain the lock on the vm_page's PV list
1502 * => caller should adjust ptp's wire_count before calling
1503 * => caller should not adjust pmap's wire_count
1506 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm,
1507 vm_offset_t va, u_int flags)
1510 rw_assert(&pvh_global_lock, RA_WLOCKED);
1511 PMAP_ASSERT_LOCKED(pm);
1512 if (pg->md.pv_kva != 0) {
1513 pve->pv_pmap = kernel_pmap;
1514 pve->pv_va = pg->md.pv_kva;
1515 pve->pv_flags = PVF_WRITE | PVF_UNMAN;
1516 if (pm != kernel_pmap)
1517 PMAP_LOCK(kernel_pmap);
1518 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list);
1519 TAILQ_INSERT_HEAD(&kernel_pmap->pm_pvlist, pve, pv_plist);
1520 if (pm != kernel_pmap)
1521 PMAP_UNLOCK(kernel_pmap);
1523 if ((pve = pmap_get_pv_entry()) == NULL)
1524 panic("pmap_kenter_pv: no pv entries");
1528 pve->pv_flags = flags;
1529 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list);
1530 TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist);
1531 pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD);
1532 if (pve->pv_flags & PVF_WIRED)
1533 ++pm->pm_stats.wired_count;
1534 vm_page_aflag_set(pg, PGA_REFERENCED);
1539 * pmap_find_pv: Find a pv entry
1541 * => caller should hold lock on vm_page
1543 static PMAP_INLINE struct pv_entry *
1544 pmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1546 struct pv_entry *pv;
1548 rw_assert(&pvh_global_lock, RA_WLOCKED);
1549 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list)
1550 if (pm == pv->pv_pmap && va == pv->pv_va)
1556 * vector_page_setprot:
1558 * Manipulate the protection of the vector page.
1561 vector_page_setprot(int prot)
1563 struct l2_bucket *l2b;
1566 l2b = pmap_get_l2_bucket(kernel_pmap, vector_page);
1568 ptep = &l2b->l2b_kva[l2pte_index(vector_page)];
1570 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot);
1572 cpu_tlb_flushD_SE(vector_page);
1577 * pmap_remove_pv: try to remove a mapping from a pv_list
1579 * => caller should hold proper lock on pmap_main_lock
1580 * => pmap should be locked
1581 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1582 * => caller should adjust ptp's wire_count and free PTP if needed
1583 * => caller should NOT adjust pmap's wire_count
1584 * => we return the removed pve
1588 pmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve)
1591 struct pv_entry *pv;
1592 rw_assert(&pvh_global_lock, RA_WLOCKED);
1593 PMAP_ASSERT_LOCKED(pm);
1594 TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list);
1595 TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist);
1596 if (pve->pv_flags & PVF_WIRED)
1597 --pm->pm_stats.wired_count;
1598 if (pg->md.pvh_attrs & PVF_MOD)
1600 if (TAILQ_FIRST(&pg->md.pv_list) == NULL)
1601 pg->md.pvh_attrs &= ~PVF_REF;
1603 vm_page_aflag_set(pg, PGA_REFERENCED);
1604 if ((pve->pv_flags & PVF_NC) && ((pm == kernel_pmap) ||
1605 (pve->pv_flags & PVF_WRITE) || !(pve->pv_flags & PVF_MWC)))
1606 pmap_fix_cache(pg, pm, 0);
1607 else if (pve->pv_flags & PVF_WRITE) {
1608 TAILQ_FOREACH(pve, &pg->md.pv_list, pv_list)
1609 if (pve->pv_flags & PVF_WRITE)
1612 pg->md.pvh_attrs &= ~PVF_MOD;
1613 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1616 pv = TAILQ_FIRST(&pg->md.pv_list);
1617 if (pv != NULL && (pv->pv_flags & PVF_UNMAN) &&
1618 TAILQ_NEXT(pv, pv_list) == NULL) {
1620 pg->md.pv_kva = pv->pv_va;
1621 /* a recursive pmap_nuke_pv */
1622 TAILQ_REMOVE(&pg->md.pv_list, pv, pv_list);
1623 TAILQ_REMOVE(&pm->pm_pvlist, pv, pv_plist);
1624 if (pv->pv_flags & PVF_WIRED)
1625 --pm->pm_stats.wired_count;
1626 pg->md.pvh_attrs &= ~PVF_REF;
1627 pg->md.pvh_attrs &= ~PVF_MOD;
1628 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1629 pmap_free_pv_entry(pv);
1633 static struct pv_entry *
1634 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1636 struct pv_entry *pve;
1638 rw_assert(&pvh_global_lock, RA_WLOCKED);
1639 pve = TAILQ_FIRST(&pg->md.pv_list);
1642 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */
1643 pmap_nuke_pv(pg, pm, pve);
1646 pve = TAILQ_NEXT(pve, pv_list);
1649 if (pve == NULL && pg->md.pv_kva == va)
1652 return(pve); /* return removed pve */
1656 * pmap_modify_pv: Update pv flags
1658 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1659 * => caller should NOT adjust pmap's wire_count
1660 * => we return the old flags
1662 * Modify a physical-virtual mapping in the pv table
1665 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va,
1666 u_int clr_mask, u_int set_mask)
1668 struct pv_entry *npv;
1669 u_int flags, oflags;
1671 PMAP_ASSERT_LOCKED(pm);
1672 rw_assert(&pvh_global_lock, RA_WLOCKED);
1673 if ((npv = pmap_find_pv(pg, pm, va)) == NULL)
1677 * There is at least one VA mapping this page.
1680 if (clr_mask & (PVF_REF | PVF_MOD))
1681 pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD);
1683 oflags = npv->pv_flags;
1684 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask;
1686 if ((flags ^ oflags) & PVF_WIRED) {
1687 if (flags & PVF_WIRED)
1688 ++pm->pm_stats.wired_count;
1690 --pm->pm_stats.wired_count;
1693 if ((flags ^ oflags) & PVF_WRITE)
1694 pmap_fix_cache(pg, pm, 0);
1699 /* Function to set the debug level of the pmap code */
1702 pmap_debug(int level)
1704 pmap_debug_level = level;
1705 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
1707 #endif /* PMAP_DEBUG */
1710 pmap_pinit0(struct pmap *pmap)
1712 PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap));
1714 bcopy(kernel_pmap, pmap, sizeof(*pmap));
1715 bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx));
1716 PMAP_LOCK_INIT(pmap);
1720 * Initialize a vm_page's machine-dependent fields.
1723 pmap_page_init(vm_page_t m)
1726 TAILQ_INIT(&m->md.pv_list);
1727 m->md.pv_memattr = VM_MEMATTR_DEFAULT;
1731 * Initialize the pmap module.
1732 * Called by vm_init, to initialize any structures that the pmap
1733 * system needs to map virtual memory.
1738 int shpgperproc = PMAP_SHPGPERPROC;
1740 l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor,
1741 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1742 l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable), NULL,
1743 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1746 * Initialize the PV entry allocator.
1748 pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL,
1749 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1750 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1751 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1752 uma_zone_reserve_kva(pvzone, pv_entry_max);
1753 pv_entry_high_water = 9 * (pv_entry_max / 10);
1756 * Now it is safe to enable pv_table recording.
1758 PDEBUG(1, printf("pmap_init: done!\n"));
1762 pmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user)
1764 struct l2_dtable *l2;
1765 struct l2_bucket *l2b;
1766 pd_entry_t *pl1pd, l1pd;
1767 pt_entry_t *ptep, pte;
1773 rw_wlock(&pvh_global_lock);
1777 * If there is no l2_dtable for this address, then the process
1778 * has no business accessing it.
1780 * Note: This will catch userland processes trying to access
1783 l2 = pm->pm_l2[L2_IDX(l1idx)];
1788 * Likewise if there is no L2 descriptor table
1790 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
1791 if (l2b->l2b_kva == NULL)
1795 * Check the PTE itself.
1797 ptep = &l2b->l2b_kva[l2pte_index(va)];
1803 * Catch a userland access to the vector page mapped at 0x0
1805 if (user && (pte & L2_S_PROT_U) == 0)
1807 if (va == vector_page)
1812 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) {
1814 * This looks like a good candidate for "page modified"
1817 struct pv_entry *pv;
1820 /* Extract the physical address of the page */
1821 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) {
1824 /* Get the current flags for this page. */
1826 pv = pmap_find_pv(pg, pm, va);
1832 * Do the flags say this page is writable? If not then it
1833 * is a genuine write fault. If yes then the write fault is
1834 * our fault as we did not reflect the write access in the
1835 * PTE. Now we know a write has occurred we can correct this
1836 * and also set the modified bit
1838 if ((pv->pv_flags & PVF_WRITE) == 0) {
1842 pg->md.pvh_attrs |= PVF_REF | PVF_MOD;
1844 pv->pv_flags |= PVF_REF | PVF_MOD;
1847 * Re-enable write permissions for the page. No need to call
1848 * pmap_fix_cache(), since this is just a
1849 * modified-emulation fault, and the PVF_WRITE bit isn't
1850 * changing. We've already set the cacheable bits based on
1851 * the assumption that we can write to this page.
1853 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W;
1857 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) {
1859 * This looks like a good candidate for "page referenced"
1862 struct pv_entry *pv;
1865 /* Extract the physical address of the page */
1866 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL)
1868 /* Get the current flags for this page. */
1870 pv = pmap_find_pv(pg, pm, va);
1874 pg->md.pvh_attrs |= PVF_REF;
1875 pv->pv_flags |= PVF_REF;
1878 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO;
1884 * We know there is a valid mapping here, so simply
1885 * fix up the L1 if necessary.
1887 pl1pd = &pm->pm_l1->l1_kva[l1idx];
1888 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO;
1889 if (*pl1pd != l1pd) {
1897 * If 'rv == 0' at this point, it generally indicates that there is a
1898 * stale TLB entry for the faulting address. This happens when two or
1899 * more processes are sharing an L1. Since we don't flush the TLB on
1900 * a context switch between such processes, we can take domain faults
1901 * for mappings which exist at the same VA in both processes. EVEN IF
1902 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for
1905 * This is extremely likely to happen if pmap_enter() updated the L1
1906 * entry for a recently entered mapping. In this case, the TLB is
1907 * flushed for the new mapping, but there may still be TLB entries for
1908 * other mappings belonging to other processes in the 1MB range
1909 * covered by the L1 entry.
1911 * Since 'rv == 0', we know that the L1 already contains the correct
1912 * value, so the fault must be due to a stale TLB entry.
1914 * Since we always need to flush the TLB anyway in the case where we
1915 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with
1916 * stale TLB entries dynamically.
1918 * However, the above condition can ONLY happen if the current L1 is
1919 * being shared. If it happens when the L1 is unshared, it indicates
1920 * that other parts of the pmap are not doing their job WRT managing
1923 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) {
1924 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n",
1925 pm, (u_long)va, ftype);
1926 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n",
1927 l2, l2b, ptep, pl1pd);
1928 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n",
1929 pte, l1pd, last_fault_code);
1936 cpu_tlb_flushID_SE(va);
1942 rw_wunlock(&pvh_global_lock);
1950 struct l2_bucket *l2b;
1951 struct l1_ttable *l1;
1953 pt_entry_t *ptep, pte;
1954 vm_offset_t va, eva;
1957 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0);
1959 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK);
1961 for (loop = 0; loop < needed; loop++, l1++) {
1962 /* Allocate a L1 page table */
1963 va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0,
1964 0xffffffff, L1_TABLE_SIZE, 0);
1967 panic("Cannot allocate L1 KVM");
1969 eva = va + L1_TABLE_SIZE;
1970 pl1pt = (pd_entry_t *)va;
1973 l2b = pmap_get_l2_bucket(kernel_pmap, va);
1974 ptep = &l2b->l2b_kva[l2pte_index(va)];
1976 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
1979 cpu_tlb_flushD_SE(va);
1983 pmap_init_l1(l1, pl1pt);
1988 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n",
1994 * This is used to stuff certain critical values into the PCB where they
1995 * can be accessed quickly from cpu_switch() et al.
1998 pmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb)
2000 struct l2_bucket *l2b;
2002 pcb->pcb_pagedir = pm->pm_l1->l1_physaddr;
2003 pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) |
2004 (DOMAIN_CLIENT << (pm->pm_domain * 2));
2006 if (vector_page < KERNBASE) {
2007 pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)];
2008 l2b = pmap_get_l2_bucket(pm, vector_page);
2009 pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO |
2010 L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL);
2012 pcb->pcb_pl1vec = NULL;
2016 pmap_activate(struct thread *td)
2021 pm = vmspace_pmap(td->td_proc->p_vmspace);
2025 pmap_set_pcb_pagedir(pm, pcb);
2027 if (td == curthread) {
2028 u_int cur_dacr, cur_ttb;
2030 __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb));
2031 __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr));
2033 cur_ttb &= ~(L1_TABLE_SIZE - 1);
2035 if (cur_ttb == (u_int)pcb->pcb_pagedir &&
2036 cur_dacr == pcb->pcb_dacr) {
2038 * No need to switch address spaces.
2046 * We MUST, I repeat, MUST fix up the L1 entry corresponding
2047 * to 'vector_page' in the incoming L1 table before switching
2048 * to it otherwise subsequent interrupts/exceptions (including
2049 * domain faults!) will jump into hyperspace.
2051 if (pcb->pcb_pl1vec) {
2053 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2055 * Don't need to PTE_SYNC() at this point since
2056 * cpu_setttb() is about to flush both the cache
2061 cpu_domains(pcb->pcb_dacr);
2062 cpu_setttb(pcb->pcb_pagedir);
2068 pmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va)
2070 pd_entry_t *pdep, pde;
2071 pt_entry_t *ptep, pte;
2076 * Make sure the descriptor itself has the correct cache mode
2078 pdep = &kl1[L1_IDX(va)];
2081 if (l1pte_section_p(pde)) {
2082 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) {
2083 *pdep = (pde & ~L1_S_CACHE_MASK) |
2084 pte_l1_s_cache_mode_pt;
2086 cpu_dcache_wbinv_range((vm_offset_t)pdep,
2088 cpu_l2cache_wbinv_range((vm_offset_t)pdep,
2093 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2094 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2096 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep);
2098 ptep = &ptep[l2pte_index(va)];
2100 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
2101 *ptep = (pte & ~L2_S_CACHE_MASK) |
2102 pte_l2_s_cache_mode_pt;
2104 cpu_dcache_wbinv_range((vm_offset_t)ptep,
2106 cpu_l2cache_wbinv_range((vm_offset_t)ptep,
2116 pmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap,
2119 vm_offset_t va = *availp;
2120 struct l2_bucket *l2b;
2123 l2b = pmap_get_l2_bucket(kernel_pmap, va);
2125 panic("pmap_alloc_specials: no l2b for 0x%x", va);
2127 *ptep = &l2b->l2b_kva[l2pte_index(va)];
2131 *availp = va + (PAGE_SIZE * pages);
2135 * Bootstrap the system enough to run with virtual memory.
2137 * On the arm this is called after mapping has already been enabled
2138 * and just syncs the pmap module with what has already been done.
2139 * [We can't call it easily with mapping off since the kernel is not
2140 * mapped with PA == VA, hence we would have to relocate every address
2141 * from the linked base (virtual) address "KERNBASE" to the actual
2142 * (physical) address starting relative to 0]
2144 #define PMAP_STATIC_L2_SIZE 16
2146 pmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt)
2148 static struct l1_ttable static_l1;
2149 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE];
2150 struct l1_ttable *l1 = &static_l1;
2151 struct l2_dtable *l2;
2152 struct l2_bucket *l2b;
2154 pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va;
2156 pt_entry_t *qmap_pte;
2160 int l1idx, l2idx, l2next = 0;
2162 PDEBUG(1, printf("firstaddr = %08x, lastaddr = %08x\n",
2163 firstaddr, vm_max_kernel_address));
2165 virtual_avail = firstaddr;
2166 kernel_pmap->pm_l1 = l1;
2167 kernel_l1pa = l1pt->pv_pa;
2170 * Scan the L1 translation table created by initarm() and create
2171 * the required metadata for all valid mappings found in it.
2173 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) {
2174 pde = kernel_l1pt[l1idx];
2177 * We're only interested in Coarse mappings.
2178 * pmap_extract() can deal with section mappings without
2179 * recourse to checking L2 metadata.
2181 if ((pde & L1_TYPE_MASK) != L1_TYPE_C)
2185 * Lookup the KVA of this L2 descriptor table
2187 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2188 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2191 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx",
2192 (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa);
2196 * Fetch the associated L2 metadata structure.
2197 * Allocate a new one if necessary.
2199 if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) {
2200 if (l2next == PMAP_STATIC_L2_SIZE)
2201 panic("pmap_bootstrap: out of static L2s");
2202 kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 =
2203 &static_l2[l2next++];
2207 * One more L1 slot tracked...
2212 * Fill in the details of the L2 descriptor in the
2213 * appropriate bucket.
2215 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2216 l2b->l2b_kva = ptep;
2218 l2b->l2b_l1idx = l1idx;
2221 * Establish an initial occupancy count for this descriptor
2224 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
2226 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) {
2227 l2b->l2b_occupancy++;
2232 * Make sure the descriptor itself has the correct cache mode.
2233 * If not, fix it, but whine about the problem. Port-meisters
2234 * should consider this a clue to fix up their initarm()
2237 if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) {
2238 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2239 "L2 pte @ %p\n", ptep);
2245 * Ensure the primary (kernel) L1 has the correct cache mode for
2246 * a page table. Bitch if it is not correctly set.
2248 for (va = (vm_offset_t)kernel_l1pt;
2249 va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) {
2250 if (pmap_set_pt_cache_mode(kernel_l1pt, va))
2251 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2252 "primary L1 @ 0x%x\n", va);
2255 cpu_dcache_wbinv_all();
2256 cpu_l2cache_wbinv_all();
2260 PMAP_LOCK_INIT(kernel_pmap);
2261 CPU_FILL(&kernel_pmap->pm_active);
2262 kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL;
2263 TAILQ_INIT(&kernel_pmap->pm_pvlist);
2266 * Initialize the global pv list lock.
2268 rw_init_flags(&pvh_global_lock, "pmap pv global", RW_RECURSE);
2271 * Reserve some special page table entries/VA space for temporary
2274 pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte);
2275 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte);
2276 pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte);
2277 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte);
2278 pmap_alloc_specials(&virtual_avail, 1, &qmap_addr, &qmap_pte);
2279 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)qmap_pte);
2280 size = ((vm_max_kernel_address - pmap_curmaxkvaddr) + L1_S_OFFSET) /
2282 pmap_alloc_specials(&virtual_avail,
2283 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE,
2284 &pmap_kernel_l2ptp_kva, NULL);
2286 size = howmany(size, L2_BUCKET_SIZE);
2287 pmap_alloc_specials(&virtual_avail,
2288 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE,
2289 &pmap_kernel_l2dtable_kva, NULL);
2291 pmap_alloc_specials(&virtual_avail,
2292 1, (vm_offset_t*)&_tmppt, NULL);
2293 pmap_alloc_specials(&virtual_avail,
2294 MAXDUMPPGS, (vm_offset_t *)&crashdumpmap, NULL);
2295 SLIST_INIT(&l1_list);
2296 TAILQ_INIT(&l1_lru_list);
2297 mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF);
2298 pmap_init_l1(l1, kernel_l1pt);
2299 cpu_dcache_wbinv_all();
2300 cpu_l2cache_wbinv_all();
2302 virtual_avail = round_page(virtual_avail);
2303 virtual_end = vm_max_kernel_address;
2304 kernel_vm_end = pmap_curmaxkvaddr;
2305 mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF);
2306 mtx_init(&qmap_mtx, "quick mapping mtx", NULL, MTX_DEF);
2308 pmap_set_pcb_pagedir(kernel_pmap, thread0.td_pcb);
2311 /***************************************************
2312 * Pmap allocation/deallocation routines.
2313 ***************************************************/
2316 * Release any resources held by the given physical map.
2317 * Called when a pmap initialized by pmap_pinit is being released.
2318 * Should only be called if the map contains no valid mappings.
2321 pmap_release(pmap_t pmap)
2325 pmap_idcache_wbinv_all(pmap);
2326 cpu_l2cache_wbinv_all();
2327 pmap_tlb_flushID(pmap);
2329 if (vector_page < KERNBASE) {
2330 struct pcb *curpcb = PCPU_GET(curpcb);
2331 pcb = thread0.td_pcb;
2332 if (pmap_is_current(pmap)) {
2334 * Frob the L1 entry corresponding to the vector
2335 * page so that it contains the kernel pmap's domain
2336 * number. This will ensure pmap_remove() does not
2337 * pull the current vector page out from under us.
2340 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2341 cpu_domains(pcb->pcb_dacr);
2342 cpu_setttb(pcb->pcb_pagedir);
2345 pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE);
2347 * Make sure cpu_switch(), et al, DTRT. This is safe to do
2348 * since this process has no remaining mappings of its own.
2350 curpcb->pcb_pl1vec = pcb->pcb_pl1vec;
2351 curpcb->pcb_l1vec = pcb->pcb_l1vec;
2352 curpcb->pcb_dacr = pcb->pcb_dacr;
2353 curpcb->pcb_pagedir = pcb->pcb_pagedir;
2358 dprintf("pmap_release()\n");
2364 * Helper function for pmap_grow_l2_bucket()
2367 pmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap)
2369 struct l2_bucket *l2b;
2374 pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
2377 pa = VM_PAGE_TO_PHYS(pg);
2382 l2b = pmap_get_l2_bucket(kernel_pmap, va);
2384 ptep = &l2b->l2b_kva[l2pte_index(va)];
2385 *ptep = L2_S_PROTO | pa | cache_mode |
2386 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE);
2392 * This is the same as pmap_alloc_l2_bucket(), except that it is only
2393 * used by pmap_growkernel().
2395 static __inline struct l2_bucket *
2396 pmap_grow_l2_bucket(pmap_t pm, vm_offset_t va)
2398 struct l2_dtable *l2;
2399 struct l2_bucket *l2b;
2400 struct l1_ttable *l1;
2407 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
2409 * No mapping at this address, as there is
2410 * no entry in the L1 table.
2411 * Need to allocate a new l2_dtable.
2413 nva = pmap_kernel_l2dtable_kva;
2414 if ((nva & PAGE_MASK) == 0) {
2416 * Need to allocate a backing page
2418 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2422 l2 = (struct l2_dtable *)nva;
2423 nva += sizeof(struct l2_dtable);
2425 if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva &
2428 * The new l2_dtable straddles a page boundary.
2429 * Map in another page to cover it.
2431 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2435 pmap_kernel_l2dtable_kva = nva;
2438 * Link it into the parent pmap
2440 pm->pm_l2[L2_IDX(l1idx)] = l2;
2441 memset(l2, 0, sizeof(*l2));
2444 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2447 * Fetch pointer to the L2 page table associated with the address.
2449 if (l2b->l2b_kva == NULL) {
2453 * No L2 page table has been allocated. Chances are, this
2454 * is because we just allocated the l2_dtable, above.
2456 nva = pmap_kernel_l2ptp_kva;
2457 ptep = (pt_entry_t *)nva;
2458 if ((nva & PAGE_MASK) == 0) {
2460 * Need to allocate a backing page
2462 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt,
2463 &pmap_kernel_l2ptp_phys))
2465 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t));
2467 memset(ptep, 0, L2_TABLE_SIZE_REAL);
2469 l2b->l2b_kva = ptep;
2470 l2b->l2b_l1idx = l1idx;
2471 l2b->l2b_phys = pmap_kernel_l2ptp_phys;
2473 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL;
2474 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL;
2477 /* Distribute new L1 entry to all other L1s */
2478 SLIST_FOREACH(l1, &l1_list, l1_link) {
2479 pl1pd = &l1->l1_kva[L1_IDX(va)];
2480 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) |
2490 * grow the number of kernel page table entries, if needed
2493 pmap_growkernel(vm_offset_t addr)
2495 pmap_t kpm = kernel_pmap;
2497 if (addr <= pmap_curmaxkvaddr)
2498 return; /* we are OK */
2501 * whoops! we need to add kernel PTPs
2504 /* Map 1MB at a time */
2505 for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE)
2506 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr);
2509 * flush out the cache, expensive but growkernel will happen so
2512 cpu_dcache_wbinv_all();
2513 cpu_l2cache_wbinv_all();
2516 kernel_vm_end = pmap_curmaxkvaddr;
2521 * Remove all pages from specified address space
2522 * this aids process exit speeds. Also, this code
2523 * is special cased for current process only, but
2524 * can have the more generic (and slightly slower)
2525 * mode enabled. This is much faster than pmap_remove
2526 * in the case of running down an entire address space.
2529 pmap_remove_pages(pmap_t pmap)
2531 struct pv_entry *pv, *npv;
2532 struct l2_bucket *l2b = NULL;
2536 rw_wlock(&pvh_global_lock);
2538 cpu_idcache_wbinv_all();
2539 cpu_l2cache_wbinv_all();
2540 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) {
2541 if (pv->pv_flags & PVF_WIRED || pv->pv_flags & PVF_UNMAN) {
2542 /* Cannot remove wired or unmanaged pages now. */
2543 npv = TAILQ_NEXT(pv, pv_plist);
2546 pmap->pm_stats.resident_count--;
2547 l2b = pmap_get_l2_bucket(pmap, pv->pv_va);
2548 KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages"));
2549 pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
2550 m = PHYS_TO_VM_PAGE(*pt & L2_S_FRAME);
2551 KASSERT((vm_offset_t)m >= KERNBASE, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt));
2554 npv = TAILQ_NEXT(pv, pv_plist);
2555 pmap_nuke_pv(m, pmap, pv);
2556 if (TAILQ_EMPTY(&m->md.pv_list))
2557 vm_page_aflag_clear(m, PGA_WRITEABLE);
2558 pmap_free_pv_entry(pv);
2559 pmap_free_l2_bucket(pmap, l2b, 1);
2561 rw_wunlock(&pvh_global_lock);
2568 /***************************************************
2569 * Low level mapping routines.....
2570 ***************************************************/
2572 #ifdef ARM_HAVE_SUPERSECTIONS
2573 /* Map a super section into the KVA. */
2576 pmap_kenter_supersection(vm_offset_t va, uint64_t pa, int flags)
2578 pd_entry_t pd = L1_S_PROTO | L1_S_SUPERSEC | (pa & L1_SUP_FRAME) |
2579 (((pa >> 32) & 0xf) << 20) | L1_S_PROT(PTE_KERNEL,
2580 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
2581 struct l1_ttable *l1;
2582 vm_offset_t va0, va_end;
2584 KASSERT(((va | pa) & L1_SUP_OFFSET) == 0,
2585 ("Not a valid super section mapping"));
2586 if (flags & SECTION_CACHE)
2587 pd |= pte_l1_s_cache_mode;
2588 else if (flags & SECTION_PT)
2589 pd |= pte_l1_s_cache_mode_pt;
2590 va0 = va & L1_SUP_FRAME;
2591 va_end = va + L1_SUP_SIZE;
2592 SLIST_FOREACH(l1, &l1_list, l1_link) {
2594 for (; va < va_end; va += L1_S_SIZE) {
2595 l1->l1_kva[L1_IDX(va)] = pd;
2596 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2602 /* Map a section into the KVA. */
2605 pmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags)
2607 pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL,
2608 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
2609 struct l1_ttable *l1;
2611 KASSERT(((va | pa) & L1_S_OFFSET) == 0,
2612 ("Not a valid section mapping"));
2613 if (flags & SECTION_CACHE)
2614 pd |= pte_l1_s_cache_mode;
2615 else if (flags & SECTION_PT)
2616 pd |= pte_l1_s_cache_mode_pt;
2617 SLIST_FOREACH(l1, &l1_list, l1_link) {
2618 l1->l1_kva[L1_IDX(va)] = pd;
2619 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2624 * Make a temporary mapping for a physical address. This is only intended
2625 * to be used for panic dumps.
2628 pmap_kenter_temporary(vm_paddr_t pa, int i)
2632 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
2633 pmap_kenter(va, pa);
2634 return ((void *)crashdumpmap);
2638 * add a wired page to the kva
2639 * note that in order for the mapping to take effect -- you
2640 * should do a invltlb after doing the pmap_kenter...
2642 static PMAP_INLINE void
2643 pmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags)
2645 struct l2_bucket *l2b;
2648 struct pv_entry *pve;
2651 PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n",
2652 (uint32_t) va, (uint32_t) pa));
2655 l2b = pmap_get_l2_bucket(kernel_pmap, va);
2657 l2b = pmap_grow_l2_bucket(kernel_pmap, va);
2658 KASSERT(l2b != NULL, ("No L2 Bucket"));
2659 pte = &l2b->l2b_kva[l2pte_index(va)];
2661 PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n",
2662 (uint32_t) pte, opte, *pte));
2663 if (l2pte_valid(opte)) {
2667 l2b->l2b_occupancy++;
2669 *pte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL,
2670 VM_PROT_READ | VM_PROT_WRITE);
2671 if (flags & KENTER_CACHE)
2672 *pte |= pte_l2_s_cache_mode;
2673 if (flags & KENTER_USER)
2674 *pte |= L2_S_PROT_U;
2678 * A kernel mapping may not be the page's only mapping, so create a PV
2679 * entry to ensure proper caching.
2681 * The existence test for the pvzone is used to delay the recording of
2682 * kernel mappings until the VM system is fully initialized.
2684 * This expects the physical memory to have a vm_page_array entry.
2686 if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa)) != NULL) {
2687 rw_wlock(&pvh_global_lock);
2688 if (!TAILQ_EMPTY(&m->md.pv_list) || m->md.pv_kva != 0) {
2689 if ((pve = pmap_get_pv_entry()) == NULL)
2690 panic("pmap_kenter_internal: no pv entries");
2691 PMAP_LOCK(kernel_pmap);
2692 pmap_enter_pv(m, pve, kernel_pmap, va,
2693 PVF_WRITE | PVF_UNMAN);
2694 pmap_fix_cache(m, kernel_pmap, va);
2695 PMAP_UNLOCK(kernel_pmap);
2699 rw_wunlock(&pvh_global_lock);
2704 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2706 pmap_kenter_internal(va, pa, KENTER_CACHE);
2710 pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa)
2713 pmap_kenter_internal(va, pa, 0);
2717 pmap_kenter_device(vm_offset_t va, vm_size_t size, vm_paddr_t pa)
2721 KASSERT((size & PAGE_MASK) == 0,
2722 ("%s: device mapping not page-sized", __func__));
2726 pmap_kenter_internal(va, pa, 0);
2734 pmap_kremove_device(vm_offset_t va, vm_size_t size)
2738 KASSERT((size & PAGE_MASK) == 0,
2739 ("%s: device mapping not page-sized", __func__));
2750 pmap_kenter_user(vm_offset_t va, vm_paddr_t pa)
2753 pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER);
2755 * Call pmap_fault_fixup now, to make sure we'll have no exception
2756 * at the first use of the new address, or bad things will happen,
2757 * as we use one of these addresses in the exception handlers.
2759 pmap_fault_fixup(kernel_pmap, va, VM_PROT_READ|VM_PROT_WRITE, 1);
2763 pmap_kextract(vm_offset_t va)
2766 return (pmap_extract_locked(kernel_pmap, va));
2770 * remove a page from the kernel pagetables
2773 pmap_kremove(vm_offset_t va)
2775 struct l2_bucket *l2b;
2776 pt_entry_t *pte, opte;
2777 struct pv_entry *pve;
2781 l2b = pmap_get_l2_bucket(kernel_pmap, va);
2784 KASSERT(l2b != NULL, ("No L2 Bucket"));
2785 pte = &l2b->l2b_kva[l2pte_index(va)];
2787 if (l2pte_valid(opte)) {
2788 /* pa = vtophs(va) taken from pmap_extract() */
2789 if ((opte & L2_TYPE_MASK) == L2_TYPE_L)
2790 pa = (opte & L2_L_FRAME) | (va & L2_L_OFFSET);
2792 pa = (opte & L2_S_FRAME) | (va & L2_S_OFFSET);
2793 /* note: should never have to remove an allocation
2794 * before the pvzone is initialized.
2796 rw_wlock(&pvh_global_lock);
2797 PMAP_LOCK(kernel_pmap);
2798 if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa)) &&
2799 (pve = pmap_remove_pv(m, kernel_pmap, va)))
2800 pmap_free_pv_entry(pve);
2801 PMAP_UNLOCK(kernel_pmap);
2802 rw_wunlock(&pvh_global_lock);
2803 va = va & ~PAGE_MASK;
2804 cpu_dcache_wbinv_range(va, PAGE_SIZE);
2805 cpu_l2cache_wbinv_range(va, PAGE_SIZE);
2806 cpu_tlb_flushD_SE(va);
2814 * Used to map a range of physical addresses into kernel
2815 * virtual address space.
2817 * The value passed in '*virt' is a suggested virtual address for
2818 * the mapping. Architectures which can support a direct-mapped
2819 * physical to virtual region can return the appropriate address
2820 * within that region, leaving '*virt' unchanged. Other
2821 * architectures should map the pages starting at '*virt' and
2822 * update '*virt' with the first usable address after the mapped
2826 pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot)
2828 vm_offset_t sva = *virt;
2829 vm_offset_t va = sva;
2831 PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, "
2832 "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end,
2835 while (start < end) {
2836 pmap_kenter(va, start);
2845 pmap_wb_page(vm_page_t m)
2847 struct pv_entry *pv;
2849 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
2850 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, FALSE,
2851 (pv->pv_flags & PVF_WRITE) == 0);
2855 pmap_inv_page(vm_page_t m)
2857 struct pv_entry *pv;
2859 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
2860 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, TRUE, TRUE);
2863 * Add a list of wired pages to the kva
2864 * this routine is only used for temporary
2865 * kernel mappings that do not need to have
2866 * page modification or references recorded.
2867 * Note that old mappings are simply written
2868 * over. The page *must* be wired.
2871 pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
2875 for (i = 0; i < count; i++) {
2877 pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]),
2885 * this routine jerks page mappings from the
2886 * kernel -- it is meant only for temporary mappings.
2889 pmap_qremove(vm_offset_t va, int count)
2894 for (i = 0; i < count; i++) {
2897 pmap_inv_page(PHYS_TO_VM_PAGE(pa));
2906 * pmap_object_init_pt preloads the ptes for a given object
2907 * into the specified pmap. This eliminates the blast of soft
2908 * faults on process startup and immediately after an mmap.
2911 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
2912 vm_pindex_t pindex, vm_size_t size)
2915 VM_OBJECT_ASSERT_WLOCKED(object);
2916 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2917 ("pmap_object_init_pt: non-device object"));
2922 * pmap_is_prefaultable:
2924 * Return whether or not the specified virtual address is elgible
2928 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
2933 if (!pmap_get_pde_pte(pmap, addr, &pde, &pte))
2935 KASSERT(pte != NULL, ("Valid mapping but no pte ?"));
2942 * Fetch pointers to the PDE/PTE for the given pmap/VA pair.
2943 * Returns TRUE if the mapping exists, else FALSE.
2945 * NOTE: This function is only used by a couple of arm-specific modules.
2946 * It is not safe to take any pmap locks here, since we could be right
2947 * in the middle of debugging the pmap anyway...
2949 * It is possible for this routine to return FALSE even though a valid
2950 * mapping does exist. This is because we don't lock, so the metadata
2951 * state may be inconsistent.
2953 * NOTE: We can return a NULL *ptp in the case where the L1 pde is
2954 * a "section" mapping.
2957 pmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp)
2959 struct l2_dtable *l2;
2960 pd_entry_t *pl1pd, l1pd;
2964 if (pm->pm_l1 == NULL)
2968 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx];
2971 if (l1pte_section_p(l1pd)) {
2976 if (pm->pm_l2 == NULL)
2979 l2 = pm->pm_l2[L2_IDX(l1idx)];
2982 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
2986 *ptp = &ptep[l2pte_index(va)];
2991 * Routine: pmap_remove_all
2993 * Removes this physical page from
2994 * all physical maps in which it resides.
2995 * Reflects back modify bits to the pager.
2998 * Original versions of this routine were very
2999 * inefficient because they iteratively called
3000 * pmap_remove (slow...)
3003 pmap_remove_all(vm_page_t m)
3007 struct l2_bucket *l2b;
3008 boolean_t flush = FALSE;
3012 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3013 ("pmap_remove_all: page %p is not managed", m));
3014 if (TAILQ_EMPTY(&m->md.pv_list))
3016 rw_wlock(&pvh_global_lock);
3019 * XXX This call shouldn't exist. Iterating over the PV list twice,
3020 * once in pmap_clearbit() and again below, is both unnecessary and
3021 * inefficient. The below code should itself write back the cache
3022 * entry before it destroys the mapping.
3024 pmap_clearbit(m, PVF_WRITE);
3025 curpm = vmspace_pmap(curproc->p_vmspace);
3026 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3027 if (flush == FALSE && (pv->pv_pmap == curpm ||
3028 pv->pv_pmap == kernel_pmap))
3031 PMAP_LOCK(pv->pv_pmap);
3033 * Cached contents were written-back in pmap_clearbit(),
3034 * but we still have to invalidate the cache entry to make
3035 * sure stale data are not retrieved when another page will be
3036 * mapped under this virtual address.
3038 if (pmap_is_current(pv->pv_pmap)) {
3039 cpu_dcache_inv_range(pv->pv_va, PAGE_SIZE);
3040 if (pmap_has_valid_mapping(pv->pv_pmap, pv->pv_va))
3041 cpu_l2cache_inv_range(pv->pv_va, PAGE_SIZE);
3044 if (pv->pv_flags & PVF_UNMAN) {
3045 /* remove the pv entry, but do not remove the mapping
3046 * and remember this is a kernel mapped page
3048 m->md.pv_kva = pv->pv_va;
3050 /* remove the mapping and pv entry */
3051 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
3052 KASSERT(l2b != NULL, ("No l2 bucket"));
3053 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
3055 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
3056 pmap_free_l2_bucket(pv->pv_pmap, l2b, 1);
3057 pv->pv_pmap->pm_stats.resident_count--;
3058 flags |= pv->pv_flags;
3060 pmap_nuke_pv(m, pv->pv_pmap, pv);
3061 PMAP_UNLOCK(pv->pv_pmap);
3062 pmap_free_pv_entry(pv);
3066 if (PV_BEEN_EXECD(flags))
3067 pmap_tlb_flushID(curpm);
3069 pmap_tlb_flushD(curpm);
3071 vm_page_aflag_clear(m, PGA_WRITEABLE);
3072 rw_wunlock(&pvh_global_lock);
3077 * Set the physical protection on the
3078 * specified range of this map as requested.
3081 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3083 struct l2_bucket *l2b;
3084 pt_entry_t *ptep, pte;
3085 vm_offset_t next_bucket;
3089 CTR4(KTR_PMAP, "pmap_protect: pmap %p sva 0x%08x eva 0x%08x prot %x",
3090 pm, sva, eva, prot);
3092 if ((prot & VM_PROT_READ) == 0) {
3093 pmap_remove(pm, sva, eva);
3097 if (prot & VM_PROT_WRITE) {
3099 * If this is a read->write transition, just ignore it and let
3100 * vm_fault() take care of it later.
3105 rw_wlock(&pvh_global_lock);
3109 * OK, at this point, we know we're doing write-protect operation.
3110 * If the pmap is active, write-back the range.
3112 pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE);
3114 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1;
3118 next_bucket = L2_NEXT_BUCKET(sva);
3119 if (next_bucket > eva)
3122 l2b = pmap_get_l2_bucket(pm, sva);
3128 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3130 while (sva < next_bucket) {
3131 if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) {
3135 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
3136 pte &= ~L2_S_PROT_W;
3140 if (!(pg->oflags & VPO_UNMANAGED)) {
3141 f = pmap_modify_pv(pg, pm, sva,
3152 if (PV_BEEN_EXECD(f))
3153 pmap_tlb_flushID_SE(pm, sva);
3155 if (PV_BEEN_REFD(f))
3156 pmap_tlb_flushD_SE(pm, sva);
3166 if (PV_BEEN_EXECD(flags))
3167 pmap_tlb_flushID(pm);
3169 if (PV_BEEN_REFD(flags))
3170 pmap_tlb_flushD(pm);
3172 rw_wunlock(&pvh_global_lock);
3179 * Insert the given physical page (p) at
3180 * the specified virtual address (v) in the
3181 * target physical map with the protection requested.
3183 * If specified, the page will be wired down, meaning
3184 * that the related pte can not be reclaimed.
3186 * NB: This is the only routine which MAY NOT lazy-evaluate
3187 * or lose information. That is, this routine must actually
3188 * insert this page into the given map NOW.
3192 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3193 u_int flags, int8_t psind __unused)
3197 rw_wlock(&pvh_global_lock);
3199 rv = pmap_enter_locked(pmap, va, m, prot, flags);
3200 rw_wunlock(&pvh_global_lock);
3206 * The pvh global and pmap locks must be held.
3209 pmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3212 struct l2_bucket *l2b = NULL;
3213 struct vm_page *opg;
3214 struct pv_entry *pve = NULL;
3215 pt_entry_t *ptep, npte, opte;
3220 PMAP_ASSERT_LOCKED(pmap);
3221 rw_assert(&pvh_global_lock, RA_WLOCKED);
3222 if (va == vector_page) {
3223 pa = systempage.pv_pa;
3226 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3227 VM_OBJECT_ASSERT_LOCKED(m->object);
3228 pa = VM_PAGE_TO_PHYS(m);
3231 if (prot & VM_PROT_WRITE)
3232 nflags |= PVF_WRITE;
3233 if (prot & VM_PROT_EXECUTE)
3235 if ((flags & PMAP_ENTER_WIRED) != 0)
3236 nflags |= PVF_WIRED;
3237 PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, "
3238 "flags = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, flags));
3240 if (pmap == kernel_pmap) {
3241 l2b = pmap_get_l2_bucket(pmap, va);
3243 l2b = pmap_grow_l2_bucket(pmap, va);
3246 l2b = pmap_alloc_l2_bucket(pmap, va);
3248 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
3250 rw_wunlock(&pvh_global_lock);
3252 rw_wlock(&pvh_global_lock);
3256 return (KERN_RESOURCE_SHORTAGE);
3260 ptep = &l2b->l2b_kva[l2pte_index(va)];
3267 * There is already a mapping at this address.
3268 * If the physical address is different, lookup the
3271 if (l2pte_pa(opte) != pa)
3272 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte));
3278 if ((prot & (VM_PROT_ALL)) ||
3279 (!m || m->md.pvh_attrs & PVF_REF)) {
3281 * - The access type indicates that we don't need
3282 * to do referenced emulation.
3284 * - The physical page has already been referenced
3285 * so no need to re-do referenced emulation here.
3291 if (m && ((prot & VM_PROT_WRITE) != 0 ||
3292 (m->md.pvh_attrs & PVF_MOD))) {
3294 * This is a writable mapping, and the
3295 * page's mod state indicates it has
3296 * already been modified. Make it
3297 * writable from the outset.
3300 if (!(m->md.pvh_attrs & PVF_MOD))
3304 vm_page_aflag_set(m, PGA_REFERENCED);
3307 * Need to do page referenced emulation.
3309 npte |= L2_TYPE_INV;
3312 if (prot & VM_PROT_WRITE) {
3313 npte |= L2_S_PROT_W;
3315 (m->oflags & VPO_UNMANAGED) == 0)
3316 vm_page_aflag_set(m, PGA_WRITEABLE);
3318 if (m->md.pv_memattr != VM_MEMATTR_UNCACHEABLE)
3319 npte |= pte_l2_s_cache_mode;
3320 if (m && m == opg) {
3322 * We're changing the attrs of an existing mapping.
3324 oflags = pmap_modify_pv(m, pmap, va,
3325 PVF_WRITE | PVF_EXEC | PVF_WIRED |
3326 PVF_MOD | PVF_REF, nflags);
3329 * We may need to flush the cache if we're
3332 if (pmap_is_current(pmap) &&
3333 (oflags & PVF_NC) == 0 &&
3334 (opte & L2_S_PROT_W) != 0 &&
3335 (prot & VM_PROT_WRITE) == 0 &&
3336 (opte & L2_TYPE_MASK) != L2_TYPE_INV) {
3337 cpu_dcache_wb_range(va, PAGE_SIZE);
3338 cpu_l2cache_wb_range(va, PAGE_SIZE);
3342 * New mapping, or changing the backing page
3343 * of an existing mapping.
3347 * Replacing an existing mapping with a new one.
3348 * It is part of our managed memory so we
3349 * must remove it from the PV list
3351 if ((pve = pmap_remove_pv(opg, pmap, va))) {
3353 /* note for patch: the oflags/invalidation was moved
3354 * because PG_FICTITIOUS pages could free the pve
3356 oflags = pve->pv_flags;
3358 * If the old mapping was valid (ref/mod
3359 * emulation creates 'invalid' mappings
3360 * initially) then make sure to frob
3363 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) {
3364 if (PV_BEEN_EXECD(oflags)) {
3365 pmap_idcache_wbinv_range(pmap, va,
3368 if (PV_BEEN_REFD(oflags)) {
3369 pmap_dcache_wb_range(pmap, va,
3371 (oflags & PVF_WRITE) == 0);
3375 /* free/allocate a pv_entry for UNMANAGED pages if
3376 * this physical page is not/is already mapped.
3379 if (m && (m->oflags & VPO_UNMANAGED) &&
3381 TAILQ_EMPTY(&m->md.pv_list)) {
3382 pmap_free_pv_entry(pve);
3386 (!(m->oflags & VPO_UNMANAGED) || m->md.pv_kva ||
3387 !TAILQ_EMPTY(&m->md.pv_list)))
3388 pve = pmap_get_pv_entry();
3390 (!(m->oflags & VPO_UNMANAGED) || m->md.pv_kva ||
3391 !TAILQ_EMPTY(&m->md.pv_list)))
3392 pve = pmap_get_pv_entry();
3395 if ((m->oflags & VPO_UNMANAGED)) {
3396 if (!TAILQ_EMPTY(&m->md.pv_list) ||
3398 KASSERT(pve != NULL, ("No pv"));
3399 nflags |= PVF_UNMAN;
3400 pmap_enter_pv(m, pve, pmap, va, nflags);
3404 KASSERT(va < kmi.clean_sva ||
3405 va >= kmi.clean_eva,
3406 ("pmap_enter: managed mapping within the clean submap"));
3407 KASSERT(pve != NULL, ("No pv"));
3408 pmap_enter_pv(m, pve, pmap, va, nflags);
3413 * Make sure userland mappings get the right permissions
3415 if (pmap != kernel_pmap && va != vector_page) {
3416 npte |= L2_S_PROT_U;
3420 * Keep the stats up to date
3423 l2b->l2b_occupancy++;
3424 pmap->pm_stats.resident_count++;
3428 * If this is just a wiring change, the two PTEs will be
3429 * identical, so there's no need to update the page table.
3432 boolean_t is_cached = pmap_is_current(pmap);
3437 * We only need to frob the cache/tlb if this pmap
3441 if (L1_IDX(va) != L1_IDX(vector_page) &&
3442 l2pte_valid(npte)) {
3444 * This mapping is likely to be accessed as
3445 * soon as we return to userland. Fix up the
3446 * L1 entry to avoid taking another
3447 * page/domain fault.
3449 pd_entry_t *pl1pd, l1pd;
3451 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
3452 l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) |
3454 if (*pl1pd != l1pd) {
3461 if (PV_BEEN_EXECD(oflags))
3462 pmap_tlb_flushID_SE(pmap, va);
3463 else if (PV_BEEN_REFD(oflags))
3464 pmap_tlb_flushD_SE(pmap, va);
3468 pmap_fix_cache(m, pmap, va);
3470 return (KERN_SUCCESS);
3474 * Maps a sequence of resident pages belonging to the same object.
3475 * The sequence begins with the given page m_start. This page is
3476 * mapped at the given virtual address start. Each subsequent page is
3477 * mapped at a virtual address that is offset from start by the same
3478 * amount as the page is offset from m_start within the object. The
3479 * last page in the sequence is the page with the largest offset from
3480 * m_start that can be mapped at a virtual address less than the given
3481 * virtual address end. Not every virtual page between start and end
3482 * is mapped; only those for which a resident page exists with the
3483 * corresponding offset from m_start are mapped.
3486 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3487 vm_page_t m_start, vm_prot_t prot)
3490 vm_pindex_t diff, psize;
3492 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3494 psize = atop(end - start);
3496 rw_wlock(&pvh_global_lock);
3498 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3499 pmap_enter_locked(pmap, start + ptoa(diff), m, prot &
3500 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP);
3501 m = TAILQ_NEXT(m, listq);
3503 rw_wunlock(&pvh_global_lock);
3508 * this code makes some *MAJOR* assumptions:
3509 * 1. Current pmap & pmap exists.
3512 * 4. No page table pages.
3513 * but is *MUCH* faster than pmap_enter...
3517 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3520 rw_wlock(&pvh_global_lock);
3522 pmap_enter_locked(pmap, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
3523 PMAP_ENTER_NOSLEEP);
3524 rw_wunlock(&pvh_global_lock);
3529 * Clear the wired attribute from the mappings for the specified range of
3530 * addresses in the given pmap. Every valid mapping within that range
3531 * must have the wired attribute set. In contrast, invalid mappings
3532 * cannot have the wired attribute set, so they are ignored.
3534 * XXX Wired mappings of unmanaged pages cannot be counted by this pmap
3538 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3540 struct l2_bucket *l2b;
3541 pt_entry_t *ptep, pte;
3543 vm_offset_t next_bucket;
3546 rw_wlock(&pvh_global_lock);
3549 next_bucket = L2_NEXT_BUCKET(sva);
3550 if (next_bucket > eva)
3552 l2b = pmap_get_l2_bucket(pmap, sva);
3557 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; sva < next_bucket;
3558 sva += PAGE_SIZE, ptep++) {
3559 if ((pte = *ptep) == 0 ||
3560 (m = PHYS_TO_VM_PAGE(l2pte_pa(pte))) == NULL ||
3561 (m->oflags & VPO_UNMANAGED) != 0)
3563 pv = pmap_find_pv(m, pmap, sva);
3564 if ((pv->pv_flags & PVF_WIRED) == 0)
3565 panic("pmap_unwire: pv %p isn't wired", pv);
3566 pv->pv_flags &= ~PVF_WIRED;
3567 pmap->pm_stats.wired_count--;
3570 rw_wunlock(&pvh_global_lock);
3576 * Copy the range specified by src_addr/len
3577 * from the source map to the range dst_addr/len
3578 * in the destination map.
3580 * This routine is only advisory and need not do anything.
3583 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
3584 vm_size_t len, vm_offset_t src_addr)
3590 * Routine: pmap_extract
3592 * Extract the physical page address associated
3593 * with the given map/virtual_address pair.
3596 pmap_extract(pmap_t pmap, vm_offset_t va)
3601 pa = pmap_extract_locked(pmap, va);
3607 pmap_extract_locked(pmap_t pmap, vm_offset_t va)
3609 struct l2_dtable *l2;
3611 pt_entry_t *ptep, pte;
3615 if (pmap != kernel_pmap)
3616 PMAP_ASSERT_LOCKED(pmap);
3618 l1pd = pmap->pm_l1->l1_kva[l1idx];
3619 if (l1pte_section_p(l1pd)) {
3621 * These should only happen for the kernel pmap.
3623 KASSERT(pmap == kernel_pmap, ("unexpected section"));
3624 /* XXX: what to do about the bits > 32 ? */
3625 if (l1pd & L1_S_SUPERSEC)
3626 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3628 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3631 * Note that we can't rely on the validity of the L1
3632 * descriptor as an indication that a mapping exists.
3633 * We have to look it up in the L2 dtable.
3635 l2 = pmap->pm_l2[L2_IDX(l1idx)];
3637 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL)
3639 pte = ptep[l2pte_index(va)];
3642 if ((pte & L2_TYPE_MASK) == L2_TYPE_L)
3643 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3645 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3651 * Atomically extract and hold the physical page with the given
3652 * pmap and virtual address pair if that mapping permits the given
3657 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3659 struct l2_dtable *l2;
3661 pt_entry_t *ptep, pte;
3662 vm_paddr_t pa, paddr;
3670 l1pd = pmap->pm_l1->l1_kva[l1idx];
3671 if (l1pte_section_p(l1pd)) {
3673 * These should only happen for kernel_pmap
3675 KASSERT(pmap == kernel_pmap, ("huh"));
3676 /* XXX: what to do about the bits > 32 ? */
3677 if (l1pd & L1_S_SUPERSEC)
3678 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3680 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3681 if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr))
3683 if (l1pd & L1_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3684 m = PHYS_TO_VM_PAGE(pa);
3690 * Note that we can't rely on the validity of the L1
3691 * descriptor as an indication that a mapping exists.
3692 * We have to look it up in the L2 dtable.
3694 l2 = pmap->pm_l2[L2_IDX(l1idx)];
3697 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3702 ptep = &ptep[l2pte_index(va)];
3709 if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3710 if ((pte & L2_TYPE_MASK) == L2_TYPE_L)
3711 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3713 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3714 if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr))
3716 m = PHYS_TO_VM_PAGE(pa);
3722 PA_UNLOCK_COND(paddr);
3727 pmap_dump_kextract(vm_offset_t va, pt2_entry_t *pte2p)
3729 struct l2_dtable *l2;
3731 pt_entry_t *ptep, pte;
3736 l1pd = kernel_pmap->pm_l1->l1_kva[l1idx];
3737 if (l1pte_section_p(l1pd)) {
3738 if (l1pd & L1_S_SUPERSEC)
3739 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3741 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3742 pte = L2_S_PROTO | pa |
3743 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE);
3745 l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)];
3747 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3752 pte = ptep[l2pte_index(va)];
3757 if ((pte & L2_TYPE_MASK) == L2_TYPE_L)
3758 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3760 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3769 * Initialize a preallocated and zeroed pmap structure,
3770 * such as one in a vmspace structure.
3774 pmap_pinit(pmap_t pmap)
3776 PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap));
3778 pmap_alloc_l1(pmap);
3779 bzero(pmap->pm_l2, sizeof(pmap->pm_l2));
3781 CPU_ZERO(&pmap->pm_active);
3783 TAILQ_INIT(&pmap->pm_pvlist);
3784 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3785 pmap->pm_stats.resident_count = 1;
3786 if (vector_page < KERNBASE) {
3787 pmap_enter(pmap, vector_page, PHYS_TO_VM_PAGE(systempage.pv_pa),
3788 VM_PROT_READ, PMAP_ENTER_WIRED | VM_PROT_READ, 0);
3794 /***************************************************
3795 * page management routines.
3796 ***************************************************/
3800 pmap_free_pv_entry(pv_entry_t pv)
3803 uma_zfree(pvzone, pv);
3808 * get a new pv_entry, allocating a block from the system
3810 * the memory allocation is performed bypassing the malloc code
3811 * because of the possibility of allocations at interrupt time.
3814 pmap_get_pv_entry(void)
3816 pv_entry_t ret_value;
3819 if (pv_entry_count > pv_entry_high_water)
3820 pagedaemon_wakeup(0); /* XXX ARM NUMA */
3821 ret_value = uma_zalloc(pvzone, M_NOWAIT);
3826 * Remove the given range of addresses from the specified map.
3828 * It is assumed that the start and end are properly
3829 * rounded to the page size.
3831 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3
3833 pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva)
3835 struct l2_bucket *l2b;
3836 vm_offset_t next_bucket;
3839 u_int mappings, is_exec, is_refd;
3844 * we lock in the pmap => pv_head direction
3847 rw_wlock(&pvh_global_lock);
3852 * Do one L2 bucket's worth at a time.
3854 next_bucket = L2_NEXT_BUCKET(sva);
3855 if (next_bucket > eva)
3858 l2b = pmap_get_l2_bucket(pm, sva);
3864 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3867 while (sva < next_bucket) {
3876 * Nothing here, move along
3883 pm->pm_stats.resident_count--;
3889 * Update flags. In a number of circumstances,
3890 * we could cluster a lot of these and do a
3891 * number of sequential pages in one go.
3893 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) {
3894 struct pv_entry *pve;
3896 pve = pmap_remove_pv(pg, pm, sva);
3898 is_exec = PV_BEEN_EXECD(pve->pv_flags);
3899 is_refd = PV_BEEN_REFD(pve->pv_flags);
3900 pmap_free_pv_entry(pve);
3904 if (l2pte_valid(pte) && pmap_is_current(pm)) {
3905 if (total < PMAP_REMOVE_CLEAN_LIST_SIZE) {
3908 cpu_idcache_wbinv_range(sva,
3910 cpu_l2cache_wbinv_range(sva,
3912 cpu_tlb_flushID_SE(sva);
3913 } else if (is_refd) {
3914 cpu_dcache_wbinv_range(sva,
3916 cpu_l2cache_wbinv_range(sva,
3918 cpu_tlb_flushD_SE(sva);
3920 } else if (total == PMAP_REMOVE_CLEAN_LIST_SIZE) {
3921 /* flushall will also only get set for
3922 * for a current pmap
3924 cpu_idcache_wbinv_all();
3925 cpu_l2cache_wbinv_all();
3938 pmap_free_l2_bucket(pm, l2b, mappings);
3941 rw_wunlock(&pvh_global_lock);
3950 * Zero a given physical page by mapping it at a page hook point.
3951 * In doing the zero page op, the page we zero is mapped cachable, as with
3952 * StrongARM accesses to non-cached pages are non-burst making writing
3953 * _any_ bulk data very slow.
3955 #if ARM_MMU_GENERIC != 0 || defined(CPU_XSCALE_CORE3)
3957 pmap_zero_page_generic(vm_paddr_t phys, int off, int size)
3960 if (_arm_bzero && size >= _min_bzero_size &&
3961 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0)
3966 * Hook in the page, zero it, invalidate the TLB as needed.
3968 * Note the temporary zero-page mapping must be a non-cached page in
3969 * order to work without corruption when write-allocate is enabled.
3971 *cdst_pte = L2_S_PROTO | phys | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE);
3973 cpu_tlb_flushD_SE(cdstp);
3975 if (off || size != PAGE_SIZE)
3976 bzero((void *)(cdstp + off), size);
3982 #endif /* ARM_MMU_GENERIC != 0 */
3984 #if ARM_MMU_XSCALE == 1
3986 pmap_zero_page_xscale(vm_paddr_t phys, int off, int size)
3989 if (_arm_bzero && size >= _min_bzero_size &&
3990 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0)
3995 * Hook in the page, zero it, and purge the cache for that
3996 * zeroed page. Invalidate the TLB as needed.
3998 *cdst_pte = L2_S_PROTO | phys |
3999 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4000 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4002 cpu_tlb_flushD_SE(cdstp);
4004 if (off || size != PAGE_SIZE)
4005 bzero((void *)(cdstp + off), size);
4009 xscale_cache_clean_minidata();
4013 * Change the PTEs for the specified kernel mappings such that they
4014 * will use the mini data cache instead of the main data cache.
4017 pmap_use_minicache(vm_offset_t va, vm_size_t size)
4019 struct l2_bucket *l2b;
4020 pt_entry_t *ptep, *sptep, pte;
4021 vm_offset_t next_bucket, eva;
4023 #if (ARM_NMMUS > 1) || defined(CPU_XSCALE_CORE3)
4024 if (xscale_use_minidata == 0)
4031 next_bucket = L2_NEXT_BUCKET(va);
4032 if (next_bucket > eva)
4035 l2b = pmap_get_l2_bucket(kernel_pmap, va);
4037 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)];
4039 while (va < next_bucket) {
4041 if (!l2pte_minidata(pte)) {
4042 cpu_dcache_wbinv_range(va, PAGE_SIZE);
4043 cpu_tlb_flushD_SE(va);
4044 *ptep = pte & ~L2_B;
4049 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep));
4053 #endif /* ARM_MMU_XSCALE == 1 */
4056 * pmap_zero_page zeros the specified hardware page by mapping
4057 * the page into KVM and using bzero to clear its contents.
4060 pmap_zero_page(vm_page_t m)
4062 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), 0, PAGE_SIZE);
4067 * pmap_zero_page_area zeros the specified hardware page by mapping
4068 * the page into KVM and using bzero to clear its contents.
4070 * off and size may not cover an area beyond a single hardware page.
4073 pmap_zero_page_area(vm_page_t m, int off, int size)
4076 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), off, size);
4084 * This is a local function used to work out the best strategy to clean
4085 * a single page referenced by its entry in the PV table. It should be used by
4086 * pmap_copy_page, pmap_zero page and maybe some others later on.
4088 * Its policy is effectively:
4089 * o If there are no mappings, we don't bother doing anything with the cache.
4090 * o If there is one mapping, we clean just that page.
4091 * o If there are multiple mappings, we clean the entire cache.
4093 * So that some functions can be further optimised, it returns 0 if it didn't
4094 * clean the entire cache, or 1 if it did.
4096 * XXX One bug in this routine is that if the pv_entry has a single page
4097 * mapped at 0x00000000 a whole cache clean will be performed rather than
4098 * just the 1 page. Since this should not occur in everyday use and if it does
4099 * it will just result in not the most efficient clean for the page.
4101 * We don't yet use this function but may want to.
4104 pmap_clean_page(struct pv_entry *pv, boolean_t is_src)
4106 pmap_t pm, pm_to_clean = NULL;
4107 struct pv_entry *npv;
4108 u_int cache_needs_cleaning = 0;
4110 vm_offset_t page_to_clean = 0;
4113 /* nothing mapped in so nothing to flush */
4118 * Since we flush the cache each time we change to a different
4119 * user vmspace, we only need to flush the page if it is in the
4123 pm = vmspace_pmap(curproc->p_vmspace);
4127 for (npv = pv; npv; npv = TAILQ_NEXT(npv, pv_list)) {
4128 if (npv->pv_pmap == kernel_pmap || npv->pv_pmap == pm) {
4129 flags |= npv->pv_flags;
4131 * The page is mapped non-cacheable in
4132 * this map. No need to flush the cache.
4134 if (npv->pv_flags & PVF_NC) {
4136 if (cache_needs_cleaning)
4137 panic("pmap_clean_page: "
4138 "cache inconsistency");
4141 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0)
4143 if (cache_needs_cleaning) {
4147 page_to_clean = npv->pv_va;
4148 pm_to_clean = npv->pv_pmap;
4150 cache_needs_cleaning = 1;
4153 if (page_to_clean) {
4154 if (PV_BEEN_EXECD(flags))
4155 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean,
4158 pmap_dcache_wb_range(pm_to_clean, page_to_clean,
4159 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0);
4160 } else if (cache_needs_cleaning) {
4161 if (PV_BEEN_EXECD(flags))
4162 pmap_idcache_wbinv_all(pm);
4164 pmap_dcache_wbinv_all(pm);
4172 * pmap_copy_page copies the specified (machine independent)
4173 * page by mapping the page into virtual memory and using
4174 * bcopy to copy the page, one machine dependent page at a
4181 * Copy one physical page into another, by mapping the pages into
4182 * hook points. The same comment regarding cachability as in
4183 * pmap_zero_page also applies here.
4185 #if ARM_MMU_GENERIC != 0 || defined (CPU_XSCALE_CORE3)
4187 pmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst)
4190 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4194 * Clean the source page. Hold the source page's lock for
4195 * the duration of the copy so that no other mappings can
4196 * be created while we have a potentially aliased mapping.
4200 * XXX: Not needed while we call cpu_dcache_wbinv_all() in
4203 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4206 * Map the pages into the page hook points, copy them, and purge
4207 * the cache for the appropriate page. Invalidate the TLB
4211 *csrc_pte = L2_S_PROTO | src |
4212 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
4214 *cdst_pte = L2_S_PROTO | dst |
4215 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
4217 cpu_tlb_flushD_SE(csrcp);
4218 cpu_tlb_flushD_SE(cdstp);
4220 bcopy_page(csrcp, cdstp);
4222 cpu_dcache_inv_range(csrcp, PAGE_SIZE);
4223 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE);
4224 cpu_l2cache_inv_range(csrcp, PAGE_SIZE);
4225 cpu_l2cache_wbinv_range(cdstp, PAGE_SIZE);
4229 pmap_copy_page_offs_generic(vm_paddr_t a_phys, vm_offset_t a_offs,
4230 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt)
4234 *csrc_pte = L2_S_PROTO | a_phys |
4235 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
4237 *cdst_pte = L2_S_PROTO | b_phys |
4238 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
4240 cpu_tlb_flushD_SE(csrcp);
4241 cpu_tlb_flushD_SE(cdstp);
4243 bcopy((char *)csrcp + a_offs, (char *)cdstp + b_offs, cnt);
4245 cpu_dcache_inv_range(csrcp + a_offs, cnt);
4246 cpu_dcache_wbinv_range(cdstp + b_offs, cnt);
4247 cpu_l2cache_inv_range(csrcp + a_offs, cnt);
4248 cpu_l2cache_wbinv_range(cdstp + b_offs, cnt);
4250 #endif /* ARM_MMU_GENERIC != 0 */
4252 #if ARM_MMU_XSCALE == 1
4254 pmap_copy_page_xscale(vm_paddr_t src, vm_paddr_t dst)
4257 /* XXX: Only needed for pmap_clean_page(), which is commented out. */
4258 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4262 * Clean the source page. Hold the source page's lock for
4263 * the duration of the copy so that no other mappings can
4264 * be created while we have a potentially aliased mapping.
4268 * XXX: Not needed while we call cpu_dcache_wbinv_all() in
4271 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4274 * Map the pages into the page hook points, copy them, and purge
4275 * the cache for the appropriate page. Invalidate the TLB
4279 *csrc_pte = L2_S_PROTO | src |
4280 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
4281 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4283 *cdst_pte = L2_S_PROTO | dst |
4284 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4285 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4287 cpu_tlb_flushD_SE(csrcp);
4288 cpu_tlb_flushD_SE(cdstp);
4290 bcopy_page(csrcp, cdstp);
4292 xscale_cache_clean_minidata();
4296 pmap_copy_page_offs_xscale(vm_paddr_t a_phys, vm_offset_t a_offs,
4297 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt)
4301 *csrc_pte = L2_S_PROTO | a_phys |
4302 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
4303 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X);
4305 *cdst_pte = L2_S_PROTO | b_phys |
4306 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4307 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X);
4309 cpu_tlb_flushD_SE(csrcp);
4310 cpu_tlb_flushD_SE(cdstp);
4312 bcopy((char *)csrcp + a_offs, (char *)cdstp + b_offs, cnt);
4314 xscale_cache_clean_minidata();
4316 #endif /* ARM_MMU_XSCALE == 1 */
4319 pmap_copy_page(vm_page_t src, vm_page_t dst)
4322 cpu_dcache_wbinv_all();
4323 cpu_l2cache_wbinv_all();
4324 if (_arm_memcpy && PAGE_SIZE >= _min_memcpy_size &&
4325 _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst),
4326 (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0)
4328 pmap_copy_page_func(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst));
4332 * We have code to do unmapped I/O. However, it isn't quite right and
4333 * causes un-page-aligned I/O to devices to fail (most notably newfs
4334 * or fsck). We give up a little performance to not allow unmapped I/O
4335 * to gain stability.
4337 int unmapped_buf_allowed = 0;
4340 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4341 vm_offset_t b_offset, int xfersize)
4343 vm_page_t a_pg, b_pg;
4344 vm_offset_t a_pg_offset, b_pg_offset;
4347 cpu_dcache_wbinv_all();
4348 cpu_l2cache_wbinv_all();
4349 while (xfersize > 0) {
4350 a_pg = ma[a_offset >> PAGE_SHIFT];
4351 a_pg_offset = a_offset & PAGE_MASK;
4352 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4353 b_pg = mb[b_offset >> PAGE_SHIFT];
4354 b_pg_offset = b_offset & PAGE_MASK;
4355 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4356 pmap_copy_page_offs_func(VM_PAGE_TO_PHYS(a_pg), a_pg_offset,
4357 VM_PAGE_TO_PHYS(b_pg), b_pg_offset, cnt);
4365 pmap_quick_enter_page(vm_page_t m)
4368 * Don't bother with a PCPU pageframe, since we don't support
4369 * SMP for anything pre-armv7. Use pmap_kenter() to ensure
4370 * caching is handled correctly for multiple mappings of the
4371 * same physical page.
4374 mtx_assert(&qmap_mtx, MA_NOTOWNED);
4375 mtx_lock(&qmap_mtx);
4377 pmap_kenter(qmap_addr, VM_PAGE_TO_PHYS(m));
4383 pmap_quick_remove_page(vm_offset_t addr)
4385 KASSERT(addr == qmap_addr,
4386 ("pmap_quick_remove_page: invalid address"));
4387 mtx_assert(&qmap_mtx, MA_OWNED);
4389 mtx_unlock(&qmap_mtx);
4393 * this routine returns true if a physical page resides
4394 * in the given pmap.
4397 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4403 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4404 ("pmap_page_exists_quick: page %p is not managed", m));
4406 rw_wlock(&pvh_global_lock);
4407 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4408 if (pv->pv_pmap == pmap) {
4416 rw_wunlock(&pvh_global_lock);
4421 * pmap_page_wired_mappings:
4423 * Return the number of managed mappings to the given physical page
4427 pmap_page_wired_mappings(vm_page_t m)
4433 if ((m->oflags & VPO_UNMANAGED) != 0)
4435 rw_wlock(&pvh_global_lock);
4436 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
4437 if ((pv->pv_flags & PVF_WIRED) != 0)
4439 rw_wunlock(&pvh_global_lock);
4444 * This function is advisory.
4447 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4452 * pmap_ts_referenced:
4454 * Return the count of reference bits for a page, clearing all of them.
4457 pmap_ts_referenced(vm_page_t m)
4460 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4461 ("pmap_ts_referenced: page %p is not managed", m));
4462 return (pmap_clearbit(m, PVF_REF));
4467 pmap_is_modified(vm_page_t m)
4470 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4471 ("pmap_is_modified: page %p is not managed", m));
4472 if (m->md.pvh_attrs & PVF_MOD)
4480 * Clear the modify bits on the specified physical page.
4483 pmap_clear_modify(vm_page_t m)
4486 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4487 ("pmap_clear_modify: page %p is not managed", m));
4488 VM_OBJECT_ASSERT_WLOCKED(m->object);
4489 KASSERT(!vm_page_xbusied(m),
4490 ("pmap_clear_modify: page %p is exclusive busied", m));
4493 * If the page is not PGA_WRITEABLE, then no mappings can be modified.
4494 * If the object containing the page is locked and the page is not
4495 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
4497 if ((m->aflags & PGA_WRITEABLE) == 0)
4499 if (m->md.pvh_attrs & PVF_MOD)
4500 pmap_clearbit(m, PVF_MOD);
4505 * pmap_is_referenced:
4507 * Return whether or not the specified physical page was referenced
4508 * in any physical maps.
4511 pmap_is_referenced(vm_page_t m)
4514 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4515 ("pmap_is_referenced: page %p is not managed", m));
4516 return ((m->md.pvh_attrs & PVF_REF) != 0);
4521 * Clear the write and modified bits in each of the given page's mappings.
4524 pmap_remove_write(vm_page_t m)
4527 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4528 ("pmap_remove_write: page %p is not managed", m));
4531 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4532 * set by another thread while the object is locked. Thus,
4533 * if PGA_WRITEABLE is clear, no page table entries need updating.
4535 VM_OBJECT_ASSERT_WLOCKED(m->object);
4536 if (vm_page_xbusied(m) || (m->aflags & PGA_WRITEABLE) != 0)
4537 pmap_clearbit(m, PVF_WRITE);
4542 * perform the pmap work for mincore
4545 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
4547 struct l2_bucket *l2b;
4548 pt_entry_t *ptep, pte;
4556 l2b = pmap_get_l2_bucket(pmap, addr);
4561 ptep = &l2b->l2b_kva[l2pte_index(addr)];
4563 if (!l2pte_valid(pte)) {
4567 val = MINCORE_INCORE;
4568 if (pte & L2_S_PROT_W)
4569 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4572 m = PHYS_TO_VM_PAGE(pa);
4573 if (m != NULL && !(m->oflags & VPO_UNMANAGED))
4577 * The ARM pmap tries to maintain a per-mapping
4578 * reference bit. The trouble is that it's kept in
4579 * the PV entry, not the PTE, so it's costly to access
4580 * here. You would need to acquire the pvh global
4581 * lock, call pmap_find_pv(), and introduce a custom
4582 * version of vm_page_pa_tryrelock() that releases and
4583 * reacquires the pvh global lock. In the end, I
4584 * doubt it's worthwhile. This may falsely report
4585 * the given address as referenced.
4587 if ((m->md.pvh_attrs & PVF_REF) != 0)
4588 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4590 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
4591 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
4592 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
4593 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
4597 PA_UNLOCK_COND(*locked_pa);
4604 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
4610 * Increase the starting virtual address of the given mapping if a
4611 * different alignment might result in more superpage mappings.
4614 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
4615 vm_offset_t *addr, vm_size_t size)
4619 #define BOOTSTRAP_DEBUG
4624 * Create a single section mapping.
4627 pmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4628 int prot, int cache)
4630 pd_entry_t *pde = (pd_entry_t *) l1pt;
4633 KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2"));
4642 fl = pte_l1_s_cache_mode;
4646 fl = pte_l1_s_cache_mode_pt;
4650 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4651 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL);
4652 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4659 * Link the L2 page table specified by l2pv.pv_pa into the L1
4660 * page table at the slot for "va".
4663 pmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv)
4665 pd_entry_t *pde = (pd_entry_t *) l1pt, proto;
4666 u_int slot = va >> L1_S_SHIFT;
4668 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO;
4670 #ifdef VERBOSE_INIT_ARM
4671 printf("pmap_link_l2pt: pa=0x%x va=0x%x\n", l2pv->pv_pa, l2pv->pv_va);
4674 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000);
4676 PTE_SYNC(&pde[slot]);
4678 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list);
4686 * Create a single page mapping.
4689 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot,
4692 pd_entry_t *pde = (pd_entry_t *) l1pt;
4696 KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin"));
4705 fl = pte_l2_s_cache_mode;
4709 fl = pte_l2_s_cache_mode_pt;
4713 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4714 panic("pmap_map_entry: no L2 table for VA 0x%08x", va);
4716 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4719 panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va);
4721 pte[l2pte_index(va)] =
4722 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl;
4723 PTE_SYNC(&pte[l2pte_index(va)]);
4729 * Map a chunk of memory using the most efficient mappings
4730 * possible (section. large page, small page) into the
4731 * provided L1 and L2 tables at the specified virtual address.
4734 pmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4735 vm_size_t size, int prot, int cache)
4737 pd_entry_t *pde = (pd_entry_t *) l1pt;
4738 pt_entry_t *pte, f1, f2s, f2l;
4742 resid = roundup2(size, PAGE_SIZE);
4745 panic("pmap_map_chunk: no L1 table provided");
4747 #ifdef VERBOSE_INIT_ARM
4748 printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x "
4749 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache);
4761 f1 = pte_l1_s_cache_mode;
4762 f2l = pte_l2_l_cache_mode;
4763 f2s = pte_l2_s_cache_mode;
4767 f1 = pte_l1_s_cache_mode_pt;
4768 f2l = pte_l2_l_cache_mode_pt;
4769 f2s = pte_l2_s_cache_mode_pt;
4776 /* See if we can use a section mapping. */
4777 if (L1_S_MAPPABLE_P(va, pa, resid)) {
4778 #ifdef VERBOSE_INIT_ARM
4781 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4782 L1_S_PROT(PTE_KERNEL, prot) | f1 |
4783 L1_S_DOM(PMAP_DOMAIN_KERNEL);
4784 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4792 * Ok, we're going to use an L2 table. Make sure
4793 * one is actually in the corresponding L1 slot
4794 * for the current VA.
4796 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4797 panic("pmap_map_chunk: no L2 table for VA 0x%08x", va);
4799 pte = (pt_entry_t *) kernel_pt_lookup(
4800 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4802 panic("pmap_map_chunk: can't find L2 table for VA"
4804 /* See if we can use a L2 large page mapping. */
4805 if (L2_L_MAPPABLE_P(va, pa, resid)) {
4806 #ifdef VERBOSE_INIT_ARM
4809 for (i = 0; i < 16; i++) {
4810 pte[l2pte_index(va) + i] =
4812 L2_L_PROT(PTE_KERNEL, prot) | f2l;
4813 PTE_SYNC(&pte[l2pte_index(va) + i]);
4821 /* Use a small page mapping. */
4822 #ifdef VERBOSE_INIT_ARM
4825 pte[l2pte_index(va)] =
4826 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s;
4827 PTE_SYNC(&pte[l2pte_index(va)]);
4832 #ifdef VERBOSE_INIT_ARM
4840 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
4843 * Remember the memattr in a field that gets used to set the appropriate
4844 * bits in the PTEs as mappings are established.
4846 m->md.pv_memattr = ma;
4849 * It appears that this function can only be called before any mappings
4850 * for the page are established on ARM. If this ever changes, this code
4851 * will need to walk the pv_list and make each of the existing mappings
4852 * uncacheable, being careful to sync caches and PTEs (and maybe
4853 * invalidate TLB?) for any current mapping it modifies.
4855 if (m->md.pv_kva != 0 || TAILQ_FIRST(&m->md.pv_list) != NULL)
4856 panic("Can't change memattr on page with existing mappings");