2 * SPDX-License-Identifier: BSD-3-Clause AND BSD-2-Clause
4 * Copyright (c) 1991 Regents of the University of California.
5 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
7 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
8 * Copyright (c) 2014-2016 Svatopluk Kraus <skra@FreeBSD.org>
9 * Copyright (c) 2014-2016 Michal Meloun <mmel@FreeBSD.org>
10 * All rights reserved.
12 * This code is derived from software contributed to Berkeley by
13 * the Systems Programming Group of the University of Utah Computer
14 * Science Department and William Jolitz of UUNET Technologies Inc.
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions
19 * 1. Redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution.
24 * 3. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
43 * Copyright (c) 2003 Networks Associates Technology, Inc.
44 * All rights reserved.
46 * This software was developed for the FreeBSD Project by Jake Burkholder,
47 * Safeport Network Services, and Network Associates Laboratories, the
48 * Security Research Division of Network Associates, Inc. under
49 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
50 * CHATS research program.
52 * Redistribution and use in source and binary forms, with or without
53 * modification, are permitted provided that the following conditions
55 * 1. Redistributions of source code must retain the above copyright
56 * notice, this list of conditions and the following disclaimer.
57 * 2. Redistributions in binary form must reproduce the above copyright
58 * notice, this list of conditions and the following disclaimer in the
59 * documentation and/or other materials provided with the distribution.
61 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
62 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
64 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
74 #include <sys/cdefs.h>
75 __FBSDID("$FreeBSD$");
78 * Manages physical address maps.
80 * Since the information managed by this module is
81 * also stored by the logical address mapping module,
82 * this module may throw away valid virtual-to-physical
83 * mappings at almost any time. However, invalidations
84 * of virtual-to-physical mappings must be done as
87 * In order to cope with hardware architectures which
88 * make virtual-to-physical map invalidates expensive,
89 * this module may delay invalidate or reduced protection
90 * operations until such time as they are actually
91 * necessary. This module is given full information as
92 * to which processors are currently using which maps,
93 * and to when physical maps must be made correct.
100 #include <sys/param.h>
101 #include <sys/systm.h>
102 #include <sys/kernel.h>
104 #include <sys/lock.h>
105 #include <sys/proc.h>
106 #include <sys/rwlock.h>
107 #include <sys/malloc.h>
108 #include <sys/vmmeter.h>
109 #include <sys/malloc.h>
110 #include <sys/mman.h>
111 #include <sys/sf_buf.h>
113 #include <sys/sched.h>
114 #include <sys/sysctl.h>
123 #include <vm/vm_param.h>
124 #include <vm/vm_kern.h>
125 #include <vm/vm_object.h>
126 #include <vm/vm_map.h>
127 #include <vm/vm_page.h>
128 #include <vm/vm_pageout.h>
129 #include <vm/vm_phys.h>
130 #include <vm/vm_extern.h>
131 #include <vm/vm_reserv.h>
132 #include <sys/lock.h>
133 #include <sys/mutex.h>
135 #include <machine/md_var.h>
136 #include <machine/pmap_var.h>
137 #include <machine/cpu.h>
138 #include <machine/pcb.h>
139 #include <machine/sf_buf.h>
141 #include <machine/smp.h>
143 #ifndef PMAP_SHPGPERPROC
144 #define PMAP_SHPGPERPROC 200
148 #define PMAP_INLINE __inline
154 static void pmap_zero_page_check(vm_page_t m);
155 void pmap_debug(int level);
156 int pmap_pid_dump(int pid);
158 #define PDEBUG(_lev_,_stat_) \
159 if (pmap_debug_level >= (_lev_)) \
161 #define dprintf printf
162 int pmap_debug_level = 1;
163 #else /* PMAP_DEBUG */
164 #define PDEBUG(_lev_,_stat_) /* Nothing */
165 #define dprintf(x, arg...)
166 #endif /* PMAP_DEBUG */
169 * Level 2 page tables map definion ('max' is excluded).
172 #define PT2V_MIN_ADDRESS ((vm_offset_t)PT2MAP)
173 #define PT2V_MAX_ADDRESS ((vm_offset_t)PT2MAP + PT2MAP_SIZE)
175 #define UPT2V_MIN_ADDRESS ((vm_offset_t)PT2MAP)
176 #define UPT2V_MAX_ADDRESS \
177 ((vm_offset_t)(PT2MAP + (KERNBASE >> PT2MAP_SHIFT)))
180 * Promotion to a 1MB (PTE1) page mapping requires that the corresponding
181 * 4KB (PTE2) page mappings have identical settings for the following fields:
183 #define PTE2_PROMOTE (PTE2_V | PTE2_A | PTE2_NM | PTE2_S | PTE2_NG | \
184 PTE2_NX | PTE2_RO | PTE2_U | PTE2_W | \
187 #define PTE1_PROMOTE (PTE1_V | PTE1_A | PTE1_NM | PTE1_S | PTE1_NG | \
188 PTE1_NX | PTE1_RO | PTE1_U | PTE1_W | \
191 #define ATTR_TO_L1(l2_attr) ((((l2_attr) & L2_TEX0) ? L1_S_TEX0 : 0) | \
192 (((l2_attr) & L2_C) ? L1_S_C : 0) | \
193 (((l2_attr) & L2_B) ? L1_S_B : 0) | \
194 (((l2_attr) & PTE2_A) ? PTE1_A : 0) | \
195 (((l2_attr) & PTE2_NM) ? PTE1_NM : 0) | \
196 (((l2_attr) & PTE2_S) ? PTE1_S : 0) | \
197 (((l2_attr) & PTE2_NG) ? PTE1_NG : 0) | \
198 (((l2_attr) & PTE2_NX) ? PTE1_NX : 0) | \
199 (((l2_attr) & PTE2_RO) ? PTE1_RO : 0) | \
200 (((l2_attr) & PTE2_U) ? PTE1_U : 0) | \
201 (((l2_attr) & PTE2_W) ? PTE1_W : 0))
203 #define ATTR_TO_L2(l1_attr) ((((l1_attr) & L1_S_TEX0) ? L2_TEX0 : 0) | \
204 (((l1_attr) & L1_S_C) ? L2_C : 0) | \
205 (((l1_attr) & L1_S_B) ? L2_B : 0) | \
206 (((l1_attr) & PTE1_A) ? PTE2_A : 0) | \
207 (((l1_attr) & PTE1_NM) ? PTE2_NM : 0) | \
208 (((l1_attr) & PTE1_S) ? PTE2_S : 0) | \
209 (((l1_attr) & PTE1_NG) ? PTE2_NG : 0) | \
210 (((l1_attr) & PTE1_NX) ? PTE2_NX : 0) | \
211 (((l1_attr) & PTE1_RO) ? PTE2_RO : 0) | \
212 (((l1_attr) & PTE1_U) ? PTE2_U : 0) | \
213 (((l1_attr) & PTE1_W) ? PTE2_W : 0))
216 * PTE2 descriptors creation macros.
218 #define PTE2_ATTR_DEFAULT vm_memattr_to_pte2(VM_MEMATTR_DEFAULT)
219 #define PTE2_ATTR_PT vm_memattr_to_pte2(pt_memattr)
221 #define PTE2_KPT(pa) PTE2_KERN(pa, PTE2_AP_KRW, PTE2_ATTR_PT)
222 #define PTE2_KPT_NG(pa) PTE2_KERN_NG(pa, PTE2_AP_KRW, PTE2_ATTR_PT)
224 #define PTE2_KRW(pa) PTE2_KERN(pa, PTE2_AP_KRW, PTE2_ATTR_DEFAULT)
225 #define PTE2_KRO(pa) PTE2_KERN(pa, PTE2_AP_KR, PTE2_ATTR_DEFAULT)
229 #define PV_STAT(x) do { x ; } while (0)
231 #define PV_STAT(x) do { } while (0)
235 * The boot_pt1 is used temporary in very early boot stage as L1 page table.
236 * We can init many things with no memory allocation thanks to its static
237 * allocation and this brings two main advantages:
238 * (1) other cores can be started very simply,
239 * (2) various boot loaders can be supported as its arguments can be processed
240 * in virtual address space and can be moved to safe location before
241 * first allocation happened.
242 * Only disadvantage is that boot_pt1 is used only in very early boot stage.
243 * However, the table is uninitialized and so lays in bss. Therefore kernel
244 * image size is not influenced.
246 * QQQ: In the future, maybe, boot_pt1 can be used for soft reset and
247 * CPU suspend/resume game.
249 extern pt1_entry_t boot_pt1[];
252 pt1_entry_t *kern_pt1;
253 pt2_entry_t *kern_pt2tab;
256 static uint32_t ttb_flags;
257 static vm_memattr_t pt_memattr;
258 ttb_entry_t pmap_kern_ttb;
260 struct pmap kernel_pmap_store;
261 LIST_HEAD(pmaplist, pmap);
262 static struct pmaplist allpmaps;
263 static struct mtx allpmaps_lock;
265 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
266 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
268 static vm_offset_t kernel_vm_end_new;
269 vm_offset_t kernel_vm_end = KERNBASE + NKPT2PG * NPT2_IN_PG * PTE1_SIZE;
270 vm_offset_t vm_max_kernel_address;
271 vm_paddr_t kernel_l1pa;
273 static struct rwlock __aligned(CACHE_LINE_SIZE) pvh_global_lock;
276 * Data for the pv entry allocation mechanism
278 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
279 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
280 static struct md_page *pv_table; /* XXX: Is it used only the list in md_page? */
281 static int shpgperproc = PMAP_SHPGPERPROC;
283 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
284 int pv_maxchunks; /* How many chunks we have KVA for */
285 vm_offset_t pv_vafree; /* freelist stored in the PTE */
287 vm_paddr_t first_managed_pa;
288 #define pa_to_pvh(pa) (&pv_table[pte1_index(pa - first_managed_pa)])
291 * All those kernel PT submaps that BSD is so fond of
298 static caddr_t crashdumpmap;
300 static pt2_entry_t *PMAP1 = NULL, *PMAP2;
301 static pt2_entry_t *PADDR1 = NULL, *PADDR2;
303 static pt2_entry_t *PMAP3;
304 static pt2_entry_t *PADDR3;
305 static int PMAP3cpu __unused; /* for SMP only */
309 static int PMAP1changedcpu;
310 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
312 "Number of times pmap_pte2_quick changed CPU with same PMAP1");
314 static int PMAP1changed;
315 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
317 "Number of times pmap_pte2_quick changed PMAP1");
318 static int PMAP1unchanged;
319 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
321 "Number of times pmap_pte2_quick didn't change PMAP1");
322 static struct mtx PMAP2mutex;
325 * Internal flags for pmap_enter()'s helper functions.
327 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
328 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
330 static __inline void pt2_wirecount_init(vm_page_t m);
331 static boolean_t pmap_demote_pte1(pmap_t pmap, pt1_entry_t *pte1p,
333 static int pmap_enter_pte1(pmap_t pmap, vm_offset_t va, pt1_entry_t pte1,
334 u_int flags, vm_page_t m);
335 void cache_icache_sync_fresh(vm_offset_t va, vm_paddr_t pa, vm_size_t size);
338 * Function to set the debug level of the pmap code.
342 pmap_debug(int level)
345 pmap_debug_level = level;
346 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
348 #endif /* PMAP_DEBUG */
351 * This table must corespond with memory attribute configuration in vm.h.
352 * First entry is used for normal system mapping.
354 * Device memory is always marked as shared.
355 * Normal memory is shared only in SMP .
356 * Not outer shareable bits are not used yet.
357 * Class 6 cannot be used on ARM11.
359 #define TEXDEF_TYPE_SHIFT 0
360 #define TEXDEF_TYPE_MASK 0x3
361 #define TEXDEF_INNER_SHIFT 2
362 #define TEXDEF_INNER_MASK 0x3
363 #define TEXDEF_OUTER_SHIFT 4
364 #define TEXDEF_OUTER_MASK 0x3
365 #define TEXDEF_NOS_SHIFT 6
366 #define TEXDEF_NOS_MASK 0x1
368 #define TEX(t, i, o, s) \
369 ((t) << TEXDEF_TYPE_SHIFT) | \
370 ((i) << TEXDEF_INNER_SHIFT) | \
371 ((o) << TEXDEF_OUTER_SHIFT | \
372 ((s) << TEXDEF_NOS_SHIFT))
374 static uint32_t tex_class[8] = {
375 /* type inner cache outer cache */
376 TEX(PRRR_MEM, NMRR_WB_WA, NMRR_WB_WA, 0), /* 0 - ATTR_WB_WA */
377 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 1 - ATTR_NOCACHE */
378 TEX(PRRR_DEV, NMRR_NC, NMRR_NC, 0), /* 2 - ATTR_DEVICE */
379 TEX(PRRR_SO, NMRR_NC, NMRR_NC, 0), /* 3 - ATTR_SO */
380 TEX(PRRR_MEM, NMRR_WT, NMRR_WT, 0), /* 4 - ATTR_WT */
381 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 5 - NOT USED YET */
382 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 6 - NOT USED YET */
383 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 7 - NOT USED YET */
387 static uint32_t pte2_attr_tab[8] = {
388 PTE2_ATTR_WB_WA, /* 0 - VM_MEMATTR_WB_WA */
389 PTE2_ATTR_NOCACHE, /* 1 - VM_MEMATTR_NOCACHE */
390 PTE2_ATTR_DEVICE, /* 2 - VM_MEMATTR_DEVICE */
391 PTE2_ATTR_SO, /* 3 - VM_MEMATTR_SO */
392 PTE2_ATTR_WT, /* 4 - VM_MEMATTR_WRITE_THROUGH */
393 0, /* 5 - NOT USED YET */
394 0, /* 6 - NOT USED YET */
395 0 /* 7 - NOT USED YET */
397 CTASSERT(VM_MEMATTR_WB_WA == 0);
398 CTASSERT(VM_MEMATTR_NOCACHE == 1);
399 CTASSERT(VM_MEMATTR_DEVICE == 2);
400 CTASSERT(VM_MEMATTR_SO == 3);
401 CTASSERT(VM_MEMATTR_WRITE_THROUGH == 4);
402 #define VM_MEMATTR_END (VM_MEMATTR_WRITE_THROUGH + 1)
405 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
408 return (mode >= 0 && mode < VM_MEMATTR_END);
411 static inline uint32_t
412 vm_memattr_to_pte2(vm_memattr_t ma)
415 KASSERT((u_int)ma < VM_MEMATTR_END,
416 ("%s: bad vm_memattr_t %d", __func__, ma));
417 return (pte2_attr_tab[(u_int)ma]);
420 static inline uint32_t
421 vm_page_pte2_attr(vm_page_t m)
424 return (vm_memattr_to_pte2(m->md.pat_mode));
428 * Convert TEX definition entry to TTB flags.
431 encode_ttb_flags(int idx)
433 uint32_t inner, outer, nos, reg;
435 inner = (tex_class[idx] >> TEXDEF_INNER_SHIFT) &
437 outer = (tex_class[idx] >> TEXDEF_OUTER_SHIFT) &
439 nos = (tex_class[idx] >> TEXDEF_NOS_SHIFT) &
444 if (cpuinfo.coherent_walk)
445 reg |= (inner & 0x1) << 6;
446 reg |= (inner & 0x2) >> 1;
456 * Set TEX remapping registers in current CPU.
462 uint32_t type, inner, outer, nos;
465 #ifdef PMAP_PTE_NOCACHE
467 if (cpuinfo.coherent_walk) {
468 pt_memattr = VM_MEMATTR_WB_WA;
469 ttb_flags = encode_ttb_flags(0);
472 pt_memattr = VM_MEMATTR_NOCACHE;
473 ttb_flags = encode_ttb_flags(1);
476 pt_memattr = VM_MEMATTR_WB_WA;
477 ttb_flags = encode_ttb_flags(0);
483 /* Build remapping register from TEX classes. */
484 for (i = 0; i < 8; i++) {
485 type = (tex_class[i] >> TEXDEF_TYPE_SHIFT) &
487 inner = (tex_class[i] >> TEXDEF_INNER_SHIFT) &
489 outer = (tex_class[i] >> TEXDEF_OUTER_SHIFT) &
491 nos = (tex_class[i] >> TEXDEF_NOS_SHIFT) &
494 prrr |= type << (i * 2);
495 prrr |= nos << (i + 24);
496 nmrr |= inner << (i * 2);
497 nmrr |= outer << (i * 2 + 16);
499 /* Add shareable bits for device memory. */
500 prrr |= PRRR_DS0 | PRRR_DS1;
502 /* Add shareable bits for normal memory in SMP case. */
511 /* Caches are disabled, so full TLB flush should be enough. */
512 tlb_flush_all_local();
516 * Remap one vm_meattr class to another one. This can be useful as
517 * workaround for SOC errata, e.g. if devices must be accessed using
520 * !!! Please note that this function is absolutely last resort thing.
521 * It should not be used under normal circumstances. !!!
524 * - it shall be called after pmap_bootstrap_prepare() and before
525 * cpu_mp_start() (thus only on boot CPU). In practice, it's expected
526 * to be called from platform_attach() or platform_late_init().
528 * - if remapping doesn't change caching mode, or until uncached class
529 * is remapped to any kind of cached one, then no other restriction exists.
531 * - if pmap_remap_vm_attr() changes caching mode, but both (original and
532 * remapped) remain cached, then caller is resposible for calling
533 * of dcache_wbinv_poc_all().
535 * - remapping of any kind of cached class to uncached is not permitted.
538 pmap_remap_vm_attr(vm_memattr_t old_attr, vm_memattr_t new_attr)
540 int old_idx, new_idx;
542 /* Map VM memattrs to indexes to tex_class table. */
543 old_idx = PTE2_ATTR2IDX(pte2_attr_tab[(int)old_attr]);
544 new_idx = PTE2_ATTR2IDX(pte2_attr_tab[(int)new_attr]);
546 /* Replace TEX attribute and apply it. */
547 tex_class[old_idx] = tex_class[new_idx];
552 * KERNBASE must be multiple of NPT2_IN_PG * PTE1_SIZE. In other words,
553 * KERNBASE is mapped by first L2 page table in L2 page table page. It
554 * meets same constrain due to PT2MAP being placed just under KERNBASE.
556 CTASSERT((KERNBASE & (NPT2_IN_PG * PTE1_SIZE - 1)) == 0);
557 CTASSERT((KERNBASE - VM_MAXUSER_ADDRESS) >= PT2MAP_SIZE);
560 * In crazy dreams, PAGE_SIZE could be a multiple of PTE2_SIZE in general.
561 * For now, anyhow, the following check must be fulfilled.
563 CTASSERT(PAGE_SIZE == PTE2_SIZE);
565 * We don't want to mess up MI code with all MMU and PMAP definitions,
566 * so some things, which depend on other ones, are defined independently.
567 * Now, it is time to check that we don't screw up something.
569 CTASSERT(PDRSHIFT == PTE1_SHIFT);
571 * Check L1 and L2 page table entries definitions consistency.
573 CTASSERT(NB_IN_PT1 == (sizeof(pt1_entry_t) * NPTE1_IN_PT1));
574 CTASSERT(NB_IN_PT2 == (sizeof(pt2_entry_t) * NPTE2_IN_PT2));
576 * Check L2 page tables page consistency.
578 CTASSERT(PAGE_SIZE == (NPT2_IN_PG * NB_IN_PT2));
579 CTASSERT((1 << PT2PG_SHIFT) == NPT2_IN_PG);
581 * Check PT2TAB consistency.
582 * PT2TAB_ENTRIES is defined as a division of NPTE1_IN_PT1 by NPT2_IN_PG.
583 * This should be done without remainder.
585 CTASSERT(NPTE1_IN_PT1 == (PT2TAB_ENTRIES * NPT2_IN_PG));
590 * All level 2 page tables (PT2s) are mapped continuously and accordingly
591 * into PT2MAP address space. As PT2 size is less than PAGE_SIZE, this can
592 * be done only if PAGE_SIZE is a multiple of PT2 size. All PT2s in one page
593 * must be used together, but not necessary at once. The first PT2 in a page
594 * must map things on correctly aligned address and the others must follow
597 #define NB_IN_PT2TAB (PT2TAB_ENTRIES * sizeof(pt2_entry_t))
598 #define NPT2_IN_PT2TAB (NB_IN_PT2TAB / NB_IN_PT2)
599 #define NPG_IN_PT2TAB (NB_IN_PT2TAB / PAGE_SIZE)
602 * Check PT2TAB consistency.
603 * NPT2_IN_PT2TAB is defined as a division of NB_IN_PT2TAB by NB_IN_PT2.
604 * NPG_IN_PT2TAB is defined as a division of NB_IN_PT2TAB by PAGE_SIZE.
605 * The both should be done without remainder.
607 CTASSERT(NB_IN_PT2TAB == (NPT2_IN_PT2TAB * NB_IN_PT2));
608 CTASSERT(NB_IN_PT2TAB == (NPG_IN_PT2TAB * PAGE_SIZE));
610 * The implementation was made general, however, with the assumption
611 * bellow in mind. In case of another value of NPG_IN_PT2TAB,
612 * the code should be once more rechecked.
614 CTASSERT(NPG_IN_PT2TAB == 1);
617 * Get offset of PT2 in a page
618 * associated with given PT1 index.
620 static __inline u_int
621 page_pt2off(u_int pt1_idx)
624 return ((pt1_idx & PT2PG_MASK) * NB_IN_PT2);
628 * Get physical address of PT2
629 * associated with given PT2s page and PT1 index.
631 static __inline vm_paddr_t
632 page_pt2pa(vm_paddr_t pgpa, u_int pt1_idx)
635 return (pgpa + page_pt2off(pt1_idx));
639 * Get first entry of PT2
640 * associated with given PT2s page and PT1 index.
642 static __inline pt2_entry_t *
643 page_pt2(vm_offset_t pgva, u_int pt1_idx)
646 return ((pt2_entry_t *)(pgva + page_pt2off(pt1_idx)));
650 * Get virtual address of PT2s page (mapped in PT2MAP)
651 * which holds PT2 which holds entry which maps given virtual address.
653 static __inline vm_offset_t
654 pt2map_pt2pg(vm_offset_t va)
657 va &= ~(NPT2_IN_PG * PTE1_SIZE - 1);
658 return ((vm_offset_t)pt2map_entry(va));
661 /*****************************************************************************
663 * THREE pmap initialization milestones exist:
666 * -> fundamental init (including MMU) in ASM
669 * -> fundamental init continues in C
670 * -> first available physical address is known
672 * pmap_bootstrap_prepare() -> FIRST PMAP MILESTONE (first epoch begins)
673 * -> basic (safe) interface for physical address allocation is made
674 * -> basic (safe) interface for virtual mapping is made
675 * -> limited not SMP coherent work is possible
677 * -> more fundamental init continues in C
678 * -> locks and some more things are available
679 * -> all fundamental allocations and mappings are done
681 * pmap_bootstrap() -> SECOND PMAP MILESTONE (second epoch begins)
682 * -> phys_avail[] and virtual_avail is set
683 * -> control is passed to vm subsystem
684 * -> physical and virtual address allocation are off limit
685 * -> low level mapping functions, some SMP coherent,
686 * are available, which cannot be used before vm subsystem
690 * -> vm subsystem is being inited
692 * pmap_init() -> THIRD PMAP MILESTONE (third epoch begins)
693 * -> pmap is fully inited
695 *****************************************************************************/
697 /*****************************************************************************
699 * PMAP first stage initialization and utility functions
700 * for pre-bootstrap epoch.
702 * After pmap_bootstrap_prepare() is called, the following functions
705 * (1) strictly only for this stage functions for physical page allocations,
706 * virtual space allocations, and mappings:
708 * vm_paddr_t pmap_preboot_get_pages(u_int num);
709 * void pmap_preboot_map_pages(vm_paddr_t pa, vm_offset_t va, u_int num);
710 * vm_offset_t pmap_preboot_reserve_pages(u_int num);
711 * vm_offset_t pmap_preboot_get_vpages(u_int num);
712 * void pmap_preboot_map_attr(vm_paddr_t pa, vm_offset_t va, vm_size_t size,
713 * vm_prot_t prot, vm_memattr_t attr);
715 * (2) for all stages:
717 * vm_paddr_t pmap_kextract(vm_offset_t va);
719 * NOTE: This is not SMP coherent stage.
721 *****************************************************************************/
723 #define KERNEL_P2V(pa) \
724 ((vm_offset_t)((pa) - arm_physmem_kernaddr + KERNVIRTADDR))
725 #define KERNEL_V2P(va) \
726 ((vm_paddr_t)((va) - KERNVIRTADDR + arm_physmem_kernaddr))
728 static vm_paddr_t last_paddr;
731 * Pre-bootstrap epoch page allocator.
734 pmap_preboot_get_pages(u_int num)
739 last_paddr += num * PAGE_SIZE;
745 * The fundamental initialization of PMAP stuff.
747 * Some things already happened in locore.S and some things could happen
748 * before pmap_bootstrap_prepare() is called, so let's recall what is done:
749 * 1. Caches are disabled.
750 * 2. We are running on virtual addresses already with 'boot_pt1'
752 * 3. So far, all virtual addresses can be converted to physical ones and
753 * vice versa by the following macros:
754 * KERNEL_P2V(pa) .... physical to virtual ones,
755 * KERNEL_V2P(va) .... virtual to physical ones.
757 * What is done herein:
758 * 1. The 'boot_pt1' is replaced by real kernel L1 page table 'kern_pt1'.
759 * 2. PT2MAP magic is brought to live.
760 * 3. Basic preboot functions for page allocations and mappings can be used.
761 * 4. Everything is prepared for L1 cache enabling.
764 * 1. To use second TTB register, so kernel and users page tables will be
765 * separated. This way process forking - pmap_pinit() - could be faster,
766 * it saves physical pages and KVA per a process, and it's simple change.
767 * However, it will lead, due to hardware matter, to the following:
768 * (a) 2G space for kernel and 2G space for users.
769 * (b) 1G space for kernel in low addresses and 3G for users above it.
770 * A question is: Is the case (b) really an option? Note that case (b)
771 * does save neither physical memory and KVA.
774 pmap_bootstrap_prepare(vm_paddr_t last)
776 vm_paddr_t pt2pg_pa, pt2tab_pa, pa, size;
777 vm_offset_t pt2pg_va;
784 * Now, we are going to make real kernel mapping. Note that we are
785 * already running on some mapping made in locore.S and we expect
786 * that it's large enough to ensure nofault access to physical memory
787 * allocated herein before switch.
789 * As kernel image and everything needed before are and will be mapped
790 * by section mappings, we align last physical address to PTE1_SIZE.
792 last_paddr = pte1_roundup(last);
795 * Allocate and zero page(s) for kernel L1 page table.
797 * Note that it's first allocation on space which was PTE1_SIZE
798 * aligned and as such base_pt1 is aligned to NB_IN_PT1 too.
800 base_pt1 = pmap_preboot_get_pages(NPG_IN_PT1);
801 kern_pt1 = (pt1_entry_t *)KERNEL_P2V(base_pt1);
802 bzero((void*)kern_pt1, NB_IN_PT1);
803 pte1_sync_range(kern_pt1, NB_IN_PT1);
805 /* Allocate and zero page(s) for kernel PT2TAB. */
806 pt2tab_pa = pmap_preboot_get_pages(NPG_IN_PT2TAB);
807 kern_pt2tab = (pt2_entry_t *)KERNEL_P2V(pt2tab_pa);
808 bzero(kern_pt2tab, NB_IN_PT2TAB);
809 pte2_sync_range(kern_pt2tab, NB_IN_PT2TAB);
811 /* Allocate and zero page(s) for kernel L2 page tables. */
812 pt2pg_pa = pmap_preboot_get_pages(NKPT2PG);
813 pt2pg_va = KERNEL_P2V(pt2pg_pa);
814 size = NKPT2PG * PAGE_SIZE;
815 bzero((void*)pt2pg_va, size);
816 pte2_sync_range((pt2_entry_t *)pt2pg_va, size);
819 * Add a physical memory segment (vm_phys_seg) corresponding to the
820 * preallocated pages for kernel L2 page tables so that vm_page
821 * structures representing these pages will be created. The vm_page
822 * structures are required for promotion of the corresponding kernel
823 * virtual addresses to section mappings.
825 vm_phys_add_seg(pt2tab_pa, pmap_preboot_get_pages(0));
828 * Insert allocated L2 page table pages to PT2TAB and make
829 * link to all PT2s in L1 page table. See how kernel_vm_end
832 * We play simple and safe. So every KVA will have underlaying
833 * L2 page table, even kernel image mapped by sections.
835 pte2p = kern_pt2tab_entry(KERNBASE);
836 for (pa = pt2pg_pa; pa < pt2pg_pa + size; pa += PTE2_SIZE)
837 pt2tab_store(pte2p++, PTE2_KPT(pa));
839 pte1p = kern_pte1(KERNBASE);
840 for (pa = pt2pg_pa; pa < pt2pg_pa + size; pa += NB_IN_PT2)
841 pte1_store(pte1p++, PTE1_LINK(pa));
843 /* Make section mappings for kernel. */
844 l1_attr = ATTR_TO_L1(PTE2_ATTR_DEFAULT);
845 pte1p = kern_pte1(KERNBASE);
846 for (pa = KERNEL_V2P(KERNBASE); pa < last; pa += PTE1_SIZE)
847 pte1_store(pte1p++, PTE1_KERN(pa, PTE1_AP_KRW, l1_attr));
850 * Get free and aligned space for PT2MAP and make L1 page table links
851 * to L2 page tables held in PT2TAB.
853 * Note that pages holding PT2s are stored in PT2TAB as pt2_entry_t
854 * descriptors and PT2TAB page(s) itself is(are) used as PT2s. Thus
855 * each entry in PT2TAB maps all PT2s in a page. This implies that
856 * virtual address of PT2MAP must be aligned to NPT2_IN_PG * PTE1_SIZE.
858 PT2MAP = (pt2_entry_t *)(KERNBASE - PT2MAP_SIZE);
859 pte1p = kern_pte1((vm_offset_t)PT2MAP);
860 for (pa = pt2tab_pa, i = 0; i < NPT2_IN_PT2TAB; i++, pa += NB_IN_PT2) {
861 pte1_store(pte1p++, PTE1_LINK(pa));
865 * Store PT2TAB in PT2TAB itself, i.e. self reference mapping.
866 * Each pmap will hold own PT2TAB, so the mapping should be not global.
868 pte2p = kern_pt2tab_entry((vm_offset_t)PT2MAP);
869 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE) {
870 pt2tab_store(pte2p++, PTE2_KPT_NG(pa));
874 * Choose correct L2 page table and make mappings for allocations
875 * made herein which replaces temporary locore.S mappings after a while.
876 * Note that PT2MAP cannot be used until we switch to kern_pt1.
878 * Note, that these allocations started aligned on 1M section and
879 * kernel PT1 was allocated first. Making of mappings must follow
880 * order of physical allocations as we've used KERNEL_P2V() macro
881 * for virtual addresses resolution.
883 pte2p = kern_pt2tab_entry((vm_offset_t)kern_pt1);
884 pt2pg_va = KERNEL_P2V(pte2_pa(pte2_load(pte2p)));
886 pte2p = page_pt2(pt2pg_va, pte1_index((vm_offset_t)kern_pt1));
888 /* Make mapping for kernel L1 page table. */
889 for (pa = base_pt1, i = 0; i < NPG_IN_PT1; i++, pa += PTE2_SIZE)
890 pte2_store(pte2p++, PTE2_KPT(pa));
892 /* Make mapping for kernel PT2TAB. */
893 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE)
894 pte2_store(pte2p++, PTE2_KPT(pa));
896 /* Finally, switch from 'boot_pt1' to 'kern_pt1'. */
897 pmap_kern_ttb = base_pt1 | ttb_flags;
898 cpuinfo_reinit_mmu(pmap_kern_ttb);
900 * Initialize the first available KVA. As kernel image is mapped by
901 * sections, we are leaving some gap behind.
903 virtual_avail = (vm_offset_t)kern_pt2tab + NPG_IN_PT2TAB * PAGE_SIZE;
907 * Setup L2 page table page for given KVA.
908 * Used in pre-bootstrap epoch.
910 * Note that we have allocated NKPT2PG pages for L2 page tables in advance
911 * and used them for mapping KVA starting from KERNBASE. However, this is not
912 * enough. Vectors and devices need L2 page tables too. Note that they are
913 * even above VM_MAX_KERNEL_ADDRESS.
915 static __inline vm_paddr_t
916 pmap_preboot_pt2pg_setup(vm_offset_t va)
918 pt2_entry_t *pte2p, pte2;
921 /* Get associated entry in PT2TAB. */
922 pte2p = kern_pt2tab_entry(va);
924 /* Just return, if PT2s page exists already. */
925 pte2 = pt2tab_load(pte2p);
926 if (pte2_is_valid(pte2))
927 return (pte2_pa(pte2));
929 KASSERT(va >= VM_MAX_KERNEL_ADDRESS,
930 ("%s: NKPT2PG too small", __func__));
933 * Allocate page for PT2s and insert it to PT2TAB.
934 * In other words, map it into PT2MAP space.
936 pt2pg_pa = pmap_preboot_get_pages(1);
937 pt2tab_store(pte2p, PTE2_KPT(pt2pg_pa));
939 /* Zero all PT2s in allocated page. */
940 bzero((void*)pt2map_pt2pg(va), PAGE_SIZE);
941 pte2_sync_range((pt2_entry_t *)pt2map_pt2pg(va), PAGE_SIZE);
947 * Setup L2 page table for given KVA.
948 * Used in pre-bootstrap epoch.
951 pmap_preboot_pt2_setup(vm_offset_t va)
954 vm_paddr_t pt2pg_pa, pt2_pa;
956 /* Setup PT2's page. */
957 pt2pg_pa = pmap_preboot_pt2pg_setup(va);
958 pt2_pa = page_pt2pa(pt2pg_pa, pte1_index(va));
960 /* Insert PT2 to PT1. */
961 pte1p = kern_pte1(va);
962 pte1_store(pte1p, PTE1_LINK(pt2_pa));
966 * Get L2 page entry associated with given KVA.
967 * Used in pre-bootstrap epoch.
969 static __inline pt2_entry_t*
970 pmap_preboot_vtopte2(vm_offset_t va)
974 /* Setup PT2 if needed. */
975 pte1p = kern_pte1(va);
976 if (!pte1_is_valid(pte1_load(pte1p))) /* XXX - sections ?! */
977 pmap_preboot_pt2_setup(va);
979 return (pt2map_entry(va));
983 * Pre-bootstrap epoch page(s) mapping(s).
986 pmap_preboot_map_pages(vm_paddr_t pa, vm_offset_t va, u_int num)
991 /* Map all the pages. */
992 for (i = 0; i < num; i++) {
993 pte2p = pmap_preboot_vtopte2(va);
994 pte2_store(pte2p, PTE2_KRW(pa));
1001 * Pre-bootstrap epoch virtual space alocator.
1004 pmap_preboot_reserve_pages(u_int num)
1007 vm_offset_t start, va;
1010 /* Allocate virtual space. */
1011 start = va = virtual_avail;
1012 virtual_avail += num * PAGE_SIZE;
1014 /* Zero the mapping. */
1015 for (i = 0; i < num; i++) {
1016 pte2p = pmap_preboot_vtopte2(va);
1017 pte2_store(pte2p, 0);
1025 * Pre-bootstrap epoch page(s) allocation and mapping(s).
1028 pmap_preboot_get_vpages(u_int num)
1033 /* Allocate physical page(s). */
1034 pa = pmap_preboot_get_pages(num);
1036 /* Allocate virtual space. */
1038 virtual_avail += num * PAGE_SIZE;
1040 /* Map and zero all. */
1041 pmap_preboot_map_pages(pa, va, num);
1042 bzero((void *)va, num * PAGE_SIZE);
1048 * Pre-bootstrap epoch page mapping(s) with attributes.
1051 pmap_preboot_map_attr(vm_paddr_t pa, vm_offset_t va, vm_size_t size,
1052 vm_prot_t prot, vm_memattr_t attr)
1055 u_int l1_attr, l1_prot, l2_prot, l2_attr;
1059 l2_prot = prot & VM_PROT_WRITE ? PTE2_AP_KRW : PTE2_AP_KR;
1060 l2_prot |= (prot & VM_PROT_EXECUTE) ? PTE2_X : PTE2_NX;
1061 l2_attr = vm_memattr_to_pte2(attr);
1062 l1_prot = ATTR_TO_L1(l2_prot);
1063 l1_attr = ATTR_TO_L1(l2_attr);
1065 /* Map all the pages. */
1066 num = round_page(size);
1068 if ((((va | pa) & PTE1_OFFSET) == 0) && (num >= PTE1_SIZE)) {
1069 pte1p = kern_pte1(va);
1070 pte1_store(pte1p, PTE1_KERN(pa, l1_prot, l1_attr));
1075 pte2p = pmap_preboot_vtopte2(va);
1076 pte2_store(pte2p, PTE2_KERN(pa, l2_prot, l2_attr));
1085 * Extract from the kernel page table the physical address
1086 * that is mapped by the given virtual address "va".
1089 pmap_kextract(vm_offset_t va)
1095 pte1 = pte1_load(kern_pte1(va));
1096 if (pte1_is_section(pte1)) {
1097 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1098 } else if (pte1_is_link(pte1)) {
1100 * We should beware of concurrent promotion that changes
1101 * pte1 at this point. However, it's not a problem as PT2
1102 * page is preserved by promotion in PT2TAB. So even if
1103 * it happens, using of PT2MAP is still safe.
1105 * QQQ: However, concurrent removing is a problem which
1106 * ends in abort on PT2MAP space. Locking must be used
1107 * to deal with this.
1109 pte2 = pte2_load(pt2map_entry(va));
1110 pa = pte2_pa(pte2) | (va & PTE2_OFFSET);
1113 panic("%s: va %#x pte1 %#x", __func__, va, pte1);
1119 * Extract from the kernel page table the physical address
1120 * that is mapped by the given virtual address "va". Also
1121 * return L2 page table entry which maps the address.
1123 * This is only intended to be used for panic dumps.
1126 pmap_dump_kextract(vm_offset_t va, pt2_entry_t *pte2p)
1132 pte1 = pte1_load(kern_pte1(va));
1133 if (pte1_is_section(pte1)) {
1134 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1135 pte2 = pa | ATTR_TO_L2(pte1) | PTE2_V;
1136 } else if (pte1_is_link(pte1)) {
1137 pte2 = pte2_load(pt2map_entry(va));
1148 /*****************************************************************************
1150 * PMAP second stage initialization and utility functions
1151 * for bootstrap epoch.
1153 * After pmap_bootstrap() is called, the following functions for
1154 * mappings can be used:
1156 * void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
1157 * void pmap_kremove(vm_offset_t va);
1158 * vm_offset_t pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end,
1161 * NOTE: This is not SMP coherent stage. And physical page allocation is not
1162 * allowed during this stage.
1164 *****************************************************************************/
1167 * Initialize kernel PMAP locks and lists, kernel_pmap itself, and
1168 * reserve various virtual spaces for temporary mappings.
1171 pmap_bootstrap(vm_offset_t firstaddr)
1173 pt2_entry_t *unused __unused;
1177 * Initialize the kernel pmap (which is statically allocated).
1179 PMAP_LOCK_INIT(kernel_pmap);
1180 kernel_l1pa = (vm_paddr_t)kern_pt1; /* for libkvm */
1181 kernel_pmap->pm_pt1 = kern_pt1;
1182 kernel_pmap->pm_pt2tab = kern_pt2tab;
1183 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1184 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1187 * Initialize the global pv list lock.
1189 rw_init(&pvh_global_lock, "pmap pv global");
1191 LIST_INIT(&allpmaps);
1194 * Request a spin mutex so that changes to allpmaps cannot be
1195 * preempted by smp_rendezvous_cpus().
1197 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
1198 mtx_lock_spin(&allpmaps_lock);
1199 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
1200 mtx_unlock_spin(&allpmaps_lock);
1203 * Reserve some special page table entries/VA space for temporary
1206 #define SYSMAP(c, p, v, n) do { \
1207 v = (c)pmap_preboot_reserve_pages(n); \
1208 p = pt2map_entry((vm_offset_t)v); \
1212 * Local CMAP1/CMAP2 are used for zeroing and copying pages.
1213 * Local CMAP2 is also used for data cache cleaning.
1216 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
1217 SYSMAP(caddr_t, pc->pc_cmap1_pte2p, pc->pc_cmap1_addr, 1);
1218 SYSMAP(caddr_t, pc->pc_cmap2_pte2p, pc->pc_cmap2_addr, 1);
1219 SYSMAP(vm_offset_t, pc->pc_qmap_pte2p, pc->pc_qmap_addr, 1);
1224 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS);
1227 * _tmppt is used for reading arbitrary physical pages via /dev/mem.
1229 SYSMAP(caddr_t, unused, _tmppt, 1);
1232 * PADDR1 and PADDR2 are used by pmap_pte2_quick() and pmap_pte2(),
1233 * respectively. PADDR3 is used by pmap_pte2_ddb().
1235 SYSMAP(pt2_entry_t *, PMAP1, PADDR1, 1);
1236 SYSMAP(pt2_entry_t *, PMAP2, PADDR2, 1);
1238 SYSMAP(pt2_entry_t *, PMAP3, PADDR3, 1);
1240 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
1243 * Note that in very short time in initarm(), we are going to
1244 * initialize phys_avail[] array and no further page allocation
1245 * can happen after that until vm subsystem will be initialized.
1247 kernel_vm_end_new = kernel_vm_end;
1248 virtual_end = vm_max_kernel_address;
1252 pmap_init_reserved_pages(void)
1261 * Skip if the mapping has already been initialized,
1262 * i.e. this is the BSP.
1264 if (pc->pc_cmap1_addr != 0)
1266 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
1267 pages = kva_alloc(PAGE_SIZE * 3);
1269 panic("%s: unable to allocate KVA", __func__);
1270 pc->pc_cmap1_pte2p = pt2map_entry(pages);
1271 pc->pc_cmap2_pte2p = pt2map_entry(pages + PAGE_SIZE);
1272 pc->pc_qmap_pte2p = pt2map_entry(pages + (PAGE_SIZE * 2));
1273 pc->pc_cmap1_addr = (caddr_t)pages;
1274 pc->pc_cmap2_addr = (caddr_t)(pages + PAGE_SIZE);
1275 pc->pc_qmap_addr = pages + (PAGE_SIZE * 2);
1278 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
1281 * The function can already be use in second initialization stage.
1282 * As such, the function DOES NOT call pmap_growkernel() where PT2
1283 * allocation can happen. So if used, be sure that PT2 for given
1284 * virtual address is allocated already!
1286 * Add a wired page to the kva.
1287 * Note: not SMP coherent.
1289 static __inline void
1290 pmap_kenter_prot_attr(vm_offset_t va, vm_paddr_t pa, uint32_t prot,
1296 pte1p = kern_pte1(va);
1297 if (!pte1_is_valid(pte1_load(pte1p))) { /* XXX - sections ?! */
1299 * This is a very low level function, so PT2 and particularly
1300 * PT2PG associated with given virtual address must be already
1301 * allocated. It's a pain mainly during pmap initialization
1302 * stage. However, called after pmap initialization with
1303 * virtual address not under kernel_vm_end will lead to
1306 if (!pte2_is_valid(pte2_load(kern_pt2tab_entry(va))))
1307 panic("%s: kernel PT2 not allocated!", __func__);
1310 pte2p = pt2map_entry(va);
1311 pte2_store(pte2p, PTE2_KERN(pa, prot, attr));
1315 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1318 pmap_kenter_prot_attr(va, pa, PTE2_AP_KRW, PTE2_ATTR_DEFAULT);
1322 * Remove a page from the kernel pagetables.
1323 * Note: not SMP coherent.
1326 pmap_kremove(vm_offset_t va)
1331 pte1p = kern_pte1(va);
1332 if (pte1_is_section(pte1_load(pte1p))) {
1335 pte2p = pt2map_entry(va);
1341 * Share new kernel PT2PG with all pmaps.
1342 * The caller is responsible for maintaining TLB consistency.
1345 pmap_kenter_pt2tab(vm_offset_t va, pt2_entry_t npte2)
1350 mtx_lock_spin(&allpmaps_lock);
1351 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1352 pte2p = pmap_pt2tab_entry(pmap, va);
1353 pt2tab_store(pte2p, npte2);
1355 mtx_unlock_spin(&allpmaps_lock);
1359 * Share new kernel PTE1 with all pmaps.
1360 * The caller is responsible for maintaining TLB consistency.
1363 pmap_kenter_pte1(vm_offset_t va, pt1_entry_t npte1)
1368 mtx_lock_spin(&allpmaps_lock);
1369 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1370 pte1p = pmap_pte1(pmap, va);
1371 pte1_store(pte1p, npte1);
1373 mtx_unlock_spin(&allpmaps_lock);
1377 * Used to map a range of physical addresses into kernel
1378 * virtual address space.
1380 * The value passed in '*virt' is a suggested virtual address for
1381 * the mapping. Architectures which can support a direct-mapped
1382 * physical to virtual region can return the appropriate address
1383 * within that region, leaving '*virt' unchanged. Other
1384 * architectures should map the pages starting at '*virt' and
1385 * update '*virt' with the first usable address after the mapped
1388 * NOTE: Read the comments above pmap_kenter_prot_attr() as
1389 * the function is used herein!
1392 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1394 vm_offset_t va, sva;
1395 vm_paddr_t pte1_offset;
1397 uint32_t l1prot, l2prot;
1398 uint32_t l1attr, l2attr;
1400 PDEBUG(1, printf("%s: virt = %#x, start = %#x, end = %#x (size = %#x),"
1401 " prot = %d\n", __func__, *virt, start, end, end - start, prot));
1403 l2prot = (prot & VM_PROT_WRITE) ? PTE2_AP_KRW : PTE2_AP_KR;
1404 l2prot |= (prot & VM_PROT_EXECUTE) ? PTE2_X : PTE2_NX;
1405 l1prot = ATTR_TO_L1(l2prot);
1407 l2attr = PTE2_ATTR_DEFAULT;
1408 l1attr = ATTR_TO_L1(l2attr);
1412 * Does the physical address range's size and alignment permit at
1413 * least one section mapping to be created?
1415 pte1_offset = start & PTE1_OFFSET;
1416 if ((end - start) - ((PTE1_SIZE - pte1_offset) & PTE1_OFFSET) >=
1419 * Increase the starting virtual address so that its alignment
1420 * does not preclude the use of section mappings.
1422 if ((va & PTE1_OFFSET) < pte1_offset)
1423 va = pte1_trunc(va) + pte1_offset;
1424 else if ((va & PTE1_OFFSET) > pte1_offset)
1425 va = pte1_roundup(va) + pte1_offset;
1428 while (start < end) {
1429 if ((start & PTE1_OFFSET) == 0 && end - start >= PTE1_SIZE) {
1430 KASSERT((va & PTE1_OFFSET) == 0,
1431 ("%s: misaligned va %#x", __func__, va));
1432 npte1 = PTE1_KERN(start, l1prot, l1attr);
1433 pmap_kenter_pte1(va, npte1);
1437 pmap_kenter_prot_attr(va, start, l2prot, l2attr);
1442 tlb_flush_range(sva, va - sva);
1448 * Make a temporary mapping for a physical address.
1449 * This is only intended to be used for panic dumps.
1452 pmap_kenter_temporary(vm_paddr_t pa, int i)
1456 /* QQQ: 'i' should be less or equal to MAXDUMPPGS. */
1458 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
1459 pmap_kenter(va, pa);
1460 tlb_flush_local(va);
1461 return ((void *)crashdumpmap);
1464 /*************************************
1466 * TLB & cache maintenance routines.
1468 *************************************/
1471 * We inline these within pmap.c for speed.
1474 pmap_tlb_flush(pmap_t pmap, vm_offset_t va)
1477 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1482 pmap_tlb_flush_range(pmap_t pmap, vm_offset_t sva, vm_size_t size)
1485 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1486 tlb_flush_range(sva, size);
1490 * Abuse the pte2 nodes for unmapped kva to thread a kva freelist through.
1492 * - Must deal with pages in order to ensure that none of the PTE2_* bits
1493 * are ever set, PTE2_V in particular.
1494 * - Assumes we can write to pte2s without pte2_store() atomic ops.
1495 * - Assumes nothing will ever test these addresses for 0 to indicate
1496 * no mapping instead of correctly checking PTE2_V.
1497 * - Assumes a vm_offset_t will fit in a pte2 (true for arm).
1498 * Because PTE2_V is never set, there can be no mappings to invalidate.
1501 pmap_pte2list_alloc(vm_offset_t *head)
1508 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
1509 pte2p = pt2map_entry(va);
1512 panic("%s: va with PTE2_V set!", __func__);
1518 pmap_pte2list_free(vm_offset_t *head, vm_offset_t va)
1523 panic("%s: freeing va with PTE2_V set!", __func__);
1524 pte2p = pt2map_entry(va);
1525 *pte2p = *head; /* virtual! PTE2_V is 0 though */
1530 pmap_pte2list_init(vm_offset_t *head, void *base, int npages)
1536 for (i = npages - 1; i >= 0; i--) {
1537 va = (vm_offset_t)base + i * PAGE_SIZE;
1538 pmap_pte2list_free(head, va);
1542 /*****************************************************************************
1544 * PMAP third and final stage initialization.
1546 * After pmap_init() is called, PMAP subsystem is fully initialized.
1548 *****************************************************************************/
1550 SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
1551 "VM/pmap parameters");
1553 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
1554 "Max number of PV entries");
1555 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
1556 "Page share factor per proc");
1558 static u_long nkpt2pg = NKPT2PG;
1559 SYSCTL_ULONG(_vm_pmap, OID_AUTO, nkpt2pg, CTLFLAG_RD,
1560 &nkpt2pg, 0, "Pre-allocated pages for kernel PT2s");
1562 static int sp_enabled = 1;
1563 SYSCTL_INT(_vm_pmap, OID_AUTO, sp_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
1564 &sp_enabled, 0, "Are large page mappings enabled?");
1567 pmap_ps_enabled(pmap_t pmap __unused)
1570 return (sp_enabled != 0);
1573 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pte1, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
1574 "1MB page mapping counters");
1576 static u_long pmap_pte1_demotions;
1577 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, demotions, CTLFLAG_RD,
1578 &pmap_pte1_demotions, 0, "1MB page demotions");
1580 static u_long pmap_pte1_mappings;
1581 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, mappings, CTLFLAG_RD,
1582 &pmap_pte1_mappings, 0, "1MB page mappings");
1584 static u_long pmap_pte1_p_failures;
1585 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, p_failures, CTLFLAG_RD,
1586 &pmap_pte1_p_failures, 0, "1MB page promotion failures");
1588 static u_long pmap_pte1_promotions;
1589 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, promotions, CTLFLAG_RD,
1590 &pmap_pte1_promotions, 0, "1MB page promotions");
1592 static u_long pmap_pte1_kern_demotions;
1593 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, kern_demotions, CTLFLAG_RD,
1594 &pmap_pte1_kern_demotions, 0, "1MB page kernel demotions");
1596 static u_long pmap_pte1_kern_promotions;
1597 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, kern_promotions, CTLFLAG_RD,
1598 &pmap_pte1_kern_promotions, 0, "1MB page kernel promotions");
1600 static __inline ttb_entry_t
1601 pmap_ttb_get(pmap_t pmap)
1604 return (vtophys(pmap->pm_pt1) | ttb_flags);
1608 * Initialize a vm_page's machine-dependent fields.
1611 * 1. Pages for L2 page tables are always not managed. So, pv_list and
1612 * pt2_wirecount can share same physical space. However, proper
1613 * initialization on a page alloc for page tables and reinitialization
1614 * on the page free must be ensured.
1617 pmap_page_init(vm_page_t m)
1620 TAILQ_INIT(&m->md.pv_list);
1621 pt2_wirecount_init(m);
1622 m->md.pat_mode = VM_MEMATTR_DEFAULT;
1626 * Virtualization for faster way how to zero whole page.
1628 static __inline void
1629 pagezero(void *page)
1632 bzero(page, PAGE_SIZE);
1636 * Zero L2 page table page.
1637 * Use same KVA as in pmap_zero_page().
1639 static __inline vm_paddr_t
1640 pmap_pt2pg_zero(vm_page_t m)
1642 pt2_entry_t *cmap2_pte2p;
1646 pa = VM_PAGE_TO_PHYS(m);
1649 * XXX: For now, we map whole page even if it's already zero,
1650 * to sync it even if the sync is only DSB.
1654 cmap2_pte2p = pc->pc_cmap2_pte2p;
1655 mtx_lock(&pc->pc_cmap_lock);
1656 if (pte2_load(cmap2_pte2p) != 0)
1657 panic("%s: CMAP2 busy", __func__);
1658 pte2_store(cmap2_pte2p, PTE2_KERN_NG(pa, PTE2_AP_KRW,
1659 vm_page_pte2_attr(m)));
1660 /* Even VM_ALLOC_ZERO request is only advisory. */
1661 if ((m->flags & PG_ZERO) == 0)
1662 pagezero(pc->pc_cmap2_addr);
1663 pte2_sync_range((pt2_entry_t *)pc->pc_cmap2_addr, PAGE_SIZE);
1664 pte2_clear(cmap2_pte2p);
1665 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
1668 * Unpin the thread before releasing the lock. Otherwise the thread
1669 * could be rescheduled while still bound to the current CPU, only
1670 * to unpin itself immediately upon resuming execution.
1673 mtx_unlock(&pc->pc_cmap_lock);
1679 * Init just allocated page as L2 page table(s) holder
1680 * and return its physical address.
1682 static __inline vm_paddr_t
1683 pmap_pt2pg_init(pmap_t pmap, vm_offset_t va, vm_page_t m)
1688 /* Check page attributes. */
1689 if (m->md.pat_mode != pt_memattr)
1690 pmap_page_set_memattr(m, pt_memattr);
1692 /* Zero page and init wire counts. */
1693 pa = pmap_pt2pg_zero(m);
1694 pt2_wirecount_init(m);
1697 * Map page to PT2MAP address space for given pmap.
1698 * Note that PT2MAP space is shared with all pmaps.
1700 if (pmap == kernel_pmap)
1701 pmap_kenter_pt2tab(va, PTE2_KPT(pa));
1703 pte2p = pmap_pt2tab_entry(pmap, va);
1704 pt2tab_store(pte2p, PTE2_KPT_NG(pa));
1711 * Initialize the pmap module.
1712 * Called by vm_init, to initialize any structures that the pmap
1713 * system needs to map virtual memory.
1719 pt2_entry_t *pte2p, pte2;
1720 u_int i, pte1_idx, pv_npg;
1722 PDEBUG(1, printf("%s: phys_start = %#x\n", __func__, PHYSADDR));
1725 * Initialize the vm page array entries for kernel pmap's
1726 * L2 page table pages allocated in advance.
1728 pte1_idx = pte1_index(KERNBASE - PT2MAP_SIZE);
1729 pte2p = kern_pt2tab_entry(KERNBASE - PT2MAP_SIZE);
1730 for (i = 0; i < nkpt2pg + NPG_IN_PT2TAB; i++, pte2p++) {
1734 pte2 = pte2_load(pte2p);
1735 KASSERT(pte2_is_valid(pte2), ("%s: no valid entry", __func__));
1738 m = PHYS_TO_VM_PAGE(pa);
1739 KASSERT(m >= vm_page_array &&
1740 m < &vm_page_array[vm_page_array_size],
1741 ("%s: L2 page table page is out of range", __func__));
1743 m->pindex = pte1_idx;
1745 pte1_idx += NPT2_IN_PG;
1749 * Initialize the address space (zone) for the pv entries. Set a
1750 * high water mark so that the system can recover from excessive
1751 * numbers of pv entries.
1753 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1754 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1755 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1756 pv_entry_max = roundup(pv_entry_max, _NPCPV);
1757 pv_entry_high_water = 9 * (pv_entry_max / 10);
1760 * Are large page mappings enabled?
1762 TUNABLE_INT_FETCH("vm.pmap.sp_enabled", &sp_enabled);
1764 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1765 ("%s: can't assign to pagesizes[1]", __func__));
1766 pagesizes[1] = PTE1_SIZE;
1770 * Calculate the size of the pv head table for sections.
1771 * Handle the possibility that "vm_phys_segs[...].end" is zero.
1772 * Note that the table is only for sections which could be promoted.
1774 first_managed_pa = pte1_trunc(vm_phys_segs[0].start);
1775 pv_npg = (pte1_trunc(vm_phys_segs[vm_phys_nsegs - 1].end - PAGE_SIZE)
1776 - first_managed_pa) / PTE1_SIZE + 1;
1779 * Allocate memory for the pv head table for sections.
1781 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1783 pv_table = kmem_malloc(s, M_WAITOK | M_ZERO);
1784 for (i = 0; i < pv_npg; i++)
1785 TAILQ_INIT(&pv_table[i].pv_list);
1787 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
1788 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
1789 if (pv_chunkbase == NULL)
1790 panic("%s: not enough kvm for pv chunks", __func__);
1791 pmap_pte2list_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
1795 * Add a list of wired pages to the kva
1796 * this routine is only used for temporary
1797 * kernel mappings that do not need to have
1798 * page modification or references recorded.
1799 * Note that old mappings are simply written
1800 * over. The page *must* be wired.
1801 * Note: SMP coherent. Uses a ranged shootdown IPI.
1804 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1807 pt2_entry_t *epte2p, *pte2p, pte2;
1812 pte2p = pt2map_entry(sva);
1813 epte2p = pte2p + count;
1814 while (pte2p < epte2p) {
1816 pa = VM_PAGE_TO_PHYS(m);
1817 pte2 = pte2_load(pte2p);
1818 if ((pte2_pa(pte2) != pa) ||
1819 (pte2_attr(pte2) != vm_page_pte2_attr(m))) {
1821 pte2_store(pte2p, PTE2_KERN(pa, PTE2_AP_KRW,
1822 vm_page_pte2_attr(m)));
1826 if (__predict_false(anychanged))
1827 tlb_flush_range(sva, count * PAGE_SIZE);
1831 * This routine tears out page mappings from the
1832 * kernel -- it is meant only for temporary mappings.
1833 * Note: SMP coherent. Uses a ranged shootdown IPI.
1836 pmap_qremove(vm_offset_t sva, int count)
1841 while (count-- > 0) {
1845 tlb_flush_range(sva, va - sva);
1849 * Are we current address space or kernel?
1852 pmap_is_current(pmap_t pmap)
1855 return (pmap == kernel_pmap ||
1856 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace)));
1860 * If the given pmap is not the current or kernel pmap, the returned
1861 * pte2 must be released by passing it to pmap_pte2_release().
1863 static pt2_entry_t *
1864 pmap_pte2(pmap_t pmap, vm_offset_t va)
1867 vm_paddr_t pt2pg_pa;
1869 pte1 = pte1_load(pmap_pte1(pmap, va));
1870 if (pte1_is_section(pte1))
1871 panic("%s: attempt to map PTE1", __func__);
1872 if (pte1_is_link(pte1)) {
1873 /* Are we current address space or kernel? */
1874 if (pmap_is_current(pmap))
1875 return (pt2map_entry(va));
1876 /* Note that L2 page table size is not equal to PAGE_SIZE. */
1877 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
1878 mtx_lock(&PMAP2mutex);
1879 if (pte2_pa(pte2_load(PMAP2)) != pt2pg_pa) {
1880 pte2_store(PMAP2, PTE2_KPT(pt2pg_pa));
1881 tlb_flush((vm_offset_t)PADDR2);
1883 return (PADDR2 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
1889 * Releases a pte2 that was obtained from pmap_pte2().
1890 * Be prepared for the pte2p being NULL.
1892 static __inline void
1893 pmap_pte2_release(pt2_entry_t *pte2p)
1896 if ((pt2_entry_t *)(trunc_page((vm_offset_t)pte2p)) == PADDR2) {
1897 mtx_unlock(&PMAP2mutex);
1902 * Super fast pmap_pte2 routine best used when scanning
1903 * the pv lists. This eliminates many coarse-grained
1904 * invltlb calls. Note that many of the pv list
1905 * scans are across different pmaps. It is very wasteful
1906 * to do an entire tlb flush for checking a single mapping.
1908 * If the given pmap is not the current pmap, pvh_global_lock
1909 * must be held and curthread pinned to a CPU.
1911 static pt2_entry_t *
1912 pmap_pte2_quick(pmap_t pmap, vm_offset_t va)
1915 vm_paddr_t pt2pg_pa;
1917 pte1 = pte1_load(pmap_pte1(pmap, va));
1918 if (pte1_is_section(pte1))
1919 panic("%s: attempt to map PTE1", __func__);
1920 if (pte1_is_link(pte1)) {
1921 /* Are we current address space or kernel? */
1922 if (pmap_is_current(pmap))
1923 return (pt2map_entry(va));
1924 rw_assert(&pvh_global_lock, RA_WLOCKED);
1925 KASSERT(curthread->td_pinned > 0,
1926 ("%s: curthread not pinned", __func__));
1927 /* Note that L2 page table size is not equal to PAGE_SIZE. */
1928 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
1929 if (pte2_pa(pte2_load(PMAP1)) != pt2pg_pa) {
1930 pte2_store(PMAP1, PTE2_KPT(pt2pg_pa));
1932 PMAP1cpu = PCPU_GET(cpuid);
1934 tlb_flush_local((vm_offset_t)PADDR1);
1938 if (PMAP1cpu != PCPU_GET(cpuid)) {
1939 PMAP1cpu = PCPU_GET(cpuid);
1940 tlb_flush_local((vm_offset_t)PADDR1);
1945 return (PADDR1 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
1951 * Routine: pmap_extract
1953 * Extract the physical page address associated
1954 * with the given map/virtual_address pair.
1957 pmap_extract(pmap_t pmap, vm_offset_t va)
1964 pte1 = pte1_load(pmap_pte1(pmap, va));
1965 if (pte1_is_section(pte1))
1966 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1967 else if (pte1_is_link(pte1)) {
1968 pte2p = pmap_pte2(pmap, va);
1969 pa = pte2_pa(pte2_load(pte2p)) | (va & PTE2_OFFSET);
1970 pmap_pte2_release(pte2p);
1978 * Routine: pmap_extract_and_hold
1980 * Atomically extract and hold the physical page
1981 * with the given pmap and virtual address pair
1982 * if that mapping permits the given protection.
1985 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1989 pt2_entry_t pte2, *pte2p;
1994 pte1 = pte1_load(pmap_pte1(pmap, va));
1995 if (pte1_is_section(pte1)) {
1996 if (!(pte1 & PTE1_RO) || !(prot & VM_PROT_WRITE)) {
1997 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1998 m = PHYS_TO_VM_PAGE(pa);
1999 if (!vm_page_wire_mapped(m))
2002 } else if (pte1_is_link(pte1)) {
2003 pte2p = pmap_pte2(pmap, va);
2004 pte2 = pte2_load(pte2p);
2005 pmap_pte2_release(pte2p);
2006 if (pte2_is_valid(pte2) &&
2007 (!(pte2 & PTE2_RO) || !(prot & VM_PROT_WRITE))) {
2009 m = PHYS_TO_VM_PAGE(pa);
2010 if (!vm_page_wire_mapped(m))
2019 * Grow the number of kernel L2 page table entries, if needed.
2022 pmap_growkernel(vm_offset_t addr)
2025 vm_paddr_t pt2pg_pa, pt2_pa;
2029 PDEBUG(1, printf("%s: addr = %#x\n", __func__, addr));
2031 * All the time kernel_vm_end is first KVA for which underlying
2032 * L2 page table is either not allocated or linked from L1 page table
2033 * (not considering sections). Except for two possible cases:
2035 * (1) in the very beginning as long as pmap_growkernel() was
2036 * not called, it could be first unused KVA (which is not
2037 * rounded up to PTE1_SIZE),
2039 * (2) when all KVA space is mapped and vm_map_max(kernel_map)
2040 * address is not rounded up to PTE1_SIZE. (For example,
2041 * it could be 0xFFFFFFFF.)
2043 kernel_vm_end = pte1_roundup(kernel_vm_end);
2044 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2045 addr = roundup2(addr, PTE1_SIZE);
2046 if (addr - 1 >= vm_map_max(kernel_map))
2047 addr = vm_map_max(kernel_map);
2048 while (kernel_vm_end < addr) {
2049 pte1 = pte1_load(kern_pte1(kernel_vm_end));
2050 if (pte1_is_valid(pte1)) {
2051 kernel_vm_end += PTE1_SIZE;
2052 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2053 kernel_vm_end = vm_map_max(kernel_map);
2060 * kernel_vm_end_new is used in pmap_pinit() when kernel
2061 * mappings are entered to new pmap all at once to avoid race
2062 * between pmap_kenter_pte1() and kernel_vm_end increase.
2063 * The same aplies to pmap_kenter_pt2tab().
2065 kernel_vm_end_new = kernel_vm_end + PTE1_SIZE;
2067 pte2 = pt2tab_load(kern_pt2tab_entry(kernel_vm_end));
2068 if (!pte2_is_valid(pte2)) {
2070 * Install new PT2s page into kernel PT2TAB.
2072 m = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT |
2073 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2075 panic("%s: no memory to grow kernel", __func__);
2076 m->pindex = pte1_index(kernel_vm_end) & ~PT2PG_MASK;
2079 * QQQ: To link all new L2 page tables from L1 page
2080 * table now and so pmap_kenter_pte1() them
2081 * at once together with pmap_kenter_pt2tab()
2082 * could be nice speed up. However,
2083 * pmap_growkernel() does not happen so often...
2084 * QQQ: The other TTBR is another option.
2086 pt2pg_pa = pmap_pt2pg_init(kernel_pmap, kernel_vm_end,
2089 pt2pg_pa = pte2_pa(pte2);
2091 pt2_pa = page_pt2pa(pt2pg_pa, pte1_index(kernel_vm_end));
2092 pmap_kenter_pte1(kernel_vm_end, PTE1_LINK(pt2_pa));
2094 kernel_vm_end = kernel_vm_end_new;
2095 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2096 kernel_vm_end = vm_map_max(kernel_map);
2103 kvm_size(SYSCTL_HANDLER_ARGS)
2105 unsigned long ksize = vm_max_kernel_address - KERNBASE;
2107 return (sysctl_handle_long(oidp, &ksize, 0, req));
2109 SYSCTL_PROC(_vm, OID_AUTO, kvm_size,
2110 CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 0, 0, kvm_size, "IU",
2114 kvm_free(SYSCTL_HANDLER_ARGS)
2116 unsigned long kfree = vm_max_kernel_address - kernel_vm_end;
2118 return (sysctl_handle_long(oidp, &kfree, 0, req));
2120 SYSCTL_PROC(_vm, OID_AUTO, kvm_free,
2121 CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 0, 0, kvm_free, "IU",
2122 "Amount of KVM free");
2124 /***********************************************
2126 * Pmap allocation/deallocation routines.
2128 ***********************************************/
2131 * Initialize the pmap for the swapper process.
2134 pmap_pinit0(pmap_t pmap)
2136 PDEBUG(1, printf("%s: pmap = %p\n", __func__, pmap));
2138 PMAP_LOCK_INIT(pmap);
2141 * Kernel page table directory and pmap stuff around is already
2142 * initialized, we are using it right now and here. So, finish
2143 * only PMAP structures initialization for process0 ...
2145 * Since the L1 page table and PT2TAB is shared with the kernel pmap,
2146 * which is already included in the list "allpmaps", this pmap does
2147 * not need to be inserted into that list.
2149 pmap->pm_pt1 = kern_pt1;
2150 pmap->pm_pt2tab = kern_pt2tab;
2151 CPU_ZERO(&pmap->pm_active);
2152 PCPU_SET(curpmap, pmap);
2153 TAILQ_INIT(&pmap->pm_pvchunk);
2154 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2155 CPU_SET(0, &pmap->pm_active);
2158 static __inline void
2159 pte1_copy_nosync(pt1_entry_t *spte1p, pt1_entry_t *dpte1p, vm_offset_t sva,
2164 idx = pte1_index(sva);
2165 count = (pte1_index(eva) - idx + 1) * sizeof(pt1_entry_t);
2166 bcopy(spte1p + idx, dpte1p + idx, count);
2169 static __inline void
2170 pt2tab_copy_nosync(pt2_entry_t *spte2p, pt2_entry_t *dpte2p, vm_offset_t sva,
2175 idx = pt2tab_index(sva);
2176 count = (pt2tab_index(eva) - idx + 1) * sizeof(pt2_entry_t);
2177 bcopy(spte2p + idx, dpte2p + idx, count);
2181 * Initialize a preallocated and zeroed pmap structure,
2182 * such as one in a vmspace structure.
2185 pmap_pinit(pmap_t pmap)
2189 vm_paddr_t pa, pt2tab_pa;
2192 PDEBUG(6, printf("%s: pmap = %p, pm_pt1 = %p\n", __func__, pmap,
2196 * No need to allocate L2 page table space yet but we do need
2197 * a valid L1 page table and PT2TAB table.
2199 * Install shared kernel mappings to these tables. It's a little
2200 * tricky as some parts of KVA are reserved for vectors, devices,
2201 * and whatever else. These parts are supposed to be above
2202 * vm_max_kernel_address. Thus two regions should be installed:
2204 * (1) <KERNBASE, kernel_vm_end),
2205 * (2) <vm_max_kernel_address, 0xFFFFFFFF>.
2207 * QQQ: The second region should be stable enough to be installed
2208 * only once in time when the tables are allocated.
2209 * QQQ: Maybe copy of both regions at once could be faster ...
2210 * QQQ: Maybe the other TTBR is an option.
2212 * Finally, install own PT2TAB table to these tables.
2215 if (pmap->pm_pt1 == NULL) {
2216 pmap->pm_pt1 = kmem_alloc_contig(NB_IN_PT1,
2217 M_NOWAIT | M_ZERO, 0, -1UL, NB_IN_PT1, 0, pt_memattr);
2218 if (pmap->pm_pt1 == NULL)
2221 if (pmap->pm_pt2tab == NULL) {
2223 * QQQ: (1) PT2TAB must be contiguous. If PT2TAB is one page
2224 * only, what should be the only size for 32 bit systems,
2225 * then we could allocate it with vm_page_alloc() and all
2226 * the stuff needed as other L2 page table pages.
2227 * (2) Note that a process PT2TAB is special L2 page table
2228 * page. Its mapping in kernel_arena is permanent and can
2229 * be used no matter which process is current. Its mapping
2230 * in PT2MAP can be used only for current process.
2232 pmap->pm_pt2tab = kmem_alloc_attr(NB_IN_PT2TAB,
2233 M_NOWAIT | M_ZERO, 0, -1UL, pt_memattr);
2234 if (pmap->pm_pt2tab == NULL) {
2236 * QQQ: As struct pmap is allocated from UMA with
2237 * UMA_ZONE_NOFREE flag, it's important to leave
2238 * no allocation in pmap if initialization failed.
2240 kmem_free(pmap->pm_pt1, NB_IN_PT1);
2241 pmap->pm_pt1 = NULL;
2245 * QQQ: Each L2 page table page vm_page_t has pindex set to
2246 * pte1 index of virtual address mapped by this page.
2247 * It's not valid for non kernel PT2TABs themselves.
2248 * The pindex of these pages can not be altered because
2249 * of the way how they are allocated now. However, it
2250 * should not be a problem.
2254 mtx_lock_spin(&allpmaps_lock);
2256 * To avoid race with pmap_kenter_pte1() and pmap_kenter_pt2tab(),
2257 * kernel_vm_end_new is used here instead of kernel_vm_end.
2259 pte1_copy_nosync(kern_pt1, pmap->pm_pt1, KERNBASE,
2260 kernel_vm_end_new - 1);
2261 pte1_copy_nosync(kern_pt1, pmap->pm_pt1, vm_max_kernel_address,
2263 pt2tab_copy_nosync(kern_pt2tab, pmap->pm_pt2tab, KERNBASE,
2264 kernel_vm_end_new - 1);
2265 pt2tab_copy_nosync(kern_pt2tab, pmap->pm_pt2tab, vm_max_kernel_address,
2267 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
2268 mtx_unlock_spin(&allpmaps_lock);
2271 * Store PT2MAP PT2 pages (a.k.a. PT2TAB) in PT2TAB itself.
2272 * I.e. self reference mapping. The PT2TAB is private, however mapped
2273 * into shared PT2MAP space, so the mapping should be not global.
2275 pt2tab_pa = vtophys(pmap->pm_pt2tab);
2276 pte2p = pmap_pt2tab_entry(pmap, (vm_offset_t)PT2MAP);
2277 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE) {
2278 pt2tab_store(pte2p++, PTE2_KPT_NG(pa));
2281 /* Insert PT2MAP PT2s into pmap PT1. */
2282 pte1p = pmap_pte1(pmap, (vm_offset_t)PT2MAP);
2283 for (pa = pt2tab_pa, i = 0; i < NPT2_IN_PT2TAB; i++, pa += NB_IN_PT2) {
2284 pte1_store(pte1p++, PTE1_LINK(pa));
2288 * Now synchronize new mapping which was made above.
2290 pte1_sync_range(pmap->pm_pt1, NB_IN_PT1);
2291 pte2_sync_range(pmap->pm_pt2tab, NB_IN_PT2TAB);
2293 CPU_ZERO(&pmap->pm_active);
2294 TAILQ_INIT(&pmap->pm_pvchunk);
2295 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2302 pt2tab_user_is_empty(pt2_entry_t *tab)
2306 end = pt2tab_index(VM_MAXUSER_ADDRESS);
2307 for (i = 0; i < end; i++)
2308 if (tab[i] != 0) return (FALSE);
2313 * Release any resources held by the given physical map.
2314 * Called when a pmap initialized by pmap_pinit is being released.
2315 * Should only be called if the map contains no valid mappings.
2318 pmap_release(pmap_t pmap)
2321 vm_offset_t start, end;
2323 KASSERT(pmap->pm_stats.resident_count == 0,
2324 ("%s: pmap resident count %ld != 0", __func__,
2325 pmap->pm_stats.resident_count));
2326 KASSERT(pt2tab_user_is_empty(pmap->pm_pt2tab),
2327 ("%s: has allocated user PT2(s)", __func__));
2328 KASSERT(CPU_EMPTY(&pmap->pm_active),
2329 ("%s: pmap %p is active on some CPU(s)", __func__, pmap));
2331 mtx_lock_spin(&allpmaps_lock);
2332 LIST_REMOVE(pmap, pm_list);
2333 mtx_unlock_spin(&allpmaps_lock);
2336 start = pte1_index(KERNBASE) * sizeof(pt1_entry_t);
2337 end = (pte1_index(0xFFFFFFFF) + 1) * sizeof(pt1_entry_t);
2338 bzero((char *)pmap->pm_pt1 + start, end - start);
2340 start = pt2tab_index(KERNBASE) * sizeof(pt2_entry_t);
2341 end = (pt2tab_index(0xFFFFFFFF) + 1) * sizeof(pt2_entry_t);
2342 bzero((char *)pmap->pm_pt2tab + start, end - start);
2345 * We are leaving PT1 and PT2TAB allocated on released pmap,
2346 * so hopefully UMA vmspace_zone will always be inited with
2347 * UMA_ZONE_NOFREE flag.
2351 /*********************************************************
2353 * L2 table pages and their pages management routines.
2355 *********************************************************/
2358 * Virtual interface for L2 page table wire counting.
2360 * Each L2 page table in a page has own counter which counts a number of
2361 * valid mappings in a table. Global page counter counts mappings in all
2362 * tables in a page plus a single itself mapping in PT2TAB.
2364 * During a promotion we leave the associated L2 page table counter
2365 * untouched, so the table (strictly speaking a page which holds it)
2366 * is never freed if promoted.
2368 * If a page m->ref_count == 1 then no valid mappings exist in any L2 page
2369 * table in the page and the page itself is only mapped in PT2TAB.
2372 static __inline void
2373 pt2_wirecount_init(vm_page_t m)
2378 * Note: A page m is allocated with VM_ALLOC_WIRED flag and
2379 * m->ref_count should be already set correctly.
2380 * So, there is no need to set it again herein.
2382 for (i = 0; i < NPT2_IN_PG; i++)
2383 m->md.pt2_wirecount[i] = 0;
2386 static __inline void
2387 pt2_wirecount_inc(vm_page_t m, uint32_t pte1_idx)
2391 * Note: A just modificated pte2 (i.e. already allocated)
2392 * is acquiring one extra reference which must be
2393 * explicitly cleared. It influences the KASSERTs herein.
2394 * All L2 page tables in a page always belong to the same
2395 * pmap, so we allow only one extra reference for the page.
2397 KASSERT(m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] < (NPTE2_IN_PT2 + 1),
2398 ("%s: PT2 is overflowing ...", __func__));
2399 KASSERT(m->ref_count <= (NPTE2_IN_PG + 1),
2400 ("%s: PT2PG is overflowing ...", __func__));
2403 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]++;
2406 static __inline void
2407 pt2_wirecount_dec(vm_page_t m, uint32_t pte1_idx)
2410 KASSERT(m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] != 0,
2411 ("%s: PT2 is underflowing ...", __func__));
2412 KASSERT(m->ref_count > 1,
2413 ("%s: PT2PG is underflowing ...", __func__));
2416 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]--;
2419 static __inline void
2420 pt2_wirecount_set(vm_page_t m, uint32_t pte1_idx, uint16_t count)
2423 KASSERT(count <= NPTE2_IN_PT2,
2424 ("%s: invalid count %u", __func__, count));
2425 KASSERT(m->ref_count > m->md.pt2_wirecount[pte1_idx & PT2PG_MASK],
2426 ("%s: PT2PG corrupting (%u, %u) ...", __func__, m->ref_count,
2427 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]));
2429 m->ref_count -= m->md.pt2_wirecount[pte1_idx & PT2PG_MASK];
2430 m->ref_count += count;
2431 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] = count;
2433 KASSERT(m->ref_count <= (NPTE2_IN_PG + 1),
2434 ("%s: PT2PG is overflowed (%u) ...", __func__, m->ref_count));
2437 static __inline uint32_t
2438 pt2_wirecount_get(vm_page_t m, uint32_t pte1_idx)
2441 return (m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]);
2444 static __inline boolean_t
2445 pt2_is_empty(vm_page_t m, vm_offset_t va)
2448 return (m->md.pt2_wirecount[pte1_index(va) & PT2PG_MASK] == 0);
2451 static __inline boolean_t
2452 pt2_is_full(vm_page_t m, vm_offset_t va)
2455 return (m->md.pt2_wirecount[pte1_index(va) & PT2PG_MASK] ==
2459 static __inline boolean_t
2460 pt2pg_is_empty(vm_page_t m)
2463 return (m->ref_count == 1);
2467 * This routine is called if the L2 page table
2468 * is not mapped correctly.
2471 _pmap_allocpte2(pmap_t pmap, vm_offset_t va, u_int flags)
2477 vm_paddr_t pt2pg_pa, pt2_pa;
2479 pte1_idx = pte1_index(va);
2480 pte1p = pmap->pm_pt1 + pte1_idx;
2482 KASSERT(pte1_load(pte1p) == 0,
2483 ("%s: pm_pt1[%#x] is not zero: %#x", __func__, pte1_idx,
2486 pte2 = pt2tab_load(pmap_pt2tab_entry(pmap, va));
2487 if (!pte2_is_valid(pte2)) {
2489 * Install new PT2s page into pmap PT2TAB.
2491 m = vm_page_alloc_noobj(VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2493 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2495 rw_wunlock(&pvh_global_lock);
2497 rw_wlock(&pvh_global_lock);
2502 * Indicate the need to retry. While waiting,
2503 * the L2 page table page may have been allocated.
2507 m->pindex = pte1_idx & ~PT2PG_MASK;
2508 pmap->pm_stats.resident_count++;
2509 pt2pg_pa = pmap_pt2pg_init(pmap, va, m);
2511 pt2pg_pa = pte2_pa(pte2);
2512 m = PHYS_TO_VM_PAGE(pt2pg_pa);
2515 pt2_wirecount_inc(m, pte1_idx);
2516 pt2_pa = page_pt2pa(pt2pg_pa, pte1_idx);
2517 pte1_store(pte1p, PTE1_LINK(pt2_pa));
2523 pmap_allocpte2(pmap_t pmap, vm_offset_t va, u_int flags)
2526 pt1_entry_t *pte1p, pte1;
2529 pte1_idx = pte1_index(va);
2531 pte1p = pmap->pm_pt1 + pte1_idx;
2532 pte1 = pte1_load(pte1p);
2535 * This supports switching from a 1MB page to a
2538 if (pte1_is_section(pte1)) {
2539 (void)pmap_demote_pte1(pmap, pte1p, va);
2541 * Reload pte1 after demotion.
2543 * Note: Demotion can even fail as either PT2 is not find for
2544 * the virtual address or PT2PG can not be allocated.
2546 pte1 = pte1_load(pte1p);
2550 * If the L2 page table page is mapped, we just increment the
2551 * hold count, and activate it.
2553 if (pte1_is_link(pte1)) {
2554 m = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
2555 pt2_wirecount_inc(m, pte1_idx);
2558 * Here if the PT2 isn't mapped, or if it has
2561 m = _pmap_allocpte2(pmap, va, flags);
2562 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2570 * Schedule the specified unused L2 page table page to be freed. Specifically,
2571 * add the page to the specified list of pages that will be released to the
2572 * physical memory manager after the TLB has been updated.
2574 static __inline void
2575 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free)
2579 * Put page on a list so that it is released after
2580 * *ALL* TLB shootdown is done
2583 pmap_zero_page_check(m);
2585 m->flags |= PG_ZERO;
2586 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2590 * Unwire L2 page tables page.
2593 pmap_unwire_pt2pg(pmap_t pmap, vm_offset_t va, vm_page_t m)
2595 pt1_entry_t *pte1p, opte1 __unused;
2599 KASSERT(pt2pg_is_empty(m),
2600 ("%s: pmap %p PT2PG %p wired", __func__, pmap, m));
2603 * Unmap all L2 page tables in the page from L1 page table.
2605 * QQQ: Individual L2 page tables (except the last one) can be unmapped
2606 * earlier. However, we are doing that this way.
2608 KASSERT(m->pindex == (pte1_index(va) & ~PT2PG_MASK),
2609 ("%s: pmap %p va %#x PT2PG %p bad index", __func__, pmap, va, m));
2610 pte1p = pmap->pm_pt1 + m->pindex;
2611 for (i = 0; i < NPT2_IN_PG; i++, pte1p++) {
2612 KASSERT(m->md.pt2_wirecount[i] == 0,
2613 ("%s: pmap %p PT2 %u (PG %p) wired", __func__, pmap, i, m));
2614 opte1 = pte1_load(pte1p);
2615 if (pte1_is_link(opte1)) {
2618 * Flush intermediate TLB cache.
2620 pmap_tlb_flush(pmap, (m->pindex + i) << PTE1_SHIFT);
2624 KASSERT((opte1 == 0) || pte1_is_section(opte1),
2625 ("%s: pmap %p va %#x bad pte1 %x at %u", __func__,
2626 pmap, va, opte1, i));
2631 * Unmap the page from PT2TAB.
2633 pte2p = pmap_pt2tab_entry(pmap, va);
2634 (void)pt2tab_load_clear(pte2p);
2635 pmap_tlb_flush(pmap, pt2map_pt2pg(va));
2638 pmap->pm_stats.resident_count--;
2641 * This barrier is so that the ordinary store unmapping
2642 * the L2 page table page is globally performed before TLB shoot-
2650 * Decrements a L2 page table page's wire count, which is used to record the
2651 * number of valid page table entries within the page. If the wire count
2652 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2653 * page table page was unmapped and FALSE otherwise.
2655 static __inline boolean_t
2656 pmap_unwire_pt2(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2658 pt2_wirecount_dec(m, pte1_index(va));
2659 if (pt2pg_is_empty(m)) {
2661 * QQQ: Wire count is zero, so whole page should be zero and
2662 * we can set PG_ZERO flag to it.
2663 * Note that when promotion is enabled, it takes some
2664 * more efforts. See pmap_unwire_pt2_all() below.
2666 pmap_unwire_pt2pg(pmap, va, m);
2667 pmap_add_delayed_free_list(m, free);
2674 * Drop a L2 page table page's wire count at once, which is used to record
2675 * the number of valid L2 page table entries within the page. If the wire
2676 * count drops to zero, then the L2 page table page is unmapped.
2678 static __inline void
2679 pmap_unwire_pt2_all(pmap_t pmap, vm_offset_t va, vm_page_t m,
2680 struct spglist *free)
2682 u_int pte1_idx = pte1_index(va);
2684 KASSERT(m->pindex == (pte1_idx & ~PT2PG_MASK),
2685 ("%s: PT2 page's pindex is wrong", __func__));
2686 KASSERT(m->ref_count > pt2_wirecount_get(m, pte1_idx),
2687 ("%s: bad pt2 wire count %u > %u", __func__, m->ref_count,
2688 pt2_wirecount_get(m, pte1_idx)));
2691 * It's possible that the L2 page table was never used.
2692 * It happened in case that a section was created without promotion.
2694 if (pt2_is_full(m, va)) {
2695 pt2_wirecount_set(m, pte1_idx, 0);
2698 * QQQ: We clear L2 page table now, so when L2 page table page
2699 * is going to be freed, we can set it PG_ZERO flag ...
2700 * This function is called only on section mappings, so
2701 * hopefully it's not to big overload.
2703 * XXX: If pmap is current, existing PT2MAP mapping could be
2706 pmap_zero_page_area(m, page_pt2off(pte1_idx), NB_IN_PT2);
2710 KASSERT(pt2_is_empty(m, va), ("%s: PT2 is not empty (%u)",
2711 __func__, pt2_wirecount_get(m, pte1_idx)));
2713 if (pt2pg_is_empty(m)) {
2714 pmap_unwire_pt2pg(pmap, va, m);
2715 pmap_add_delayed_free_list(m, free);
2720 * After removing a L2 page table entry, this routine is used to
2721 * conditionally free the page, and manage the hold/wire counts.
2724 pmap_unuse_pt2(pmap_t pmap, vm_offset_t va, struct spglist *free)
2729 if (va >= VM_MAXUSER_ADDRESS)
2731 pte1 = pte1_load(pmap_pte1(pmap, va));
2732 mpte = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
2733 return (pmap_unwire_pt2(pmap, va, mpte, free));
2736 /*************************************
2738 * Page management routines.
2740 *************************************/
2742 static const uint32_t pc_freemask[_NPCM] = {
2743 [0 ... _NPCM - 2] = PC_FREEN,
2744 [_NPCM - 1] = PC_FREEL
2747 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2748 "Current number of pv entries");
2751 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2753 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2754 "Current number of pv entry chunks");
2755 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2756 "Current number of pv entry chunks allocated");
2757 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2758 "Current number of pv entry chunks frees");
2759 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail,
2760 0, "Number of times tried to get a chunk page but failed.");
2762 static long pv_entry_frees, pv_entry_allocs;
2763 static int pv_entry_spare;
2765 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2766 "Current number of pv entry frees");
2767 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs,
2768 0, "Current number of pv entry allocs");
2769 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2770 "Current number of spare pv entries");
2774 * Is given page managed?
2776 static __inline bool
2777 is_managed(vm_paddr_t pa)
2781 m = PHYS_TO_VM_PAGE(pa);
2784 return ((m->oflags & VPO_UNMANAGED) == 0);
2787 static __inline bool
2788 pte1_is_managed(pt1_entry_t pte1)
2791 return (is_managed(pte1_pa(pte1)));
2794 static __inline bool
2795 pte2_is_managed(pt2_entry_t pte2)
2798 return (is_managed(pte2_pa(pte2)));
2802 * We are in a serious low memory condition. Resort to
2803 * drastic measures to free some pages so we can allocate
2804 * another pv entry chunk.
2807 pmap_pv_reclaim(pmap_t locked_pmap)
2810 struct pv_chunk *pc;
2811 struct md_page *pvh;
2814 pt2_entry_t *pte2p, tpte2;
2818 struct spglist free;
2820 int bit, field, freed;
2822 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2826 TAILQ_INIT(&newtail);
2827 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2828 SLIST_EMPTY(&free))) {
2829 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2830 if (pmap != pc->pc_pmap) {
2832 if (pmap != locked_pmap)
2836 /* Avoid deadlock and lock recursion. */
2837 if (pmap > locked_pmap)
2839 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2841 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2847 * Destroy every non-wired, 4 KB page mapping in the chunk.
2850 for (field = 0; field < _NPCM; field++) {
2851 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2852 inuse != 0; inuse &= ~(1UL << bit)) {
2853 bit = ffs(inuse) - 1;
2854 pv = &pc->pc_pventry[field * 32 + bit];
2856 pte1p = pmap_pte1(pmap, va);
2857 if (pte1_is_section(pte1_load(pte1p)))
2859 pte2p = pmap_pte2(pmap, va);
2860 tpte2 = pte2_load(pte2p);
2861 if ((tpte2 & PTE2_W) == 0)
2862 tpte2 = pte2_load_clear(pte2p);
2863 pmap_pte2_release(pte2p);
2864 if ((tpte2 & PTE2_W) != 0)
2867 ("pmap_pv_reclaim: pmap %p va %#x zero pte",
2869 pmap_tlb_flush(pmap, va);
2870 m = PHYS_TO_VM_PAGE(pte2_pa(tpte2));
2871 if (pte2_is_dirty(tpte2))
2873 if ((tpte2 & PTE2_A) != 0)
2874 vm_page_aflag_set(m, PGA_REFERENCED);
2875 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2876 if (TAILQ_EMPTY(&m->md.pv_list) &&
2877 (m->flags & PG_FICTITIOUS) == 0) {
2878 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2879 if (TAILQ_EMPTY(&pvh->pv_list)) {
2880 vm_page_aflag_clear(m,
2884 pc->pc_map[field] |= 1UL << bit;
2885 pmap_unuse_pt2(pmap, va, &free);
2890 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2893 /* Every freed mapping is for a 4 KB page. */
2894 pmap->pm_stats.resident_count -= freed;
2895 PV_STAT(pv_entry_frees += freed);
2896 PV_STAT(pv_entry_spare += freed);
2897 pv_entry_count -= freed;
2898 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2899 for (field = 0; field < _NPCM; field++)
2900 if (pc->pc_map[field] != pc_freemask[field]) {
2901 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2903 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2906 * One freed pv entry in locked_pmap is
2909 if (pmap == locked_pmap)
2913 if (field == _NPCM) {
2914 PV_STAT(pv_entry_spare -= _NPCPV);
2915 PV_STAT(pc_chunk_count--);
2916 PV_STAT(pc_chunk_frees++);
2917 /* Entire chunk is free; return it. */
2918 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2919 pmap_qremove((vm_offset_t)pc, 1);
2920 pmap_pte2list_free(&pv_vafree, (vm_offset_t)pc);
2925 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2927 if (pmap != locked_pmap)
2930 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2931 m_pc = SLIST_FIRST(&free);
2932 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2933 /* Recycle a freed page table page. */
2934 m_pc->ref_count = 1;
2937 vm_page_free_pages_toq(&free, false);
2942 free_pv_chunk(struct pv_chunk *pc)
2946 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2947 PV_STAT(pv_entry_spare -= _NPCPV);
2948 PV_STAT(pc_chunk_count--);
2949 PV_STAT(pc_chunk_frees++);
2950 /* entire chunk is free, return it */
2951 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2952 pmap_qremove((vm_offset_t)pc, 1);
2953 vm_page_unwire_noq(m);
2955 pmap_pte2list_free(&pv_vafree, (vm_offset_t)pc);
2959 * Free the pv_entry back to the free list.
2962 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2964 struct pv_chunk *pc;
2965 int idx, field, bit;
2967 rw_assert(&pvh_global_lock, RA_WLOCKED);
2968 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2969 PV_STAT(pv_entry_frees++);
2970 PV_STAT(pv_entry_spare++);
2972 pc = pv_to_chunk(pv);
2973 idx = pv - &pc->pc_pventry[0];
2976 pc->pc_map[field] |= 1ul << bit;
2977 for (idx = 0; idx < _NPCM; idx++)
2978 if (pc->pc_map[idx] != pc_freemask[idx]) {
2980 * 98% of the time, pc is already at the head of the
2981 * list. If it isn't already, move it to the head.
2983 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2985 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2986 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2991 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2996 * Get a new pv_entry, allocating a block from the system
3000 get_pv_entry(pmap_t pmap, boolean_t try)
3002 static const struct timeval printinterval = { 60, 0 };
3003 static struct timeval lastprint;
3006 struct pv_chunk *pc;
3009 rw_assert(&pvh_global_lock, RA_WLOCKED);
3010 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3011 PV_STAT(pv_entry_allocs++);
3013 if (pv_entry_count > pv_entry_high_water)
3014 if (ratecheck(&lastprint, &printinterval))
3015 printf("Approaching the limit on PV entries, consider "
3016 "increasing either the vm.pmap.shpgperproc or the "
3017 "vm.pmap.pv_entries tunable.\n");
3019 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3021 for (field = 0; field < _NPCM; field++) {
3022 if (pc->pc_map[field]) {
3023 bit = ffs(pc->pc_map[field]) - 1;
3027 if (field < _NPCM) {
3028 pv = &pc->pc_pventry[field * 32 + bit];
3029 pc->pc_map[field] &= ~(1ul << bit);
3030 /* If this was the last item, move it to tail */
3031 for (field = 0; field < _NPCM; field++)
3032 if (pc->pc_map[field] != 0) {
3033 PV_STAT(pv_entry_spare--);
3034 return (pv); /* not full, return */
3036 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3037 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3038 PV_STAT(pv_entry_spare--);
3043 * Access to the pte2list "pv_vafree" is synchronized by the pvh
3044 * global lock. If "pv_vafree" is currently non-empty, it will
3045 * remain non-empty until pmap_pte2list_alloc() completes.
3047 if (pv_vafree == 0 ||
3048 (m = vm_page_alloc_noobj(VM_ALLOC_WIRED)) == NULL) {
3051 PV_STAT(pc_chunk_tryfail++);
3054 m = pmap_pv_reclaim(pmap);
3058 PV_STAT(pc_chunk_count++);
3059 PV_STAT(pc_chunk_allocs++);
3060 pc = (struct pv_chunk *)pmap_pte2list_alloc(&pv_vafree);
3061 pmap_qenter((vm_offset_t)pc, &m, 1);
3063 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
3064 for (field = 1; field < _NPCM; field++)
3065 pc->pc_map[field] = pc_freemask[field];
3066 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
3067 pv = &pc->pc_pventry[0];
3068 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3069 PV_STAT(pv_entry_spare += _NPCPV - 1);
3074 * Create a pv entry for page at pa for
3078 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
3082 rw_assert(&pvh_global_lock, RA_WLOCKED);
3083 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3084 pv = get_pv_entry(pmap, FALSE);
3086 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3089 static __inline pv_entry_t
3090 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3094 rw_assert(&pvh_global_lock, RA_WLOCKED);
3095 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3096 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3097 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3105 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3109 pv = pmap_pvh_remove(pvh, pmap, va);
3110 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3111 free_pv_entry(pmap, pv);
3115 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
3117 struct md_page *pvh;
3119 rw_assert(&pvh_global_lock, RA_WLOCKED);
3120 pmap_pvh_free(&m->md, pmap, va);
3121 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
3122 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3123 if (TAILQ_EMPTY(&pvh->pv_list))
3124 vm_page_aflag_clear(m, PGA_WRITEABLE);
3129 pmap_pv_demote_pte1(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3131 struct md_page *pvh;
3133 vm_offset_t va_last;
3136 rw_assert(&pvh_global_lock, RA_WLOCKED);
3137 KASSERT((pa & PTE1_OFFSET) == 0,
3138 ("pmap_pv_demote_pte1: pa is not 1mpage aligned"));
3141 * Transfer the 1mpage's pv entry for this mapping to the first
3144 pvh = pa_to_pvh(pa);
3145 va = pte1_trunc(va);
3146 pv = pmap_pvh_remove(pvh, pmap, va);
3147 KASSERT(pv != NULL, ("pmap_pv_demote_pte1: pv not found"));
3148 m = PHYS_TO_VM_PAGE(pa);
3149 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3150 /* Instantiate the remaining NPTE2_IN_PT2 - 1 pv entries. */
3151 va_last = va + PTE1_SIZE - PAGE_SIZE;
3154 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3155 ("pmap_pv_demote_pte1: page %p is not managed", m));
3157 pmap_insert_entry(pmap, va, m);
3158 } while (va < va_last);
3161 #if VM_NRESERVLEVEL > 0
3163 pmap_pv_promote_pte1(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3165 struct md_page *pvh;
3167 vm_offset_t va_last;
3170 rw_assert(&pvh_global_lock, RA_WLOCKED);
3171 KASSERT((pa & PTE1_OFFSET) == 0,
3172 ("pmap_pv_promote_pte1: pa is not 1mpage aligned"));
3175 * Transfer the first page's pv entry for this mapping to the
3176 * 1mpage's pv list. Aside from avoiding the cost of a call
3177 * to get_pv_entry(), a transfer avoids the possibility that
3178 * get_pv_entry() calls pmap_pv_reclaim() and that pmap_pv_reclaim()
3179 * removes one of the mappings that is being promoted.
3181 m = PHYS_TO_VM_PAGE(pa);
3182 va = pte1_trunc(va);
3183 pv = pmap_pvh_remove(&m->md, pmap, va);
3184 KASSERT(pv != NULL, ("pmap_pv_promote_pte1: pv not found"));
3185 pvh = pa_to_pvh(pa);
3186 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3187 /* Free the remaining NPTE2_IN_PT2 - 1 pv entries. */
3188 va_last = va + PTE1_SIZE - PAGE_SIZE;
3192 pmap_pvh_free(&m->md, pmap, va);
3193 } while (va < va_last);
3198 * Conditionally create a pv entry.
3201 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
3205 rw_assert(&pvh_global_lock, RA_WLOCKED);
3206 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3207 if (pv_entry_count < pv_entry_high_water &&
3208 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
3210 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3217 * Create the pv entries for each of the pages within a section.
3220 pmap_pv_insert_pte1(pmap_t pmap, vm_offset_t va, pt1_entry_t pte1, u_int flags)
3222 struct md_page *pvh;
3226 rw_assert(&pvh_global_lock, RA_WLOCKED);
3227 noreclaim = (flags & PMAP_ENTER_NORECLAIM) != 0;
3228 if ((noreclaim && pv_entry_count >= pv_entry_high_water) ||
3229 (pv = get_pv_entry(pmap, noreclaim)) == NULL)
3232 pvh = pa_to_pvh(pte1_pa(pte1));
3233 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3238 pmap_tlb_flush_pte1(pmap_t pmap, vm_offset_t va, pt1_entry_t npte1)
3241 /* Kill all the small mappings or the big one only. */
3242 if (pte1_is_section(npte1))
3243 pmap_tlb_flush_range(pmap, pte1_trunc(va), PTE1_SIZE);
3245 pmap_tlb_flush(pmap, pte1_trunc(va));
3249 * Update kernel pte1 on all pmaps.
3251 * The following function is called only on one cpu with disabled interrupts.
3252 * In SMP case, smp_rendezvous_cpus() is used to stop other cpus. This way
3253 * nobody can invoke explicit hardware table walk during the update of pte1.
3254 * Unsolicited hardware table walk can still happen, invoked by speculative
3255 * data or instruction prefetch or even by speculative hardware table walk.
3257 * The break-before-make approach should be implemented here. However, it's
3258 * not so easy to do that for kernel mappings as it would be unhappy to unmap
3259 * itself unexpectedly but voluntarily.
3262 pmap_update_pte1_kernel(vm_offset_t va, pt1_entry_t npte1)
3268 * Get current pmap. Interrupts should be disabled here
3269 * so PCPU_GET() is done atomically.
3271 pmap = PCPU_GET(curpmap);
3276 * (1) Change pte1 on current pmap.
3277 * (2) Flush all obsolete TLB entries on current CPU.
3278 * (3) Change pte1 on all pmaps.
3279 * (4) Flush all obsolete TLB entries on all CPUs in SMP case.
3282 pte1p = pmap_pte1(pmap, va);
3283 pte1_store(pte1p, npte1);
3285 /* Kill all the small mappings or the big one only. */
3286 if (pte1_is_section(npte1)) {
3287 pmap_pte1_kern_promotions++;
3288 tlb_flush_range_local(pte1_trunc(va), PTE1_SIZE);
3290 pmap_pte1_kern_demotions++;
3291 tlb_flush_local(pte1_trunc(va));
3295 * In SMP case, this function is called when all cpus are at smp
3296 * rendezvous, so there is no need to use 'allpmaps_lock' lock here.
3297 * In UP case, the function is called with this lock locked.
3299 LIST_FOREACH(pmap, &allpmaps, pm_list) {
3300 pte1p = pmap_pte1(pmap, va);
3301 pte1_store(pte1p, npte1);
3305 /* Kill all the small mappings or the big one only. */
3306 if (pte1_is_section(npte1))
3307 tlb_flush_range(pte1_trunc(va), PTE1_SIZE);
3309 tlb_flush(pte1_trunc(va));
3314 struct pte1_action {
3317 u_int update; /* CPU that updates the PTE1 */
3321 pmap_update_pte1_action(void *arg)
3323 struct pte1_action *act = arg;
3325 if (act->update == PCPU_GET(cpuid))
3326 pmap_update_pte1_kernel(act->va, act->npte1);
3330 * Change pte1 on current pmap.
3331 * Note that kernel pte1 must be changed on all pmaps.
3333 * According to the architecture reference manual published by ARM,
3334 * the behaviour is UNPREDICTABLE when two or more TLB entries map the same VA.
3335 * According to this manual, UNPREDICTABLE behaviours must never happen in
3336 * a viable system. In contrast, on x86 processors, it is not specified which
3337 * TLB entry mapping the virtual address will be used, but the MMU doesn't
3338 * generate a bogus translation the way it does on Cortex-A8 rev 2 (Beaglebone
3341 * It's a problem when either promotion or demotion is being done. The pte1
3342 * update and appropriate TLB flush must be done atomically in general.
3345 pmap_change_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va,
3349 if (pmap == kernel_pmap) {
3350 struct pte1_action act;
3355 act.update = PCPU_GET(cpuid);
3356 smp_rendezvous_cpus(all_cpus, smp_no_rendezvous_barrier,
3357 pmap_update_pte1_action, NULL, &act);
3363 * Use break-before-make approach for changing userland
3364 * mappings. It can cause L1 translation aborts on other
3365 * cores in SMP case. So, special treatment is implemented
3366 * in pmap_fault(). To reduce the likelihood that another core
3367 * will be affected by the broken mapping, disable interrupts
3368 * until the mapping change is completed.
3370 cspr = disable_interrupts(PSR_I | PSR_F);
3372 pmap_tlb_flush_pte1(pmap, va, npte1);
3373 pte1_store(pte1p, npte1);
3374 restore_interrupts(cspr);
3379 pmap_change_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va,
3383 if (pmap == kernel_pmap) {
3384 mtx_lock_spin(&allpmaps_lock);
3385 pmap_update_pte1_kernel(va, npte1);
3386 mtx_unlock_spin(&allpmaps_lock);
3391 * Use break-before-make approach for changing userland
3392 * mappings. It's absolutely safe in UP case when interrupts
3395 cspr = disable_interrupts(PSR_I | PSR_F);
3397 pmap_tlb_flush_pte1(pmap, va, npte1);
3398 pte1_store(pte1p, npte1);
3399 restore_interrupts(cspr);
3404 #if VM_NRESERVLEVEL > 0
3406 * Tries to promote the NPTE2_IN_PT2, contiguous 4KB page mappings that are
3407 * within a single page table page (PT2) to a single 1MB page mapping.
3408 * For promotion to occur, two conditions must be met: (1) the 4KB page
3409 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3410 * mappings must have identical characteristics.
3412 * Managed (PG_MANAGED) mappings within the kernel address space are not
3413 * promoted. The reason is that kernel PTE1s are replicated in each pmap but
3414 * pmap_remove_write(), pmap_clear_modify(), and pmap_clear_reference() only
3415 * read the PTE1 from the kernel pmap.
3418 pmap_promote_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3421 pt2_entry_t *fpte2p, fpte2, fpte2_fav;
3422 pt2_entry_t *pte2p, pte2;
3423 vm_offset_t pteva __unused;
3424 vm_page_t m __unused;
3426 PDEBUG(6, printf("%s(%p): try for va %#x pte1 %#x at %p\n", __func__,
3427 pmap, va, pte1_load(pte1p), pte1p));
3429 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3432 * Examine the first PTE2 in the specified PT2. Abort if this PTE2 is
3433 * either invalid, unused, or does not map the first 4KB physical page
3434 * within a 1MB page.
3436 fpte2p = pmap_pte2_quick(pmap, pte1_trunc(va));
3437 fpte2 = pte2_load(fpte2p);
3438 if ((fpte2 & ((PTE2_FRAME & PTE1_OFFSET) | PTE2_A | PTE2_V)) !=
3439 (PTE2_A | PTE2_V)) {
3440 pmap_pte1_p_failures++;
3441 CTR3(KTR_PMAP, "%s: failure(1) for va %#x in pmap %p",
3442 __func__, va, pmap);
3445 if (pte2_is_managed(fpte2) && pmap == kernel_pmap) {
3446 pmap_pte1_p_failures++;
3447 CTR3(KTR_PMAP, "%s: failure(2) for va %#x in pmap %p",
3448 __func__, va, pmap);
3451 if ((fpte2 & (PTE2_NM | PTE2_RO)) == PTE2_NM) {
3453 * When page is not modified, PTE2_RO can be set without
3454 * a TLB invalidation.
3457 pte2_store(fpte2p, fpte2);
3461 * Examine each of the other PTE2s in the specified PT2. Abort if this
3462 * PTE2 maps an unexpected 4KB physical page or does not have identical
3463 * characteristics to the first PTE2.
3465 fpte2_fav = (fpte2 & (PTE2_FRAME | PTE2_A | PTE2_V));
3466 fpte2_fav += PTE1_SIZE - PTE2_SIZE; /* examine from the end */
3467 for (pte2p = fpte2p + NPTE2_IN_PT2 - 1; pte2p > fpte2p; pte2p--) {
3468 pte2 = pte2_load(pte2p);
3469 if ((pte2 & (PTE2_FRAME | PTE2_A | PTE2_V)) != fpte2_fav) {
3470 pmap_pte1_p_failures++;
3471 CTR3(KTR_PMAP, "%s: failure(3) for va %#x in pmap %p",
3472 __func__, va, pmap);
3475 if ((pte2 & (PTE2_NM | PTE2_RO)) == PTE2_NM) {
3477 * When page is not modified, PTE2_RO can be set
3478 * without a TLB invalidation. See note above.
3481 pte2_store(pte2p, pte2);
3482 pteva = pte1_trunc(va) | (pte2 & PTE1_OFFSET &
3484 CTR3(KTR_PMAP, "%s: protect for va %#x in pmap %p",
3485 __func__, pteva, pmap);
3487 if ((pte2 & PTE2_PROMOTE) != (fpte2 & PTE2_PROMOTE)) {
3488 pmap_pte1_p_failures++;
3489 CTR3(KTR_PMAP, "%s: failure(4) for va %#x in pmap %p",
3490 __func__, va, pmap);
3494 fpte2_fav -= PTE2_SIZE;
3497 * The page table page in its current state will stay in PT2TAB
3498 * until the PTE1 mapping the section is demoted by pmap_demote_pte1()
3499 * or destroyed by pmap_remove_pte1().
3501 * Note that L2 page table size is not equal to PAGE_SIZE.
3503 m = PHYS_TO_VM_PAGE(trunc_page(pte1_link_pa(pte1_load(pte1p))));
3504 KASSERT(m >= vm_page_array && m < &vm_page_array[vm_page_array_size],
3505 ("%s: PT2 page is out of range", __func__));
3506 KASSERT(m->pindex == (pte1_index(va) & ~PT2PG_MASK),
3507 ("%s: PT2 page's pindex is wrong", __func__));
3510 * Get pte1 from pte2 format.
3512 npte1 = (fpte2 & PTE1_FRAME) | ATTR_TO_L1(fpte2) | PTE1_V;
3515 * Promote the pv entries.
3517 if (pte2_is_managed(fpte2))
3518 pmap_pv_promote_pte1(pmap, va, pte1_pa(npte1));
3521 * Promote the mappings.
3523 pmap_change_pte1(pmap, pte1p, va, npte1);
3525 pmap_pte1_promotions++;
3526 CTR3(KTR_PMAP, "%s: success for va %#x in pmap %p",
3527 __func__, va, pmap);
3529 PDEBUG(6, printf("%s(%p): success for va %#x pte1 %#x(%#x) at %p\n",
3530 __func__, pmap, va, npte1, pte1_load(pte1p), pte1p));
3532 #endif /* VM_NRESERVLEVEL > 0 */
3535 * Zero L2 page table page.
3537 static __inline void
3538 pmap_clear_pt2(pt2_entry_t *fpte2p)
3542 for (pte2p = fpte2p; pte2p < fpte2p + NPTE2_IN_PT2; pte2p++)
3548 * Removes a 1MB page mapping from the kernel pmap.
3551 pmap_remove_kernel_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3555 pt2_entry_t *fpte2p;
3558 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3559 m = pmap_pt2_page(pmap, va);
3562 * QQQ: Is this function called only on promoted pte1?
3563 * We certainly do section mappings directly
3564 * (without promotion) in kernel !!!
3566 panic("%s: missing pt2 page", __func__);
3568 pte1_idx = pte1_index(va);
3571 * Initialize the L2 page table.
3573 fpte2p = page_pt2(pt2map_pt2pg(va), pte1_idx);
3574 pmap_clear_pt2(fpte2p);
3577 * Remove the mapping.
3579 pt2_pa = page_pt2pa(VM_PAGE_TO_PHYS(m), pte1_idx);
3580 pmap_kenter_pte1(va, PTE1_LINK(pt2_pa));
3583 * QQQ: We do not need to invalidate PT2MAP mapping
3584 * as we did not change it. I.e. the L2 page table page
3585 * was and still is mapped the same way.
3590 * Do the things to unmap a section in a process
3593 pmap_remove_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t sva,
3594 struct spglist *free)
3597 struct md_page *pvh;
3598 vm_offset_t eva, va;
3601 PDEBUG(6, printf("%s(%p): va %#x pte1 %#x at %p\n", __func__, pmap, sva,
3602 pte1_load(pte1p), pte1p));
3604 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3605 KASSERT((sva & PTE1_OFFSET) == 0,
3606 ("%s: sva is not 1mpage aligned", __func__));
3609 * Clear and invalidate the mapping. It should occupy one and only TLB
3610 * entry. So, pmap_tlb_flush() called with aligned address should be
3613 opte1 = pte1_load_clear(pte1p);
3614 pmap_tlb_flush(pmap, sva);
3616 if (pte1_is_wired(opte1))
3617 pmap->pm_stats.wired_count -= PTE1_SIZE / PAGE_SIZE;
3618 pmap->pm_stats.resident_count -= PTE1_SIZE / PAGE_SIZE;
3619 if (pte1_is_managed(opte1)) {
3620 pvh = pa_to_pvh(pte1_pa(opte1));
3621 pmap_pvh_free(pvh, pmap, sva);
3622 eva = sva + PTE1_SIZE;
3623 for (va = sva, m = PHYS_TO_VM_PAGE(pte1_pa(opte1));
3624 va < eva; va += PAGE_SIZE, m++) {
3625 if (pte1_is_dirty(opte1))
3628 vm_page_aflag_set(m, PGA_REFERENCED);
3629 if (TAILQ_EMPTY(&m->md.pv_list) &&
3630 TAILQ_EMPTY(&pvh->pv_list))
3631 vm_page_aflag_clear(m, PGA_WRITEABLE);
3634 if (pmap == kernel_pmap) {
3636 * L2 page table(s) can't be removed from kernel map as
3637 * kernel counts on it (stuff around pmap_growkernel()).
3639 pmap_remove_kernel_pte1(pmap, pte1p, sva);
3642 * Get associated L2 page table page.
3643 * It's possible that the page was never allocated.
3645 m = pmap_pt2_page(pmap, sva);
3647 pmap_unwire_pt2_all(pmap, sva, m, free);
3652 * Fills L2 page table page with mappings to consecutive physical pages.
3654 static __inline void
3655 pmap_fill_pt2(pt2_entry_t *fpte2p, pt2_entry_t npte2)
3659 for (pte2p = fpte2p; pte2p < fpte2p + NPTE2_IN_PT2; pte2p++) {
3660 pte2_store(pte2p, npte2);
3666 * Tries to demote a 1MB page mapping. If demotion fails, the
3667 * 1MB page mapping is invalidated.
3670 pmap_demote_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3672 pt1_entry_t opte1, npte1;
3673 pt2_entry_t *fpte2p, npte2;
3674 vm_paddr_t pt2pg_pa, pt2_pa;
3676 struct spglist free;
3677 uint32_t pte1_idx, isnew = 0;
3679 PDEBUG(6, printf("%s(%p): try for va %#x pte1 %#x at %p\n", __func__,
3680 pmap, va, pte1_load(pte1p), pte1p));
3682 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3684 opte1 = pte1_load(pte1p);
3685 KASSERT(pte1_is_section(opte1), ("%s: opte1 not a section", __func__));
3687 if ((opte1 & PTE1_A) == 0 || (m = pmap_pt2_page(pmap, va)) == NULL) {
3688 KASSERT(!pte1_is_wired(opte1),
3689 ("%s: PT2 page for a wired mapping is missing", __func__));
3692 * Invalidate the 1MB page mapping and return
3693 * "failure" if the mapping was never accessed or the
3694 * allocation of the new page table page fails.
3696 if ((opte1 & PTE1_A) == 0 ||
3697 (m = vm_page_alloc_noobj(VM_ALLOC_WIRED)) == NULL) {
3699 pmap_remove_pte1(pmap, pte1p, pte1_trunc(va), &free);
3700 vm_page_free_pages_toq(&free, false);
3701 CTR3(KTR_PMAP, "%s: failure for va %#x in pmap %p",
3702 __func__, va, pmap);
3705 m->pindex = pte1_index(va) & ~PT2PG_MASK;
3706 if (va < VM_MAXUSER_ADDRESS)
3707 pmap->pm_stats.resident_count++;
3712 * We init all L2 page tables in the page even if
3713 * we are going to change everything for one L2 page
3716 pt2pg_pa = pmap_pt2pg_init(pmap, va, m);
3718 if (va < VM_MAXUSER_ADDRESS) {
3719 if (pt2_is_empty(m, va))
3720 isnew = 1; /* Demoting section w/o promotion. */
3723 KASSERT(pt2_is_full(m, va), ("%s: bad PT2 wire"
3724 " count %u", __func__,
3725 pt2_wirecount_get(m, pte1_index(va))));
3730 pt2pg_pa = VM_PAGE_TO_PHYS(m);
3731 pte1_idx = pte1_index(va);
3733 * If the pmap is current, then the PT2MAP can provide access to
3734 * the page table page (promoted L2 page tables are not unmapped).
3735 * Otherwise, temporarily map the L2 page table page (m) into
3736 * the kernel's address space at either PADDR1 or PADDR2.
3738 * Note that L2 page table size is not equal to PAGE_SIZE.
3740 if (pmap_is_current(pmap))
3741 fpte2p = page_pt2(pt2map_pt2pg(va), pte1_idx);
3742 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
3743 if (pte2_pa(pte2_load(PMAP1)) != pt2pg_pa) {
3744 pte2_store(PMAP1, PTE2_KPT(pt2pg_pa));
3746 PMAP1cpu = PCPU_GET(cpuid);
3748 tlb_flush_local((vm_offset_t)PADDR1);
3752 if (PMAP1cpu != PCPU_GET(cpuid)) {
3753 PMAP1cpu = PCPU_GET(cpuid);
3754 tlb_flush_local((vm_offset_t)PADDR1);
3759 fpte2p = page_pt2((vm_offset_t)PADDR1, pte1_idx);
3761 mtx_lock(&PMAP2mutex);
3762 if (pte2_pa(pte2_load(PMAP2)) != pt2pg_pa) {
3763 pte2_store(PMAP2, PTE2_KPT(pt2pg_pa));
3764 tlb_flush((vm_offset_t)PADDR2);
3766 fpte2p = page_pt2((vm_offset_t)PADDR2, pte1_idx);
3768 pt2_pa = page_pt2pa(pt2pg_pa, pte1_idx);
3769 npte1 = PTE1_LINK(pt2_pa);
3771 KASSERT((opte1 & PTE1_A) != 0,
3772 ("%s: opte1 is missing PTE1_A", __func__));
3773 KASSERT((opte1 & (PTE1_NM | PTE1_RO)) != PTE1_NM,
3774 ("%s: opte1 has PTE1_NM", __func__));
3777 * Get pte2 from pte1 format.
3779 npte2 = pte1_pa(opte1) | ATTR_TO_L2(opte1) | PTE2_V;
3782 * If the L2 page table page is new, initialize it. If the mapping
3783 * has changed attributes, update the page table entries.
3786 pt2_wirecount_set(m, pte1_idx, NPTE2_IN_PT2);
3787 pmap_fill_pt2(fpte2p, npte2);
3788 } else if ((pte2_load(fpte2p) & PTE2_PROMOTE) !=
3789 (npte2 & PTE2_PROMOTE))
3790 pmap_fill_pt2(fpte2p, npte2);
3792 KASSERT(pte2_pa(pte2_load(fpte2p)) == pte2_pa(npte2),
3793 ("%s: fpte2p and npte2 map different physical addresses",
3796 if (fpte2p == PADDR2)
3797 mtx_unlock(&PMAP2mutex);
3800 * Demote the mapping. This pmap is locked. The old PTE1 has
3801 * PTE1_A set. If the old PTE1 has not PTE1_RO set, it also
3802 * has not PTE1_NM set. Thus, there is no danger of a race with
3803 * another processor changing the setting of PTE1_A and/or PTE1_NM
3804 * between the read above and the store below.
3806 pmap_change_pte1(pmap, pte1p, va, npte1);
3809 * Demote the pv entry. This depends on the earlier demotion
3810 * of the mapping. Specifically, the (re)creation of a per-
3811 * page pv entry might trigger the execution of pmap_pv_reclaim(),
3812 * which might reclaim a newly (re)created per-page pv entry
3813 * and destroy the associated mapping. In order to destroy
3814 * the mapping, the PTE1 must have already changed from mapping
3815 * the 1mpage to referencing the page table page.
3817 if (pte1_is_managed(opte1))
3818 pmap_pv_demote_pte1(pmap, va, pte1_pa(opte1));
3820 pmap_pte1_demotions++;
3821 CTR3(KTR_PMAP, "%s: success for va %#x in pmap %p",
3822 __func__, va, pmap);
3824 PDEBUG(6, printf("%s(%p): success for va %#x pte1 %#x(%#x) at %p\n",
3825 __func__, pmap, va, npte1, pte1_load(pte1p), pte1p));
3830 * Insert the given physical page (p) at
3831 * the specified virtual address (v) in the
3832 * target physical map with the protection requested.
3834 * If specified, the page will be wired down, meaning
3835 * that the related pte can not be reclaimed.
3837 * NB: This is the only routine which MAY NOT lazy-evaluate
3838 * or lose information. That is, this routine must actually
3839 * insert this page into the given map NOW.
3842 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3843 u_int flags, int8_t psind)
3847 pt2_entry_t npte2, opte2;
3850 vm_page_t mpte2, om;
3853 va = trunc_page(va);
3854 KASSERT(va <= vm_max_kernel_address, ("%s: toobig", __func__));
3855 KASSERT(va < UPT2V_MIN_ADDRESS || va >= UPT2V_MAX_ADDRESS,
3856 ("%s: invalid to pmap_enter page table pages (va: 0x%x)", __func__,
3858 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || !VA_IS_CLEANMAP(va),
3859 ("%s: managed mapping within the clean submap", __func__));
3860 if ((m->oflags & VPO_UNMANAGED) == 0)
3861 VM_PAGE_OBJECT_BUSY_ASSERT(m);
3862 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
3863 ("%s: flags %u has reserved bits set", __func__, flags));
3864 pa = VM_PAGE_TO_PHYS(m);
3865 npte2 = PTE2(pa, PTE2_A, vm_page_pte2_attr(m));
3866 if ((flags & VM_PROT_WRITE) == 0)
3868 if ((prot & VM_PROT_WRITE) == 0)
3870 KASSERT((npte2 & (PTE2_NM | PTE2_RO)) != PTE2_RO,
3871 ("%s: flags includes VM_PROT_WRITE but prot doesn't", __func__));
3872 if ((prot & VM_PROT_EXECUTE) == 0)
3874 if ((flags & PMAP_ENTER_WIRED) != 0)
3876 if (va < VM_MAXUSER_ADDRESS)
3878 if (pmap != kernel_pmap)
3881 rw_wlock(&pvh_global_lock);
3885 /* Assert the required virtual and physical alignment. */
3886 KASSERT((va & PTE1_OFFSET) == 0,
3887 ("%s: va unaligned", __func__));
3888 KASSERT(m->psind > 0, ("%s: m->psind < psind", __func__));
3889 rv = pmap_enter_pte1(pmap, va, PTE1_PA(pa) | ATTR_TO_L1(npte2) |
3895 * In the case that a page table page is not
3896 * resident, we are creating it here.
3898 if (va < VM_MAXUSER_ADDRESS) {
3899 mpte2 = pmap_allocpte2(pmap, va, flags);
3900 if (mpte2 == NULL) {
3901 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3902 ("pmap_allocpte2 failed with sleep allowed"));
3903 rv = KERN_RESOURCE_SHORTAGE;
3908 pte1p = pmap_pte1(pmap, va);
3909 if (pte1_is_section(pte1_load(pte1p)))
3910 panic("%s: attempted on 1MB page", __func__);
3911 pte2p = pmap_pte2_quick(pmap, va);
3913 panic("%s: invalid L1 page table entry va=%#x", __func__, va);
3916 opte2 = pte2_load(pte2p);
3917 opa = pte2_pa(opte2);
3919 * Mapping has not changed, must be protection or wiring change.
3921 if (pte2_is_valid(opte2) && (opa == pa)) {
3923 * Wiring change, just update stats. We don't worry about
3924 * wiring PT2 pages as they remain resident as long as there
3925 * are valid mappings in them. Hence, if a user page is wired,
3926 * the PT2 page will be also.
3928 if (pte2_is_wired(npte2) && !pte2_is_wired(opte2))
3929 pmap->pm_stats.wired_count++;
3930 else if (!pte2_is_wired(npte2) && pte2_is_wired(opte2))
3931 pmap->pm_stats.wired_count--;
3934 * Remove extra pte2 reference
3937 pt2_wirecount_dec(mpte2, pte1_index(va));
3938 if ((m->oflags & VPO_UNMANAGED) == 0)
3944 * QQQ: We think that changing physical address on writeable mapping
3945 * is not safe. Well, maybe on kernel address space with correct
3946 * locking, it can make a sense. However, we have no idea why
3947 * anyone should do that on user address space. Are we wrong?
3949 KASSERT((opa == 0) || (opa == pa) ||
3950 !pte2_is_valid(opte2) || ((opte2 & PTE2_RO) != 0),
3951 ("%s: pmap %p va %#x(%#x) opa %#x pa %#x - gotcha %#x %#x!",
3952 __func__, pmap, va, opte2, opa, pa, flags, prot));
3957 * Mapping has changed, invalidate old range and fall through to
3958 * handle validating new mapping.
3961 if (pte2_is_wired(opte2))
3962 pmap->pm_stats.wired_count--;
3963 om = PHYS_TO_VM_PAGE(opa);
3964 if (om != NULL && (om->oflags & VPO_UNMANAGED) != 0)
3967 pv = pmap_pvh_remove(&om->md, pmap, va);
3970 * Remove extra pte2 reference
3973 pt2_wirecount_dec(mpte2, va >> PTE1_SHIFT);
3975 pmap->pm_stats.resident_count++;
3978 * Enter on the PV list if part of our managed memory.
3980 if ((m->oflags & VPO_UNMANAGED) == 0) {
3982 pv = get_pv_entry(pmap, FALSE);
3985 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3986 } else if (pv != NULL)
3987 free_pv_entry(pmap, pv);
3990 * Increment counters
3992 if (pte2_is_wired(npte2))
3993 pmap->pm_stats.wired_count++;
3997 * Now validate mapping with desired protection/wiring.
3999 if (prot & VM_PROT_WRITE) {
4000 if ((m->oflags & VPO_UNMANAGED) == 0)
4001 vm_page_aflag_set(m, PGA_WRITEABLE);
4005 * If the mapping or permission bits are different, we need
4006 * to update the pte2.
4008 * QQQ: Think again and again what to do
4009 * if the mapping is going to be changed!
4011 if ((opte2 & ~(PTE2_NM | PTE2_A)) != (npte2 & ~(PTE2_NM | PTE2_A))) {
4013 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4014 * is set. Do it now, before the mapping is stored and made
4015 * valid for hardware table walk. If done later, there is a race
4016 * for other threads of current process in lazy loading case.
4017 * Don't do it for kernel memory which is mapped with exec
4018 * permission even if the memory isn't going to hold executable
4019 * code. The only time when icache sync is needed is after
4020 * kernel module is loaded and the relocation info is processed.
4021 * And it's done in elf_cpu_load_file().
4023 * QQQ: (1) Does it exist any better way where
4024 * or how to sync icache?
4025 * (2) Now, we do it on a page basis.
4027 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
4028 m->md.pat_mode == VM_MEMATTR_WB_WA &&
4029 (opa != pa || (opte2 & PTE2_NX)))
4030 cache_icache_sync_fresh(va, pa, PAGE_SIZE);
4032 if (opte2 & PTE2_V) {
4033 /* Change mapping with break-before-make approach. */
4034 opte2 = pte2_load_clear(pte2p);
4035 pmap_tlb_flush(pmap, va);
4036 pte2_store(pte2p, npte2);
4038 KASSERT((om->oflags & VPO_UNMANAGED) == 0,
4039 ("%s: om %p unmanaged", __func__, om));
4040 if ((opte2 & PTE2_A) != 0)
4041 vm_page_aflag_set(om, PGA_REFERENCED);
4042 if (pte2_is_dirty(opte2))
4044 if (TAILQ_EMPTY(&om->md.pv_list) &&
4045 ((om->flags & PG_FICTITIOUS) != 0 ||
4046 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
4047 vm_page_aflag_clear(om, PGA_WRITEABLE);
4050 pte2_store(pte2p, npte2);
4055 * QQQ: In time when both access and not mofified bits are
4056 * emulated by software, this should not happen. Some
4057 * analysis is need, if this really happen. Missing
4058 * tlb flush somewhere could be the reason.
4060 panic("%s: pmap %p va %#x opte2 %x npte2 %x !!", __func__, pmap,
4065 #if VM_NRESERVLEVEL > 0
4067 * If both the L2 page table page and the reservation are fully
4068 * populated, then attempt promotion.
4070 if ((mpte2 == NULL || pt2_is_full(mpte2, va)) &&
4071 sp_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
4072 vm_reserv_level_iffullpop(m) == 0)
4073 pmap_promote_pte1(pmap, pte1p, va);
4079 rw_wunlock(&pvh_global_lock);
4085 * Do the things to unmap a page in a process.
4088 pmap_remove_pte2(pmap_t pmap, pt2_entry_t *pte2p, vm_offset_t va,
4089 struct spglist *free)
4094 rw_assert(&pvh_global_lock, RA_WLOCKED);
4095 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4097 /* Clear and invalidate the mapping. */
4098 opte2 = pte2_load_clear(pte2p);
4099 pmap_tlb_flush(pmap, va);
4101 KASSERT(pte2_is_valid(opte2), ("%s: pmap %p va %#x not link pte2 %#x",
4102 __func__, pmap, va, opte2));
4105 pmap->pm_stats.wired_count -= 1;
4106 pmap->pm_stats.resident_count -= 1;
4107 if (pte2_is_managed(opte2)) {
4108 m = PHYS_TO_VM_PAGE(pte2_pa(opte2));
4109 if (pte2_is_dirty(opte2))
4112 vm_page_aflag_set(m, PGA_REFERENCED);
4113 pmap_remove_entry(pmap, m, va);
4115 return (pmap_unuse_pt2(pmap, va, free));
4119 * Remove a single page from a process address space.
4122 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
4126 rw_assert(&pvh_global_lock, RA_WLOCKED);
4127 KASSERT(curthread->td_pinned > 0,
4128 ("%s: curthread not pinned", __func__));
4129 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4130 if ((pte2p = pmap_pte2_quick(pmap, va)) == NULL ||
4131 !pte2_is_valid(pte2_load(pte2p)))
4133 pmap_remove_pte2(pmap, pte2p, va, free);
4137 * Remove the given range of addresses from the specified map.
4139 * It is assumed that the start and end are properly
4140 * rounded to the page size.
4143 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4146 pt1_entry_t *pte1p, pte1;
4147 pt2_entry_t *pte2p, pte2;
4148 struct spglist free;
4151 * Perform an unsynchronized read. This is, however, safe.
4153 if (pmap->pm_stats.resident_count == 0)
4158 rw_wlock(&pvh_global_lock);
4163 * Special handling of removing one page. A very common
4164 * operation and easy to short circuit some code.
4166 if (sva + PAGE_SIZE == eva) {
4167 pte1 = pte1_load(pmap_pte1(pmap, sva));
4168 if (pte1_is_link(pte1)) {
4169 pmap_remove_page(pmap, sva, &free);
4174 for (; sva < eva; sva = nextva) {
4176 * Calculate address for next L2 page table.
4178 nextva = pte1_trunc(sva + PTE1_SIZE);
4181 if (pmap->pm_stats.resident_count == 0)
4184 pte1p = pmap_pte1(pmap, sva);
4185 pte1 = pte1_load(pte1p);
4188 * Weed out invalid mappings. Note: we assume that the L1 page
4189 * table is always allocated, and in kernel virtual.
4194 if (pte1_is_section(pte1)) {
4196 * Are we removing the entire large page? If not,
4197 * demote the mapping and fall through.
4199 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
4200 pmap_remove_pte1(pmap, pte1p, sva, &free);
4202 } else if (!pmap_demote_pte1(pmap, pte1p, sva)) {
4203 /* The large page mapping was destroyed. */
4208 /* Update pte1 after demotion. */
4209 pte1 = pte1_load(pte1p);
4214 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
4215 " is not link", __func__, pmap, sva, pte1, pte1p));
4218 * Limit our scan to either the end of the va represented
4219 * by the current L2 page table page, or to the end of the
4220 * range being removed.
4225 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva;
4226 pte2p++, sva += PAGE_SIZE) {
4227 pte2 = pte2_load(pte2p);
4228 if (!pte2_is_valid(pte2))
4230 if (pmap_remove_pte2(pmap, pte2p, sva, &free))
4236 rw_wunlock(&pvh_global_lock);
4238 vm_page_free_pages_toq(&free, false);
4242 * Routine: pmap_remove_all
4244 * Removes this physical page from
4245 * all physical maps in which it resides.
4246 * Reflects back modify bits to the pager.
4249 * Original versions of this routine were very
4250 * inefficient because they iteratively called
4251 * pmap_remove (slow...)
4255 pmap_remove_all(vm_page_t m)
4257 struct md_page *pvh;
4260 pt2_entry_t *pte2p, opte2;
4263 struct spglist free;
4265 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4266 ("%s: page %p is not managed", __func__, m));
4268 rw_wlock(&pvh_global_lock);
4270 if ((m->flags & PG_FICTITIOUS) != 0)
4271 goto small_mappings;
4272 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4273 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
4277 pte1p = pmap_pte1(pmap, va);
4278 (void)pmap_demote_pte1(pmap, pte1p, va);
4282 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4285 pmap->pm_stats.resident_count--;
4286 pte1p = pmap_pte1(pmap, pv->pv_va);
4287 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found "
4288 "a 1mpage in page %p's pv list", __func__, m));
4289 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
4290 opte2 = pte2_load_clear(pte2p);
4291 pmap_tlb_flush(pmap, pv->pv_va);
4292 KASSERT(pte2_is_valid(opte2), ("%s: pmap %p va %x zero pte2",
4293 __func__, pmap, pv->pv_va));
4294 if (pte2_is_wired(opte2))
4295 pmap->pm_stats.wired_count--;
4297 vm_page_aflag_set(m, PGA_REFERENCED);
4300 * Update the vm_page_t clean and reference bits.
4302 if (pte2_is_dirty(opte2))
4304 pmap_unuse_pt2(pmap, pv->pv_va, &free);
4305 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4306 free_pv_entry(pmap, pv);
4309 vm_page_aflag_clear(m, PGA_WRITEABLE);
4311 rw_wunlock(&pvh_global_lock);
4312 vm_page_free_pages_toq(&free, false);
4316 * Just subroutine for pmap_remove_pages() to reasonably satisfy
4317 * good coding style, a.k.a. 80 character line width limit hell.
4319 static __inline void
4320 pmap_remove_pte1_quick(pmap_t pmap, pt1_entry_t pte1, pv_entry_t pv,
4321 struct spglist *free)
4324 vm_page_t m, mt, mpt2pg;
4325 struct md_page *pvh;
4328 m = PHYS_TO_VM_PAGE(pa);
4330 KASSERT(m->phys_addr == pa, ("%s: vm_page_t %p addr mismatch %#x %#x",
4331 __func__, m, m->phys_addr, pa));
4332 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4333 m < &vm_page_array[vm_page_array_size],
4334 ("%s: bad pte1 %#x", __func__, pte1));
4336 if (pte1_is_dirty(pte1)) {
4337 for (mt = m; mt < &m[PTE1_SIZE / PAGE_SIZE]; mt++)
4341 pmap->pm_stats.resident_count -= PTE1_SIZE / PAGE_SIZE;
4342 pvh = pa_to_pvh(pa);
4343 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4344 if (TAILQ_EMPTY(&pvh->pv_list)) {
4345 for (mt = m; mt < &m[PTE1_SIZE / PAGE_SIZE]; mt++)
4346 if (TAILQ_EMPTY(&mt->md.pv_list))
4347 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4349 mpt2pg = pmap_pt2_page(pmap, pv->pv_va);
4351 pmap_unwire_pt2_all(pmap, pv->pv_va, mpt2pg, free);
4355 * Just subroutine for pmap_remove_pages() to reasonably satisfy
4356 * good coding style, a.k.a. 80 character line width limit hell.
4358 static __inline void
4359 pmap_remove_pte2_quick(pmap_t pmap, pt2_entry_t pte2, pv_entry_t pv,
4360 struct spglist *free)
4364 struct md_page *pvh;
4367 m = PHYS_TO_VM_PAGE(pa);
4369 KASSERT(m->phys_addr == pa, ("%s: vm_page_t %p addr mismatch %#x %#x",
4370 __func__, m, m->phys_addr, pa));
4371 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4372 m < &vm_page_array[vm_page_array_size],
4373 ("%s: bad pte2 %#x", __func__, pte2));
4375 if (pte2_is_dirty(pte2))
4378 pmap->pm_stats.resident_count--;
4379 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4380 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
4381 pvh = pa_to_pvh(pa);
4382 if (TAILQ_EMPTY(&pvh->pv_list))
4383 vm_page_aflag_clear(m, PGA_WRITEABLE);
4385 pmap_unuse_pt2(pmap, pv->pv_va, free);
4389 * Remove all pages from specified address space this aids process
4390 * exit speeds. Also, this code is special cased for current process
4391 * only, but can have the more generic (and slightly slower) mode enabled.
4392 * This is much faster than pmap_remove in the case of running down
4393 * an entire address space.
4396 pmap_remove_pages(pmap_t pmap)
4398 pt1_entry_t *pte1p, pte1;
4399 pt2_entry_t *pte2p, pte2;
4401 struct pv_chunk *pc, *npc;
4402 struct spglist free;
4405 uint32_t inuse, bitmask;
4409 * Assert that the given pmap is only active on the current
4410 * CPU. Unfortunately, we cannot block another CPU from
4411 * activating the pmap while this function is executing.
4413 KASSERT(pmap == vmspace_pmap(curthread->td_proc->p_vmspace),
4414 ("%s: non-current pmap %p", __func__, pmap));
4415 #if defined(SMP) && defined(INVARIANTS)
4417 cpuset_t other_cpus;
4420 other_cpus = pmap->pm_active;
4421 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
4423 KASSERT(CPU_EMPTY(&other_cpus),
4424 ("%s: pmap %p active on other cpus", __func__, pmap));
4428 rw_wlock(&pvh_global_lock);
4431 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4432 KASSERT(pc->pc_pmap == pmap, ("%s: wrong pmap %p %p",
4433 __func__, pmap, pc->pc_pmap));
4435 for (field = 0; field < _NPCM; field++) {
4436 inuse = (~(pc->pc_map[field])) & pc_freemask[field];
4437 while (inuse != 0) {
4438 bit = ffs(inuse) - 1;
4439 bitmask = 1UL << bit;
4440 idx = field * 32 + bit;
4441 pv = &pc->pc_pventry[idx];
4445 * Note that we cannot remove wired pages
4446 * from a process' mapping at this time
4448 pte1p = pmap_pte1(pmap, pv->pv_va);
4449 pte1 = pte1_load(pte1p);
4450 if (pte1_is_section(pte1)) {
4451 if (pte1_is_wired(pte1)) {
4456 pmap_remove_pte1_quick(pmap, pte1, pv,
4459 else if (pte1_is_link(pte1)) {
4460 pte2p = pt2map_entry(pv->pv_va);
4461 pte2 = pte2_load(pte2p);
4463 if (!pte2_is_valid(pte2)) {
4464 printf("%s: pmap %p va %#x "
4465 "pte2 %#x\n", __func__,
4466 pmap, pv->pv_va, pte2);
4470 if (pte2_is_wired(pte2)) {
4475 pmap_remove_pte2_quick(pmap, pte2, pv,
4478 printf("%s: pmap %p va %#x pte1 %#x\n",
4479 __func__, pmap, pv->pv_va, pte1);
4484 PV_STAT(pv_entry_frees++);
4485 PV_STAT(pv_entry_spare++);
4487 pc->pc_map[field] |= bitmask;
4491 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4495 tlb_flush_all_ng_local();
4497 rw_wunlock(&pvh_global_lock);
4499 vm_page_free_pages_toq(&free, false);
4503 * This code makes some *MAJOR* assumptions:
4504 * 1. Current pmap & pmap exists.
4507 * 4. No L2 page table pages.
4508 * but is *MUCH* faster than pmap_enter...
4511 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4512 vm_prot_t prot, vm_page_t mpt2pg)
4514 pt2_entry_t *pte2p, pte2;
4516 struct spglist free;
4519 KASSERT(!VA_IS_CLEANMAP(va) ||
4520 (m->oflags & VPO_UNMANAGED) != 0,
4521 ("%s: managed mapping within the clean submap", __func__));
4522 rw_assert(&pvh_global_lock, RA_WLOCKED);
4523 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4526 * In the case that a L2 page table page is not
4527 * resident, we are creating it here.
4529 if (va < VM_MAXUSER_ADDRESS) {
4531 pt1_entry_t pte1, *pte1p;
4535 * Get L1 page table things.
4537 pte1_idx = pte1_index(va);
4538 pte1p = pmap_pte1(pmap, va);
4539 pte1 = pte1_load(pte1p);
4541 if (mpt2pg && (mpt2pg->pindex == (pte1_idx & ~PT2PG_MASK))) {
4543 * Each of NPT2_IN_PG L2 page tables on the page can
4544 * come here. Make sure that associated L1 page table
4545 * link is established.
4547 * QQQ: It comes that we don't establish all links to
4548 * L2 page tables for newly allocated L2 page
4551 KASSERT(!pte1_is_section(pte1),
4552 ("%s: pte1 %#x is section", __func__, pte1));
4553 if (!pte1_is_link(pte1)) {
4554 pt2_pa = page_pt2pa(VM_PAGE_TO_PHYS(mpt2pg),
4556 pte1_store(pte1p, PTE1_LINK(pt2_pa));
4558 pt2_wirecount_inc(mpt2pg, pte1_idx);
4561 * If the L2 page table page is mapped, we just
4562 * increment the hold count, and activate it.
4564 if (pte1_is_section(pte1)) {
4566 } else if (pte1_is_link(pte1)) {
4567 mpt2pg = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
4568 pt2_wirecount_inc(mpt2pg, pte1_idx);
4570 mpt2pg = _pmap_allocpte2(pmap, va,
4571 PMAP_ENTER_NOSLEEP);
4581 * This call to pt2map_entry() makes the assumption that we are
4582 * entering the page into the current pmap. In order to support
4583 * quick entry into any pmap, one would likely use pmap_pte2_quick().
4584 * But that isn't as quick as pt2map_entry().
4586 pte2p = pt2map_entry(va);
4587 pte2 = pte2_load(pte2p);
4588 if (pte2_is_valid(pte2)) {
4589 if (mpt2pg != NULL) {
4591 * Remove extra pte2 reference
4593 pt2_wirecount_dec(mpt2pg, pte1_index(va));
4600 * Enter on the PV list if part of our managed memory.
4602 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4603 !pmap_try_insert_pv_entry(pmap, va, m)) {
4604 if (mpt2pg != NULL) {
4606 if (pmap_unwire_pt2(pmap, va, mpt2pg, &free)) {
4607 pmap_tlb_flush(pmap, va);
4608 vm_page_free_pages_toq(&free, false);
4617 * Increment counters
4619 pmap->pm_stats.resident_count++;
4622 * Now validate mapping with RO protection
4624 pa = VM_PAGE_TO_PHYS(m);
4625 l2prot = PTE2_RO | PTE2_NM;
4626 if (va < VM_MAXUSER_ADDRESS)
4627 l2prot |= PTE2_U | PTE2_NG;
4628 if ((prot & VM_PROT_EXECUTE) == 0)
4630 else if (m->md.pat_mode == VM_MEMATTR_WB_WA && pmap != kernel_pmap) {
4632 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4633 * is set. QQQ: For more info, see comments in pmap_enter().
4635 cache_icache_sync_fresh(va, pa, PAGE_SIZE);
4637 pte2_store(pte2p, PTE2(pa, l2prot, vm_page_pte2_attr(m)));
4643 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4646 rw_wlock(&pvh_global_lock);
4648 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
4649 rw_wunlock(&pvh_global_lock);
4654 * Tries to create a read- and/or execute-only 1 MB page mapping. Returns
4655 * true if successful. Returns false if (1) a mapping already exists at the
4656 * specified virtual address or (2) a PV entry cannot be allocated without
4657 * reclaiming another PV entry.
4660 pmap_enter_1mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4665 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4666 pa = VM_PAGE_TO_PHYS(m);
4667 pte1 = PTE1(pa, PTE1_NM | PTE1_RO, ATTR_TO_L1(vm_page_pte2_attr(m)));
4668 if ((prot & VM_PROT_EXECUTE) == 0)
4670 if (va < VM_MAXUSER_ADDRESS)
4672 if (pmap != kernel_pmap)
4674 return (pmap_enter_pte1(pmap, va, pte1, PMAP_ENTER_NOSLEEP |
4675 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, m) == KERN_SUCCESS);
4679 * Tries to create the specified 1 MB page mapping. Returns KERN_SUCCESS if
4680 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
4681 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
4682 * a mapping already exists at the specified virtual address. Returns
4683 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NORECLAIM was specified and PV entry
4684 * allocation failed.
4687 pmap_enter_pte1(pmap_t pmap, vm_offset_t va, pt1_entry_t pte1, u_int flags,
4690 struct spglist free;
4691 pt1_entry_t opte1, *pte1p;
4692 pt2_entry_t pte2, *pte2p;
4693 vm_offset_t cur, end;
4696 rw_assert(&pvh_global_lock, RA_WLOCKED);
4697 KASSERT((pte1 & (PTE1_NM | PTE1_RO)) == 0 ||
4698 (pte1 & (PTE1_NM | PTE1_RO)) == (PTE1_NM | PTE1_RO),
4699 ("%s: pte1 has inconsistent NM and RO attributes", __func__));
4700 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4701 pte1p = pmap_pte1(pmap, va);
4702 opte1 = pte1_load(pte1p);
4703 if (pte1_is_valid(opte1)) {
4704 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
4705 CTR3(KTR_PMAP, "%s: failure for va %#lx in pmap %p",
4706 __func__, va, pmap);
4707 return (KERN_FAILURE);
4709 /* Break the existing mapping(s). */
4711 if (pte1_is_section(opte1)) {
4713 * If the section resulted from a promotion, then a
4714 * reserved PT page could be freed.
4716 pmap_remove_pte1(pmap, pte1p, va, &free);
4719 end = va + PTE1_SIZE;
4720 for (cur = va, pte2p = pmap_pte2_quick(pmap, va);
4721 cur != end; cur += PAGE_SIZE, pte2p++) {
4722 pte2 = pte2_load(pte2p);
4723 if (!pte2_is_valid(pte2))
4725 if (pmap_remove_pte2(pmap, pte2p, cur, &free))
4730 vm_page_free_pages_toq(&free, false);
4732 if ((m->oflags & VPO_UNMANAGED) == 0) {
4734 * Abort this mapping if its PV entry could not be created.
4736 if (!pmap_pv_insert_pte1(pmap, va, pte1, flags)) {
4737 CTR3(KTR_PMAP, "%s: failure for va %#lx in pmap %p",
4738 __func__, va, pmap);
4739 return (KERN_RESOURCE_SHORTAGE);
4741 if ((pte1 & PTE1_RO) == 0) {
4742 for (mt = m; mt < &m[PTE1_SIZE / PAGE_SIZE]; mt++)
4743 vm_page_aflag_set(mt, PGA_WRITEABLE);
4748 * Increment counters.
4750 if (pte1_is_wired(pte1))
4751 pmap->pm_stats.wired_count += PTE1_SIZE / PAGE_SIZE;
4752 pmap->pm_stats.resident_count += PTE1_SIZE / PAGE_SIZE;
4755 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4756 * is set. QQQ: For more info, see comments in pmap_enter().
4758 if ((pte1 & PTE1_NX) == 0 && m->md.pat_mode == VM_MEMATTR_WB_WA &&
4759 pmap != kernel_pmap && (!pte1_is_section(opte1) ||
4760 pte1_pa(opte1) != VM_PAGE_TO_PHYS(m) || (opte1 & PTE2_NX) != 0))
4761 cache_icache_sync_fresh(va, VM_PAGE_TO_PHYS(m), PTE1_SIZE);
4766 pte1_store(pte1p, pte1);
4768 pmap_pte1_mappings++;
4769 CTR3(KTR_PMAP, "%s: success for va %#lx in pmap %p", __func__, va,
4771 return (KERN_SUCCESS);
4775 * Maps a sequence of resident pages belonging to the same object.
4776 * The sequence begins with the given page m_start. This page is
4777 * mapped at the given virtual address start. Each subsequent page is
4778 * mapped at a virtual address that is offset from start by the same
4779 * amount as the page is offset from m_start within the object. The
4780 * last page in the sequence is the page with the largest offset from
4781 * m_start that can be mapped at a virtual address less than the given
4782 * virtual address end. Not every virtual page between start and end
4783 * is mapped; only those for which a resident page exists with the
4784 * corresponding offset from m_start are mapped.
4787 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4788 vm_page_t m_start, vm_prot_t prot)
4791 vm_page_t m, mpt2pg;
4792 vm_pindex_t diff, psize;
4794 PDEBUG(6, printf("%s: pmap %p start %#x end %#x m %p prot %#x\n",
4795 __func__, pmap, start, end, m_start, prot));
4797 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4798 psize = atop(end - start);
4801 rw_wlock(&pvh_global_lock);
4803 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4804 va = start + ptoa(diff);
4805 if ((va & PTE1_OFFSET) == 0 && va + PTE1_SIZE <= end &&
4806 m->psind == 1 && sp_enabled &&
4807 pmap_enter_1mpage(pmap, va, m, prot))
4808 m = &m[PTE1_SIZE / PAGE_SIZE - 1];
4810 mpt2pg = pmap_enter_quick_locked(pmap, va, m, prot,
4812 m = TAILQ_NEXT(m, listq);
4814 rw_wunlock(&pvh_global_lock);
4819 * This code maps large physical mmap regions into the
4820 * processor address space. Note that some shortcuts
4821 * are taken, but the code works.
4824 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4825 vm_pindex_t pindex, vm_size_t size)
4828 vm_paddr_t pa, pte2_pa;
4830 vm_memattr_t pat_mode;
4831 u_int l1attr, l1prot;
4833 VM_OBJECT_ASSERT_WLOCKED(object);
4834 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4835 ("%s: non-device object", __func__));
4836 if ((addr & PTE1_OFFSET) == 0 && (size & PTE1_OFFSET) == 0) {
4837 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4839 p = vm_page_lookup(object, pindex);
4840 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4841 ("%s: invalid page %p", __func__, p));
4842 pat_mode = p->md.pat_mode;
4845 * Abort the mapping if the first page is not physically
4846 * aligned to a 1MB page boundary.
4848 pte2_pa = VM_PAGE_TO_PHYS(p);
4849 if (pte2_pa & PTE1_OFFSET)
4853 * Skip the first page. Abort the mapping if the rest of
4854 * the pages are not physically contiguous or have differing
4855 * memory attributes.
4857 p = TAILQ_NEXT(p, listq);
4858 for (pa = pte2_pa + PAGE_SIZE; pa < pte2_pa + size;
4860 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4861 ("%s: invalid page %p", __func__, p));
4862 if (pa != VM_PAGE_TO_PHYS(p) ||
4863 pat_mode != p->md.pat_mode)
4865 p = TAILQ_NEXT(p, listq);
4869 * Map using 1MB pages.
4871 * QQQ: Well, we are mapping a section, so same condition must
4872 * be hold like during promotion. It looks that only RW mapping
4873 * is done here, so readonly mapping must be done elsewhere.
4875 l1prot = PTE1_U | PTE1_NG | PTE1_RW | PTE1_M | PTE1_A;
4876 l1attr = ATTR_TO_L1(vm_memattr_to_pte2(pat_mode));
4878 for (pa = pte2_pa; pa < pte2_pa + size; pa += PTE1_SIZE) {
4879 pte1p = pmap_pte1(pmap, addr);
4880 if (!pte1_is_valid(pte1_load(pte1p))) {
4881 pte1_store(pte1p, PTE1(pa, l1prot, l1attr));
4882 pmap->pm_stats.resident_count += PTE1_SIZE /
4884 pmap_pte1_mappings++;
4886 /* Else continue on if the PTE1 is already valid. */
4894 * Do the things to protect a 1mpage in a process.
4897 pmap_protect_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t sva,
4900 pt1_entry_t npte1, opte1;
4901 vm_offset_t eva, va;
4904 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4905 KASSERT((sva & PTE1_OFFSET) == 0,
4906 ("%s: sva is not 1mpage aligned", __func__));
4908 opte1 = npte1 = pte1_load(pte1p);
4909 if (pte1_is_managed(opte1) && pte1_is_dirty(opte1)) {
4910 eva = sva + PTE1_SIZE;
4911 for (va = sva, m = PHYS_TO_VM_PAGE(pte1_pa(opte1));
4912 va < eva; va += PAGE_SIZE, m++)
4915 if ((prot & VM_PROT_WRITE) == 0)
4916 npte1 |= PTE1_RO | PTE1_NM;
4917 if ((prot & VM_PROT_EXECUTE) == 0)
4921 * QQQ: Herein, execute permission is never set.
4922 * It only can be cleared. So, no icache
4923 * syncing is needed.
4926 if (npte1 != opte1) {
4927 pte1_store(pte1p, npte1);
4928 pmap_tlb_flush(pmap, sva);
4933 * Set the physical protection on the
4934 * specified range of this map as requested.
4937 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
4939 boolean_t pv_lists_locked;
4941 pt1_entry_t *pte1p, pte1;
4942 pt2_entry_t *pte2p, opte2, npte2;
4944 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
4945 if (prot == VM_PROT_NONE) {
4946 pmap_remove(pmap, sva, eva);
4950 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
4951 (VM_PROT_WRITE | VM_PROT_EXECUTE))
4954 if (pmap_is_current(pmap))
4955 pv_lists_locked = FALSE;
4957 pv_lists_locked = TRUE;
4959 rw_wlock(&pvh_global_lock);
4964 for (; sva < eva; sva = nextva) {
4966 * Calculate address for next L2 page table.
4968 nextva = pte1_trunc(sva + PTE1_SIZE);
4972 pte1p = pmap_pte1(pmap, sva);
4973 pte1 = pte1_load(pte1p);
4976 * Weed out invalid mappings. Note: we assume that L1 page
4977 * page table is always allocated, and in kernel virtual.
4982 if (pte1_is_section(pte1)) {
4984 * Are we protecting the entire large page? If not,
4985 * demote the mapping and fall through.
4987 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
4988 pmap_protect_pte1(pmap, pte1p, sva, prot);
4991 if (!pv_lists_locked) {
4992 pv_lists_locked = TRUE;
4993 if (!rw_try_wlock(&pvh_global_lock)) {
4999 if (!pmap_demote_pte1(pmap, pte1p, sva)) {
5001 * The large page mapping
5008 /* Update pte1 after demotion */
5009 pte1 = pte1_load(pte1p);
5015 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
5016 " is not link", __func__, pmap, sva, pte1, pte1p));
5019 * Limit our scan to either the end of the va represented
5020 * by the current L2 page table page, or to the end of the
5021 * range being protected.
5026 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva; pte2p++,
5030 opte2 = npte2 = pte2_load(pte2p);
5031 if (!pte2_is_valid(opte2))
5034 if ((prot & VM_PROT_WRITE) == 0) {
5035 if (pte2_is_managed(opte2) &&
5036 pte2_is_dirty(opte2)) {
5037 m = PHYS_TO_VM_PAGE(pte2_pa(opte2));
5040 npte2 |= PTE2_RO | PTE2_NM;
5043 if ((prot & VM_PROT_EXECUTE) == 0)
5047 * QQQ: Herein, execute permission is never set.
5048 * It only can be cleared. So, no icache
5049 * syncing is needed.
5052 if (npte2 != opte2) {
5053 pte2_store(pte2p, npte2);
5054 pmap_tlb_flush(pmap, sva);
5058 if (pv_lists_locked) {
5060 rw_wunlock(&pvh_global_lock);
5066 * pmap_pvh_wired_mappings:
5068 * Return the updated number "count" of managed mappings that are wired.
5071 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
5078 rw_assert(&pvh_global_lock, RA_WLOCKED);
5080 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5083 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5084 if (pte1_is_section(pte1)) {
5085 if (pte1_is_wired(pte1))
5088 KASSERT(pte1_is_link(pte1),
5089 ("%s: pte1 %#x is not link", __func__, pte1));
5090 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5091 if (pte2_is_wired(pte2))
5101 * pmap_page_wired_mappings:
5103 * Return the number of managed mappings to the given physical page
5107 pmap_page_wired_mappings(vm_page_t m)
5112 if ((m->oflags & VPO_UNMANAGED) != 0)
5114 rw_wlock(&pvh_global_lock);
5115 count = pmap_pvh_wired_mappings(&m->md, count);
5116 if ((m->flags & PG_FICTITIOUS) == 0) {
5117 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
5120 rw_wunlock(&pvh_global_lock);
5125 * Returns TRUE if any of the given mappings were used to modify
5126 * physical memory. Otherwise, returns FALSE. Both page and 1mpage
5127 * mappings are supported.
5130 pmap_is_modified_pvh(struct md_page *pvh)
5138 rw_assert(&pvh_global_lock, RA_WLOCKED);
5141 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5144 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5145 if (pte1_is_section(pte1)) {
5146 rv = pte1_is_dirty(pte1);
5148 KASSERT(pte1_is_link(pte1),
5149 ("%s: pte1 %#x is not link", __func__, pte1));
5150 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5151 rv = pte2_is_dirty(pte2);
5164 * Return whether or not the specified physical page was modified
5165 * in any physical maps.
5168 pmap_is_modified(vm_page_t m)
5172 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5173 ("%s: page %p is not managed", __func__, m));
5176 * If the page is not busied then this check is racy.
5178 if (!pmap_page_is_write_mapped(m))
5180 rw_wlock(&pvh_global_lock);
5181 rv = pmap_is_modified_pvh(&m->md) ||
5182 ((m->flags & PG_FICTITIOUS) == 0 &&
5183 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
5184 rw_wunlock(&pvh_global_lock);
5189 * pmap_is_prefaultable:
5191 * Return whether or not the specified virtual address is eligible
5195 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
5203 pte1 = pte1_load(pmap_pte1(pmap, addr));
5204 if (pte1_is_link(pte1)) {
5205 pte2 = pte2_load(pt2map_entry(addr));
5206 rv = !pte2_is_valid(pte2) ;
5213 * Returns TRUE if any of the given mappings were referenced and FALSE
5214 * otherwise. Both page and 1mpage mappings are supported.
5217 pmap_is_referenced_pvh(struct md_page *pvh)
5226 rw_assert(&pvh_global_lock, RA_WLOCKED);
5229 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5232 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5233 if (pte1_is_section(pte1)) {
5234 rv = (pte1 & (PTE1_A | PTE1_V)) == (PTE1_A | PTE1_V);
5236 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5237 rv = (pte2 & (PTE2_A | PTE2_V)) == (PTE2_A | PTE2_V);
5248 * pmap_is_referenced:
5250 * Return whether or not the specified physical page was referenced
5251 * in any physical maps.
5254 pmap_is_referenced(vm_page_t m)
5258 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5259 ("%s: page %p is not managed", __func__, m));
5260 rw_wlock(&pvh_global_lock);
5261 rv = pmap_is_referenced_pvh(&m->md) ||
5262 ((m->flags & PG_FICTITIOUS) == 0 &&
5263 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
5264 rw_wunlock(&pvh_global_lock);
5269 * pmap_ts_referenced:
5271 * Return a count of reference bits for a page, clearing those bits.
5272 * It is not necessary for every reference bit to be cleared, but it
5273 * is necessary that 0 only be returned when there are truly no
5274 * reference bits set.
5276 * As an optimization, update the page's dirty field if a modified bit is
5277 * found while counting reference bits. This opportunistic update can be
5278 * performed at low cost and can eliminate the need for some future calls
5279 * to pmap_is_modified(). However, since this function stops after
5280 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5281 * dirty pages. Those dirty pages will only be detected by a future call
5282 * to pmap_is_modified().
5285 pmap_ts_referenced(vm_page_t m)
5287 struct md_page *pvh;
5290 pt1_entry_t *pte1p, opte1;
5291 pt2_entry_t *pte2p, opte2;
5295 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5296 ("%s: page %p is not managed", __func__, m));
5297 pa = VM_PAGE_TO_PHYS(m);
5298 pvh = pa_to_pvh(pa);
5299 rw_wlock(&pvh_global_lock);
5301 if ((m->flags & PG_FICTITIOUS) != 0 ||
5302 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5303 goto small_mappings;
5308 pte1p = pmap_pte1(pmap, pv->pv_va);
5309 opte1 = pte1_load(pte1p);
5310 if (pte1_is_dirty(opte1)) {
5312 * Although "opte1" is mapping a 1MB page, because
5313 * this function is called at a 4KB page granularity,
5314 * we only update the 4KB page under test.
5318 if ((opte1 & PTE1_A) != 0) {
5320 * Since this reference bit is shared by 256 4KB pages,
5321 * it should not be cleared every time it is tested.
5322 * Apply a simple "hash" function on the physical page
5323 * number, the virtual section number, and the pmap
5324 * address to select one 4KB page out of the 256
5325 * on which testing the reference bit will result
5326 * in clearing that bit. This function is designed
5327 * to avoid the selection of the same 4KB page
5328 * for every 1MB page mapping.
5330 * On demotion, a mapping that hasn't been referenced
5331 * is simply destroyed. To avoid the possibility of a
5332 * subsequent page fault on a demoted wired mapping,
5333 * always leave its reference bit set. Moreover,
5334 * since the section is wired, the current state of
5335 * its reference bit won't affect page replacement.
5337 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PTE1_SHIFT) ^
5338 (uintptr_t)pmap) & (NPTE2_IN_PG - 1)) == 0 &&
5339 !pte1_is_wired(opte1)) {
5340 pte1_clear_bit(pte1p, PTE1_A);
5341 pmap_tlb_flush(pmap, pv->pv_va);
5346 /* Rotate the PV list if it has more than one entry. */
5347 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5348 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5349 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5351 if (rtval >= PMAP_TS_REFERENCED_MAX)
5353 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5355 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5361 pte1p = pmap_pte1(pmap, pv->pv_va);
5362 KASSERT(pte1_is_link(pte1_load(pte1p)),
5363 ("%s: not found a link in page %p's pv list", __func__, m));
5365 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5366 opte2 = pte2_load(pte2p);
5367 if (pte2_is_dirty(opte2))
5369 if ((opte2 & PTE2_A) != 0) {
5370 pte2_clear_bit(pte2p, PTE2_A);
5371 pmap_tlb_flush(pmap, pv->pv_va);
5375 /* Rotate the PV list if it has more than one entry. */
5376 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5377 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5378 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5380 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
5381 PMAP_TS_REFERENCED_MAX);
5384 rw_wunlock(&pvh_global_lock);
5389 * Clear the wired attribute from the mappings for the specified range of
5390 * addresses in the given pmap. Every valid mapping within that range
5391 * must have the wired attribute set. In contrast, invalid mappings
5392 * cannot have the wired attribute set, so they are ignored.
5394 * The wired attribute of the page table entry is not a hardware feature,
5395 * so there is no need to invalidate any TLB entries.
5398 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5401 pt1_entry_t *pte1p, pte1;
5402 pt2_entry_t *pte2p, pte2;
5403 boolean_t pv_lists_locked;
5405 if (pmap_is_current(pmap))
5406 pv_lists_locked = FALSE;
5408 pv_lists_locked = TRUE;
5410 rw_wlock(&pvh_global_lock);
5414 for (; sva < eva; sva = nextva) {
5415 nextva = pte1_trunc(sva + PTE1_SIZE);
5419 pte1p = pmap_pte1(pmap, sva);
5420 pte1 = pte1_load(pte1p);
5423 * Weed out invalid mappings. Note: we assume that L1 page
5424 * page table is always allocated, and in kernel virtual.
5429 if (pte1_is_section(pte1)) {
5430 if (!pte1_is_wired(pte1))
5431 panic("%s: pte1 %#x not wired", __func__, pte1);
5434 * Are we unwiring the entire large page? If not,
5435 * demote the mapping and fall through.
5437 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
5438 pte1_clear_bit(pte1p, PTE1_W);
5439 pmap->pm_stats.wired_count -= PTE1_SIZE /
5443 if (!pv_lists_locked) {
5444 pv_lists_locked = TRUE;
5445 if (!rw_try_wlock(&pvh_global_lock)) {
5452 if (!pmap_demote_pte1(pmap, pte1p, sva))
5453 panic("%s: demotion failed", __func__);
5456 /* Update pte1 after demotion */
5457 pte1 = pte1_load(pte1p);
5463 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
5464 " is not link", __func__, pmap, sva, pte1, pte1p));
5467 * Limit our scan to either the end of the va represented
5468 * by the current L2 page table page, or to the end of the
5469 * range being protected.
5474 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva; pte2p++,
5476 pte2 = pte2_load(pte2p);
5477 if (!pte2_is_valid(pte2))
5479 if (!pte2_is_wired(pte2))
5480 panic("%s: pte2 %#x is missing PTE2_W",
5484 * PTE2_W must be cleared atomically. Although the pmap
5485 * lock synchronizes access to PTE2_W, another processor
5486 * could be changing PTE2_NM and/or PTE2_A concurrently.
5488 pte2_clear_bit(pte2p, PTE2_W);
5489 pmap->pm_stats.wired_count--;
5492 if (pv_lists_locked) {
5494 rw_wunlock(&pvh_global_lock);
5500 * Clear the write and modified bits in each of the given page's mappings.
5503 pmap_remove_write(vm_page_t m)
5505 struct md_page *pvh;
5506 pv_entry_t next_pv, pv;
5509 pt2_entry_t *pte2p, opte2;
5512 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5513 ("%s: page %p is not managed", __func__, m));
5514 vm_page_assert_busied(m);
5516 if (!pmap_page_is_write_mapped(m))
5518 rw_wlock(&pvh_global_lock);
5520 if ((m->flags & PG_FICTITIOUS) != 0)
5521 goto small_mappings;
5522 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5523 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5527 pte1p = pmap_pte1(pmap, va);
5528 if (!(pte1_load(pte1p) & PTE1_RO))
5529 (void)pmap_demote_pte1(pmap, pte1p, va);
5533 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5536 pte1p = pmap_pte1(pmap, pv->pv_va);
5537 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found"
5538 " a section in page %p's pv list", __func__, m));
5539 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5540 opte2 = pte2_load(pte2p);
5541 if (!(opte2 & PTE2_RO)) {
5542 pte2_store(pte2p, opte2 | PTE2_RO | PTE2_NM);
5543 if (pte2_is_dirty(opte2))
5545 pmap_tlb_flush(pmap, pv->pv_va);
5549 vm_page_aflag_clear(m, PGA_WRITEABLE);
5551 rw_wunlock(&pvh_global_lock);
5555 * Apply the given advice to the specified range of addresses within the
5556 * given pmap. Depending on the advice, clear the referenced and/or
5557 * modified flags in each mapping and set the mapped page's dirty field.
5560 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5562 pt1_entry_t *pte1p, opte1;
5563 pt2_entry_t *pte2p, pte2;
5566 boolean_t pv_lists_locked;
5568 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5570 if (pmap_is_current(pmap))
5571 pv_lists_locked = FALSE;
5573 pv_lists_locked = TRUE;
5575 rw_wlock(&pvh_global_lock);
5579 for (; sva < eva; sva = pdnxt) {
5580 pdnxt = pte1_trunc(sva + PTE1_SIZE);
5583 pte1p = pmap_pte1(pmap, sva);
5584 opte1 = pte1_load(pte1p);
5585 if (!pte1_is_valid(opte1)) /* XXX */
5587 else if (pte1_is_section(opte1)) {
5588 if (!pte1_is_managed(opte1))
5590 if (!pv_lists_locked) {
5591 pv_lists_locked = TRUE;
5592 if (!rw_try_wlock(&pvh_global_lock)) {
5598 if (!pmap_demote_pte1(pmap, pte1p, sva)) {
5600 * The large page mapping was destroyed.
5606 * Unless the page mappings are wired, remove the
5607 * mapping to a single page so that a subsequent
5608 * access may repromote. Since the underlying L2 page
5609 * table is fully populated, this removal never
5610 * frees a L2 page table page.
5612 if (!pte1_is_wired(opte1)) {
5613 pte2p = pmap_pte2_quick(pmap, sva);
5614 KASSERT(pte2_is_valid(pte2_load(pte2p)),
5615 ("%s: invalid PTE2", __func__));
5616 pmap_remove_pte2(pmap, pte2p, sva, NULL);
5621 for (pte2p = pmap_pte2_quick(pmap, sva); sva != pdnxt; pte2p++,
5623 pte2 = pte2_load(pte2p);
5624 if (!pte2_is_valid(pte2) || !pte2_is_managed(pte2))
5626 else if (pte2_is_dirty(pte2)) {
5627 if (advice == MADV_DONTNEED) {
5629 * Future calls to pmap_is_modified()
5630 * can be avoided by making the page
5633 m = PHYS_TO_VM_PAGE(pte2_pa(pte2));
5636 pte2_set_bit(pte2p, PTE2_NM);
5637 pte2_clear_bit(pte2p, PTE2_A);
5638 } else if ((pte2 & PTE2_A) != 0)
5639 pte2_clear_bit(pte2p, PTE2_A);
5642 pmap_tlb_flush(pmap, sva);
5645 if (pv_lists_locked) {
5647 rw_wunlock(&pvh_global_lock);
5653 * Clear the modify bits on the specified physical page.
5656 pmap_clear_modify(vm_page_t m)
5658 struct md_page *pvh;
5659 pv_entry_t next_pv, pv;
5661 pt1_entry_t *pte1p, opte1;
5662 pt2_entry_t *pte2p, opte2;
5665 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5666 ("%s: page %p is not managed", __func__, m));
5667 vm_page_assert_busied(m);
5669 if (!pmap_page_is_write_mapped(m))
5671 rw_wlock(&pvh_global_lock);
5673 if ((m->flags & PG_FICTITIOUS) != 0)
5674 goto small_mappings;
5675 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5676 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5680 pte1p = pmap_pte1(pmap, va);
5681 opte1 = pte1_load(pte1p);
5682 if (!(opte1 & PTE1_RO)) {
5683 if (pmap_demote_pte1(pmap, pte1p, va) &&
5684 !pte1_is_wired(opte1)) {
5686 * Write protect the mapping to a
5687 * single page so that a subsequent
5688 * write access may repromote.
5690 va += VM_PAGE_TO_PHYS(m) - pte1_pa(opte1);
5691 pte2p = pmap_pte2_quick(pmap, va);
5692 opte2 = pte2_load(pte2p);
5693 if ((opte2 & PTE2_V)) {
5694 pte2_set_bit(pte2p, PTE2_NM | PTE2_RO);
5696 pmap_tlb_flush(pmap, va);
5703 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5706 pte1p = pmap_pte1(pmap, pv->pv_va);
5707 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found"
5708 " a section in page %p's pv list", __func__, m));
5709 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5710 if (pte2_is_dirty(pte2_load(pte2p))) {
5711 pte2_set_bit(pte2p, PTE2_NM);
5712 pmap_tlb_flush(pmap, pv->pv_va);
5717 rw_wunlock(&pvh_global_lock);
5721 * Sets the memory attribute for the specified page.
5724 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5726 pt2_entry_t *cmap2_pte2p;
5731 oma = m->md.pat_mode;
5732 m->md.pat_mode = ma;
5734 CTR5(KTR_PMAP, "%s: page %p - 0x%08X oma: %d, ma: %d", __func__, m,
5735 VM_PAGE_TO_PHYS(m), oma, ma);
5736 if ((m->flags & PG_FICTITIOUS) != 0)
5740 * If "m" is a normal page, flush it from the cache.
5742 * First, try to find an existing mapping of the page by sf
5743 * buffer. sf_buf_invalidate_cache() modifies mapping and
5744 * flushes the cache.
5746 if (sf_buf_invalidate_cache(m, oma))
5750 * If page is not mapped by sf buffer, map the page
5751 * transient and do invalidation.
5754 pa = VM_PAGE_TO_PHYS(m);
5757 cmap2_pte2p = pc->pc_cmap2_pte2p;
5758 mtx_lock(&pc->pc_cmap_lock);
5759 if (pte2_load(cmap2_pte2p) != 0)
5760 panic("%s: CMAP2 busy", __func__);
5761 pte2_store(cmap2_pte2p, PTE2_KERN_NG(pa, PTE2_AP_KRW,
5762 vm_memattr_to_pte2(ma)));
5763 dcache_wbinv_poc((vm_offset_t)pc->pc_cmap2_addr, pa, PAGE_SIZE);
5764 pte2_clear(cmap2_pte2p);
5765 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5767 mtx_unlock(&pc->pc_cmap_lock);
5772 * Miscellaneous support routines follow
5776 * Returns TRUE if the given page is mapped individually or as part of
5777 * a 1mpage. Otherwise, returns FALSE.
5780 pmap_page_is_mapped(vm_page_t m)
5784 if ((m->oflags & VPO_UNMANAGED) != 0)
5786 rw_wlock(&pvh_global_lock);
5787 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5788 ((m->flags & PG_FICTITIOUS) == 0 &&
5789 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
5790 rw_wunlock(&pvh_global_lock);
5795 * Returns true if the pmap's pv is one of the first
5796 * 16 pvs linked to from this page. This count may
5797 * be changed upwards or downwards in the future; it
5798 * is only necessary that true be returned for a small
5799 * subset of pmaps for proper page aging.
5802 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5804 struct md_page *pvh;
5809 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5810 ("%s: page %p is not managed", __func__, m));
5812 rw_wlock(&pvh_global_lock);
5813 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5814 if (PV_PMAP(pv) == pmap) {
5822 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5823 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5824 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5825 if (PV_PMAP(pv) == pmap) {
5834 rw_wunlock(&pvh_global_lock);
5839 * pmap_zero_page zeros the specified hardware page by mapping
5840 * the page into KVM and using bzero to clear its contents.
5843 pmap_zero_page(vm_page_t m)
5845 pt2_entry_t *cmap2_pte2p;
5850 cmap2_pte2p = pc->pc_cmap2_pte2p;
5851 mtx_lock(&pc->pc_cmap_lock);
5852 if (pte2_load(cmap2_pte2p) != 0)
5853 panic("%s: CMAP2 busy", __func__);
5854 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5855 vm_page_pte2_attr(m)));
5856 pagezero(pc->pc_cmap2_addr);
5857 pte2_clear(cmap2_pte2p);
5858 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5860 mtx_unlock(&pc->pc_cmap_lock);
5864 * pmap_zero_page_area zeros the specified hardware page by mapping
5865 * the page into KVM and using bzero to clear its contents.
5867 * off and size may not cover an area beyond a single hardware page.
5870 pmap_zero_page_area(vm_page_t m, int off, int size)
5872 pt2_entry_t *cmap2_pte2p;
5877 cmap2_pte2p = pc->pc_cmap2_pte2p;
5878 mtx_lock(&pc->pc_cmap_lock);
5879 if (pte2_load(cmap2_pte2p) != 0)
5880 panic("%s: CMAP2 busy", __func__);
5881 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5882 vm_page_pte2_attr(m)));
5883 if (off == 0 && size == PAGE_SIZE)
5884 pagezero(pc->pc_cmap2_addr);
5886 bzero(pc->pc_cmap2_addr + off, size);
5887 pte2_clear(cmap2_pte2p);
5888 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5890 mtx_unlock(&pc->pc_cmap_lock);
5894 * pmap_copy_page copies the specified (machine independent)
5895 * page by mapping the page into virtual memory and using
5896 * bcopy to copy the page, one machine dependent page at a
5900 pmap_copy_page(vm_page_t src, vm_page_t dst)
5902 pt2_entry_t *cmap1_pte2p, *cmap2_pte2p;
5907 cmap1_pte2p = pc->pc_cmap1_pte2p;
5908 cmap2_pte2p = pc->pc_cmap2_pte2p;
5909 mtx_lock(&pc->pc_cmap_lock);
5910 if (pte2_load(cmap1_pte2p) != 0)
5911 panic("%s: CMAP1 busy", __func__);
5912 if (pte2_load(cmap2_pte2p) != 0)
5913 panic("%s: CMAP2 busy", __func__);
5914 pte2_store(cmap1_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(src),
5915 PTE2_AP_KR | PTE2_NM, vm_page_pte2_attr(src)));
5916 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(dst),
5917 PTE2_AP_KRW, vm_page_pte2_attr(dst)));
5918 bcopy(pc->pc_cmap1_addr, pc->pc_cmap2_addr, PAGE_SIZE);
5919 pte2_clear(cmap1_pte2p);
5920 tlb_flush((vm_offset_t)pc->pc_cmap1_addr);
5921 pte2_clear(cmap2_pte2p);
5922 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5924 mtx_unlock(&pc->pc_cmap_lock);
5927 int unmapped_buf_allowed = 1;
5930 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5931 vm_offset_t b_offset, int xfersize)
5933 pt2_entry_t *cmap1_pte2p, *cmap2_pte2p;
5934 vm_page_t a_pg, b_pg;
5936 vm_offset_t a_pg_offset, b_pg_offset;
5942 cmap1_pte2p = pc->pc_cmap1_pte2p;
5943 cmap2_pte2p = pc->pc_cmap2_pte2p;
5944 mtx_lock(&pc->pc_cmap_lock);
5945 if (pte2_load(cmap1_pte2p) != 0)
5946 panic("pmap_copy_pages: CMAP1 busy");
5947 if (pte2_load(cmap2_pte2p) != 0)
5948 panic("pmap_copy_pages: CMAP2 busy");
5949 while (xfersize > 0) {
5950 a_pg = ma[a_offset >> PAGE_SHIFT];
5951 a_pg_offset = a_offset & PAGE_MASK;
5952 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5953 b_pg = mb[b_offset >> PAGE_SHIFT];
5954 b_pg_offset = b_offset & PAGE_MASK;
5955 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5956 pte2_store(cmap1_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(a_pg),
5957 PTE2_AP_KR | PTE2_NM, vm_page_pte2_attr(a_pg)));
5958 tlb_flush_local((vm_offset_t)pc->pc_cmap1_addr);
5959 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(b_pg),
5960 PTE2_AP_KRW, vm_page_pte2_attr(b_pg)));
5961 tlb_flush_local((vm_offset_t)pc->pc_cmap2_addr);
5962 a_cp = pc->pc_cmap1_addr + a_pg_offset;
5963 b_cp = pc->pc_cmap2_addr + b_pg_offset;
5964 bcopy(a_cp, b_cp, cnt);
5969 pte2_clear(cmap1_pte2p);
5970 tlb_flush((vm_offset_t)pc->pc_cmap1_addr);
5971 pte2_clear(cmap2_pte2p);
5972 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5974 mtx_unlock(&pc->pc_cmap_lock);
5978 pmap_quick_enter_page(vm_page_t m)
5985 pte2p = pc->pc_qmap_pte2p;
5987 KASSERT(pte2_load(pte2p) == 0, ("%s: PTE2 busy", __func__));
5989 pte2_store(pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5990 vm_page_pte2_attr(m)));
5991 return (pc->pc_qmap_addr);
5995 pmap_quick_remove_page(vm_offset_t addr)
6001 pte2p = pc->pc_qmap_pte2p;
6003 KASSERT(addr == pc->pc_qmap_addr, ("%s: invalid address", __func__));
6004 KASSERT(pte2_load(pte2p) != 0, ("%s: PTE2 not in use", __func__));
6007 tlb_flush(pc->pc_qmap_addr);
6012 * Copy the range specified by src_addr/len
6013 * from the source map to the range dst_addr/len
6014 * in the destination map.
6016 * This routine is only advisory and need not do anything.
6019 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
6020 vm_offset_t src_addr)
6022 struct spglist free;
6024 vm_offset_t end_addr = src_addr + len;
6027 if (dst_addr != src_addr)
6030 if (!pmap_is_current(src_pmap))
6033 rw_wlock(&pvh_global_lock);
6034 if (dst_pmap < src_pmap) {
6035 PMAP_LOCK(dst_pmap);
6036 PMAP_LOCK(src_pmap);
6038 PMAP_LOCK(src_pmap);
6039 PMAP_LOCK(dst_pmap);
6042 for (addr = src_addr; addr < end_addr; addr = nextva) {
6043 pt2_entry_t *src_pte2p, *dst_pte2p;
6044 vm_page_t dst_mpt2pg, src_mpt2pg;
6045 pt1_entry_t src_pte1;
6048 KASSERT(addr < VM_MAXUSER_ADDRESS,
6049 ("%s: invalid to pmap_copy page tables", __func__));
6051 nextva = pte1_trunc(addr + PTE1_SIZE);
6055 pte1_idx = pte1_index(addr);
6056 src_pte1 = src_pmap->pm_pt1[pte1_idx];
6057 if (pte1_is_section(src_pte1)) {
6058 if ((addr & PTE1_OFFSET) != 0 ||
6059 (addr + PTE1_SIZE) > end_addr)
6061 if (dst_pmap->pm_pt1[pte1_idx] == 0 &&
6062 (!pte1_is_managed(src_pte1) ||
6063 pmap_pv_insert_pte1(dst_pmap, addr, src_pte1,
6064 PMAP_ENTER_NORECLAIM))) {
6065 dst_pmap->pm_pt1[pte1_idx] = src_pte1 &
6067 dst_pmap->pm_stats.resident_count +=
6068 PTE1_SIZE / PAGE_SIZE;
6069 pmap_pte1_mappings++;
6072 } else if (!pte1_is_link(src_pte1))
6075 src_mpt2pg = PHYS_TO_VM_PAGE(pte1_link_pa(src_pte1));
6078 * We leave PT2s to be linked from PT1 even if they are not
6079 * referenced until all PT2s in a page are without reference.
6081 * QQQ: It could be changed ...
6083 #if 0 /* single_pt2_link_is_cleared */
6084 KASSERT(pt2_wirecount_get(src_mpt2pg, pte1_idx) > 0,
6085 ("%s: source page table page is unused", __func__));
6087 if (pt2_wirecount_get(src_mpt2pg, pte1_idx) == 0)
6090 if (nextva > end_addr)
6093 src_pte2p = pt2map_entry(addr);
6094 while (addr < nextva) {
6095 pt2_entry_t temp_pte2;
6096 temp_pte2 = pte2_load(src_pte2p);
6098 * we only virtual copy managed pages
6100 if (pte2_is_managed(temp_pte2)) {
6101 dst_mpt2pg = pmap_allocpte2(dst_pmap, addr,
6102 PMAP_ENTER_NOSLEEP);
6103 if (dst_mpt2pg == NULL)
6105 dst_pte2p = pmap_pte2_quick(dst_pmap, addr);
6106 if (!pte2_is_valid(pte2_load(dst_pte2p)) &&
6107 pmap_try_insert_pv_entry(dst_pmap, addr,
6108 PHYS_TO_VM_PAGE(pte2_pa(temp_pte2)))) {
6110 * Clear the wired, modified, and
6111 * accessed (referenced) bits
6114 temp_pte2 &= ~(PTE2_W | PTE2_A);
6115 temp_pte2 |= PTE2_NM;
6116 pte2_store(dst_pte2p, temp_pte2);
6117 dst_pmap->pm_stats.resident_count++;
6120 if (pmap_unwire_pt2(dst_pmap, addr,
6121 dst_mpt2pg, &free)) {
6122 pmap_tlb_flush(dst_pmap, addr);
6123 vm_page_free_pages_toq(&free,
6128 if (pt2_wirecount_get(dst_mpt2pg, pte1_idx) >=
6129 pt2_wirecount_get(src_mpt2pg, pte1_idx))
6138 rw_wunlock(&pvh_global_lock);
6139 PMAP_UNLOCK(src_pmap);
6140 PMAP_UNLOCK(dst_pmap);
6144 * Increase the starting virtual address of the given mapping if a
6145 * different alignment might result in more section mappings.
6148 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6149 vm_offset_t *addr, vm_size_t size)
6151 vm_offset_t pte1_offset;
6153 if (size < PTE1_SIZE)
6155 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6156 offset += ptoa(object->pg_color);
6157 pte1_offset = offset & PTE1_OFFSET;
6158 if (size - ((PTE1_SIZE - pte1_offset) & PTE1_OFFSET) < PTE1_SIZE ||
6159 (*addr & PTE1_OFFSET) == pte1_offset)
6161 if ((*addr & PTE1_OFFSET) < pte1_offset)
6162 *addr = pte1_trunc(*addr) + pte1_offset;
6164 *addr = pte1_roundup(*addr) + pte1_offset;
6168 pmap_activate(struct thread *td)
6170 pmap_t pmap, oldpmap;
6173 PDEBUG(9, printf("%s: td = %08x\n", __func__, (uint32_t)td));
6176 pmap = vmspace_pmap(td->td_proc->p_vmspace);
6177 oldpmap = PCPU_GET(curpmap);
6178 cpuid = PCPU_GET(cpuid);
6181 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
6182 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
6184 CPU_CLR(cpuid, &oldpmap->pm_active);
6185 CPU_SET(cpuid, &pmap->pm_active);
6188 ttb = pmap_ttb_get(pmap);
6191 * pmap_activate is for the current thread on the current cpu
6193 td->td_pcb->pcb_pagedir = ttb;
6195 PCPU_SET(curpmap, pmap);
6200 * Perform the pmap work for mincore(2). If the page is not both referenced and
6201 * modified by this pmap, returns its physical address so that the caller can
6202 * find other mappings.
6205 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
6207 pt1_entry_t *pte1p, pte1;
6208 pt2_entry_t *pte2p, pte2;
6214 pte1p = pmap_pte1(pmap, addr);
6215 pte1 = pte1_load(pte1p);
6216 if (pte1_is_section(pte1)) {
6217 pa = trunc_page(pte1_pa(pte1) | (addr & PTE1_OFFSET));
6218 managed = pte1_is_managed(pte1);
6219 val = MINCORE_PSIND(1) | MINCORE_INCORE;
6220 if (pte1_is_dirty(pte1))
6221 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6223 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6224 } else if (pte1_is_link(pte1)) {
6225 pte2p = pmap_pte2(pmap, addr);
6226 pte2 = pte2_load(pte2p);
6227 pmap_pte2_release(pte2p);
6229 managed = pte2_is_managed(pte2);
6230 val = MINCORE_INCORE;
6231 if (pte2_is_dirty(pte2))
6232 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6234 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6239 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
6240 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
6248 pmap_kenter_device(vm_offset_t va, vm_size_t size, vm_paddr_t pa)
6253 KASSERT((size & PAGE_MASK) == 0,
6254 ("%s: device mapping not page-sized", __func__));
6257 l2attr = vm_memattr_to_pte2(VM_MEMATTR_DEVICE);
6259 pmap_kenter_prot_attr(va, pa, PTE2_AP_KRW, l2attr);
6264 tlb_flush_range(sva, va - sva);
6268 pmap_kremove_device(vm_offset_t va, vm_size_t size)
6272 KASSERT((size & PAGE_MASK) == 0,
6273 ("%s: device mapping not page-sized", __func__));
6281 tlb_flush_range(sva, va - sva);
6285 pmap_set_pcb_pagedir(pmap_t pmap, struct pcb *pcb)
6288 pcb->pcb_pagedir = pmap_ttb_get(pmap);
6292 * Clean L1 data cache range by physical address.
6293 * The range must be within a single page.
6296 pmap_dcache_wb_pou(vm_paddr_t pa, vm_size_t size, uint32_t attr)
6298 pt2_entry_t *cmap2_pte2p;
6301 KASSERT(((pa & PAGE_MASK) + size) <= PAGE_SIZE,
6302 ("%s: not on single page", __func__));
6306 cmap2_pte2p = pc->pc_cmap2_pte2p;
6307 mtx_lock(&pc->pc_cmap_lock);
6308 if (pte2_load(cmap2_pte2p) != 0)
6309 panic("%s: CMAP2 busy", __func__);
6310 pte2_store(cmap2_pte2p, PTE2_KERN_NG(pa, PTE2_AP_KRW, attr));
6311 dcache_wb_pou((vm_offset_t)pc->pc_cmap2_addr + (pa & PAGE_MASK), size);
6312 pte2_clear(cmap2_pte2p);
6313 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
6315 mtx_unlock(&pc->pc_cmap_lock);
6319 * Sync instruction cache range which is not mapped yet.
6322 cache_icache_sync_fresh(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
6324 uint32_t len, offset;
6327 /* Write back d-cache on given address range. */
6328 offset = pa & PAGE_MASK;
6329 for ( ; size != 0; size -= len, pa += len, offset = 0) {
6330 len = min(PAGE_SIZE - offset, size);
6331 m = PHYS_TO_VM_PAGE(pa);
6332 KASSERT(m != NULL, ("%s: vm_page_t is null for %#x",
6334 pmap_dcache_wb_pou(pa, len, vm_page_pte2_attr(m));
6337 * I-cache is VIPT. Only way how to flush all virtual mappings
6338 * on given physical address is to invalidate all i-cache.
6344 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t size)
6347 /* Write back d-cache on given address range. */
6348 if (va >= VM_MIN_KERNEL_ADDRESS) {
6349 dcache_wb_pou(va, size);
6351 uint32_t len, offset;
6355 offset = va & PAGE_MASK;
6356 for ( ; size != 0; size -= len, va += len, offset = 0) {
6357 pa = pmap_extract(pmap, va); /* offset is preserved */
6358 len = min(PAGE_SIZE - offset, size);
6359 m = PHYS_TO_VM_PAGE(pa);
6360 KASSERT(m != NULL, ("%s: vm_page_t is null for %#x",
6362 pmap_dcache_wb_pou(pa, len, vm_page_pte2_attr(m));
6366 * I-cache is VIPT. Only way how to flush all virtual mappings
6367 * on given physical address is to invalidate all i-cache.
6373 * The implementation of pmap_fault() uses IN_RANGE2() macro which
6374 * depends on the fact that given range size is a power of 2.
6376 CTASSERT(powerof2(NB_IN_PT1));
6377 CTASSERT(powerof2(PT2MAP_SIZE));
6379 #define IN_RANGE2(addr, start, size) \
6380 ((vm_offset_t)(start) == ((vm_offset_t)(addr) & ~((size) - 1)))
6383 * Handle access and R/W emulation faults.
6386 pmap_fault(pmap_t pmap, vm_offset_t far, uint32_t fsr, int idx, bool usermode)
6388 pt1_entry_t *pte1p, pte1;
6389 pt2_entry_t *pte2p, pte2;
6395 * In kernel, we should never get abort with FAR which is in range of
6396 * pmap->pm_pt1 or PT2MAP address spaces. If it happens, stop here
6397 * and print out a useful abort message and even get to the debugger
6398 * otherwise it likely ends with never ending loop of aborts.
6400 if (__predict_false(IN_RANGE2(far, pmap->pm_pt1, NB_IN_PT1))) {
6402 * All L1 tables should always be mapped and present.
6403 * However, we check only current one herein. For user mode,
6404 * only permission abort from malicious user is not fatal.
6405 * And alignment abort as it may have higher priority.
6407 if (!usermode || (idx != FAULT_ALIGN && idx != FAULT_PERM_L2)) {
6408 CTR4(KTR_PMAP, "%s: pmap %#x pm_pt1 %#x far %#x",
6409 __func__, pmap, pmap->pm_pt1, far);
6410 panic("%s: pm_pt1 abort", __func__);
6412 return (KERN_INVALID_ADDRESS);
6414 if (__predict_false(IN_RANGE2(far, PT2MAP, PT2MAP_SIZE))) {
6416 * PT2MAP should be always mapped and present in current
6417 * L1 table. However, only existing L2 tables are mapped
6418 * in PT2MAP. For user mode, only L2 translation abort and
6419 * permission abort from malicious user is not fatal.
6420 * And alignment abort as it may have higher priority.
6422 if (!usermode || (idx != FAULT_ALIGN &&
6423 idx != FAULT_TRAN_L2 && idx != FAULT_PERM_L2)) {
6424 CTR4(KTR_PMAP, "%s: pmap %#x PT2MAP %#x far %#x",
6425 __func__, pmap, PT2MAP, far);
6426 panic("%s: PT2MAP abort", __func__);
6428 return (KERN_INVALID_ADDRESS);
6432 * A pmap lock is used below for handling of access and R/W emulation
6433 * aborts. They were handled by atomic operations before so some
6434 * analysis of new situation is needed to answer the following question:
6435 * Is it safe to use the lock even for these aborts?
6437 * There may happen two cases in general:
6439 * (1) Aborts while the pmap lock is locked already - this should not
6440 * happen as pmap lock is not recursive. However, under pmap lock only
6441 * internal kernel data should be accessed and such data should be
6442 * mapped with A bit set and NM bit cleared. If double abort happens,
6443 * then a mapping of data which has caused it must be fixed. Further,
6444 * all new mappings are always made with A bit set and the bit can be
6445 * cleared only on managed mappings.
6447 * (2) Aborts while another lock(s) is/are locked - this already can
6448 * happen. However, there is no difference here if it's either access or
6449 * R/W emulation abort, or if it's some other abort.
6454 pte1 = pte1_load(pmap_pte1(pmap, far));
6455 if (pte1_is_link(pte1)) {
6457 * Check in advance that associated L2 page table is mapped into
6458 * PT2MAP space. Note that faulty access to not mapped L2 page
6459 * table is caught in more general check above where "far" is
6460 * checked that it does not lay in PT2MAP space. Note also that
6461 * L1 page table and PT2TAB always exist and are mapped.
6463 pte2 = pt2tab_load(pmap_pt2tab_entry(pmap, far));
6464 if (!pte2_is_valid(pte2))
6465 panic("%s: missing L2 page table (%p, %#x)",
6466 __func__, pmap, far);
6471 * Special treatment is due to break-before-make approach done when
6472 * pte1 is updated for userland mapping during section promotion or
6473 * demotion. If not caught here, pmap_enter() can find a section
6474 * mapping on faulting address. That is not allowed.
6476 if (idx == FAULT_TRAN_L1 && usermode && cp15_ats1cur_check(far) == 0) {
6478 return (KERN_SUCCESS);
6482 * Accesss bits for page and section. Note that the entry
6483 * is not in TLB yet, so TLB flush is not necessary.
6485 * QQQ: This is hardware emulation, we do not call userret()
6486 * for aborts from user mode.
6488 if (idx == FAULT_ACCESS_L2) {
6489 pte1 = pte1_load(pmap_pte1(pmap, far));
6490 if (pte1_is_link(pte1)) {
6491 /* L2 page table should exist and be mapped. */
6492 pte2p = pt2map_entry(far);
6493 pte2 = pte2_load(pte2p);
6494 if (pte2_is_valid(pte2)) {
6495 pte2_store(pte2p, pte2 | PTE2_A);
6497 return (KERN_SUCCESS);
6501 * We got L2 access fault but PTE1 is not a link.
6502 * Probably some race happened, do nothing.
6504 CTR3(KTR_PMAP, "%s: FAULT_ACCESS_L2 - pmap %#x far %#x",
6505 __func__, pmap, far);
6507 return (KERN_SUCCESS);
6510 if (idx == FAULT_ACCESS_L1) {
6511 pte1p = pmap_pte1(pmap, far);
6512 pte1 = pte1_load(pte1p);
6513 if (pte1_is_section(pte1)) {
6514 pte1_store(pte1p, pte1 | PTE1_A);
6516 return (KERN_SUCCESS);
6519 * We got L1 access fault but PTE1 is not section
6520 * mapping. Probably some race happened, do nothing.
6522 CTR3(KTR_PMAP, "%s: FAULT_ACCESS_L1 - pmap %#x far %#x",
6523 __func__, pmap, far);
6525 return (KERN_SUCCESS);
6530 * Handle modify bits for page and section. Note that the modify
6531 * bit is emulated by software. So PTEx_RO is software read only
6532 * bit and PTEx_NM flag is real hardware read only bit.
6534 * QQQ: This is hardware emulation, we do not call userret()
6535 * for aborts from user mode.
6537 if ((fsr & FSR_WNR) && (idx == FAULT_PERM_L2)) {
6538 pte1 = pte1_load(pmap_pte1(pmap, far));
6539 if (pte1_is_link(pte1)) {
6540 /* L2 page table should exist and be mapped. */
6541 pte2p = pt2map_entry(far);
6542 pte2 = pte2_load(pte2p);
6543 if (pte2_is_valid(pte2) && !(pte2 & PTE2_RO) &&
6545 pte2_store(pte2p, pte2 & ~PTE2_NM);
6546 tlb_flush(trunc_page(far));
6548 return (KERN_SUCCESS);
6552 * We got L2 permission fault but PTE1 is not a link.
6553 * Probably some race happened, do nothing.
6555 CTR3(KTR_PMAP, "%s: FAULT_PERM_L2 - pmap %#x far %#x",
6556 __func__, pmap, far);
6558 return (KERN_SUCCESS);
6561 if ((fsr & FSR_WNR) && (idx == FAULT_PERM_L1)) {
6562 pte1p = pmap_pte1(pmap, far);
6563 pte1 = pte1_load(pte1p);
6564 if (pte1_is_section(pte1)) {
6565 if (!(pte1 & PTE1_RO) && (pte1 & PTE1_NM)) {
6566 pte1_store(pte1p, pte1 & ~PTE1_NM);
6567 tlb_flush(pte1_trunc(far));
6569 return (KERN_SUCCESS);
6573 * We got L1 permission fault but PTE1 is not section
6574 * mapping. Probably some race happened, do nothing.
6576 CTR3(KTR_PMAP, "%s: FAULT_PERM_L1 - pmap %#x far %#x",
6577 __func__, pmap, far);
6579 return (KERN_SUCCESS);
6584 * QQQ: The previous code, mainly fast handling of access and
6585 * modify bits aborts, could be moved to ASM. Now we are
6586 * starting to deal with not fast aborts.
6589 return (KERN_FAILURE);
6592 #if defined(PMAP_DEBUG)
6594 * Reusing of KVA used in pmap_zero_page function !!!
6597 pmap_zero_page_check(vm_page_t m)
6599 pt2_entry_t *cmap2_pte2p;
6605 cmap2_pte2p = pc->pc_cmap2_pte2p;
6606 mtx_lock(&pc->pc_cmap_lock);
6607 if (pte2_load(cmap2_pte2p) != 0)
6608 panic("%s: CMAP2 busy", __func__);
6609 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
6610 vm_page_pte2_attr(m)));
6611 end = (uint32_t*)(pc->pc_cmap2_addr + PAGE_SIZE);
6612 for (p = (uint32_t*)pc->pc_cmap2_addr; p < end; p++)
6614 panic("%s: page %p not zero, va: %p", __func__, m,
6616 pte2_clear(cmap2_pte2p);
6617 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
6619 mtx_unlock(&pc->pc_cmap_lock);
6623 pmap_pid_dump(int pid)
6630 sx_slock(&allproc_lock);
6631 FOREACH_PROC_IN_SYSTEM(p) {
6632 if (p->p_pid != pid || p->p_vmspace == NULL)
6635 pmap = vmspace_pmap(p->p_vmspace);
6636 for (i = 0; i < NPTE1_IN_PT1; i++) {
6638 pt2_entry_t *pte2p, pte2;
6639 vm_offset_t base, va;
6643 base = i << PTE1_SHIFT;
6644 pte1 = pte1_load(&pmap->pm_pt1[i]);
6646 if (pte1_is_section(pte1)) {
6648 * QQQ: Do something here!
6650 } else if (pte1_is_link(pte1)) {
6651 for (j = 0; j < NPTE2_IN_PT2; j++) {
6652 va = base + (j << PAGE_SHIFT);
6653 if (va >= VM_MIN_KERNEL_ADDRESS) {
6658 sx_sunlock(&allproc_lock);
6661 pte2p = pmap_pte2(pmap, va);
6662 pte2 = pte2_load(pte2p);
6663 pmap_pte2_release(pte2p);
6664 if (!pte2_is_valid(pte2))
6668 m = PHYS_TO_VM_PAGE(pa);
6669 printf("va: 0x%x, pa: 0x%x, w: %d, "
6671 m->ref_count, m->flags);
6684 sx_sunlock(&allproc_lock);
6691 static pt2_entry_t *
6692 pmap_pte2_ddb(pmap_t pmap, vm_offset_t va)
6695 vm_paddr_t pt2pg_pa;
6697 pte1 = pte1_load(pmap_pte1(pmap, va));
6698 if (!pte1_is_link(pte1))
6701 if (pmap_is_current(pmap))
6702 return (pt2map_entry(va));
6704 /* Note that L2 page table size is not equal to PAGE_SIZE. */
6705 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
6706 if (pte2_pa(pte2_load(PMAP3)) != pt2pg_pa) {
6707 pte2_store(PMAP3, PTE2_KPT(pt2pg_pa));
6709 PMAP3cpu = PCPU_GET(cpuid);
6711 tlb_flush_local((vm_offset_t)PADDR3);
6714 else if (PMAP3cpu != PCPU_GET(cpuid)) {
6715 PMAP3cpu = PCPU_GET(cpuid);
6716 tlb_flush_local((vm_offset_t)PADDR3);
6719 return (PADDR3 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
6723 dump_pmap(pmap_t pmap)
6726 printf("pmap %p\n", pmap);
6727 printf(" pm_pt1: %p\n", pmap->pm_pt1);
6728 printf(" pm_pt2tab: %p\n", pmap->pm_pt2tab);
6729 printf(" pm_active: 0x%08lX\n", pmap->pm_active.__bits[0]);
6732 DB_SHOW_COMMAND(pmaps, pmap_list_pmaps)
6736 LIST_FOREACH(pmap, &allpmaps, pm_list) {
6742 pte2_class(pt2_entry_t pte2)
6746 cls = (pte2 >> 2) & 0x03;
6747 cls |= (pte2 >> 4) & 0x04;
6752 dump_section(pmap_t pmap, uint32_t pte1_idx)
6757 dump_link(pmap_t pmap, uint32_t pte1_idx, boolean_t invalid_ok)
6761 pt2_entry_t *pte2p, pte2;
6764 va = pte1_idx << PTE1_SHIFT;
6765 pte2p = pmap_pte2_ddb(pmap, va);
6766 for (i = 0; i < NPTE2_IN_PT2; i++, pte2p++, va += PAGE_SIZE) {
6767 pte2 = pte2_load(pte2p);
6770 if (!pte2_is_valid(pte2)) {
6771 printf(" 0x%08X: 0x%08X", va, pte2);
6773 printf(" - not valid !!!");
6777 m = PHYS_TO_VM_PAGE(pte2_pa(pte2));
6778 printf(" 0x%08X: 0x%08X, TEX%d, s:%d, g:%d, m:%p", va , pte2,
6779 pte2_class(pte2), !!(pte2 & PTE2_S), !(pte2 & PTE2_NG), m);
6781 printf(" v:%d w:%d f:0x%04X\n", m->valid,
6782 m->ref_count, m->flags);
6789 static __inline boolean_t
6790 is_pv_chunk_space(vm_offset_t va)
6793 if ((((vm_offset_t)pv_chunkbase) <= va) &&
6794 (va < ((vm_offset_t)pv_chunkbase + PAGE_SIZE * pv_maxchunks)))
6799 DB_SHOW_COMMAND(pmap, pmap_pmap_print)
6801 /* XXX convert args. */
6802 pmap_t pmap = (pmap_t)addr;
6805 vm_offset_t va, eva;
6808 boolean_t invalid_ok, dump_link_ok, dump_pv_chunk;
6813 LIST_FOREACH(pm, &allpmaps, pm_list)
6814 if (pm == pmap) break;
6816 printf("given pmap %p is not in allpmaps list\n", pmap);
6820 pmap = PCPU_GET(curpmap);
6822 eva = (modif[0] == 'u') ? VM_MAXUSER_ADDRESS : 0xFFFFFFFF;
6823 dump_pv_chunk = FALSE; /* XXX evaluate from modif[] */
6825 printf("pmap: 0x%08X\n", (uint32_t)pmap);
6826 printf("PT2MAP: 0x%08X\n", (uint32_t)PT2MAP);
6827 printf("pt2tab: 0x%08X\n", (uint32_t)pmap->pm_pt2tab);
6829 for(i = 0; i < NPTE1_IN_PT1; i++) {
6830 pte1 = pte1_load(&pmap->pm_pt1[i]);
6833 va = i << PTE1_SHIFT;
6837 if (pte1_is_section(pte1)) {
6838 printf("0x%08X: Section 0x%08X, s:%d g:%d\n", va, pte1,
6839 !!(pte1 & PTE1_S), !(pte1 & PTE1_NG));
6840 dump_section(pmap, i);
6841 } else if (pte1_is_link(pte1)) {
6842 dump_link_ok = TRUE;
6844 pte2 = pte2_load(pmap_pt2tab_entry(pmap, va));
6845 m = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
6846 printf("0x%08X: Link 0x%08X, pt2tab: 0x%08X m: %p",
6848 if (is_pv_chunk_space(va)) {
6849 printf(" - pv_chunk space");
6853 dump_link_ok = FALSE;
6856 printf(" w:%d w2:%u", m->ref_count,
6857 pt2_wirecount_get(m, pte1_index(va)));
6859 printf(" !!! pt2tab entry is ZERO");
6860 else if (pte2_pa(pte1) != pte2_pa(pte2))
6861 printf(" !!! pt2tab entry is DIFFERENT - m: %p",
6862 PHYS_TO_VM_PAGE(pte2_pa(pte2)));
6865 dump_link(pmap, i, invalid_ok);
6867 printf("0x%08X: Invalid entry 0x%08X\n", va, pte1);
6872 dump_pt2tab(pmap_t pmap)
6880 printf("PT2TAB:\n");
6881 for (i = 0; i < PT2TAB_ENTRIES; i++) {
6882 pte2 = pte2_load(&pmap->pm_pt2tab[i]);
6883 if (!pte2_is_valid(pte2))
6885 va = i << PT2TAB_SHIFT;
6887 m = PHYS_TO_VM_PAGE(pa);
6888 printf(" 0x%08X: 0x%08X, TEX%d, s:%d, m:%p", va, pte2,
6889 pte2_class(pte2), !!(pte2 & PTE2_S), m);
6891 printf(" , w: %d, f: 0x%04X pidx: %lld",
6892 m->ref_count, m->flags, m->pindex);
6897 DB_SHOW_COMMAND(pmap_pt2tab, pmap_pt2tab_print)
6899 /* XXX convert args. */
6900 pmap_t pmap = (pmap_t)addr;
6907 printf("supported only on current pmap\n");
6911 pmap = PCPU_GET(curpmap);
6912 printf("curpmap: 0x%08X\n", (uint32_t)pmap);
6913 printf("PT2MAP: 0x%08X\n", (uint32_t)PT2MAP);
6914 printf("pt2tab: 0x%08X\n", (uint32_t)pmap->pm_pt2tab);
6916 start = pte1_index((vm_offset_t)PT2MAP);
6917 for (i = start; i < (start + NPT2_IN_PT2TAB); i++) {
6918 pte1 = pte1_load(&pmap->pm_pt1[i]);
6921 va = i << PTE1_SHIFT;
6922 if (pte1_is_section(pte1)) {
6923 printf("0x%08X: Section 0x%08X, s:%d\n", va, pte1,
6925 dump_section(pmap, i);
6926 } else if (pte1_is_link(pte1)) {
6927 pte2 = pte2_load(pmap_pt2tab_entry(pmap, va));
6928 printf("0x%08X: Link 0x%08X, pt2tab: 0x%08X\n", va,
6931 printf(" !!! pt2tab entry is ZERO\n");
6933 printf("0x%08X: Invalid entry 0x%08X\n", va, pte1);