2 * SPDX-License-Identifier: BSD-3-Clause AND BSD-2-Clause-FreeBSD
4 * Copyright (c) 1991 Regents of the University of California.
5 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
7 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
8 * Copyright (c) 2014-2016 Svatopluk Kraus <skra@FreeBSD.org>
9 * Copyright (c) 2014-2016 Michal Meloun <mmel@FreeBSD.org>
10 * All rights reserved.
12 * This code is derived from software contributed to Berkeley by
13 * the Systems Programming Group of the University of Utah Computer
14 * Science Department and William Jolitz of UUNET Technologies Inc.
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions
19 * 1. Redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution.
24 * 3. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
43 * Copyright (c) 2003 Networks Associates Technology, Inc.
44 * All rights reserved.
46 * This software was developed for the FreeBSD Project by Jake Burkholder,
47 * Safeport Network Services, and Network Associates Laboratories, the
48 * Security Research Division of Network Associates, Inc. under
49 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
50 * CHATS research program.
52 * Redistribution and use in source and binary forms, with or without
53 * modification, are permitted provided that the following conditions
55 * 1. Redistributions of source code must retain the above copyright
56 * notice, this list of conditions and the following disclaimer.
57 * 2. Redistributions in binary form must reproduce the above copyright
58 * notice, this list of conditions and the following disclaimer in the
59 * documentation and/or other materials provided with the distribution.
61 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
62 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
64 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
74 #include <sys/cdefs.h>
75 __FBSDID("$FreeBSD$");
78 * Manages physical address maps.
80 * Since the information managed by this module is
81 * also stored by the logical address mapping module,
82 * this module may throw away valid virtual-to-physical
83 * mappings at almost any time. However, invalidations
84 * of virtual-to-physical mappings must be done as
87 * In order to cope with hardware architectures which
88 * make virtual-to-physical map invalidates expensive,
89 * this module may delay invalidate or reduced protection
90 * operations until such time as they are actually
91 * necessary. This module is given full information as
92 * to which processors are currently using which maps,
93 * and to when physical maps must be made correct.
100 #include <sys/param.h>
101 #include <sys/systm.h>
102 #include <sys/kernel.h>
104 #include <sys/lock.h>
105 #include <sys/proc.h>
106 #include <sys/rwlock.h>
107 #include <sys/malloc.h>
108 #include <sys/vmmeter.h>
109 #include <sys/malloc.h>
110 #include <sys/mman.h>
111 #include <sys/sf_buf.h>
113 #include <sys/sched.h>
114 #include <sys/sysctl.h>
120 #include <machine/physmem.h>
125 #include <vm/vm_param.h>
126 #include <vm/vm_kern.h>
127 #include <vm/vm_object.h>
128 #include <vm/vm_map.h>
129 #include <vm/vm_page.h>
130 #include <vm/vm_pageout.h>
131 #include <vm/vm_phys.h>
132 #include <vm/vm_extern.h>
133 #include <vm/vm_reserv.h>
134 #include <sys/lock.h>
135 #include <sys/mutex.h>
137 #include <machine/md_var.h>
138 #include <machine/pmap_var.h>
139 #include <machine/cpu.h>
140 #include <machine/pcb.h>
141 #include <machine/sf_buf.h>
143 #include <machine/smp.h>
145 #ifndef PMAP_SHPGPERPROC
146 #define PMAP_SHPGPERPROC 200
150 #define PMAP_INLINE __inline
156 static void pmap_zero_page_check(vm_page_t m);
157 void pmap_debug(int level);
158 int pmap_pid_dump(int pid);
160 #define PDEBUG(_lev_,_stat_) \
161 if (pmap_debug_level >= (_lev_)) \
163 #define dprintf printf
164 int pmap_debug_level = 1;
165 #else /* PMAP_DEBUG */
166 #define PDEBUG(_lev_,_stat_) /* Nothing */
167 #define dprintf(x, arg...)
168 #endif /* PMAP_DEBUG */
171 * Level 2 page tables map definion ('max' is excluded).
174 #define PT2V_MIN_ADDRESS ((vm_offset_t)PT2MAP)
175 #define PT2V_MAX_ADDRESS ((vm_offset_t)PT2MAP + PT2MAP_SIZE)
177 #define UPT2V_MIN_ADDRESS ((vm_offset_t)PT2MAP)
178 #define UPT2V_MAX_ADDRESS \
179 ((vm_offset_t)(PT2MAP + (KERNBASE >> PT2MAP_SHIFT)))
182 * Promotion to a 1MB (PTE1) page mapping requires that the corresponding
183 * 4KB (PTE2) page mappings have identical settings for the following fields:
185 #define PTE2_PROMOTE (PTE2_V | PTE2_A | PTE2_NM | PTE2_S | PTE2_NG | \
186 PTE2_NX | PTE2_RO | PTE2_U | PTE2_W | \
189 #define PTE1_PROMOTE (PTE1_V | PTE1_A | PTE1_NM | PTE1_S | PTE1_NG | \
190 PTE1_NX | PTE1_RO | PTE1_U | PTE1_W | \
193 #define ATTR_TO_L1(l2_attr) ((((l2_attr) & L2_TEX0) ? L1_S_TEX0 : 0) | \
194 (((l2_attr) & L2_C) ? L1_S_C : 0) | \
195 (((l2_attr) & L2_B) ? L1_S_B : 0) | \
196 (((l2_attr) & PTE2_A) ? PTE1_A : 0) | \
197 (((l2_attr) & PTE2_NM) ? PTE1_NM : 0) | \
198 (((l2_attr) & PTE2_S) ? PTE1_S : 0) | \
199 (((l2_attr) & PTE2_NG) ? PTE1_NG : 0) | \
200 (((l2_attr) & PTE2_NX) ? PTE1_NX : 0) | \
201 (((l2_attr) & PTE2_RO) ? PTE1_RO : 0) | \
202 (((l2_attr) & PTE2_U) ? PTE1_U : 0) | \
203 (((l2_attr) & PTE2_W) ? PTE1_W : 0))
205 #define ATTR_TO_L2(l1_attr) ((((l1_attr) & L1_S_TEX0) ? L2_TEX0 : 0) | \
206 (((l1_attr) & L1_S_C) ? L2_C : 0) | \
207 (((l1_attr) & L1_S_B) ? L2_B : 0) | \
208 (((l1_attr) & PTE1_A) ? PTE2_A : 0) | \
209 (((l1_attr) & PTE1_NM) ? PTE2_NM : 0) | \
210 (((l1_attr) & PTE1_S) ? PTE2_S : 0) | \
211 (((l1_attr) & PTE1_NG) ? PTE2_NG : 0) | \
212 (((l1_attr) & PTE1_NX) ? PTE2_NX : 0) | \
213 (((l1_attr) & PTE1_RO) ? PTE2_RO : 0) | \
214 (((l1_attr) & PTE1_U) ? PTE2_U : 0) | \
215 (((l1_attr) & PTE1_W) ? PTE2_W : 0))
218 * PTE2 descriptors creation macros.
220 #define PTE2_ATTR_DEFAULT vm_memattr_to_pte2(VM_MEMATTR_DEFAULT)
221 #define PTE2_ATTR_PT vm_memattr_to_pte2(pt_memattr)
223 #define PTE2_KPT(pa) PTE2_KERN(pa, PTE2_AP_KRW, PTE2_ATTR_PT)
224 #define PTE2_KPT_NG(pa) PTE2_KERN_NG(pa, PTE2_AP_KRW, PTE2_ATTR_PT)
226 #define PTE2_KRW(pa) PTE2_KERN(pa, PTE2_AP_KRW, PTE2_ATTR_DEFAULT)
227 #define PTE2_KRO(pa) PTE2_KERN(pa, PTE2_AP_KR, PTE2_ATTR_DEFAULT)
231 #define PV_STAT(x) do { x ; } while (0)
233 #define PV_STAT(x) do { } while (0)
237 * The boot_pt1 is used temporary in very early boot stage as L1 page table.
238 * We can init many things with no memory allocation thanks to its static
239 * allocation and this brings two main advantages:
240 * (1) other cores can be started very simply,
241 * (2) various boot loaders can be supported as its arguments can be processed
242 * in virtual address space and can be moved to safe location before
243 * first allocation happened.
244 * Only disadvantage is that boot_pt1 is used only in very early boot stage.
245 * However, the table is uninitialized and so lays in bss. Therefore kernel
246 * image size is not influenced.
248 * QQQ: In the future, maybe, boot_pt1 can be used for soft reset and
249 * CPU suspend/resume game.
251 extern pt1_entry_t boot_pt1[];
254 pt1_entry_t *kern_pt1;
255 pt2_entry_t *kern_pt2tab;
258 static uint32_t ttb_flags;
259 static vm_memattr_t pt_memattr;
260 ttb_entry_t pmap_kern_ttb;
262 struct pmap kernel_pmap_store;
263 LIST_HEAD(pmaplist, pmap);
264 static struct pmaplist allpmaps;
265 static struct mtx allpmaps_lock;
267 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
268 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
270 static vm_offset_t kernel_vm_end_new;
271 vm_offset_t kernel_vm_end = KERNBASE + NKPT2PG * NPT2_IN_PG * PTE1_SIZE;
272 vm_offset_t vm_max_kernel_address;
273 vm_paddr_t kernel_l1pa;
275 static struct rwlock __aligned(CACHE_LINE_SIZE) pvh_global_lock;
278 * Data for the pv entry allocation mechanism
280 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
281 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
282 static struct md_page *pv_table; /* XXX: Is it used only the list in md_page? */
283 static int shpgperproc = PMAP_SHPGPERPROC;
285 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
286 int pv_maxchunks; /* How many chunks we have KVA for */
287 vm_offset_t pv_vafree; /* freelist stored in the PTE */
289 vm_paddr_t first_managed_pa;
290 #define pa_to_pvh(pa) (&pv_table[pte1_index(pa - first_managed_pa)])
293 * All those kernel PT submaps that BSD is so fond of
300 static caddr_t crashdumpmap;
302 static pt2_entry_t *PMAP1 = NULL, *PMAP2;
303 static pt2_entry_t *PADDR1 = NULL, *PADDR2;
305 static pt2_entry_t *PMAP3;
306 static pt2_entry_t *PADDR3;
307 static int PMAP3cpu __unused; /* for SMP only */
311 static int PMAP1changedcpu;
312 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
314 "Number of times pmap_pte2_quick changed CPU with same PMAP1");
316 static int PMAP1changed;
317 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
319 "Number of times pmap_pte2_quick changed PMAP1");
320 static int PMAP1unchanged;
321 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
323 "Number of times pmap_pte2_quick didn't change PMAP1");
324 static struct mtx PMAP2mutex;
327 * Internal flags for pmap_enter()'s helper functions.
329 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
330 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
332 static __inline void pt2_wirecount_init(vm_page_t m);
333 static boolean_t pmap_demote_pte1(pmap_t pmap, pt1_entry_t *pte1p,
335 static int pmap_enter_pte1(pmap_t pmap, vm_offset_t va, pt1_entry_t pte1,
336 u_int flags, vm_page_t m);
337 void cache_icache_sync_fresh(vm_offset_t va, vm_paddr_t pa, vm_size_t size);
340 * Function to set the debug level of the pmap code.
344 pmap_debug(int level)
347 pmap_debug_level = level;
348 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
350 #endif /* PMAP_DEBUG */
353 * This table must corespond with memory attribute configuration in vm.h.
354 * First entry is used for normal system mapping.
356 * Device memory is always marked as shared.
357 * Normal memory is shared only in SMP .
358 * Not outer shareable bits are not used yet.
359 * Class 6 cannot be used on ARM11.
361 #define TEXDEF_TYPE_SHIFT 0
362 #define TEXDEF_TYPE_MASK 0x3
363 #define TEXDEF_INNER_SHIFT 2
364 #define TEXDEF_INNER_MASK 0x3
365 #define TEXDEF_OUTER_SHIFT 4
366 #define TEXDEF_OUTER_MASK 0x3
367 #define TEXDEF_NOS_SHIFT 6
368 #define TEXDEF_NOS_MASK 0x1
370 #define TEX(t, i, o, s) \
371 ((t) << TEXDEF_TYPE_SHIFT) | \
372 ((i) << TEXDEF_INNER_SHIFT) | \
373 ((o) << TEXDEF_OUTER_SHIFT | \
374 ((s) << TEXDEF_NOS_SHIFT))
376 static uint32_t tex_class[8] = {
377 /* type inner cache outer cache */
378 TEX(PRRR_MEM, NMRR_WB_WA, NMRR_WB_WA, 0), /* 0 - ATTR_WB_WA */
379 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 1 - ATTR_NOCACHE */
380 TEX(PRRR_DEV, NMRR_NC, NMRR_NC, 0), /* 2 - ATTR_DEVICE */
381 TEX(PRRR_SO, NMRR_NC, NMRR_NC, 0), /* 3 - ATTR_SO */
382 TEX(PRRR_MEM, NMRR_WT, NMRR_WT, 0), /* 4 - ATTR_WT */
383 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 5 - NOT USED YET */
384 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 6 - NOT USED YET */
385 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 7 - NOT USED YET */
389 static uint32_t pte2_attr_tab[8] = {
390 PTE2_ATTR_WB_WA, /* 0 - VM_MEMATTR_WB_WA */
391 PTE2_ATTR_NOCACHE, /* 1 - VM_MEMATTR_NOCACHE */
392 PTE2_ATTR_DEVICE, /* 2 - VM_MEMATTR_DEVICE */
393 PTE2_ATTR_SO, /* 3 - VM_MEMATTR_SO */
394 PTE2_ATTR_WT, /* 4 - VM_MEMATTR_WRITE_THROUGH */
395 0, /* 5 - NOT USED YET */
396 0, /* 6 - NOT USED YET */
397 0 /* 7 - NOT USED YET */
399 CTASSERT(VM_MEMATTR_WB_WA == 0);
400 CTASSERT(VM_MEMATTR_NOCACHE == 1);
401 CTASSERT(VM_MEMATTR_DEVICE == 2);
402 CTASSERT(VM_MEMATTR_SO == 3);
403 CTASSERT(VM_MEMATTR_WRITE_THROUGH == 4);
404 #define VM_MEMATTR_END (VM_MEMATTR_WRITE_THROUGH + 1)
407 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
410 return (mode >= 0 && mode < VM_MEMATTR_END);
413 static inline uint32_t
414 vm_memattr_to_pte2(vm_memattr_t ma)
417 KASSERT((u_int)ma < VM_MEMATTR_END,
418 ("%s: bad vm_memattr_t %d", __func__, ma));
419 return (pte2_attr_tab[(u_int)ma]);
422 static inline uint32_t
423 vm_page_pte2_attr(vm_page_t m)
426 return (vm_memattr_to_pte2(m->md.pat_mode));
430 * Convert TEX definition entry to TTB flags.
433 encode_ttb_flags(int idx)
435 uint32_t inner, outer, nos, reg;
437 inner = (tex_class[idx] >> TEXDEF_INNER_SHIFT) &
439 outer = (tex_class[idx] >> TEXDEF_OUTER_SHIFT) &
441 nos = (tex_class[idx] >> TEXDEF_NOS_SHIFT) &
446 if (cpuinfo.coherent_walk)
447 reg |= (inner & 0x1) << 6;
448 reg |= (inner & 0x2) >> 1;
458 * Set TEX remapping registers in current CPU.
464 uint32_t type, inner, outer, nos;
467 #ifdef PMAP_PTE_NOCACHE
469 if (cpuinfo.coherent_walk) {
470 pt_memattr = VM_MEMATTR_WB_WA;
471 ttb_flags = encode_ttb_flags(0);
474 pt_memattr = VM_MEMATTR_NOCACHE;
475 ttb_flags = encode_ttb_flags(1);
478 pt_memattr = VM_MEMATTR_WB_WA;
479 ttb_flags = encode_ttb_flags(0);
485 /* Build remapping register from TEX classes. */
486 for (i = 0; i < 8; i++) {
487 type = (tex_class[i] >> TEXDEF_TYPE_SHIFT) &
489 inner = (tex_class[i] >> TEXDEF_INNER_SHIFT) &
491 outer = (tex_class[i] >> TEXDEF_OUTER_SHIFT) &
493 nos = (tex_class[i] >> TEXDEF_NOS_SHIFT) &
496 prrr |= type << (i * 2);
497 prrr |= nos << (i + 24);
498 nmrr |= inner << (i * 2);
499 nmrr |= outer << (i * 2 + 16);
501 /* Add shareable bits for device memory. */
502 prrr |= PRRR_DS0 | PRRR_DS1;
504 /* Add shareable bits for normal memory in SMP case. */
513 /* Caches are disabled, so full TLB flush should be enough. */
514 tlb_flush_all_local();
518 * Remap one vm_meattr class to another one. This can be useful as
519 * workaround for SOC errata, e.g. if devices must be accessed using
522 * !!! Please note that this function is absolutely last resort thing.
523 * It should not be used under normal circumstances. !!!
526 * - it shall be called after pmap_bootstrap_prepare() and before
527 * cpu_mp_start() (thus only on boot CPU). In practice, it's expected
528 * to be called from platform_attach() or platform_late_init().
530 * - if remapping doesn't change caching mode, or until uncached class
531 * is remapped to any kind of cached one, then no other restriction exists.
533 * - if pmap_remap_vm_attr() changes caching mode, but both (original and
534 * remapped) remain cached, then caller is resposible for calling
535 * of dcache_wbinv_poc_all().
537 * - remapping of any kind of cached class to uncached is not permitted.
540 pmap_remap_vm_attr(vm_memattr_t old_attr, vm_memattr_t new_attr)
542 int old_idx, new_idx;
544 /* Map VM memattrs to indexes to tex_class table. */
545 old_idx = PTE2_ATTR2IDX(pte2_attr_tab[(int)old_attr]);
546 new_idx = PTE2_ATTR2IDX(pte2_attr_tab[(int)new_attr]);
548 /* Replace TEX attribute and apply it. */
549 tex_class[old_idx] = tex_class[new_idx];
554 * KERNBASE must be multiple of NPT2_IN_PG * PTE1_SIZE. In other words,
555 * KERNBASE is mapped by first L2 page table in L2 page table page. It
556 * meets same constrain due to PT2MAP being placed just under KERNBASE.
558 CTASSERT((KERNBASE & (NPT2_IN_PG * PTE1_SIZE - 1)) == 0);
559 CTASSERT((KERNBASE - VM_MAXUSER_ADDRESS) >= PT2MAP_SIZE);
562 * In crazy dreams, PAGE_SIZE could be a multiple of PTE2_SIZE in general.
563 * For now, anyhow, the following check must be fulfilled.
565 CTASSERT(PAGE_SIZE == PTE2_SIZE);
567 * We don't want to mess up MI code with all MMU and PMAP definitions,
568 * so some things, which depend on other ones, are defined independently.
569 * Now, it is time to check that we don't screw up something.
571 CTASSERT(PDRSHIFT == PTE1_SHIFT);
573 * Check L1 and L2 page table entries definitions consistency.
575 CTASSERT(NB_IN_PT1 == (sizeof(pt1_entry_t) * NPTE1_IN_PT1));
576 CTASSERT(NB_IN_PT2 == (sizeof(pt2_entry_t) * NPTE2_IN_PT2));
578 * Check L2 page tables page consistency.
580 CTASSERT(PAGE_SIZE == (NPT2_IN_PG * NB_IN_PT2));
581 CTASSERT((1 << PT2PG_SHIFT) == NPT2_IN_PG);
583 * Check PT2TAB consistency.
584 * PT2TAB_ENTRIES is defined as a division of NPTE1_IN_PT1 by NPT2_IN_PG.
585 * This should be done without remainder.
587 CTASSERT(NPTE1_IN_PT1 == (PT2TAB_ENTRIES * NPT2_IN_PG));
592 * All level 2 page tables (PT2s) are mapped continuously and accordingly
593 * into PT2MAP address space. As PT2 size is less than PAGE_SIZE, this can
594 * be done only if PAGE_SIZE is a multiple of PT2 size. All PT2s in one page
595 * must be used together, but not necessary at once. The first PT2 in a page
596 * must map things on correctly aligned address and the others must follow
599 #define NB_IN_PT2TAB (PT2TAB_ENTRIES * sizeof(pt2_entry_t))
600 #define NPT2_IN_PT2TAB (NB_IN_PT2TAB / NB_IN_PT2)
601 #define NPG_IN_PT2TAB (NB_IN_PT2TAB / PAGE_SIZE)
604 * Check PT2TAB consistency.
605 * NPT2_IN_PT2TAB is defined as a division of NB_IN_PT2TAB by NB_IN_PT2.
606 * NPG_IN_PT2TAB is defined as a division of NB_IN_PT2TAB by PAGE_SIZE.
607 * The both should be done without remainder.
609 CTASSERT(NB_IN_PT2TAB == (NPT2_IN_PT2TAB * NB_IN_PT2));
610 CTASSERT(NB_IN_PT2TAB == (NPG_IN_PT2TAB * PAGE_SIZE));
612 * The implementation was made general, however, with the assumption
613 * bellow in mind. In case of another value of NPG_IN_PT2TAB,
614 * the code should be once more rechecked.
616 CTASSERT(NPG_IN_PT2TAB == 1);
619 * Get offset of PT2 in a page
620 * associated with given PT1 index.
622 static __inline u_int
623 page_pt2off(u_int pt1_idx)
626 return ((pt1_idx & PT2PG_MASK) * NB_IN_PT2);
630 * Get physical address of PT2
631 * associated with given PT2s page and PT1 index.
633 static __inline vm_paddr_t
634 page_pt2pa(vm_paddr_t pgpa, u_int pt1_idx)
637 return (pgpa + page_pt2off(pt1_idx));
641 * Get first entry of PT2
642 * associated with given PT2s page and PT1 index.
644 static __inline pt2_entry_t *
645 page_pt2(vm_offset_t pgva, u_int pt1_idx)
648 return ((pt2_entry_t *)(pgva + page_pt2off(pt1_idx)));
652 * Get virtual address of PT2s page (mapped in PT2MAP)
653 * which holds PT2 which holds entry which maps given virtual address.
655 static __inline vm_offset_t
656 pt2map_pt2pg(vm_offset_t va)
659 va &= ~(NPT2_IN_PG * PTE1_SIZE - 1);
660 return ((vm_offset_t)pt2map_entry(va));
663 /*****************************************************************************
665 * THREE pmap initialization milestones exist:
668 * -> fundamental init (including MMU) in ASM
671 * -> fundamental init continues in C
672 * -> first available physical address is known
674 * pmap_bootstrap_prepare() -> FIRST PMAP MILESTONE (first epoch begins)
675 * -> basic (safe) interface for physical address allocation is made
676 * -> basic (safe) interface for virtual mapping is made
677 * -> limited not SMP coherent work is possible
679 * -> more fundamental init continues in C
680 * -> locks and some more things are available
681 * -> all fundamental allocations and mappings are done
683 * pmap_bootstrap() -> SECOND PMAP MILESTONE (second epoch begins)
684 * -> phys_avail[] and virtual_avail is set
685 * -> control is passed to vm subsystem
686 * -> physical and virtual address allocation are off limit
687 * -> low level mapping functions, some SMP coherent,
688 * are available, which cannot be used before vm subsystem
692 * -> vm subsystem is being inited
694 * pmap_init() -> THIRD PMAP MILESTONE (third epoch begins)
695 * -> pmap is fully inited
697 *****************************************************************************/
699 /*****************************************************************************
701 * PMAP first stage initialization and utility functions
702 * for pre-bootstrap epoch.
704 * After pmap_bootstrap_prepare() is called, the following functions
707 * (1) strictly only for this stage functions for physical page allocations,
708 * virtual space allocations, and mappings:
710 * vm_paddr_t pmap_preboot_get_pages(u_int num);
711 * void pmap_preboot_map_pages(vm_paddr_t pa, vm_offset_t va, u_int num);
712 * vm_offset_t pmap_preboot_reserve_pages(u_int num);
713 * vm_offset_t pmap_preboot_get_vpages(u_int num);
714 * void pmap_preboot_map_attr(vm_paddr_t pa, vm_offset_t va, vm_size_t size,
715 * vm_prot_t prot, vm_memattr_t attr);
717 * (2) for all stages:
719 * vm_paddr_t pmap_kextract(vm_offset_t va);
721 * NOTE: This is not SMP coherent stage.
723 *****************************************************************************/
725 #define KERNEL_P2V(pa) \
726 ((vm_offset_t)((pa) - arm_physmem_kernaddr + KERNVIRTADDR))
727 #define KERNEL_V2P(va) \
728 ((vm_paddr_t)((va) - KERNVIRTADDR + arm_physmem_kernaddr))
730 static vm_paddr_t last_paddr;
733 * Pre-bootstrap epoch page allocator.
736 pmap_preboot_get_pages(u_int num)
741 last_paddr += num * PAGE_SIZE;
747 * The fundamental initialization of PMAP stuff.
749 * Some things already happened in locore.S and some things could happen
750 * before pmap_bootstrap_prepare() is called, so let's recall what is done:
751 * 1. Caches are disabled.
752 * 2. We are running on virtual addresses already with 'boot_pt1'
754 * 3. So far, all virtual addresses can be converted to physical ones and
755 * vice versa by the following macros:
756 * KERNEL_P2V(pa) .... physical to virtual ones,
757 * KERNEL_V2P(va) .... virtual to physical ones.
759 * What is done herein:
760 * 1. The 'boot_pt1' is replaced by real kernel L1 page table 'kern_pt1'.
761 * 2. PT2MAP magic is brought to live.
762 * 3. Basic preboot functions for page allocations and mappings can be used.
763 * 4. Everything is prepared for L1 cache enabling.
766 * 1. To use second TTB register, so kernel and users page tables will be
767 * separated. This way process forking - pmap_pinit() - could be faster,
768 * it saves physical pages and KVA per a process, and it's simple change.
769 * However, it will lead, due to hardware matter, to the following:
770 * (a) 2G space for kernel and 2G space for users.
771 * (b) 1G space for kernel in low addresses and 3G for users above it.
772 * A question is: Is the case (b) really an option? Note that case (b)
773 * does save neither physical memory and KVA.
776 pmap_bootstrap_prepare(vm_paddr_t last)
778 vm_paddr_t pt2pg_pa, pt2tab_pa, pa, size;
779 vm_offset_t pt2pg_va;
786 * Now, we are going to make real kernel mapping. Note that we are
787 * already running on some mapping made in locore.S and we expect
788 * that it's large enough to ensure nofault access to physical memory
789 * allocated herein before switch.
791 * As kernel image and everything needed before are and will be mapped
792 * by section mappings, we align last physical address to PTE1_SIZE.
794 last_paddr = pte1_roundup(last);
797 * Allocate and zero page(s) for kernel L1 page table.
799 * Note that it's first allocation on space which was PTE1_SIZE
800 * aligned and as such base_pt1 is aligned to NB_IN_PT1 too.
802 base_pt1 = pmap_preboot_get_pages(NPG_IN_PT1);
803 kern_pt1 = (pt1_entry_t *)KERNEL_P2V(base_pt1);
804 bzero((void*)kern_pt1, NB_IN_PT1);
805 pte1_sync_range(kern_pt1, NB_IN_PT1);
807 /* Allocate and zero page(s) for kernel PT2TAB. */
808 pt2tab_pa = pmap_preboot_get_pages(NPG_IN_PT2TAB);
809 kern_pt2tab = (pt2_entry_t *)KERNEL_P2V(pt2tab_pa);
810 bzero(kern_pt2tab, NB_IN_PT2TAB);
811 pte2_sync_range(kern_pt2tab, NB_IN_PT2TAB);
813 /* Allocate and zero page(s) for kernel L2 page tables. */
814 pt2pg_pa = pmap_preboot_get_pages(NKPT2PG);
815 pt2pg_va = KERNEL_P2V(pt2pg_pa);
816 size = NKPT2PG * PAGE_SIZE;
817 bzero((void*)pt2pg_va, size);
818 pte2_sync_range((pt2_entry_t *)pt2pg_va, size);
821 * Add a physical memory segment (vm_phys_seg) corresponding to the
822 * preallocated pages for kernel L2 page tables so that vm_page
823 * structures representing these pages will be created. The vm_page
824 * structures are required for promotion of the corresponding kernel
825 * virtual addresses to section mappings.
827 vm_phys_add_seg(pt2tab_pa, pmap_preboot_get_pages(0));
830 * Insert allocated L2 page table pages to PT2TAB and make
831 * link to all PT2s in L1 page table. See how kernel_vm_end
834 * We play simple and safe. So every KVA will have underlaying
835 * L2 page table, even kernel image mapped by sections.
837 pte2p = kern_pt2tab_entry(KERNBASE);
838 for (pa = pt2pg_pa; pa < pt2pg_pa + size; pa += PTE2_SIZE)
839 pt2tab_store(pte2p++, PTE2_KPT(pa));
841 pte1p = kern_pte1(KERNBASE);
842 for (pa = pt2pg_pa; pa < pt2pg_pa + size; pa += NB_IN_PT2)
843 pte1_store(pte1p++, PTE1_LINK(pa));
845 /* Make section mappings for kernel. */
846 l1_attr = ATTR_TO_L1(PTE2_ATTR_DEFAULT);
847 pte1p = kern_pte1(KERNBASE);
848 for (pa = KERNEL_V2P(KERNBASE); pa < last; pa += PTE1_SIZE)
849 pte1_store(pte1p++, PTE1_KERN(pa, PTE1_AP_KRW, l1_attr));
852 * Get free and aligned space for PT2MAP and make L1 page table links
853 * to L2 page tables held in PT2TAB.
855 * Note that pages holding PT2s are stored in PT2TAB as pt2_entry_t
856 * descriptors and PT2TAB page(s) itself is(are) used as PT2s. Thus
857 * each entry in PT2TAB maps all PT2s in a page. This implies that
858 * virtual address of PT2MAP must be aligned to NPT2_IN_PG * PTE1_SIZE.
860 PT2MAP = (pt2_entry_t *)(KERNBASE - PT2MAP_SIZE);
861 pte1p = kern_pte1((vm_offset_t)PT2MAP);
862 for (pa = pt2tab_pa, i = 0; i < NPT2_IN_PT2TAB; i++, pa += NB_IN_PT2) {
863 pte1_store(pte1p++, PTE1_LINK(pa));
867 * Store PT2TAB in PT2TAB itself, i.e. self reference mapping.
868 * Each pmap will hold own PT2TAB, so the mapping should be not global.
870 pte2p = kern_pt2tab_entry((vm_offset_t)PT2MAP);
871 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE) {
872 pt2tab_store(pte2p++, PTE2_KPT_NG(pa));
876 * Choose correct L2 page table and make mappings for allocations
877 * made herein which replaces temporary locore.S mappings after a while.
878 * Note that PT2MAP cannot be used until we switch to kern_pt1.
880 * Note, that these allocations started aligned on 1M section and
881 * kernel PT1 was allocated first. Making of mappings must follow
882 * order of physical allocations as we've used KERNEL_P2V() macro
883 * for virtual addresses resolution.
885 pte2p = kern_pt2tab_entry((vm_offset_t)kern_pt1);
886 pt2pg_va = KERNEL_P2V(pte2_pa(pte2_load(pte2p)));
888 pte2p = page_pt2(pt2pg_va, pte1_index((vm_offset_t)kern_pt1));
890 /* Make mapping for kernel L1 page table. */
891 for (pa = base_pt1, i = 0; i < NPG_IN_PT1; i++, pa += PTE2_SIZE)
892 pte2_store(pte2p++, PTE2_KPT(pa));
894 /* Make mapping for kernel PT2TAB. */
895 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE)
896 pte2_store(pte2p++, PTE2_KPT(pa));
898 /* Finally, switch from 'boot_pt1' to 'kern_pt1'. */
899 pmap_kern_ttb = base_pt1 | ttb_flags;
900 cpuinfo_reinit_mmu(pmap_kern_ttb);
902 * Initialize the first available KVA. As kernel image is mapped by
903 * sections, we are leaving some gap behind.
905 virtual_avail = (vm_offset_t)kern_pt2tab + NPG_IN_PT2TAB * PAGE_SIZE;
909 * Setup L2 page table page for given KVA.
910 * Used in pre-bootstrap epoch.
912 * Note that we have allocated NKPT2PG pages for L2 page tables in advance
913 * and used them for mapping KVA starting from KERNBASE. However, this is not
914 * enough. Vectors and devices need L2 page tables too. Note that they are
915 * even above VM_MAX_KERNEL_ADDRESS.
917 static __inline vm_paddr_t
918 pmap_preboot_pt2pg_setup(vm_offset_t va)
920 pt2_entry_t *pte2p, pte2;
923 /* Get associated entry in PT2TAB. */
924 pte2p = kern_pt2tab_entry(va);
926 /* Just return, if PT2s page exists already. */
927 pte2 = pt2tab_load(pte2p);
928 if (pte2_is_valid(pte2))
929 return (pte2_pa(pte2));
931 KASSERT(va >= VM_MAX_KERNEL_ADDRESS,
932 ("%s: NKPT2PG too small", __func__));
935 * Allocate page for PT2s and insert it to PT2TAB.
936 * In other words, map it into PT2MAP space.
938 pt2pg_pa = pmap_preboot_get_pages(1);
939 pt2tab_store(pte2p, PTE2_KPT(pt2pg_pa));
941 /* Zero all PT2s in allocated page. */
942 bzero((void*)pt2map_pt2pg(va), PAGE_SIZE);
943 pte2_sync_range((pt2_entry_t *)pt2map_pt2pg(va), PAGE_SIZE);
949 * Setup L2 page table for given KVA.
950 * Used in pre-bootstrap epoch.
953 pmap_preboot_pt2_setup(vm_offset_t va)
956 vm_paddr_t pt2pg_pa, pt2_pa;
958 /* Setup PT2's page. */
959 pt2pg_pa = pmap_preboot_pt2pg_setup(va);
960 pt2_pa = page_pt2pa(pt2pg_pa, pte1_index(va));
962 /* Insert PT2 to PT1. */
963 pte1p = kern_pte1(va);
964 pte1_store(pte1p, PTE1_LINK(pt2_pa));
968 * Get L2 page entry associated with given KVA.
969 * Used in pre-bootstrap epoch.
971 static __inline pt2_entry_t*
972 pmap_preboot_vtopte2(vm_offset_t va)
976 /* Setup PT2 if needed. */
977 pte1p = kern_pte1(va);
978 if (!pte1_is_valid(pte1_load(pte1p))) /* XXX - sections ?! */
979 pmap_preboot_pt2_setup(va);
981 return (pt2map_entry(va));
985 * Pre-bootstrap epoch page(s) mapping(s).
988 pmap_preboot_map_pages(vm_paddr_t pa, vm_offset_t va, u_int num)
993 /* Map all the pages. */
994 for (i = 0; i < num; i++) {
995 pte2p = pmap_preboot_vtopte2(va);
996 pte2_store(pte2p, PTE2_KRW(pa));
1003 * Pre-bootstrap epoch virtual space alocator.
1006 pmap_preboot_reserve_pages(u_int num)
1009 vm_offset_t start, va;
1012 /* Allocate virtual space. */
1013 start = va = virtual_avail;
1014 virtual_avail += num * PAGE_SIZE;
1016 /* Zero the mapping. */
1017 for (i = 0; i < num; i++) {
1018 pte2p = pmap_preboot_vtopte2(va);
1019 pte2_store(pte2p, 0);
1027 * Pre-bootstrap epoch page(s) allocation and mapping(s).
1030 pmap_preboot_get_vpages(u_int num)
1035 /* Allocate physical page(s). */
1036 pa = pmap_preboot_get_pages(num);
1038 /* Allocate virtual space. */
1040 virtual_avail += num * PAGE_SIZE;
1042 /* Map and zero all. */
1043 pmap_preboot_map_pages(pa, va, num);
1044 bzero((void *)va, num * PAGE_SIZE);
1050 * Pre-bootstrap epoch page mapping(s) with attributes.
1053 pmap_preboot_map_attr(vm_paddr_t pa, vm_offset_t va, vm_size_t size,
1054 vm_prot_t prot, vm_memattr_t attr)
1057 u_int l1_attr, l1_prot, l2_prot, l2_attr;
1061 l2_prot = prot & VM_PROT_WRITE ? PTE2_AP_KRW : PTE2_AP_KR;
1062 l2_prot |= (prot & VM_PROT_EXECUTE) ? PTE2_X : PTE2_NX;
1063 l2_attr = vm_memattr_to_pte2(attr);
1064 l1_prot = ATTR_TO_L1(l2_prot);
1065 l1_attr = ATTR_TO_L1(l2_attr);
1067 /* Map all the pages. */
1068 num = round_page(size);
1070 if ((((va | pa) & PTE1_OFFSET) == 0) && (num >= PTE1_SIZE)) {
1071 pte1p = kern_pte1(va);
1072 pte1_store(pte1p, PTE1_KERN(pa, l1_prot, l1_attr));
1077 pte2p = pmap_preboot_vtopte2(va);
1078 pte2_store(pte2p, PTE2_KERN(pa, l2_prot, l2_attr));
1087 * Extract from the kernel page table the physical address
1088 * that is mapped by the given virtual address "va".
1091 pmap_kextract(vm_offset_t va)
1097 pte1 = pte1_load(kern_pte1(va));
1098 if (pte1_is_section(pte1)) {
1099 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1100 } else if (pte1_is_link(pte1)) {
1102 * We should beware of concurrent promotion that changes
1103 * pte1 at this point. However, it's not a problem as PT2
1104 * page is preserved by promotion in PT2TAB. So even if
1105 * it happens, using of PT2MAP is still safe.
1107 * QQQ: However, concurrent removing is a problem which
1108 * ends in abort on PT2MAP space. Locking must be used
1109 * to deal with this.
1111 pte2 = pte2_load(pt2map_entry(va));
1112 pa = pte2_pa(pte2) | (va & PTE2_OFFSET);
1115 panic("%s: va %#x pte1 %#x", __func__, va, pte1);
1121 * Extract from the kernel page table the physical address
1122 * that is mapped by the given virtual address "va". Also
1123 * return L2 page table entry which maps the address.
1125 * This is only intended to be used for panic dumps.
1128 pmap_dump_kextract(vm_offset_t va, pt2_entry_t *pte2p)
1134 pte1 = pte1_load(kern_pte1(va));
1135 if (pte1_is_section(pte1)) {
1136 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1137 pte2 = pa | ATTR_TO_L2(pte1) | PTE2_V;
1138 } else if (pte1_is_link(pte1)) {
1139 pte2 = pte2_load(pt2map_entry(va));
1150 /*****************************************************************************
1152 * PMAP second stage initialization and utility functions
1153 * for bootstrap epoch.
1155 * After pmap_bootstrap() is called, the following functions for
1156 * mappings can be used:
1158 * void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
1159 * void pmap_kremove(vm_offset_t va);
1160 * vm_offset_t pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end,
1163 * NOTE: This is not SMP coherent stage. And physical page allocation is not
1164 * allowed during this stage.
1166 *****************************************************************************/
1169 * Initialize kernel PMAP locks and lists, kernel_pmap itself, and
1170 * reserve various virtual spaces for temporary mappings.
1173 pmap_bootstrap(vm_offset_t firstaddr)
1175 pt2_entry_t *unused __unused;
1179 * Initialize the kernel pmap (which is statically allocated).
1181 PMAP_LOCK_INIT(kernel_pmap);
1182 kernel_l1pa = (vm_paddr_t)kern_pt1; /* for libkvm */
1183 kernel_pmap->pm_pt1 = kern_pt1;
1184 kernel_pmap->pm_pt2tab = kern_pt2tab;
1185 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1186 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1189 * Initialize the global pv list lock.
1191 rw_init(&pvh_global_lock, "pmap pv global");
1193 LIST_INIT(&allpmaps);
1196 * Request a spin mutex so that changes to allpmaps cannot be
1197 * preempted by smp_rendezvous_cpus().
1199 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
1200 mtx_lock_spin(&allpmaps_lock);
1201 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
1202 mtx_unlock_spin(&allpmaps_lock);
1205 * Reserve some special page table entries/VA space for temporary
1208 #define SYSMAP(c, p, v, n) do { \
1209 v = (c)pmap_preboot_reserve_pages(n); \
1210 p = pt2map_entry((vm_offset_t)v); \
1214 * Local CMAP1/CMAP2 are used for zeroing and copying pages.
1215 * Local CMAP2 is also used for data cache cleaning.
1218 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
1219 SYSMAP(caddr_t, pc->pc_cmap1_pte2p, pc->pc_cmap1_addr, 1);
1220 SYSMAP(caddr_t, pc->pc_cmap2_pte2p, pc->pc_cmap2_addr, 1);
1221 SYSMAP(vm_offset_t, pc->pc_qmap_pte2p, pc->pc_qmap_addr, 1);
1226 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS);
1229 * _tmppt is used for reading arbitrary physical pages via /dev/mem.
1231 SYSMAP(caddr_t, unused, _tmppt, 1);
1234 * PADDR1 and PADDR2 are used by pmap_pte2_quick() and pmap_pte2(),
1235 * respectively. PADDR3 is used by pmap_pte2_ddb().
1237 SYSMAP(pt2_entry_t *, PMAP1, PADDR1, 1);
1238 SYSMAP(pt2_entry_t *, PMAP2, PADDR2, 1);
1240 SYSMAP(pt2_entry_t *, PMAP3, PADDR3, 1);
1242 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
1245 * Note that in very short time in initarm(), we are going to
1246 * initialize phys_avail[] array and no further page allocation
1247 * can happen after that until vm subsystem will be initialized.
1249 kernel_vm_end_new = kernel_vm_end;
1250 virtual_end = vm_max_kernel_address;
1254 pmap_init_reserved_pages(void)
1263 * Skip if the mapping has already been initialized,
1264 * i.e. this is the BSP.
1266 if (pc->pc_cmap1_addr != 0)
1268 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
1269 pages = kva_alloc(PAGE_SIZE * 3);
1271 panic("%s: unable to allocate KVA", __func__);
1272 pc->pc_cmap1_pte2p = pt2map_entry(pages);
1273 pc->pc_cmap2_pte2p = pt2map_entry(pages + PAGE_SIZE);
1274 pc->pc_qmap_pte2p = pt2map_entry(pages + (PAGE_SIZE * 2));
1275 pc->pc_cmap1_addr = (caddr_t)pages;
1276 pc->pc_cmap2_addr = (caddr_t)(pages + PAGE_SIZE);
1277 pc->pc_qmap_addr = pages + (PAGE_SIZE * 2);
1280 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
1283 * The function can already be use in second initialization stage.
1284 * As such, the function DOES NOT call pmap_growkernel() where PT2
1285 * allocation can happen. So if used, be sure that PT2 for given
1286 * virtual address is allocated already!
1288 * Add a wired page to the kva.
1289 * Note: not SMP coherent.
1291 static __inline void
1292 pmap_kenter_prot_attr(vm_offset_t va, vm_paddr_t pa, uint32_t prot,
1298 pte1p = kern_pte1(va);
1299 if (!pte1_is_valid(pte1_load(pte1p))) { /* XXX - sections ?! */
1301 * This is a very low level function, so PT2 and particularly
1302 * PT2PG associated with given virtual address must be already
1303 * allocated. It's a pain mainly during pmap initialization
1304 * stage. However, called after pmap initialization with
1305 * virtual address not under kernel_vm_end will lead to
1308 if (!pte2_is_valid(pte2_load(kern_pt2tab_entry(va))))
1309 panic("%s: kernel PT2 not allocated!", __func__);
1312 pte2p = pt2map_entry(va);
1313 pte2_store(pte2p, PTE2_KERN(pa, prot, attr));
1317 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1320 pmap_kenter_prot_attr(va, pa, PTE2_AP_KRW, PTE2_ATTR_DEFAULT);
1324 * Remove a page from the kernel pagetables.
1325 * Note: not SMP coherent.
1328 pmap_kremove(vm_offset_t va)
1333 pte1p = kern_pte1(va);
1334 if (pte1_is_section(pte1_load(pte1p))) {
1337 pte2p = pt2map_entry(va);
1343 * Share new kernel PT2PG with all pmaps.
1344 * The caller is responsible for maintaining TLB consistency.
1347 pmap_kenter_pt2tab(vm_offset_t va, pt2_entry_t npte2)
1352 mtx_lock_spin(&allpmaps_lock);
1353 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1354 pte2p = pmap_pt2tab_entry(pmap, va);
1355 pt2tab_store(pte2p, npte2);
1357 mtx_unlock_spin(&allpmaps_lock);
1361 * Share new kernel PTE1 with all pmaps.
1362 * The caller is responsible for maintaining TLB consistency.
1365 pmap_kenter_pte1(vm_offset_t va, pt1_entry_t npte1)
1370 mtx_lock_spin(&allpmaps_lock);
1371 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1372 pte1p = pmap_pte1(pmap, va);
1373 pte1_store(pte1p, npte1);
1375 mtx_unlock_spin(&allpmaps_lock);
1379 * Used to map a range of physical addresses into kernel
1380 * virtual address space.
1382 * The value passed in '*virt' is a suggested virtual address for
1383 * the mapping. Architectures which can support a direct-mapped
1384 * physical to virtual region can return the appropriate address
1385 * within that region, leaving '*virt' unchanged. Other
1386 * architectures should map the pages starting at '*virt' and
1387 * update '*virt' with the first usable address after the mapped
1390 * NOTE: Read the comments above pmap_kenter_prot_attr() as
1391 * the function is used herein!
1394 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1396 vm_offset_t va, sva;
1397 vm_paddr_t pte1_offset;
1399 uint32_t l1prot, l2prot;
1400 uint32_t l1attr, l2attr;
1402 PDEBUG(1, printf("%s: virt = %#x, start = %#x, end = %#x (size = %#x),"
1403 " prot = %d\n", __func__, *virt, start, end, end - start, prot));
1405 l2prot = (prot & VM_PROT_WRITE) ? PTE2_AP_KRW : PTE2_AP_KR;
1406 l2prot |= (prot & VM_PROT_EXECUTE) ? PTE2_X : PTE2_NX;
1407 l1prot = ATTR_TO_L1(l2prot);
1409 l2attr = PTE2_ATTR_DEFAULT;
1410 l1attr = ATTR_TO_L1(l2attr);
1414 * Does the physical address range's size and alignment permit at
1415 * least one section mapping to be created?
1417 pte1_offset = start & PTE1_OFFSET;
1418 if ((end - start) - ((PTE1_SIZE - pte1_offset) & PTE1_OFFSET) >=
1421 * Increase the starting virtual address so that its alignment
1422 * does not preclude the use of section mappings.
1424 if ((va & PTE1_OFFSET) < pte1_offset)
1425 va = pte1_trunc(va) + pte1_offset;
1426 else if ((va & PTE1_OFFSET) > pte1_offset)
1427 va = pte1_roundup(va) + pte1_offset;
1430 while (start < end) {
1431 if ((start & PTE1_OFFSET) == 0 && end - start >= PTE1_SIZE) {
1432 KASSERT((va & PTE1_OFFSET) == 0,
1433 ("%s: misaligned va %#x", __func__, va));
1434 npte1 = PTE1_KERN(start, l1prot, l1attr);
1435 pmap_kenter_pte1(va, npte1);
1439 pmap_kenter_prot_attr(va, start, l2prot, l2attr);
1444 tlb_flush_range(sva, va - sva);
1450 * Make a temporary mapping for a physical address.
1451 * This is only intended to be used for panic dumps.
1454 pmap_kenter_temporary(vm_paddr_t pa, int i)
1458 /* QQQ: 'i' should be less or equal to MAXDUMPPGS. */
1460 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
1461 pmap_kenter(va, pa);
1462 tlb_flush_local(va);
1463 return ((void *)crashdumpmap);
1467 /*************************************
1469 * TLB & cache maintenance routines.
1471 *************************************/
1474 * We inline these within pmap.c for speed.
1477 pmap_tlb_flush(pmap_t pmap, vm_offset_t va)
1480 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1485 pmap_tlb_flush_range(pmap_t pmap, vm_offset_t sva, vm_size_t size)
1488 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1489 tlb_flush_range(sva, size);
1493 * Abuse the pte2 nodes for unmapped kva to thread a kva freelist through.
1495 * - Must deal with pages in order to ensure that none of the PTE2_* bits
1496 * are ever set, PTE2_V in particular.
1497 * - Assumes we can write to pte2s without pte2_store() atomic ops.
1498 * - Assumes nothing will ever test these addresses for 0 to indicate
1499 * no mapping instead of correctly checking PTE2_V.
1500 * - Assumes a vm_offset_t will fit in a pte2 (true for arm).
1501 * Because PTE2_V is never set, there can be no mappings to invalidate.
1504 pmap_pte2list_alloc(vm_offset_t *head)
1511 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
1512 pte2p = pt2map_entry(va);
1515 panic("%s: va with PTE2_V set!", __func__);
1521 pmap_pte2list_free(vm_offset_t *head, vm_offset_t va)
1526 panic("%s: freeing va with PTE2_V set!", __func__);
1527 pte2p = pt2map_entry(va);
1528 *pte2p = *head; /* virtual! PTE2_V is 0 though */
1533 pmap_pte2list_init(vm_offset_t *head, void *base, int npages)
1539 for (i = npages - 1; i >= 0; i--) {
1540 va = (vm_offset_t)base + i * PAGE_SIZE;
1541 pmap_pte2list_free(head, va);
1545 /*****************************************************************************
1547 * PMAP third and final stage initialization.
1549 * After pmap_init() is called, PMAP subsystem is fully initialized.
1551 *****************************************************************************/
1553 SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
1555 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
1556 "Max number of PV entries");
1557 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
1558 "Page share factor per proc");
1560 static u_long nkpt2pg = NKPT2PG;
1561 SYSCTL_ULONG(_vm_pmap, OID_AUTO, nkpt2pg, CTLFLAG_RD,
1562 &nkpt2pg, 0, "Pre-allocated pages for kernel PT2s");
1564 static int sp_enabled = 1;
1565 SYSCTL_INT(_vm_pmap, OID_AUTO, sp_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
1566 &sp_enabled, 0, "Are large page mappings enabled?");
1569 pmap_ps_enabled(pmap_t pmap __unused)
1572 return (sp_enabled != 0);
1575 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pte1, CTLFLAG_RD, 0,
1576 "1MB page mapping counters");
1578 static u_long pmap_pte1_demotions;
1579 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, demotions, CTLFLAG_RD,
1580 &pmap_pte1_demotions, 0, "1MB page demotions");
1582 static u_long pmap_pte1_mappings;
1583 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, mappings, CTLFLAG_RD,
1584 &pmap_pte1_mappings, 0, "1MB page mappings");
1586 static u_long pmap_pte1_p_failures;
1587 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, p_failures, CTLFLAG_RD,
1588 &pmap_pte1_p_failures, 0, "1MB page promotion failures");
1590 static u_long pmap_pte1_promotions;
1591 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, promotions, CTLFLAG_RD,
1592 &pmap_pte1_promotions, 0, "1MB page promotions");
1594 static u_long pmap_pte1_kern_demotions;
1595 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, kern_demotions, CTLFLAG_RD,
1596 &pmap_pte1_kern_demotions, 0, "1MB page kernel demotions");
1598 static u_long pmap_pte1_kern_promotions;
1599 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, kern_promotions, CTLFLAG_RD,
1600 &pmap_pte1_kern_promotions, 0, "1MB page kernel promotions");
1602 static __inline ttb_entry_t
1603 pmap_ttb_get(pmap_t pmap)
1606 return (vtophys(pmap->pm_pt1) | ttb_flags);
1610 * Initialize a vm_page's machine-dependent fields.
1613 * 1. Pages for L2 page tables are always not managed. So, pv_list and
1614 * pt2_wirecount can share same physical space. However, proper
1615 * initialization on a page alloc for page tables and reinitialization
1616 * on the page free must be ensured.
1619 pmap_page_init(vm_page_t m)
1622 TAILQ_INIT(&m->md.pv_list);
1623 pt2_wirecount_init(m);
1624 m->md.pat_mode = VM_MEMATTR_DEFAULT;
1628 * Virtualization for faster way how to zero whole page.
1630 static __inline void
1631 pagezero(void *page)
1634 bzero(page, PAGE_SIZE);
1638 * Zero L2 page table page.
1639 * Use same KVA as in pmap_zero_page().
1641 static __inline vm_paddr_t
1642 pmap_pt2pg_zero(vm_page_t m)
1644 pt2_entry_t *cmap2_pte2p;
1648 pa = VM_PAGE_TO_PHYS(m);
1651 * XXX: For now, we map whole page even if it's already zero,
1652 * to sync it even if the sync is only DSB.
1656 cmap2_pte2p = pc->pc_cmap2_pte2p;
1657 mtx_lock(&pc->pc_cmap_lock);
1658 if (pte2_load(cmap2_pte2p) != 0)
1659 panic("%s: CMAP2 busy", __func__);
1660 pte2_store(cmap2_pte2p, PTE2_KERN_NG(pa, PTE2_AP_KRW,
1661 vm_page_pte2_attr(m)));
1662 /* Even VM_ALLOC_ZERO request is only advisory. */
1663 if ((m->flags & PG_ZERO) == 0)
1664 pagezero(pc->pc_cmap2_addr);
1665 pte2_sync_range((pt2_entry_t *)pc->pc_cmap2_addr, PAGE_SIZE);
1666 pte2_clear(cmap2_pte2p);
1667 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
1670 * Unpin the thread before releasing the lock. Otherwise the thread
1671 * could be rescheduled while still bound to the current CPU, only
1672 * to unpin itself immediately upon resuming execution.
1675 mtx_unlock(&pc->pc_cmap_lock);
1681 * Init just allocated page as L2 page table(s) holder
1682 * and return its physical address.
1684 static __inline vm_paddr_t
1685 pmap_pt2pg_init(pmap_t pmap, vm_offset_t va, vm_page_t m)
1690 /* Check page attributes. */
1691 if (m->md.pat_mode != pt_memattr)
1692 pmap_page_set_memattr(m, pt_memattr);
1694 /* Zero page and init wire counts. */
1695 pa = pmap_pt2pg_zero(m);
1696 pt2_wirecount_init(m);
1699 * Map page to PT2MAP address space for given pmap.
1700 * Note that PT2MAP space is shared with all pmaps.
1702 if (pmap == kernel_pmap)
1703 pmap_kenter_pt2tab(va, PTE2_KPT(pa));
1705 pte2p = pmap_pt2tab_entry(pmap, va);
1706 pt2tab_store(pte2p, PTE2_KPT_NG(pa));
1713 * Initialize the pmap module.
1714 * Called by vm_init, to initialize any structures that the pmap
1715 * system needs to map virtual memory.
1721 pt2_entry_t *pte2p, pte2;
1722 u_int i, pte1_idx, pv_npg;
1724 PDEBUG(1, printf("%s: phys_start = %#x\n", __func__, PHYSADDR));
1727 * Initialize the vm page array entries for kernel pmap's
1728 * L2 page table pages allocated in advance.
1730 pte1_idx = pte1_index(KERNBASE - PT2MAP_SIZE);
1731 pte2p = kern_pt2tab_entry(KERNBASE - PT2MAP_SIZE);
1732 for (i = 0; i < nkpt2pg + NPG_IN_PT2TAB; i++, pte2p++) {
1736 pte2 = pte2_load(pte2p);
1737 KASSERT(pte2_is_valid(pte2), ("%s: no valid entry", __func__));
1740 m = PHYS_TO_VM_PAGE(pa);
1741 KASSERT(m >= vm_page_array &&
1742 m < &vm_page_array[vm_page_array_size],
1743 ("%s: L2 page table page is out of range", __func__));
1745 m->pindex = pte1_idx;
1747 pte1_idx += NPT2_IN_PG;
1751 * Initialize the address space (zone) for the pv entries. Set a
1752 * high water mark so that the system can recover from excessive
1753 * numbers of pv entries.
1755 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1756 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1757 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1758 pv_entry_max = roundup(pv_entry_max, _NPCPV);
1759 pv_entry_high_water = 9 * (pv_entry_max / 10);
1762 * Are large page mappings enabled?
1764 TUNABLE_INT_FETCH("vm.pmap.sp_enabled", &sp_enabled);
1766 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1767 ("%s: can't assign to pagesizes[1]", __func__));
1768 pagesizes[1] = PTE1_SIZE;
1772 * Calculate the size of the pv head table for sections.
1773 * Handle the possibility that "vm_phys_segs[...].end" is zero.
1774 * Note that the table is only for sections which could be promoted.
1776 first_managed_pa = pte1_trunc(vm_phys_segs[0].start);
1777 pv_npg = (pte1_trunc(vm_phys_segs[vm_phys_nsegs - 1].end - PAGE_SIZE)
1778 - first_managed_pa) / PTE1_SIZE + 1;
1781 * Allocate memory for the pv head table for sections.
1783 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1785 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
1787 for (i = 0; i < pv_npg; i++)
1788 TAILQ_INIT(&pv_table[i].pv_list);
1790 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
1791 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
1792 if (pv_chunkbase == NULL)
1793 panic("%s: not enough kvm for pv chunks", __func__);
1794 pmap_pte2list_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
1798 * Add a list of wired pages to the kva
1799 * this routine is only used for temporary
1800 * kernel mappings that do not need to have
1801 * page modification or references recorded.
1802 * Note that old mappings are simply written
1803 * over. The page *must* be wired.
1804 * Note: SMP coherent. Uses a ranged shootdown IPI.
1807 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1810 pt2_entry_t *epte2p, *pte2p, pte2;
1815 pte2p = pt2map_entry(sva);
1816 epte2p = pte2p + count;
1817 while (pte2p < epte2p) {
1819 pa = VM_PAGE_TO_PHYS(m);
1820 pte2 = pte2_load(pte2p);
1821 if ((pte2_pa(pte2) != pa) ||
1822 (pte2_attr(pte2) != vm_page_pte2_attr(m))) {
1824 pte2_store(pte2p, PTE2_KERN(pa, PTE2_AP_KRW,
1825 vm_page_pte2_attr(m)));
1829 if (__predict_false(anychanged))
1830 tlb_flush_range(sva, count * PAGE_SIZE);
1834 * This routine tears out page mappings from the
1835 * kernel -- it is meant only for temporary mappings.
1836 * Note: SMP coherent. Uses a ranged shootdown IPI.
1839 pmap_qremove(vm_offset_t sva, int count)
1844 while (count-- > 0) {
1848 tlb_flush_range(sva, va - sva);
1852 * Are we current address space or kernel?
1855 pmap_is_current(pmap_t pmap)
1858 return (pmap == kernel_pmap ||
1859 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace)));
1863 * If the given pmap is not the current or kernel pmap, the returned
1864 * pte2 must be released by passing it to pmap_pte2_release().
1866 static pt2_entry_t *
1867 pmap_pte2(pmap_t pmap, vm_offset_t va)
1870 vm_paddr_t pt2pg_pa;
1872 pte1 = pte1_load(pmap_pte1(pmap, va));
1873 if (pte1_is_section(pte1))
1874 panic("%s: attempt to map PTE1", __func__);
1875 if (pte1_is_link(pte1)) {
1876 /* Are we current address space or kernel? */
1877 if (pmap_is_current(pmap))
1878 return (pt2map_entry(va));
1879 /* Note that L2 page table size is not equal to PAGE_SIZE. */
1880 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
1881 mtx_lock(&PMAP2mutex);
1882 if (pte2_pa(pte2_load(PMAP2)) != pt2pg_pa) {
1883 pte2_store(PMAP2, PTE2_KPT(pt2pg_pa));
1884 tlb_flush((vm_offset_t)PADDR2);
1886 return (PADDR2 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
1892 * Releases a pte2 that was obtained from pmap_pte2().
1893 * Be prepared for the pte2p being NULL.
1895 static __inline void
1896 pmap_pte2_release(pt2_entry_t *pte2p)
1899 if ((pt2_entry_t *)(trunc_page((vm_offset_t)pte2p)) == PADDR2) {
1900 mtx_unlock(&PMAP2mutex);
1905 * Super fast pmap_pte2 routine best used when scanning
1906 * the pv lists. This eliminates many coarse-grained
1907 * invltlb calls. Note that many of the pv list
1908 * scans are across different pmaps. It is very wasteful
1909 * to do an entire tlb flush for checking a single mapping.
1911 * If the given pmap is not the current pmap, pvh_global_lock
1912 * must be held and curthread pinned to a CPU.
1914 static pt2_entry_t *
1915 pmap_pte2_quick(pmap_t pmap, vm_offset_t va)
1918 vm_paddr_t pt2pg_pa;
1920 pte1 = pte1_load(pmap_pte1(pmap, va));
1921 if (pte1_is_section(pte1))
1922 panic("%s: attempt to map PTE1", __func__);
1923 if (pte1_is_link(pte1)) {
1924 /* Are we current address space or kernel? */
1925 if (pmap_is_current(pmap))
1926 return (pt2map_entry(va));
1927 rw_assert(&pvh_global_lock, RA_WLOCKED);
1928 KASSERT(curthread->td_pinned > 0,
1929 ("%s: curthread not pinned", __func__));
1930 /* Note that L2 page table size is not equal to PAGE_SIZE. */
1931 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
1932 if (pte2_pa(pte2_load(PMAP1)) != pt2pg_pa) {
1933 pte2_store(PMAP1, PTE2_KPT(pt2pg_pa));
1935 PMAP1cpu = PCPU_GET(cpuid);
1937 tlb_flush_local((vm_offset_t)PADDR1);
1941 if (PMAP1cpu != PCPU_GET(cpuid)) {
1942 PMAP1cpu = PCPU_GET(cpuid);
1943 tlb_flush_local((vm_offset_t)PADDR1);
1948 return (PADDR1 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
1954 * Routine: pmap_extract
1956 * Extract the physical page address associated
1957 * with the given map/virtual_address pair.
1960 pmap_extract(pmap_t pmap, vm_offset_t va)
1967 pte1 = pte1_load(pmap_pte1(pmap, va));
1968 if (pte1_is_section(pte1))
1969 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1970 else if (pte1_is_link(pte1)) {
1971 pte2p = pmap_pte2(pmap, va);
1972 pa = pte2_pa(pte2_load(pte2p)) | (va & PTE2_OFFSET);
1973 pmap_pte2_release(pte2p);
1981 * Routine: pmap_extract_and_hold
1983 * Atomically extract and hold the physical page
1984 * with the given pmap and virtual address pair
1985 * if that mapping permits the given protection.
1988 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1990 vm_paddr_t pa, lockpa;
1992 pt2_entry_t pte2, *pte2p;
1999 pte1 = pte1_load(pmap_pte1(pmap, va));
2000 if (pte1_is_section(pte1)) {
2001 if (!(pte1 & PTE1_RO) || !(prot & VM_PROT_WRITE)) {
2002 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
2003 if (vm_page_pa_tryrelock(pmap, pa, &lockpa))
2005 m = PHYS_TO_VM_PAGE(pa);
2008 } else if (pte1_is_link(pte1)) {
2009 pte2p = pmap_pte2(pmap, va);
2010 pte2 = pte2_load(pte2p);
2011 pmap_pte2_release(pte2p);
2012 if (pte2_is_valid(pte2) &&
2013 (!(pte2 & PTE2_RO) || !(prot & VM_PROT_WRITE))) {
2015 if (vm_page_pa_tryrelock(pmap, pa, &lockpa))
2017 m = PHYS_TO_VM_PAGE(pa);
2021 PA_UNLOCK_COND(lockpa);
2027 * Grow the number of kernel L2 page table entries, if needed.
2030 pmap_growkernel(vm_offset_t addr)
2033 vm_paddr_t pt2pg_pa, pt2_pa;
2037 PDEBUG(1, printf("%s: addr = %#x\n", __func__, addr));
2039 * All the time kernel_vm_end is first KVA for which underlying
2040 * L2 page table is either not allocated or linked from L1 page table
2041 * (not considering sections). Except for two possible cases:
2043 * (1) in the very beginning as long as pmap_growkernel() was
2044 * not called, it could be first unused KVA (which is not
2045 * rounded up to PTE1_SIZE),
2047 * (2) when all KVA space is mapped and kernel_map->max_offset
2048 * address is not rounded up to PTE1_SIZE. (For example,
2049 * it could be 0xFFFFFFFF.)
2051 kernel_vm_end = pte1_roundup(kernel_vm_end);
2052 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2053 addr = roundup2(addr, PTE1_SIZE);
2054 if (addr - 1 >= kernel_map->max_offset)
2055 addr = kernel_map->max_offset;
2056 while (kernel_vm_end < addr) {
2057 pte1 = pte1_load(kern_pte1(kernel_vm_end));
2058 if (pte1_is_valid(pte1)) {
2059 kernel_vm_end += PTE1_SIZE;
2060 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2061 kernel_vm_end = kernel_map->max_offset;
2068 * kernel_vm_end_new is used in pmap_pinit() when kernel
2069 * mappings are entered to new pmap all at once to avoid race
2070 * between pmap_kenter_pte1() and kernel_vm_end increase.
2071 * The same aplies to pmap_kenter_pt2tab().
2073 kernel_vm_end_new = kernel_vm_end + PTE1_SIZE;
2075 pte2 = pt2tab_load(kern_pt2tab_entry(kernel_vm_end));
2076 if (!pte2_is_valid(pte2)) {
2078 * Install new PT2s page into kernel PT2TAB.
2080 m = vm_page_alloc(NULL,
2081 pte1_index(kernel_vm_end) & ~PT2PG_MASK,
2082 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2083 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2085 panic("%s: no memory to grow kernel", __func__);
2087 * QQQ: To link all new L2 page tables from L1 page
2088 * table now and so pmap_kenter_pte1() them
2089 * at once together with pmap_kenter_pt2tab()
2090 * could be nice speed up. However,
2091 * pmap_growkernel() does not happen so often...
2092 * QQQ: The other TTBR is another option.
2094 pt2pg_pa = pmap_pt2pg_init(kernel_pmap, kernel_vm_end,
2097 pt2pg_pa = pte2_pa(pte2);
2099 pt2_pa = page_pt2pa(pt2pg_pa, pte1_index(kernel_vm_end));
2100 pmap_kenter_pte1(kernel_vm_end, PTE1_LINK(pt2_pa));
2102 kernel_vm_end = kernel_vm_end_new;
2103 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2104 kernel_vm_end = kernel_map->max_offset;
2111 kvm_size(SYSCTL_HANDLER_ARGS)
2113 unsigned long ksize = vm_max_kernel_address - KERNBASE;
2115 return (sysctl_handle_long(oidp, &ksize, 0, req));
2117 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2118 0, 0, kvm_size, "IU", "Size of KVM");
2121 kvm_free(SYSCTL_HANDLER_ARGS)
2123 unsigned long kfree = vm_max_kernel_address - kernel_vm_end;
2125 return (sysctl_handle_long(oidp, &kfree, 0, req));
2127 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2128 0, 0, kvm_free, "IU", "Amount of KVM free");
2130 /***********************************************
2132 * Pmap allocation/deallocation routines.
2134 ***********************************************/
2137 * Initialize the pmap for the swapper process.
2140 pmap_pinit0(pmap_t pmap)
2142 PDEBUG(1, printf("%s: pmap = %p\n", __func__, pmap));
2144 PMAP_LOCK_INIT(pmap);
2147 * Kernel page table directory and pmap stuff around is already
2148 * initialized, we are using it right now and here. So, finish
2149 * only PMAP structures initialization for process0 ...
2151 * Since the L1 page table and PT2TAB is shared with the kernel pmap,
2152 * which is already included in the list "allpmaps", this pmap does
2153 * not need to be inserted into that list.
2155 pmap->pm_pt1 = kern_pt1;
2156 pmap->pm_pt2tab = kern_pt2tab;
2157 CPU_ZERO(&pmap->pm_active);
2158 PCPU_SET(curpmap, pmap);
2159 TAILQ_INIT(&pmap->pm_pvchunk);
2160 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2161 CPU_SET(0, &pmap->pm_active);
2164 static __inline void
2165 pte1_copy_nosync(pt1_entry_t *spte1p, pt1_entry_t *dpte1p, vm_offset_t sva,
2170 idx = pte1_index(sva);
2171 count = (pte1_index(eva) - idx + 1) * sizeof(pt1_entry_t);
2172 bcopy(spte1p + idx, dpte1p + idx, count);
2175 static __inline void
2176 pt2tab_copy_nosync(pt2_entry_t *spte2p, pt2_entry_t *dpte2p, vm_offset_t sva,
2181 idx = pt2tab_index(sva);
2182 count = (pt2tab_index(eva) - idx + 1) * sizeof(pt2_entry_t);
2183 bcopy(spte2p + idx, dpte2p + idx, count);
2187 * Initialize a preallocated and zeroed pmap structure,
2188 * such as one in a vmspace structure.
2191 pmap_pinit(pmap_t pmap)
2195 vm_paddr_t pa, pt2tab_pa;
2198 PDEBUG(6, printf("%s: pmap = %p, pm_pt1 = %p\n", __func__, pmap,
2202 * No need to allocate L2 page table space yet but we do need
2203 * a valid L1 page table and PT2TAB table.
2205 * Install shared kernel mappings to these tables. It's a little
2206 * tricky as some parts of KVA are reserved for vectors, devices,
2207 * and whatever else. These parts are supposed to be above
2208 * vm_max_kernel_address. Thus two regions should be installed:
2210 * (1) <KERNBASE, kernel_vm_end),
2211 * (2) <vm_max_kernel_address, 0xFFFFFFFF>.
2213 * QQQ: The second region should be stable enough to be installed
2214 * only once in time when the tables are allocated.
2215 * QQQ: Maybe copy of both regions at once could be faster ...
2216 * QQQ: Maybe the other TTBR is an option.
2218 * Finally, install own PT2TAB table to these tables.
2221 if (pmap->pm_pt1 == NULL) {
2222 pmap->pm_pt1 = (pt1_entry_t *)kmem_alloc_contig(NB_IN_PT1,
2223 M_NOWAIT | M_ZERO, 0, -1UL, NB_IN_PT1, 0, pt_memattr);
2224 if (pmap->pm_pt1 == NULL)
2227 if (pmap->pm_pt2tab == NULL) {
2229 * QQQ: (1) PT2TAB must be contiguous. If PT2TAB is one page
2230 * only, what should be the only size for 32 bit systems,
2231 * then we could allocate it with vm_page_alloc() and all
2232 * the stuff needed as other L2 page table pages.
2233 * (2) Note that a process PT2TAB is special L2 page table
2234 * page. Its mapping in kernel_arena is permanent and can
2235 * be used no matter which process is current. Its mapping
2236 * in PT2MAP can be used only for current process.
2238 pmap->pm_pt2tab = (pt2_entry_t *)kmem_alloc_attr(NB_IN_PT2TAB,
2239 M_NOWAIT | M_ZERO, 0, -1UL, pt_memattr);
2240 if (pmap->pm_pt2tab == NULL) {
2242 * QQQ: As struct pmap is allocated from UMA with
2243 * UMA_ZONE_NOFREE flag, it's important to leave
2244 * no allocation in pmap if initialization failed.
2246 kmem_free(kernel_arena, (vm_offset_t)pmap->pm_pt1,
2248 pmap->pm_pt1 = NULL;
2252 * QQQ: Each L2 page table page vm_page_t has pindex set to
2253 * pte1 index of virtual address mapped by this page.
2254 * It's not valid for non kernel PT2TABs themselves.
2255 * The pindex of these pages can not be altered because
2256 * of the way how they are allocated now. However, it
2257 * should not be a problem.
2261 mtx_lock_spin(&allpmaps_lock);
2263 * To avoid race with pmap_kenter_pte1() and pmap_kenter_pt2tab(),
2264 * kernel_vm_end_new is used here instead of kernel_vm_end.
2266 pte1_copy_nosync(kern_pt1, pmap->pm_pt1, KERNBASE,
2267 kernel_vm_end_new - 1);
2268 pte1_copy_nosync(kern_pt1, pmap->pm_pt1, vm_max_kernel_address,
2270 pt2tab_copy_nosync(kern_pt2tab, pmap->pm_pt2tab, KERNBASE,
2271 kernel_vm_end_new - 1);
2272 pt2tab_copy_nosync(kern_pt2tab, pmap->pm_pt2tab, vm_max_kernel_address,
2274 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
2275 mtx_unlock_spin(&allpmaps_lock);
2278 * Store PT2MAP PT2 pages (a.k.a. PT2TAB) in PT2TAB itself.
2279 * I.e. self reference mapping. The PT2TAB is private, however mapped
2280 * into shared PT2MAP space, so the mapping should be not global.
2282 pt2tab_pa = vtophys(pmap->pm_pt2tab);
2283 pte2p = pmap_pt2tab_entry(pmap, (vm_offset_t)PT2MAP);
2284 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE) {
2285 pt2tab_store(pte2p++, PTE2_KPT_NG(pa));
2288 /* Insert PT2MAP PT2s into pmap PT1. */
2289 pte1p = pmap_pte1(pmap, (vm_offset_t)PT2MAP);
2290 for (pa = pt2tab_pa, i = 0; i < NPT2_IN_PT2TAB; i++, pa += NB_IN_PT2) {
2291 pte1_store(pte1p++, PTE1_LINK(pa));
2295 * Now synchronize new mapping which was made above.
2297 pte1_sync_range(pmap->pm_pt1, NB_IN_PT1);
2298 pte2_sync_range(pmap->pm_pt2tab, NB_IN_PT2TAB);
2300 CPU_ZERO(&pmap->pm_active);
2301 TAILQ_INIT(&pmap->pm_pvchunk);
2302 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2309 pt2tab_user_is_empty(pt2_entry_t *tab)
2313 end = pt2tab_index(VM_MAXUSER_ADDRESS);
2314 for (i = 0; i < end; i++)
2315 if (tab[i] != 0) return (FALSE);
2320 * Release any resources held by the given physical map.
2321 * Called when a pmap initialized by pmap_pinit is being released.
2322 * Should only be called if the map contains no valid mappings.
2325 pmap_release(pmap_t pmap)
2328 vm_offset_t start, end;
2330 KASSERT(pmap->pm_stats.resident_count == 0,
2331 ("%s: pmap resident count %ld != 0", __func__,
2332 pmap->pm_stats.resident_count));
2333 KASSERT(pt2tab_user_is_empty(pmap->pm_pt2tab),
2334 ("%s: has allocated user PT2(s)", __func__));
2335 KASSERT(CPU_EMPTY(&pmap->pm_active),
2336 ("%s: pmap %p is active on some CPU(s)", __func__, pmap));
2338 mtx_lock_spin(&allpmaps_lock);
2339 LIST_REMOVE(pmap, pm_list);
2340 mtx_unlock_spin(&allpmaps_lock);
2343 start = pte1_index(KERNBASE) * sizeof(pt1_entry_t);
2344 end = (pte1_index(0xFFFFFFFF) + 1) * sizeof(pt1_entry_t);
2345 bzero((char *)pmap->pm_pt1 + start, end - start);
2347 start = pt2tab_index(KERNBASE) * sizeof(pt2_entry_t);
2348 end = (pt2tab_index(0xFFFFFFFF) + 1) * sizeof(pt2_entry_t);
2349 bzero((char *)pmap->pm_pt2tab + start, end - start);
2352 * We are leaving PT1 and PT2TAB allocated on released pmap,
2353 * so hopefully UMA vmspace_zone will always be inited with
2354 * UMA_ZONE_NOFREE flag.
2358 /*********************************************************
2360 * L2 table pages and their pages management routines.
2362 *********************************************************/
2365 * Virtual interface for L2 page table wire counting.
2367 * Each L2 page table in a page has own counter which counts a number of
2368 * valid mappings in a table. Global page counter counts mappings in all
2369 * tables in a page plus a single itself mapping in PT2TAB.
2371 * During a promotion we leave the associated L2 page table counter
2372 * untouched, so the table (strictly speaking a page which holds it)
2373 * is never freed if promoted.
2375 * If a page m->wire_count == 1 then no valid mappings exist in any L2 page
2376 * table in the page and the page itself is only mapped in PT2TAB.
2379 static __inline void
2380 pt2_wirecount_init(vm_page_t m)
2385 * Note: A page m is allocated with VM_ALLOC_WIRED flag and
2386 * m->wire_count should be already set correctly.
2387 * So, there is no need to set it again herein.
2389 for (i = 0; i < NPT2_IN_PG; i++)
2390 m->md.pt2_wirecount[i] = 0;
2393 static __inline void
2394 pt2_wirecount_inc(vm_page_t m, uint32_t pte1_idx)
2398 * Note: A just modificated pte2 (i.e. already allocated)
2399 * is acquiring one extra reference which must be
2400 * explicitly cleared. It influences the KASSERTs herein.
2401 * All L2 page tables in a page always belong to the same
2402 * pmap, so we allow only one extra reference for the page.
2404 KASSERT(m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] < (NPTE2_IN_PT2 + 1),
2405 ("%s: PT2 is overflowing ...", __func__));
2406 KASSERT(m->wire_count <= (NPTE2_IN_PG + 1),
2407 ("%s: PT2PG is overflowing ...", __func__));
2410 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]++;
2413 static __inline void
2414 pt2_wirecount_dec(vm_page_t m, uint32_t pte1_idx)
2417 KASSERT(m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] != 0,
2418 ("%s: PT2 is underflowing ...", __func__));
2419 KASSERT(m->wire_count > 1,
2420 ("%s: PT2PG is underflowing ...", __func__));
2423 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]--;
2426 static __inline void
2427 pt2_wirecount_set(vm_page_t m, uint32_t pte1_idx, uint16_t count)
2430 KASSERT(count <= NPTE2_IN_PT2,
2431 ("%s: invalid count %u", __func__, count));
2432 KASSERT(m->wire_count > m->md.pt2_wirecount[pte1_idx & PT2PG_MASK],
2433 ("%s: PT2PG corrupting (%u, %u) ...", __func__, m->wire_count,
2434 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]));
2436 m->wire_count -= m->md.pt2_wirecount[pte1_idx & PT2PG_MASK];
2437 m->wire_count += count;
2438 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] = count;
2440 KASSERT(m->wire_count <= (NPTE2_IN_PG + 1),
2441 ("%s: PT2PG is overflowed (%u) ...", __func__, m->wire_count));
2444 static __inline uint32_t
2445 pt2_wirecount_get(vm_page_t m, uint32_t pte1_idx)
2448 return (m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]);
2451 static __inline boolean_t
2452 pt2_is_empty(vm_page_t m, vm_offset_t va)
2455 return (m->md.pt2_wirecount[pte1_index(va) & PT2PG_MASK] == 0);
2458 static __inline boolean_t
2459 pt2_is_full(vm_page_t m, vm_offset_t va)
2462 return (m->md.pt2_wirecount[pte1_index(va) & PT2PG_MASK] ==
2466 static __inline boolean_t
2467 pt2pg_is_empty(vm_page_t m)
2470 return (m->wire_count == 1);
2474 * This routine is called if the L2 page table
2475 * is not mapped correctly.
2478 _pmap_allocpte2(pmap_t pmap, vm_offset_t va, u_int flags)
2484 vm_paddr_t pt2pg_pa, pt2_pa;
2486 pte1_idx = pte1_index(va);
2487 pte1p = pmap->pm_pt1 + pte1_idx;
2489 KASSERT(pte1_load(pte1p) == 0,
2490 ("%s: pm_pt1[%#x] is not zero: %#x", __func__, pte1_idx,
2493 pte2 = pt2tab_load(pmap_pt2tab_entry(pmap, va));
2494 if (!pte2_is_valid(pte2)) {
2496 * Install new PT2s page into pmap PT2TAB.
2498 m = vm_page_alloc(NULL, pte1_idx & ~PT2PG_MASK,
2499 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2501 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2503 rw_wunlock(&pvh_global_lock);
2505 rw_wlock(&pvh_global_lock);
2510 * Indicate the need to retry. While waiting,
2511 * the L2 page table page may have been allocated.
2515 pmap->pm_stats.resident_count++;
2516 pt2pg_pa = pmap_pt2pg_init(pmap, va, m);
2518 pt2pg_pa = pte2_pa(pte2);
2519 m = PHYS_TO_VM_PAGE(pt2pg_pa);
2522 pt2_wirecount_inc(m, pte1_idx);
2523 pt2_pa = page_pt2pa(pt2pg_pa, pte1_idx);
2524 pte1_store(pte1p, PTE1_LINK(pt2_pa));
2530 pmap_allocpte2(pmap_t pmap, vm_offset_t va, u_int flags)
2533 pt1_entry_t *pte1p, pte1;
2536 pte1_idx = pte1_index(va);
2538 pte1p = pmap->pm_pt1 + pte1_idx;
2539 pte1 = pte1_load(pte1p);
2542 * This supports switching from a 1MB page to a
2545 if (pte1_is_section(pte1)) {
2546 (void)pmap_demote_pte1(pmap, pte1p, va);
2548 * Reload pte1 after demotion.
2550 * Note: Demotion can even fail as either PT2 is not find for
2551 * the virtual address or PT2PG can not be allocated.
2553 pte1 = pte1_load(pte1p);
2557 * If the L2 page table page is mapped, we just increment the
2558 * hold count, and activate it.
2560 if (pte1_is_link(pte1)) {
2561 m = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
2562 pt2_wirecount_inc(m, pte1_idx);
2565 * Here if the PT2 isn't mapped, or if it has
2568 m = _pmap_allocpte2(pmap, va, flags);
2569 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2577 * Schedule the specified unused L2 page table page to be freed. Specifically,
2578 * add the page to the specified list of pages that will be released to the
2579 * physical memory manager after the TLB has been updated.
2581 static __inline void
2582 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free)
2586 * Put page on a list so that it is released after
2587 * *ALL* TLB shootdown is done
2590 pmap_zero_page_check(m);
2592 m->flags |= PG_ZERO;
2593 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2597 * Unwire L2 page tables page.
2600 pmap_unwire_pt2pg(pmap_t pmap, vm_offset_t va, vm_page_t m)
2602 pt1_entry_t *pte1p, opte1 __unused;
2606 KASSERT(pt2pg_is_empty(m),
2607 ("%s: pmap %p PT2PG %p wired", __func__, pmap, m));
2610 * Unmap all L2 page tables in the page from L1 page table.
2612 * QQQ: Individual L2 page tables (except the last one) can be unmapped
2613 * earlier. However, we are doing that this way.
2615 KASSERT(m->pindex == (pte1_index(va) & ~PT2PG_MASK),
2616 ("%s: pmap %p va %#x PT2PG %p bad index", __func__, pmap, va, m));
2617 pte1p = pmap->pm_pt1 + m->pindex;
2618 for (i = 0; i < NPT2_IN_PG; i++, pte1p++) {
2619 KASSERT(m->md.pt2_wirecount[i] == 0,
2620 ("%s: pmap %p PT2 %u (PG %p) wired", __func__, pmap, i, m));
2621 opte1 = pte1_load(pte1p);
2622 if (pte1_is_link(opte1)) {
2625 * Flush intermediate TLB cache.
2627 pmap_tlb_flush(pmap, (m->pindex + i) << PTE1_SHIFT);
2631 KASSERT((opte1 == 0) || pte1_is_section(opte1),
2632 ("%s: pmap %p va %#x bad pte1 %x at %u", __func__,
2633 pmap, va, opte1, i));
2638 * Unmap the page from PT2TAB.
2640 pte2p = pmap_pt2tab_entry(pmap, va);
2641 (void)pt2tab_load_clear(pte2p);
2642 pmap_tlb_flush(pmap, pt2map_pt2pg(va));
2645 pmap->pm_stats.resident_count--;
2648 * This barrier is so that the ordinary store unmapping
2649 * the L2 page table page is globally performed before TLB shoot-
2657 * Decrements a L2 page table page's wire count, which is used to record the
2658 * number of valid page table entries within the page. If the wire count
2659 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2660 * page table page was unmapped and FALSE otherwise.
2662 static __inline boolean_t
2663 pmap_unwire_pt2(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2665 pt2_wirecount_dec(m, pte1_index(va));
2666 if (pt2pg_is_empty(m)) {
2668 * QQQ: Wire count is zero, so whole page should be zero and
2669 * we can set PG_ZERO flag to it.
2670 * Note that when promotion is enabled, it takes some
2671 * more efforts. See pmap_unwire_pt2_all() below.
2673 pmap_unwire_pt2pg(pmap, va, m);
2674 pmap_add_delayed_free_list(m, free);
2681 * Drop a L2 page table page's wire count at once, which is used to record
2682 * the number of valid L2 page table entries within the page. If the wire
2683 * count drops to zero, then the L2 page table page is unmapped.
2685 static __inline void
2686 pmap_unwire_pt2_all(pmap_t pmap, vm_offset_t va, vm_page_t m,
2687 struct spglist *free)
2689 u_int pte1_idx = pte1_index(va);
2691 KASSERT(m->pindex == (pte1_idx & ~PT2PG_MASK),
2692 ("%s: PT2 page's pindex is wrong", __func__));
2693 KASSERT(m->wire_count > pt2_wirecount_get(m, pte1_idx),
2694 ("%s: bad pt2 wire count %u > %u", __func__, m->wire_count,
2695 pt2_wirecount_get(m, pte1_idx)));
2698 * It's possible that the L2 page table was never used.
2699 * It happened in case that a section was created without promotion.
2701 if (pt2_is_full(m, va)) {
2702 pt2_wirecount_set(m, pte1_idx, 0);
2705 * QQQ: We clear L2 page table now, so when L2 page table page
2706 * is going to be freed, we can set it PG_ZERO flag ...
2707 * This function is called only on section mappings, so
2708 * hopefully it's not to big overload.
2710 * XXX: If pmap is current, existing PT2MAP mapping could be
2713 pmap_zero_page_area(m, page_pt2off(pte1_idx), NB_IN_PT2);
2717 KASSERT(pt2_is_empty(m, va), ("%s: PT2 is not empty (%u)",
2718 __func__, pt2_wirecount_get(m, pte1_idx)));
2720 if (pt2pg_is_empty(m)) {
2721 pmap_unwire_pt2pg(pmap, va, m);
2722 pmap_add_delayed_free_list(m, free);
2727 * After removing a L2 page table entry, this routine is used to
2728 * conditionally free the page, and manage the hold/wire counts.
2731 pmap_unuse_pt2(pmap_t pmap, vm_offset_t va, struct spglist *free)
2736 if (va >= VM_MAXUSER_ADDRESS)
2738 pte1 = pte1_load(pmap_pte1(pmap, va));
2739 mpte = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
2740 return (pmap_unwire_pt2(pmap, va, mpte, free));
2743 /*************************************
2745 * Page management routines.
2747 *************************************/
2749 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2750 CTASSERT(_NPCM == 11);
2751 CTASSERT(_NPCPV == 336);
2753 static __inline struct pv_chunk *
2754 pv_to_chunk(pv_entry_t pv)
2757 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2760 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2762 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2763 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2765 static const uint32_t pc_freemask[_NPCM] = {
2766 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2767 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2768 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2769 PC_FREE0_9, PC_FREE10
2772 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2773 "Current number of pv entries");
2776 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2778 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2779 "Current number of pv entry chunks");
2780 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2781 "Current number of pv entry chunks allocated");
2782 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2783 "Current number of pv entry chunks frees");
2784 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail,
2785 0, "Number of times tried to get a chunk page but failed.");
2787 static long pv_entry_frees, pv_entry_allocs;
2788 static int pv_entry_spare;
2790 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2791 "Current number of pv entry frees");
2792 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs,
2793 0, "Current number of pv entry allocs");
2794 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2795 "Current number of spare pv entries");
2799 * Is given page managed?
2801 static __inline bool
2802 is_managed(vm_paddr_t pa)
2806 m = PHYS_TO_VM_PAGE(pa);
2809 return ((m->oflags & VPO_UNMANAGED) == 0);
2812 static __inline bool
2813 pte1_is_managed(pt1_entry_t pte1)
2816 return (is_managed(pte1_pa(pte1)));
2819 static __inline bool
2820 pte2_is_managed(pt2_entry_t pte2)
2823 return (is_managed(pte2_pa(pte2)));
2827 * We are in a serious low memory condition. Resort to
2828 * drastic measures to free some pages so we can allocate
2829 * another pv entry chunk.
2832 pmap_pv_reclaim(pmap_t locked_pmap)
2835 struct pv_chunk *pc;
2836 struct md_page *pvh;
2839 pt2_entry_t *pte2p, tpte2;
2843 struct spglist free;
2845 int bit, field, freed;
2847 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2851 TAILQ_INIT(&newtail);
2852 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2853 SLIST_EMPTY(&free))) {
2854 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2855 if (pmap != pc->pc_pmap) {
2857 if (pmap != locked_pmap)
2861 /* Avoid deadlock and lock recursion. */
2862 if (pmap > locked_pmap)
2864 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2866 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2872 * Destroy every non-wired, 4 KB page mapping in the chunk.
2875 for (field = 0; field < _NPCM; field++) {
2876 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2877 inuse != 0; inuse &= ~(1UL << bit)) {
2878 bit = ffs(inuse) - 1;
2879 pv = &pc->pc_pventry[field * 32 + bit];
2881 pte1p = pmap_pte1(pmap, va);
2882 if (pte1_is_section(pte1_load(pte1p)))
2884 pte2p = pmap_pte2(pmap, va);
2885 tpte2 = pte2_load(pte2p);
2886 if ((tpte2 & PTE2_W) == 0)
2887 tpte2 = pte2_load_clear(pte2p);
2888 pmap_pte2_release(pte2p);
2889 if ((tpte2 & PTE2_W) != 0)
2892 ("pmap_pv_reclaim: pmap %p va %#x zero pte",
2894 pmap_tlb_flush(pmap, va);
2895 m = PHYS_TO_VM_PAGE(pte2_pa(tpte2));
2896 if (pte2_is_dirty(tpte2))
2898 if ((tpte2 & PTE2_A) != 0)
2899 vm_page_aflag_set(m, PGA_REFERENCED);
2900 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2901 if (TAILQ_EMPTY(&m->md.pv_list) &&
2902 (m->flags & PG_FICTITIOUS) == 0) {
2903 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2904 if (TAILQ_EMPTY(&pvh->pv_list)) {
2905 vm_page_aflag_clear(m,
2909 pc->pc_map[field] |= 1UL << bit;
2910 pmap_unuse_pt2(pmap, va, &free);
2915 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2918 /* Every freed mapping is for a 4 KB page. */
2919 pmap->pm_stats.resident_count -= freed;
2920 PV_STAT(pv_entry_frees += freed);
2921 PV_STAT(pv_entry_spare += freed);
2922 pv_entry_count -= freed;
2923 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2924 for (field = 0; field < _NPCM; field++)
2925 if (pc->pc_map[field] != pc_freemask[field]) {
2926 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2928 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2931 * One freed pv entry in locked_pmap is
2934 if (pmap == locked_pmap)
2938 if (field == _NPCM) {
2939 PV_STAT(pv_entry_spare -= _NPCPV);
2940 PV_STAT(pc_chunk_count--);
2941 PV_STAT(pc_chunk_frees++);
2942 /* Entire chunk is free; return it. */
2943 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2944 pmap_qremove((vm_offset_t)pc, 1);
2945 pmap_pte2list_free(&pv_vafree, (vm_offset_t)pc);
2950 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2952 if (pmap != locked_pmap)
2955 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2956 m_pc = SLIST_FIRST(&free);
2957 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2958 /* Recycle a freed page table page. */
2959 m_pc->wire_count = 1;
2962 vm_page_free_pages_toq(&free, false);
2967 free_pv_chunk(struct pv_chunk *pc)
2971 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2972 PV_STAT(pv_entry_spare -= _NPCPV);
2973 PV_STAT(pc_chunk_count--);
2974 PV_STAT(pc_chunk_frees++);
2975 /* entire chunk is free, return it */
2976 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2977 pmap_qremove((vm_offset_t)pc, 1);
2978 vm_page_unwire(m, PQ_NONE);
2980 pmap_pte2list_free(&pv_vafree, (vm_offset_t)pc);
2984 * Free the pv_entry back to the free list.
2987 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2989 struct pv_chunk *pc;
2990 int idx, field, bit;
2992 rw_assert(&pvh_global_lock, RA_WLOCKED);
2993 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2994 PV_STAT(pv_entry_frees++);
2995 PV_STAT(pv_entry_spare++);
2997 pc = pv_to_chunk(pv);
2998 idx = pv - &pc->pc_pventry[0];
3001 pc->pc_map[field] |= 1ul << bit;
3002 for (idx = 0; idx < _NPCM; idx++)
3003 if (pc->pc_map[idx] != pc_freemask[idx]) {
3005 * 98% of the time, pc is already at the head of the
3006 * list. If it isn't already, move it to the head.
3008 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
3010 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3011 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
3016 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3021 * Get a new pv_entry, allocating a block from the system
3025 get_pv_entry(pmap_t pmap, boolean_t try)
3027 static const struct timeval printinterval = { 60, 0 };
3028 static struct timeval lastprint;
3031 struct pv_chunk *pc;
3034 rw_assert(&pvh_global_lock, RA_WLOCKED);
3035 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3036 PV_STAT(pv_entry_allocs++);
3038 if (pv_entry_count > pv_entry_high_water)
3039 if (ratecheck(&lastprint, &printinterval))
3040 printf("Approaching the limit on PV entries, consider "
3041 "increasing either the vm.pmap.shpgperproc or the "
3042 "vm.pmap.pv_entry_max tunable.\n");
3044 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3046 for (field = 0; field < _NPCM; field++) {
3047 if (pc->pc_map[field]) {
3048 bit = ffs(pc->pc_map[field]) - 1;
3052 if (field < _NPCM) {
3053 pv = &pc->pc_pventry[field * 32 + bit];
3054 pc->pc_map[field] &= ~(1ul << bit);
3055 /* If this was the last item, move it to tail */
3056 for (field = 0; field < _NPCM; field++)
3057 if (pc->pc_map[field] != 0) {
3058 PV_STAT(pv_entry_spare--);
3059 return (pv); /* not full, return */
3061 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3062 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3063 PV_STAT(pv_entry_spare--);
3068 * Access to the pte2list "pv_vafree" is synchronized by the pvh
3069 * global lock. If "pv_vafree" is currently non-empty, it will
3070 * remain non-empty until pmap_pte2list_alloc() completes.
3072 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3073 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
3076 PV_STAT(pc_chunk_tryfail++);
3079 m = pmap_pv_reclaim(pmap);
3083 PV_STAT(pc_chunk_count++);
3084 PV_STAT(pc_chunk_allocs++);
3085 pc = (struct pv_chunk *)pmap_pte2list_alloc(&pv_vafree);
3086 pmap_qenter((vm_offset_t)pc, &m, 1);
3088 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
3089 for (field = 1; field < _NPCM; field++)
3090 pc->pc_map[field] = pc_freemask[field];
3091 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
3092 pv = &pc->pc_pventry[0];
3093 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3094 PV_STAT(pv_entry_spare += _NPCPV - 1);
3099 * Create a pv entry for page at pa for
3103 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
3107 rw_assert(&pvh_global_lock, RA_WLOCKED);
3108 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3109 pv = get_pv_entry(pmap, FALSE);
3111 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3114 static __inline pv_entry_t
3115 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3119 rw_assert(&pvh_global_lock, RA_WLOCKED);
3120 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3121 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3122 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3130 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3134 pv = pmap_pvh_remove(pvh, pmap, va);
3135 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3136 free_pv_entry(pmap, pv);
3140 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
3142 struct md_page *pvh;
3144 rw_assert(&pvh_global_lock, RA_WLOCKED);
3145 pmap_pvh_free(&m->md, pmap, va);
3146 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
3147 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3148 if (TAILQ_EMPTY(&pvh->pv_list))
3149 vm_page_aflag_clear(m, PGA_WRITEABLE);
3154 pmap_pv_demote_pte1(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3156 struct md_page *pvh;
3158 vm_offset_t va_last;
3161 rw_assert(&pvh_global_lock, RA_WLOCKED);
3162 KASSERT((pa & PTE1_OFFSET) == 0,
3163 ("pmap_pv_demote_pte1: pa is not 1mpage aligned"));
3166 * Transfer the 1mpage's pv entry for this mapping to the first
3169 pvh = pa_to_pvh(pa);
3170 va = pte1_trunc(va);
3171 pv = pmap_pvh_remove(pvh, pmap, va);
3172 KASSERT(pv != NULL, ("pmap_pv_demote_pte1: pv not found"));
3173 m = PHYS_TO_VM_PAGE(pa);
3174 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3175 /* Instantiate the remaining NPTE2_IN_PT2 - 1 pv entries. */
3176 va_last = va + PTE1_SIZE - PAGE_SIZE;
3179 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3180 ("pmap_pv_demote_pte1: page %p is not managed", m));
3182 pmap_insert_entry(pmap, va, m);
3183 } while (va < va_last);
3186 #if VM_NRESERVLEVEL > 0
3188 pmap_pv_promote_pte1(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3190 struct md_page *pvh;
3192 vm_offset_t va_last;
3195 rw_assert(&pvh_global_lock, RA_WLOCKED);
3196 KASSERT((pa & PTE1_OFFSET) == 0,
3197 ("pmap_pv_promote_pte1: pa is not 1mpage aligned"));
3200 * Transfer the first page's pv entry for this mapping to the
3201 * 1mpage's pv list. Aside from avoiding the cost of a call
3202 * to get_pv_entry(), a transfer avoids the possibility that
3203 * get_pv_entry() calls pmap_pv_reclaim() and that pmap_pv_reclaim()
3204 * removes one of the mappings that is being promoted.
3206 m = PHYS_TO_VM_PAGE(pa);
3207 va = pte1_trunc(va);
3208 pv = pmap_pvh_remove(&m->md, pmap, va);
3209 KASSERT(pv != NULL, ("pmap_pv_promote_pte1: pv not found"));
3210 pvh = pa_to_pvh(pa);
3211 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3212 /* Free the remaining NPTE2_IN_PT2 - 1 pv entries. */
3213 va_last = va + PTE1_SIZE - PAGE_SIZE;
3217 pmap_pvh_free(&m->md, pmap, va);
3218 } while (va < va_last);
3223 * Conditionally create a pv entry.
3226 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
3230 rw_assert(&pvh_global_lock, RA_WLOCKED);
3231 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3232 if (pv_entry_count < pv_entry_high_water &&
3233 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
3235 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3242 * Create the pv entries for each of the pages within a section.
3245 pmap_pv_insert_pte1(pmap_t pmap, vm_offset_t va, pt1_entry_t pte1, u_int flags)
3247 struct md_page *pvh;
3251 rw_assert(&pvh_global_lock, RA_WLOCKED);
3252 noreclaim = (flags & PMAP_ENTER_NORECLAIM) != 0;
3253 if ((noreclaim && pv_entry_count >= pv_entry_high_water) ||
3254 (pv = get_pv_entry(pmap, noreclaim)) == NULL)
3257 pvh = pa_to_pvh(pte1_pa(pte1));
3258 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3263 pmap_tlb_flush_pte1(pmap_t pmap, vm_offset_t va, pt1_entry_t npte1)
3266 /* Kill all the small mappings or the big one only. */
3267 if (pte1_is_section(npte1))
3268 pmap_tlb_flush_range(pmap, pte1_trunc(va), PTE1_SIZE);
3270 pmap_tlb_flush(pmap, pte1_trunc(va));
3274 * Update kernel pte1 on all pmaps.
3276 * The following function is called only on one cpu with disabled interrupts.
3277 * In SMP case, smp_rendezvous_cpus() is used to stop other cpus. This way
3278 * nobody can invoke explicit hardware table walk during the update of pte1.
3279 * Unsolicited hardware table walk can still happen, invoked by speculative
3280 * data or instruction prefetch or even by speculative hardware table walk.
3282 * The break-before-make approach should be implemented here. However, it's
3283 * not so easy to do that for kernel mappings as it would be unhappy to unmap
3284 * itself unexpectedly but voluntarily.
3287 pmap_update_pte1_kernel(vm_offset_t va, pt1_entry_t npte1)
3293 * Get current pmap. Interrupts should be disabled here
3294 * so PCPU_GET() is done atomically.
3296 pmap = PCPU_GET(curpmap);
3301 * (1) Change pte1 on current pmap.
3302 * (2) Flush all obsolete TLB entries on current CPU.
3303 * (3) Change pte1 on all pmaps.
3304 * (4) Flush all obsolete TLB entries on all CPUs in SMP case.
3307 pte1p = pmap_pte1(pmap, va);
3308 pte1_store(pte1p, npte1);
3310 /* Kill all the small mappings or the big one only. */
3311 if (pte1_is_section(npte1)) {
3312 pmap_pte1_kern_promotions++;
3313 tlb_flush_range_local(pte1_trunc(va), PTE1_SIZE);
3315 pmap_pte1_kern_demotions++;
3316 tlb_flush_local(pte1_trunc(va));
3320 * In SMP case, this function is called when all cpus are at smp
3321 * rendezvous, so there is no need to use 'allpmaps_lock' lock here.
3322 * In UP case, the function is called with this lock locked.
3324 LIST_FOREACH(pmap, &allpmaps, pm_list) {
3325 pte1p = pmap_pte1(pmap, va);
3326 pte1_store(pte1p, npte1);
3330 /* Kill all the small mappings or the big one only. */
3331 if (pte1_is_section(npte1))
3332 tlb_flush_range(pte1_trunc(va), PTE1_SIZE);
3334 tlb_flush(pte1_trunc(va));
3339 struct pte1_action {
3342 u_int update; /* CPU that updates the PTE1 */
3346 pmap_update_pte1_action(void *arg)
3348 struct pte1_action *act = arg;
3350 if (act->update == PCPU_GET(cpuid))
3351 pmap_update_pte1_kernel(act->va, act->npte1);
3355 * Change pte1 on current pmap.
3356 * Note that kernel pte1 must be changed on all pmaps.
3358 * According to the architecture reference manual published by ARM,
3359 * the behaviour is UNPREDICTABLE when two or more TLB entries map the same VA.
3360 * According to this manual, UNPREDICTABLE behaviours must never happen in
3361 * a viable system. In contrast, on x86 processors, it is not specified which
3362 * TLB entry mapping the virtual address will be used, but the MMU doesn't
3363 * generate a bogus translation the way it does on Cortex-A8 rev 2 (Beaglebone
3366 * It's a problem when either promotion or demotion is being done. The pte1
3367 * update and appropriate TLB flush must be done atomically in general.
3370 pmap_change_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va,
3374 if (pmap == kernel_pmap) {
3375 struct pte1_action act;
3380 act.update = PCPU_GET(cpuid);
3381 smp_rendezvous_cpus(all_cpus, smp_no_rendezvous_barrier,
3382 pmap_update_pte1_action, NULL, &act);
3388 * Use break-before-make approach for changing userland
3389 * mappings. It can cause L1 translation aborts on other
3390 * cores in SMP case. So, special treatment is implemented
3391 * in pmap_fault(). To reduce the likelihood that another core
3392 * will be affected by the broken mapping, disable interrupts
3393 * until the mapping change is completed.
3395 cspr = disable_interrupts(PSR_I | PSR_F);
3397 pmap_tlb_flush_pte1(pmap, va, npte1);
3398 pte1_store(pte1p, npte1);
3399 restore_interrupts(cspr);
3404 pmap_change_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va,
3408 if (pmap == kernel_pmap) {
3409 mtx_lock_spin(&allpmaps_lock);
3410 pmap_update_pte1_kernel(va, npte1);
3411 mtx_unlock_spin(&allpmaps_lock);
3416 * Use break-before-make approach for changing userland
3417 * mappings. It's absolutely safe in UP case when interrupts
3420 cspr = disable_interrupts(PSR_I | PSR_F);
3422 pmap_tlb_flush_pte1(pmap, va, npte1);
3423 pte1_store(pte1p, npte1);
3424 restore_interrupts(cspr);
3429 #if VM_NRESERVLEVEL > 0
3431 * Tries to promote the NPTE2_IN_PT2, contiguous 4KB page mappings that are
3432 * within a single page table page (PT2) to a single 1MB page mapping.
3433 * For promotion to occur, two conditions must be met: (1) the 4KB page
3434 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3435 * mappings must have identical characteristics.
3437 * Managed (PG_MANAGED) mappings within the kernel address space are not
3438 * promoted. The reason is that kernel PTE1s are replicated in each pmap but
3439 * pmap_remove_write(), pmap_clear_modify(), and pmap_clear_reference() only
3440 * read the PTE1 from the kernel pmap.
3443 pmap_promote_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3446 pt2_entry_t *fpte2p, fpte2, fpte2_fav;
3447 pt2_entry_t *pte2p, pte2;
3448 vm_offset_t pteva __unused;
3449 vm_page_t m __unused;
3451 PDEBUG(6, printf("%s(%p): try for va %#x pte1 %#x at %p\n", __func__,
3452 pmap, va, pte1_load(pte1p), pte1p));
3454 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3457 * Examine the first PTE2 in the specified PT2. Abort if this PTE2 is
3458 * either invalid, unused, or does not map the first 4KB physical page
3459 * within a 1MB page.
3461 fpte2p = pmap_pte2_quick(pmap, pte1_trunc(va));
3462 fpte2 = pte2_load(fpte2p);
3463 if ((fpte2 & ((PTE2_FRAME & PTE1_OFFSET) | PTE2_A | PTE2_V)) !=
3464 (PTE2_A | PTE2_V)) {
3465 pmap_pte1_p_failures++;
3466 CTR3(KTR_PMAP, "%s: failure(1) for va %#x in pmap %p",
3467 __func__, va, pmap);
3470 if (pte2_is_managed(fpte2) && pmap == kernel_pmap) {
3471 pmap_pte1_p_failures++;
3472 CTR3(KTR_PMAP, "%s: failure(2) for va %#x in pmap %p",
3473 __func__, va, pmap);
3476 if ((fpte2 & (PTE2_NM | PTE2_RO)) == PTE2_NM) {
3478 * When page is not modified, PTE2_RO can be set without
3479 * a TLB invalidation.
3482 pte2_store(fpte2p, fpte2);
3486 * Examine each of the other PTE2s in the specified PT2. Abort if this
3487 * PTE2 maps an unexpected 4KB physical page or does not have identical
3488 * characteristics to the first PTE2.
3490 fpte2_fav = (fpte2 & (PTE2_FRAME | PTE2_A | PTE2_V));
3491 fpte2_fav += PTE1_SIZE - PTE2_SIZE; /* examine from the end */
3492 for (pte2p = fpte2p + NPTE2_IN_PT2 - 1; pte2p > fpte2p; pte2p--) {
3493 pte2 = pte2_load(pte2p);
3494 if ((pte2 & (PTE2_FRAME | PTE2_A | PTE2_V)) != fpte2_fav) {
3495 pmap_pte1_p_failures++;
3496 CTR3(KTR_PMAP, "%s: failure(3) for va %#x in pmap %p",
3497 __func__, va, pmap);
3500 if ((pte2 & (PTE2_NM | PTE2_RO)) == PTE2_NM) {
3502 * When page is not modified, PTE2_RO can be set
3503 * without a TLB invalidation. See note above.
3506 pte2_store(pte2p, pte2);
3507 pteva = pte1_trunc(va) | (pte2 & PTE1_OFFSET &
3509 CTR3(KTR_PMAP, "%s: protect for va %#x in pmap %p",
3510 __func__, pteva, pmap);
3512 if ((pte2 & PTE2_PROMOTE) != (fpte2 & PTE2_PROMOTE)) {
3513 pmap_pte1_p_failures++;
3514 CTR3(KTR_PMAP, "%s: failure(4) for va %#x in pmap %p",
3515 __func__, va, pmap);
3519 fpte2_fav -= PTE2_SIZE;
3522 * The page table page in its current state will stay in PT2TAB
3523 * until the PTE1 mapping the section is demoted by pmap_demote_pte1()
3524 * or destroyed by pmap_remove_pte1().
3526 * Note that L2 page table size is not equal to PAGE_SIZE.
3528 m = PHYS_TO_VM_PAGE(trunc_page(pte1_link_pa(pte1_load(pte1p))));
3529 KASSERT(m >= vm_page_array && m < &vm_page_array[vm_page_array_size],
3530 ("%s: PT2 page is out of range", __func__));
3531 KASSERT(m->pindex == (pte1_index(va) & ~PT2PG_MASK),
3532 ("%s: PT2 page's pindex is wrong", __func__));
3535 * Get pte1 from pte2 format.
3537 npte1 = (fpte2 & PTE1_FRAME) | ATTR_TO_L1(fpte2) | PTE1_V;
3540 * Promote the pv entries.
3542 if (pte2_is_managed(fpte2))
3543 pmap_pv_promote_pte1(pmap, va, pte1_pa(npte1));
3546 * Promote the mappings.
3548 pmap_change_pte1(pmap, pte1p, va, npte1);
3550 pmap_pte1_promotions++;
3551 CTR3(KTR_PMAP, "%s: success for va %#x in pmap %p",
3552 __func__, va, pmap);
3554 PDEBUG(6, printf("%s(%p): success for va %#x pte1 %#x(%#x) at %p\n",
3555 __func__, pmap, va, npte1, pte1_load(pte1p), pte1p));
3557 #endif /* VM_NRESERVLEVEL > 0 */
3560 * Zero L2 page table page.
3562 static __inline void
3563 pmap_clear_pt2(pt2_entry_t *fpte2p)
3567 for (pte2p = fpte2p; pte2p < fpte2p + NPTE2_IN_PT2; pte2p++)
3573 * Removes a 1MB page mapping from the kernel pmap.
3576 pmap_remove_kernel_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3580 pt2_entry_t *fpte2p;
3583 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3584 m = pmap_pt2_page(pmap, va);
3587 * QQQ: Is this function called only on promoted pte1?
3588 * We certainly do section mappings directly
3589 * (without promotion) in kernel !!!
3591 panic("%s: missing pt2 page", __func__);
3593 pte1_idx = pte1_index(va);
3596 * Initialize the L2 page table.
3598 fpte2p = page_pt2(pt2map_pt2pg(va), pte1_idx);
3599 pmap_clear_pt2(fpte2p);
3602 * Remove the mapping.
3604 pt2_pa = page_pt2pa(VM_PAGE_TO_PHYS(m), pte1_idx);
3605 pmap_kenter_pte1(va, PTE1_LINK(pt2_pa));
3608 * QQQ: We do not need to invalidate PT2MAP mapping
3609 * as we did not change it. I.e. the L2 page table page
3610 * was and still is mapped the same way.
3615 * Do the things to unmap a section in a process
3618 pmap_remove_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t sva,
3619 struct spglist *free)
3622 struct md_page *pvh;
3623 vm_offset_t eva, va;
3626 PDEBUG(6, printf("%s(%p): va %#x pte1 %#x at %p\n", __func__, pmap, sva,
3627 pte1_load(pte1p), pte1p));
3629 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3630 KASSERT((sva & PTE1_OFFSET) == 0,
3631 ("%s: sva is not 1mpage aligned", __func__));
3634 * Clear and invalidate the mapping. It should occupy one and only TLB
3635 * entry. So, pmap_tlb_flush() called with aligned address should be
3638 opte1 = pte1_load_clear(pte1p);
3639 pmap_tlb_flush(pmap, sva);
3641 if (pte1_is_wired(opte1))
3642 pmap->pm_stats.wired_count -= PTE1_SIZE / PAGE_SIZE;
3643 pmap->pm_stats.resident_count -= PTE1_SIZE / PAGE_SIZE;
3644 if (pte1_is_managed(opte1)) {
3645 pvh = pa_to_pvh(pte1_pa(opte1));
3646 pmap_pvh_free(pvh, pmap, sva);
3647 eva = sva + PTE1_SIZE;
3648 for (va = sva, m = PHYS_TO_VM_PAGE(pte1_pa(opte1));
3649 va < eva; va += PAGE_SIZE, m++) {
3650 if (pte1_is_dirty(opte1))
3653 vm_page_aflag_set(m, PGA_REFERENCED);
3654 if (TAILQ_EMPTY(&m->md.pv_list) &&
3655 TAILQ_EMPTY(&pvh->pv_list))
3656 vm_page_aflag_clear(m, PGA_WRITEABLE);
3659 if (pmap == kernel_pmap) {
3661 * L2 page table(s) can't be removed from kernel map as
3662 * kernel counts on it (stuff around pmap_growkernel()).
3664 pmap_remove_kernel_pte1(pmap, pte1p, sva);
3667 * Get associated L2 page table page.
3668 * It's possible that the page was never allocated.
3670 m = pmap_pt2_page(pmap, sva);
3672 pmap_unwire_pt2_all(pmap, sva, m, free);
3677 * Fills L2 page table page with mappings to consecutive physical pages.
3679 static __inline void
3680 pmap_fill_pt2(pt2_entry_t *fpte2p, pt2_entry_t npte2)
3684 for (pte2p = fpte2p; pte2p < fpte2p + NPTE2_IN_PT2; pte2p++) {
3685 pte2_store(pte2p, npte2);
3691 * Tries to demote a 1MB page mapping. If demotion fails, the
3692 * 1MB page mapping is invalidated.
3695 pmap_demote_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3697 pt1_entry_t opte1, npte1;
3698 pt2_entry_t *fpte2p, npte2;
3699 vm_paddr_t pt2pg_pa, pt2_pa;
3701 struct spglist free;
3702 uint32_t pte1_idx, isnew = 0;
3704 PDEBUG(6, printf("%s(%p): try for va %#x pte1 %#x at %p\n", __func__,
3705 pmap, va, pte1_load(pte1p), pte1p));
3707 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3709 opte1 = pte1_load(pte1p);
3710 KASSERT(pte1_is_section(opte1), ("%s: opte1 not a section", __func__));
3712 if ((opte1 & PTE1_A) == 0 || (m = pmap_pt2_page(pmap, va)) == NULL) {
3713 KASSERT(!pte1_is_wired(opte1),
3714 ("%s: PT2 page for a wired mapping is missing", __func__));
3717 * Invalidate the 1MB page mapping and return
3718 * "failure" if the mapping was never accessed or the
3719 * allocation of the new page table page fails.
3721 if ((opte1 & PTE1_A) == 0 || (m = vm_page_alloc(NULL,
3722 pte1_index(va) & ~PT2PG_MASK, VM_ALLOC_NOOBJ |
3723 VM_ALLOC_NORMAL | VM_ALLOC_WIRED)) == NULL) {
3725 pmap_remove_pte1(pmap, pte1p, pte1_trunc(va), &free);
3726 vm_page_free_pages_toq(&free, false);
3727 CTR3(KTR_PMAP, "%s: failure for va %#x in pmap %p",
3728 __func__, va, pmap);
3731 if (va < VM_MAXUSER_ADDRESS)
3732 pmap->pm_stats.resident_count++;
3737 * We init all L2 page tables in the page even if
3738 * we are going to change everything for one L2 page
3741 pt2pg_pa = pmap_pt2pg_init(pmap, va, m);
3743 if (va < VM_MAXUSER_ADDRESS) {
3744 if (pt2_is_empty(m, va))
3745 isnew = 1; /* Demoting section w/o promotion. */
3748 KASSERT(pt2_is_full(m, va), ("%s: bad PT2 wire"
3749 " count %u", __func__,
3750 pt2_wirecount_get(m, pte1_index(va))));
3755 pt2pg_pa = VM_PAGE_TO_PHYS(m);
3756 pte1_idx = pte1_index(va);
3758 * If the pmap is current, then the PT2MAP can provide access to
3759 * the page table page (promoted L2 page tables are not unmapped).
3760 * Otherwise, temporarily map the L2 page table page (m) into
3761 * the kernel's address space at either PADDR1 or PADDR2.
3763 * Note that L2 page table size is not equal to PAGE_SIZE.
3765 if (pmap_is_current(pmap))
3766 fpte2p = page_pt2(pt2map_pt2pg(va), pte1_idx);
3767 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
3768 if (pte2_pa(pte2_load(PMAP1)) != pt2pg_pa) {
3769 pte2_store(PMAP1, PTE2_KPT(pt2pg_pa));
3771 PMAP1cpu = PCPU_GET(cpuid);
3773 tlb_flush_local((vm_offset_t)PADDR1);
3777 if (PMAP1cpu != PCPU_GET(cpuid)) {
3778 PMAP1cpu = PCPU_GET(cpuid);
3779 tlb_flush_local((vm_offset_t)PADDR1);
3784 fpte2p = page_pt2((vm_offset_t)PADDR1, pte1_idx);
3786 mtx_lock(&PMAP2mutex);
3787 if (pte2_pa(pte2_load(PMAP2)) != pt2pg_pa) {
3788 pte2_store(PMAP2, PTE2_KPT(pt2pg_pa));
3789 tlb_flush((vm_offset_t)PADDR2);
3791 fpte2p = page_pt2((vm_offset_t)PADDR2, pte1_idx);
3793 pt2_pa = page_pt2pa(pt2pg_pa, pte1_idx);
3794 npte1 = PTE1_LINK(pt2_pa);
3796 KASSERT((opte1 & PTE1_A) != 0,
3797 ("%s: opte1 is missing PTE1_A", __func__));
3798 KASSERT((opte1 & (PTE1_NM | PTE1_RO)) != PTE1_NM,
3799 ("%s: opte1 has PTE1_NM", __func__));
3802 * Get pte2 from pte1 format.
3804 npte2 = pte1_pa(opte1) | ATTR_TO_L2(opte1) | PTE2_V;
3807 * If the L2 page table page is new, initialize it. If the mapping
3808 * has changed attributes, update the page table entries.
3811 pt2_wirecount_set(m, pte1_idx, NPTE2_IN_PT2);
3812 pmap_fill_pt2(fpte2p, npte2);
3813 } else if ((pte2_load(fpte2p) & PTE2_PROMOTE) !=
3814 (npte2 & PTE2_PROMOTE))
3815 pmap_fill_pt2(fpte2p, npte2);
3817 KASSERT(pte2_pa(pte2_load(fpte2p)) == pte2_pa(npte2),
3818 ("%s: fpte2p and npte2 map different physical addresses",
3821 if (fpte2p == PADDR2)
3822 mtx_unlock(&PMAP2mutex);
3825 * Demote the mapping. This pmap is locked. The old PTE1 has
3826 * PTE1_A set. If the old PTE1 has not PTE1_RO set, it also
3827 * has not PTE1_NM set. Thus, there is no danger of a race with
3828 * another processor changing the setting of PTE1_A and/or PTE1_NM
3829 * between the read above and the store below.
3831 pmap_change_pte1(pmap, pte1p, va, npte1);
3834 * Demote the pv entry. This depends on the earlier demotion
3835 * of the mapping. Specifically, the (re)creation of a per-
3836 * page pv entry might trigger the execution of pmap_pv_reclaim(),
3837 * which might reclaim a newly (re)created per-page pv entry
3838 * and destroy the associated mapping. In order to destroy
3839 * the mapping, the PTE1 must have already changed from mapping
3840 * the 1mpage to referencing the page table page.
3842 if (pte1_is_managed(opte1))
3843 pmap_pv_demote_pte1(pmap, va, pte1_pa(opte1));
3845 pmap_pte1_demotions++;
3846 CTR3(KTR_PMAP, "%s: success for va %#x in pmap %p",
3847 __func__, va, pmap);
3849 PDEBUG(6, printf("%s(%p): success for va %#x pte1 %#x(%#x) at %p\n",
3850 __func__, pmap, va, npte1, pte1_load(pte1p), pte1p));
3855 * Insert the given physical page (p) at
3856 * the specified virtual address (v) in the
3857 * target physical map with the protection requested.
3859 * If specified, the page will be wired down, meaning
3860 * that the related pte can not be reclaimed.
3862 * NB: This is the only routine which MAY NOT lazy-evaluate
3863 * or lose information. That is, this routine must actually
3864 * insert this page into the given map NOW.
3867 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3868 u_int flags, int8_t psind)
3872 pt2_entry_t npte2, opte2;
3875 vm_page_t mpte2, om;
3878 va = trunc_page(va);
3879 KASSERT(va <= vm_max_kernel_address, ("%s: toobig", __func__));
3880 KASSERT(va < UPT2V_MIN_ADDRESS || va >= UPT2V_MAX_ADDRESS,
3881 ("%s: invalid to pmap_enter page table pages (va: 0x%x)", __func__,
3883 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
3884 va >= kmi.clean_eva,
3885 ("%s: managed mapping within the clean submap", __func__));
3886 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3887 VM_OBJECT_ASSERT_LOCKED(m->object);
3888 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
3889 ("%s: flags %u has reserved bits set", __func__, flags));
3890 pa = VM_PAGE_TO_PHYS(m);
3891 npte2 = PTE2(pa, PTE2_A, vm_page_pte2_attr(m));
3892 if ((flags & VM_PROT_WRITE) == 0)
3894 if ((prot & VM_PROT_WRITE) == 0)
3896 KASSERT((npte2 & (PTE2_NM | PTE2_RO)) != PTE2_RO,
3897 ("%s: flags includes VM_PROT_WRITE but prot doesn't", __func__));
3898 if ((prot & VM_PROT_EXECUTE) == 0)
3900 if ((flags & PMAP_ENTER_WIRED) != 0)
3902 if (va < VM_MAXUSER_ADDRESS)
3904 if (pmap != kernel_pmap)
3907 rw_wlock(&pvh_global_lock);
3911 /* Assert the required virtual and physical alignment. */
3912 KASSERT((va & PTE1_OFFSET) == 0,
3913 ("%s: va unaligned", __func__));
3914 KASSERT(m->psind > 0, ("%s: m->psind < psind", __func__));
3915 rv = pmap_enter_pte1(pmap, va, PTE1_PA(pa) | ATTR_TO_L1(npte2) |
3921 * In the case that a page table page is not
3922 * resident, we are creating it here.
3924 if (va < VM_MAXUSER_ADDRESS) {
3925 mpte2 = pmap_allocpte2(pmap, va, flags);
3926 if (mpte2 == NULL) {
3927 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3928 ("pmap_allocpte2 failed with sleep allowed"));
3929 rv = KERN_RESOURCE_SHORTAGE;
3934 pte1p = pmap_pte1(pmap, va);
3935 if (pte1_is_section(pte1_load(pte1p)))
3936 panic("%s: attempted on 1MB page", __func__);
3937 pte2p = pmap_pte2_quick(pmap, va);
3939 panic("%s: invalid L1 page table entry va=%#x", __func__, va);
3942 opte2 = pte2_load(pte2p);
3943 opa = pte2_pa(opte2);
3945 * Mapping has not changed, must be protection or wiring change.
3947 if (pte2_is_valid(opte2) && (opa == pa)) {
3949 * Wiring change, just update stats. We don't worry about
3950 * wiring PT2 pages as they remain resident as long as there
3951 * are valid mappings in them. Hence, if a user page is wired,
3952 * the PT2 page will be also.
3954 if (pte2_is_wired(npte2) && !pte2_is_wired(opte2))
3955 pmap->pm_stats.wired_count++;
3956 else if (!pte2_is_wired(npte2) && pte2_is_wired(opte2))
3957 pmap->pm_stats.wired_count--;
3960 * Remove extra pte2 reference
3963 pt2_wirecount_dec(mpte2, pte1_index(va));
3964 if ((m->oflags & VPO_UNMANAGED) == 0)
3970 * QQQ: We think that changing physical address on writeable mapping
3971 * is not safe. Well, maybe on kernel address space with correct
3972 * locking, it can make a sense. However, we have no idea why
3973 * anyone should do that on user address space. Are we wrong?
3975 KASSERT((opa == 0) || (opa == pa) ||
3976 !pte2_is_valid(opte2) || ((opte2 & PTE2_RO) != 0),
3977 ("%s: pmap %p va %#x(%#x) opa %#x pa %#x - gotcha %#x %#x!",
3978 __func__, pmap, va, opte2, opa, pa, flags, prot));
3983 * Mapping has changed, invalidate old range and fall through to
3984 * handle validating new mapping.
3987 if (pte2_is_wired(opte2))
3988 pmap->pm_stats.wired_count--;
3989 om = PHYS_TO_VM_PAGE(opa);
3990 if (om != NULL && (om->oflags & VPO_UNMANAGED) != 0)
3993 pv = pmap_pvh_remove(&om->md, pmap, va);
3996 * Remove extra pte2 reference
3999 pt2_wirecount_dec(mpte2, va >> PTE1_SHIFT);
4001 pmap->pm_stats.resident_count++;
4004 * Enter on the PV list if part of our managed memory.
4006 if ((m->oflags & VPO_UNMANAGED) == 0) {
4008 pv = get_pv_entry(pmap, FALSE);
4011 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4012 } else if (pv != NULL)
4013 free_pv_entry(pmap, pv);
4016 * Increment counters
4018 if (pte2_is_wired(npte2))
4019 pmap->pm_stats.wired_count++;
4023 * Now validate mapping with desired protection/wiring.
4025 if (prot & VM_PROT_WRITE) {
4026 if ((m->oflags & VPO_UNMANAGED) == 0)
4027 vm_page_aflag_set(m, PGA_WRITEABLE);
4031 * If the mapping or permission bits are different, we need
4032 * to update the pte2.
4034 * QQQ: Think again and again what to do
4035 * if the mapping is going to be changed!
4037 if ((opte2 & ~(PTE2_NM | PTE2_A)) != (npte2 & ~(PTE2_NM | PTE2_A))) {
4039 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4040 * is set. Do it now, before the mapping is stored and made
4041 * valid for hardware table walk. If done later, there is a race
4042 * for other threads of current process in lazy loading case.
4043 * Don't do it for kernel memory which is mapped with exec
4044 * permission even if the memory isn't going to hold executable
4045 * code. The only time when icache sync is needed is after
4046 * kernel module is loaded and the relocation info is processed.
4047 * And it's done in elf_cpu_load_file().
4049 * QQQ: (1) Does it exist any better way where
4050 * or how to sync icache?
4051 * (2) Now, we do it on a page basis.
4053 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
4054 m->md.pat_mode == VM_MEMATTR_WB_WA &&
4055 (opa != pa || (opte2 & PTE2_NX)))
4056 cache_icache_sync_fresh(va, pa, PAGE_SIZE);
4058 if (opte2 & PTE2_V) {
4059 /* Change mapping with break-before-make approach. */
4060 opte2 = pte2_load_clear(pte2p);
4061 pmap_tlb_flush(pmap, va);
4062 pte2_store(pte2p, npte2);
4064 KASSERT((om->oflags & VPO_UNMANAGED) == 0,
4065 ("%s: om %p unmanaged", __func__, om));
4066 if ((opte2 & PTE2_A) != 0)
4067 vm_page_aflag_set(om, PGA_REFERENCED);
4068 if (pte2_is_dirty(opte2))
4070 if (TAILQ_EMPTY(&om->md.pv_list) &&
4071 ((om->flags & PG_FICTITIOUS) != 0 ||
4072 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
4073 vm_page_aflag_clear(om, PGA_WRITEABLE);
4076 pte2_store(pte2p, npte2);
4081 * QQQ: In time when both access and not mofified bits are
4082 * emulated by software, this should not happen. Some
4083 * analysis is need, if this really happen. Missing
4084 * tlb flush somewhere could be the reason.
4086 panic("%s: pmap %p va %#x opte2 %x npte2 %x !!", __func__, pmap,
4091 #if VM_NRESERVLEVEL > 0
4093 * If both the L2 page table page and the reservation are fully
4094 * populated, then attempt promotion.
4096 if ((mpte2 == NULL || pt2_is_full(mpte2, va)) &&
4097 sp_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
4098 vm_reserv_level_iffullpop(m) == 0)
4099 pmap_promote_pte1(pmap, pte1p, va);
4105 rw_wunlock(&pvh_global_lock);
4111 * Do the things to unmap a page in a process.
4114 pmap_remove_pte2(pmap_t pmap, pt2_entry_t *pte2p, vm_offset_t va,
4115 struct spglist *free)
4120 rw_assert(&pvh_global_lock, RA_WLOCKED);
4121 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4123 /* Clear and invalidate the mapping. */
4124 opte2 = pte2_load_clear(pte2p);
4125 pmap_tlb_flush(pmap, va);
4127 KASSERT(pte2_is_valid(opte2), ("%s: pmap %p va %#x not link pte2 %#x",
4128 __func__, pmap, va, opte2));
4131 pmap->pm_stats.wired_count -= 1;
4132 pmap->pm_stats.resident_count -= 1;
4133 if (pte2_is_managed(opte2)) {
4134 m = PHYS_TO_VM_PAGE(pte2_pa(opte2));
4135 if (pte2_is_dirty(opte2))
4138 vm_page_aflag_set(m, PGA_REFERENCED);
4139 pmap_remove_entry(pmap, m, va);
4141 return (pmap_unuse_pt2(pmap, va, free));
4145 * Remove a single page from a process address space.
4148 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
4152 rw_assert(&pvh_global_lock, RA_WLOCKED);
4153 KASSERT(curthread->td_pinned > 0,
4154 ("%s: curthread not pinned", __func__));
4155 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4156 if ((pte2p = pmap_pte2_quick(pmap, va)) == NULL ||
4157 !pte2_is_valid(pte2_load(pte2p)))
4159 pmap_remove_pte2(pmap, pte2p, va, free);
4163 * Remove the given range of addresses from the specified map.
4165 * It is assumed that the start and end are properly
4166 * rounded to the page size.
4169 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4172 pt1_entry_t *pte1p, pte1;
4173 pt2_entry_t *pte2p, pte2;
4174 struct spglist free;
4177 * Perform an unsynchronized read. This is, however, safe.
4179 if (pmap->pm_stats.resident_count == 0)
4184 rw_wlock(&pvh_global_lock);
4189 * Special handling of removing one page. A very common
4190 * operation and easy to short circuit some code.
4192 if (sva + PAGE_SIZE == eva) {
4193 pte1 = pte1_load(pmap_pte1(pmap, sva));
4194 if (pte1_is_link(pte1)) {
4195 pmap_remove_page(pmap, sva, &free);
4200 for (; sva < eva; sva = nextva) {
4202 * Calculate address for next L2 page table.
4204 nextva = pte1_trunc(sva + PTE1_SIZE);
4207 if (pmap->pm_stats.resident_count == 0)
4210 pte1p = pmap_pte1(pmap, sva);
4211 pte1 = pte1_load(pte1p);
4214 * Weed out invalid mappings. Note: we assume that the L1 page
4215 * table is always allocated, and in kernel virtual.
4220 if (pte1_is_section(pte1)) {
4222 * Are we removing the entire large page? If not,
4223 * demote the mapping and fall through.
4225 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
4226 pmap_remove_pte1(pmap, pte1p, sva, &free);
4228 } else if (!pmap_demote_pte1(pmap, pte1p, sva)) {
4229 /* The large page mapping was destroyed. */
4234 /* Update pte1 after demotion. */
4235 pte1 = pte1_load(pte1p);
4240 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
4241 " is not link", __func__, pmap, sva, pte1, pte1p));
4244 * Limit our scan to either the end of the va represented
4245 * by the current L2 page table page, or to the end of the
4246 * range being removed.
4251 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva;
4252 pte2p++, sva += PAGE_SIZE) {
4253 pte2 = pte2_load(pte2p);
4254 if (!pte2_is_valid(pte2))
4256 if (pmap_remove_pte2(pmap, pte2p, sva, &free))
4262 rw_wunlock(&pvh_global_lock);
4264 vm_page_free_pages_toq(&free, false);
4268 * Routine: pmap_remove_all
4270 * Removes this physical page from
4271 * all physical maps in which it resides.
4272 * Reflects back modify bits to the pager.
4275 * Original versions of this routine were very
4276 * inefficient because they iteratively called
4277 * pmap_remove (slow...)
4281 pmap_remove_all(vm_page_t m)
4283 struct md_page *pvh;
4286 pt2_entry_t *pte2p, opte2;
4289 struct spglist free;
4291 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4292 ("%s: page %p is not managed", __func__, m));
4294 rw_wlock(&pvh_global_lock);
4296 if ((m->flags & PG_FICTITIOUS) != 0)
4297 goto small_mappings;
4298 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4299 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
4303 pte1p = pmap_pte1(pmap, va);
4304 (void)pmap_demote_pte1(pmap, pte1p, va);
4308 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4311 pmap->pm_stats.resident_count--;
4312 pte1p = pmap_pte1(pmap, pv->pv_va);
4313 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found "
4314 "a 1mpage in page %p's pv list", __func__, m));
4315 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
4316 opte2 = pte2_load_clear(pte2p);
4317 pmap_tlb_flush(pmap, pv->pv_va);
4318 KASSERT(pte2_is_valid(opte2), ("%s: pmap %p va %x zero pte2",
4319 __func__, pmap, pv->pv_va));
4320 if (pte2_is_wired(opte2))
4321 pmap->pm_stats.wired_count--;
4323 vm_page_aflag_set(m, PGA_REFERENCED);
4326 * Update the vm_page_t clean and reference bits.
4328 if (pte2_is_dirty(opte2))
4330 pmap_unuse_pt2(pmap, pv->pv_va, &free);
4331 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4332 free_pv_entry(pmap, pv);
4335 vm_page_aflag_clear(m, PGA_WRITEABLE);
4337 rw_wunlock(&pvh_global_lock);
4338 vm_page_free_pages_toq(&free, false);
4342 * Just subroutine for pmap_remove_pages() to reasonably satisfy
4343 * good coding style, a.k.a. 80 character line width limit hell.
4345 static __inline void
4346 pmap_remove_pte1_quick(pmap_t pmap, pt1_entry_t pte1, pv_entry_t pv,
4347 struct spglist *free)
4350 vm_page_t m, mt, mpt2pg;
4351 struct md_page *pvh;
4354 m = PHYS_TO_VM_PAGE(pa);
4356 KASSERT(m->phys_addr == pa, ("%s: vm_page_t %p addr mismatch %#x %#x",
4357 __func__, m, m->phys_addr, pa));
4358 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4359 m < &vm_page_array[vm_page_array_size],
4360 ("%s: bad pte1 %#x", __func__, pte1));
4362 if (pte1_is_dirty(pte1)) {
4363 for (mt = m; mt < &m[PTE1_SIZE / PAGE_SIZE]; mt++)
4367 pmap->pm_stats.resident_count -= PTE1_SIZE / PAGE_SIZE;
4368 pvh = pa_to_pvh(pa);
4369 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4370 if (TAILQ_EMPTY(&pvh->pv_list)) {
4371 for (mt = m; mt < &m[PTE1_SIZE / PAGE_SIZE]; mt++)
4372 if (TAILQ_EMPTY(&mt->md.pv_list))
4373 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4375 mpt2pg = pmap_pt2_page(pmap, pv->pv_va);
4377 pmap_unwire_pt2_all(pmap, pv->pv_va, mpt2pg, free);
4381 * Just subroutine for pmap_remove_pages() to reasonably satisfy
4382 * good coding style, a.k.a. 80 character line width limit hell.
4384 static __inline void
4385 pmap_remove_pte2_quick(pmap_t pmap, pt2_entry_t pte2, pv_entry_t pv,
4386 struct spglist *free)
4390 struct md_page *pvh;
4393 m = PHYS_TO_VM_PAGE(pa);
4395 KASSERT(m->phys_addr == pa, ("%s: vm_page_t %p addr mismatch %#x %#x",
4396 __func__, m, m->phys_addr, pa));
4397 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4398 m < &vm_page_array[vm_page_array_size],
4399 ("%s: bad pte2 %#x", __func__, pte2));
4401 if (pte2_is_dirty(pte2))
4404 pmap->pm_stats.resident_count--;
4405 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4406 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
4407 pvh = pa_to_pvh(pa);
4408 if (TAILQ_EMPTY(&pvh->pv_list))
4409 vm_page_aflag_clear(m, PGA_WRITEABLE);
4411 pmap_unuse_pt2(pmap, pv->pv_va, free);
4415 * Remove all pages from specified address space this aids process
4416 * exit speeds. Also, this code is special cased for current process
4417 * only, but can have the more generic (and slightly slower) mode enabled.
4418 * This is much faster than pmap_remove in the case of running down
4419 * an entire address space.
4422 pmap_remove_pages(pmap_t pmap)
4424 pt1_entry_t *pte1p, pte1;
4425 pt2_entry_t *pte2p, pte2;
4427 struct pv_chunk *pc, *npc;
4428 struct spglist free;
4431 uint32_t inuse, bitmask;
4435 * Assert that the given pmap is only active on the current
4436 * CPU. Unfortunately, we cannot block another CPU from
4437 * activating the pmap while this function is executing.
4439 KASSERT(pmap == vmspace_pmap(curthread->td_proc->p_vmspace),
4440 ("%s: non-current pmap %p", __func__, pmap));
4441 #if defined(SMP) && defined(INVARIANTS)
4443 cpuset_t other_cpus;
4446 other_cpus = pmap->pm_active;
4447 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
4449 KASSERT(CPU_EMPTY(&other_cpus),
4450 ("%s: pmap %p active on other cpus", __func__, pmap));
4454 rw_wlock(&pvh_global_lock);
4457 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4458 KASSERT(pc->pc_pmap == pmap, ("%s: wrong pmap %p %p",
4459 __func__, pmap, pc->pc_pmap));
4461 for (field = 0; field < _NPCM; field++) {
4462 inuse = (~(pc->pc_map[field])) & pc_freemask[field];
4463 while (inuse != 0) {
4464 bit = ffs(inuse) - 1;
4465 bitmask = 1UL << bit;
4466 idx = field * 32 + bit;
4467 pv = &pc->pc_pventry[idx];
4471 * Note that we cannot remove wired pages
4472 * from a process' mapping at this time
4474 pte1p = pmap_pte1(pmap, pv->pv_va);
4475 pte1 = pte1_load(pte1p);
4476 if (pte1_is_section(pte1)) {
4477 if (pte1_is_wired(pte1)) {
4482 pmap_remove_pte1_quick(pmap, pte1, pv,
4485 else if (pte1_is_link(pte1)) {
4486 pte2p = pt2map_entry(pv->pv_va);
4487 pte2 = pte2_load(pte2p);
4489 if (!pte2_is_valid(pte2)) {
4490 printf("%s: pmap %p va %#x "
4491 "pte2 %#x\n", __func__,
4492 pmap, pv->pv_va, pte2);
4496 if (pte2_is_wired(pte2)) {
4501 pmap_remove_pte2_quick(pmap, pte2, pv,
4504 printf("%s: pmap %p va %#x pte1 %#x\n",
4505 __func__, pmap, pv->pv_va, pte1);
4510 PV_STAT(pv_entry_frees++);
4511 PV_STAT(pv_entry_spare++);
4513 pc->pc_map[field] |= bitmask;
4517 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4521 tlb_flush_all_ng_local();
4523 rw_wunlock(&pvh_global_lock);
4525 vm_page_free_pages_toq(&free, false);
4529 * This code makes some *MAJOR* assumptions:
4530 * 1. Current pmap & pmap exists.
4533 * 4. No L2 page table pages.
4534 * but is *MUCH* faster than pmap_enter...
4537 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4538 vm_prot_t prot, vm_page_t mpt2pg)
4540 pt2_entry_t *pte2p, pte2;
4542 struct spglist free;
4545 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
4546 (m->oflags & VPO_UNMANAGED) != 0,
4547 ("%s: managed mapping within the clean submap", __func__));
4548 rw_assert(&pvh_global_lock, RA_WLOCKED);
4549 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4552 * In the case that a L2 page table page is not
4553 * resident, we are creating it here.
4555 if (va < VM_MAXUSER_ADDRESS) {
4557 pt1_entry_t pte1, *pte1p;
4561 * Get L1 page table things.
4563 pte1_idx = pte1_index(va);
4564 pte1p = pmap_pte1(pmap, va);
4565 pte1 = pte1_load(pte1p);
4567 if (mpt2pg && (mpt2pg->pindex == (pte1_idx & ~PT2PG_MASK))) {
4569 * Each of NPT2_IN_PG L2 page tables on the page can
4570 * come here. Make sure that associated L1 page table
4571 * link is established.
4573 * QQQ: It comes that we don't establish all links to
4574 * L2 page tables for newly allocated L2 page
4577 KASSERT(!pte1_is_section(pte1),
4578 ("%s: pte1 %#x is section", __func__, pte1));
4579 if (!pte1_is_link(pte1)) {
4580 pt2_pa = page_pt2pa(VM_PAGE_TO_PHYS(mpt2pg),
4582 pte1_store(pte1p, PTE1_LINK(pt2_pa));
4584 pt2_wirecount_inc(mpt2pg, pte1_idx);
4587 * If the L2 page table page is mapped, we just
4588 * increment the hold count, and activate it.
4590 if (pte1_is_section(pte1)) {
4592 } else if (pte1_is_link(pte1)) {
4593 mpt2pg = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
4594 pt2_wirecount_inc(mpt2pg, pte1_idx);
4596 mpt2pg = _pmap_allocpte2(pmap, va,
4597 PMAP_ENTER_NOSLEEP);
4607 * This call to pt2map_entry() makes the assumption that we are
4608 * entering the page into the current pmap. In order to support
4609 * quick entry into any pmap, one would likely use pmap_pte2_quick().
4610 * But that isn't as quick as pt2map_entry().
4612 pte2p = pt2map_entry(va);
4613 pte2 = pte2_load(pte2p);
4614 if (pte2_is_valid(pte2)) {
4615 if (mpt2pg != NULL) {
4617 * Remove extra pte2 reference
4619 pt2_wirecount_dec(mpt2pg, pte1_index(va));
4626 * Enter on the PV list if part of our managed memory.
4628 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4629 !pmap_try_insert_pv_entry(pmap, va, m)) {
4630 if (mpt2pg != NULL) {
4632 if (pmap_unwire_pt2(pmap, va, mpt2pg, &free)) {
4633 pmap_tlb_flush(pmap, va);
4634 vm_page_free_pages_toq(&free, false);
4643 * Increment counters
4645 pmap->pm_stats.resident_count++;
4648 * Now validate mapping with RO protection
4650 pa = VM_PAGE_TO_PHYS(m);
4651 l2prot = PTE2_RO | PTE2_NM;
4652 if (va < VM_MAXUSER_ADDRESS)
4653 l2prot |= PTE2_U | PTE2_NG;
4654 if ((prot & VM_PROT_EXECUTE) == 0)
4656 else if (m->md.pat_mode == VM_MEMATTR_WB_WA && pmap != kernel_pmap) {
4658 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4659 * is set. QQQ: For more info, see comments in pmap_enter().
4661 cache_icache_sync_fresh(va, pa, PAGE_SIZE);
4663 pte2_store(pte2p, PTE2(pa, l2prot, vm_page_pte2_attr(m)));
4669 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4672 rw_wlock(&pvh_global_lock);
4674 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
4675 rw_wunlock(&pvh_global_lock);
4680 * Tries to create a read- and/or execute-only 1 MB page mapping. Returns
4681 * true if successful. Returns false if (1) a mapping already exists at the
4682 * specified virtual address or (2) a PV entry cannot be allocated without
4683 * reclaiming another PV entry.
4686 pmap_enter_1mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4691 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4692 pa = VM_PAGE_TO_PHYS(m);
4693 pte1 = PTE1(pa, PTE1_NM | PTE1_RO, ATTR_TO_L1(vm_page_pte2_attr(m)));
4694 if ((prot & VM_PROT_EXECUTE) == 0)
4696 if (va < VM_MAXUSER_ADDRESS)
4698 if (pmap != kernel_pmap)
4700 return (pmap_enter_pte1(pmap, va, pte1, PMAP_ENTER_NOSLEEP |
4701 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, m) == KERN_SUCCESS);
4705 * Tries to create the specified 1 MB page mapping. Returns KERN_SUCCESS if
4706 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
4707 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
4708 * a mapping already exists at the specified virtual address. Returns
4709 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NORECLAIM was specified and PV entry
4710 * allocation failed.
4713 pmap_enter_pte1(pmap_t pmap, vm_offset_t va, pt1_entry_t pte1, u_int flags,
4716 struct spglist free;
4717 pt1_entry_t opte1, *pte1p;
4718 pt2_entry_t pte2, *pte2p;
4719 vm_offset_t cur, end;
4722 rw_assert(&pvh_global_lock, RA_WLOCKED);
4723 KASSERT((pte1 & (PTE1_NM | PTE1_RO)) == 0 ||
4724 (pte1 & (PTE1_NM | PTE1_RO)) == (PTE1_NM | PTE1_RO),
4725 ("%s: pte1 has inconsistent NM and RO attributes", __func__));
4726 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4727 pte1p = pmap_pte1(pmap, va);
4728 opte1 = pte1_load(pte1p);
4729 if (pte1_is_valid(opte1)) {
4730 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
4731 CTR3(KTR_PMAP, "%s: failure for va %#lx in pmap %p",
4732 __func__, va, pmap);
4733 return (KERN_FAILURE);
4735 /* Break the existing mapping(s). */
4737 if (pte1_is_section(opte1)) {
4739 * If the section resulted from a promotion, then a
4740 * reserved PT page could be freed.
4742 pmap_remove_pte1(pmap, pte1p, va, &free);
4745 end = va + PTE1_SIZE;
4746 for (cur = va, pte2p = pmap_pte2_quick(pmap, va);
4747 cur != end; cur += PAGE_SIZE, pte2p++) {
4748 pte2 = pte2_load(pte2p);
4749 if (!pte2_is_valid(pte2))
4751 if (pmap_remove_pte2(pmap, pte2p, cur, &free))
4756 vm_page_free_pages_toq(&free, false);
4758 if ((m->oflags & VPO_UNMANAGED) == 0) {
4760 * Abort this mapping if its PV entry could not be created.
4762 if (!pmap_pv_insert_pte1(pmap, va, pte1, flags)) {
4763 CTR3(KTR_PMAP, "%s: failure for va %#lx in pmap %p",
4764 __func__, va, pmap);
4765 return (KERN_RESOURCE_SHORTAGE);
4767 if ((pte1 & PTE1_RO) == 0) {
4768 for (mt = m; mt < &m[PTE1_SIZE / PAGE_SIZE]; mt++)
4769 vm_page_aflag_set(mt, PGA_WRITEABLE);
4774 * Increment counters.
4776 if (pte1_is_wired(pte1))
4777 pmap->pm_stats.wired_count += PTE1_SIZE / PAGE_SIZE;
4778 pmap->pm_stats.resident_count += PTE1_SIZE / PAGE_SIZE;
4781 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4782 * is set. QQQ: For more info, see comments in pmap_enter().
4784 if ((pte1 & PTE1_NX) == 0 && m->md.pat_mode == VM_MEMATTR_WB_WA &&
4785 pmap != kernel_pmap && (!pte1_is_section(opte1) ||
4786 pte1_pa(opte1) != VM_PAGE_TO_PHYS(m) || (opte1 & PTE2_NX) != 0))
4787 cache_icache_sync_fresh(va, VM_PAGE_TO_PHYS(m), PTE1_SIZE);
4792 pte1_store(pte1p, pte1);
4794 pmap_pte1_mappings++;
4795 CTR3(KTR_PMAP, "%s: success for va %#lx in pmap %p", __func__, va,
4797 return (KERN_SUCCESS);
4801 * Maps a sequence of resident pages belonging to the same object.
4802 * The sequence begins with the given page m_start. This page is
4803 * mapped at the given virtual address start. Each subsequent page is
4804 * mapped at a virtual address that is offset from start by the same
4805 * amount as the page is offset from m_start within the object. The
4806 * last page in the sequence is the page with the largest offset from
4807 * m_start that can be mapped at a virtual address less than the given
4808 * virtual address end. Not every virtual page between start and end
4809 * is mapped; only those for which a resident page exists with the
4810 * corresponding offset from m_start are mapped.
4813 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4814 vm_page_t m_start, vm_prot_t prot)
4817 vm_page_t m, mpt2pg;
4818 vm_pindex_t diff, psize;
4820 PDEBUG(6, printf("%s: pmap %p start %#x end %#x m %p prot %#x\n",
4821 __func__, pmap, start, end, m_start, prot));
4823 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4824 psize = atop(end - start);
4827 rw_wlock(&pvh_global_lock);
4829 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4830 va = start + ptoa(diff);
4831 if ((va & PTE1_OFFSET) == 0 && va + PTE1_SIZE <= end &&
4832 m->psind == 1 && sp_enabled &&
4833 pmap_enter_1mpage(pmap, va, m, prot))
4834 m = &m[PTE1_SIZE / PAGE_SIZE - 1];
4836 mpt2pg = pmap_enter_quick_locked(pmap, va, m, prot,
4838 m = TAILQ_NEXT(m, listq);
4840 rw_wunlock(&pvh_global_lock);
4845 * This code maps large physical mmap regions into the
4846 * processor address space. Note that some shortcuts
4847 * are taken, but the code works.
4850 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4851 vm_pindex_t pindex, vm_size_t size)
4854 vm_paddr_t pa, pte2_pa;
4856 vm_memattr_t pat_mode;
4857 u_int l1attr, l1prot;
4859 VM_OBJECT_ASSERT_WLOCKED(object);
4860 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4861 ("%s: non-device object", __func__));
4862 if ((addr & PTE1_OFFSET) == 0 && (size & PTE1_OFFSET) == 0) {
4863 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4865 p = vm_page_lookup(object, pindex);
4866 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4867 ("%s: invalid page %p", __func__, p));
4868 pat_mode = p->md.pat_mode;
4871 * Abort the mapping if the first page is not physically
4872 * aligned to a 1MB page boundary.
4874 pte2_pa = VM_PAGE_TO_PHYS(p);
4875 if (pte2_pa & PTE1_OFFSET)
4879 * Skip the first page. Abort the mapping if the rest of
4880 * the pages are not physically contiguous or have differing
4881 * memory attributes.
4883 p = TAILQ_NEXT(p, listq);
4884 for (pa = pte2_pa + PAGE_SIZE; pa < pte2_pa + size;
4886 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4887 ("%s: invalid page %p", __func__, p));
4888 if (pa != VM_PAGE_TO_PHYS(p) ||
4889 pat_mode != p->md.pat_mode)
4891 p = TAILQ_NEXT(p, listq);
4895 * Map using 1MB pages.
4897 * QQQ: Well, we are mapping a section, so same condition must
4898 * be hold like during promotion. It looks that only RW mapping
4899 * is done here, so readonly mapping must be done elsewhere.
4901 l1prot = PTE1_U | PTE1_NG | PTE1_RW | PTE1_M | PTE1_A;
4902 l1attr = ATTR_TO_L1(vm_memattr_to_pte2(pat_mode));
4904 for (pa = pte2_pa; pa < pte2_pa + size; pa += PTE1_SIZE) {
4905 pte1p = pmap_pte1(pmap, addr);
4906 if (!pte1_is_valid(pte1_load(pte1p))) {
4907 pte1_store(pte1p, PTE1(pa, l1prot, l1attr));
4908 pmap->pm_stats.resident_count += PTE1_SIZE /
4910 pmap_pte1_mappings++;
4912 /* Else continue on if the PTE1 is already valid. */
4920 * Do the things to protect a 1mpage in a process.
4923 pmap_protect_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t sva,
4926 pt1_entry_t npte1, opte1;
4927 vm_offset_t eva, va;
4930 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4931 KASSERT((sva & PTE1_OFFSET) == 0,
4932 ("%s: sva is not 1mpage aligned", __func__));
4934 opte1 = npte1 = pte1_load(pte1p);
4935 if (pte1_is_managed(opte1) && pte1_is_dirty(opte1)) {
4936 eva = sva + PTE1_SIZE;
4937 for (va = sva, m = PHYS_TO_VM_PAGE(pte1_pa(opte1));
4938 va < eva; va += PAGE_SIZE, m++)
4941 if ((prot & VM_PROT_WRITE) == 0)
4942 npte1 |= PTE1_RO | PTE1_NM;
4943 if ((prot & VM_PROT_EXECUTE) == 0)
4947 * QQQ: Herein, execute permission is never set.
4948 * It only can be cleared. So, no icache
4949 * syncing is needed.
4952 if (npte1 != opte1) {
4953 pte1_store(pte1p, npte1);
4954 pmap_tlb_flush(pmap, sva);
4959 * Set the physical protection on the
4960 * specified range of this map as requested.
4963 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
4965 boolean_t pv_lists_locked;
4967 pt1_entry_t *pte1p, pte1;
4968 pt2_entry_t *pte2p, opte2, npte2;
4970 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
4971 if (prot == VM_PROT_NONE) {
4972 pmap_remove(pmap, sva, eva);
4976 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
4977 (VM_PROT_WRITE | VM_PROT_EXECUTE))
4980 if (pmap_is_current(pmap))
4981 pv_lists_locked = FALSE;
4983 pv_lists_locked = TRUE;
4985 rw_wlock(&pvh_global_lock);
4990 for (; sva < eva; sva = nextva) {
4992 * Calculate address for next L2 page table.
4994 nextva = pte1_trunc(sva + PTE1_SIZE);
4998 pte1p = pmap_pte1(pmap, sva);
4999 pte1 = pte1_load(pte1p);
5002 * Weed out invalid mappings. Note: we assume that L1 page
5003 * page table is always allocated, and in kernel virtual.
5008 if (pte1_is_section(pte1)) {
5010 * Are we protecting the entire large page? If not,
5011 * demote the mapping and fall through.
5013 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
5014 pmap_protect_pte1(pmap, pte1p, sva, prot);
5017 if (!pv_lists_locked) {
5018 pv_lists_locked = TRUE;
5019 if (!rw_try_wlock(&pvh_global_lock)) {
5025 if (!pmap_demote_pte1(pmap, pte1p, sva)) {
5027 * The large page mapping
5034 /* Update pte1 after demotion */
5035 pte1 = pte1_load(pte1p);
5041 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
5042 " is not link", __func__, pmap, sva, pte1, pte1p));
5045 * Limit our scan to either the end of the va represented
5046 * by the current L2 page table page, or to the end of the
5047 * range being protected.
5052 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva; pte2p++,
5056 opte2 = npte2 = pte2_load(pte2p);
5057 if (!pte2_is_valid(opte2))
5060 if ((prot & VM_PROT_WRITE) == 0) {
5061 if (pte2_is_managed(opte2) &&
5062 pte2_is_dirty(opte2)) {
5063 m = PHYS_TO_VM_PAGE(pte2_pa(opte2));
5066 npte2 |= PTE2_RO | PTE2_NM;
5069 if ((prot & VM_PROT_EXECUTE) == 0)
5073 * QQQ: Herein, execute permission is never set.
5074 * It only can be cleared. So, no icache
5075 * syncing is needed.
5078 if (npte2 != opte2) {
5079 pte2_store(pte2p, npte2);
5080 pmap_tlb_flush(pmap, sva);
5084 if (pv_lists_locked) {
5086 rw_wunlock(&pvh_global_lock);
5092 * pmap_pvh_wired_mappings:
5094 * Return the updated number "count" of managed mappings that are wired.
5097 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
5104 rw_assert(&pvh_global_lock, RA_WLOCKED);
5106 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5109 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5110 if (pte1_is_section(pte1)) {
5111 if (pte1_is_wired(pte1))
5114 KASSERT(pte1_is_link(pte1),
5115 ("%s: pte1 %#x is not link", __func__, pte1));
5116 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5117 if (pte2_is_wired(pte2))
5127 * pmap_page_wired_mappings:
5129 * Return the number of managed mappings to the given physical page
5133 pmap_page_wired_mappings(vm_page_t m)
5138 if ((m->oflags & VPO_UNMANAGED) != 0)
5140 rw_wlock(&pvh_global_lock);
5141 count = pmap_pvh_wired_mappings(&m->md, count);
5142 if ((m->flags & PG_FICTITIOUS) == 0) {
5143 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
5146 rw_wunlock(&pvh_global_lock);
5151 * Returns TRUE if any of the given mappings were used to modify
5152 * physical memory. Otherwise, returns FALSE. Both page and 1mpage
5153 * mappings are supported.
5156 pmap_is_modified_pvh(struct md_page *pvh)
5164 rw_assert(&pvh_global_lock, RA_WLOCKED);
5167 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5170 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5171 if (pte1_is_section(pte1)) {
5172 rv = pte1_is_dirty(pte1);
5174 KASSERT(pte1_is_link(pte1),
5175 ("%s: pte1 %#x is not link", __func__, pte1));
5176 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5177 rv = pte2_is_dirty(pte2);
5190 * Return whether or not the specified physical page was modified
5191 * in any physical maps.
5194 pmap_is_modified(vm_page_t m)
5198 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5199 ("%s: page %p is not managed", __func__, m));
5202 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5203 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
5204 * is clear, no PTE2s can have PG_M set.
5206 VM_OBJECT_ASSERT_WLOCKED(m->object);
5207 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5209 rw_wlock(&pvh_global_lock);
5210 rv = pmap_is_modified_pvh(&m->md) ||
5211 ((m->flags & PG_FICTITIOUS) == 0 &&
5212 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
5213 rw_wunlock(&pvh_global_lock);
5218 * pmap_is_prefaultable:
5220 * Return whether or not the specified virtual address is eligible
5224 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
5232 pte1 = pte1_load(pmap_pte1(pmap, addr));
5233 if (pte1_is_link(pte1)) {
5234 pte2 = pte2_load(pt2map_entry(addr));
5235 rv = !pte2_is_valid(pte2) ;
5242 * Returns TRUE if any of the given mappings were referenced and FALSE
5243 * otherwise. Both page and 1mpage mappings are supported.
5246 pmap_is_referenced_pvh(struct md_page *pvh)
5255 rw_assert(&pvh_global_lock, RA_WLOCKED);
5258 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5261 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5262 if (pte1_is_section(pte1)) {
5263 rv = (pte1 & (PTE1_A | PTE1_V)) == (PTE1_A | PTE1_V);
5265 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5266 rv = (pte2 & (PTE2_A | PTE2_V)) == (PTE2_A | PTE2_V);
5277 * pmap_is_referenced:
5279 * Return whether or not the specified physical page was referenced
5280 * in any physical maps.
5283 pmap_is_referenced(vm_page_t m)
5287 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5288 ("%s: page %p is not managed", __func__, m));
5289 rw_wlock(&pvh_global_lock);
5290 rv = pmap_is_referenced_pvh(&m->md) ||
5291 ((m->flags & PG_FICTITIOUS) == 0 &&
5292 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
5293 rw_wunlock(&pvh_global_lock);
5298 * pmap_ts_referenced:
5300 * Return a count of reference bits for a page, clearing those bits.
5301 * It is not necessary for every reference bit to be cleared, but it
5302 * is necessary that 0 only be returned when there are truly no
5303 * reference bits set.
5305 * As an optimization, update the page's dirty field if a modified bit is
5306 * found while counting reference bits. This opportunistic update can be
5307 * performed at low cost and can eliminate the need for some future calls
5308 * to pmap_is_modified(). However, since this function stops after
5309 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5310 * dirty pages. Those dirty pages will only be detected by a future call
5311 * to pmap_is_modified().
5314 pmap_ts_referenced(vm_page_t m)
5316 struct md_page *pvh;
5319 pt1_entry_t *pte1p, opte1;
5320 pt2_entry_t *pte2p, opte2;
5324 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5325 ("%s: page %p is not managed", __func__, m));
5326 pa = VM_PAGE_TO_PHYS(m);
5327 pvh = pa_to_pvh(pa);
5328 rw_wlock(&pvh_global_lock);
5330 if ((m->flags & PG_FICTITIOUS) != 0 ||
5331 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5332 goto small_mappings;
5337 pte1p = pmap_pte1(pmap, pv->pv_va);
5338 opte1 = pte1_load(pte1p);
5339 if (pte1_is_dirty(opte1)) {
5341 * Although "opte1" is mapping a 1MB page, because
5342 * this function is called at a 4KB page granularity,
5343 * we only update the 4KB page under test.
5347 if ((opte1 & PTE1_A) != 0) {
5349 * Since this reference bit is shared by 256 4KB pages,
5350 * it should not be cleared every time it is tested.
5351 * Apply a simple "hash" function on the physical page
5352 * number, the virtual section number, and the pmap
5353 * address to select one 4KB page out of the 256
5354 * on which testing the reference bit will result
5355 * in clearing that bit. This function is designed
5356 * to avoid the selection of the same 4KB page
5357 * for every 1MB page mapping.
5359 * On demotion, a mapping that hasn't been referenced
5360 * is simply destroyed. To avoid the possibility of a
5361 * subsequent page fault on a demoted wired mapping,
5362 * always leave its reference bit set. Moreover,
5363 * since the section is wired, the current state of
5364 * its reference bit won't affect page replacement.
5366 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PTE1_SHIFT) ^
5367 (uintptr_t)pmap) & (NPTE2_IN_PG - 1)) == 0 &&
5368 !pte1_is_wired(opte1)) {
5369 pte1_clear_bit(pte1p, PTE1_A);
5370 pmap_tlb_flush(pmap, pv->pv_va);
5375 /* Rotate the PV list if it has more than one entry. */
5376 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5377 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5378 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5380 if (rtval >= PMAP_TS_REFERENCED_MAX)
5382 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5384 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5390 pte1p = pmap_pte1(pmap, pv->pv_va);
5391 KASSERT(pte1_is_link(pte1_load(pte1p)),
5392 ("%s: not found a link in page %p's pv list", __func__, m));
5394 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5395 opte2 = pte2_load(pte2p);
5396 if (pte2_is_dirty(opte2))
5398 if ((opte2 & PTE2_A) != 0) {
5399 pte2_clear_bit(pte2p, PTE2_A);
5400 pmap_tlb_flush(pmap, pv->pv_va);
5404 /* Rotate the PV list if it has more than one entry. */
5405 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5406 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5407 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5409 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
5410 PMAP_TS_REFERENCED_MAX);
5413 rw_wunlock(&pvh_global_lock);
5418 * Clear the wired attribute from the mappings for the specified range of
5419 * addresses in the given pmap. Every valid mapping within that range
5420 * must have the wired attribute set. In contrast, invalid mappings
5421 * cannot have the wired attribute set, so they are ignored.
5423 * The wired attribute of the page table entry is not a hardware feature,
5424 * so there is no need to invalidate any TLB entries.
5427 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5430 pt1_entry_t *pte1p, pte1;
5431 pt2_entry_t *pte2p, pte2;
5432 boolean_t pv_lists_locked;
5434 if (pmap_is_current(pmap))
5435 pv_lists_locked = FALSE;
5437 pv_lists_locked = TRUE;
5439 rw_wlock(&pvh_global_lock);
5443 for (; sva < eva; sva = nextva) {
5444 nextva = pte1_trunc(sva + PTE1_SIZE);
5448 pte1p = pmap_pte1(pmap, sva);
5449 pte1 = pte1_load(pte1p);
5452 * Weed out invalid mappings. Note: we assume that L1 page
5453 * page table is always allocated, and in kernel virtual.
5458 if (pte1_is_section(pte1)) {
5459 if (!pte1_is_wired(pte1))
5460 panic("%s: pte1 %#x not wired", __func__, pte1);
5463 * Are we unwiring the entire large page? If not,
5464 * demote the mapping and fall through.
5466 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
5467 pte1_clear_bit(pte1p, PTE1_W);
5468 pmap->pm_stats.wired_count -= PTE1_SIZE /
5472 if (!pv_lists_locked) {
5473 pv_lists_locked = TRUE;
5474 if (!rw_try_wlock(&pvh_global_lock)) {
5481 if (!pmap_demote_pte1(pmap, pte1p, sva))
5482 panic("%s: demotion failed", __func__);
5485 /* Update pte1 after demotion */
5486 pte1 = pte1_load(pte1p);
5492 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
5493 " is not link", __func__, pmap, sva, pte1, pte1p));
5496 * Limit our scan to either the end of the va represented
5497 * by the current L2 page table page, or to the end of the
5498 * range being protected.
5503 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva; pte2p++,
5505 pte2 = pte2_load(pte2p);
5506 if (!pte2_is_valid(pte2))
5508 if (!pte2_is_wired(pte2))
5509 panic("%s: pte2 %#x is missing PTE2_W",
5513 * PTE2_W must be cleared atomically. Although the pmap
5514 * lock synchronizes access to PTE2_W, another processor
5515 * could be changing PTE2_NM and/or PTE2_A concurrently.
5517 pte2_clear_bit(pte2p, PTE2_W);
5518 pmap->pm_stats.wired_count--;
5521 if (pv_lists_locked) {
5523 rw_wunlock(&pvh_global_lock);
5529 * Clear the write and modified bits in each of the given page's mappings.
5532 pmap_remove_write(vm_page_t m)
5534 struct md_page *pvh;
5535 pv_entry_t next_pv, pv;
5538 pt2_entry_t *pte2p, opte2;
5541 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5542 ("%s: page %p is not managed", __func__, m));
5545 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5546 * set by another thread while the object is locked. Thus,
5547 * if PGA_WRITEABLE is clear, no page table entries need updating.
5549 VM_OBJECT_ASSERT_WLOCKED(m->object);
5550 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5552 rw_wlock(&pvh_global_lock);
5554 if ((m->flags & PG_FICTITIOUS) != 0)
5555 goto small_mappings;
5556 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5557 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5561 pte1p = pmap_pte1(pmap, va);
5562 if (!(pte1_load(pte1p) & PTE1_RO))
5563 (void)pmap_demote_pte1(pmap, pte1p, va);
5567 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5570 pte1p = pmap_pte1(pmap, pv->pv_va);
5571 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found"
5572 " a section in page %p's pv list", __func__, m));
5573 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5574 opte2 = pte2_load(pte2p);
5575 if (!(opte2 & PTE2_RO)) {
5576 pte2_store(pte2p, opte2 | PTE2_RO | PTE2_NM);
5577 if (pte2_is_dirty(opte2))
5579 pmap_tlb_flush(pmap, pv->pv_va);
5583 vm_page_aflag_clear(m, PGA_WRITEABLE);
5585 rw_wunlock(&pvh_global_lock);
5589 * Apply the given advice to the specified range of addresses within the
5590 * given pmap. Depending on the advice, clear the referenced and/or
5591 * modified flags in each mapping and set the mapped page's dirty field.
5594 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5596 pt1_entry_t *pte1p, opte1;
5597 pt2_entry_t *pte2p, pte2;
5600 boolean_t pv_lists_locked;
5602 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5604 if (pmap_is_current(pmap))
5605 pv_lists_locked = FALSE;
5607 pv_lists_locked = TRUE;
5609 rw_wlock(&pvh_global_lock);
5613 for (; sva < eva; sva = pdnxt) {
5614 pdnxt = pte1_trunc(sva + PTE1_SIZE);
5617 pte1p = pmap_pte1(pmap, sva);
5618 opte1 = pte1_load(pte1p);
5619 if (!pte1_is_valid(opte1)) /* XXX */
5621 else if (pte1_is_section(opte1)) {
5622 if (!pte1_is_managed(opte1))
5624 if (!pv_lists_locked) {
5625 pv_lists_locked = TRUE;
5626 if (!rw_try_wlock(&pvh_global_lock)) {
5632 if (!pmap_demote_pte1(pmap, pte1p, sva)) {
5634 * The large page mapping was destroyed.
5640 * Unless the page mappings are wired, remove the
5641 * mapping to a single page so that a subsequent
5642 * access may repromote. Since the underlying L2 page
5643 * table is fully populated, this removal never
5644 * frees a L2 page table page.
5646 if (!pte1_is_wired(opte1)) {
5647 pte2p = pmap_pte2_quick(pmap, sva);
5648 KASSERT(pte2_is_valid(pte2_load(pte2p)),
5649 ("%s: invalid PTE2", __func__));
5650 pmap_remove_pte2(pmap, pte2p, sva, NULL);
5655 for (pte2p = pmap_pte2_quick(pmap, sva); sva != pdnxt; pte2p++,
5657 pte2 = pte2_load(pte2p);
5658 if (!pte2_is_valid(pte2) || !pte2_is_managed(pte2))
5660 else if (pte2_is_dirty(pte2)) {
5661 if (advice == MADV_DONTNEED) {
5663 * Future calls to pmap_is_modified()
5664 * can be avoided by making the page
5667 m = PHYS_TO_VM_PAGE(pte2_pa(pte2));
5670 pte2_set_bit(pte2p, PTE2_NM);
5671 pte2_clear_bit(pte2p, PTE2_A);
5672 } else if ((pte2 & PTE2_A) != 0)
5673 pte2_clear_bit(pte2p, PTE2_A);
5676 pmap_tlb_flush(pmap, sva);
5679 if (pv_lists_locked) {
5681 rw_wunlock(&pvh_global_lock);
5687 * Clear the modify bits on the specified physical page.
5690 pmap_clear_modify(vm_page_t m)
5692 struct md_page *pvh;
5693 pv_entry_t next_pv, pv;
5695 pt1_entry_t *pte1p, opte1;
5696 pt2_entry_t *pte2p, opte2;
5699 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5700 ("%s: page %p is not managed", __func__, m));
5701 VM_OBJECT_ASSERT_WLOCKED(m->object);
5702 KASSERT(!vm_page_xbusied(m),
5703 ("%s: page %p is exclusive busy", __func__, m));
5706 * If the page is not PGA_WRITEABLE, then no PTE2s can have PTE2_NM
5707 * cleared. If the object containing the page is locked and the page
5708 * is not exclusive busied, then PGA_WRITEABLE cannot be concurrently
5711 if ((m->flags & PGA_WRITEABLE) == 0)
5713 rw_wlock(&pvh_global_lock);
5715 if ((m->flags & PG_FICTITIOUS) != 0)
5716 goto small_mappings;
5717 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5718 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5722 pte1p = pmap_pte1(pmap, va);
5723 opte1 = pte1_load(pte1p);
5724 if (!(opte1 & PTE1_RO)) {
5725 if (pmap_demote_pte1(pmap, pte1p, va) &&
5726 !pte1_is_wired(opte1)) {
5728 * Write protect the mapping to a
5729 * single page so that a subsequent
5730 * write access may repromote.
5732 va += VM_PAGE_TO_PHYS(m) - pte1_pa(opte1);
5733 pte2p = pmap_pte2_quick(pmap, va);
5734 opte2 = pte2_load(pte2p);
5735 if ((opte2 & PTE2_V)) {
5736 pte2_set_bit(pte2p, PTE2_NM | PTE2_RO);
5738 pmap_tlb_flush(pmap, va);
5745 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5748 pte1p = pmap_pte1(pmap, pv->pv_va);
5749 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found"
5750 " a section in page %p's pv list", __func__, m));
5751 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5752 if (pte2_is_dirty(pte2_load(pte2p))) {
5753 pte2_set_bit(pte2p, PTE2_NM);
5754 pmap_tlb_flush(pmap, pv->pv_va);
5759 rw_wunlock(&pvh_global_lock);
5764 * Sets the memory attribute for the specified page.
5767 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5769 pt2_entry_t *cmap2_pte2p;
5774 oma = m->md.pat_mode;
5775 m->md.pat_mode = ma;
5777 CTR5(KTR_PMAP, "%s: page %p - 0x%08X oma: %d, ma: %d", __func__, m,
5778 VM_PAGE_TO_PHYS(m), oma, ma);
5779 if ((m->flags & PG_FICTITIOUS) != 0)
5783 * If "m" is a normal page, flush it from the cache.
5785 * First, try to find an existing mapping of the page by sf
5786 * buffer. sf_buf_invalidate_cache() modifies mapping and
5787 * flushes the cache.
5789 if (sf_buf_invalidate_cache(m, oma))
5793 * If page is not mapped by sf buffer, map the page
5794 * transient and do invalidation.
5797 pa = VM_PAGE_TO_PHYS(m);
5800 cmap2_pte2p = pc->pc_cmap2_pte2p;
5801 mtx_lock(&pc->pc_cmap_lock);
5802 if (pte2_load(cmap2_pte2p) != 0)
5803 panic("%s: CMAP2 busy", __func__);
5804 pte2_store(cmap2_pte2p, PTE2_KERN_NG(pa, PTE2_AP_KRW,
5805 vm_memattr_to_pte2(ma)));
5806 dcache_wbinv_poc((vm_offset_t)pc->pc_cmap2_addr, pa, PAGE_SIZE);
5807 pte2_clear(cmap2_pte2p);
5808 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5810 mtx_unlock(&pc->pc_cmap_lock);
5815 * Miscellaneous support routines follow
5819 * Returns TRUE if the given page is mapped individually or as part of
5820 * a 1mpage. Otherwise, returns FALSE.
5823 pmap_page_is_mapped(vm_page_t m)
5827 if ((m->oflags & VPO_UNMANAGED) != 0)
5829 rw_wlock(&pvh_global_lock);
5830 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5831 ((m->flags & PG_FICTITIOUS) == 0 &&
5832 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
5833 rw_wunlock(&pvh_global_lock);
5838 * Returns true if the pmap's pv is one of the first
5839 * 16 pvs linked to from this page. This count may
5840 * be changed upwards or downwards in the future; it
5841 * is only necessary that true be returned for a small
5842 * subset of pmaps for proper page aging.
5845 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5847 struct md_page *pvh;
5852 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5853 ("%s: page %p is not managed", __func__, m));
5855 rw_wlock(&pvh_global_lock);
5856 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5857 if (PV_PMAP(pv) == pmap) {
5865 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5866 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5867 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5868 if (PV_PMAP(pv) == pmap) {
5877 rw_wunlock(&pvh_global_lock);
5882 * pmap_zero_page zeros the specified hardware page by mapping
5883 * the page into KVM and using bzero to clear its contents.
5886 pmap_zero_page(vm_page_t m)
5888 pt2_entry_t *cmap2_pte2p;
5893 cmap2_pte2p = pc->pc_cmap2_pte2p;
5894 mtx_lock(&pc->pc_cmap_lock);
5895 if (pte2_load(cmap2_pte2p) != 0)
5896 panic("%s: CMAP2 busy", __func__);
5897 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5898 vm_page_pte2_attr(m)));
5899 pagezero(pc->pc_cmap2_addr);
5900 pte2_clear(cmap2_pte2p);
5901 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5903 mtx_unlock(&pc->pc_cmap_lock);
5907 * pmap_zero_page_area zeros the specified hardware page by mapping
5908 * the page into KVM and using bzero to clear its contents.
5910 * off and size may not cover an area beyond a single hardware page.
5913 pmap_zero_page_area(vm_page_t m, int off, int size)
5915 pt2_entry_t *cmap2_pte2p;
5920 cmap2_pte2p = pc->pc_cmap2_pte2p;
5921 mtx_lock(&pc->pc_cmap_lock);
5922 if (pte2_load(cmap2_pte2p) != 0)
5923 panic("%s: CMAP2 busy", __func__);
5924 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5925 vm_page_pte2_attr(m)));
5926 if (off == 0 && size == PAGE_SIZE)
5927 pagezero(pc->pc_cmap2_addr);
5929 bzero(pc->pc_cmap2_addr + off, size);
5930 pte2_clear(cmap2_pte2p);
5931 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5933 mtx_unlock(&pc->pc_cmap_lock);
5937 * pmap_copy_page copies the specified (machine independent)
5938 * page by mapping the page into virtual memory and using
5939 * bcopy to copy the page, one machine dependent page at a
5943 pmap_copy_page(vm_page_t src, vm_page_t dst)
5945 pt2_entry_t *cmap1_pte2p, *cmap2_pte2p;
5950 cmap1_pte2p = pc->pc_cmap1_pte2p;
5951 cmap2_pte2p = pc->pc_cmap2_pte2p;
5952 mtx_lock(&pc->pc_cmap_lock);
5953 if (pte2_load(cmap1_pte2p) != 0)
5954 panic("%s: CMAP1 busy", __func__);
5955 if (pte2_load(cmap2_pte2p) != 0)
5956 panic("%s: CMAP2 busy", __func__);
5957 pte2_store(cmap1_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(src),
5958 PTE2_AP_KR | PTE2_NM, vm_page_pte2_attr(src)));
5959 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(dst),
5960 PTE2_AP_KRW, vm_page_pte2_attr(dst)));
5961 bcopy(pc->pc_cmap1_addr, pc->pc_cmap2_addr, PAGE_SIZE);
5962 pte2_clear(cmap1_pte2p);
5963 tlb_flush((vm_offset_t)pc->pc_cmap1_addr);
5964 pte2_clear(cmap2_pte2p);
5965 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5967 mtx_unlock(&pc->pc_cmap_lock);
5970 int unmapped_buf_allowed = 1;
5973 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5974 vm_offset_t b_offset, int xfersize)
5976 pt2_entry_t *cmap1_pte2p, *cmap2_pte2p;
5977 vm_page_t a_pg, b_pg;
5979 vm_offset_t a_pg_offset, b_pg_offset;
5985 cmap1_pte2p = pc->pc_cmap1_pte2p;
5986 cmap2_pte2p = pc->pc_cmap2_pte2p;
5987 mtx_lock(&pc->pc_cmap_lock);
5988 if (pte2_load(cmap1_pte2p) != 0)
5989 panic("pmap_copy_pages: CMAP1 busy");
5990 if (pte2_load(cmap2_pte2p) != 0)
5991 panic("pmap_copy_pages: CMAP2 busy");
5992 while (xfersize > 0) {
5993 a_pg = ma[a_offset >> PAGE_SHIFT];
5994 a_pg_offset = a_offset & PAGE_MASK;
5995 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5996 b_pg = mb[b_offset >> PAGE_SHIFT];
5997 b_pg_offset = b_offset & PAGE_MASK;
5998 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5999 pte2_store(cmap1_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(a_pg),
6000 PTE2_AP_KR | PTE2_NM, vm_page_pte2_attr(a_pg)));
6001 tlb_flush_local((vm_offset_t)pc->pc_cmap1_addr);
6002 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(b_pg),
6003 PTE2_AP_KRW, vm_page_pte2_attr(b_pg)));
6004 tlb_flush_local((vm_offset_t)pc->pc_cmap2_addr);
6005 a_cp = pc->pc_cmap1_addr + a_pg_offset;
6006 b_cp = pc->pc_cmap2_addr + b_pg_offset;
6007 bcopy(a_cp, b_cp, cnt);
6012 pte2_clear(cmap1_pte2p);
6013 tlb_flush((vm_offset_t)pc->pc_cmap1_addr);
6014 pte2_clear(cmap2_pte2p);
6015 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
6017 mtx_unlock(&pc->pc_cmap_lock);
6021 pmap_quick_enter_page(vm_page_t m)
6028 pte2p = pc->pc_qmap_pte2p;
6030 KASSERT(pte2_load(pte2p) == 0, ("%s: PTE2 busy", __func__));
6032 pte2_store(pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
6033 vm_page_pte2_attr(m)));
6034 return (pc->pc_qmap_addr);
6038 pmap_quick_remove_page(vm_offset_t addr)
6044 pte2p = pc->pc_qmap_pte2p;
6046 KASSERT(addr == pc->pc_qmap_addr, ("%s: invalid address", __func__));
6047 KASSERT(pte2_load(pte2p) != 0, ("%s: PTE2 not in use", __func__));
6050 tlb_flush(pc->pc_qmap_addr);
6055 * Copy the range specified by src_addr/len
6056 * from the source map to the range dst_addr/len
6057 * in the destination map.
6059 * This routine is only advisory and need not do anything.
6062 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
6063 vm_offset_t src_addr)
6065 struct spglist free;
6067 vm_offset_t end_addr = src_addr + len;
6070 if (dst_addr != src_addr)
6073 if (!pmap_is_current(src_pmap))
6076 rw_wlock(&pvh_global_lock);
6077 if (dst_pmap < src_pmap) {
6078 PMAP_LOCK(dst_pmap);
6079 PMAP_LOCK(src_pmap);
6081 PMAP_LOCK(src_pmap);
6082 PMAP_LOCK(dst_pmap);
6085 for (addr = src_addr; addr < end_addr; addr = nextva) {
6086 pt2_entry_t *src_pte2p, *dst_pte2p;
6087 vm_page_t dst_mpt2pg, src_mpt2pg;
6088 pt1_entry_t src_pte1;
6091 KASSERT(addr < VM_MAXUSER_ADDRESS,
6092 ("%s: invalid to pmap_copy page tables", __func__));
6094 nextva = pte1_trunc(addr + PTE1_SIZE);
6098 pte1_idx = pte1_index(addr);
6099 src_pte1 = src_pmap->pm_pt1[pte1_idx];
6100 if (pte1_is_section(src_pte1)) {
6101 if ((addr & PTE1_OFFSET) != 0 ||
6102 (addr + PTE1_SIZE) > end_addr)
6104 if (dst_pmap->pm_pt1[pte1_idx] == 0 &&
6105 (!pte1_is_managed(src_pte1) ||
6106 pmap_pv_insert_pte1(dst_pmap, addr, src_pte1,
6107 PMAP_ENTER_NORECLAIM))) {
6108 dst_pmap->pm_pt1[pte1_idx] = src_pte1 &
6110 dst_pmap->pm_stats.resident_count +=
6111 PTE1_SIZE / PAGE_SIZE;
6112 pmap_pte1_mappings++;
6115 } else if (!pte1_is_link(src_pte1))
6118 src_mpt2pg = PHYS_TO_VM_PAGE(pte1_link_pa(src_pte1));
6121 * We leave PT2s to be linked from PT1 even if they are not
6122 * referenced until all PT2s in a page are without reference.
6124 * QQQ: It could be changed ...
6126 #if 0 /* single_pt2_link_is_cleared */
6127 KASSERT(pt2_wirecount_get(src_mpt2pg, pte1_idx) > 0,
6128 ("%s: source page table page is unused", __func__));
6130 if (pt2_wirecount_get(src_mpt2pg, pte1_idx) == 0)
6133 if (nextva > end_addr)
6136 src_pte2p = pt2map_entry(addr);
6137 while (addr < nextva) {
6138 pt2_entry_t temp_pte2;
6139 temp_pte2 = pte2_load(src_pte2p);
6141 * we only virtual copy managed pages
6143 if (pte2_is_managed(temp_pte2)) {
6144 dst_mpt2pg = pmap_allocpte2(dst_pmap, addr,
6145 PMAP_ENTER_NOSLEEP);
6146 if (dst_mpt2pg == NULL)
6148 dst_pte2p = pmap_pte2_quick(dst_pmap, addr);
6149 if (!pte2_is_valid(pte2_load(dst_pte2p)) &&
6150 pmap_try_insert_pv_entry(dst_pmap, addr,
6151 PHYS_TO_VM_PAGE(pte2_pa(temp_pte2)))) {
6153 * Clear the wired, modified, and
6154 * accessed (referenced) bits
6157 temp_pte2 &= ~(PTE2_W | PTE2_A);
6158 temp_pte2 |= PTE2_NM;
6159 pte2_store(dst_pte2p, temp_pte2);
6160 dst_pmap->pm_stats.resident_count++;
6163 if (pmap_unwire_pt2(dst_pmap, addr,
6164 dst_mpt2pg, &free)) {
6165 pmap_tlb_flush(dst_pmap, addr);
6166 vm_page_free_pages_toq(&free,
6171 if (pt2_wirecount_get(dst_mpt2pg, pte1_idx) >=
6172 pt2_wirecount_get(src_mpt2pg, pte1_idx))
6181 rw_wunlock(&pvh_global_lock);
6182 PMAP_UNLOCK(src_pmap);
6183 PMAP_UNLOCK(dst_pmap);
6187 * Increase the starting virtual address of the given mapping if a
6188 * different alignment might result in more section mappings.
6191 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6192 vm_offset_t *addr, vm_size_t size)
6194 vm_offset_t pte1_offset;
6196 if (size < PTE1_SIZE)
6198 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6199 offset += ptoa(object->pg_color);
6200 pte1_offset = offset & PTE1_OFFSET;
6201 if (size - ((PTE1_SIZE - pte1_offset) & PTE1_OFFSET) < PTE1_SIZE ||
6202 (*addr & PTE1_OFFSET) == pte1_offset)
6204 if ((*addr & PTE1_OFFSET) < pte1_offset)
6205 *addr = pte1_trunc(*addr) + pte1_offset;
6207 *addr = pte1_roundup(*addr) + pte1_offset;
6211 pmap_activate(struct thread *td)
6213 pmap_t pmap, oldpmap;
6216 PDEBUG(9, printf("%s: td = %08x\n", __func__, (uint32_t)td));
6219 pmap = vmspace_pmap(td->td_proc->p_vmspace);
6220 oldpmap = PCPU_GET(curpmap);
6221 cpuid = PCPU_GET(cpuid);
6224 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
6225 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
6227 CPU_CLR(cpuid, &oldpmap->pm_active);
6228 CPU_SET(cpuid, &pmap->pm_active);
6231 ttb = pmap_ttb_get(pmap);
6234 * pmap_activate is for the current thread on the current cpu
6236 td->td_pcb->pcb_pagedir = ttb;
6238 PCPU_SET(curpmap, pmap);
6243 * Perform the pmap work for mincore.
6246 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
6248 pt1_entry_t *pte1p, pte1;
6249 pt2_entry_t *pte2p, pte2;
6256 pte1p = pmap_pte1(pmap, addr);
6257 pte1 = pte1_load(pte1p);
6258 if (pte1_is_section(pte1)) {
6259 pa = trunc_page(pte1_pa(pte1) | (addr & PTE1_OFFSET));
6260 managed = pte1_is_managed(pte1);
6261 val = MINCORE_SUPER | MINCORE_INCORE;
6262 if (pte1_is_dirty(pte1))
6263 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6265 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6266 } else if (pte1_is_link(pte1)) {
6267 pte2p = pmap_pte2(pmap, addr);
6268 pte2 = pte2_load(pte2p);
6269 pmap_pte2_release(pte2p);
6271 managed = pte2_is_managed(pte2);
6272 val = MINCORE_INCORE;
6273 if (pte2_is_dirty(pte2))
6274 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6276 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6281 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
6282 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
6283 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
6284 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
6287 PA_UNLOCK_COND(*locked_pa);
6293 pmap_kenter_device(vm_offset_t va, vm_size_t size, vm_paddr_t pa)
6298 KASSERT((size & PAGE_MASK) == 0,
6299 ("%s: device mapping not page-sized", __func__));
6302 l2attr = vm_memattr_to_pte2(VM_MEMATTR_DEVICE);
6304 pmap_kenter_prot_attr(va, pa, PTE2_AP_KRW, l2attr);
6309 tlb_flush_range(sva, va - sva);
6313 pmap_kremove_device(vm_offset_t va, vm_size_t size)
6317 KASSERT((size & PAGE_MASK) == 0,
6318 ("%s: device mapping not page-sized", __func__));
6326 tlb_flush_range(sva, va - sva);
6330 pmap_set_pcb_pagedir(pmap_t pmap, struct pcb *pcb)
6333 pcb->pcb_pagedir = pmap_ttb_get(pmap);
6338 * Clean L1 data cache range by physical address.
6339 * The range must be within a single page.
6342 pmap_dcache_wb_pou(vm_paddr_t pa, vm_size_t size, uint32_t attr)
6344 pt2_entry_t *cmap2_pte2p;
6347 KASSERT(((pa & PAGE_MASK) + size) <= PAGE_SIZE,
6348 ("%s: not on single page", __func__));
6352 cmap2_pte2p = pc->pc_cmap2_pte2p;
6353 mtx_lock(&pc->pc_cmap_lock);
6354 if (pte2_load(cmap2_pte2p) != 0)
6355 panic("%s: CMAP2 busy", __func__);
6356 pte2_store(cmap2_pte2p, PTE2_KERN_NG(pa, PTE2_AP_KRW, attr));
6357 dcache_wb_pou((vm_offset_t)pc->pc_cmap2_addr + (pa & PAGE_MASK), size);
6358 pte2_clear(cmap2_pte2p);
6359 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
6361 mtx_unlock(&pc->pc_cmap_lock);
6365 * Sync instruction cache range which is not mapped yet.
6368 cache_icache_sync_fresh(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
6370 uint32_t len, offset;
6373 /* Write back d-cache on given address range. */
6374 offset = pa & PAGE_MASK;
6375 for ( ; size != 0; size -= len, pa += len, offset = 0) {
6376 len = min(PAGE_SIZE - offset, size);
6377 m = PHYS_TO_VM_PAGE(pa);
6378 KASSERT(m != NULL, ("%s: vm_page_t is null for %#x",
6380 pmap_dcache_wb_pou(pa, len, vm_page_pte2_attr(m));
6383 * I-cache is VIPT. Only way how to flush all virtual mappings
6384 * on given physical address is to invalidate all i-cache.
6390 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t size)
6393 /* Write back d-cache on given address range. */
6394 if (va >= VM_MIN_KERNEL_ADDRESS) {
6395 dcache_wb_pou(va, size);
6397 uint32_t len, offset;
6401 offset = va & PAGE_MASK;
6402 for ( ; size != 0; size -= len, va += len, offset = 0) {
6403 pa = pmap_extract(pmap, va); /* offset is preserved */
6404 len = min(PAGE_SIZE - offset, size);
6405 m = PHYS_TO_VM_PAGE(pa);
6406 KASSERT(m != NULL, ("%s: vm_page_t is null for %#x",
6408 pmap_dcache_wb_pou(pa, len, vm_page_pte2_attr(m));
6412 * I-cache is VIPT. Only way how to flush all virtual mappings
6413 * on given physical address is to invalidate all i-cache.
6419 * The implementation of pmap_fault() uses IN_RANGE2() macro which
6420 * depends on the fact that given range size is a power of 2.
6422 CTASSERT(powerof2(NB_IN_PT1));
6423 CTASSERT(powerof2(PT2MAP_SIZE));
6425 #define IN_RANGE2(addr, start, size) \
6426 ((vm_offset_t)(start) == ((vm_offset_t)(addr) & ~((size) - 1)))
6429 * Handle access and R/W emulation faults.
6432 pmap_fault(pmap_t pmap, vm_offset_t far, uint32_t fsr, int idx, bool usermode)
6434 pt1_entry_t *pte1p, pte1;
6435 pt2_entry_t *pte2p, pte2;
6441 * In kernel, we should never get abort with FAR which is in range of
6442 * pmap->pm_pt1 or PT2MAP address spaces. If it happens, stop here
6443 * and print out a useful abort message and even get to the debugger
6444 * otherwise it likely ends with never ending loop of aborts.
6446 if (__predict_false(IN_RANGE2(far, pmap->pm_pt1, NB_IN_PT1))) {
6448 * All L1 tables should always be mapped and present.
6449 * However, we check only current one herein. For user mode,
6450 * only permission abort from malicious user is not fatal.
6451 * And alignment abort as it may have higher priority.
6453 if (!usermode || (idx != FAULT_ALIGN && idx != FAULT_PERM_L2)) {
6454 CTR4(KTR_PMAP, "%s: pmap %#x pm_pt1 %#x far %#x",
6455 __func__, pmap, pmap->pm_pt1, far);
6456 panic("%s: pm_pt1 abort", __func__);
6458 return (KERN_INVALID_ADDRESS);
6460 if (__predict_false(IN_RANGE2(far, PT2MAP, PT2MAP_SIZE))) {
6462 * PT2MAP should be always mapped and present in current
6463 * L1 table. However, only existing L2 tables are mapped
6464 * in PT2MAP. For user mode, only L2 translation abort and
6465 * permission abort from malicious user is not fatal.
6466 * And alignment abort as it may have higher priority.
6468 if (!usermode || (idx != FAULT_ALIGN &&
6469 idx != FAULT_TRAN_L2 && idx != FAULT_PERM_L2)) {
6470 CTR4(KTR_PMAP, "%s: pmap %#x PT2MAP %#x far %#x",
6471 __func__, pmap, PT2MAP, far);
6472 panic("%s: PT2MAP abort", __func__);
6474 return (KERN_INVALID_ADDRESS);
6478 * A pmap lock is used below for handling of access and R/W emulation
6479 * aborts. They were handled by atomic operations before so some
6480 * analysis of new situation is needed to answer the following question:
6481 * Is it safe to use the lock even for these aborts?
6483 * There may happen two cases in general:
6485 * (1) Aborts while the pmap lock is locked already - this should not
6486 * happen as pmap lock is not recursive. However, under pmap lock only
6487 * internal kernel data should be accessed and such data should be
6488 * mapped with A bit set and NM bit cleared. If double abort happens,
6489 * then a mapping of data which has caused it must be fixed. Further,
6490 * all new mappings are always made with A bit set and the bit can be
6491 * cleared only on managed mappings.
6493 * (2) Aborts while another lock(s) is/are locked - this already can
6494 * happen. However, there is no difference here if it's either access or
6495 * R/W emulation abort, or if it's some other abort.
6500 pte1 = pte1_load(pmap_pte1(pmap, far));
6501 if (pte1_is_link(pte1)) {
6503 * Check in advance that associated L2 page table is mapped into
6504 * PT2MAP space. Note that faulty access to not mapped L2 page
6505 * table is caught in more general check above where "far" is
6506 * checked that it does not lay in PT2MAP space. Note also that
6507 * L1 page table and PT2TAB always exist and are mapped.
6509 pte2 = pt2tab_load(pmap_pt2tab_entry(pmap, far));
6510 if (!pte2_is_valid(pte2))
6511 panic("%s: missing L2 page table (%p, %#x)",
6512 __func__, pmap, far);
6517 * Special treatment is due to break-before-make approach done when
6518 * pte1 is updated for userland mapping during section promotion or
6519 * demotion. If not caught here, pmap_enter() can find a section
6520 * mapping on faulting address. That is not allowed.
6522 if (idx == FAULT_TRAN_L1 && usermode && cp15_ats1cur_check(far) == 0) {
6524 return (KERN_SUCCESS);
6528 * Accesss bits for page and section. Note that the entry
6529 * is not in TLB yet, so TLB flush is not necessary.
6531 * QQQ: This is hardware emulation, we do not call userret()
6532 * for aborts from user mode.
6534 if (idx == FAULT_ACCESS_L2) {
6535 pte1 = pte1_load(pmap_pte1(pmap, far));
6536 if (pte1_is_link(pte1)) {
6537 /* L2 page table should exist and be mapped. */
6538 pte2p = pt2map_entry(far);
6539 pte2 = pte2_load(pte2p);
6540 if (pte2_is_valid(pte2)) {
6541 pte2_store(pte2p, pte2 | PTE2_A);
6543 return (KERN_SUCCESS);
6547 * We got L2 access fault but PTE1 is not a link.
6548 * Probably some race happened, do nothing.
6550 CTR3(KTR_PMAP, "%s: FAULT_ACCESS_L2 - pmap %#x far %#x",
6551 __func__, pmap, far);
6553 return (KERN_SUCCESS);
6556 if (idx == FAULT_ACCESS_L1) {
6557 pte1p = pmap_pte1(pmap, far);
6558 pte1 = pte1_load(pte1p);
6559 if (pte1_is_section(pte1)) {
6560 pte1_store(pte1p, pte1 | PTE1_A);
6562 return (KERN_SUCCESS);
6565 * We got L1 access fault but PTE1 is not section
6566 * mapping. Probably some race happened, do nothing.
6568 CTR3(KTR_PMAP, "%s: FAULT_ACCESS_L1 - pmap %#x far %#x",
6569 __func__, pmap, far);
6571 return (KERN_SUCCESS);
6576 * Handle modify bits for page and section. Note that the modify
6577 * bit is emulated by software. So PTEx_RO is software read only
6578 * bit and PTEx_NM flag is real hardware read only bit.
6580 * QQQ: This is hardware emulation, we do not call userret()
6581 * for aborts from user mode.
6583 if ((fsr & FSR_WNR) && (idx == FAULT_PERM_L2)) {
6584 pte1 = pte1_load(pmap_pte1(pmap, far));
6585 if (pte1_is_link(pte1)) {
6586 /* L2 page table should exist and be mapped. */
6587 pte2p = pt2map_entry(far);
6588 pte2 = pte2_load(pte2p);
6589 if (pte2_is_valid(pte2) && !(pte2 & PTE2_RO) &&
6591 pte2_store(pte2p, pte2 & ~PTE2_NM);
6592 tlb_flush(trunc_page(far));
6594 return (KERN_SUCCESS);
6598 * We got L2 permission fault but PTE1 is not a link.
6599 * Probably some race happened, do nothing.
6601 CTR3(KTR_PMAP, "%s: FAULT_PERM_L2 - pmap %#x far %#x",
6602 __func__, pmap, far);
6604 return (KERN_SUCCESS);
6607 if ((fsr & FSR_WNR) && (idx == FAULT_PERM_L1)) {
6608 pte1p = pmap_pte1(pmap, far);
6609 pte1 = pte1_load(pte1p);
6610 if (pte1_is_section(pte1)) {
6611 if (!(pte1 & PTE1_RO) && (pte1 & PTE1_NM)) {
6612 pte1_store(pte1p, pte1 & ~PTE1_NM);
6613 tlb_flush(pte1_trunc(far));
6615 return (KERN_SUCCESS);
6619 * We got L1 permission fault but PTE1 is not section
6620 * mapping. Probably some race happened, do nothing.
6622 CTR3(KTR_PMAP, "%s: FAULT_PERM_L1 - pmap %#x far %#x",
6623 __func__, pmap, far);
6625 return (KERN_SUCCESS);
6630 * QQQ: The previous code, mainly fast handling of access and
6631 * modify bits aborts, could be moved to ASM. Now we are
6632 * starting to deal with not fast aborts.
6635 return (KERN_FAILURE);
6638 #if defined(PMAP_DEBUG)
6640 * Reusing of KVA used in pmap_zero_page function !!!
6643 pmap_zero_page_check(vm_page_t m)
6645 pt2_entry_t *cmap2_pte2p;
6651 cmap2_pte2p = pc->pc_cmap2_pte2p;
6652 mtx_lock(&pc->pc_cmap_lock);
6653 if (pte2_load(cmap2_pte2p) != 0)
6654 panic("%s: CMAP2 busy", __func__);
6655 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
6656 vm_page_pte2_attr(m)));
6657 end = (uint32_t*)(pc->pc_cmap2_addr + PAGE_SIZE);
6658 for (p = (uint32_t*)pc->pc_cmap2_addr; p < end; p++)
6660 panic("%s: page %p not zero, va: %p", __func__, m,
6662 pte2_clear(cmap2_pte2p);
6663 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
6665 mtx_unlock(&pc->pc_cmap_lock);
6669 pmap_pid_dump(int pid)
6676 sx_slock(&allproc_lock);
6677 FOREACH_PROC_IN_SYSTEM(p) {
6678 if (p->p_pid != pid || p->p_vmspace == NULL)
6681 pmap = vmspace_pmap(p->p_vmspace);
6682 for (i = 0; i < NPTE1_IN_PT1; i++) {
6684 pt2_entry_t *pte2p, pte2;
6685 vm_offset_t base, va;
6689 base = i << PTE1_SHIFT;
6690 pte1 = pte1_load(&pmap->pm_pt1[i]);
6692 if (pte1_is_section(pte1)) {
6694 * QQQ: Do something here!
6696 } else if (pte1_is_link(pte1)) {
6697 for (j = 0; j < NPTE2_IN_PT2; j++) {
6698 va = base + (j << PAGE_SHIFT);
6699 if (va >= VM_MIN_KERNEL_ADDRESS) {
6704 sx_sunlock(&allproc_lock);
6707 pte2p = pmap_pte2(pmap, va);
6708 pte2 = pte2_load(pte2p);
6709 pmap_pte2_release(pte2p);
6710 if (!pte2_is_valid(pte2))
6714 m = PHYS_TO_VM_PAGE(pa);
6715 printf("va: 0x%x, pa: 0x%x, h: %d, w:"
6716 " %d, f: 0x%x", va, pa,
6717 m->hold_count, m->wire_count,
6731 sx_sunlock(&allproc_lock);
6738 static pt2_entry_t *
6739 pmap_pte2_ddb(pmap_t pmap, vm_offset_t va)
6742 vm_paddr_t pt2pg_pa;
6744 pte1 = pte1_load(pmap_pte1(pmap, va));
6745 if (!pte1_is_link(pte1))
6748 if (pmap_is_current(pmap))
6749 return (pt2map_entry(va));
6751 /* Note that L2 page table size is not equal to PAGE_SIZE. */
6752 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
6753 if (pte2_pa(pte2_load(PMAP3)) != pt2pg_pa) {
6754 pte2_store(PMAP3, PTE2_KPT(pt2pg_pa));
6756 PMAP3cpu = PCPU_GET(cpuid);
6758 tlb_flush_local((vm_offset_t)PADDR3);
6761 else if (PMAP3cpu != PCPU_GET(cpuid)) {
6762 PMAP3cpu = PCPU_GET(cpuid);
6763 tlb_flush_local((vm_offset_t)PADDR3);
6766 return (PADDR3 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
6770 dump_pmap(pmap_t pmap)
6773 printf("pmap %p\n", pmap);
6774 printf(" pm_pt1: %p\n", pmap->pm_pt1);
6775 printf(" pm_pt2tab: %p\n", pmap->pm_pt2tab);
6776 printf(" pm_active: 0x%08lX\n", pmap->pm_active.__bits[0]);
6779 DB_SHOW_COMMAND(pmaps, pmap_list_pmaps)
6783 LIST_FOREACH(pmap, &allpmaps, pm_list) {
6789 pte2_class(pt2_entry_t pte2)
6793 cls = (pte2 >> 2) & 0x03;
6794 cls |= (pte2 >> 4) & 0x04;
6799 dump_section(pmap_t pmap, uint32_t pte1_idx)
6804 dump_link(pmap_t pmap, uint32_t pte1_idx, boolean_t invalid_ok)
6808 pt2_entry_t *pte2p, pte2;
6811 va = pte1_idx << PTE1_SHIFT;
6812 pte2p = pmap_pte2_ddb(pmap, va);
6813 for (i = 0; i < NPTE2_IN_PT2; i++, pte2p++, va += PAGE_SIZE) {
6814 pte2 = pte2_load(pte2p);
6817 if (!pte2_is_valid(pte2)) {
6818 printf(" 0x%08X: 0x%08X", va, pte2);
6820 printf(" - not valid !!!");
6824 m = PHYS_TO_VM_PAGE(pte2_pa(pte2));
6825 printf(" 0x%08X: 0x%08X, TEX%d, s:%d, g:%d, m:%p", va , pte2,
6826 pte2_class(pte2), !!(pte2 & PTE2_S), !(pte2 & PTE2_NG), m);
6828 printf(" v:%d h:%d w:%d f:0x%04X\n", m->valid,
6829 m->hold_count, m->wire_count, m->flags);
6836 static __inline boolean_t
6837 is_pv_chunk_space(vm_offset_t va)
6840 if ((((vm_offset_t)pv_chunkbase) <= va) &&
6841 (va < ((vm_offset_t)pv_chunkbase + PAGE_SIZE * pv_maxchunks)))
6846 DB_SHOW_COMMAND(pmap, pmap_pmap_print)
6848 /* XXX convert args. */
6849 pmap_t pmap = (pmap_t)addr;
6852 vm_offset_t va, eva;
6855 boolean_t invalid_ok, dump_link_ok, dump_pv_chunk;
6860 LIST_FOREACH(pm, &allpmaps, pm_list)
6861 if (pm == pmap) break;
6863 printf("given pmap %p is not in allpmaps list\n", pmap);
6867 pmap = PCPU_GET(curpmap);
6869 eva = (modif[0] == 'u') ? VM_MAXUSER_ADDRESS : 0xFFFFFFFF;
6870 dump_pv_chunk = FALSE; /* XXX evaluate from modif[] */
6872 printf("pmap: 0x%08X\n", (uint32_t)pmap);
6873 printf("PT2MAP: 0x%08X\n", (uint32_t)PT2MAP);
6874 printf("pt2tab: 0x%08X\n", (uint32_t)pmap->pm_pt2tab);
6876 for(i = 0; i < NPTE1_IN_PT1; i++) {
6877 pte1 = pte1_load(&pmap->pm_pt1[i]);
6880 va = i << PTE1_SHIFT;
6884 if (pte1_is_section(pte1)) {
6885 printf("0x%08X: Section 0x%08X, s:%d g:%d\n", va, pte1,
6886 !!(pte1 & PTE1_S), !(pte1 & PTE1_NG));
6887 dump_section(pmap, i);
6888 } else if (pte1_is_link(pte1)) {
6889 dump_link_ok = TRUE;
6891 pte2 = pte2_load(pmap_pt2tab_entry(pmap, va));
6892 m = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
6893 printf("0x%08X: Link 0x%08X, pt2tab: 0x%08X m: %p",
6895 if (is_pv_chunk_space(va)) {
6896 printf(" - pv_chunk space");
6900 dump_link_ok = FALSE;
6903 printf(" w:%d w2:%u", m->wire_count,
6904 pt2_wirecount_get(m, pte1_index(va)));
6906 printf(" !!! pt2tab entry is ZERO");
6907 else if (pte2_pa(pte1) != pte2_pa(pte2))
6908 printf(" !!! pt2tab entry is DIFFERENT - m: %p",
6909 PHYS_TO_VM_PAGE(pte2_pa(pte2)));
6912 dump_link(pmap, i, invalid_ok);
6914 printf("0x%08X: Invalid entry 0x%08X\n", va, pte1);
6919 dump_pt2tab(pmap_t pmap)
6927 printf("PT2TAB:\n");
6928 for (i = 0; i < PT2TAB_ENTRIES; i++) {
6929 pte2 = pte2_load(&pmap->pm_pt2tab[i]);
6930 if (!pte2_is_valid(pte2))
6932 va = i << PT2TAB_SHIFT;
6934 m = PHYS_TO_VM_PAGE(pa);
6935 printf(" 0x%08X: 0x%08X, TEX%d, s:%d, m:%p", va, pte2,
6936 pte2_class(pte2), !!(pte2 & PTE2_S), m);
6938 printf(" , h: %d, w: %d, f: 0x%04X pidx: %lld",
6939 m->hold_count, m->wire_count, m->flags, m->pindex);
6944 DB_SHOW_COMMAND(pmap_pt2tab, pmap_pt2tab_print)
6946 /* XXX convert args. */
6947 pmap_t pmap = (pmap_t)addr;
6954 printf("supported only on current pmap\n");
6958 pmap = PCPU_GET(curpmap);
6959 printf("curpmap: 0x%08X\n", (uint32_t)pmap);
6960 printf("PT2MAP: 0x%08X\n", (uint32_t)PT2MAP);
6961 printf("pt2tab: 0x%08X\n", (uint32_t)pmap->pm_pt2tab);
6963 start = pte1_index((vm_offset_t)PT2MAP);
6964 for (i = start; i < (start + NPT2_IN_PT2TAB); i++) {
6965 pte1 = pte1_load(&pmap->pm_pt1[i]);
6968 va = i << PTE1_SHIFT;
6969 if (pte1_is_section(pte1)) {
6970 printf("0x%08X: Section 0x%08X, s:%d\n", va, pte1,
6972 dump_section(pmap, i);
6973 } else if (pte1_is_link(pte1)) {
6974 pte2 = pte2_load(pmap_pt2tab_entry(pmap, va));
6975 printf("0x%08X: Link 0x%08X, pt2tab: 0x%08X\n", va,
6978 printf(" !!! pt2tab entry is ZERO\n");
6980 printf("0x%08X: Invalid entry 0x%08X\n", va, pte1);