2 * Copyright (c) 1991 Regents of the University of California.
3 * Copyright (c) 1994 John S. Dyson
4 * Copyright (c) 1994 David Greenman
5 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
6 * Copyright (c) 2014-2016 Svatopluk Kraus <skra@FreeBSD.org>
7 * Copyright (c) 2014-2016 Michal Meloun <mmel@FreeBSD.org>
10 * This code is derived from software contributed to Berkeley by
11 * the Systems Programming Group of the University of Utah Computer
12 * Science Department and William Jolitz of UUNET Technologies Inc.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
41 * Copyright (c) 2003 Networks Associates Technology, Inc.
42 * All rights reserved.
44 * This software was developed for the FreeBSD Project by Jake Burkholder,
45 * Safeport Network Services, and Network Associates Laboratories, the
46 * Security Research Division of Network Associates, Inc. under
47 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
48 * CHATS research program.
50 * Redistribution and use in source and binary forms, with or without
51 * modification, are permitted provided that the following conditions
53 * 1. Redistributions of source code must retain the above copyright
54 * notice, this list of conditions and the following disclaimer.
55 * 2. Redistributions in binary form must reproduce the above copyright
56 * notice, this list of conditions and the following disclaimer in the
57 * documentation and/or other materials provided with the distribution.
59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
62 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
72 #include <sys/cdefs.h>
73 __FBSDID("$FreeBSD$");
76 * Manages physical address maps.
78 * Since the information managed by this module is
79 * also stored by the logical address mapping module,
80 * this module may throw away valid virtual-to-physical
81 * mappings at almost any time. However, invalidations
82 * of virtual-to-physical mappings must be done as
85 * In order to cope with hardware architectures which
86 * make virtual-to-physical map invalidates expensive,
87 * this module may delay invalidate or reduced protection
88 * operations until such time as they are actually
89 * necessary. This module is given full information as
90 * to which processors are currently using which maps,
91 * and to when physical maps must be made correct.
98 #include <sys/param.h>
99 #include <sys/systm.h>
100 #include <sys/kernel.h>
102 #include <sys/lock.h>
103 #include <sys/proc.h>
104 #include <sys/rwlock.h>
105 #include <sys/malloc.h>
106 #include <sys/vmmeter.h>
107 #include <sys/malloc.h>
108 #include <sys/mman.h>
109 #include <sys/sf_buf.h>
111 #include <sys/sched.h>
112 #include <sys/sysctl.h>
116 #include <sys/cpuset.h>
123 #include <machine/physmem.h>
124 #include <machine/vmparam.h>
129 #include <vm/vm_param.h>
130 #include <vm/vm_kern.h>
131 #include <vm/vm_object.h>
132 #include <vm/vm_map.h>
133 #include <vm/vm_page.h>
134 #include <vm/vm_pageout.h>
135 #include <vm/vm_phys.h>
136 #include <vm/vm_extern.h>
137 #include <vm/vm_reserv.h>
138 #include <sys/lock.h>
139 #include <sys/mutex.h>
141 #include <machine/md_var.h>
142 #include <machine/pmap_var.h>
143 #include <machine/cpu.h>
144 #include <machine/pcb.h>
145 #include <machine/sf_buf.h>
147 #include <machine/smp.h>
150 #ifndef PMAP_SHPGPERPROC
151 #define PMAP_SHPGPERPROC 200
155 #define PMAP_INLINE __inline
161 static void pmap_zero_page_check(vm_page_t m);
162 void pmap_debug(int level);
163 int pmap_pid_dump(int pid);
165 #define PDEBUG(_lev_,_stat_) \
166 if (pmap_debug_level >= (_lev_)) \
168 #define dprintf printf
169 int pmap_debug_level = 1;
170 #else /* PMAP_DEBUG */
171 #define PDEBUG(_lev_,_stat_) /* Nothing */
172 #define dprintf(x, arg...)
173 #endif /* PMAP_DEBUG */
176 * Level 2 page tables map definion ('max' is excluded).
179 #define PT2V_MIN_ADDRESS ((vm_offset_t)PT2MAP)
180 #define PT2V_MAX_ADDRESS ((vm_offset_t)PT2MAP + PT2MAP_SIZE)
182 #define UPT2V_MIN_ADDRESS ((vm_offset_t)PT2MAP)
183 #define UPT2V_MAX_ADDRESS \
184 ((vm_offset_t)(PT2MAP + (KERNBASE >> PT2MAP_SHIFT)))
187 * Promotion to a 1MB (PTE1) page mapping requires that the corresponding
188 * 4KB (PTE2) page mappings have identical settings for the following fields:
190 #define PTE2_PROMOTE (PTE2_V | PTE2_A | PTE2_NM | PTE2_S | PTE2_NG | \
191 PTE2_NX | PTE2_RO | PTE2_U | PTE2_W | \
194 #define PTE1_PROMOTE (PTE1_V | PTE1_A | PTE1_NM | PTE1_S | PTE1_NG | \
195 PTE1_NX | PTE1_RO | PTE1_U | PTE1_W | \
198 #define ATTR_TO_L1(l2_attr) ((((l2_attr) & L2_TEX0) ? L1_S_TEX0 : 0) | \
199 (((l2_attr) & L2_C) ? L1_S_C : 0) | \
200 (((l2_attr) & L2_B) ? L1_S_B : 0) | \
201 (((l2_attr) & PTE2_A) ? PTE1_A : 0) | \
202 (((l2_attr) & PTE2_NM) ? PTE1_NM : 0) | \
203 (((l2_attr) & PTE2_S) ? PTE1_S : 0) | \
204 (((l2_attr) & PTE2_NG) ? PTE1_NG : 0) | \
205 (((l2_attr) & PTE2_NX) ? PTE1_NX : 0) | \
206 (((l2_attr) & PTE2_RO) ? PTE1_RO : 0) | \
207 (((l2_attr) & PTE2_U) ? PTE1_U : 0) | \
208 (((l2_attr) & PTE2_W) ? PTE1_W : 0))
210 #define ATTR_TO_L2(l1_attr) ((((l1_attr) & L1_S_TEX0) ? L2_TEX0 : 0) | \
211 (((l1_attr) & L1_S_C) ? L2_C : 0) | \
212 (((l1_attr) & L1_S_B) ? L2_B : 0) | \
213 (((l1_attr) & PTE1_A) ? PTE2_A : 0) | \
214 (((l1_attr) & PTE1_NM) ? PTE2_NM : 0) | \
215 (((l1_attr) & PTE1_S) ? PTE2_S : 0) | \
216 (((l1_attr) & PTE1_NG) ? PTE2_NG : 0) | \
217 (((l1_attr) & PTE1_NX) ? PTE2_NX : 0) | \
218 (((l1_attr) & PTE1_RO) ? PTE2_RO : 0) | \
219 (((l1_attr) & PTE1_U) ? PTE2_U : 0) | \
220 (((l1_attr) & PTE1_W) ? PTE2_W : 0))
223 * PTE2 descriptors creation macros.
225 #define PTE2_ATTR_DEFAULT vm_memattr_to_pte2(VM_MEMATTR_DEFAULT)
226 #define PTE2_ATTR_PT vm_memattr_to_pte2(pt_memattr)
228 #define PTE2_KPT(pa) PTE2_KERN(pa, PTE2_AP_KRW, PTE2_ATTR_PT)
229 #define PTE2_KPT_NG(pa) PTE2_KERN_NG(pa, PTE2_AP_KRW, PTE2_ATTR_PT)
231 #define PTE2_KRW(pa) PTE2_KERN(pa, PTE2_AP_KRW, PTE2_ATTR_DEFAULT)
232 #define PTE2_KRO(pa) PTE2_KERN(pa, PTE2_AP_KR, PTE2_ATTR_DEFAULT)
236 #define PV_STAT(x) do { x ; } while (0)
238 #define PV_STAT(x) do { } while (0)
242 * The boot_pt1 is used temporary in very early boot stage as L1 page table.
243 * We can init many things with no memory allocation thanks to its static
244 * allocation and this brings two main advantages:
245 * (1) other cores can be started very simply,
246 * (2) various boot loaders can be supported as its arguments can be processed
247 * in virtual address space and can be moved to safe location before
248 * first allocation happened.
249 * Only disadvantage is that boot_pt1 is used only in very early boot stage.
250 * However, the table is uninitialized and so lays in bss. Therefore kernel
251 * image size is not influenced.
253 * QQQ: In the future, maybe, boot_pt1 can be used for soft reset and
254 * CPU suspend/resume game.
256 extern pt1_entry_t boot_pt1[];
259 pt1_entry_t *kern_pt1;
260 pt2_entry_t *kern_pt2tab;
263 static uint32_t ttb_flags;
264 static vm_memattr_t pt_memattr;
265 ttb_entry_t pmap_kern_ttb;
267 struct pmap kernel_pmap_store;
268 LIST_HEAD(pmaplist, pmap);
269 static struct pmaplist allpmaps;
270 static struct mtx allpmaps_lock;
272 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
273 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
275 static vm_offset_t kernel_vm_end_new;
276 vm_offset_t kernel_vm_end = KERNBASE + NKPT2PG * NPT2_IN_PG * PTE1_SIZE;
277 vm_offset_t vm_max_kernel_address;
278 vm_paddr_t kernel_l1pa;
280 static struct rwlock __aligned(CACHE_LINE_SIZE) pvh_global_lock;
283 * Data for the pv entry allocation mechanism
285 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
286 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
287 static struct md_page *pv_table; /* XXX: Is it used only the list in md_page? */
288 static int shpgperproc = PMAP_SHPGPERPROC;
290 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
291 int pv_maxchunks; /* How many chunks we have KVA for */
292 vm_offset_t pv_vafree; /* freelist stored in the PTE */
294 vm_paddr_t first_managed_pa;
295 #define pa_to_pvh(pa) (&pv_table[pte1_index(pa - first_managed_pa)])
298 * All those kernel PT submaps that BSD is so fond of
309 static struct sysmaps sysmaps_pcpu[MAXCPU];
310 static pt2_entry_t *CMAP3;
311 static caddr_t CADDR3;
314 struct msgbuf *msgbufp = 0; /* XXX move it to machdep.c */
319 static caddr_t crashdumpmap;
321 static pt2_entry_t *PMAP1 = 0, *PMAP2;
322 static pt2_entry_t *PADDR1 = 0, *PADDR2;
324 static pt2_entry_t *PMAP3;
325 static pt2_entry_t *PADDR3;
326 static int PMAP3cpu __unused; /* for SMP only */
330 static int PMAP1changedcpu;
331 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
333 "Number of times pmap_pte2_quick changed CPU with same PMAP1");
335 static int PMAP1changed;
336 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
338 "Number of times pmap_pte2_quick changed PMAP1");
339 static int PMAP1unchanged;
340 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
342 "Number of times pmap_pte2_quick didn't change PMAP1");
343 static struct mtx PMAP2mutex;
345 static __inline void pt2_wirecount_init(vm_page_t m);
346 static boolean_t pmap_demote_pte1(pmap_t pmap, pt1_entry_t *pte1p,
348 void cache_icache_sync_fresh(vm_offset_t va, vm_paddr_t pa, vm_size_t size);
351 * Function to set the debug level of the pmap code.
355 pmap_debug(int level)
358 pmap_debug_level = level;
359 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
361 #endif /* PMAP_DEBUG */
364 * This table must corespond with memory attribute configuration in vm.h.
365 * First entry is used for normal system mapping.
367 * Device memory is always marked as shared.
368 * Normal memory is shared only in SMP .
369 * Not outer shareable bits are not used yet.
370 * Class 6 cannot be used on ARM11.
372 #define TEXDEF_TYPE_SHIFT 0
373 #define TEXDEF_TYPE_MASK 0x3
374 #define TEXDEF_INNER_SHIFT 2
375 #define TEXDEF_INNER_MASK 0x3
376 #define TEXDEF_OUTER_SHIFT 4
377 #define TEXDEF_OUTER_MASK 0x3
378 #define TEXDEF_NOS_SHIFT 6
379 #define TEXDEF_NOS_MASK 0x1
381 #define TEX(t, i, o, s) \
382 ((t) << TEXDEF_TYPE_SHIFT) | \
383 ((i) << TEXDEF_INNER_SHIFT) | \
384 ((o) << TEXDEF_OUTER_SHIFT | \
385 ((s) << TEXDEF_NOS_SHIFT))
387 static uint32_t tex_class[8] = {
388 /* type inner cache outer cache */
389 TEX(PRRR_MEM, NMRR_WB_WA, NMRR_WB_WA, 0), /* 0 - ATTR_WB_WA */
390 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 1 - ATTR_NOCACHE */
391 TEX(PRRR_DEV, NMRR_NC, NMRR_NC, 0), /* 2 - ATTR_DEVICE */
392 TEX(PRRR_SO, NMRR_NC, NMRR_NC, 0), /* 3 - ATTR_SO */
393 TEX(PRRR_MEM, NMRR_WT, NMRR_WT, 0), /* 4 - ATTR_WT */
394 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 5 - NOT USED YET */
395 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 6 - NOT USED YET */
396 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 7 - NOT USED YET */
400 static uint32_t pte2_attr_tab[8] = {
401 PTE2_ATTR_WB_WA, /* 0 - VM_MEMATTR_WB_WA */
402 PTE2_ATTR_NOCACHE, /* 1 - VM_MEMATTR_NOCACHE */
403 PTE2_ATTR_DEVICE, /* 2 - VM_MEMATTR_DEVICE */
404 PTE2_ATTR_SO, /* 3 - VM_MEMATTR_SO */
405 PTE2_ATTR_WT, /* 4 - VM_MEMATTR_WRITE_THROUGH */
406 0, /* 5 - NOT USED YET */
407 0, /* 6 - NOT USED YET */
408 0 /* 7 - NOT USED YET */
410 CTASSERT(VM_MEMATTR_WB_WA == 0);
411 CTASSERT(VM_MEMATTR_NOCACHE == 1);
412 CTASSERT(VM_MEMATTR_DEVICE == 2);
413 CTASSERT(VM_MEMATTR_SO == 3);
414 CTASSERT(VM_MEMATTR_WRITE_THROUGH == 4);
416 static inline uint32_t
417 vm_memattr_to_pte2(vm_memattr_t ma)
420 KASSERT((u_int)ma < 5, ("%s: bad vm_memattr_t %d", __func__, ma));
421 return (pte2_attr_tab[(u_int)ma]);
424 static inline uint32_t
425 vm_page_pte2_attr(vm_page_t m)
428 return (vm_memattr_to_pte2(m->md.pat_mode));
432 * Convert TEX definition entry to TTB flags.
435 encode_ttb_flags(int idx)
437 uint32_t inner, outer, nos, reg;
439 inner = (tex_class[idx] >> TEXDEF_INNER_SHIFT) &
441 outer = (tex_class[idx] >> TEXDEF_OUTER_SHIFT) &
443 nos = (tex_class[idx] >> TEXDEF_NOS_SHIFT) &
448 if (cpuinfo.coherent_walk)
449 reg |= (inner & 0x1) << 6;
450 reg |= (inner & 0x2) >> 1;
458 * Set TEX remapping registers in current CPU.
464 uint32_t type, inner, outer, nos;
467 #ifdef PMAP_PTE_NOCACHE
469 if (cpuinfo.coherent_walk) {
470 pt_memattr = VM_MEMATTR_WB_WA;
471 ttb_flags = encode_ttb_flags(0);
474 pt_memattr = VM_MEMATTR_NOCACHE;
475 ttb_flags = encode_ttb_flags(1);
478 pt_memattr = VM_MEMATTR_WB_WA;
479 ttb_flags = encode_ttb_flags(0);
485 /* Build remapping register from TEX classes. */
486 for (i = 0; i < 8; i++) {
487 type = (tex_class[i] >> TEXDEF_TYPE_SHIFT) &
489 inner = (tex_class[i] >> TEXDEF_INNER_SHIFT) &
491 outer = (tex_class[i] >> TEXDEF_OUTER_SHIFT) &
493 nos = (tex_class[i] >> TEXDEF_NOS_SHIFT) &
496 prrr |= type << (i * 2);
497 prrr |= nos << (i + 24);
498 nmrr |= inner << (i * 2);
499 nmrr |= outer << (i * 2 + 16);
501 /* Add shareable bits for device memory. */
502 prrr |= PRRR_DS0 | PRRR_DS1;
504 /* Add shareable bits for normal memory in SMP case. */
511 /* Caches are disabled, so full TLB flush should be enough. */
512 tlb_flush_all_local();
516 * KERNBASE must be multiple of NPT2_IN_PG * PTE1_SIZE. In other words,
517 * KERNBASE is mapped by first L2 page table in L2 page table page. It
518 * meets same constrain due to PT2MAP being placed just under KERNBASE.
520 CTASSERT((KERNBASE & (NPT2_IN_PG * PTE1_SIZE - 1)) == 0);
521 CTASSERT((KERNBASE - VM_MAXUSER_ADDRESS) >= PT2MAP_SIZE);
524 * In crazy dreams, PAGE_SIZE could be a multiple of PTE2_SIZE in general.
525 * For now, anyhow, the following check must be fulfilled.
527 CTASSERT(PAGE_SIZE == PTE2_SIZE);
529 * We don't want to mess up MI code with all MMU and PMAP definitions,
530 * so some things, which depend on other ones, are defined independently.
531 * Now, it is time to check that we don't screw up something.
533 CTASSERT(PDRSHIFT == PTE1_SHIFT);
535 * Check L1 and L2 page table entries definitions consistency.
537 CTASSERT(NB_IN_PT1 == (sizeof(pt1_entry_t) * NPTE1_IN_PT1));
538 CTASSERT(NB_IN_PT2 == (sizeof(pt2_entry_t) * NPTE2_IN_PT2));
540 * Check L2 page tables page consistency.
542 CTASSERT(PAGE_SIZE == (NPT2_IN_PG * NB_IN_PT2));
543 CTASSERT((1 << PT2PG_SHIFT) == NPT2_IN_PG);
545 * Check PT2TAB consistency.
546 * PT2TAB_ENTRIES is defined as a division of NPTE1_IN_PT1 by NPT2_IN_PG.
547 * This should be done without remainder.
549 CTASSERT(NPTE1_IN_PT1 == (PT2TAB_ENTRIES * NPT2_IN_PG));
554 * All level 2 page tables (PT2s) are mapped continuously and accordingly
555 * into PT2MAP address space. As PT2 size is less than PAGE_SIZE, this can
556 * be done only if PAGE_SIZE is a multiple of PT2 size. All PT2s in one page
557 * must be used together, but not necessary at once. The first PT2 in a page
558 * must map things on correctly aligned address and the others must follow
561 #define NB_IN_PT2TAB (PT2TAB_ENTRIES * sizeof(pt2_entry_t))
562 #define NPT2_IN_PT2TAB (NB_IN_PT2TAB / NB_IN_PT2)
563 #define NPG_IN_PT2TAB (NB_IN_PT2TAB / PAGE_SIZE)
566 * Check PT2TAB consistency.
567 * NPT2_IN_PT2TAB is defined as a division of NB_IN_PT2TAB by NB_IN_PT2.
568 * NPG_IN_PT2TAB is defined as a division of NB_IN_PT2TAB by PAGE_SIZE.
569 * The both should be done without remainder.
571 CTASSERT(NB_IN_PT2TAB == (NPT2_IN_PT2TAB * NB_IN_PT2));
572 CTASSERT(NB_IN_PT2TAB == (NPG_IN_PT2TAB * PAGE_SIZE));
574 * The implementation was made general, however, with the assumption
575 * bellow in mind. In case of another value of NPG_IN_PT2TAB,
576 * the code should be once more rechecked.
578 CTASSERT(NPG_IN_PT2TAB == 1);
581 * Get offset of PT2 in a page
582 * associated with given PT1 index.
584 static __inline u_int
585 page_pt2off(u_int pt1_idx)
588 return ((pt1_idx & PT2PG_MASK) * NB_IN_PT2);
592 * Get physical address of PT2
593 * associated with given PT2s page and PT1 index.
595 static __inline vm_paddr_t
596 page_pt2pa(vm_paddr_t pgpa, u_int pt1_idx)
599 return (pgpa + page_pt2off(pt1_idx));
603 * Get first entry of PT2
604 * associated with given PT2s page and PT1 index.
606 static __inline pt2_entry_t *
607 page_pt2(vm_offset_t pgva, u_int pt1_idx)
610 return ((pt2_entry_t *)(pgva + page_pt2off(pt1_idx)));
614 * Get virtual address of PT2s page (mapped in PT2MAP)
615 * which holds PT2 which holds entry which maps given virtual address.
617 static __inline vm_offset_t
618 pt2map_pt2pg(vm_offset_t va)
621 va &= ~(NPT2_IN_PG * PTE1_SIZE - 1);
622 return ((vm_offset_t)pt2map_entry(va));
625 /*****************************************************************************
627 * THREE pmap initialization milestones exist:
630 * -> fundamental init (including MMU) in ASM
633 * -> fundamental init continues in C
634 * -> first available physical address is known
636 * pmap_bootstrap_prepare() -> FIRST PMAP MILESTONE (first epoch begins)
637 * -> basic (safe) interface for physical address allocation is made
638 * -> basic (safe) interface for virtual mapping is made
639 * -> limited not SMP coherent work is possible
641 * -> more fundamental init continues in C
642 * -> locks and some more things are available
643 * -> all fundamental allocations and mappings are done
645 * pmap_bootstrap() -> SECOND PMAP MILESTONE (second epoch begins)
646 * -> phys_avail[] and virtual_avail is set
647 * -> control is passed to vm subsystem
648 * -> physical and virtual address allocation are off limit
649 * -> low level mapping functions, some SMP coherent,
650 * are available, which cannot be used before vm subsystem
654 * -> vm subsystem is being inited
656 * pmap_init() -> THIRD PMAP MILESTONE (third epoch begins)
657 * -> pmap is fully inited
659 *****************************************************************************/
661 /*****************************************************************************
663 * PMAP first stage initialization and utility functions
664 * for pre-bootstrap epoch.
666 * After pmap_bootstrap_prepare() is called, the following functions
669 * (1) strictly only for this stage functions for physical page allocations,
670 * virtual space allocations, and mappings:
672 * vm_paddr_t pmap_preboot_get_pages(u_int num);
673 * void pmap_preboot_map_pages(vm_paddr_t pa, vm_offset_t va, u_int num);
674 * vm_offset_t pmap_preboot_reserve_pages(u_int num);
675 * vm_offset_t pmap_preboot_get_vpages(u_int num);
676 * void pmap_preboot_map_attr(vm_paddr_t pa, vm_offset_t va, vm_size_t size,
677 * vm_prot_t prot, vm_memattr_t attr);
679 * (2) for all stages:
681 * vm_paddr_t pmap_kextract(vm_offset_t va);
683 * NOTE: This is not SMP coherent stage.
685 *****************************************************************************/
687 #define KERNEL_P2V(pa) \
688 ((vm_offset_t)((pa) - arm_physmem_kernaddr + KERNVIRTADDR))
689 #define KERNEL_V2P(va) \
690 ((vm_paddr_t)((va) - KERNVIRTADDR + arm_physmem_kernaddr))
692 static vm_paddr_t last_paddr;
695 * Pre-bootstrap epoch page allocator.
698 pmap_preboot_get_pages(u_int num)
703 last_paddr += num * PAGE_SIZE;
709 * The fundamental initalization of PMAP stuff.
711 * Some things already happened in locore.S and some things could happen
712 * before pmap_bootstrap_prepare() is called, so let's recall what is done:
713 * 1. Caches are disabled.
714 * 2. We are running on virtual addresses already with 'boot_pt1'
716 * 3. So far, all virtual addresses can be converted to physical ones and
717 * vice versa by the following macros:
718 * KERNEL_P2V(pa) .... physical to virtual ones,
719 * KERNEL_V2P(va) .... virtual to physical ones.
721 * What is done herein:
722 * 1. The 'boot_pt1' is replaced by real kernel L1 page table 'kern_pt1'.
723 * 2. PT2MAP magic is brought to live.
724 * 3. Basic preboot functions for page allocations and mappings can be used.
725 * 4. Everything is prepared for L1 cache enabling.
728 * 1. To use second TTB register, so kernel and users page tables will be
729 * separated. This way process forking - pmap_pinit() - could be faster,
730 * it saves physical pages and KVA per a process, and it's simple change.
731 * However, it will lead, due to hardware matter, to the following:
732 * (a) 2G space for kernel and 2G space for users.
733 * (b) 1G space for kernel in low addresses and 3G for users above it.
734 * A question is: Is the case (b) really an option? Note that case (b)
735 * does save neither physical memory and KVA.
738 pmap_bootstrap_prepare(vm_paddr_t last)
740 vm_paddr_t pt2pg_pa, pt2tab_pa, pa, size;
741 vm_offset_t pt2pg_va;
745 uint32_t actlr_mask, actlr_set, l1_attr;
748 * Now, we are going to make real kernel mapping. Note that we are
749 * already running on some mapping made in locore.S and we expect
750 * that it's large enough to ensure nofault access to physical memory
751 * allocated herein before switch.
753 * As kernel image and everything needed before are and will be mapped
754 * by section mappings, we align last physical address to PTE1_SIZE.
756 last_paddr = pte1_roundup(last);
759 * Allocate and zero page(s) for kernel L1 page table.
761 * Note that it's first allocation on space which was PTE1_SIZE
762 * aligned and as such base_pt1 is aligned to NB_IN_PT1 too.
764 base_pt1 = pmap_preboot_get_pages(NPG_IN_PT1);
765 kern_pt1 = (pt1_entry_t *)KERNEL_P2V(base_pt1);
766 bzero((void*)kern_pt1, NB_IN_PT1);
767 pte1_sync_range(kern_pt1, NB_IN_PT1);
769 /* Allocate and zero page(s) for kernel PT2TAB. */
770 pt2tab_pa = pmap_preboot_get_pages(NPG_IN_PT2TAB);
771 kern_pt2tab = (pt2_entry_t *)KERNEL_P2V(pt2tab_pa);
772 bzero(kern_pt2tab, NB_IN_PT2TAB);
773 pte2_sync_range(kern_pt2tab, NB_IN_PT2TAB);
775 /* Allocate and zero page(s) for kernel L2 page tables. */
776 pt2pg_pa = pmap_preboot_get_pages(NKPT2PG);
777 pt2pg_va = KERNEL_P2V(pt2pg_pa);
778 size = NKPT2PG * PAGE_SIZE;
779 bzero((void*)pt2pg_va, size);
780 pte2_sync_range((pt2_entry_t *)pt2pg_va, size);
783 * Add a physical memory segment (vm_phys_seg) corresponding to the
784 * preallocated pages for kernel L2 page tables so that vm_page
785 * structures representing these pages will be created. The vm_page
786 * structures are required for promotion of the corresponding kernel
787 * virtual addresses to section mappings.
789 vm_phys_add_seg(pt2tab_pa, pmap_preboot_get_pages(0));
792 * Insert allocated L2 page table pages to PT2TAB and make
793 * link to all PT2s in L1 page table. See how kernel_vm_end
796 * We play simple and safe. So every KVA will have underlaying
797 * L2 page table, even kernel image mapped by sections.
799 pte2p = kern_pt2tab_entry(KERNBASE);
800 for (pa = pt2pg_pa; pa < pt2pg_pa + size; pa += PTE2_SIZE)
801 pt2tab_store(pte2p++, PTE2_KPT(pa));
803 pte1p = kern_pte1(KERNBASE);
804 for (pa = pt2pg_pa; pa < pt2pg_pa + size; pa += NB_IN_PT2)
805 pte1_store(pte1p++, PTE1_LINK(pa));
807 /* Make section mappings for kernel. */
808 l1_attr = ATTR_TO_L1(PTE2_ATTR_DEFAULT);
809 pte1p = kern_pte1(KERNBASE);
810 for (pa = KERNEL_V2P(KERNBASE); pa < last; pa += PTE1_SIZE)
811 pte1_store(pte1p++, PTE1_KERN(pa, PTE1_AP_KRW, l1_attr));
814 * Get free and aligned space for PT2MAP and make L1 page table links
815 * to L2 page tables held in PT2TAB.
817 * Note that pages holding PT2s are stored in PT2TAB as pt2_entry_t
818 * descriptors and PT2TAB page(s) itself is(are) used as PT2s. Thus
819 * each entry in PT2TAB maps all PT2s in a page. This implies that
820 * virtual address of PT2MAP must be aligned to NPT2_IN_PG * PTE1_SIZE.
822 PT2MAP = (pt2_entry_t *)(KERNBASE - PT2MAP_SIZE);
823 pte1p = kern_pte1((vm_offset_t)PT2MAP);
824 for (pa = pt2tab_pa, i = 0; i < NPT2_IN_PT2TAB; i++, pa += NB_IN_PT2) {
825 pte1_store(pte1p++, PTE1_LINK(pa));
829 * Store PT2TAB in PT2TAB itself, i.e. self reference mapping.
830 * Each pmap will hold own PT2TAB, so the mapping should be not global.
832 pte2p = kern_pt2tab_entry((vm_offset_t)PT2MAP);
833 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE) {
834 pt2tab_store(pte2p++, PTE2_KPT_NG(pa));
838 * Choose correct L2 page table and make mappings for allocations
839 * made herein which replaces temporary locore.S mappings after a while.
840 * Note that PT2MAP cannot be used until we switch to kern_pt1.
842 * Note, that these allocations started aligned on 1M section and
843 * kernel PT1 was allocated first. Making of mappings must follow
844 * order of physical allocations as we've used KERNEL_P2V() macro
845 * for virtual addresses resolution.
847 pte2p = kern_pt2tab_entry((vm_offset_t)kern_pt1);
848 pt2pg_va = KERNEL_P2V(pte2_pa(pte2_load(pte2p)));
850 pte2p = page_pt2(pt2pg_va, pte1_index((vm_offset_t)kern_pt1));
852 /* Make mapping for kernel L1 page table. */
853 for (pa = base_pt1, i = 0; i < NPG_IN_PT1; i++, pa += PTE2_SIZE)
854 pte2_store(pte2p++, PTE2_KPT(pa));
856 /* Make mapping for kernel PT2TAB. */
857 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE)
858 pte2_store(pte2p++, PTE2_KPT(pa));
860 /* Finally, switch from 'boot_pt1' to 'kern_pt1'. */
861 pmap_kern_ttb = base_pt1 | ttb_flags;
862 cpuinfo_get_actlr_modifier(&actlr_mask, &actlr_set);
863 reinit_mmu(pmap_kern_ttb, actlr_mask, actlr_set);
865 * Initialize the first available KVA. As kernel image is mapped by
866 * sections, we are leaving some gap behind.
868 virtual_avail = (vm_offset_t)kern_pt2tab + NPG_IN_PT2TAB * PAGE_SIZE;
872 * Setup L2 page table page for given KVA.
873 * Used in pre-bootstrap epoch.
875 * Note that we have allocated NKPT2PG pages for L2 page tables in advance
876 * and used them for mapping KVA starting from KERNBASE. However, this is not
877 * enough. Vectors and devices need L2 page tables too. Note that they are
878 * even above VM_MAX_KERNEL_ADDRESS.
880 static __inline vm_paddr_t
881 pmap_preboot_pt2pg_setup(vm_offset_t va)
883 pt2_entry_t *pte2p, pte2;
886 /* Get associated entry in PT2TAB. */
887 pte2p = kern_pt2tab_entry(va);
889 /* Just return, if PT2s page exists already. */
890 pte2 = pt2tab_load(pte2p);
891 if (pte2_is_valid(pte2))
892 return (pte2_pa(pte2));
894 KASSERT(va >= VM_MAX_KERNEL_ADDRESS,
895 ("%s: NKPT2PG too small", __func__));
898 * Allocate page for PT2s and insert it to PT2TAB.
899 * In other words, map it into PT2MAP space.
901 pt2pg_pa = pmap_preboot_get_pages(1);
902 pt2tab_store(pte2p, PTE2_KPT(pt2pg_pa));
904 /* Zero all PT2s in allocated page. */
905 bzero((void*)pt2map_pt2pg(va), PAGE_SIZE);
906 pte2_sync_range((pt2_entry_t *)pt2map_pt2pg(va), PAGE_SIZE);
912 * Setup L2 page table for given KVA.
913 * Used in pre-bootstrap epoch.
916 pmap_preboot_pt2_setup(vm_offset_t va)
919 vm_paddr_t pt2pg_pa, pt2_pa;
921 /* Setup PT2's page. */
922 pt2pg_pa = pmap_preboot_pt2pg_setup(va);
923 pt2_pa = page_pt2pa(pt2pg_pa, pte1_index(va));
925 /* Insert PT2 to PT1. */
926 pte1p = kern_pte1(va);
927 pte1_store(pte1p, PTE1_LINK(pt2_pa));
931 * Get L2 page entry associated with given KVA.
932 * Used in pre-bootstrap epoch.
934 static __inline pt2_entry_t*
935 pmap_preboot_vtopte2(vm_offset_t va)
939 /* Setup PT2 if needed. */
940 pte1p = kern_pte1(va);
941 if (!pte1_is_valid(pte1_load(pte1p))) /* XXX - sections ?! */
942 pmap_preboot_pt2_setup(va);
944 return (pt2map_entry(va));
948 * Pre-bootstrap epoch page(s) mapping(s).
951 pmap_preboot_map_pages(vm_paddr_t pa, vm_offset_t va, u_int num)
956 /* Map all the pages. */
957 for (i = 0; i < num; i++) {
958 pte2p = pmap_preboot_vtopte2(va);
959 pte2_store(pte2p, PTE2_KRW(pa));
966 * Pre-bootstrap epoch virtual space alocator.
969 pmap_preboot_reserve_pages(u_int num)
972 vm_offset_t start, va;
975 /* Allocate virtual space. */
976 start = va = virtual_avail;
977 virtual_avail += num * PAGE_SIZE;
979 /* Zero the mapping. */
980 for (i = 0; i < num; i++) {
981 pte2p = pmap_preboot_vtopte2(va);
982 pte2_store(pte2p, 0);
990 * Pre-bootstrap epoch page(s) allocation and mapping(s).
993 pmap_preboot_get_vpages(u_int num)
998 /* Allocate physical page(s). */
999 pa = pmap_preboot_get_pages(num);
1001 /* Allocate virtual space. */
1003 virtual_avail += num * PAGE_SIZE;
1005 /* Map and zero all. */
1006 pmap_preboot_map_pages(pa, va, num);
1007 bzero((void *)va, num * PAGE_SIZE);
1013 * Pre-bootstrap epoch page mapping(s) with attributes.
1016 pmap_preboot_map_attr(vm_paddr_t pa, vm_offset_t va, vm_size_t size,
1017 vm_prot_t prot, vm_memattr_t attr)
1020 u_int l1_attr, l1_prot, l2_prot, l2_attr;
1024 l2_prot = prot & VM_PROT_WRITE ? PTE2_AP_KRW : PTE2_AP_KR;
1025 l2_attr = vm_memattr_to_pte2(attr);
1026 l1_prot = ATTR_TO_L1(l2_prot);
1027 l1_attr = ATTR_TO_L1(l2_attr);
1029 /* Map all the pages. */
1030 num = round_page(size);
1032 if ((((va | pa) & PTE1_OFFSET) == 0) && (num >= PTE1_SIZE)) {
1033 pte1p = kern_pte1(va);
1034 pte1_store(pte1p, PTE1_KERN(pa, l1_prot, l1_attr));
1039 pte2p = pmap_preboot_vtopte2(va);
1040 pte2_store(pte2p, PTE2_KERN(pa, l2_prot, l2_attr));
1049 * Extract from the kernel page table the physical address
1050 * that is mapped by the given virtual address "va".
1053 pmap_kextract(vm_offset_t va)
1059 pte1 = pte1_load(kern_pte1(va));
1060 if (pte1_is_section(pte1)) {
1061 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1062 } else if (pte1_is_link(pte1)) {
1064 * We should beware of concurrent promotion that changes
1065 * pte1 at this point. However, it's not a problem as PT2
1066 * page is preserved by promotion in PT2TAB. So even if
1067 * it happens, using of PT2MAP is still safe.
1069 * QQQ: However, concurrent removing is a problem which
1070 * ends in abort on PT2MAP space. Locking must be used
1071 * to deal with this.
1073 pte2 = pte2_load(pt2map_entry(va));
1074 pa = pte2_pa(pte2) | (va & PTE2_OFFSET);
1077 panic("%s: va %#x pte1 %#x", __func__, va, pte1);
1083 * Extract from the kernel page table the physical address
1084 * that is mapped by the given virtual address "va". Also
1085 * return L2 page table entry which maps the address.
1087 * This is only intended to be used for panic dumps.
1090 pmap_dump_kextract(vm_offset_t va, pt2_entry_t *pte2p)
1096 pte1 = pte1_load(kern_pte1(va));
1097 if (pte1_is_section(pte1)) {
1098 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1099 pte2 = pa | ATTR_TO_L2(pte1) | PTE2_V;
1100 } else if (pte1_is_link(pte1)) {
1101 pte2 = pte2_load(pt2map_entry(va));
1112 /*****************************************************************************
1114 * PMAP second stage initialization and utility functions
1115 * for bootstrap epoch.
1117 * After pmap_bootstrap() is called, the following functions for
1118 * mappings can be used:
1120 * void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
1121 * void pmap_kremove(vm_offset_t va);
1122 * vm_offset_t pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end,
1125 * NOTE: This is not SMP coherent stage. And physical page allocation is not
1126 * allowed during this stage.
1128 *****************************************************************************/
1131 * Initialize kernel PMAP locks and lists, kernel_pmap itself, and
1132 * reserve various virtual spaces for temporary mappings.
1135 pmap_bootstrap(vm_offset_t firstaddr)
1137 pt2_entry_t *unused __unused;
1138 struct sysmaps *sysmaps;
1142 * Initialize the kernel pmap (which is statically allocated).
1144 PMAP_LOCK_INIT(kernel_pmap);
1145 kernel_l1pa = (vm_paddr_t)kern_pt1; /* for libkvm */
1146 kernel_pmap->pm_pt1 = kern_pt1;
1147 kernel_pmap->pm_pt2tab = kern_pt2tab;
1148 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1149 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1152 * Initialize the global pv list lock.
1154 rw_init(&pvh_global_lock, "pmap pv global");
1156 LIST_INIT(&allpmaps);
1159 * Request a spin mutex so that changes to allpmaps cannot be
1160 * preempted by smp_rendezvous_cpus().
1162 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
1163 mtx_lock_spin(&allpmaps_lock);
1164 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
1165 mtx_unlock_spin(&allpmaps_lock);
1168 * Reserve some special page table entries/VA space for temporary
1171 #define SYSMAP(c, p, v, n) do { \
1172 v = (c)pmap_preboot_reserve_pages(n); \
1173 p = pt2map_entry((vm_offset_t)v); \
1177 * Local CMAP1/CMAP2 are used for zeroing and copying pages.
1178 * Local CMAP3 is used for data cache cleaning.
1179 * Global CMAP3 is used for the idle process page zeroing.
1181 for (i = 0; i < MAXCPU; i++) {
1182 sysmaps = &sysmaps_pcpu[i];
1183 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF);
1184 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1);
1185 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1);
1186 SYSMAP(caddr_t, sysmaps->CMAP3, sysmaps->CADDR3, 1);
1188 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
1193 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS);
1196 * _tmppt is used for reading arbitrary physical pages via /dev/mem.
1198 SYSMAP(caddr_t, unused, _tmppt, 1);
1201 * PADDR1 and PADDR2 are used by pmap_pte2_quick() and pmap_pte2(),
1202 * respectively. PADDR3 is used by pmap_pte2_ddb().
1204 SYSMAP(pt2_entry_t *, PMAP1, PADDR1, 1);
1205 SYSMAP(pt2_entry_t *, PMAP2, PADDR2, 1);
1207 SYSMAP(pt2_entry_t *, PMAP3, PADDR3, 1);
1209 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
1212 * Note that in very short time in initarm(), we are going to
1213 * initialize phys_avail[] array and no futher page allocation
1214 * can happen after that until vm subsystem will be initialized.
1216 kernel_vm_end_new = kernel_vm_end;
1217 virtual_end = vm_max_kernel_address;
1221 pmap_init_qpages(void)
1228 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE);
1229 if (pc->pc_qmap_addr == 0)
1230 panic("%s: unable to allocate KVA", __func__);
1233 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_qpages, NULL);
1236 * The function can already be use in second initialization stage.
1237 * As such, the function DOES NOT call pmap_growkernel() where PT2
1238 * allocation can happen. So if used, be sure that PT2 for given
1239 * virtual address is allocated already!
1241 * Add a wired page to the kva.
1242 * Note: not SMP coherent.
1244 static __inline void
1245 pmap_kenter_prot_attr(vm_offset_t va, vm_paddr_t pa, uint32_t prot,
1251 pte1p = kern_pte1(va);
1252 if (!pte1_is_valid(pte1_load(pte1p))) { /* XXX - sections ?! */
1254 * This is a very low level function, so PT2 and particularly
1255 * PT2PG associated with given virtual address must be already
1256 * allocated. It's a pain mainly during pmap initialization
1257 * stage. However, called after pmap initialization with
1258 * virtual address not under kernel_vm_end will lead to
1261 if (!pte2_is_valid(pte2_load(kern_pt2tab_entry(va))))
1262 panic("%s: kernel PT2 not allocated!", __func__);
1265 pte2p = pt2map_entry(va);
1266 pte2_store(pte2p, PTE2_KERN(pa, prot, attr));
1269 static __inline void
1270 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int attr)
1273 pmap_kenter_prot_attr(va, pa, PTE2_AP_KRW, attr);
1277 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1280 pmap_kenter_prot_attr(va, pa, PTE2_AP_KRW, PTE2_ATTR_DEFAULT);
1284 * Remove a page from the kernel pagetables.
1285 * Note: not SMP coherent.
1288 pmap_kremove(vm_offset_t va)
1292 pte2p = pt2map_entry(va);
1297 * Share new kernel PT2PG with all pmaps.
1298 * The caller is responsible for maintaining TLB consistency.
1301 pmap_kenter_pt2tab(vm_offset_t va, pt2_entry_t npte2)
1306 mtx_lock_spin(&allpmaps_lock);
1307 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1308 pte2p = pmap_pt2tab_entry(pmap, va);
1309 pt2tab_store(pte2p, npte2);
1311 mtx_unlock_spin(&allpmaps_lock);
1315 * Share new kernel PTE1 with all pmaps.
1316 * The caller is responsible for maintaining TLB consistency.
1319 pmap_kenter_pte1(vm_offset_t va, pt1_entry_t npte1)
1324 mtx_lock_spin(&allpmaps_lock);
1325 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1326 pte1p = pmap_pte1(pmap, va);
1327 pte1_store(pte1p, npte1);
1329 mtx_unlock_spin(&allpmaps_lock);
1333 * Used to map a range of physical addresses into kernel
1334 * virtual address space.
1336 * The value passed in '*virt' is a suggested virtual address for
1337 * the mapping. Architectures which can support a direct-mapped
1338 * physical to virtual region can return the appropriate address
1339 * within that region, leaving '*virt' unchanged. Other
1340 * architectures should map the pages starting at '*virt' and
1341 * update '*virt' with the first usable address after the mapped
1344 * NOTE: Read the comments above pmap_kenter_prot_attr() as
1345 * the function is used herein!
1348 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1350 vm_offset_t va, sva;
1351 vm_paddr_t pte1_offset;
1353 uint32_t l1prot, l2prot;
1354 uint32_t l1attr, l2attr;
1356 PDEBUG(1, printf("%s: virt = %#x, start = %#x, end = %#x (size = %#x),"
1357 " prot = %d\n", __func__, *virt, start, end, end - start, prot));
1359 l2prot = (prot & VM_PROT_WRITE) ? PTE2_AP_KRW : PTE2_AP_KR;
1360 l2prot |= (prot & VM_PROT_EXECUTE) ? PTE2_X : PTE2_NX;
1361 l1prot = ATTR_TO_L1(l2prot);
1363 l2attr = PTE2_ATTR_DEFAULT;
1364 l1attr = ATTR_TO_L1(l2attr);
1368 * Does the physical address range's size and alignment permit at
1369 * least one section mapping to be created?
1371 pte1_offset = start & PTE1_OFFSET;
1372 if ((end - start) - ((PTE1_SIZE - pte1_offset) & PTE1_OFFSET) >=
1375 * Increase the starting virtual address so that its alignment
1376 * does not preclude the use of section mappings.
1378 if ((va & PTE1_OFFSET) < pte1_offset)
1379 va = pte1_trunc(va) + pte1_offset;
1380 else if ((va & PTE1_OFFSET) > pte1_offset)
1381 va = pte1_roundup(va) + pte1_offset;
1384 while (start < end) {
1385 if ((start & PTE1_OFFSET) == 0 && end - start >= PTE1_SIZE) {
1386 KASSERT((va & PTE1_OFFSET) == 0,
1387 ("%s: misaligned va %#x", __func__, va));
1388 npte1 = PTE1_KERN(start, l1prot, l1attr);
1389 pmap_kenter_pte1(va, npte1);
1393 pmap_kenter_prot_attr(va, start, l2prot, l2attr);
1398 tlb_flush_range(sva, va - sva);
1404 * Make a temporary mapping for a physical address.
1405 * This is only intended to be used for panic dumps.
1408 pmap_kenter_temporary(vm_paddr_t pa, int i)
1412 /* QQQ: 'i' should be less or equal to MAXDUMPPGS. */
1414 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
1415 pmap_kenter(va, pa);
1416 tlb_flush_local(va);
1417 return ((void *)crashdumpmap);
1421 /*************************************
1423 * TLB & cache maintenance routines.
1425 *************************************/
1428 * We inline these within pmap.c for speed.
1431 pmap_tlb_flush(pmap_t pmap, vm_offset_t va)
1434 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1439 pmap_tlb_flush_range(pmap_t pmap, vm_offset_t sva, vm_size_t size)
1442 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1443 tlb_flush_range(sva, size);
1447 * Abuse the pte2 nodes for unmapped kva to thread a kva freelist through.
1449 * - Must deal with pages in order to ensure that none of the PTE2_* bits
1450 * are ever set, PTE2_V in particular.
1451 * - Assumes we can write to pte2s without pte2_store() atomic ops.
1452 * - Assumes nothing will ever test these addresses for 0 to indicate
1453 * no mapping instead of correctly checking PTE2_V.
1454 * - Assumes a vm_offset_t will fit in a pte2 (true for arm).
1455 * Because PTE2_V is never set, there can be no mappings to invalidate.
1458 pmap_pte2list_alloc(vm_offset_t *head)
1465 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
1466 pte2p = pt2map_entry(va);
1469 panic("%s: va with PTE2_V set!", __func__);
1475 pmap_pte2list_free(vm_offset_t *head, vm_offset_t va)
1480 panic("%s: freeing va with PTE2_V set!", __func__);
1481 pte2p = pt2map_entry(va);
1482 *pte2p = *head; /* virtual! PTE2_V is 0 though */
1487 pmap_pte2list_init(vm_offset_t *head, void *base, int npages)
1493 for (i = npages - 1; i >= 0; i--) {
1494 va = (vm_offset_t)base + i * PAGE_SIZE;
1495 pmap_pte2list_free(head, va);
1499 /*****************************************************************************
1501 * PMAP third and final stage initialization.
1503 * After pmap_init() is called, PMAP subsystem is fully initialized.
1505 *****************************************************************************/
1507 SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
1509 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
1510 "Max number of PV entries");
1511 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
1512 "Page share factor per proc");
1514 static u_long nkpt2pg = NKPT2PG;
1515 SYSCTL_ULONG(_vm_pmap, OID_AUTO, nkpt2pg, CTLFLAG_RD,
1516 &nkpt2pg, 0, "Pre-allocated pages for kernel PT2s");
1518 static int sp_enabled = 1;
1519 SYSCTL_INT(_vm_pmap, OID_AUTO, sp_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
1520 &sp_enabled, 0, "Are large page mappings enabled?");
1522 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pte1, CTLFLAG_RD, 0,
1523 "1MB page mapping counters");
1525 static u_long pmap_pte1_demotions;
1526 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, demotions, CTLFLAG_RD,
1527 &pmap_pte1_demotions, 0, "1MB page demotions");
1529 static u_long pmap_pte1_mappings;
1530 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, mappings, CTLFLAG_RD,
1531 &pmap_pte1_mappings, 0, "1MB page mappings");
1533 static u_long pmap_pte1_p_failures;
1534 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, p_failures, CTLFLAG_RD,
1535 &pmap_pte1_p_failures, 0, "1MB page promotion failures");
1537 static u_long pmap_pte1_promotions;
1538 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, promotions, CTLFLAG_RD,
1539 &pmap_pte1_promotions, 0, "1MB page promotions");
1541 static __inline ttb_entry_t
1542 pmap_ttb_get(pmap_t pmap)
1545 return (vtophys(pmap->pm_pt1) | ttb_flags);
1549 * Initialize a vm_page's machine-dependent fields.
1552 * 1. Pages for L2 page tables are always not managed. So, pv_list and
1553 * pt2_wirecount can share same physical space. However, proper
1554 * initialization on a page alloc for page tables and reinitialization
1555 * on the page free must be ensured.
1558 pmap_page_init(vm_page_t m)
1561 TAILQ_INIT(&m->md.pv_list);
1562 pt2_wirecount_init(m);
1563 m->md.pat_mode = VM_MEMATTR_DEFAULT;
1567 * Virtualization for faster way how to zero whole page.
1569 static __inline void
1570 pagezero(void *page)
1573 bzero(page, PAGE_SIZE);
1577 * Zero L2 page table page.
1578 * Use same KVA as in pmap_zero_page().
1580 static __inline vm_paddr_t
1581 pmap_pt2pg_zero(vm_page_t m)
1584 struct sysmaps *sysmaps;
1586 pa = VM_PAGE_TO_PHYS(m);
1589 * XXX: For now, we map whole page even if it's already zero,
1590 * to sync it even if the sync is only DSB.
1593 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
1594 mtx_lock(&sysmaps->lock);
1595 if (pte2_load(sysmaps->CMAP2) != 0)
1596 panic("%s: CMAP2 busy", __func__);
1597 pte2_store(sysmaps->CMAP2, PTE2_KERN_NG(pa, PTE2_AP_KRW,
1598 vm_page_pte2_attr(m)));
1599 /* Even VM_ALLOC_ZERO request is only advisory. */
1600 if ((m->flags & PG_ZERO) == 0)
1601 pagezero(sysmaps->CADDR2);
1602 pte2_sync_range((pt2_entry_t *)sysmaps->CADDR2, PAGE_SIZE);
1603 pte2_clear(sysmaps->CMAP2);
1604 tlb_flush((vm_offset_t)sysmaps->CADDR2);
1606 mtx_unlock(&sysmaps->lock);
1612 * Init just allocated page as L2 page table(s) holder
1613 * and return its physical address.
1615 static __inline vm_paddr_t
1616 pmap_pt2pg_init(pmap_t pmap, vm_offset_t va, vm_page_t m)
1621 /* Check page attributes. */
1622 if (m->md.pat_mode != pt_memattr)
1623 pmap_page_set_memattr(m, pt_memattr);
1625 /* Zero page and init wire counts. */
1626 pa = pmap_pt2pg_zero(m);
1627 pt2_wirecount_init(m);
1630 * Map page to PT2MAP address space for given pmap.
1631 * Note that PT2MAP space is shared with all pmaps.
1633 if (pmap == kernel_pmap)
1634 pmap_kenter_pt2tab(va, PTE2_KPT(pa));
1636 pte2p = pmap_pt2tab_entry(pmap, va);
1637 pt2tab_store(pte2p, PTE2_KPT_NG(pa));
1644 * Initialize the pmap module.
1645 * Called by vm_init, to initialize any structures that the pmap
1646 * system needs to map virtual memory.
1652 pt2_entry_t *pte2p, pte2;
1653 u_int i, pte1_idx, pv_npg;
1655 PDEBUG(1, printf("%s: phys_start = %#x\n", __func__, PHYSADDR));
1658 * Initialize the vm page array entries for kernel pmap's
1659 * L2 page table pages allocated in advance.
1661 pte1_idx = pte1_index(KERNBASE - PT2MAP_SIZE);
1662 pte2p = kern_pt2tab_entry(KERNBASE - PT2MAP_SIZE);
1663 for (i = 0; i < nkpt2pg + NPG_IN_PT2TAB; i++, pte2p++) {
1667 pte2 = pte2_load(pte2p);
1668 KASSERT(pte2_is_valid(pte2), ("%s: no valid entry", __func__));
1671 m = PHYS_TO_VM_PAGE(pa);
1672 KASSERT(m >= vm_page_array &&
1673 m < &vm_page_array[vm_page_array_size],
1674 ("%s: L2 page table page is out of range", __func__));
1676 m->pindex = pte1_idx;
1678 pte1_idx += NPT2_IN_PG;
1682 * Initialize the address space (zone) for the pv entries. Set a
1683 * high water mark so that the system can recover from excessive
1684 * numbers of pv entries.
1686 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1687 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1688 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1689 pv_entry_max = roundup(pv_entry_max, _NPCPV);
1690 pv_entry_high_water = 9 * (pv_entry_max / 10);
1693 * Are large page mappings enabled?
1695 TUNABLE_INT_FETCH("vm.pmap.sp_enabled", &sp_enabled);
1697 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1698 ("%s: can't assign to pagesizes[1]", __func__));
1699 pagesizes[1] = PTE1_SIZE;
1703 * Calculate the size of the pv head table for sections.
1704 * Handle the possibility that "vm_phys_segs[...].end" is zero.
1705 * Note that the table is only for sections which could be promoted.
1707 first_managed_pa = pte1_trunc(vm_phys_segs[0].start);
1708 pv_npg = (pte1_trunc(vm_phys_segs[vm_phys_nsegs - 1].end - PAGE_SIZE)
1709 - first_managed_pa) / PTE1_SIZE + 1;
1712 * Allocate memory for the pv head table for sections.
1714 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1716 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
1718 for (i = 0; i < pv_npg; i++)
1719 TAILQ_INIT(&pv_table[i].pv_list);
1721 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
1722 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
1723 if (pv_chunkbase == NULL)
1724 panic("%s: not enough kvm for pv chunks", __func__);
1725 pmap_pte2list_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
1729 * Add a list of wired pages to the kva
1730 * this routine is only used for temporary
1731 * kernel mappings that do not need to have
1732 * page modification or references recorded.
1733 * Note that old mappings are simply written
1734 * over. The page *must* be wired.
1735 * Note: SMP coherent. Uses a ranged shootdown IPI.
1738 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1741 pt2_entry_t *epte2p, *pte2p, pte2;
1746 pte2p = pt2map_entry(sva);
1747 epte2p = pte2p + count;
1748 while (pte2p < epte2p) {
1750 pa = VM_PAGE_TO_PHYS(m);
1751 pte2 = pte2_load(pte2p);
1752 if ((pte2_pa(pte2) != pa) ||
1753 (pte2_attr(pte2) != vm_page_pte2_attr(m))) {
1755 pte2_store(pte2p, PTE2_KERN(pa, PTE2_AP_KRW,
1756 vm_page_pte2_attr(m)));
1760 if (__predict_false(anychanged))
1761 tlb_flush_range(sva, count * PAGE_SIZE);
1765 * This routine tears out page mappings from the
1766 * kernel -- it is meant only for temporary mappings.
1767 * Note: SMP coherent. Uses a ranged shootdown IPI.
1770 pmap_qremove(vm_offset_t sva, int count)
1775 while (count-- > 0) {
1779 tlb_flush_range(sva, va - sva);
1783 * Are we current address space or kernel?
1786 pmap_is_current(pmap_t pmap)
1789 return (pmap == kernel_pmap ||
1790 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace)));
1794 * If the given pmap is not the current or kernel pmap, the returned
1795 * pte2 must be released by passing it to pmap_pte2_release().
1797 static pt2_entry_t *
1798 pmap_pte2(pmap_t pmap, vm_offset_t va)
1801 vm_paddr_t pt2pg_pa;
1803 pte1 = pte1_load(pmap_pte1(pmap, va));
1804 if (pte1_is_section(pte1))
1805 panic("%s: attempt to map PTE1", __func__);
1806 if (pte1_is_link(pte1)) {
1807 /* Are we current address space or kernel? */
1808 if (pmap_is_current(pmap))
1809 return (pt2map_entry(va));
1810 /* Note that L2 page table size is not equal to PAGE_SIZE. */
1811 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
1812 mtx_lock(&PMAP2mutex);
1813 if (pte2_pa(pte2_load(PMAP2)) != pt2pg_pa) {
1814 pte2_store(PMAP2, PTE2_KPT(pt2pg_pa));
1815 tlb_flush((vm_offset_t)PADDR2);
1817 return (PADDR2 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
1823 * Releases a pte2 that was obtained from pmap_pte2().
1824 * Be prepared for the pte2p being NULL.
1826 static __inline void
1827 pmap_pte2_release(pt2_entry_t *pte2p)
1830 if ((pt2_entry_t *)(trunc_page((vm_offset_t)pte2p)) == PADDR2) {
1831 mtx_unlock(&PMAP2mutex);
1836 * Super fast pmap_pte2 routine best used when scanning
1837 * the pv lists. This eliminates many coarse-grained
1838 * invltlb calls. Note that many of the pv list
1839 * scans are across different pmaps. It is very wasteful
1840 * to do an entire tlb flush for checking a single mapping.
1842 * If the given pmap is not the current pmap, pvh_global_lock
1843 * must be held and curthread pinned to a CPU.
1845 static pt2_entry_t *
1846 pmap_pte2_quick(pmap_t pmap, vm_offset_t va)
1849 vm_paddr_t pt2pg_pa;
1851 pte1 = pte1_load(pmap_pte1(pmap, va));
1852 if (pte1_is_section(pte1))
1853 panic("%s: attempt to map PTE1", __func__);
1854 if (pte1_is_link(pte1)) {
1855 /* Are we current address space or kernel? */
1856 if (pmap_is_current(pmap))
1857 return (pt2map_entry(va));
1858 rw_assert(&pvh_global_lock, RA_WLOCKED);
1859 KASSERT(curthread->td_pinned > 0,
1860 ("%s: curthread not pinned", __func__));
1861 /* Note that L2 page table size is not equal to PAGE_SIZE. */
1862 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
1863 if (pte2_pa(pte2_load(PMAP1)) != pt2pg_pa) {
1864 pte2_store(PMAP1, PTE2_KPT(pt2pg_pa));
1866 PMAP1cpu = PCPU_GET(cpuid);
1868 tlb_flush_local((vm_offset_t)PADDR1);
1872 if (PMAP1cpu != PCPU_GET(cpuid)) {
1873 PMAP1cpu = PCPU_GET(cpuid);
1874 tlb_flush_local((vm_offset_t)PADDR1);
1879 return (PADDR1 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
1885 * Routine: pmap_extract
1887 * Extract the physical page address associated
1888 * with the given map/virtual_address pair.
1891 pmap_extract(pmap_t pmap, vm_offset_t va)
1898 pte1 = pte1_load(pmap_pte1(pmap, va));
1899 if (pte1_is_section(pte1))
1900 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1901 else if (pte1_is_link(pte1)) {
1902 pte2p = pmap_pte2(pmap, va);
1903 pa = pte2_pa(pte2_load(pte2p)) | (va & PTE2_OFFSET);
1904 pmap_pte2_release(pte2p);
1912 * Routine: pmap_extract_and_hold
1914 * Atomically extract and hold the physical page
1915 * with the given pmap and virtual address pair
1916 * if that mapping permits the given protection.
1919 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1921 vm_paddr_t pa, lockpa;
1923 pt2_entry_t pte2, *pte2p;
1930 pte1 = pte1_load(pmap_pte1(pmap, va));
1931 if (pte1_is_section(pte1)) {
1932 if (!(pte1 & PTE1_RO) || !(prot & VM_PROT_WRITE)) {
1933 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1934 if (vm_page_pa_tryrelock(pmap, pa, &lockpa))
1936 m = PHYS_TO_VM_PAGE(pa);
1939 } else if (pte1_is_link(pte1)) {
1940 pte2p = pmap_pte2(pmap, va);
1941 pte2 = pte2_load(pte2p);
1942 pmap_pte2_release(pte2p);
1943 if (pte2_is_valid(pte2) &&
1944 (!(pte2 & PTE2_RO) || !(prot & VM_PROT_WRITE))) {
1946 if (vm_page_pa_tryrelock(pmap, pa, &lockpa))
1948 m = PHYS_TO_VM_PAGE(pa);
1952 PA_UNLOCK_COND(lockpa);
1958 * Grow the number of kernel L2 page table entries, if needed.
1961 pmap_growkernel(vm_offset_t addr)
1964 vm_paddr_t pt2pg_pa, pt2_pa;
1968 PDEBUG(1, printf("%s: addr = %#x\n", __func__, addr));
1970 * All the time kernel_vm_end is first KVA for which underlying
1971 * L2 page table is either not allocated or linked from L1 page table
1972 * (not considering sections). Except for two possible cases:
1974 * (1) in the very beginning as long as pmap_growkernel() was
1975 * not called, it could be first unused KVA (which is not
1976 * rounded up to PTE1_SIZE),
1978 * (2) when all KVA space is mapped and kernel_map->max_offset
1979 * address is not rounded up to PTE1_SIZE. (For example,
1980 * it could be 0xFFFFFFFF.)
1982 kernel_vm_end = pte1_roundup(kernel_vm_end);
1983 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1984 addr = roundup2(addr, PTE1_SIZE);
1985 if (addr - 1 >= kernel_map->max_offset)
1986 addr = kernel_map->max_offset;
1987 while (kernel_vm_end < addr) {
1988 pte1 = pte1_load(kern_pte1(kernel_vm_end));
1989 if (pte1_is_valid(pte1)) {
1990 kernel_vm_end += PTE1_SIZE;
1991 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1992 kernel_vm_end = kernel_map->max_offset;
1999 * kernel_vm_end_new is used in pmap_pinit() when kernel
2000 * mappings are entered to new pmap all at once to avoid race
2001 * between pmap_kenter_pte1() and kernel_vm_end increase.
2002 * The same aplies to pmap_kenter_pt2tab().
2004 kernel_vm_end_new = kernel_vm_end + PTE1_SIZE;
2006 pte2 = pt2tab_load(kern_pt2tab_entry(kernel_vm_end));
2007 if (!pte2_is_valid(pte2)) {
2009 * Install new PT2s page into kernel PT2TAB.
2011 m = vm_page_alloc(NULL,
2012 pte1_index(kernel_vm_end) & ~PT2PG_MASK,
2013 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2014 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2016 panic("%s: no memory to grow kernel", __func__);
2018 * QQQ: To link all new L2 page tables from L1 page
2019 * table now and so pmap_kenter_pte1() them
2020 * at once together with pmap_kenter_pt2tab()
2021 * could be nice speed up. However,
2022 * pmap_growkernel() does not happen so often...
2023 * QQQ: The other TTBR is another option.
2025 pt2pg_pa = pmap_pt2pg_init(kernel_pmap, kernel_vm_end,
2028 pt2pg_pa = pte2_pa(pte2);
2030 pt2_pa = page_pt2pa(pt2pg_pa, pte1_index(kernel_vm_end));
2031 pmap_kenter_pte1(kernel_vm_end, PTE1_LINK(pt2_pa));
2033 kernel_vm_end = kernel_vm_end_new;
2034 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2035 kernel_vm_end = kernel_map->max_offset;
2042 kvm_size(SYSCTL_HANDLER_ARGS)
2044 unsigned long ksize = vm_max_kernel_address - KERNBASE;
2046 return (sysctl_handle_long(oidp, &ksize, 0, req));
2048 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2049 0, 0, kvm_size, "IU", "Size of KVM");
2052 kvm_free(SYSCTL_HANDLER_ARGS)
2054 unsigned long kfree = vm_max_kernel_address - kernel_vm_end;
2056 return (sysctl_handle_long(oidp, &kfree, 0, req));
2058 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2059 0, 0, kvm_free, "IU", "Amount of KVM free");
2061 /***********************************************
2063 * Pmap allocation/deallocation routines.
2065 ***********************************************/
2068 * Initialize the pmap for the swapper process.
2071 pmap_pinit0(pmap_t pmap)
2073 PDEBUG(1, printf("%s: pmap = %p\n", __func__, pmap));
2075 PMAP_LOCK_INIT(pmap);
2078 * Kernel page table directory and pmap stuff around is already
2079 * initialized, we are using it right now and here. So, finish
2080 * only PMAP structures initialization for process0 ...
2082 * Since the L1 page table and PT2TAB is shared with the kernel pmap,
2083 * which is already included in the list "allpmaps", this pmap does
2084 * not need to be inserted into that list.
2086 pmap->pm_pt1 = kern_pt1;
2087 pmap->pm_pt2tab = kern_pt2tab;
2088 CPU_ZERO(&pmap->pm_active);
2089 PCPU_SET(curpmap, pmap);
2090 TAILQ_INIT(&pmap->pm_pvchunk);
2091 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2092 CPU_SET(0, &pmap->pm_active);
2095 static __inline void
2096 pte1_copy_nosync(pt1_entry_t *spte1p, pt1_entry_t *dpte1p, vm_offset_t sva,
2101 idx = pte1_index(sva);
2102 count = (pte1_index(eva) - idx + 1) * sizeof(pt1_entry_t);
2103 bcopy(spte1p + idx, dpte1p + idx, count);
2106 static __inline void
2107 pt2tab_copy_nosync(pt2_entry_t *spte2p, pt2_entry_t *dpte2p, vm_offset_t sva,
2112 idx = pt2tab_index(sva);
2113 count = (pt2tab_index(eva) - idx + 1) * sizeof(pt2_entry_t);
2114 bcopy(spte2p + idx, dpte2p + idx, count);
2118 * Initialize a preallocated and zeroed pmap structure,
2119 * such as one in a vmspace structure.
2122 pmap_pinit(pmap_t pmap)
2126 vm_paddr_t pa, pt2tab_pa;
2129 PDEBUG(6, printf("%s: pmap = %p, pm_pt1 = %p\n", __func__, pmap,
2133 * No need to allocate L2 page table space yet but we do need
2134 * a valid L1 page table and PT2TAB table.
2136 * Install shared kernel mappings to these tables. It's a little
2137 * tricky as some parts of KVA are reserved for vectors, devices,
2138 * and whatever else. These parts are supposed to be above
2139 * vm_max_kernel_address. Thus two regions should be installed:
2141 * (1) <KERNBASE, kernel_vm_end),
2142 * (2) <vm_max_kernel_address, 0xFFFFFFFF>.
2144 * QQQ: The second region should be stable enough to be installed
2145 * only once in time when the tables are allocated.
2146 * QQQ: Maybe copy of both regions at once could be faster ...
2147 * QQQ: Maybe the other TTBR is an option.
2149 * Finally, install own PT2TAB table to these tables.
2152 if (pmap->pm_pt1 == NULL) {
2153 pmap->pm_pt1 = (pt1_entry_t *)kmem_alloc_contig(kernel_arena,
2154 NB_IN_PT1, M_NOWAIT | M_ZERO, 0, -1UL, NB_IN_PT1, 0,
2156 if (pmap->pm_pt1 == NULL)
2159 if (pmap->pm_pt2tab == NULL) {
2161 * QQQ: (1) PT2TAB must be contiguous. If PT2TAB is one page
2162 * only, what should be the only size for 32 bit systems,
2163 * then we could allocate it with vm_page_alloc() and all
2164 * the stuff needed as other L2 page table pages.
2165 * (2) Note that a process PT2TAB is special L2 page table
2166 * page. Its mapping in kernel_arena is permanent and can
2167 * be used no matter which process is current. Its mapping
2168 * in PT2MAP can be used only for current process.
2170 pmap->pm_pt2tab = (pt2_entry_t *)kmem_alloc_attr(kernel_arena,
2171 NB_IN_PT2TAB, M_NOWAIT | M_ZERO, 0, -1UL, pt_memattr);
2172 if (pmap->pm_pt2tab == NULL) {
2174 * QQQ: As struct pmap is allocated from UMA with
2175 * UMA_ZONE_NOFREE flag, it's important to leave
2176 * no allocation in pmap if initialization failed.
2178 kmem_free(kernel_arena, (vm_offset_t)pmap->pm_pt1,
2180 pmap->pm_pt1 = NULL;
2184 * QQQ: Each L2 page table page vm_page_t has pindex set to
2185 * pte1 index of virtual address mapped by this page.
2186 * It's not valid for non kernel PT2TABs themselves.
2187 * The pindex of these pages can not be altered because
2188 * of the way how they are allocated now. However, it
2189 * should not be a problem.
2193 mtx_lock_spin(&allpmaps_lock);
2195 * To avoid race with pmap_kenter_pte1() and pmap_kenter_pt2tab(),
2196 * kernel_vm_end_new is used here instead of kernel_vm_end.
2198 pte1_copy_nosync(kern_pt1, pmap->pm_pt1, KERNBASE,
2199 kernel_vm_end_new - 1);
2200 pte1_copy_nosync(kern_pt1, pmap->pm_pt1, vm_max_kernel_address,
2202 pt2tab_copy_nosync(kern_pt2tab, pmap->pm_pt2tab, KERNBASE,
2203 kernel_vm_end_new - 1);
2204 pt2tab_copy_nosync(kern_pt2tab, pmap->pm_pt2tab, vm_max_kernel_address,
2206 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
2207 mtx_unlock_spin(&allpmaps_lock);
2210 * Store PT2MAP PT2 pages (a.k.a. PT2TAB) in PT2TAB itself.
2211 * I.e. self reference mapping. The PT2TAB is private, however mapped
2212 * into shared PT2MAP space, so the mapping should be not global.
2214 pt2tab_pa = vtophys(pmap->pm_pt2tab);
2215 pte2p = pmap_pt2tab_entry(pmap, (vm_offset_t)PT2MAP);
2216 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE) {
2217 pt2tab_store(pte2p++, PTE2_KPT_NG(pa));
2220 /* Insert PT2MAP PT2s into pmap PT1. */
2221 pte1p = pmap_pte1(pmap, (vm_offset_t)PT2MAP);
2222 for (pa = pt2tab_pa, i = 0; i < NPT2_IN_PT2TAB; i++, pa += NB_IN_PT2) {
2223 pte1_store(pte1p++, PTE1_LINK(pa));
2227 * Now synchronize new mapping which was made above.
2229 pte1_sync_range(pmap->pm_pt1, NB_IN_PT1);
2230 pte2_sync_range(pmap->pm_pt2tab, NB_IN_PT2TAB);
2232 CPU_ZERO(&pmap->pm_active);
2233 TAILQ_INIT(&pmap->pm_pvchunk);
2234 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2241 pt2tab_user_is_empty(pt2_entry_t *tab)
2245 end = pt2tab_index(VM_MAXUSER_ADDRESS);
2246 for (i = 0; i < end; i++)
2247 if (tab[i] != 0) return (FALSE);
2252 * Release any resources held by the given physical map.
2253 * Called when a pmap initialized by pmap_pinit is being released.
2254 * Should only be called if the map contains no valid mappings.
2257 pmap_release(pmap_t pmap)
2260 vm_offset_t start, end;
2262 KASSERT(pmap->pm_stats.resident_count == 0,
2263 ("%s: pmap resident count %ld != 0", __func__,
2264 pmap->pm_stats.resident_count));
2265 KASSERT(pt2tab_user_is_empty(pmap->pm_pt2tab),
2266 ("%s: has allocated user PT2(s)", __func__));
2267 KASSERT(CPU_EMPTY(&pmap->pm_active),
2268 ("%s: pmap %p is active on some CPU(s)", __func__, pmap));
2270 mtx_lock_spin(&allpmaps_lock);
2271 LIST_REMOVE(pmap, pm_list);
2272 mtx_unlock_spin(&allpmaps_lock);
2275 start = pte1_index(KERNBASE) * sizeof(pt1_entry_t);
2276 end = (pte1_index(0xFFFFFFFF) + 1) * sizeof(pt1_entry_t);
2277 bzero((char *)pmap->pm_pt1 + start, end - start);
2279 start = pt2tab_index(KERNBASE) * sizeof(pt2_entry_t);
2280 end = (pt2tab_index(0xFFFFFFFF) + 1) * sizeof(pt2_entry_t);
2281 bzero((char *)pmap->pm_pt2tab + start, end - start);
2284 * We are leaving PT1 and PT2TAB allocated on released pmap,
2285 * so hopefully UMA vmspace_zone will always be inited with
2286 * UMA_ZONE_NOFREE flag.
2290 /*********************************************************
2292 * L2 table pages and their pages management routines.
2294 *********************************************************/
2297 * Virtual interface for L2 page table wire counting.
2299 * Each L2 page table in a page has own counter which counts a number of
2300 * valid mappings in a table. Global page counter counts mappings in all
2301 * tables in a page plus a single itself mapping in PT2TAB.
2303 * During a promotion we leave the associated L2 page table counter
2304 * untouched, so the table (strictly speaking a page which holds it)
2305 * is never freed if promoted.
2307 * If a page m->wire_count == 1 then no valid mappings exist in any L2 page
2308 * table in the page and the page itself is only mapped in PT2TAB.
2311 static __inline void
2312 pt2_wirecount_init(vm_page_t m)
2317 * Note: A page m is allocated with VM_ALLOC_WIRED flag and
2318 * m->wire_count should be already set correctly.
2319 * So, there is no need to set it again herein.
2321 for (i = 0; i < NPT2_IN_PG; i++)
2322 m->md.pt2_wirecount[i] = 0;
2325 static __inline void
2326 pt2_wirecount_inc(vm_page_t m, uint32_t pte1_idx)
2330 * Note: A just modificated pte2 (i.e. already allocated)
2331 * is acquiring one extra reference which must be
2332 * explicitly cleared. It influences the KASSERTs herein.
2333 * All L2 page tables in a page always belong to the same
2334 * pmap, so we allow only one extra reference for the page.
2336 KASSERT(m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] < (NPTE2_IN_PT2 + 1),
2337 ("%s: PT2 is overflowing ...", __func__));
2338 KASSERT(m->wire_count <= (NPTE2_IN_PG + 1),
2339 ("%s: PT2PG is overflowing ...", __func__));
2342 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]++;
2345 static __inline void
2346 pt2_wirecount_dec(vm_page_t m, uint32_t pte1_idx)
2349 KASSERT(m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] != 0,
2350 ("%s: PT2 is underflowing ...", __func__));
2351 KASSERT(m->wire_count > 1,
2352 ("%s: PT2PG is underflowing ...", __func__));
2355 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]--;
2358 static __inline void
2359 pt2_wirecount_set(vm_page_t m, uint32_t pte1_idx, uint16_t count)
2362 KASSERT(count <= NPTE2_IN_PT2,
2363 ("%s: invalid count %u", __func__, count));
2364 KASSERT(m->wire_count > m->md.pt2_wirecount[pte1_idx & PT2PG_MASK],
2365 ("%s: PT2PG corrupting (%u, %u) ...", __func__, m->wire_count,
2366 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]));
2368 m->wire_count -= m->md.pt2_wirecount[pte1_idx & PT2PG_MASK];
2369 m->wire_count += count;
2370 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] = count;
2372 KASSERT(m->wire_count <= (NPTE2_IN_PG + 1),
2373 ("%s: PT2PG is overflowed (%u) ...", __func__, m->wire_count));
2376 static __inline uint32_t
2377 pt2_wirecount_get(vm_page_t m, uint32_t pte1_idx)
2380 return (m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]);
2383 static __inline boolean_t
2384 pt2_is_empty(vm_page_t m, vm_offset_t va)
2387 return (m->md.pt2_wirecount[pte1_index(va) & PT2PG_MASK] == 0);
2390 static __inline boolean_t
2391 pt2_is_full(vm_page_t m, vm_offset_t va)
2394 return (m->md.pt2_wirecount[pte1_index(va) & PT2PG_MASK] ==
2398 static __inline boolean_t
2399 pt2pg_is_empty(vm_page_t m)
2402 return (m->wire_count == 1);
2406 * This routine is called if the L2 page table
2407 * is not mapped correctly.
2410 _pmap_allocpte2(pmap_t pmap, vm_offset_t va, u_int flags)
2416 vm_paddr_t pt2pg_pa, pt2_pa;
2418 pte1_idx = pte1_index(va);
2419 pte1p = pmap->pm_pt1 + pte1_idx;
2421 KASSERT(pte1_load(pte1p) == 0,
2422 ("%s: pm_pt1[%#x] is not zero: %#x", __func__, pte1_idx,
2425 pte2 = pt2tab_load(pmap_pt2tab_entry(pmap, va));
2426 if (!pte2_is_valid(pte2)) {
2428 * Install new PT2s page into pmap PT2TAB.
2430 m = vm_page_alloc(NULL, pte1_idx & ~PT2PG_MASK,
2431 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2433 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2435 rw_wunlock(&pvh_global_lock);
2437 rw_wlock(&pvh_global_lock);
2442 * Indicate the need to retry. While waiting,
2443 * the L2 page table page may have been allocated.
2447 pmap->pm_stats.resident_count++;
2448 pt2pg_pa = pmap_pt2pg_init(pmap, va, m);
2450 pt2pg_pa = pte2_pa(pte2);
2451 m = PHYS_TO_VM_PAGE(pt2pg_pa);
2454 pt2_wirecount_inc(m, pte1_idx);
2455 pt2_pa = page_pt2pa(pt2pg_pa, pte1_idx);
2456 pte1_store(pte1p, PTE1_LINK(pt2_pa));
2462 pmap_allocpte2(pmap_t pmap, vm_offset_t va, u_int flags)
2465 pt1_entry_t *pte1p, pte1;
2468 pte1_idx = pte1_index(va);
2470 pte1p = pmap->pm_pt1 + pte1_idx;
2471 pte1 = pte1_load(pte1p);
2474 * This supports switching from a 1MB page to a
2477 if (pte1_is_section(pte1)) {
2478 (void)pmap_demote_pte1(pmap, pte1p, va);
2480 * Reload pte1 after demotion.
2482 * Note: Demotion can even fail as either PT2 is not find for
2483 * the virtual address or PT2PG can not be allocated.
2485 pte1 = pte1_load(pte1p);
2489 * If the L2 page table page is mapped, we just increment the
2490 * hold count, and activate it.
2492 if (pte1_is_link(pte1)) {
2493 m = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
2494 pt2_wirecount_inc(m, pte1_idx);
2497 * Here if the PT2 isn't mapped, or if it has
2500 m = _pmap_allocpte2(pmap, va, flags);
2501 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2508 static __inline void
2509 pmap_free_zero_pages(struct spglist *free)
2513 while ((m = SLIST_FIRST(free)) != NULL) {
2514 SLIST_REMOVE_HEAD(free, plinks.s.ss);
2515 /* Preserve the page's PG_ZERO setting. */
2516 vm_page_free_toq(m);
2521 * Schedule the specified unused L2 page table page to be freed. Specifically,
2522 * add the page to the specified list of pages that will be released to the
2523 * physical memory manager after the TLB has been updated.
2525 static __inline void
2526 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free)
2530 * Put page on a list so that it is released after
2531 * *ALL* TLB shootdown is done
2534 pmap_zero_page_check(m);
2536 m->flags |= PG_ZERO;
2537 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2541 * Unwire L2 page tables page.
2544 pmap_unwire_pt2pg(pmap_t pmap, vm_offset_t va, vm_page_t m)
2546 pt1_entry_t *pte1p, opte1 __unused;
2550 KASSERT(pt2pg_is_empty(m),
2551 ("%s: pmap %p PT2PG %p wired", __func__, pmap, m));
2554 * Unmap all L2 page tables in the page from L1 page table.
2556 * QQQ: Individual L2 page tables (except the last one) can be unmapped
2557 * earlier. However, we are doing that this way.
2559 KASSERT(m->pindex == (pte1_index(va) & ~PT2PG_MASK),
2560 ("%s: pmap %p va %#x PT2PG %p bad index", __func__, pmap, va, m));
2561 pte1p = pmap->pm_pt1 + m->pindex;
2562 for (i = 0; i < NPT2_IN_PG; i++, pte1p++) {
2563 KASSERT(m->md.pt2_wirecount[i] == 0,
2564 ("%s: pmap %p PT2 %u (PG %p) wired", __func__, pmap, i, m));
2565 opte1 = pte1_load(pte1p);
2566 if (pte1_is_link(opte1)) {
2569 * Flush intermediate TLB cache.
2571 pmap_tlb_flush(pmap, (m->pindex + i) << PTE1_SHIFT);
2575 KASSERT((opte1 == 0) || pte1_is_section(opte1),
2576 ("%s: pmap %p va %#x bad pte1 %x at %u", __func__,
2577 pmap, va, opte1, i));
2582 * Unmap the page from PT2TAB.
2584 pte2p = pmap_pt2tab_entry(pmap, va);
2585 (void)pt2tab_load_clear(pte2p);
2586 pmap_tlb_flush(pmap, pt2map_pt2pg(va));
2589 pmap->pm_stats.resident_count--;
2592 * This is a release store so that the ordinary store unmapping
2593 * the L2 page table page is globally performed before TLB shoot-
2596 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1);
2600 * Decrements a L2 page table page's wire count, which is used to record the
2601 * number of valid page table entries within the page. If the wire count
2602 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2603 * page table page was unmapped and FALSE otherwise.
2605 static __inline boolean_t
2606 pmap_unwire_pt2(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2608 pt2_wirecount_dec(m, pte1_index(va));
2609 if (pt2pg_is_empty(m)) {
2611 * QQQ: Wire count is zero, so whole page should be zero and
2612 * we can set PG_ZERO flag to it.
2613 * Note that when promotion is enabled, it takes some
2614 * more efforts. See pmap_unwire_pt2_all() below.
2616 pmap_unwire_pt2pg(pmap, va, m);
2617 pmap_add_delayed_free_list(m, free);
2624 * Drop a L2 page table page's wire count at once, which is used to record
2625 * the number of valid L2 page table entries within the page. If the wire
2626 * count drops to zero, then the L2 page table page is unmapped.
2628 static __inline void
2629 pmap_unwire_pt2_all(pmap_t pmap, vm_offset_t va, vm_page_t m,
2630 struct spglist *free)
2632 u_int pte1_idx = pte1_index(va);
2634 KASSERT(m->pindex == (pte1_idx & ~PT2PG_MASK),
2635 ("%s: PT2 page's pindex is wrong", __func__));
2636 KASSERT(m->wire_count > pt2_wirecount_get(m, pte1_idx),
2637 ("%s: bad pt2 wire count %u > %u", __func__, m->wire_count,
2638 pt2_wirecount_get(m, pte1_idx)));
2641 * It's possible that the L2 page table was never used.
2642 * It happened in case that a section was created without promotion.
2644 if (pt2_is_full(m, va)) {
2645 pt2_wirecount_set(m, pte1_idx, 0);
2648 * QQQ: We clear L2 page table now, so when L2 page table page
2649 * is going to be freed, we can set it PG_ZERO flag ...
2650 * This function is called only on section mappings, so
2651 * hopefully it's not to big overload.
2653 * XXX: If pmap is current, existing PT2MAP mapping could be
2656 pmap_zero_page_area(m, page_pt2off(pte1_idx), NB_IN_PT2);
2660 KASSERT(pt2_is_empty(m, va), ("%s: PT2 is not empty (%u)",
2661 __func__, pt2_wirecount_get(m, pte1_idx)));
2663 if (pt2pg_is_empty(m)) {
2664 pmap_unwire_pt2pg(pmap, va, m);
2665 pmap_add_delayed_free_list(m, free);
2670 * After removing a L2 page table entry, this routine is used to
2671 * conditionally free the page, and manage the hold/wire counts.
2674 pmap_unuse_pt2(pmap_t pmap, vm_offset_t va, struct spglist *free)
2679 if (va >= VM_MAXUSER_ADDRESS)
2681 pte1 = pte1_load(pmap_pte1(pmap, va));
2682 mpte = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
2683 return (pmap_unwire_pt2(pmap, va, mpte, free));
2686 /*************************************
2688 * Page management routines.
2690 *************************************/
2692 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2693 CTASSERT(_NPCM == 11);
2694 CTASSERT(_NPCPV == 336);
2696 static __inline struct pv_chunk *
2697 pv_to_chunk(pv_entry_t pv)
2700 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2703 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2705 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2706 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2708 static const uint32_t pc_freemask[_NPCM] = {
2709 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2710 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2711 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2712 PC_FREE0_9, PC_FREE10
2715 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2716 "Current number of pv entries");
2719 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2721 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2722 "Current number of pv entry chunks");
2723 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2724 "Current number of pv entry chunks allocated");
2725 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2726 "Current number of pv entry chunks frees");
2727 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail,
2728 0, "Number of times tried to get a chunk page but failed.");
2730 static long pv_entry_frees, pv_entry_allocs;
2731 static int pv_entry_spare;
2733 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2734 "Current number of pv entry frees");
2735 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs,
2736 0, "Current number of pv entry allocs");
2737 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2738 "Current number of spare pv entries");
2742 * Is given page managed?
2744 static __inline boolean_t
2745 is_managed(vm_paddr_t pa)
2751 if (pgnum >= first_page) {
2752 m = PHYS_TO_VM_PAGE(pa);
2755 if ((m->oflags & VPO_UNMANAGED) == 0)
2761 static __inline boolean_t
2762 pte1_is_managed(pt1_entry_t pte1)
2765 return (is_managed(pte1_pa(pte1)));
2768 static __inline boolean_t
2769 pte2_is_managed(pt2_entry_t pte2)
2772 return (is_managed(pte2_pa(pte2)));
2776 * We are in a serious low memory condition. Resort to
2777 * drastic measures to free some pages so we can allocate
2778 * another pv entry chunk.
2781 pmap_pv_reclaim(pmap_t locked_pmap)
2784 struct pv_chunk *pc;
2785 struct md_page *pvh;
2788 pt2_entry_t *pte2p, tpte2;
2792 struct spglist free;
2794 int bit, field, freed;
2796 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2800 TAILQ_INIT(&newtail);
2801 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2802 SLIST_EMPTY(&free))) {
2803 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2804 if (pmap != pc->pc_pmap) {
2806 if (pmap != locked_pmap)
2810 /* Avoid deadlock and lock recursion. */
2811 if (pmap > locked_pmap)
2813 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2815 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2821 * Destroy every non-wired, 4 KB page mapping in the chunk.
2824 for (field = 0; field < _NPCM; field++) {
2825 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2826 inuse != 0; inuse &= ~(1UL << bit)) {
2827 bit = ffs(inuse) - 1;
2828 pv = &pc->pc_pventry[field * 32 + bit];
2830 pte1p = pmap_pte1(pmap, va);
2831 if (pte1_is_section(pte1_load(pte1p)))
2833 pte2p = pmap_pte2(pmap, va);
2834 tpte2 = pte2_load(pte2p);
2835 if ((tpte2 & PTE2_W) == 0)
2836 tpte2 = pte2_load_clear(pte2p);
2837 pmap_pte2_release(pte2p);
2838 if ((tpte2 & PTE2_W) != 0)
2841 ("pmap_pv_reclaim: pmap %p va %#x zero pte",
2843 pmap_tlb_flush(pmap, va);
2844 m = PHYS_TO_VM_PAGE(pte2_pa(tpte2));
2845 if (pte2_is_dirty(tpte2))
2847 if ((tpte2 & PTE2_A) != 0)
2848 vm_page_aflag_set(m, PGA_REFERENCED);
2849 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2850 if (TAILQ_EMPTY(&m->md.pv_list) &&
2851 (m->flags & PG_FICTITIOUS) == 0) {
2852 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2853 if (TAILQ_EMPTY(&pvh->pv_list)) {
2854 vm_page_aflag_clear(m,
2858 pc->pc_map[field] |= 1UL << bit;
2859 pmap_unuse_pt2(pmap, va, &free);
2864 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2867 /* Every freed mapping is for a 4 KB page. */
2868 pmap->pm_stats.resident_count -= freed;
2869 PV_STAT(pv_entry_frees += freed);
2870 PV_STAT(pv_entry_spare += freed);
2871 pv_entry_count -= freed;
2872 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2873 for (field = 0; field < _NPCM; field++)
2874 if (pc->pc_map[field] != pc_freemask[field]) {
2875 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2877 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2880 * One freed pv entry in locked_pmap is
2883 if (pmap == locked_pmap)
2887 if (field == _NPCM) {
2888 PV_STAT(pv_entry_spare -= _NPCPV);
2889 PV_STAT(pc_chunk_count--);
2890 PV_STAT(pc_chunk_frees++);
2891 /* Entire chunk is free; return it. */
2892 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2893 pmap_qremove((vm_offset_t)pc, 1);
2894 pmap_pte2list_free(&pv_vafree, (vm_offset_t)pc);
2899 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2901 if (pmap != locked_pmap)
2904 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2905 m_pc = SLIST_FIRST(&free);
2906 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2907 /* Recycle a freed page table page. */
2908 m_pc->wire_count = 1;
2909 atomic_add_int(&vm_cnt.v_wire_count, 1);
2911 pmap_free_zero_pages(&free);
2916 free_pv_chunk(struct pv_chunk *pc)
2920 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2921 PV_STAT(pv_entry_spare -= _NPCPV);
2922 PV_STAT(pc_chunk_count--);
2923 PV_STAT(pc_chunk_frees++);
2924 /* entire chunk is free, return it */
2925 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2926 pmap_qremove((vm_offset_t)pc, 1);
2927 vm_page_unwire(m, PQ_NONE);
2929 pmap_pte2list_free(&pv_vafree, (vm_offset_t)pc);
2933 * Free the pv_entry back to the free list.
2936 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2938 struct pv_chunk *pc;
2939 int idx, field, bit;
2941 rw_assert(&pvh_global_lock, RA_WLOCKED);
2942 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2943 PV_STAT(pv_entry_frees++);
2944 PV_STAT(pv_entry_spare++);
2946 pc = pv_to_chunk(pv);
2947 idx = pv - &pc->pc_pventry[0];
2950 pc->pc_map[field] |= 1ul << bit;
2951 for (idx = 0; idx < _NPCM; idx++)
2952 if (pc->pc_map[idx] != pc_freemask[idx]) {
2954 * 98% of the time, pc is already at the head of the
2955 * list. If it isn't already, move it to the head.
2957 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2959 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2960 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2965 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2970 * Get a new pv_entry, allocating a block from the system
2974 get_pv_entry(pmap_t pmap, boolean_t try)
2976 static const struct timeval printinterval = { 60, 0 };
2977 static struct timeval lastprint;
2980 struct pv_chunk *pc;
2983 rw_assert(&pvh_global_lock, RA_WLOCKED);
2984 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2985 PV_STAT(pv_entry_allocs++);
2987 if (pv_entry_count > pv_entry_high_water)
2988 if (ratecheck(&lastprint, &printinterval))
2989 printf("Approaching the limit on PV entries, consider "
2990 "increasing either the vm.pmap.shpgperproc or the "
2991 "vm.pmap.pv_entry_max tunable.\n");
2993 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2995 for (field = 0; field < _NPCM; field++) {
2996 if (pc->pc_map[field]) {
2997 bit = ffs(pc->pc_map[field]) - 1;
3001 if (field < _NPCM) {
3002 pv = &pc->pc_pventry[field * 32 + bit];
3003 pc->pc_map[field] &= ~(1ul << bit);
3004 /* If this was the last item, move it to tail */
3005 for (field = 0; field < _NPCM; field++)
3006 if (pc->pc_map[field] != 0) {
3007 PV_STAT(pv_entry_spare--);
3008 return (pv); /* not full, return */
3010 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3011 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3012 PV_STAT(pv_entry_spare--);
3017 * Access to the pte2list "pv_vafree" is synchronized by the pvh
3018 * global lock. If "pv_vafree" is currently non-empty, it will
3019 * remain non-empty until pmap_pte2list_alloc() completes.
3021 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3022 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
3025 PV_STAT(pc_chunk_tryfail++);
3028 m = pmap_pv_reclaim(pmap);
3032 PV_STAT(pc_chunk_count++);
3033 PV_STAT(pc_chunk_allocs++);
3034 pc = (struct pv_chunk *)pmap_pte2list_alloc(&pv_vafree);
3035 pmap_qenter((vm_offset_t)pc, &m, 1);
3037 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
3038 for (field = 1; field < _NPCM; field++)
3039 pc->pc_map[field] = pc_freemask[field];
3040 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
3041 pv = &pc->pc_pventry[0];
3042 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3043 PV_STAT(pv_entry_spare += _NPCPV - 1);
3048 * Create a pv entry for page at pa for
3052 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
3056 rw_assert(&pvh_global_lock, RA_WLOCKED);
3057 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3058 pv = get_pv_entry(pmap, FALSE);
3060 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3063 static __inline pv_entry_t
3064 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3068 rw_assert(&pvh_global_lock, RA_WLOCKED);
3069 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3070 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3071 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3079 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3083 pv = pmap_pvh_remove(pvh, pmap, va);
3084 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3085 free_pv_entry(pmap, pv);
3089 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
3091 struct md_page *pvh;
3093 rw_assert(&pvh_global_lock, RA_WLOCKED);
3094 pmap_pvh_free(&m->md, pmap, va);
3095 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
3096 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3097 if (TAILQ_EMPTY(&pvh->pv_list))
3098 vm_page_aflag_clear(m, PGA_WRITEABLE);
3103 pmap_pv_demote_pte1(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3105 struct md_page *pvh;
3107 vm_offset_t va_last;
3110 rw_assert(&pvh_global_lock, RA_WLOCKED);
3111 KASSERT((pa & PTE1_OFFSET) == 0,
3112 ("pmap_pv_demote_pte1: pa is not 1mpage aligned"));
3115 * Transfer the 1mpage's pv entry for this mapping to the first
3118 pvh = pa_to_pvh(pa);
3119 va = pte1_trunc(va);
3120 pv = pmap_pvh_remove(pvh, pmap, va);
3121 KASSERT(pv != NULL, ("pmap_pv_demote_pte1: pv not found"));
3122 m = PHYS_TO_VM_PAGE(pa);
3123 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3124 /* Instantiate the remaining NPTE2_IN_PT2 - 1 pv entries. */
3125 va_last = va + PTE1_SIZE - PAGE_SIZE;
3128 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3129 ("pmap_pv_demote_pte1: page %p is not managed", m));
3131 pmap_insert_entry(pmap, va, m);
3132 } while (va < va_last);
3136 pmap_pv_promote_pte1(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3138 struct md_page *pvh;
3140 vm_offset_t va_last;
3143 rw_assert(&pvh_global_lock, RA_WLOCKED);
3144 KASSERT((pa & PTE1_OFFSET) == 0,
3145 ("pmap_pv_promote_pte1: pa is not 1mpage aligned"));
3148 * Transfer the first page's pv entry for this mapping to the
3149 * 1mpage's pv list. Aside from avoiding the cost of a call
3150 * to get_pv_entry(), a transfer avoids the possibility that
3151 * get_pv_entry() calls pmap_pv_reclaim() and that pmap_pv_reclaim()
3152 * removes one of the mappings that is being promoted.
3154 m = PHYS_TO_VM_PAGE(pa);
3155 va = pte1_trunc(va);
3156 pv = pmap_pvh_remove(&m->md, pmap, va);
3157 KASSERT(pv != NULL, ("pmap_pv_promote_pte1: pv not found"));
3158 pvh = pa_to_pvh(pa);
3159 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3160 /* Free the remaining NPTE2_IN_PT2 - 1 pv entries. */
3161 va_last = va + PTE1_SIZE - PAGE_SIZE;
3165 pmap_pvh_free(&m->md, pmap, va);
3166 } while (va < va_last);
3170 * Conditionally create a pv entry.
3173 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
3177 rw_assert(&pvh_global_lock, RA_WLOCKED);
3178 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3179 if (pv_entry_count < pv_entry_high_water &&
3180 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
3182 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3189 * Create the pv entries for each of the pages within a section.
3192 pmap_pv_insert_pte1(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3194 struct md_page *pvh;
3197 rw_assert(&pvh_global_lock, RA_WLOCKED);
3198 if (pv_entry_count < pv_entry_high_water &&
3199 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
3201 pvh = pa_to_pvh(pa);
3202 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3209 * Tries to promote the NPTE2_IN_PT2, contiguous 4KB page mappings that are
3210 * within a single page table page (PT2) to a single 1MB page mapping.
3211 * For promotion to occur, two conditions must be met: (1) the 4KB page
3212 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3213 * mappings must have identical characteristics.
3215 * Managed (PG_MANAGED) mappings within the kernel address space are not
3216 * promoted. The reason is that kernel PTE1s are replicated in each pmap but
3217 * pmap_remove_write(), pmap_clear_modify(), and pmap_clear_reference() only
3218 * read the PTE1 from the kernel pmap.
3221 pmap_promote_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3224 pt2_entry_t *fpte2p, fpte2, fpte2_fav;
3225 pt2_entry_t *pte2p, pte2;
3226 vm_offset_t pteva __unused;
3227 vm_page_t m __unused;
3229 PDEBUG(6, printf("%s(%p): try for va %#x pte1 %#x at %p\n", __func__,
3230 pmap, va, pte1_load(pte1p), pte1p));
3232 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3235 * Examine the first PTE2 in the specified PT2. Abort if this PTE2 is
3236 * either invalid, unused, or does not map the first 4KB physical page
3237 * within a 1MB page.
3239 fpte2p = pmap_pte2_quick(pmap, pte1_trunc(va));
3241 fpte2 = pte2_load(fpte2p);
3242 if ((fpte2 & ((PTE2_FRAME & PTE1_OFFSET) | PTE2_A | PTE2_V)) !=
3243 (PTE2_A | PTE2_V)) {
3244 pmap_pte1_p_failures++;
3245 CTR3(KTR_PMAP, "%s: failure(1) for va %#x in pmap %p",
3246 __func__, va, pmap);
3249 if (pte2_is_managed(fpte2) && pmap == kernel_pmap) {
3250 pmap_pte1_p_failures++;
3251 CTR3(KTR_PMAP, "%s: failure(2) for va %#x in pmap %p",
3252 __func__, va, pmap);
3255 if ((fpte2 & (PTE2_NM | PTE2_RO)) == PTE2_NM) {
3257 * When page is not modified, PTE2_RO can be set without
3258 * a TLB invalidation.
3260 * Note: When modified bit is being set, then in hardware case,
3261 * the TLB entry is re-read (updated) from PT2, and in
3262 * software case (abort), the PTE2 is read from PT2 and
3263 * TLB flushed if changed. The following cmpset() solves
3264 * any race with setting this bit in both cases.
3266 if (!pte2_cmpset(fpte2p, fpte2, fpte2 | PTE2_RO))
3272 * Examine each of the other PTE2s in the specified PT2. Abort if this
3273 * PTE2 maps an unexpected 4KB physical page or does not have identical
3274 * characteristics to the first PTE2.
3276 fpte2_fav = (fpte2 & (PTE2_FRAME | PTE2_A | PTE2_V));
3277 fpte2_fav += PTE1_SIZE - PTE2_SIZE; /* examine from the end */
3278 for (pte2p = fpte2p + NPTE2_IN_PT2 - 1; pte2p > fpte2p; pte2p--) {
3280 pte2 = pte2_load(pte2p);
3281 if ((pte2 & (PTE2_FRAME | PTE2_A | PTE2_V)) != fpte2_fav) {
3282 pmap_pte1_p_failures++;
3283 CTR3(KTR_PMAP, "%s: failure(3) for va %#x in pmap %p",
3284 __func__, va, pmap);
3287 if ((pte2 & (PTE2_NM | PTE2_RO)) == PTE2_NM) {
3289 * When page is not modified, PTE2_RO can be set
3290 * without a TLB invalidation. See note above.
3292 if (!pte2_cmpset(pte2p, pte2, pte2 | PTE2_RO))
3295 pteva = pte1_trunc(va) | (pte2 & PTE1_OFFSET &
3297 CTR3(KTR_PMAP, "%s: protect for va %#x in pmap %p",
3298 __func__, pteva, pmap);
3300 if ((pte2 & PTE2_PROMOTE) != (fpte2 & PTE2_PROMOTE)) {
3301 pmap_pte1_p_failures++;
3302 CTR3(KTR_PMAP, "%s: failure(4) for va %#x in pmap %p",
3303 __func__, va, pmap);
3307 fpte2_fav -= PTE2_SIZE;
3310 * The page table page in its current state will stay in PT2TAB
3311 * until the PTE1 mapping the section is demoted by pmap_demote_pte1()
3312 * or destroyed by pmap_remove_pte1().
3314 * Note that L2 page table size is not equal to PAGE_SIZE.
3316 m = PHYS_TO_VM_PAGE(trunc_page(pte1_link_pa(pte1_load(pte1p))));
3317 KASSERT(m >= vm_page_array && m < &vm_page_array[vm_page_array_size],
3318 ("%s: PT2 page is out of range", __func__));
3319 KASSERT(m->pindex == (pte1_index(va) & ~PT2PG_MASK),
3320 ("%s: PT2 page's pindex is wrong", __func__));
3323 * Get pte1 from pte2 format.
3325 npte1 = (fpte2 & PTE1_FRAME) | ATTR_TO_L1(fpte2) | PTE1_V;
3328 * Promote the pv entries.
3330 if (pte2_is_managed(fpte2))
3331 pmap_pv_promote_pte1(pmap, va, pte1_pa(npte1));
3336 if (pmap == kernel_pmap)
3337 pmap_kenter_pte1(va, npte1);
3339 pte1_store(pte1p, npte1);
3341 * Flush old small mappings. We call single pmap_tlb_flush() in
3342 * pmap_demote_pte1() and pmap_remove_pte1(), so we must be sure that
3343 * no small mappings survive. We assume that given pmap is current and
3344 * don't play game with PTE2_NG.
3346 pmap_tlb_flush_range(pmap, pte1_trunc(va), PTE1_SIZE);
3348 pmap_pte1_promotions++;
3349 CTR3(KTR_PMAP, "%s: success for va %#x in pmap %p",
3350 __func__, va, pmap);
3352 PDEBUG(6, printf("%s(%p): success for va %#x pte1 %#x(%#x) at %p\n",
3353 __func__, pmap, va, npte1, pte1_load(pte1p), pte1p));
3357 * Zero L2 page table page.
3359 static __inline void
3360 pmap_clear_pt2(pt2_entry_t *fpte2p)
3364 for (pte2p = fpte2p; pte2p < fpte2p + NPTE2_IN_PT2; pte2p++)
3370 * Removes a 1MB page mapping from the kernel pmap.
3373 pmap_remove_kernel_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3377 pt2_entry_t *fpte2p;
3380 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3381 m = pmap_pt2_page(pmap, va);
3384 * QQQ: Is this function called only on promoted pte1?
3385 * We certainly do section mappings directly
3386 * (without promotion) in kernel !!!
3388 panic("%s: missing pt2 page", __func__);
3390 pte1_idx = pte1_index(va);
3393 * Initialize the L2 page table.
3395 fpte2p = page_pt2(pt2map_pt2pg(va), pte1_idx);
3396 pmap_clear_pt2(fpte2p);
3399 * Remove the mapping.
3401 pt2_pa = page_pt2pa(VM_PAGE_TO_PHYS(m), pte1_idx);
3402 pmap_kenter_pte1(va, PTE1_LINK(pt2_pa));
3405 * QQQ: We do not need to invalidate PT2MAP mapping
3406 * as we did not change it. I.e. the L2 page table page
3407 * was and still is mapped the same way.
3412 * Do the things to unmap a section in a process
3415 pmap_remove_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t sva,
3416 struct spglist *free)
3419 struct md_page *pvh;
3420 vm_offset_t eva, va;
3423 PDEBUG(6, printf("%s(%p): va %#x pte1 %#x at %p\n", __func__, pmap, sva,
3424 pte1_load(pte1p), pte1p));
3426 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3427 KASSERT((sva & PTE1_OFFSET) == 0,
3428 ("%s: sva is not 1mpage aligned", __func__));
3431 * Clear and invalidate the mapping. It should occupy one and only TLB
3432 * entry. So, pmap_tlb_flush() called with aligned address should be
3435 opte1 = pte1_load_clear(pte1p);
3436 pmap_tlb_flush(pmap, sva);
3438 if (pte1_is_wired(opte1))
3439 pmap->pm_stats.wired_count -= PTE1_SIZE / PAGE_SIZE;
3440 pmap->pm_stats.resident_count -= PTE1_SIZE / PAGE_SIZE;
3441 if (pte1_is_managed(opte1)) {
3442 pvh = pa_to_pvh(pte1_pa(opte1));
3443 pmap_pvh_free(pvh, pmap, sva);
3444 eva = sva + PTE1_SIZE;
3445 for (va = sva, m = PHYS_TO_VM_PAGE(pte1_pa(opte1));
3446 va < eva; va += PAGE_SIZE, m++) {
3447 if (pte1_is_dirty(opte1))
3450 vm_page_aflag_set(m, PGA_REFERENCED);
3451 if (TAILQ_EMPTY(&m->md.pv_list) &&
3452 TAILQ_EMPTY(&pvh->pv_list))
3453 vm_page_aflag_clear(m, PGA_WRITEABLE);
3456 if (pmap == kernel_pmap) {
3458 * L2 page table(s) can't be removed from kernel map as
3459 * kernel counts on it (stuff around pmap_growkernel()).
3461 pmap_remove_kernel_pte1(pmap, pte1p, sva);
3464 * Get associated L2 page table page.
3465 * It's possible that the page was never allocated.
3467 m = pmap_pt2_page(pmap, sva);
3469 pmap_unwire_pt2_all(pmap, sva, m, free);
3474 * Fills L2 page table page with mappings to consecutive physical pages.
3476 static __inline void
3477 pmap_fill_pt2(pt2_entry_t *fpte2p, pt2_entry_t npte2)
3481 for (pte2p = fpte2p; pte2p < fpte2p + NPTE2_IN_PT2; pte2p++) {
3482 pte2_store(pte2p, npte2);
3488 * Tries to demote a 1MB page mapping. If demotion fails, the
3489 * 1MB page mapping is invalidated.
3492 pmap_demote_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3494 pt1_entry_t opte1, npte1;
3495 pt2_entry_t *fpte2p, npte2;
3496 vm_paddr_t pt2pg_pa, pt2_pa;
3498 struct spglist free;
3499 uint32_t pte1_idx, isnew = 0;
3501 PDEBUG(6, printf("%s(%p): try for va %#x pte1 %#x at %p\n", __func__,
3502 pmap, va, pte1_load(pte1p), pte1p));
3504 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3506 opte1 = pte1_load(pte1p);
3507 KASSERT(pte1_is_section(opte1), ("%s: opte1 not a section", __func__));
3509 if ((opte1 & PTE1_A) == 0 || (m = pmap_pt2_page(pmap, va)) == NULL) {
3510 KASSERT(!pte1_is_wired(opte1),
3511 ("%s: PT2 page for a wired mapping is missing", __func__));
3514 * Invalidate the 1MB page mapping and return
3515 * "failure" if the mapping was never accessed or the
3516 * allocation of the new page table page fails.
3518 if ((opte1 & PTE1_A) == 0 || (m = vm_page_alloc(NULL,
3519 pte1_index(va) & ~PT2PG_MASK, VM_ALLOC_NOOBJ |
3520 VM_ALLOC_NORMAL | VM_ALLOC_WIRED)) == NULL) {
3522 pmap_remove_pte1(pmap, pte1p, pte1_trunc(va), &free);
3523 pmap_free_zero_pages(&free);
3524 CTR3(KTR_PMAP, "%s: failure for va %#x in pmap %p",
3525 __func__, va, pmap);
3528 if (va < VM_MAXUSER_ADDRESS)
3529 pmap->pm_stats.resident_count++;
3534 * We init all L2 page tables in the page even if
3535 * we are going to change everything for one L2 page
3538 pt2pg_pa = pmap_pt2pg_init(pmap, va, m);
3540 if (va < VM_MAXUSER_ADDRESS) {
3541 if (pt2_is_empty(m, va))
3542 isnew = 1; /* Demoting section w/o promotion. */
3545 KASSERT(pt2_is_full(m, va), ("%s: bad PT2 wire"
3546 " count %u", __func__,
3547 pt2_wirecount_get(m, pte1_index(va))));
3552 pt2pg_pa = VM_PAGE_TO_PHYS(m);
3553 pte1_idx = pte1_index(va);
3555 * If the pmap is current, then the PT2MAP can provide access to
3556 * the page table page (promoted L2 page tables are not unmapped).
3557 * Otherwise, temporarily map the L2 page table page (m) into
3558 * the kernel's address space at either PADDR1 or PADDR2.
3560 * Note that L2 page table size is not equal to PAGE_SIZE.
3562 if (pmap_is_current(pmap))
3563 fpte2p = page_pt2(pt2map_pt2pg(va), pte1_idx);
3564 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
3565 if (pte2_pa(pte2_load(PMAP1)) != pt2pg_pa) {
3566 pte2_store(PMAP1, PTE2_KPT(pt2pg_pa));
3568 PMAP1cpu = PCPU_GET(cpuid);
3570 tlb_flush_local((vm_offset_t)PADDR1);
3574 if (PMAP1cpu != PCPU_GET(cpuid)) {
3575 PMAP1cpu = PCPU_GET(cpuid);
3576 tlb_flush_local((vm_offset_t)PADDR1);
3581 fpte2p = page_pt2((vm_offset_t)PADDR1, pte1_idx);
3583 mtx_lock(&PMAP2mutex);
3584 if (pte2_pa(pte2_load(PMAP2)) != pt2pg_pa) {
3585 pte2_store(PMAP2, PTE2_KPT(pt2pg_pa));
3586 tlb_flush((vm_offset_t)PADDR2);
3588 fpte2p = page_pt2((vm_offset_t)PADDR2, pte1_idx);
3590 pt2_pa = page_pt2pa(pt2pg_pa, pte1_idx);
3591 npte1 = PTE1_LINK(pt2_pa);
3593 KASSERT((opte1 & PTE1_A) != 0,
3594 ("%s: opte1 is missing PTE1_A", __func__));
3595 KASSERT((opte1 & (PTE1_NM | PTE1_RO)) != PTE1_NM,
3596 ("%s: opte1 has PTE1_NM", __func__));
3599 * Get pte2 from pte1 format.
3601 npte2 = pte1_pa(opte1) | ATTR_TO_L2(opte1) | PTE2_V;
3604 * If the L2 page table page is new, initialize it. If the mapping
3605 * has changed attributes, update the page table entries.
3608 pt2_wirecount_set(m, pte1_idx, NPTE2_IN_PT2);
3609 pmap_fill_pt2(fpte2p, npte2);
3610 } else if ((pte2_load(fpte2p) & PTE2_PROMOTE) !=
3611 (npte2 & PTE2_PROMOTE))
3612 pmap_fill_pt2(fpte2p, npte2);
3614 KASSERT(pte2_pa(pte2_load(fpte2p)) == pte2_pa(npte2),
3615 ("%s: fpte2p and npte2 map different physical addresses",
3618 if (fpte2p == PADDR2)
3619 mtx_unlock(&PMAP2mutex);
3622 * Demote the mapping. This pmap is locked. The old PTE1 has
3623 * PTE1_A set. If the old PTE1 has not PTE1_RO set, it also
3624 * has not PTE1_NM set. Thus, there is no danger of a race with
3625 * another processor changing the setting of PTE1_A and/or PTE1_NM
3626 * between the read above and the store below.
3628 if (pmap == kernel_pmap)
3629 pmap_kenter_pte1(va, npte1);
3631 pte1_store(pte1p, npte1);
3634 * Flush old big mapping. The mapping should occupy one and only
3635 * TLB entry. So, pmap_tlb_flush() called with aligned address
3636 * should be sufficient.
3638 pmap_tlb_flush(pmap, pte1_trunc(va));
3641 * Demote the pv entry. This depends on the earlier demotion
3642 * of the mapping. Specifically, the (re)creation of a per-
3643 * page pv entry might trigger the execution of pmap_pv_reclaim(),
3644 * which might reclaim a newly (re)created per-page pv entry
3645 * and destroy the associated mapping. In order to destroy
3646 * the mapping, the PTE1 must have already changed from mapping
3647 * the 1mpage to referencing the page table page.
3649 if (pte1_is_managed(opte1))
3650 pmap_pv_demote_pte1(pmap, va, pte1_pa(opte1));
3652 pmap_pte1_demotions++;
3653 CTR3(KTR_PMAP, "%s: success for va %#x in pmap %p",
3654 __func__, va, pmap);
3656 PDEBUG(6, printf("%s(%p): success for va %#x pte1 %#x(%#x) at %p\n",
3657 __func__, pmap, va, npte1, pte1_load(pte1p), pte1p));
3662 * Insert the given physical page (p) at
3663 * the specified virtual address (v) in the
3664 * target physical map with the protection requested.
3666 * If specified, the page will be wired down, meaning
3667 * that the related pte can not be reclaimed.
3669 * NB: This is the only routine which MAY NOT lazy-evaluate
3670 * or lose information. That is, this routine must actually
3671 * insert this page into the given map NOW.
3674 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3675 u_int flags, int8_t psind)
3679 pt2_entry_t npte2, opte2;
3682 vm_page_t mpte2, om;
3685 va = trunc_page(va);
3687 wired = (flags & PMAP_ENTER_WIRED) != 0;
3689 KASSERT(va <= vm_max_kernel_address, ("%s: toobig", __func__));
3690 KASSERT(va < UPT2V_MIN_ADDRESS || va >= UPT2V_MAX_ADDRESS,
3691 ("%s: invalid to pmap_enter page table pages (va: 0x%x)", __func__,
3693 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3694 VM_OBJECT_ASSERT_LOCKED(m->object);
3696 rw_wlock(&pvh_global_lock);
3701 * In the case that a page table page is not
3702 * resident, we are creating it here.
3704 if (va < VM_MAXUSER_ADDRESS) {
3705 mpte2 = pmap_allocpte2(pmap, va, flags);
3706 if (mpte2 == NULL) {
3707 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3708 ("pmap_allocpte2 failed with sleep allowed"));
3710 rw_wunlock(&pvh_global_lock);
3712 return (KERN_RESOURCE_SHORTAGE);
3715 pte1p = pmap_pte1(pmap, va);
3716 if (pte1_is_section(pte1_load(pte1p)))
3717 panic("%s: attempted on 1MB page", __func__);
3718 pte2p = pmap_pte2_quick(pmap, va);
3720 panic("%s: invalid L1 page table entry va=%#x", __func__, va);
3723 pa = VM_PAGE_TO_PHYS(m);
3724 opte2 = pte2_load(pte2p);
3725 opa = pte2_pa(opte2);
3727 * Mapping has not changed, must be protection or wiring change.
3729 if (pte2_is_valid(opte2) && (opa == pa)) {
3731 * Wiring change, just update stats. We don't worry about
3732 * wiring PT2 pages as they remain resident as long as there
3733 * are valid mappings in them. Hence, if a user page is wired,
3734 * the PT2 page will be also.
3736 if (wired && !pte2_is_wired(opte2))
3737 pmap->pm_stats.wired_count++;
3738 else if (!wired && pte2_is_wired(opte2))
3739 pmap->pm_stats.wired_count--;
3742 * Remove extra pte2 reference
3745 pt2_wirecount_dec(mpte2, pte1_index(va));
3746 if (pte2_is_managed(opte2))
3752 * QQQ: We think that changing physical address on writeable mapping
3753 * is not safe. Well, maybe on kernel address space with correct
3754 * locking, it can make a sense. However, we have no idea why
3755 * anyone should do that on user address space. Are we wrong?
3757 KASSERT((opa == 0) || (opa == pa) ||
3758 !pte2_is_valid(opte2) || ((opte2 & PTE2_RO) != 0),
3759 ("%s: pmap %p va %#x(%#x) opa %#x pa %#x - gotcha %#x %#x!",
3760 __func__, pmap, va, opte2, opa, pa, flags, prot));
3765 * Mapping has changed, invalidate old range and fall through to
3766 * handle validating new mapping.
3769 if (pte2_is_wired(opte2))
3770 pmap->pm_stats.wired_count--;
3771 if (pte2_is_managed(opte2)) {
3772 om = PHYS_TO_VM_PAGE(opa);
3773 pv = pmap_pvh_remove(&om->md, pmap, va);
3776 * Remove extra pte2 reference
3779 pt2_wirecount_dec(mpte2, va >> PTE1_SHIFT);
3781 pmap->pm_stats.resident_count++;
3784 * Enter on the PV list if part of our managed memory.
3786 if ((m->oflags & VPO_UNMANAGED) == 0) {
3787 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3788 ("%s: managed mapping within the clean submap", __func__));
3790 pv = get_pv_entry(pmap, FALSE);
3792 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3793 } else if (pv != NULL)
3794 free_pv_entry(pmap, pv);
3797 * Increment counters
3800 pmap->pm_stats.wired_count++;
3804 * Now validate mapping with desired protection/wiring.
3806 npte2 = PTE2(pa, PTE2_NM, vm_page_pte2_attr(m));
3807 if (prot & VM_PROT_WRITE) {
3808 if (pte2_is_managed(npte2))
3809 vm_page_aflag_set(m, PGA_WRITEABLE);
3813 if ((prot & VM_PROT_EXECUTE) == 0)
3817 if (va < VM_MAXUSER_ADDRESS)
3819 if (pmap != kernel_pmap)
3823 * If the mapping or permission bits are different, we need
3824 * to update the pte2.
3826 * QQQ: Think again and again what to do
3827 * if the mapping is going to be changed!
3829 if ((opte2 & ~(PTE2_NM | PTE2_A)) != (npte2 & ~(PTE2_NM | PTE2_A))) {
3831 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
3832 * is set. Do it now, before the mapping is stored and made
3833 * valid for hardware table walk. If done later, there is a race
3834 * for other threads of current process in lazy loading case.
3835 * Don't do it for kernel memory which is mapped with exec
3836 * permission even if the memory isn't going to hold executable
3837 * code. The only time when icache sync is needed is after
3838 * kernel module is loaded and the relocation info is processed.
3839 * And it's done in elf_cpu_load_file().
3841 * QQQ: (1) Does it exist any better way where
3842 * or how to sync icache?
3843 * (2) Now, we do it on a page basis.
3845 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3846 m->md.pat_mode == VM_MEMATTR_WB_WA &&
3847 (opa != pa || (opte2 & PTE2_NX)))
3848 cache_icache_sync_fresh(va, pa, PAGE_SIZE);
3851 if (flags & VM_PROT_WRITE)
3853 if (opte2 & PTE2_V) {
3854 /* Change mapping with break-before-make approach. */
3855 opte2 = pte2_load_clear(pte2p);
3856 pmap_tlb_flush(pmap, va);
3857 pte2_store(pte2p, npte2);
3858 if (opte2 & PTE2_A) {
3859 if (pte2_is_managed(opte2))
3860 vm_page_aflag_set(om, PGA_REFERENCED);
3862 if (pte2_is_dirty(opte2)) {
3863 if (pte2_is_managed(opte2))
3866 if (pte2_is_managed(opte2) &&
3867 TAILQ_EMPTY(&om->md.pv_list) &&
3868 ((om->flags & PG_FICTITIOUS) != 0 ||
3869 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3870 vm_page_aflag_clear(om, PGA_WRITEABLE);
3872 pte2_store(pte2p, npte2);
3877 * QQQ: In time when both access and not mofified bits are
3878 * emulated by software, this should not happen. Some
3879 * analysis is need, if this really happen. Missing
3880 * tlb flush somewhere could be the reason.
3882 panic("%s: pmap %p va %#x opte2 %x npte2 %x !!", __func__, pmap,
3887 * If both the L2 page table page and the reservation are fully
3888 * populated, then attempt promotion.
3890 if ((mpte2 == NULL || pt2_is_full(mpte2, va)) &&
3891 sp_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3892 vm_reserv_level_iffullpop(m) == 0)
3893 pmap_promote_pte1(pmap, pte1p, va);
3895 rw_wunlock(&pvh_global_lock);
3897 return (KERN_SUCCESS);
3901 * Do the things to unmap a page in a process.
3904 pmap_remove_pte2(pmap_t pmap, pt2_entry_t *pte2p, vm_offset_t va,
3905 struct spglist *free)
3910 rw_assert(&pvh_global_lock, RA_WLOCKED);
3911 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3913 /* Clear and invalidate the mapping. */
3914 opte2 = pte2_load_clear(pte2p);
3915 pmap_tlb_flush(pmap, va);
3917 KASSERT(pte2_is_valid(opte2), ("%s: pmap %p va %#x not link pte2 %#x",
3918 __func__, pmap, va, opte2));
3921 pmap->pm_stats.wired_count -= 1;
3922 pmap->pm_stats.resident_count -= 1;
3923 if (pte2_is_managed(opte2)) {
3924 m = PHYS_TO_VM_PAGE(pte2_pa(opte2));
3925 if (pte2_is_dirty(opte2))
3928 vm_page_aflag_set(m, PGA_REFERENCED);
3929 pmap_remove_entry(pmap, m, va);
3931 return (pmap_unuse_pt2(pmap, va, free));
3935 * Remove a single page from a process address space.
3938 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
3942 rw_assert(&pvh_global_lock, RA_WLOCKED);
3943 KASSERT(curthread->td_pinned > 0,
3944 ("%s: curthread not pinned", __func__));
3945 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3946 if ((pte2p = pmap_pte2_quick(pmap, va)) == NULL ||
3947 !pte2_is_valid(pte2_load(pte2p)))
3949 pmap_remove_pte2(pmap, pte2p, va, free);
3953 * Remove the given range of addresses from the specified map.
3955 * It is assumed that the start and end are properly
3956 * rounded to the page size.
3959 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3962 pt1_entry_t *pte1p, pte1;
3963 pt2_entry_t *pte2p, pte2;
3964 struct spglist free;
3967 * Perform an unsynchronized read. This is, however, safe.
3969 if (pmap->pm_stats.resident_count == 0)
3974 rw_wlock(&pvh_global_lock);
3979 * Special handling of removing one page. A very common
3980 * operation and easy to short circuit some code.
3982 if (sva + PAGE_SIZE == eva) {
3983 pte1 = pte1_load(pmap_pte1(pmap, sva));
3984 if (pte1_is_link(pte1)) {
3985 pmap_remove_page(pmap, sva, &free);
3990 for (; sva < eva; sva = nextva) {
3992 * Calculate address for next L2 page table.
3994 nextva = pte1_trunc(sva + PTE1_SIZE);
3997 if (pmap->pm_stats.resident_count == 0)
4000 pte1p = pmap_pte1(pmap, sva);
4001 pte1 = pte1_load(pte1p);
4004 * Weed out invalid mappings. Note: we assume that the L1 page
4005 * table is always allocated, and in kernel virtual.
4010 if (pte1_is_section(pte1)) {
4012 * Are we removing the entire large page? If not,
4013 * demote the mapping and fall through.
4015 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
4016 pmap_remove_pte1(pmap, pte1p, sva, &free);
4018 } else if (!pmap_demote_pte1(pmap, pte1p, sva)) {
4019 /* The large page mapping was destroyed. */
4024 /* Update pte1 after demotion. */
4025 pte1 = pte1_load(pte1p);
4030 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
4031 " is not link", __func__, pmap, sva, pte1, pte1p));
4034 * Limit our scan to either the end of the va represented
4035 * by the current L2 page table page, or to the end of the
4036 * range being removed.
4041 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva;
4042 pte2p++, sva += PAGE_SIZE) {
4043 pte2 = pte2_load(pte2p);
4044 if (!pte2_is_valid(pte2))
4046 if (pmap_remove_pte2(pmap, pte2p, sva, &free))
4052 rw_wunlock(&pvh_global_lock);
4054 pmap_free_zero_pages(&free);
4058 * Routine: pmap_remove_all
4060 * Removes this physical page from
4061 * all physical maps in which it resides.
4062 * Reflects back modify bits to the pager.
4065 * Original versions of this routine were very
4066 * inefficient because they iteratively called
4067 * pmap_remove (slow...)
4071 pmap_remove_all(vm_page_t m)
4073 struct md_page *pvh;
4076 pt2_entry_t *pte2p, opte2;
4079 struct spglist free;
4081 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4082 ("%s: page %p is not managed", __func__, m));
4084 rw_wlock(&pvh_global_lock);
4086 if ((m->flags & PG_FICTITIOUS) != 0)
4087 goto small_mappings;
4088 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4089 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
4093 pte1p = pmap_pte1(pmap, va);
4094 (void)pmap_demote_pte1(pmap, pte1p, va);
4098 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4101 pmap->pm_stats.resident_count--;
4102 pte1p = pmap_pte1(pmap, pv->pv_va);
4103 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found "
4104 "a 1mpage in page %p's pv list", __func__, m));
4105 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
4106 opte2 = pte2_load_clear(pte2p);
4107 pmap_tlb_flush(pmap, pv->pv_va);
4108 KASSERT(pte2_is_valid(opte2), ("%s: pmap %p va %x zero pte2",
4109 __func__, pmap, pv->pv_va));
4110 if (pte2_is_wired(opte2))
4111 pmap->pm_stats.wired_count--;
4113 vm_page_aflag_set(m, PGA_REFERENCED);
4116 * Update the vm_page_t clean and reference bits.
4118 if (pte2_is_dirty(opte2))
4120 pmap_unuse_pt2(pmap, pv->pv_va, &free);
4121 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4122 free_pv_entry(pmap, pv);
4125 vm_page_aflag_clear(m, PGA_WRITEABLE);
4127 rw_wunlock(&pvh_global_lock);
4128 pmap_free_zero_pages(&free);
4132 * Just subroutine for pmap_remove_pages() to reasonably satisfy
4133 * good coding style, a.k.a. 80 character line width limit hell.
4135 static __inline void
4136 pmap_remove_pte1_quick(pmap_t pmap, pt1_entry_t pte1, pv_entry_t pv,
4137 struct spglist *free)
4140 vm_page_t m, mt, mpt2pg;
4141 struct md_page *pvh;
4144 m = PHYS_TO_VM_PAGE(pa);
4146 KASSERT(m->phys_addr == pa, ("%s: vm_page_t %p addr mismatch %#x %#x",
4147 __func__, m, m->phys_addr, pa));
4148 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4149 m < &vm_page_array[vm_page_array_size],
4150 ("%s: bad pte1 %#x", __func__, pte1));
4152 if (pte1_is_dirty(pte1)) {
4153 for (mt = m; mt < &m[PTE1_SIZE / PAGE_SIZE]; mt++)
4157 pmap->pm_stats.resident_count -= PTE1_SIZE / PAGE_SIZE;
4158 pvh = pa_to_pvh(pa);
4159 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4160 if (TAILQ_EMPTY(&pvh->pv_list)) {
4161 for (mt = m; mt < &m[PTE1_SIZE / PAGE_SIZE]; mt++)
4162 if (TAILQ_EMPTY(&mt->md.pv_list))
4163 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4165 mpt2pg = pmap_pt2_page(pmap, pv->pv_va);
4167 pmap_unwire_pt2_all(pmap, pv->pv_va, mpt2pg, free);
4171 * Just subroutine for pmap_remove_pages() to reasonably satisfy
4172 * good coding style, a.k.a. 80 character line width limit hell.
4174 static __inline void
4175 pmap_remove_pte2_quick(pmap_t pmap, pt2_entry_t pte2, pv_entry_t pv,
4176 struct spglist *free)
4180 struct md_page *pvh;
4183 m = PHYS_TO_VM_PAGE(pa);
4185 KASSERT(m->phys_addr == pa, ("%s: vm_page_t %p addr mismatch %#x %#x",
4186 __func__, m, m->phys_addr, pa));
4187 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4188 m < &vm_page_array[vm_page_array_size],
4189 ("%s: bad pte2 %#x", __func__, pte2));
4191 if (pte2_is_dirty(pte2))
4194 pmap->pm_stats.resident_count--;
4195 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4196 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
4197 pvh = pa_to_pvh(pa);
4198 if (TAILQ_EMPTY(&pvh->pv_list))
4199 vm_page_aflag_clear(m, PGA_WRITEABLE);
4201 pmap_unuse_pt2(pmap, pv->pv_va, free);
4205 * Remove all pages from specified address space this aids process
4206 * exit speeds. Also, this code is special cased for current process
4207 * only, but can have the more generic (and slightly slower) mode enabled.
4208 * This is much faster than pmap_remove in the case of running down
4209 * an entire address space.
4212 pmap_remove_pages(pmap_t pmap)
4214 pt1_entry_t *pte1p, pte1;
4215 pt2_entry_t *pte2p, pte2;
4217 struct pv_chunk *pc, *npc;
4218 struct spglist free;
4221 uint32_t inuse, bitmask;
4225 * Assert that the given pmap is only active on the current
4226 * CPU. Unfortunately, we cannot block another CPU from
4227 * activating the pmap while this function is executing.
4229 KASSERT(pmap == vmspace_pmap(curthread->td_proc->p_vmspace),
4230 ("%s: non-current pmap %p", __func__, pmap));
4231 #if defined(SMP) && defined(INVARIANTS)
4233 cpuset_t other_cpus;
4236 other_cpus = pmap->pm_active;
4237 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
4239 KASSERT(CPU_EMPTY(&other_cpus),
4240 ("%s: pmap %p active on other cpus", __func__, pmap));
4244 rw_wlock(&pvh_global_lock);
4247 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4248 KASSERT(pc->pc_pmap == pmap, ("%s: wrong pmap %p %p",
4249 __func__, pmap, pc->pc_pmap));
4251 for (field = 0; field < _NPCM; field++) {
4252 inuse = (~(pc->pc_map[field])) & pc_freemask[field];
4253 while (inuse != 0) {
4254 bit = ffs(inuse) - 1;
4255 bitmask = 1UL << bit;
4256 idx = field * 32 + bit;
4257 pv = &pc->pc_pventry[idx];
4261 * Note that we cannot remove wired pages
4262 * from a process' mapping at this time
4264 pte1p = pmap_pte1(pmap, pv->pv_va);
4265 pte1 = pte1_load(pte1p);
4266 if (pte1_is_section(pte1)) {
4267 if (pte1_is_wired(pte1)) {
4272 pmap_remove_pte1_quick(pmap, pte1, pv,
4275 else if (pte1_is_link(pte1)) {
4276 pte2p = pt2map_entry(pv->pv_va);
4277 pte2 = pte2_load(pte2p);
4279 if (!pte2_is_valid(pte2)) {
4280 printf("%s: pmap %p va %#x "
4281 "pte2 %#x\n", __func__,
4282 pmap, pv->pv_va, pte2);
4286 if (pte2_is_wired(pte2)) {
4291 pmap_remove_pte2_quick(pmap, pte2, pv,
4294 printf("%s: pmap %p va %#x pte1 %#x\n",
4295 __func__, pmap, pv->pv_va, pte1);
4300 PV_STAT(pv_entry_frees++);
4301 PV_STAT(pv_entry_spare++);
4303 pc->pc_map[field] |= bitmask;
4307 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4311 tlb_flush_all_ng_local();
4313 rw_wunlock(&pvh_global_lock);
4315 pmap_free_zero_pages(&free);
4319 * This code makes some *MAJOR* assumptions:
4320 * 1. Current pmap & pmap exists.
4323 * 4. No L2 page table pages.
4324 * but is *MUCH* faster than pmap_enter...
4327 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4328 vm_prot_t prot, vm_page_t mpt2pg)
4330 pt2_entry_t *pte2p, pte2;
4332 struct spglist free;
4335 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
4336 (m->oflags & VPO_UNMANAGED) != 0,
4337 ("%s: managed mapping within the clean submap", __func__));
4338 rw_assert(&pvh_global_lock, RA_WLOCKED);
4339 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4342 * In the case that a L2 page table page is not
4343 * resident, we are creating it here.
4345 if (va < VM_MAXUSER_ADDRESS) {
4347 pt1_entry_t pte1, *pte1p;
4351 * Get L1 page table things.
4353 pte1_idx = pte1_index(va);
4354 pte1p = pmap_pte1(pmap, va);
4355 pte1 = pte1_load(pte1p);
4357 if (mpt2pg && (mpt2pg->pindex == (pte1_idx & ~PT2PG_MASK))) {
4359 * Each of NPT2_IN_PG L2 page tables on the page can
4360 * come here. Make sure that associated L1 page table
4361 * link is established.
4363 * QQQ: It comes that we don't establish all links to
4364 * L2 page tables for newly allocated L2 page
4367 KASSERT(!pte1_is_section(pte1),
4368 ("%s: pte1 %#x is section", __func__, pte1));
4369 if (!pte1_is_link(pte1)) {
4370 pt2_pa = page_pt2pa(VM_PAGE_TO_PHYS(mpt2pg),
4372 pte1_store(pte1p, PTE1_LINK(pt2_pa));
4374 pt2_wirecount_inc(mpt2pg, pte1_idx);
4377 * If the L2 page table page is mapped, we just
4378 * increment the hold count, and activate it.
4380 if (pte1_is_section(pte1)) {
4382 } else if (pte1_is_link(pte1)) {
4383 mpt2pg = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
4384 pt2_wirecount_inc(mpt2pg, pte1_idx);
4386 mpt2pg = _pmap_allocpte2(pmap, va,
4387 PMAP_ENTER_NOSLEEP);
4397 * This call to pt2map_entry() makes the assumption that we are
4398 * entering the page into the current pmap. In order to support
4399 * quick entry into any pmap, one would likely use pmap_pte2_quick().
4400 * But that isn't as quick as pt2map_entry().
4402 pte2p = pt2map_entry(va);
4403 pte2 = pte2_load(pte2p);
4404 if (pte2_is_valid(pte2)) {
4405 if (mpt2pg != NULL) {
4407 * Remove extra pte2 reference
4409 pt2_wirecount_dec(mpt2pg, pte1_index(va));
4416 * Enter on the PV list if part of our managed memory.
4418 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4419 !pmap_try_insert_pv_entry(pmap, va, m)) {
4420 if (mpt2pg != NULL) {
4422 if (pmap_unwire_pt2(pmap, va, mpt2pg, &free)) {
4423 pmap_tlb_flush(pmap, va);
4424 pmap_free_zero_pages(&free);
4433 * Increment counters
4435 pmap->pm_stats.resident_count++;
4438 * Now validate mapping with RO protection
4440 pa = VM_PAGE_TO_PHYS(m);
4441 l2prot = PTE2_RO | PTE2_NM;
4442 if (va < VM_MAXUSER_ADDRESS)
4443 l2prot |= PTE2_U | PTE2_NG;
4444 if ((prot & VM_PROT_EXECUTE) == 0)
4446 else if (m->md.pat_mode == VM_MEMATTR_WB_WA && pmap != kernel_pmap) {
4448 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4449 * is set. QQQ: For more info, see comments in pmap_enter().
4451 cache_icache_sync_fresh(va, pa, PAGE_SIZE);
4453 pte2_store(pte2p, PTE2(pa, l2prot, vm_page_pte2_attr(m)));
4459 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4462 rw_wlock(&pvh_global_lock);
4464 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
4465 rw_wunlock(&pvh_global_lock);
4470 * Tries to create 1MB page mapping. Returns TRUE if successful and
4471 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
4472 * blocking, (2) a mapping already exists at the specified virtual address, or
4473 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
4476 pmap_enter_pte1(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4482 rw_assert(&pvh_global_lock, RA_WLOCKED);
4483 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4484 pte1p = pmap_pte1(pmap, va);
4485 if (pte1_is_valid(pte1_load(pte1p))) {
4486 CTR3(KTR_PMAP, "%s: failure for va %#lx in pmap %p", __func__,
4490 if ((m->oflags & VPO_UNMANAGED) == 0) {
4492 * Abort this mapping if its PV entry could not be created.
4494 if (!pmap_pv_insert_pte1(pmap, va, VM_PAGE_TO_PHYS(m))) {
4495 CTR3(KTR_PMAP, "%s: failure for va %#lx in pmap %p",
4496 __func__, va, pmap);
4501 * Increment counters.
4503 pmap->pm_stats.resident_count += PTE1_SIZE / PAGE_SIZE;
4508 * QQQ: Why VM_PROT_WRITE is not evaluated and the mapping is
4511 pa = VM_PAGE_TO_PHYS(m);
4512 l1prot = PTE1_RO | PTE1_NM;
4513 if (va < VM_MAXUSER_ADDRESS)
4514 l1prot |= PTE1_U | PTE1_NG;
4515 if ((prot & VM_PROT_EXECUTE) == 0)
4517 else if (m->md.pat_mode == VM_MEMATTR_WB_WA && pmap != kernel_pmap) {
4519 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4520 * is set. QQQ: For more info, see comments in pmap_enter().
4522 cache_icache_sync_fresh(va, pa, PTE1_SIZE);
4524 pte1_store(pte1p, PTE1(pa, l1prot, ATTR_TO_L1(vm_page_pte2_attr(m))));
4526 pmap_pte1_mappings++;
4527 CTR3(KTR_PMAP, "%s: success for va %#lx in pmap %p", __func__, va,
4533 * Maps a sequence of resident pages belonging to the same object.
4534 * The sequence begins with the given page m_start. This page is
4535 * mapped at the given virtual address start. Each subsequent page is
4536 * mapped at a virtual address that is offset from start by the same
4537 * amount as the page is offset from m_start within the object. The
4538 * last page in the sequence is the page with the largest offset from
4539 * m_start that can be mapped at a virtual address less than the given
4540 * virtual address end. Not every virtual page between start and end
4541 * is mapped; only those for which a resident page exists with the
4542 * corresponding offset from m_start are mapped.
4545 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4546 vm_page_t m_start, vm_prot_t prot)
4549 vm_page_t m, mpt2pg;
4550 vm_pindex_t diff, psize;
4552 PDEBUG(6, printf("%s: pmap %p start %#x end %#x m %p prot %#x\n",
4553 __func__, pmap, start, end, m_start, prot));
4555 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4556 psize = atop(end - start);
4559 rw_wlock(&pvh_global_lock);
4561 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4562 va = start + ptoa(diff);
4563 if ((va & PTE1_OFFSET) == 0 && va + PTE1_SIZE <= end &&
4564 m->psind == 1 && sp_enabled &&
4565 pmap_enter_pte1(pmap, va, m, prot))
4566 m = &m[PTE1_SIZE / PAGE_SIZE - 1];
4568 mpt2pg = pmap_enter_quick_locked(pmap, va, m, prot,
4570 m = TAILQ_NEXT(m, listq);
4572 rw_wunlock(&pvh_global_lock);
4577 * This code maps large physical mmap regions into the
4578 * processor address space. Note that some shortcuts
4579 * are taken, but the code works.
4582 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4583 vm_pindex_t pindex, vm_size_t size)
4586 vm_paddr_t pa, pte2_pa;
4588 vm_memattr_t pat_mode;
4589 u_int l1attr, l1prot;
4591 VM_OBJECT_ASSERT_WLOCKED(object);
4592 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4593 ("%s: non-device object", __func__));
4594 if ((addr & PTE1_OFFSET) == 0 && (size & PTE1_OFFSET) == 0) {
4595 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4597 p = vm_page_lookup(object, pindex);
4598 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4599 ("%s: invalid page %p", __func__, p));
4600 pat_mode = p->md.pat_mode;
4603 * Abort the mapping if the first page is not physically
4604 * aligned to a 1MB page boundary.
4606 pte2_pa = VM_PAGE_TO_PHYS(p);
4607 if (pte2_pa & PTE1_OFFSET)
4611 * Skip the first page. Abort the mapping if the rest of
4612 * the pages are not physically contiguous or have differing
4613 * memory attributes.
4615 p = TAILQ_NEXT(p, listq);
4616 for (pa = pte2_pa + PAGE_SIZE; pa < pte2_pa + size;
4618 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4619 ("%s: invalid page %p", __func__, p));
4620 if (pa != VM_PAGE_TO_PHYS(p) ||
4621 pat_mode != p->md.pat_mode)
4623 p = TAILQ_NEXT(p, listq);
4627 * Map using 1MB pages.
4629 * QQQ: Well, we are mapping a section, so same condition must
4630 * be hold like during promotion. It looks that only RW mapping
4631 * is done here, so readonly mapping must be done elsewhere.
4633 l1prot = PTE1_U | PTE1_NG | PTE1_RW | PTE1_M | PTE1_A;
4634 l1attr = ATTR_TO_L1(vm_memattr_to_pte2(pat_mode));
4636 for (pa = pte2_pa; pa < pte2_pa + size; pa += PTE1_SIZE) {
4637 pte1p = pmap_pte1(pmap, addr);
4638 if (!pte1_is_valid(pte1_load(pte1p))) {
4639 pte1_store(pte1p, PTE1(pa, l1prot, l1attr));
4640 pmap->pm_stats.resident_count += PTE1_SIZE /
4642 pmap_pte1_mappings++;
4644 /* Else continue on if the PTE1 is already valid. */
4652 * Do the things to protect a 1mpage in a process.
4655 pmap_protect_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t sva,
4658 pt1_entry_t npte1, opte1;
4659 vm_offset_t eva, va;
4662 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4663 KASSERT((sva & PTE1_OFFSET) == 0,
4664 ("%s: sva is not 1mpage aligned", __func__));
4666 opte1 = npte1 = pte1_load(pte1p);
4667 if (pte1_is_managed(opte1)) {
4668 eva = sva + PTE1_SIZE;
4669 for (va = sva, m = PHYS_TO_VM_PAGE(pte1_pa(opte1));
4670 va < eva; va += PAGE_SIZE, m++)
4671 if (pte1_is_dirty(opte1))
4674 if ((prot & VM_PROT_WRITE) == 0)
4675 npte1 |= PTE1_RO | PTE1_NM;
4676 if ((prot & VM_PROT_EXECUTE) == 0)
4680 * QQQ: Herein, execute permission is never set.
4681 * It only can be cleared. So, no icache
4682 * syncing is needed.
4685 if (npte1 != opte1) {
4686 if (!pte1_cmpset(pte1p, opte1, npte1))
4688 pmap_tlb_flush(pmap, sva);
4693 * Set the physical protection on the
4694 * specified range of this map as requested.
4697 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
4699 boolean_t pv_lists_locked;
4701 pt1_entry_t *pte1p, pte1;
4702 pt2_entry_t *pte2p, opte2, npte2;
4704 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
4705 if (prot == VM_PROT_NONE) {
4706 pmap_remove(pmap, sva, eva);
4710 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
4711 (VM_PROT_WRITE | VM_PROT_EXECUTE))
4714 if (pmap_is_current(pmap))
4715 pv_lists_locked = FALSE;
4717 pv_lists_locked = TRUE;
4719 rw_wlock(&pvh_global_lock);
4724 for (; sva < eva; sva = nextva) {
4726 * Calculate address for next L2 page table.
4728 nextva = pte1_trunc(sva + PTE1_SIZE);
4732 pte1p = pmap_pte1(pmap, sva);
4733 pte1 = pte1_load(pte1p);
4736 * Weed out invalid mappings. Note: we assume that L1 page
4737 * page table is always allocated, and in kernel virtual.
4742 if (pte1_is_section(pte1)) {
4744 * Are we protecting the entire large page? If not,
4745 * demote the mapping and fall through.
4747 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
4748 pmap_protect_pte1(pmap, pte1p, sva, prot);
4751 if (!pv_lists_locked) {
4752 pv_lists_locked = TRUE;
4753 if (!rw_try_wlock(&pvh_global_lock)) {
4759 if (!pmap_demote_pte1(pmap, pte1p, sva)) {
4761 * The large page mapping
4768 /* Update pte1 after demotion */
4769 pte1 = pte1_load(pte1p);
4775 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
4776 " is not link", __func__, pmap, sva, pte1, pte1p));
4779 * Limit our scan to either the end of the va represented
4780 * by the current L2 page table page, or to the end of the
4781 * range being protected.
4786 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva; pte2p++,
4790 opte2 = npte2 = pte2_load(pte2p);
4791 if (!pte2_is_valid(opte2))
4794 if ((prot & VM_PROT_WRITE) == 0) {
4795 if (pte2_is_managed(opte2) &&
4796 pte2_is_dirty(opte2)) {
4797 m = PHYS_TO_VM_PAGE(pte2_pa(opte2));
4800 npte2 |= PTE2_RO | PTE2_NM;
4803 if ((prot & VM_PROT_EXECUTE) == 0)
4807 * QQQ: Herein, execute permission is never set.
4808 * It only can be cleared. So, no icache
4809 * syncing is needed.
4812 if (npte2 != opte2) {
4814 if (!pte2_cmpset(pte2p, opte2, npte2))
4816 pmap_tlb_flush(pmap, sva);
4820 if (pv_lists_locked) {
4822 rw_wunlock(&pvh_global_lock);
4828 * pmap_pvh_wired_mappings:
4830 * Return the updated number "count" of managed mappings that are wired.
4833 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4840 rw_assert(&pvh_global_lock, RA_WLOCKED);
4842 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4845 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
4846 if (pte1_is_section(pte1)) {
4847 if (pte1_is_wired(pte1))
4850 KASSERT(pte1_is_link(pte1),
4851 ("%s: pte1 %#x is not link", __func__, pte1));
4852 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
4853 if (pte2_is_wired(pte2))
4863 * pmap_page_wired_mappings:
4865 * Return the number of managed mappings to the given physical page
4869 pmap_page_wired_mappings(vm_page_t m)
4874 if ((m->oflags & VPO_UNMANAGED) != 0)
4876 rw_wlock(&pvh_global_lock);
4877 count = pmap_pvh_wired_mappings(&m->md, count);
4878 if ((m->flags & PG_FICTITIOUS) == 0) {
4879 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4882 rw_wunlock(&pvh_global_lock);
4887 * Returns TRUE if any of the given mappings were used to modify
4888 * physical memory. Otherwise, returns FALSE. Both page and 1mpage
4889 * mappings are supported.
4892 pmap_is_modified_pvh(struct md_page *pvh)
4900 rw_assert(&pvh_global_lock, RA_WLOCKED);
4903 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4906 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
4907 if (pte1_is_section(pte1)) {
4908 rv = pte1_is_dirty(pte1);
4910 KASSERT(pte1_is_link(pte1),
4911 ("%s: pte1 %#x is not link", __func__, pte1));
4912 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
4913 rv = pte2_is_dirty(pte2);
4926 * Return whether or not the specified physical page was modified
4927 * in any physical maps.
4930 pmap_is_modified(vm_page_t m)
4934 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4935 ("%s: page %p is not managed", __func__, m));
4938 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4939 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4940 * is clear, no PTE2s can have PG_M set.
4942 VM_OBJECT_ASSERT_WLOCKED(m->object);
4943 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4945 rw_wlock(&pvh_global_lock);
4946 rv = pmap_is_modified_pvh(&m->md) ||
4947 ((m->flags & PG_FICTITIOUS) == 0 &&
4948 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4949 rw_wunlock(&pvh_global_lock);
4954 * pmap_is_prefaultable:
4956 * Return whether or not the specified virtual address is eligible
4960 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4968 pte1 = pte1_load(pmap_pte1(pmap, addr));
4969 if (pte1_is_link(pte1)) {
4970 pte2 = pte2_load(pt2map_entry(addr));
4971 rv = !pte2_is_valid(pte2) ;
4978 * Returns TRUE if any of the given mappings were referenced and FALSE
4979 * otherwise. Both page and 1mpage mappings are supported.
4982 pmap_is_referenced_pvh(struct md_page *pvh)
4991 rw_assert(&pvh_global_lock, RA_WLOCKED);
4994 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4997 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
4998 if (pte1_is_section(pte1)) {
4999 rv = (pte1 & (PTE1_A | PTE1_V)) == (PTE1_A | PTE1_V);
5001 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5002 rv = (pte2 & (PTE2_A | PTE2_V)) == (PTE2_A | PTE2_V);
5013 * pmap_is_referenced:
5015 * Return whether or not the specified physical page was referenced
5016 * in any physical maps.
5019 pmap_is_referenced(vm_page_t m)
5023 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5024 ("%s: page %p is not managed", __func__, m));
5025 rw_wlock(&pvh_global_lock);
5026 rv = pmap_is_referenced_pvh(&m->md) ||
5027 ((m->flags & PG_FICTITIOUS) == 0 &&
5028 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
5029 rw_wunlock(&pvh_global_lock);
5033 #define PMAP_TS_REFERENCED_MAX 5
5036 * pmap_ts_referenced:
5038 * Return a count of reference bits for a page, clearing those bits.
5039 * It is not necessary for every reference bit to be cleared, but it
5040 * is necessary that 0 only be returned when there are truly no
5041 * reference bits set.
5043 * XXX: The exact number of bits to check and clear is a matter that
5044 * should be tested and standardized at some point in the future for
5045 * optimal aging of shared pages.
5048 pmap_ts_referenced(vm_page_t m)
5050 struct md_page *pvh;
5053 pt1_entry_t *pte1p, opte1;
5058 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5059 ("%s: page %p is not managed", __func__, m));
5060 pa = VM_PAGE_TO_PHYS(m);
5061 pvh = pa_to_pvh(pa);
5062 rw_wlock(&pvh_global_lock);
5064 if ((m->flags & PG_FICTITIOUS) != 0 ||
5065 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5066 goto small_mappings;
5071 pte1p = pmap_pte1(pmap, pv->pv_va);
5072 opte1 = pte1_load(pte1p);
5073 if ((opte1 & PTE1_A) != 0) {
5075 * Since this reference bit is shared by 256 4KB pages,
5076 * it should not be cleared every time it is tested.
5077 * Apply a simple "hash" function on the physical page
5078 * number, the virtual section number, and the pmap
5079 * address to select one 4KB page out of the 256
5080 * on which testing the reference bit will result
5081 * in clearing that bit. This function is designed
5082 * to avoid the selection of the same 4KB page
5083 * for every 1MB page mapping.
5085 * On demotion, a mapping that hasn't been referenced
5086 * is simply destroyed. To avoid the possibility of a
5087 * subsequent page fault on a demoted wired mapping,
5088 * always leave its reference bit set. Moreover,
5089 * since the section is wired, the current state of
5090 * its reference bit won't affect page replacement.
5092 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PTE1_SHIFT) ^
5093 (uintptr_t)pmap) & (NPTE2_IN_PG - 1)) == 0 &&
5094 !pte1_is_wired(opte1)) {
5095 pte1_clear_bit(pte1p, PTE1_A);
5096 pmap_tlb_flush(pmap, pv->pv_va);
5101 /* Rotate the PV list if it has more than one entry. */
5102 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5103 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5104 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5106 if (rtval >= PMAP_TS_REFERENCED_MAX)
5108 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5110 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5116 pte1p = pmap_pte1(pmap, pv->pv_va);
5117 KASSERT(pte1_is_link(pte1_load(pte1p)),
5118 ("%s: not found a link in page %p's pv list", __func__, m));
5120 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5121 if ((pte2_load(pte2p) & PTE2_A) != 0) {
5122 pte2_clear_bit(pte2p, PTE2_A);
5123 pmap_tlb_flush(pmap, pv->pv_va);
5127 /* Rotate the PV list if it has more than one entry. */
5128 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5129 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5130 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5132 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
5133 PMAP_TS_REFERENCED_MAX);
5136 rw_wunlock(&pvh_global_lock);
5141 * Clear the wired attribute from the mappings for the specified range of
5142 * addresses in the given pmap. Every valid mapping within that range
5143 * must have the wired attribute set. In contrast, invalid mappings
5144 * cannot have the wired attribute set, so they are ignored.
5146 * The wired attribute of the page table entry is not a hardware feature,
5147 * so there is no need to invalidate any TLB entries.
5150 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5153 pt1_entry_t *pte1p, pte1;
5154 pt2_entry_t *pte2p, pte2;
5155 boolean_t pv_lists_locked;
5157 if (pmap_is_current(pmap))
5158 pv_lists_locked = FALSE;
5160 pv_lists_locked = TRUE;
5162 rw_wlock(&pvh_global_lock);
5166 for (; sva < eva; sva = nextva) {
5167 nextva = pte1_trunc(sva + PTE1_SIZE);
5171 pte1p = pmap_pte1(pmap, sva);
5172 pte1 = pte1_load(pte1p);
5175 * Weed out invalid mappings. Note: we assume that L1 page
5176 * page table is always allocated, and in kernel virtual.
5181 if (pte1_is_section(pte1)) {
5182 if (!pte1_is_wired(pte1))
5183 panic("%s: pte1 %#x not wired", __func__, pte1);
5186 * Are we unwiring the entire large page? If not,
5187 * demote the mapping and fall through.
5189 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
5190 pte1_clear_bit(pte1p, PTE1_W);
5191 pmap->pm_stats.wired_count -= PTE1_SIZE /
5195 if (!pv_lists_locked) {
5196 pv_lists_locked = TRUE;
5197 if (!rw_try_wlock(&pvh_global_lock)) {
5204 if (!pmap_demote_pte1(pmap, pte1p, sva))
5205 panic("%s: demotion failed", __func__);
5208 /* Update pte1 after demotion */
5209 pte1 = pte1_load(pte1p);
5215 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
5216 " is not link", __func__, pmap, sva, pte1, pte1p));
5219 * Limit our scan to either the end of the va represented
5220 * by the current L2 page table page, or to the end of the
5221 * range being protected.
5226 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva; pte2p++,
5228 pte2 = pte2_load(pte2p);
5229 if (!pte2_is_valid(pte2))
5231 if (!pte2_is_wired(pte2))
5232 panic("%s: pte2 %#x is missing PTE2_W",
5236 * PTE2_W must be cleared atomically. Although the pmap
5237 * lock synchronizes access to PTE2_W, another processor
5238 * could be changing PTE2_NM and/or PTE2_A concurrently.
5240 pte2_clear_bit(pte2p, PTE2_W);
5241 pmap->pm_stats.wired_count--;
5244 if (pv_lists_locked) {
5246 rw_wunlock(&pvh_global_lock);
5252 * Clear the write and modified bits in each of the given page's mappings.
5255 pmap_remove_write(vm_page_t m)
5257 struct md_page *pvh;
5258 pv_entry_t next_pv, pv;
5261 pt2_entry_t *pte2p, opte2;
5264 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5265 ("%s: page %p is not managed", __func__, m));
5268 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5269 * set by another thread while the object is locked. Thus,
5270 * if PGA_WRITEABLE is clear, no page table entries need updating.
5272 VM_OBJECT_ASSERT_WLOCKED(m->object);
5273 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5275 rw_wlock(&pvh_global_lock);
5277 if ((m->flags & PG_FICTITIOUS) != 0)
5278 goto small_mappings;
5279 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5280 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5284 pte1p = pmap_pte1(pmap, va);
5285 if (!(pte1_load(pte1p) & PTE1_RO))
5286 (void)pmap_demote_pte1(pmap, pte1p, va);
5290 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5293 pte1p = pmap_pte1(pmap, pv->pv_va);
5294 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found"
5295 " a section in page %p's pv list", __func__, m));
5296 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5298 opte2 = pte2_load(pte2p);
5299 if (!(opte2 & PTE2_RO)) {
5300 if (!pte2_cmpset(pte2p, opte2,
5301 opte2 | (PTE2_RO | PTE2_NM)))
5303 if (pte2_is_dirty(opte2))
5305 pmap_tlb_flush(pmap, pv->pv_va);
5309 vm_page_aflag_clear(m, PGA_WRITEABLE);
5311 rw_wunlock(&pvh_global_lock);
5315 * Apply the given advice to the specified range of addresses within the
5316 * given pmap. Depending on the advice, clear the referenced and/or
5317 * modified flags in each mapping and set the mapped page's dirty field.
5320 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5322 pt1_entry_t *pte1p, opte1;
5323 pt2_entry_t *pte2p, pte2;
5326 boolean_t pv_lists_locked;
5328 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5330 if (pmap_is_current(pmap))
5331 pv_lists_locked = FALSE;
5333 pv_lists_locked = TRUE;
5335 rw_wlock(&pvh_global_lock);
5339 for (; sva < eva; sva = pdnxt) {
5340 pdnxt = pte1_trunc(sva + PTE1_SIZE);
5343 pte1p = pmap_pte1(pmap, sva);
5344 opte1 = pte1_load(pte1p);
5345 if (!pte1_is_valid(opte1)) /* XXX */
5347 else if (pte1_is_section(opte1)) {
5348 if (!pte1_is_managed(opte1))
5350 if (!pv_lists_locked) {
5351 pv_lists_locked = TRUE;
5352 if (!rw_try_wlock(&pvh_global_lock)) {
5358 if (!pmap_demote_pte1(pmap, pte1p, sva)) {
5360 * The large page mapping was destroyed.
5366 * Unless the page mappings are wired, remove the
5367 * mapping to a single page so that a subsequent
5368 * access may repromote. Since the underlying L2 page
5369 * table is fully populated, this removal never
5370 * frees a L2 page table page.
5372 if (!pte1_is_wired(opte1)) {
5373 pte2p = pmap_pte2_quick(pmap, sva);
5374 KASSERT(pte2_is_valid(pte2_load(pte2p)),
5375 ("%s: invalid PTE2", __func__));
5376 pmap_remove_pte2(pmap, pte2p, sva, NULL);
5381 for (pte2p = pmap_pte2_quick(pmap, sva); sva != pdnxt; pte2p++,
5383 pte2 = pte2_load(pte2p);
5384 if (!pte2_is_valid(pte2) || !pte2_is_managed(pte2))
5386 else if (pte2_is_dirty(pte2)) {
5387 if (advice == MADV_DONTNEED) {
5389 * Future calls to pmap_is_modified()
5390 * can be avoided by making the page
5393 m = PHYS_TO_VM_PAGE(pte2_pa(pte2));
5396 pte2_set_bit(pte2p, PTE2_NM);
5397 pte2_clear_bit(pte2p, PTE2_A);
5398 } else if ((pte2 & PTE2_A) != 0)
5399 pte2_clear_bit(pte2p, PTE2_A);
5402 pmap_tlb_flush(pmap, sva);
5405 if (pv_lists_locked) {
5407 rw_wunlock(&pvh_global_lock);
5413 * Clear the modify bits on the specified physical page.
5416 pmap_clear_modify(vm_page_t m)
5418 struct md_page *pvh;
5419 pv_entry_t next_pv, pv;
5421 pt1_entry_t *pte1p, opte1;
5422 pt2_entry_t *pte2p, opte2;
5425 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5426 ("%s: page %p is not managed", __func__, m));
5427 VM_OBJECT_ASSERT_WLOCKED(m->object);
5428 KASSERT(!vm_page_xbusied(m),
5429 ("%s: page %p is exclusive busy", __func__, m));
5432 * If the page is not PGA_WRITEABLE, then no PTE2s can have PTE2_NM
5433 * cleared. If the object containing the page is locked and the page
5434 * is not exclusive busied, then PGA_WRITEABLE cannot be concurrently
5437 if ((m->flags & PGA_WRITEABLE) == 0)
5439 rw_wlock(&pvh_global_lock);
5441 if ((m->flags & PG_FICTITIOUS) != 0)
5442 goto small_mappings;
5443 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5444 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5448 pte1p = pmap_pte1(pmap, va);
5449 opte1 = pte1_load(pte1p);
5450 if (!(opte1 & PTE1_RO)) {
5451 if (pmap_demote_pte1(pmap, pte1p, va) &&
5452 !pte1_is_wired(opte1)) {
5454 * Write protect the mapping to a
5455 * single page so that a subsequent
5456 * write access may repromote.
5458 va += VM_PAGE_TO_PHYS(m) - pte1_pa(opte1);
5459 pte2p = pmap_pte2_quick(pmap, va);
5460 opte2 = pte2_load(pte2p);
5461 if ((opte2 & PTE2_V)) {
5462 pte2_set_bit(pte2p, PTE2_NM | PTE2_RO);
5464 pmap_tlb_flush(pmap, va);
5471 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5474 pte1p = pmap_pte1(pmap, pv->pv_va);
5475 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found"
5476 " a section in page %p's pv list", __func__, m));
5477 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5478 if (pte2_is_dirty(pte2_load(pte2p))) {
5479 pte2_set_bit(pte2p, PTE2_NM);
5480 pmap_tlb_flush(pmap, pv->pv_va);
5485 rw_wunlock(&pvh_global_lock);
5490 * Sets the memory attribute for the specified page.
5493 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5495 struct sysmaps *sysmaps;
5499 oma = m->md.pat_mode;
5500 m->md.pat_mode = ma;
5502 CTR5(KTR_PMAP, "%s: page %p - 0x%08X oma: %d, ma: %d", __func__, m,
5503 VM_PAGE_TO_PHYS(m), oma, ma);
5504 if ((m->flags & PG_FICTITIOUS) != 0)
5508 * If "m" is a normal page, flush it from the cache.
5510 * First, try to find an existing mapping of the page by sf
5511 * buffer. sf_buf_invalidate_cache() modifies mapping and
5512 * flushes the cache.
5514 if (sf_buf_invalidate_cache(m, oma))
5518 * If page is not mapped by sf buffer, map the page
5519 * transient and do invalidation.
5522 pa = VM_PAGE_TO_PHYS(m);
5524 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
5525 mtx_lock(&sysmaps->lock);
5526 if (*sysmaps->CMAP2)
5527 panic("%s: CMAP2 busy", __func__);
5528 pte2_store(sysmaps->CMAP2, PTE2_KERN_NG(pa, PTE2_AP_KRW,
5529 vm_memattr_to_pte2(ma)));
5530 dcache_wbinv_poc((vm_offset_t)sysmaps->CADDR2, pa, PAGE_SIZE);
5531 pte2_clear(sysmaps->CMAP2);
5532 tlb_flush((vm_offset_t)sysmaps->CADDR2);
5534 mtx_unlock(&sysmaps->lock);
5539 * Miscellaneous support routines follow
5543 * Returns TRUE if the given page is mapped individually or as part of
5544 * a 1mpage. Otherwise, returns FALSE.
5547 pmap_page_is_mapped(vm_page_t m)
5551 if ((m->oflags & VPO_UNMANAGED) != 0)
5553 rw_wlock(&pvh_global_lock);
5554 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5555 ((m->flags & PG_FICTITIOUS) == 0 &&
5556 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
5557 rw_wunlock(&pvh_global_lock);
5562 * Returns true if the pmap's pv is one of the first
5563 * 16 pvs linked to from this page. This count may
5564 * be changed upwards or downwards in the future; it
5565 * is only necessary that true be returned for a small
5566 * subset of pmaps for proper page aging.
5569 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5571 struct md_page *pvh;
5576 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5577 ("%s: page %p is not managed", __func__, m));
5579 rw_wlock(&pvh_global_lock);
5580 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5581 if (PV_PMAP(pv) == pmap) {
5589 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5590 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5591 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5592 if (PV_PMAP(pv) == pmap) {
5601 rw_wunlock(&pvh_global_lock);
5606 * pmap_zero_page zeros the specified hardware page by mapping
5607 * the page into KVM and using bzero to clear its contents.
5610 pmap_zero_page(vm_page_t m)
5612 struct sysmaps *sysmaps;
5615 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
5616 mtx_lock(&sysmaps->lock);
5617 if (pte2_load(sysmaps->CMAP2) != 0)
5618 panic("%s: CMAP2 busy", __func__);
5619 pte2_store(sysmaps->CMAP2, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5620 vm_page_pte2_attr(m)));
5621 pagezero(sysmaps->CADDR2);
5622 pte2_clear(sysmaps->CMAP2);
5623 tlb_flush((vm_offset_t)sysmaps->CADDR2);
5625 mtx_unlock(&sysmaps->lock);
5629 * pmap_zero_page_area zeros the specified hardware page by mapping
5630 * the page into KVM and using bzero to clear its contents.
5632 * off and size may not cover an area beyond a single hardware page.
5635 pmap_zero_page_area(vm_page_t m, int off, int size)
5637 struct sysmaps *sysmaps;
5640 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
5641 mtx_lock(&sysmaps->lock);
5642 if (pte2_load(sysmaps->CMAP2) != 0)
5643 panic("%s: CMAP2 busy", __func__);
5644 pte2_store(sysmaps->CMAP2, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5645 vm_page_pte2_attr(m)));
5646 if (off == 0 && size == PAGE_SIZE)
5647 pagezero(sysmaps->CADDR2);
5649 bzero(sysmaps->CADDR2 + off, size);
5650 pte2_clear(sysmaps->CMAP2);
5651 tlb_flush((vm_offset_t)sysmaps->CADDR2);
5653 mtx_unlock(&sysmaps->lock);
5657 * pmap_zero_page_idle zeros the specified hardware page by mapping
5658 * the page into KVM and using bzero to clear its contents. This
5659 * is intended to be called from the vm_pagezero process only and
5663 pmap_zero_page_idle(vm_page_t m)
5666 if (pte2_load(CMAP3) != 0)
5667 panic("%s: CMAP3 busy", __func__);
5669 pte2_store(CMAP3, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5670 vm_page_pte2_attr(m)));
5673 tlb_flush((vm_offset_t)CADDR3);
5678 * pmap_copy_page copies the specified (machine independent)
5679 * page by mapping the page into virtual memory and using
5680 * bcopy to copy the page, one machine dependent page at a
5684 pmap_copy_page(vm_page_t src, vm_page_t dst)
5686 struct sysmaps *sysmaps;
5689 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
5690 mtx_lock(&sysmaps->lock);
5691 if (pte2_load(sysmaps->CMAP1) != 0)
5692 panic("%s: CMAP1 busy", __func__);
5693 if (pte2_load(sysmaps->CMAP2) != 0)
5694 panic("%s: CMAP2 busy", __func__);
5695 pte2_store(sysmaps->CMAP1, PTE2_KERN_NG(VM_PAGE_TO_PHYS(src),
5696 PTE2_AP_KR | PTE2_NM, vm_page_pte2_attr(src)));
5697 pte2_store(sysmaps->CMAP2, PTE2_KERN_NG(VM_PAGE_TO_PHYS(dst),
5698 PTE2_AP_KRW, vm_page_pte2_attr(dst)));
5699 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE);
5700 pte2_clear(sysmaps->CMAP1);
5701 tlb_flush((vm_offset_t)sysmaps->CADDR1);
5702 pte2_clear(sysmaps->CMAP2);
5703 tlb_flush((vm_offset_t)sysmaps->CADDR2);
5705 mtx_unlock(&sysmaps->lock);
5708 int unmapped_buf_allowed = 1;
5711 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5712 vm_offset_t b_offset, int xfersize)
5714 struct sysmaps *sysmaps;
5715 vm_page_t a_pg, b_pg;
5717 vm_offset_t a_pg_offset, b_pg_offset;
5721 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
5722 mtx_lock(&sysmaps->lock);
5723 if (*sysmaps->CMAP1 != 0)
5724 panic("pmap_copy_pages: CMAP1 busy");
5725 if (*sysmaps->CMAP2 != 0)
5726 panic("pmap_copy_pages: CMAP2 busy");
5727 while (xfersize > 0) {
5728 a_pg = ma[a_offset >> PAGE_SHIFT];
5729 a_pg_offset = a_offset & PAGE_MASK;
5730 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5731 b_pg = mb[b_offset >> PAGE_SHIFT];
5732 b_pg_offset = b_offset & PAGE_MASK;
5733 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5734 pte2_store(sysmaps->CMAP1, PTE2_KERN_NG(VM_PAGE_TO_PHYS(a_pg),
5735 PTE2_AP_KR | PTE2_NM, vm_page_pte2_attr(a_pg)));
5736 tlb_flush_local((vm_offset_t)sysmaps->CADDR1);
5737 pte2_store(sysmaps->CMAP2, PTE2_KERN_NG(VM_PAGE_TO_PHYS(b_pg),
5738 PTE2_AP_KRW, vm_page_pte2_attr(b_pg)));
5739 tlb_flush_local((vm_offset_t)sysmaps->CADDR2);
5740 a_cp = sysmaps->CADDR1 + a_pg_offset;
5741 b_cp = sysmaps->CADDR2 + b_pg_offset;
5742 bcopy(a_cp, b_cp, cnt);
5747 pte2_clear(sysmaps->CMAP1);
5748 tlb_flush((vm_offset_t)sysmaps->CADDR1);
5749 pte2_clear(sysmaps->CMAP2);
5750 tlb_flush((vm_offset_t)sysmaps->CADDR2);
5752 mtx_unlock(&sysmaps->lock);
5756 pmap_quick_enter_page(vm_page_t m)
5759 vm_offset_t qmap_addr;
5762 qmap_addr = PCPU_GET(qmap_addr);
5763 pte2p = pt2map_entry(qmap_addr);
5765 KASSERT(pte2_load(pte2p) == 0, ("%s: PTE2 busy", __func__));
5767 pte2_store(pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5768 vm_page_pte2_attr(m)));
5773 pmap_quick_remove_page(vm_offset_t addr)
5776 vm_offset_t qmap_addr;
5778 qmap_addr = PCPU_GET(qmap_addr);
5779 pte2p = pt2map_entry(qmap_addr);
5781 KASSERT(addr == qmap_addr, ("%s: invalid address", __func__));
5782 KASSERT(pte2_load(pte2p) != 0, ("%s: PTE2 not in use", __func__));
5785 tlb_flush(qmap_addr);
5790 * Copy the range specified by src_addr/len
5791 * from the source map to the range dst_addr/len
5792 * in the destination map.
5794 * This routine is only advisory and need not do anything.
5797 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
5798 vm_offset_t src_addr)
5800 struct spglist free;
5802 vm_offset_t end_addr = src_addr + len;
5805 if (dst_addr != src_addr)
5808 if (!pmap_is_current(src_pmap))
5811 rw_wlock(&pvh_global_lock);
5812 if (dst_pmap < src_pmap) {
5813 PMAP_LOCK(dst_pmap);
5814 PMAP_LOCK(src_pmap);
5816 PMAP_LOCK(src_pmap);
5817 PMAP_LOCK(dst_pmap);
5820 for (addr = src_addr; addr < end_addr; addr = nextva) {
5821 pt2_entry_t *src_pte2p, *dst_pte2p;
5822 vm_page_t dst_mpt2pg, src_mpt2pg;
5823 pt1_entry_t src_pte1;
5826 KASSERT(addr < VM_MAXUSER_ADDRESS,
5827 ("%s: invalid to pmap_copy page tables", __func__));
5829 nextva = pte1_trunc(addr + PTE1_SIZE);
5833 pte1_idx = pte1_index(addr);
5834 src_pte1 = src_pmap->pm_pt1[pte1_idx];
5835 if (pte1_is_section(src_pte1)) {
5836 if ((addr & PTE1_OFFSET) != 0 ||
5837 (addr + PTE1_SIZE) > end_addr)
5839 if (dst_pmap->pm_pt1[pte1_idx] == 0 &&
5840 (!pte1_is_managed(src_pte1) ||
5841 pmap_pv_insert_pte1(dst_pmap, addr,
5842 pte1_pa(src_pte1)))) {
5843 dst_pmap->pm_pt1[pte1_idx] = src_pte1 &
5845 dst_pmap->pm_stats.resident_count +=
5846 PTE1_SIZE / PAGE_SIZE;
5847 pmap_pte1_mappings++;
5850 } else if (!pte1_is_link(src_pte1))
5853 src_mpt2pg = PHYS_TO_VM_PAGE(pte1_link_pa(src_pte1));
5856 * We leave PT2s to be linked from PT1 even if they are not
5857 * referenced until all PT2s in a page are without reference.
5859 * QQQ: It could be changed ...
5861 #if 0 /* single_pt2_link_is_cleared */
5862 KASSERT(pt2_wirecount_get(src_mpt2pg, pte1_idx) > 0,
5863 ("%s: source page table page is unused", __func__));
5865 if (pt2_wirecount_get(src_mpt2pg, pte1_idx) == 0)
5868 if (nextva > end_addr)
5871 src_pte2p = pt2map_entry(addr);
5872 while (addr < nextva) {
5873 pt2_entry_t temp_pte2;
5874 temp_pte2 = pte2_load(src_pte2p);
5876 * we only virtual copy managed pages
5878 if (pte2_is_managed(temp_pte2)) {
5879 dst_mpt2pg = pmap_allocpte2(dst_pmap, addr,
5880 PMAP_ENTER_NOSLEEP);
5881 if (dst_mpt2pg == NULL)
5883 dst_pte2p = pmap_pte2_quick(dst_pmap, addr);
5884 if (!pte2_is_valid(pte2_load(dst_pte2p)) &&
5885 pmap_try_insert_pv_entry(dst_pmap, addr,
5886 PHYS_TO_VM_PAGE(pte2_pa(temp_pte2)))) {
5888 * Clear the wired, modified, and
5889 * accessed (referenced) bits
5892 temp_pte2 &= ~(PTE2_W | PTE2_A);
5893 temp_pte2 |= PTE2_NM;
5894 pte2_store(dst_pte2p, temp_pte2);
5895 dst_pmap->pm_stats.resident_count++;
5898 if (pmap_unwire_pt2(dst_pmap, addr,
5899 dst_mpt2pg, &free)) {
5900 pmap_tlb_flush(dst_pmap, addr);
5901 pmap_free_zero_pages(&free);
5905 if (pt2_wirecount_get(dst_mpt2pg, pte1_idx) >=
5906 pt2_wirecount_get(src_mpt2pg, pte1_idx))
5915 rw_wunlock(&pvh_global_lock);
5916 PMAP_UNLOCK(src_pmap);
5917 PMAP_UNLOCK(dst_pmap);
5921 * Increase the starting virtual address of the given mapping if a
5922 * different alignment might result in more section mappings.
5925 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5926 vm_offset_t *addr, vm_size_t size)
5928 vm_offset_t pte1_offset;
5930 if (size < PTE1_SIZE)
5932 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5933 offset += ptoa(object->pg_color);
5934 pte1_offset = offset & PTE1_OFFSET;
5935 if (size - ((PTE1_SIZE - pte1_offset) & PTE1_OFFSET) < PTE1_SIZE ||
5936 (*addr & PTE1_OFFSET) == pte1_offset)
5938 if ((*addr & PTE1_OFFSET) < pte1_offset)
5939 *addr = pte1_trunc(*addr) + pte1_offset;
5941 *addr = pte1_roundup(*addr) + pte1_offset;
5945 pmap_activate(struct thread *td)
5947 pmap_t pmap, oldpmap;
5950 PDEBUG(9, printf("%s: td = %08x\n", __func__, (uint32_t)td));
5953 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5954 oldpmap = PCPU_GET(curpmap);
5955 cpuid = PCPU_GET(cpuid);
5958 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5959 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5961 CPU_CLR(cpuid, &oldpmap->pm_active);
5962 CPU_SET(cpuid, &pmap->pm_active);
5965 ttb = pmap_ttb_get(pmap);
5968 * pmap_activate is for the current thread on the current cpu
5970 td->td_pcb->pcb_pagedir = ttb;
5972 PCPU_SET(curpmap, pmap);
5977 * Perform the pmap work for mincore.
5980 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5982 pt1_entry_t *pte1p, pte1;
5983 pt2_entry_t *pte2p, pte2;
5990 pte1p = pmap_pte1(pmap, addr);
5991 pte1 = pte1_load(pte1p);
5992 if (pte1_is_section(pte1)) {
5993 pa = trunc_page(pte1_pa(pte1) | (addr & PTE1_OFFSET));
5994 managed = pte1_is_managed(pte1);
5995 val = MINCORE_SUPER | MINCORE_INCORE;
5996 if (pte1_is_dirty(pte1))
5997 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5999 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6000 } else if (pte1_is_link(pte1)) {
6001 pte2p = pmap_pte2(pmap, addr);
6002 pte2 = pte2_load(pte2p);
6003 pmap_pte2_release(pte2p);
6005 managed = pte2_is_managed(pte2);
6006 val = MINCORE_INCORE;
6007 if (pte2_is_dirty(pte2))
6008 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6010 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6015 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
6016 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
6017 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
6018 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
6021 PA_UNLOCK_COND(*locked_pa);
6027 pmap_kenter_device(vm_offset_t va, vm_size_t size, vm_paddr_t pa)
6032 KASSERT((size & PAGE_MASK) == 0,
6033 ("%s: device mapping not page-sized", __func__));
6036 l2attr = vm_memattr_to_pte2(VM_MEMATTR_DEVICE);
6038 pmap_kenter_prot_attr(va, pa, PTE2_AP_KRW, l2attr);
6043 tlb_flush_range(sva, va - sva);
6047 pmap_kremove_device(vm_offset_t va, vm_size_t size)
6051 KASSERT((size & PAGE_MASK) == 0,
6052 ("%s: device mapping not page-sized", __func__));
6060 tlb_flush_range(sva, va - sva);
6064 pmap_set_pcb_pagedir(pmap_t pmap, struct pcb *pcb)
6067 pcb->pcb_pagedir = pmap_ttb_get(pmap);
6072 * Clean L1 data cache range by physical address.
6073 * The range must be within a single page.
6076 pmap_dcache_wb_pou(vm_paddr_t pa, vm_size_t size, uint32_t attr)
6078 struct sysmaps *sysmaps;
6080 KASSERT(((pa & PAGE_MASK) + size) <= PAGE_SIZE,
6081 ("%s: not on single page", __func__));
6084 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
6085 mtx_lock(&sysmaps->lock);
6086 if (*sysmaps->CMAP3)
6087 panic("%s: CMAP3 busy", __func__);
6088 pte2_store(sysmaps->CMAP3, PTE2_KERN_NG(pa, PTE2_AP_KRW, attr));
6089 dcache_wb_pou((vm_offset_t)sysmaps->CADDR3 + (pa & PAGE_MASK), size);
6090 pte2_clear(sysmaps->CMAP3);
6091 tlb_flush((vm_offset_t)sysmaps->CADDR3);
6093 mtx_unlock(&sysmaps->lock);
6097 * Sync instruction cache range which is not mapped yet.
6100 cache_icache_sync_fresh(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
6102 uint32_t len, offset;
6105 /* Write back d-cache on given address range. */
6106 offset = pa & PAGE_MASK;
6107 for ( ; size != 0; size -= len, pa += len, offset = 0) {
6108 len = min(PAGE_SIZE - offset, size);
6109 m = PHYS_TO_VM_PAGE(pa);
6110 KASSERT(m != NULL, ("%s: vm_page_t is null for %#x",
6112 pmap_dcache_wb_pou(pa, len, vm_page_pte2_attr(m));
6115 * I-cache is VIPT. Only way how to flush all virtual mappings
6116 * on given physical address is to invalidate all i-cache.
6122 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t size)
6125 /* Write back d-cache on given address range. */
6126 if (va >= VM_MIN_KERNEL_ADDRESS) {
6127 dcache_wb_pou(va, size);
6129 uint32_t len, offset;
6133 offset = va & PAGE_MASK;
6134 for ( ; size != 0; size -= len, va += len, offset = 0) {
6135 pa = pmap_extract(pmap, va); /* offset is preserved */
6136 len = min(PAGE_SIZE - offset, size);
6137 m = PHYS_TO_VM_PAGE(pa);
6138 KASSERT(m != NULL, ("%s: vm_page_t is null for %#x",
6140 pmap_dcache_wb_pou(pa, len, vm_page_pte2_attr(m));
6144 * I-cache is VIPT. Only way how to flush all virtual mappings
6145 * on given physical address is to invalidate all i-cache.
6151 * The implementation of pmap_fault() uses IN_RANGE2() macro which
6152 * depends on the fact that given range size is a power of 2.
6154 CTASSERT(powerof2(NB_IN_PT1));
6155 CTASSERT(powerof2(PT2MAP_SIZE));
6157 #define IN_RANGE2(addr, start, size) \
6158 ((vm_offset_t)(start) == ((vm_offset_t)(addr) & ~((size) - 1)))
6161 * Handle access and R/W emulation faults.
6164 pmap_fault(pmap_t pmap, vm_offset_t far, uint32_t fsr, int idx, bool usermode)
6166 pt1_entry_t *pte1p, pte1;
6167 pt2_entry_t *pte2p, pte2;
6173 * In kernel, we should never get abort with FAR which is in range of
6174 * pmap->pm_pt1 or PT2MAP address spaces. If it happens, stop here
6175 * and print out a useful abort message and even get to the debugger
6176 * otherwise it likely ends with never ending loop of aborts.
6178 if (__predict_false(IN_RANGE2(far, pmap->pm_pt1, NB_IN_PT1))) {
6180 * All L1 tables should always be mapped and present.
6181 * However, we check only current one herein. For user mode,
6182 * only permission abort from malicious user is not fatal.
6183 * And alignment abort as it may have higher priority.
6185 if (!usermode || (idx != FAULT_ALIGN && idx != FAULT_PERM_L2)) {
6186 CTR4(KTR_PMAP, "%s: pmap %#x pm_pt1 %#x far %#x",
6187 __func__, pmap, pmap->pm_pt1, far);
6188 panic("%s: pm_pt1 abort", __func__);
6190 return (KERN_INVALID_ADDRESS);
6192 if (__predict_false(IN_RANGE2(far, PT2MAP, PT2MAP_SIZE))) {
6194 * PT2MAP should be always mapped and present in current
6195 * L1 table. However, only existing L2 tables are mapped
6196 * in PT2MAP. For user mode, only L2 translation abort and
6197 * permission abort from malicious user is not fatal.
6198 * And alignment abort as it may have higher priority.
6200 if (!usermode || (idx != FAULT_ALIGN &&
6201 idx != FAULT_TRAN_L2 && idx != FAULT_PERM_L2)) {
6202 CTR4(KTR_PMAP, "%s: pmap %#x PT2MAP %#x far %#x",
6203 __func__, pmap, PT2MAP, far);
6204 panic("%s: PT2MAP abort", __func__);
6206 return (KERN_INVALID_ADDRESS);
6210 * Accesss bits for page and section. Note that the entry
6211 * is not in TLB yet, so TLB flush is not necessary.
6213 * QQQ: This is hardware emulation, we do not call userret()
6214 * for aborts from user mode.
6215 * We do not lock PMAP, so cmpset() is a need. Hopefully,
6216 * no one removes the mapping when we are here.
6218 if (idx == FAULT_ACCESS_L2) {
6219 pte2p = pt2map_entry(far);
6221 pte2 = pte2_load(pte2p);
6222 if (pte2_is_valid(pte2)) {
6223 if (!pte2_cmpset(pte2p, pte2, pte2 | PTE2_A)) {
6226 return (KERN_SUCCESS);
6229 if (idx == FAULT_ACCESS_L1) {
6230 pte1p = pmap_pte1(pmap, far);
6232 pte1 = pte1_load(pte1p);
6233 if (pte1_is_section(pte1)) {
6234 if (!pte1_cmpset(pte1p, pte1, pte1 | PTE1_A)) {
6237 return (KERN_SUCCESS);
6242 * Handle modify bits for page and section. Note that the modify
6243 * bit is emulated by software. So PTEx_RO is software read only
6244 * bit and PTEx_NM flag is real hardware read only bit.
6246 * QQQ: This is hardware emulation, we do not call userret()
6247 * for aborts from user mode.
6248 * We do not lock PMAP, so cmpset() is a need. Hopefully,
6249 * no one removes the mapping when we are here.
6251 if ((fsr & FSR_WNR) && (idx == FAULT_PERM_L2)) {
6252 pte2p = pt2map_entry(far);
6254 pte2 = pte2_load(pte2p);
6255 if (pte2_is_valid(pte2) && !(pte2 & PTE2_RO) &&
6257 if (!pte2_cmpset(pte2p, pte2, pte2 & ~PTE2_NM)) {
6260 tlb_flush(trunc_page(far));
6261 return (KERN_SUCCESS);
6264 if ((fsr & FSR_WNR) && (idx == FAULT_PERM_L1)) {
6265 pte1p = pmap_pte1(pmap, far);
6267 pte1 = pte1_load(pte1p);
6268 if (pte1_is_section(pte1) && !(pte1 & PTE1_RO) &&
6270 if (!pte1_cmpset(pte1p, pte1, pte1 & ~PTE1_NM)) {
6273 tlb_flush(pte1_trunc(far));
6274 return (KERN_SUCCESS);
6279 * QQQ: The previous code, mainly fast handling of access and
6280 * modify bits aborts, could be moved to ASM. Now we are
6281 * starting to deal with not fast aborts.
6286 * Read an entry in PT2TAB associated with both pmap and far.
6287 * It's safe because PT2TAB is always mapped.
6289 * QQQ: We do not lock PMAP, so false positives could happen if
6290 * the mapping is removed concurrently.
6292 pte2 = pt2tab_load(pmap_pt2tab_entry(pmap, far));
6293 if (pte2_is_valid(pte2)) {
6295 * Now, when we know that L2 page table is allocated,
6296 * we can use PT2MAP to get L2 page table entry.
6298 pte2 = pte2_load(pt2map_entry(far));
6299 if (pte2_is_valid(pte2)) {
6301 * If L2 page table entry is valid, make sure that
6302 * L1 page table entry is valid too. Note that we
6303 * leave L2 page entries untouched when promoted.
6305 pte1 = pte1_load(pmap_pte1(pmap, far));
6306 if (!pte1_is_valid(pte1)) {
6307 panic("%s: missing L1 page entry (%p, %#x)",
6308 __func__, pmap, far);
6313 return (KERN_FAILURE);
6316 /* !!!! REMOVE !!!! */
6317 void vector_page_setprot(int p)
6321 #if defined(PMAP_DEBUG)
6323 * Reusing of KVA used in pmap_zero_page function !!!
6326 pmap_zero_page_check(vm_page_t m)
6329 struct sysmaps *sysmaps;
6332 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
6333 mtx_lock(&sysmaps->lock);
6334 if (pte2_load(sysmaps->CMAP2) != 0)
6335 panic("%s: CMAP2 busy", __func__);
6336 pte2_store(sysmaps->CMAP2, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
6337 vm_page_pte2_attr(m)));
6338 end = (uint32_t*)(sysmaps->CADDR2 + PAGE_SIZE);
6339 for (p = (uint32_t*)sysmaps->CADDR2; p < end; p++)
6341 panic("%s: page %p not zero, va: %p", __func__, m,
6343 pte2_clear(sysmaps->CMAP2);
6344 tlb_flush((vm_offset_t)sysmaps->CADDR2);
6346 mtx_unlock(&sysmaps->lock);
6350 pmap_pid_dump(int pid)
6357 sx_slock(&allproc_lock);
6358 FOREACH_PROC_IN_SYSTEM(p) {
6359 if (p->p_pid != pid || p->p_vmspace == NULL)
6362 pmap = vmspace_pmap(p->p_vmspace);
6363 for (i = 0; i < NPTE1_IN_PT1; i++) {
6365 pt2_entry_t *pte2p, pte2;
6366 vm_offset_t base, va;
6370 base = i << PTE1_SHIFT;
6371 pte1 = pte1_load(&pmap->pm_pt1[i]);
6373 if (pte1_is_section(pte1)) {
6375 * QQQ: Do something here!
6377 } else if (pte1_is_link(pte1)) {
6378 for (j = 0; j < NPTE2_IN_PT2; j++) {
6379 va = base + (j << PAGE_SHIFT);
6380 if (va >= VM_MIN_KERNEL_ADDRESS) {
6385 sx_sunlock(&allproc_lock);
6388 pte2p = pmap_pte2(pmap, va);
6389 pte2 = pte2_load(pte2p);
6390 pmap_pte2_release(pte2p);
6391 if (!pte2_is_valid(pte2))
6395 m = PHYS_TO_VM_PAGE(pa);
6396 printf("va: 0x%x, pa: 0x%x, h: %d, w:"
6397 " %d, f: 0x%x", va, pa,
6398 m->hold_count, m->wire_count,
6412 sx_sunlock(&allproc_lock);
6419 static pt2_entry_t *
6420 pmap_pte2_ddb(pmap_t pmap, vm_offset_t va)
6423 vm_paddr_t pt2pg_pa;
6425 pte1 = pte1_load(pmap_pte1(pmap, va));
6426 if (!pte1_is_link(pte1))
6429 if (pmap_is_current(pmap))
6430 return (pt2map_entry(va));
6432 /* Note that L2 page table size is not equal to PAGE_SIZE. */
6433 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
6434 if (pte2_pa(pte2_load(PMAP3)) != pt2pg_pa) {
6435 pte2_store(PMAP3, PTE2_KPT(pt2pg_pa));
6437 PMAP3cpu = PCPU_GET(cpuid);
6439 tlb_flush_local((vm_offset_t)PADDR3);
6442 else if (PMAP3cpu != PCPU_GET(cpuid)) {
6443 PMAP3cpu = PCPU_GET(cpuid);
6444 tlb_flush_local((vm_offset_t)PADDR3);
6447 return (PADDR3 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
6451 dump_pmap(pmap_t pmap)
6454 printf("pmap %p\n", pmap);
6455 printf(" pm_pt1: %p\n", pmap->pm_pt1);
6456 printf(" pm_pt2tab: %p\n", pmap->pm_pt2tab);
6457 printf(" pm_active: 0x%08lX\n", pmap->pm_active.__bits[0]);
6460 DB_SHOW_COMMAND(pmaps, pmap_list_pmaps)
6464 LIST_FOREACH(pmap, &allpmaps, pm_list) {
6470 pte2_class(pt2_entry_t pte2)
6474 cls = (pte2 >> 2) & 0x03;
6475 cls |= (pte2 >> 4) & 0x04;
6480 dump_section(pmap_t pmap, uint32_t pte1_idx)
6485 dump_link(pmap_t pmap, uint32_t pte1_idx, boolean_t invalid_ok)
6489 pt2_entry_t *pte2p, pte2;
6492 va = pte1_idx << PTE1_SHIFT;
6493 pte2p = pmap_pte2_ddb(pmap, va);
6494 for (i = 0; i < NPTE2_IN_PT2; i++, pte2p++, va += PAGE_SIZE) {
6495 pte2 = pte2_load(pte2p);
6498 if (!pte2_is_valid(pte2)) {
6499 printf(" 0x%08X: 0x%08X", va, pte2);
6501 printf(" - not valid !!!");
6505 m = PHYS_TO_VM_PAGE(pte2_pa(pte2));
6506 printf(" 0x%08X: 0x%08X, TEX%d, s:%d, g:%d, m:%p", va , pte2,
6507 pte2_class(pte2), !!(pte2 & PTE2_S), !(pte2 & PTE2_NG), m);
6509 printf(" v:%d h:%d w:%d f:0x%04X\n", m->valid,
6510 m->hold_count, m->wire_count, m->flags);
6517 static __inline boolean_t
6518 is_pv_chunk_space(vm_offset_t va)
6521 if ((((vm_offset_t)pv_chunkbase) <= va) &&
6522 (va < ((vm_offset_t)pv_chunkbase + PAGE_SIZE * pv_maxchunks)))
6527 DB_SHOW_COMMAND(pmap, pmap_pmap_print)
6529 /* XXX convert args. */
6530 pmap_t pmap = (pmap_t)addr;
6533 vm_offset_t va, eva;
6536 boolean_t invalid_ok, dump_link_ok, dump_pv_chunk;
6541 LIST_FOREACH(pm, &allpmaps, pm_list)
6542 if (pm == pmap) break;
6544 printf("given pmap %p is not in allpmaps list\n", pmap);
6548 pmap = PCPU_GET(curpmap);
6550 eva = (modif[0] == 'u') ? VM_MAXUSER_ADDRESS : 0xFFFFFFFF;
6551 dump_pv_chunk = FALSE; /* XXX evaluate from modif[] */
6553 printf("pmap: 0x%08X\n", (uint32_t)pmap);
6554 printf("PT2MAP: 0x%08X\n", (uint32_t)PT2MAP);
6555 printf("pt2tab: 0x%08X\n", (uint32_t)pmap->pm_pt2tab);
6557 for(i = 0; i < NPTE1_IN_PT1; i++) {
6558 pte1 = pte1_load(&pmap->pm_pt1[i]);
6561 va = i << PTE1_SHIFT;
6565 if (pte1_is_section(pte1)) {
6566 printf("0x%08X: Section 0x%08X, s:%d g:%d\n", va, pte1,
6567 !!(pte1 & PTE1_S), !(pte1 & PTE1_NG));
6568 dump_section(pmap, i);
6569 } else if (pte1_is_link(pte1)) {
6570 dump_link_ok = TRUE;
6572 pte2 = pte2_load(pmap_pt2tab_entry(pmap, va));
6573 m = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
6574 printf("0x%08X: Link 0x%08X, pt2tab: 0x%08X m: %p",
6576 if (is_pv_chunk_space(va)) {
6577 printf(" - pv_chunk space");
6581 dump_link_ok = FALSE;
6584 printf(" w:%d w2:%u", m->wire_count,
6585 pt2_wirecount_get(m, pte1_index(va)));
6587 printf(" !!! pt2tab entry is ZERO");
6588 else if (pte2_pa(pte1) != pte2_pa(pte2))
6589 printf(" !!! pt2tab entry is DIFFERENT - m: %p",
6590 PHYS_TO_VM_PAGE(pte2_pa(pte2)));
6593 dump_link(pmap, i, invalid_ok);
6595 printf("0x%08X: Invalid entry 0x%08X\n", va, pte1);
6600 dump_pt2tab(pmap_t pmap)
6608 printf("PT2TAB:\n");
6609 for (i = 0; i < PT2TAB_ENTRIES; i++) {
6610 pte2 = pte2_load(&pmap->pm_pt2tab[i]);
6611 if (!pte2_is_valid(pte2))
6613 va = i << PT2TAB_SHIFT;
6615 m = PHYS_TO_VM_PAGE(pa);
6616 printf(" 0x%08X: 0x%08X, TEX%d, s:%d, m:%p", va, pte2,
6617 pte2_class(pte2), !!(pte2 & PTE2_S), m);
6619 printf(" , h: %d, w: %d, f: 0x%04X pidx: %lld",
6620 m->hold_count, m->wire_count, m->flags, m->pindex);
6625 DB_SHOW_COMMAND(pmap_pt2tab, pmap_pt2tab_print)
6627 /* XXX convert args. */
6628 pmap_t pmap = (pmap_t)addr;
6635 printf("supported only on current pmap\n");
6639 pmap = PCPU_GET(curpmap);
6640 printf("curpmap: 0x%08X\n", (uint32_t)pmap);
6641 printf("PT2MAP: 0x%08X\n", (uint32_t)PT2MAP);
6642 printf("pt2tab: 0x%08X\n", (uint32_t)pmap->pm_pt2tab);
6644 start = pte1_index((vm_offset_t)PT2MAP);
6645 for (i = start; i < (start + NPT2_IN_PT2TAB); i++) {
6646 pte1 = pte1_load(&pmap->pm_pt1[i]);
6649 va = i << PTE1_SHIFT;
6650 if (pte1_is_section(pte1)) {
6651 printf("0x%08X: Section 0x%08X, s:%d\n", va, pte1,
6653 dump_section(pmap, i);
6654 } else if (pte1_is_link(pte1)) {
6655 pte2 = pte2_load(pmap_pt2tab_entry(pmap, va));
6656 printf("0x%08X: Link 0x%08X, pt2tab: 0x%08X\n", va,
6659 printf(" !!! pt2tab entry is ZERO\n");
6661 printf("0x%08X: Invalid entry 0x%08X\n", va, pte1);