1 /* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */
3 * Copyright 2011 Semihalf
4 * Copyright 2004 Olivier Houchard.
5 * Copyright 2003 Wasabi Systems, Inc.
8 * Written by Steve C. Woodford for Wasabi Systems, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed for the NetBSD Project by
21 * Wasabi Systems, Inc.
22 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
23 * or promote products derived from this software without specific prior
26 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
38 * From: FreeBSD: src/sys/arm/arm/pmap.c,v 1.113 2009/07/24 13:50:29
42 * Copyright (c) 2002-2003 Wasabi Systems, Inc.
43 * Copyright (c) 2001 Richard Earnshaw
44 * Copyright (c) 2001-2002 Christopher Gilbert
45 * All rights reserved.
47 * 1. Redistributions of source code must retain the above copyright
48 * notice, this list of conditions and the following disclaimer.
49 * 2. Redistributions in binary form must reproduce the above copyright
50 * notice, this list of conditions and the following disclaimer in the
51 * documentation and/or other materials provided with the distribution.
52 * 3. The name of the company nor the name of the author may be used to
53 * endorse or promote products derived from this software without specific
54 * prior written permission.
56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
57 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
58 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
59 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
60 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
61 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
62 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
63 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
64 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
65 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
69 * Copyright (c) 1999 The NetBSD Foundation, Inc.
70 * All rights reserved.
72 * This code is derived from software contributed to The NetBSD Foundation
73 * by Charles M. Hannum.
75 * Redistribution and use in source and binary forms, with or without
76 * modification, are permitted provided that the following conditions
78 * 1. Redistributions of source code must retain the above copyright
79 * notice, this list of conditions and the following disclaimer.
80 * 2. Redistributions in binary form must reproduce the above copyright
81 * notice, this list of conditions and the following disclaimer in the
82 * documentation and/or other materials provided with the distribution.
84 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
85 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
86 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
87 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
88 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
89 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
90 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
91 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
92 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
93 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
94 * POSSIBILITY OF SUCH DAMAGE.
98 * Copyright (c) 1994-1998 Mark Brinicombe.
99 * Copyright (c) 1994 Brini.
100 * All rights reserved.
102 * This code is derived from software written for Brini by Mark Brinicombe
104 * Redistribution and use in source and binary forms, with or without
105 * modification, are permitted provided that the following conditions
107 * 1. Redistributions of source code must retain the above copyright
108 * notice, this list of conditions and the following disclaimer.
109 * 2. Redistributions in binary form must reproduce the above copyright
110 * notice, this list of conditions and the following disclaimer in the
111 * documentation and/or other materials provided with the distribution.
112 * 3. All advertising materials mentioning features or use of this software
113 * must display the following acknowledgement:
114 * This product includes software developed by Mark Brinicombe.
115 * 4. The name of the author may not be used to endorse or promote products
116 * derived from this software without specific prior written permission.
118 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
119 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
120 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
121 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
122 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
123 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
124 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
125 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
126 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
128 * RiscBSD kernel project
132 * Machine dependant vm stuff
138 * Special compilation symbols
139 * PMAP_DEBUG - Build in pmap_debug_level code
141 /* Include header files */
145 #include <sys/cdefs.h>
146 __FBSDID("$FreeBSD$");
147 #include <sys/param.h>
148 #include <sys/systm.h>
149 #include <sys/kernel.h>
151 #include <sys/lock.h>
152 #include <sys/proc.h>
153 #include <sys/malloc.h>
154 #include <sys/msgbuf.h>
155 #include <sys/mutex.h>
156 #include <sys/vmmeter.h>
157 #include <sys/mman.h>
158 #include <sys/rwlock.h>
160 #include <sys/sched.h>
163 #include <vm/vm_param.h>
166 #include <vm/vm_kern.h>
167 #include <vm/vm_object.h>
168 #include <vm/vm_map.h>
169 #include <vm/vm_page.h>
170 #include <vm/vm_pageout.h>
171 #include <vm/vm_extern.h>
173 #include <machine/md_var.h>
174 #include <machine/cpu.h>
175 #include <machine/cpufunc.h>
176 #include <machine/pcb.h>
179 extern int last_fault_code;
183 #define PDEBUG(_lev_,_stat_) \
184 if (pmap_debug_level >= (_lev_)) \
186 #define dprintf printf
188 int pmap_debug_level = 0;
190 #else /* PMAP_DEBUG */
191 #define PDEBUG(_lev_,_stat_) /* Nothing */
192 #define dprintf(x, arg...)
193 #define PMAP_INLINE __inline
194 #endif /* PMAP_DEBUG */
197 #define pmap_l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range((pa), (size))
198 #define pmap_l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range((pa), (size))
200 #define pmap_l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range((va), (size))
201 #define pmap_l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range((va), (size))
204 extern struct pv_addr systempage;
207 * Internal function prototypes
209 static void pmap_free_pv_entry (pv_entry_t);
210 static pv_entry_t pmap_get_pv_entry(void);
212 static void pmap_enter_locked(pmap_t, vm_offset_t, vm_page_t,
213 vm_prot_t, boolean_t, int);
214 static vm_paddr_t pmap_extract_locked(pmap_t pmap, vm_offset_t va);
215 static void pmap_alloc_l1(pmap_t);
216 static void pmap_free_l1(pmap_t);
218 static int pmap_clearbit(struct vm_page *, u_int);
220 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t);
221 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t);
222 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int);
223 static vm_offset_t kernel_pt_lookup(vm_paddr_t);
225 static MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1");
227 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
228 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
229 vm_offset_t pmap_curmaxkvaddr;
230 vm_paddr_t kernel_l1pa;
232 vm_offset_t kernel_vm_end = 0;
234 vm_offset_t vm_max_kernel_address;
236 struct pmap kernel_pmap_store;
238 static pt_entry_t *csrc_pte, *cdst_pte;
239 static vm_offset_t csrcp, cdstp;
240 static struct mtx cmtx;
242 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *);
244 * These routines are called when the CPU type is identified to set up
245 * the PTE prototypes, cache modes, etc.
247 * The variables are always here, just in case LKMs need to reference
248 * them (though, they shouldn't).
250 static void pmap_set_prot(pt_entry_t *pte, vm_prot_t prot, uint8_t user);
251 pt_entry_t pte_l1_s_cache_mode;
252 pt_entry_t pte_l1_s_cache_mode_pt;
254 pt_entry_t pte_l2_l_cache_mode;
255 pt_entry_t pte_l2_l_cache_mode_pt;
257 pt_entry_t pte_l2_s_cache_mode;
258 pt_entry_t pte_l2_s_cache_mode_pt;
260 struct msgbuf *msgbufp = 0;
265 static caddr_t crashdumpmap;
267 extern void bcopy_page(vm_offset_t, vm_offset_t);
268 extern void bzero_page(vm_offset_t);
273 * Metadata for L1 translation tables.
276 /* Entry on the L1 Table list */
277 SLIST_ENTRY(l1_ttable) l1_link;
279 /* Entry on the L1 Least Recently Used list */
280 TAILQ_ENTRY(l1_ttable) l1_lru;
282 /* Track how many domains are allocated from this L1 */
283 volatile u_int l1_domain_use_count;
286 * A free-list of domain numbers for this L1.
287 * We avoid using ffs() and a bitmap to track domains since ffs()
290 u_int8_t l1_domain_first;
291 u_int8_t l1_domain_free[PMAP_DOMAINS];
293 /* Physical address of this L1 page table */
294 vm_paddr_t l1_physaddr;
296 /* KVA of this L1 page table */
301 * Convert a virtual address into its L1 table index. That is, the
302 * index used to locate the L2 descriptor table pointer in an L1 table.
303 * This is basically used to index l1->l1_kva[].
305 * Each L2 descriptor table represents 1MB of VA space.
307 #define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT)
310 * L1 Page Tables are tracked using a Least Recently Used list.
311 * - New L1s are allocated from the HEAD.
312 * - Freed L1s are added to the TAIl.
313 * - Recently accessed L1s (where an 'access' is some change to one of
314 * the userland pmaps which owns this L1) are moved to the TAIL.
316 static TAILQ_HEAD(, l1_ttable) l1_lru_list;
318 * A list of all L1 tables
320 static SLIST_HEAD(, l1_ttable) l1_list;
321 static struct mtx l1_lru_lock;
324 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots.
326 * This is normally 16MB worth L2 page descriptors for any given pmap.
327 * Reference counts are maintained for L2 descriptors so they can be
331 /* The number of L2 page descriptors allocated to this l2_dtable */
334 /* List of L2 page descriptors */
336 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */
337 vm_paddr_t l2b_phys; /* Physical address of same */
338 u_short l2b_l1idx; /* This L2 table's L1 index */
339 u_short l2b_occupancy; /* How many active descriptors */
340 } l2_bucket[L2_BUCKET_SIZE];
343 /* pmap_kenter_internal flags */
344 #define KENTER_CACHE 0x1
345 #define KENTER_USER 0x2
348 * Given an L1 table index, calculate the corresponding l2_dtable index
349 * and bucket index within the l2_dtable.
351 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \
353 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1))
356 * Given a virtual address, this macro returns the
357 * virtual address required to drop into the next L2 bucket.
359 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE)
362 * We try to map the page tables write-through, if possible. However, not
363 * all CPUs have a write-through cache mode, so on those we have to sync
364 * the cache when we frob page tables.
366 * We try to evaluate this at compile time, if possible. However, it's
367 * not always possible to do that, hence this run-time var.
369 int pmap_needs_pte_sync;
372 * Macro to determine if a mapping might be resident in the
373 * instruction cache and/or TLB
375 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC))
378 * Macro to determine if a mapping might be resident in the
379 * data cache and/or TLB
381 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0)
383 #ifndef PMAP_SHPGPERPROC
384 #define PMAP_SHPGPERPROC 200
387 #define pmap_is_current(pm) ((pm) == pmap_kernel() || \
388 curproc->p_vmspace->vm_map.pmap == (pm))
389 static uma_zone_t pvzone = NULL;
391 static uma_zone_t l2table_zone;
392 static vm_offset_t pmap_kernel_l2dtable_kva;
393 static vm_offset_t pmap_kernel_l2ptp_kva;
394 static vm_paddr_t pmap_kernel_l2ptp_phys;
395 static int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0;
396 static struct rwlock pvh_global_lock;
398 int l1_mem_types[] = {
400 ARM_L1S_DEVICE_NOSHARE,
401 ARM_L1S_DEVICE_SHARE,
402 ARM_L1S_NRML_NOCACHE,
403 ARM_L1S_NRML_IWT_OWT,
404 ARM_L1S_NRML_IWB_OWB,
405 ARM_L1S_NRML_IWBA_OWBA
408 int l2l_mem_types[] = {
410 ARM_L2L_DEVICE_NOSHARE,
411 ARM_L2L_DEVICE_SHARE,
412 ARM_L2L_NRML_NOCACHE,
413 ARM_L2L_NRML_IWT_OWT,
414 ARM_L2L_NRML_IWB_OWB,
415 ARM_L2L_NRML_IWBA_OWBA
418 int l2s_mem_types[] = {
420 ARM_L2S_DEVICE_NOSHARE,
421 ARM_L2S_DEVICE_SHARE,
422 ARM_L2S_NRML_NOCACHE,
423 ARM_L2S_NRML_IWT_OWT,
424 ARM_L2S_NRML_IWB_OWB,
425 ARM_L2S_NRML_IWBA_OWBA
429 * This list exists for the benefit of pmap_map_chunk(). It keeps track
430 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can
431 * find them as necessary.
433 * Note that the data on this list MUST remain valid after initarm() returns,
434 * as pmap_bootstrap() uses it to contruct L2 table metadata.
436 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list);
439 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt)
444 l1->l1_domain_use_count = 0;
445 l1->l1_domain_first = 0;
447 for (i = 0; i < PMAP_DOMAINS; i++)
448 l1->l1_domain_free[i] = i + 1;
451 * Copy the kernel's L1 entries to each new L1.
453 if (l1pt != pmap_kernel()->pm_l1->l1_kva)
454 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE);
456 if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0)
457 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt);
458 SLIST_INSERT_HEAD(&l1_list, l1, l1_link);
459 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
463 kernel_pt_lookup(vm_paddr_t pa)
467 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) {
475 pmap_pte_init_mmu_v6(void)
478 if (PTE_PAGETABLE >= 3)
479 pmap_needs_pte_sync = 1;
480 pte_l1_s_cache_mode = l1_mem_types[PTE_CACHE];
481 pte_l2_l_cache_mode = l2l_mem_types[PTE_CACHE];
482 pte_l2_s_cache_mode = l2s_mem_types[PTE_CACHE];
484 pte_l1_s_cache_mode_pt = l1_mem_types[PTE_PAGETABLE];
485 pte_l2_l_cache_mode_pt = l2l_mem_types[PTE_PAGETABLE];
486 pte_l2_s_cache_mode_pt = l2s_mem_types[PTE_PAGETABLE];
491 * Allocate an L1 translation table for the specified pmap.
492 * This is called at pmap creation time.
495 pmap_alloc_l1(pmap_t pm)
497 struct l1_ttable *l1;
501 * Remove the L1 at the head of the LRU list
503 mtx_lock(&l1_lru_lock);
504 l1 = TAILQ_FIRST(&l1_lru_list);
505 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
508 * Pick the first available domain number, and update
509 * the link to the next number.
511 domain = l1->l1_domain_first;
512 l1->l1_domain_first = l1->l1_domain_free[domain];
515 * If there are still free domain numbers in this L1,
516 * put it back on the TAIL of the LRU list.
518 if (++l1->l1_domain_use_count < PMAP_DOMAINS)
519 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
521 mtx_unlock(&l1_lru_lock);
524 * Fix up the relevant bits in the pmap structure
527 pm->pm_domain = domain + 1;
531 * Free an L1 translation table.
532 * This is called at pmap destruction time.
535 pmap_free_l1(pmap_t pm)
537 struct l1_ttable *l1 = pm->pm_l1;
539 mtx_lock(&l1_lru_lock);
542 * If this L1 is currently on the LRU list, remove it.
544 if (l1->l1_domain_use_count < PMAP_DOMAINS)
545 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
548 * Free up the domain number which was allocated to the pmap
550 l1->l1_domain_free[pm->pm_domain - 1] = l1->l1_domain_first;
551 l1->l1_domain_first = pm->pm_domain - 1;
552 l1->l1_domain_use_count--;
555 * The L1 now must have at least 1 free domain, so add
556 * it back to the LRU list. If the use count is zero,
557 * put it at the head of the list, otherwise it goes
560 if (l1->l1_domain_use_count == 0) {
561 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru);
563 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
565 mtx_unlock(&l1_lru_lock);
569 * Returns a pointer to the L2 bucket associated with the specified pmap
570 * and VA, or NULL if no L2 bucket exists for the address.
572 static PMAP_INLINE struct l2_bucket *
573 pmap_get_l2_bucket(pmap_t pm, vm_offset_t va)
575 struct l2_dtable *l2;
576 struct l2_bucket *l2b;
581 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL ||
582 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL)
589 * Returns a pointer to the L2 bucket associated with the specified pmap
592 * If no L2 bucket exists, perform the necessary allocations to put an L2
593 * bucket/page table in place.
595 * Note that if a new L2 bucket/page was allocated, the caller *must*
596 * increment the bucket occupancy counter appropriately *before*
597 * releasing the pmap's lock to ensure no other thread or cpu deallocates
598 * the bucket/page in the meantime.
600 static struct l2_bucket *
601 pmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va)
603 struct l2_dtable *l2;
604 struct l2_bucket *l2b;
609 PMAP_ASSERT_LOCKED(pm);
610 rw_assert(&pvh_global_lock, RA_WLOCKED);
611 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
613 * No mapping at this address, as there is
614 * no entry in the L1 table.
615 * Need to allocate a new l2_dtable.
618 rw_wunlock(&pvh_global_lock);
619 if ((l2 = uma_zalloc(l2table_zone, M_NOWAIT)) == NULL) {
620 rw_wlock(&pvh_global_lock);
624 rw_wlock(&pvh_global_lock);
626 if (pm->pm_l2[L2_IDX(l1idx)] != NULL) {
628 * Someone already allocated the l2_dtable while
629 * we were doing the same.
631 uma_zfree(l2table_zone, l2);
632 l2 = pm->pm_l2[L2_IDX(l1idx)];
634 bzero(l2, sizeof(*l2));
636 * Link it into the parent pmap
638 pm->pm_l2[L2_IDX(l1idx)] = l2;
642 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
645 * Fetch pointer to the L2 page table associated with the address.
647 if (l2b->l2b_kva == NULL) {
651 * No L2 page table has been allocated. Chances are, this
652 * is because we just allocated the l2_dtable, above.
655 rw_wunlock(&pvh_global_lock);
656 ptep = uma_zalloc(l2zone, M_NOWAIT);
657 rw_wlock(&pvh_global_lock);
659 if (l2b->l2b_kva != 0) {
660 /* We lost the race. */
661 uma_zfree(l2zone, ptep);
664 l2b->l2b_phys = vtophys(ptep);
667 * Oops, no more L2 page tables available at this
668 * time. We may need to deallocate the l2_dtable
669 * if we allocated a new one above.
671 if (l2->l2_occupancy == 0) {
672 pm->pm_l2[L2_IDX(l1idx)] = NULL;
673 uma_zfree(l2table_zone, l2);
680 l2b->l2b_l1idx = l1idx;
686 static PMAP_INLINE void
687 pmap_free_l2_ptp(pt_entry_t *l2)
689 uma_zfree(l2zone, l2);
692 * One or more mappings in the specified L2 descriptor table have just been
695 * Garbage collect the metadata and descriptor table itself if necessary.
697 * The pmap lock must be acquired when this is called (not necessary
698 * for the kernel pmap).
701 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count)
703 struct l2_dtable *l2;
704 pd_entry_t *pl1pd, l1pd;
710 * Update the bucket's reference count according to how many
711 * PTEs the caller has just invalidated.
713 l2b->l2b_occupancy -= count;
718 * Level 2 page tables allocated to the kernel pmap are never freed
719 * as that would require checking all Level 1 page tables and
720 * removing any references to the Level 2 page table. See also the
721 * comment elsewhere about never freeing bootstrap L2 descriptors.
723 * We make do with just invalidating the mapping in the L2 table.
725 * This isn't really a big deal in practice and, in fact, leads
726 * to a performance win over time as we don't need to continually
729 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel())
733 * There are no more valid mappings in this level 2 page table.
734 * Go ahead and NULL-out the pointer in the bucket, then
735 * free the page table.
737 l1idx = l2b->l2b_l1idx;
741 pl1pd = &pm->pm_l1->l1_kva[l1idx];
744 * If the L1 slot matches the pmap's domain
745 * number, then invalidate it.
747 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK);
748 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) {
754 * Release the L2 descriptor table back to the pool cache.
756 pmap_free_l2_ptp(ptep);
759 * Update the reference count in the associated l2_dtable
761 l2 = pm->pm_l2[L2_IDX(l1idx)];
762 if (--l2->l2_occupancy > 0)
766 * There are no more valid mappings in any of the Level 1
767 * slots managed by this l2_dtable. Go ahead and NULL-out
768 * the pointer in the parent pmap and free the l2_dtable.
770 pm->pm_l2[L2_IDX(l1idx)] = NULL;
771 uma_zfree(l2table_zone, l2);
775 * Pool cache constructors for L2 descriptor tables, metadata and pmap
779 pmap_l2ptp_ctor(void *mem, int size, void *arg, int flags)
781 struct l2_bucket *l2b;
782 pt_entry_t *ptep, pte;
783 vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK;
786 * The mappings for these page tables were initially made using
787 * pmap_kenter() by the pool subsystem. Therefore, the cache-
788 * mode will not be right for page table mappings. To avoid
789 * polluting the pmap_kenter() code with a special case for
790 * page tables, we simply fix up the cache-mode here if it's not
793 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
794 ptep = &l2b->l2b_kva[l2pte_index(va)];
797 cpu_idcache_wbinv_range(va, PAGE_SIZE);
798 pmap_l2cache_wbinv_range(va, pte & L2_S_FRAME, PAGE_SIZE);
799 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
801 * Page tables must have the cache-mode set to
804 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
806 cpu_tlb_flushD_SE(va);
810 memset(mem, 0, L2_TABLE_SIZE_REAL);
815 * Modify pte bits for all ptes corresponding to the given physical address.
816 * We use `maskbits' rather than `clearbits' because we're always passing
817 * constants and the latter would require an extra inversion at run-time.
820 pmap_clearbit(struct vm_page *pg, u_int maskbits)
822 struct l2_bucket *l2b;
824 pt_entry_t *ptep, npte, opte;
830 rw_wlock(&pvh_global_lock);
832 if (maskbits & PVF_WRITE)
835 * Clear saved attributes (modify, reference)
837 pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF));
839 if (TAILQ_EMPTY(&pg->md.pv_list)) {
840 rw_wunlock(&pvh_global_lock);
845 * Loop over all current mappings setting/clearing as appropos
847 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
850 oflags = pv->pv_flags;
851 pv->pv_flags &= ~maskbits;
855 l2b = pmap_get_l2_bucket(pm, va);
857 ptep = &l2b->l2b_kva[l2pte_index(va)];
860 if ((maskbits & (PVF_WRITE|PVF_MOD)) && L2_S_WRITABLE(opte)) {
863 /* make the pte read only */
867 if (maskbits & PVF_REF) {
869 * Make the PTE invalid so that we will take a
870 * page fault the next time the mapping is
873 npte &= ~L2_TYPE_MASK;
877 CTR4(KTR_PMAP,"clearbit: pmap:%p bits:%x pte:%x->%x",
878 pm, maskbits, opte, npte);
883 /* Flush the TLB entry if a current pmap. */
884 if (PV_BEEN_EXECD(oflags))
885 cpu_tlb_flushID_SE(pv->pv_va);
886 else if (PV_BEEN_REFD(oflags))
887 cpu_tlb_flushD_SE(pv->pv_va);
894 if (maskbits & PVF_WRITE)
895 vm_page_aflag_clear(pg, PGA_WRITEABLE);
896 rw_wunlock(&pvh_global_lock);
901 * main pv_entry manipulation functions:
902 * pmap_enter_pv: enter a mapping onto a vm_page list
903 * pmap_remove_pv: remove a mappiing from a vm_page list
905 * NOTE: pmap_enter_pv expects to lock the pvh itself
906 * pmap_remove_pv expects the caller to lock the pvh before calling
910 * pmap_enter_pv: enter a mapping onto a vm_page's PV list
912 * => caller should hold the proper lock on pvh_global_lock
913 * => caller should have pmap locked
914 * => we will (someday) gain the lock on the vm_page's PV list
915 * => caller should adjust ptp's wire_count before calling
916 * => caller should not adjust pmap's wire_count
919 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm,
920 vm_offset_t va, u_int flags)
923 rw_assert(&pvh_global_lock, RA_WLOCKED);
925 PMAP_ASSERT_LOCKED(pm);
928 pve->pv_flags = flags;
930 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list);
931 TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist);
932 pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD);
933 if (pve->pv_flags & PVF_WIRED)
934 ++pm->pm_stats.wired_count;
935 vm_page_aflag_set(pg, PGA_REFERENCED);
940 * pmap_find_pv: Find a pv entry
942 * => caller should hold lock on vm_page
944 static PMAP_INLINE struct pv_entry *
945 pmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
949 rw_assert(&pvh_global_lock, RA_WLOCKED);
950 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list)
951 if (pm == pv->pv_pmap && va == pv->pv_va)
957 * vector_page_setprot:
959 * Manipulate the protection of the vector page.
962 vector_page_setprot(int prot)
964 struct l2_bucket *l2b;
967 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page);
969 ptep = &l2b->l2b_kva[l2pte_index(vector_page)];
971 pmap_set_prot(ptep, prot|VM_PROT_EXECUTE, 0);
973 cpu_tlb_flushD_SE(vector_page);
978 pmap_set_prot(pt_entry_t *ptep, vm_prot_t prot, uint8_t user)
981 *ptep &= ~L2_S_PROT_MASK;
983 if (!(prot & VM_PROT_EXECUTE))
986 *ptep |= L2_S_PROT_R;
989 *ptep |= L2_S_PROT_U;
991 if (prot & VM_PROT_WRITE)
996 * pmap_remove_pv: try to remove a mapping from a pv_list
998 * => caller should hold proper lock on pmap_main_lock
999 * => pmap should be locked
1000 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1001 * => caller should adjust ptp's wire_count and free PTP if needed
1002 * => caller should NOT adjust pmap's wire_count
1003 * => we return the removed pve
1007 pmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve)
1010 rw_assert(&pvh_global_lock, RA_WLOCKED);
1011 PMAP_ASSERT_LOCKED(pm);
1013 TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list);
1014 TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist);
1016 if (pve->pv_flags & PVF_WIRED)
1017 --pm->pm_stats.wired_count;
1019 if (pg->md.pvh_attrs & PVF_MOD)
1022 if (TAILQ_FIRST(&pg->md.pv_list) == NULL)
1023 pg->md.pvh_attrs &= ~PVF_REF;
1025 vm_page_aflag_set(pg, PGA_REFERENCED);
1027 if (pve->pv_flags & PVF_WRITE) {
1028 TAILQ_FOREACH(pve, &pg->md.pv_list, pv_list)
1029 if (pve->pv_flags & PVF_WRITE)
1032 pg->md.pvh_attrs &= ~PVF_MOD;
1033 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1038 static struct pv_entry *
1039 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1041 struct pv_entry *pve;
1043 rw_assert(&pvh_global_lock, RA_WLOCKED);
1044 pve = TAILQ_FIRST(&pg->md.pv_list);
1047 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */
1048 pmap_nuke_pv(pg, pm, pve);
1051 pve = TAILQ_NEXT(pve, pv_list);
1054 return(pve); /* return removed pve */
1059 * pmap_modify_pv: Update pv flags
1061 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1062 * => caller should NOT adjust pmap's wire_count
1063 * => we return the old flags
1065 * Modify a physical-virtual mapping in the pv table
1068 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va,
1069 u_int clr_mask, u_int set_mask)
1071 struct pv_entry *npv;
1072 u_int flags, oflags;
1074 PMAP_ASSERT_LOCKED(pm);
1075 rw_assert(&pvh_global_lock, RA_WLOCKED);
1076 if ((npv = pmap_find_pv(pg, pm, va)) == NULL)
1080 * There is at least one VA mapping this page.
1083 if (clr_mask & (PVF_REF | PVF_MOD))
1084 pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD);
1086 oflags = npv->pv_flags;
1087 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask;
1089 if ((flags ^ oflags) & PVF_WIRED) {
1090 if (flags & PVF_WIRED)
1091 ++pm->pm_stats.wired_count;
1093 --pm->pm_stats.wired_count;
1095 if ((oflags & PVF_WRITE) && !(flags & PVF_WRITE)) {
1096 TAILQ_FOREACH(npv, &pg->md.pv_list, pv_list) {
1097 if (npv->pv_flags & PVF_WRITE)
1101 pg->md.pvh_attrs &= ~PVF_MOD;
1102 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1109 /* Function to set the debug level of the pmap code */
1112 pmap_debug(int level)
1114 pmap_debug_level = level;
1115 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
1117 #endif /* PMAP_DEBUG */
1120 pmap_pinit0(struct pmap *pmap)
1122 PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap));
1124 dprintf("pmap_pinit0: pmap = %08x, pm_pdir = %08x\n",
1125 (u_int32_t) pmap, (u_int32_t) pmap->pm_pdir);
1126 bcopy(kernel_pmap, pmap, sizeof(*pmap));
1127 bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx));
1128 PMAP_LOCK_INIT(pmap);
1132 * Initialize a vm_page's machine-dependent fields.
1135 pmap_page_init(vm_page_t m)
1138 TAILQ_INIT(&m->md.pv_list);
1139 m->md.pv_memattr = VM_MEMATTR_DEFAULT;
1143 * Initialize the pmap module.
1144 * Called by vm_init, to initialize any structures that the pmap
1145 * system needs to map virtual memory.
1150 int shpgperproc = PMAP_SHPGPERPROC;
1152 PDEBUG(1, printf("pmap_init: phys_start = %08x\n", PHYSADDR));
1154 l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor,
1155 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1156 l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable), NULL,
1157 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1160 * Initialize the PV entry allocator.
1162 pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL,
1163 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1164 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1165 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
1166 uma_zone_reserve_kva(pvzone, pv_entry_max);
1167 pv_entry_high_water = 9 * (pv_entry_max / 10);
1170 * Now it is safe to enable pv_table recording.
1172 PDEBUG(1, printf("pmap_init: done!\n"));
1176 pmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user)
1178 struct l2_dtable *l2;
1179 struct l2_bucket *l2b;
1180 pd_entry_t *pl1pd, l1pd;
1181 pt_entry_t *ptep, pte;
1187 rw_wlock(&pvh_global_lock);
1191 * If there is no l2_dtable for this address, then the process
1192 * has no business accessing it.
1194 * Note: This will catch userland processes trying to access
1197 l2 = pm->pm_l2[L2_IDX(l1idx)];
1202 * Likewise if there is no L2 descriptor table
1204 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
1205 if (l2b->l2b_kva == NULL)
1209 * Check the PTE itself.
1211 ptep = &l2b->l2b_kva[l2pte_index(va)];
1217 * Catch a userland access to the vector page mapped at 0x0
1219 if (user && ((pte & L2_S_PROT_MASK) == L2_S_PROT_U))
1221 if (va == vector_page)
1225 CTR5(KTR_PMAP, "pmap_fault_fix: pmap:%p va:%x pte:0x%x ftype:%x user:%x",
1226 pm, va, pte, ftype, user);
1227 if ((ftype & VM_PROT_WRITE) && !(L2_S_WRITABLE(pte))) {
1229 * This looks like a good candidate for "page modified"
1232 struct pv_entry *pv;
1235 /* Extract the physical address of the page */
1236 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) {
1239 /* Get the current flags for this page. */
1241 pv = pmap_find_pv(pg, pm, va);
1247 * Do the flags say this page is writable? If not then it
1248 * is a genuine write fault. If yes then the write fault is
1249 * our fault as we did not reflect the write access in the
1250 * PTE. Now we know a write has occurred we can correct this
1251 * and also set the modified bit
1253 if ((pv->pv_flags & PVF_WRITE) == 0) {
1256 pg->md.pvh_attrs |= PVF_REF | PVF_MOD;
1258 pv->pv_flags |= PVF_REF | PVF_MOD;
1260 /* Re-enable write permissions for the page */
1261 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO;
1262 pmap_set_prot(ptep, VM_PROT_WRITE, *ptep & L2_S_PROT_U);
1263 CTR1(KTR_PMAP, "pmap_fault_fix: new pte:0x%x", pte);
1266 } else if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) {
1268 * This looks like a good candidate for "page referenced"
1271 struct pv_entry *pv;
1274 /* Extract the physical address of the page */
1275 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL)
1277 /* Get the current flags for this page. */
1279 pv = pmap_find_pv(pg, pm, va);
1283 pg->md.pvh_attrs |= PVF_REF;
1284 pv->pv_flags |= PVF_REF;
1287 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO;
1293 * We know there is a valid mapping here, so simply
1294 * fix up the L1 if necessary.
1296 pl1pd = &pm->pm_l1->l1_kva[l1idx];
1297 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO;
1298 if (*pl1pd != l1pd) {
1306 * If 'rv == 0' at this point, it generally indicates that there is a
1307 * stale TLB entry for the faulting address. This happens when two or
1308 * more processes are sharing an L1. Since we don't flush the TLB on
1309 * a context switch between such processes, we can take domain faults
1310 * for mappings which exist at the same VA in both processes. EVEN IF
1311 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for
1314 * This is extremely likely to happen if pmap_enter() updated the L1
1315 * entry for a recently entered mapping. In this case, the TLB is
1316 * flushed for the new mapping, but there may still be TLB entries for
1317 * other mappings belonging to other processes in the 1MB range
1318 * covered by the L1 entry.
1320 * Since 'rv == 0', we know that the L1 already contains the correct
1321 * value, so the fault must be due to a stale TLB entry.
1323 * Since we always need to flush the TLB anyway in the case where we
1324 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with
1325 * stale TLB entries dynamically.
1327 * However, the above condition can ONLY happen if the current L1 is
1328 * being shared. If it happens when the L1 is unshared, it indicates
1329 * that other parts of the pmap are not doing their job WRT managing
1332 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) {
1333 printf("fixup: pm %p, va 0x%08x, ftype %d - nothing to do!\n",
1335 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n",
1336 l2, l2b, ptep, pl1pd);
1337 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n",
1338 pte, l1pd, last_fault_code);
1345 cpu_tlb_flushID_SE(va);
1351 rw_wunlock(&pvh_global_lock);
1359 struct l2_bucket *l2b;
1360 struct l1_ttable *l1;
1362 pt_entry_t *ptep, pte;
1363 vm_offset_t va, eva;
1366 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0);
1368 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK);
1370 for (loop = 0; loop < needed; loop++, l1++) {
1371 /* Allocate a L1 page table */
1372 va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0,
1373 0xffffffff, L1_TABLE_SIZE, 0);
1376 panic("Cannot allocate L1 KVM");
1378 eva = va + L1_TABLE_SIZE;
1379 pl1pt = (pd_entry_t *)va;
1382 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
1383 ptep = &l2b->l2b_kva[l2pte_index(va)];
1385 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
1388 cpu_tlb_flushD_SE(va);
1392 pmap_init_l1(l1, pl1pt);
1395 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n",
1401 * This is used to stuff certain critical values into the PCB where they
1402 * can be accessed quickly from cpu_switch() et al.
1405 pmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb)
1407 struct l2_bucket *l2b;
1409 pcb->pcb_pagedir = pm->pm_l1->l1_physaddr;
1410 pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) |
1411 (DOMAIN_CLIENT << (pm->pm_domain * 2));
1413 if (vector_page < KERNBASE) {
1414 pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)];
1415 l2b = pmap_get_l2_bucket(pm, vector_page);
1416 pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO |
1417 L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL);
1419 pcb->pcb_pl1vec = NULL;
1423 pmap_activate(struct thread *td)
1428 pm = vmspace_pmap(td->td_proc->p_vmspace);
1432 pmap_set_pcb_pagedir(pm, pcb);
1434 if (td == curthread) {
1435 u_int cur_dacr, cur_ttb;
1437 __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb));
1438 __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr));
1440 cur_ttb &= ~(L1_TABLE_SIZE - 1);
1442 if (cur_ttb == (u_int)pcb->pcb_pagedir &&
1443 cur_dacr == pcb->pcb_dacr) {
1445 * No need to switch address spaces.
1453 * We MUST, I repeat, MUST fix up the L1 entry corresponding
1454 * to 'vector_page' in the incoming L1 table before switching
1455 * to it otherwise subsequent interrupts/exceptions (including
1456 * domain faults!) will jump into hyperspace.
1458 if (pcb->pcb_pl1vec) {
1459 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
1462 cpu_domains(pcb->pcb_dacr);
1463 cpu_setttb(pcb->pcb_pagedir);
1469 pmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va)
1471 pd_entry_t *pdep, pde;
1472 pt_entry_t *ptep, pte;
1477 * Make sure the descriptor itself has the correct cache mode
1479 pdep = &kl1[L1_IDX(va)];
1482 if (l1pte_section_p(pde)) {
1483 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) {
1484 *pdep = (pde & ~L1_S_CACHE_MASK) |
1485 pte_l1_s_cache_mode_pt;
1490 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
1491 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
1493 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep);
1495 ptep = &ptep[l2pte_index(va)];
1497 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
1498 *ptep = (pte & ~L2_S_CACHE_MASK) |
1499 pte_l2_s_cache_mode_pt;
1509 pmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap,
1512 vm_offset_t va = *availp;
1513 struct l2_bucket *l2b;
1516 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
1518 panic("pmap_alloc_specials: no l2b for 0x%x", va);
1520 *ptep = &l2b->l2b_kva[l2pte_index(va)];
1524 *availp = va + (PAGE_SIZE * pages);
1528 * Bootstrap the system enough to run with virtual memory.
1530 * On the arm this is called after mapping has already been enabled
1531 * and just syncs the pmap module with what has already been done.
1532 * [We can't call it easily with mapping off since the kernel is not
1533 * mapped with PA == VA, hence we would have to relocate every address
1534 * from the linked base (virtual) address "KERNBASE" to the actual
1535 * (physical) address starting relative to 0]
1537 #define PMAP_STATIC_L2_SIZE 16
1540 pmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt)
1542 static struct l1_ttable static_l1;
1543 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE];
1544 struct l1_ttable *l1 = &static_l1;
1545 struct l2_dtable *l2;
1546 struct l2_bucket *l2b;
1548 pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va;
1553 int l1idx, l2idx, l2next = 0;
1555 PDEBUG(1, printf("firstaddr = %08x, lastaddr = %08x\n",
1556 firstaddr, vm_max_kernel_address));
1558 virtual_avail = firstaddr;
1559 kernel_pmap->pm_l1 = l1;
1560 kernel_l1pa = l1pt->pv_pa;
1563 * Scan the L1 translation table created by initarm() and create
1564 * the required metadata for all valid mappings found in it.
1566 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) {
1567 pde = kernel_l1pt[l1idx];
1570 * We're only interested in Coarse mappings.
1571 * pmap_extract() can deal with section mappings without
1572 * recourse to checking L2 metadata.
1574 if ((pde & L1_TYPE_MASK) != L1_TYPE_C)
1578 * Lookup the KVA of this L2 descriptor table
1580 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
1581 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
1584 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx",
1585 (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa);
1589 * Fetch the associated L2 metadata structure.
1590 * Allocate a new one if necessary.
1592 if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) {
1593 if (l2next == PMAP_STATIC_L2_SIZE)
1594 panic("pmap_bootstrap: out of static L2s");
1595 kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 =
1596 &static_l2[l2next++];
1600 * One more L1 slot tracked...
1605 * Fill in the details of the L2 descriptor in the
1606 * appropriate bucket.
1608 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
1609 l2b->l2b_kva = ptep;
1611 l2b->l2b_l1idx = l1idx;
1614 * Establish an initial occupancy count for this descriptor
1617 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
1619 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) {
1620 l2b->l2b_occupancy++;
1625 * Make sure the descriptor itself has the correct cache mode.
1626 * If not, fix it, but whine about the problem. Port-meisters
1627 * should consider this a clue to fix up their initarm()
1630 if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) {
1631 printf("pmap_bootstrap: WARNING! wrong cache mode for "
1632 "L2 pte @ %p\n", ptep);
1638 * Ensure the primary (kernel) L1 has the correct cache mode for
1639 * a page table. Bitch if it is not correctly set.
1641 for (va = (vm_offset_t)kernel_l1pt;
1642 va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) {
1643 if (pmap_set_pt_cache_mode(kernel_l1pt, va))
1644 printf("pmap_bootstrap: WARNING! wrong cache mode for "
1645 "primary L1 @ 0x%x\n", va);
1648 cpu_dcache_wbinv_all();
1649 cpu_l2cache_wbinv_all();
1653 PMAP_LOCK_INIT(kernel_pmap);
1654 CPU_FILL(&kernel_pmap->pm_active);
1655 kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL;
1656 TAILQ_INIT(&kernel_pmap->pm_pvlist);
1659 * Initialize the global pv list lock.
1661 rw_init(&pvh_global_lock, "pmap pv global");
1664 * Reserve some special page table entries/VA space for temporary
1668 pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte);
1669 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte);
1670 pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte);
1671 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte);
1672 size = ((vm_max_kernel_address - pmap_curmaxkvaddr) + L1_S_OFFSET) /
1674 pmap_alloc_specials(&virtual_avail,
1675 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE,
1676 &pmap_kernel_l2ptp_kva, NULL);
1678 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE;
1679 pmap_alloc_specials(&virtual_avail,
1680 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE,
1681 &pmap_kernel_l2dtable_kva, NULL);
1683 pmap_alloc_specials(&virtual_avail,
1684 1, (vm_offset_t*)&_tmppt, NULL);
1685 pmap_alloc_specials(&virtual_avail,
1686 MAXDUMPPGS, (vm_offset_t *)&crashdumpmap, NULL);
1687 SLIST_INIT(&l1_list);
1688 TAILQ_INIT(&l1_lru_list);
1689 mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF);
1690 pmap_init_l1(l1, kernel_l1pt);
1691 cpu_dcache_wbinv_all();
1692 cpu_l2cache_wbinv_all();
1694 virtual_avail = round_page(virtual_avail);
1695 virtual_end = vm_max_kernel_address;
1696 kernel_vm_end = pmap_curmaxkvaddr;
1697 arm_nocache_startaddr = vm_max_kernel_address;
1698 mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF);
1700 pmap_set_pcb_pagedir(kernel_pmap, thread0.td_pcb);
1703 /***************************************************
1704 * Pmap allocation/deallocation routines.
1705 ***************************************************/
1708 * Release any resources held by the given physical map.
1709 * Called when a pmap initialized by pmap_pinit is being released.
1710 * Should only be called if the map contains no valid mappings.
1713 pmap_release(pmap_t pmap)
1717 cpu_idcache_wbinv_all();
1718 cpu_l2cache_wbinv_all();
1721 if (vector_page < KERNBASE) {
1722 struct pcb *curpcb = PCPU_GET(curpcb);
1723 pcb = thread0.td_pcb;
1724 if (pmap_is_current(pmap)) {
1726 * Frob the L1 entry corresponding to the vector
1727 * page so that it contains the kernel pmap's domain
1728 * number. This will ensure pmap_remove() does not
1729 * pull the current vector page out from under us.
1732 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
1733 cpu_domains(pcb->pcb_dacr);
1734 cpu_setttb(pcb->pcb_pagedir);
1737 pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE);
1739 * Make sure cpu_switch(), et al, DTRT. This is safe to do
1740 * since this process has no remaining mappings of its own.
1742 curpcb->pcb_pl1vec = pcb->pcb_pl1vec;
1743 curpcb->pcb_l1vec = pcb->pcb_l1vec;
1744 curpcb->pcb_dacr = pcb->pcb_dacr;
1745 curpcb->pcb_pagedir = pcb->pcb_pagedir;
1749 PMAP_LOCK_DESTROY(pmap);
1751 dprintf("pmap_release()\n");
1757 * Helper function for pmap_grow_l2_bucket()
1760 pmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap)
1762 struct l2_bucket *l2b;
1767 pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
1770 pa = VM_PAGE_TO_PHYS(pg);
1775 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
1777 ptep = &l2b->l2b_kva[l2pte_index(va)];
1778 *ptep = L2_S_PROTO | pa | cache_mode;
1779 pmap_set_prot(ptep, VM_PROT_READ | VM_PROT_WRITE, 0);
1786 * This is the same as pmap_alloc_l2_bucket(), except that it is only
1787 * used by pmap_growkernel().
1789 static __inline struct l2_bucket *
1790 pmap_grow_l2_bucket(pmap_t pm, vm_offset_t va)
1792 struct l2_dtable *l2;
1793 struct l2_bucket *l2b;
1794 struct l1_ttable *l1;
1801 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
1803 * No mapping at this address, as there is
1804 * no entry in the L1 table.
1805 * Need to allocate a new l2_dtable.
1807 nva = pmap_kernel_l2dtable_kva;
1808 if ((nva & PAGE_MASK) == 0) {
1810 * Need to allocate a backing page
1812 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
1816 l2 = (struct l2_dtable *)nva;
1817 nva += sizeof(struct l2_dtable);
1819 if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva &
1822 * The new l2_dtable straddles a page boundary.
1823 * Map in another page to cover it.
1825 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
1829 pmap_kernel_l2dtable_kva = nva;
1832 * Link it into the parent pmap
1834 pm->pm_l2[L2_IDX(l1idx)] = l2;
1835 memset(l2, 0, sizeof(*l2));
1838 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
1841 * Fetch pointer to the L2 page table associated with the address.
1843 if (l2b->l2b_kva == NULL) {
1847 * No L2 page table has been allocated. Chances are, this
1848 * is because we just allocated the l2_dtable, above.
1850 nva = pmap_kernel_l2ptp_kva;
1851 ptep = (pt_entry_t *)nva;
1852 if ((nva & PAGE_MASK) == 0) {
1854 * Need to allocate a backing page
1856 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt,
1857 &pmap_kernel_l2ptp_phys))
1860 memset(ptep, 0, L2_TABLE_SIZE_REAL);
1862 l2b->l2b_kva = ptep;
1863 l2b->l2b_l1idx = l1idx;
1864 l2b->l2b_phys = pmap_kernel_l2ptp_phys;
1866 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL;
1867 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL;
1870 /* Distribute new L1 entry to all other L1s */
1871 SLIST_FOREACH(l1, &l1_list, l1_link) {
1872 pl1pd = &l1->l1_kva[L1_IDX(va)];
1873 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) |
1883 * grow the number of kernel page table entries, if needed
1886 pmap_growkernel(vm_offset_t addr)
1888 pmap_t kpm = pmap_kernel();
1890 if (addr <= pmap_curmaxkvaddr)
1891 return; /* we are OK */
1894 * whoops! we need to add kernel PTPs
1897 /* Map 1MB at a time */
1898 for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE)
1899 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr);
1902 * flush out the cache, expensive but growkernel will happen so
1905 cpu_dcache_wbinv_all();
1906 cpu_l2cache_wbinv_all();
1909 kernel_vm_end = pmap_curmaxkvaddr;
1914 * Remove all pages from specified address space
1915 * this aids process exit speeds. Also, this code
1916 * is special cased for current process only, but
1917 * can have the more generic (and slightly slower)
1918 * mode enabled. This is much faster than pmap_remove
1919 * in the case of running down an entire address space.
1922 pmap_remove_pages(pmap_t pmap)
1924 struct pv_entry *pv, *npv;
1925 struct l2_bucket *l2b = NULL;
1929 rw_wlock(&pvh_global_lock);
1931 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) {
1932 if (pv->pv_flags & PVF_WIRED) {
1933 /* Cannot remove wired pages now. */
1934 npv = TAILQ_NEXT(pv, pv_plist);
1937 pmap->pm_stats.resident_count--;
1938 l2b = pmap_get_l2_bucket(pmap, pv->pv_va);
1939 KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages"));
1940 pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
1941 m = PHYS_TO_VM_PAGE(*pt & L2_ADDR_MASK);
1942 KASSERT((vm_offset_t)m >= KERNBASE, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt));
1945 npv = TAILQ_NEXT(pv, pv_plist);
1946 pmap_nuke_pv(m, pmap, pv);
1947 if (TAILQ_EMPTY(&m->md.pv_list))
1948 vm_page_aflag_clear(m, PGA_WRITEABLE);
1949 pmap_free_pv_entry(pv);
1950 pmap_free_l2_bucket(pmap, l2b, 1);
1952 rw_wunlock(&pvh_global_lock);
1959 /***************************************************
1960 * Low level mapping routines.....
1961 ***************************************************/
1963 #ifdef ARM_HAVE_SUPERSECTIONS
1964 /* Map a super section into the KVA. */
1967 pmap_kenter_supersection(vm_offset_t va, uint64_t pa, int flags)
1969 pd_entry_t pd = L1_S_PROTO | L1_S_SUPERSEC | (pa & L1_SUP_FRAME) |
1970 (((pa >> 32) & 0xf) << 20) | L1_S_PROT(PTE_KERNEL,
1971 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
1972 struct l1_ttable *l1;
1973 vm_offset_t va0, va_end;
1975 KASSERT(((va | pa) & L1_SUP_OFFSET) == 0,
1976 ("Not a valid super section mapping"));
1977 if (flags & SECTION_CACHE)
1978 pd |= pte_l1_s_cache_mode;
1979 else if (flags & SECTION_PT)
1980 pd |= pte_l1_s_cache_mode_pt;
1982 va0 = va & L1_SUP_FRAME;
1983 va_end = va + L1_SUP_SIZE;
1984 SLIST_FOREACH(l1, &l1_list, l1_link) {
1986 for (; va < va_end; va += L1_S_SIZE) {
1987 l1->l1_kva[L1_IDX(va)] = pd;
1988 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
1994 /* Map a section into the KVA. */
1997 pmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags)
1999 pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL,
2000 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
2001 struct l1_ttable *l1;
2003 KASSERT(((va | pa) & L1_S_OFFSET) == 0,
2004 ("Not a valid section mapping"));
2005 if (flags & SECTION_CACHE)
2006 pd |= pte_l1_s_cache_mode;
2007 else if (flags & SECTION_PT)
2008 pd |= pte_l1_s_cache_mode_pt;
2010 SLIST_FOREACH(l1, &l1_list, l1_link) {
2011 l1->l1_kva[L1_IDX(va)] = pd;
2012 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2017 * Make a temporary mapping for a physical address. This is only intended
2018 * to be used for panic dumps.
2021 pmap_kenter_temp(vm_paddr_t pa, int i)
2025 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
2026 pmap_kenter(va, pa);
2027 return ((void *)crashdumpmap);
2031 * add a wired page to the kva
2032 * note that in order for the mapping to take effect -- you
2033 * should do a invltlb after doing the pmap_kenter...
2035 static PMAP_INLINE void
2036 pmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags)
2038 struct l2_bucket *l2b;
2042 PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n",
2043 (uint32_t) va, (uint32_t) pa));
2046 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2048 l2b = pmap_grow_l2_bucket(pmap_kernel(), va);
2049 KASSERT(l2b != NULL, ("No L2 Bucket"));
2051 pte = &l2b->l2b_kva[l2pte_index(va)];
2053 if (l2pte_valid(opte)) {
2054 cpu_tlb_flushD_SE(va);
2058 l2b->l2b_occupancy++;
2061 if (flags & KENTER_CACHE) {
2062 *pte = L2_S_PROTO | pa | pte_l2_s_cache_mode;
2063 pmap_set_prot(pte, VM_PROT_READ | VM_PROT_WRITE,
2064 flags & KENTER_USER);
2066 *pte = L2_S_PROTO | pa;
2067 pmap_set_prot(pte, VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE,
2071 PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n",
2072 (uint32_t) pte, opte, *pte));
2078 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2080 pmap_kenter_internal(va, pa, KENTER_CACHE);
2084 pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa)
2087 pmap_kenter_internal(va, pa, 0);
2091 pmap_kenter_user(vm_offset_t va, vm_paddr_t pa)
2094 pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER);
2096 * Call pmap_fault_fixup now, to make sure we'll have no exception
2097 * at the first use of the new address, or bad things will happen,
2098 * as we use one of these addresses in the exception handlers.
2100 pmap_fault_fixup(pmap_kernel(), va, VM_PROT_READ|VM_PROT_WRITE, 1);
2104 pmap_kextract(vm_offset_t va)
2107 return (pmap_extract_locked(kernel_pmap, va));
2111 * remove a page from the kernel pagetables
2114 pmap_kremove(vm_offset_t va)
2116 struct l2_bucket *l2b;
2117 pt_entry_t *pte, opte;
2119 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2122 KASSERT(l2b != NULL, ("No L2 Bucket"));
2123 pte = &l2b->l2b_kva[l2pte_index(va)];
2125 if (l2pte_valid(opte)) {
2126 va = va & ~PAGE_MASK;
2127 cpu_tlb_flushD_SE(va);
2136 * Used to map a range of physical addresses into kernel
2137 * virtual address space.
2139 * The value passed in '*virt' is a suggested virtual address for
2140 * the mapping. Architectures which can support a direct-mapped
2141 * physical to virtual region can return the appropriate address
2142 * within that region, leaving '*virt' unchanged. Other
2143 * architectures should map the pages starting at '*virt' and
2144 * update '*virt' with the first usable address after the mapped
2148 pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot)
2150 vm_offset_t sva = *virt;
2151 vm_offset_t va = sva;
2153 PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, "
2154 "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end,
2157 while (start < end) {
2158 pmap_kenter(va, start);
2167 * Add a list of wired pages to the kva
2168 * this routine is only used for temporary
2169 * kernel mappings that do not need to have
2170 * page modification or references recorded.
2171 * Note that old mappings are simply written
2172 * over. The page *must* be wired.
2175 pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
2179 for (i = 0; i < count; i++) {
2180 pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]),
2188 * this routine jerks page mappings from the
2189 * kernel -- it is meant only for temporary mappings.
2192 pmap_qremove(vm_offset_t va, int count)
2196 for (i = 0; i < count; i++) {
2206 * pmap_object_init_pt preloads the ptes for a given object
2207 * into the specified pmap. This eliminates the blast of soft
2208 * faults on process startup and immediately after an mmap.
2211 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
2212 vm_pindex_t pindex, vm_size_t size)
2215 VM_OBJECT_ASSERT_WLOCKED(object);
2216 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2217 ("pmap_object_init_pt: non-device object"));
2222 * pmap_is_prefaultable:
2224 * Return whether or not the specified virtual address is elgible
2228 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
2233 if (!pmap_get_pde_pte(pmap, addr, &pde, &pte))
2235 KASSERT(pte != NULL, ("Valid mapping but no pte ?"));
2242 * Fetch pointers to the PDE/PTE for the given pmap/VA pair.
2243 * Returns TRUE if the mapping exists, else FALSE.
2245 * NOTE: This function is only used by a couple of arm-specific modules.
2246 * It is not safe to take any pmap locks here, since we could be right
2247 * in the middle of debugging the pmap anyway...
2249 * It is possible for this routine to return FALSE even though a valid
2250 * mapping does exist. This is because we don't lock, so the metadata
2251 * state may be inconsistent.
2253 * NOTE: We can return a NULL *ptp in the case where the L1 pde is
2254 * a "section" mapping.
2257 pmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp)
2259 struct l2_dtable *l2;
2260 pd_entry_t *pl1pd, l1pd;
2264 if (pm->pm_l1 == NULL)
2268 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx];
2271 if (l1pte_section_p(l1pd)) {
2276 if (pm->pm_l2 == NULL)
2279 l2 = pm->pm_l2[L2_IDX(l1idx)];
2282 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
2286 *ptp = &ptep[l2pte_index(va)];
2291 * Routine: pmap_remove_all
2293 * Removes this physical page from
2294 * all physical maps in which it resides.
2295 * Reflects back modify bits to the pager.
2298 * Original versions of this routine were very
2299 * inefficient because they iteratively called
2300 * pmap_remove (slow...)
2303 pmap_remove_all(vm_page_t m)
2307 struct l2_bucket *l2b;
2308 boolean_t flush = FALSE;
2312 KASSERT((m->flags & PG_FICTITIOUS) == 0,
2313 ("pmap_remove_all: page %p is fictitious", m));
2315 if (TAILQ_EMPTY(&m->md.pv_list))
2317 rw_wlock(&pvh_global_lock);
2318 curpm = vmspace_pmap(curproc->p_vmspace);
2319 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2320 if (flush == FALSE && (pv->pv_pmap == curpm ||
2321 pv->pv_pmap == pmap_kernel()))
2324 PMAP_LOCK(pv->pv_pmap);
2325 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
2326 KASSERT(l2b != NULL, ("No l2 bucket"));
2327 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
2328 if (L2_S_WRITABLE(*ptep))
2331 if (pmap_is_current(pv->pv_pmap))
2333 pmap_free_l2_bucket(pv->pv_pmap, l2b, 1);
2334 pv->pv_pmap->pm_stats.resident_count--;
2335 flags |= pv->pv_flags;
2336 pmap_nuke_pv(m, pv->pv_pmap, pv);
2337 PMAP_UNLOCK(pv->pv_pmap);
2338 pmap_free_pv_entry(pv);
2340 m->md.pvh_attrs &= ~(PVF_MOD | PVF_REF);
2343 if (PV_BEEN_EXECD(flags))
2348 vm_page_aflag_clear(m, PGA_WRITEABLE);
2349 rw_wunlock(&pvh_global_lock);
2353 pmap_change_attr(vm_offset_t sva, vm_size_t len, int mode)
2355 vm_offset_t base, offset, tmpva;
2357 struct l2_bucket *l2b;
2358 pt_entry_t *ptep, pte;
2359 vm_offset_t next_bucket;
2361 PMAP_LOCK(kernel_pmap);
2363 base = trunc_page(sva);
2364 offset = sva & PAGE_MASK;
2365 size = roundup(offset + len, PAGE_SIZE);
2369 * Only supported on kernel virtual addresses, including the direct
2370 * map but excluding the recursive map.
2372 if (base < DMAP_MIN_ADDRESS) {
2373 PMAP_UNLOCK(kernel_pmap);
2377 for (tmpva = base; tmpva < base + size; ) {
2378 next_bucket = L2_NEXT_BUCKET(tmpva);
2379 if (next_bucket > base + size)
2380 next_bucket = base + size;
2382 l2b = pmap_get_l2_bucket(kernel_pmap, tmpva);
2384 tmpva = next_bucket;
2388 ptep = &l2b->l2b_kva[l2pte_index(tmpva)];
2391 PMAP_UNLOCK(kernel_pmap);
2395 pte = *ptep &~ L2_S_CACHE_MASK;
2396 cpu_idcache_wbinv_range(tmpva, PAGE_SIZE);
2397 pmap_l2cache_wbinv_range(tmpva, pte & L2_S_FRAME, PAGE_SIZE);
2399 cpu_tlb_flushID_SE(tmpva);
2401 dprintf("%s: for va:%x ptep:%x pte:%x\n",
2402 __func__, tmpva, (uint32_t)ptep, pte);
2406 PMAP_UNLOCK(kernel_pmap);
2412 * Set the physical protection on the
2413 * specified range of this map as requested.
2416 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2418 struct l2_bucket *l2b;
2419 pt_entry_t *ptep, pte;
2420 vm_offset_t next_bucket;
2424 if ((prot & VM_PROT_READ) == 0) {
2425 pmap_remove(pm, sva, eva);
2429 if (prot & VM_PROT_WRITE) {
2431 * If this is a read->write transition, just ignore it and let
2432 * vm_fault() take care of it later.
2437 rw_wlock(&pvh_global_lock);
2441 * OK, at this point, we know we're doing write-protect operation.
2442 * If the pmap is active, write-back the range.
2445 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1;
2449 next_bucket = L2_NEXT_BUCKET(sva);
2450 if (next_bucket > eva)
2453 l2b = pmap_get_l2_bucket(pm, sva);
2459 ptep = &l2b->l2b_kva[l2pte_index(sva)];
2461 while (sva < next_bucket) {
2462 if ((pte = *ptep) != 0 && L2_S_WRITABLE(pte)) {
2466 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
2467 pmap_set_prot(ptep, prot, !(pm == pmap_kernel()));
2470 f = pmap_modify_pv(pg, pm, sva,
2479 if (PV_BEEN_EXECD(f))
2480 cpu_tlb_flushID_SE(sva);
2482 if (PV_BEEN_REFD(f))
2483 cpu_tlb_flushD_SE(sva);
2493 if (PV_BEEN_EXECD(flags))
2496 if (PV_BEEN_REFD(flags))
2499 rw_wunlock(&pvh_global_lock);
2506 * Insert the given physical page (p) at
2507 * the specified virtual address (v) in the
2508 * target physical map with the protection requested.
2510 * If specified, the page will be wired down, meaning
2511 * that the related pte can not be reclaimed.
2513 * NB: This is the only routine which MAY NOT lazy-evaluate
2514 * or lose information. That is, this routine must actually
2515 * insert this page into the given map NOW.
2519 pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
2520 vm_prot_t prot, boolean_t wired)
2523 rw_wlock(&pvh_global_lock);
2525 pmap_enter_locked(pmap, va, m, prot, wired, M_WAITOK);
2527 rw_wunlock(&pvh_global_lock);
2531 * The pvh global and pmap locks must be held.
2534 pmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2535 boolean_t wired, int flags)
2537 struct l2_bucket *l2b = NULL;
2538 struct vm_page *opg;
2539 struct pv_entry *pve = NULL;
2540 pt_entry_t *ptep, npte, opte;
2546 PMAP_ASSERT_LOCKED(pmap);
2547 rw_assert(&pvh_global_lock, RA_WLOCKED);
2548 if (va == vector_page) {
2549 pa = systempage.pv_pa;
2552 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 ||
2553 (flags & M_NOWAIT) != 0,
2554 ("pmap_enter_locked: page %p is not busy", m));
2555 pa = VM_PAGE_TO_PHYS(m);
2560 * Make sure userland mappings get the right permissions
2562 if (pmap != pmap_kernel() && va != vector_page)
2567 if (prot & VM_PROT_WRITE)
2568 nflags |= PVF_WRITE;
2569 if (prot & VM_PROT_EXECUTE)
2572 nflags |= PVF_WIRED;
2574 PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, "
2575 "wired = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, wired));
2577 if (pmap == pmap_kernel()) {
2578 l2b = pmap_get_l2_bucket(pmap, va);
2580 l2b = pmap_grow_l2_bucket(pmap, va);
2583 l2b = pmap_alloc_l2_bucket(pmap, va);
2585 if (flags & M_WAITOK) {
2587 rw_wunlock(&pvh_global_lock);
2589 rw_wlock(&pvh_global_lock);
2597 ptep = &l2b->l2b_kva[l2pte_index(va)];
2604 * There is already a mapping at this address.
2605 * If the physical address is different, lookup the
2608 if (l2pte_pa(opte) != pa)
2609 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte));
2615 if ((prot & (VM_PROT_ALL)) ||
2616 (!m || m->md.pvh_attrs & PVF_REF)) {
2618 * - The access type indicates that we don't need
2619 * to do referenced emulation.
2621 * - The physical page has already been referenced
2622 * so no need to re-do referenced emulation here.
2631 if (m && ((prot & VM_PROT_WRITE) != 0 ||
2632 (m->md.pvh_attrs & PVF_MOD))) {
2634 * This is a writable mapping, and the
2635 * page's mod state indicates it has
2636 * already been modified. Make it
2637 * writable from the outset.
2640 if (!(m->md.pvh_attrs & PVF_MOD))
2644 vm_page_aflag_set(m, PGA_REFERENCED);
2647 * Need to do page referenced emulation.
2649 npte |= L2_TYPE_INV;
2652 npte |= L2_S_PROT_R;
2654 if (prot & VM_PROT_WRITE) {
2658 (m->oflags & VPO_UNMANAGED) == 0)
2659 vm_page_aflag_set(m, PGA_WRITEABLE);
2663 npte |= L2_S_PROT_U;
2666 if (!(prot & VM_PROT_EXECUTE) && m)
2669 if (m->md.pv_memattr != VM_MEMATTR_UNCACHEABLE)
2670 npte |= pte_l2_s_cache_mode;
2672 if (m && m == opg) {
2674 * We're changing the attrs of an existing mapping.
2676 oflags = pmap_modify_pv(m, pmap, va,
2677 PVF_WRITE | PVF_EXEC | PVF_WIRED |
2678 PVF_MOD | PVF_REF, nflags);
2681 * New mapping, or changing the backing page
2682 * of an existing mapping.
2686 * Replacing an existing mapping with a new one.
2687 * It is part of our managed memory so we
2688 * must remove it from the PV list
2690 if ((pve = pmap_remove_pv(opg, pmap, va))) {
2691 oflags = pve->pv_flags;
2693 if (m && ((m->oflags & VPO_UNMANAGED))) {
2694 pmap_free_pv_entry(pve);
2700 if ((m && !(m->oflags & VPO_UNMANAGED))) {
2701 if ((!pve) && (pve = pmap_get_pv_entry()) == NULL)
2702 panic("pmap_enter: no pv entries");
2704 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
2705 ("pmap_enter: managed mapping within the clean submap"));
2706 KASSERT(pve != NULL, ("No pv"));
2707 pmap_enter_pv(m, pve, pmap, va, nflags);
2712 * Keep the stats up to date
2715 l2b->l2b_occupancy++;
2716 pmap->pm_stats.resident_count++;
2719 CTR5(KTR_PMAP,"enter: pmap:%p va:%x prot:%x pte:%x->%x",
2720 pmap, va, prot, opte, npte);
2722 * If this is just a wiring change, the two PTEs will be
2723 * identical, so there's no need to update the page table.
2726 boolean_t is_cached = pmap_is_current(pmap);
2732 * We only need to frob the cache/tlb if this pmap
2735 if (L1_IDX(va) != L1_IDX(vector_page) &&
2736 l2pte_valid(npte)) {
2738 * This mapping is likely to be accessed as
2739 * soon as we return to userland. Fix up the
2740 * L1 entry to avoid taking another
2741 * page/domain fault.
2743 pd_entry_t *pl1pd, l1pd;
2745 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
2746 l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) |
2748 if (*pl1pd != l1pd) {
2755 if (PV_BEEN_EXECD(oflags))
2756 cpu_tlb_flushID_SE(va);
2757 else if (PV_BEEN_REFD(oflags))
2758 cpu_tlb_flushD_SE(va);
2761 if ((pmap != pmap_kernel()) && (pmap == &curproc->p_vmspace->vm_pmap))
2762 cpu_icache_sync_range(va, PAGE_SIZE);
2766 * Maps a sequence of resident pages belonging to the same object.
2767 * The sequence begins with the given page m_start. This page is
2768 * mapped at the given virtual address start. Each subsequent page is
2769 * mapped at a virtual address that is offset from start by the same
2770 * amount as the page is offset from m_start within the object. The
2771 * last page in the sequence is the page with the largest offset from
2772 * m_start that can be mapped at a virtual address less than the given
2773 * virtual address end. Not every virtual page between start and end
2774 * is mapped; only those for which a resident page exists with the
2775 * corresponding offset from m_start are mapped.
2778 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
2779 vm_page_t m_start, vm_prot_t prot)
2782 vm_pindex_t diff, psize;
2784 psize = atop(end - start);
2786 rw_wlock(&pvh_global_lock);
2788 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
2789 pmap_enter_locked(pmap, start + ptoa(diff), m, prot &
2790 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE, M_NOWAIT);
2791 m = TAILQ_NEXT(m, listq);
2794 rw_wunlock(&pvh_global_lock);
2798 * this code makes some *MAJOR* assumptions:
2799 * 1. Current pmap & pmap exists.
2802 * 4. No page table pages.
2803 * but is *MUCH* faster than pmap_enter...
2807 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
2810 rw_wlock(&pvh_global_lock);
2812 pmap_enter_locked(pmap, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
2815 rw_wunlock(&pvh_global_lock);
2819 * Routine: pmap_change_wiring
2820 * Function: Change the wiring attribute for a map/virtual-address
2822 * In/out conditions:
2823 * The mapping must already exist in the pmap.
2826 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
2828 struct l2_bucket *l2b;
2829 pt_entry_t *ptep, pte;
2832 rw_wlock(&pvh_global_lock);
2834 l2b = pmap_get_l2_bucket(pmap, va);
2835 KASSERT(l2b, ("No l2b bucket in pmap_change_wiring"));
2836 ptep = &l2b->l2b_kva[l2pte_index(va)];
2838 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
2840 pmap_modify_pv(pg, pmap, va, PVF_WIRED, wired);
2841 rw_wunlock(&pvh_global_lock);
2847 * Copy the range specified by src_addr/len
2848 * from the source map to the range dst_addr/len
2849 * in the destination map.
2851 * This routine is only advisory and need not do anything.
2854 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
2855 vm_size_t len, vm_offset_t src_addr)
2861 * Routine: pmap_extract
2863 * Extract the physical page address associated
2864 * with the given map/virtual_address pair.
2867 pmap_extract(pmap_t pmap, vm_offset_t va)
2872 pa = pmap_extract_locked(pmap, va);
2878 pmap_extract_locked(pmap_t pmap, vm_offset_t va)
2880 struct l2_dtable *l2;
2882 pt_entry_t *ptep, pte;
2886 if (pmap != kernel_pmap)
2887 PMAP_ASSERT_LOCKED(pmap);
2889 l1pd = pmap->pm_l1->l1_kva[l1idx];
2890 if (l1pte_section_p(l1pd)) {
2892 * These should only happen for the kernel pmap.
2894 KASSERT(pmap == kernel_pmap, ("unexpected section"));
2895 /* XXX: what to do about the bits > 32 ? */
2896 if (l1pd & L1_S_SUPERSEC)
2897 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
2899 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
2902 * Note that we can't rely on the validity of the L1
2903 * descriptor as an indication that a mapping exists.
2904 * We have to look it up in the L2 dtable.
2906 l2 = pmap->pm_l2[L2_IDX(l1idx)];
2908 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL)
2910 pte = ptep[l2pte_index(va)];
2913 switch (pte & L2_TYPE_MASK) {
2915 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
2918 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
2926 * Atomically extract and hold the physical page with the given
2927 * pmap and virtual address pair if that mapping permits the given
2932 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
2934 struct l2_dtable *l2;
2936 pt_entry_t *ptep, pte;
2937 vm_paddr_t pa, paddr;
2945 l1pd = pmap->pm_l1->l1_kva[l1idx];
2946 if (l1pte_section_p(l1pd)) {
2948 * These should only happen for pmap_kernel()
2950 KASSERT(pmap == pmap_kernel(), ("huh"));
2951 /* XXX: what to do about the bits > 32 ? */
2952 if (l1pd & L1_S_SUPERSEC)
2953 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
2955 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
2956 if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr))
2958 if (L1_S_WRITABLE(l1pd) || (prot & VM_PROT_WRITE) == 0) {
2959 m = PHYS_TO_VM_PAGE(pa);
2964 * Note that we can't rely on the validity of the L1
2965 * descriptor as an indication that a mapping exists.
2966 * We have to look it up in the L2 dtable.
2968 l2 = pmap->pm_l2[L2_IDX(l1idx)];
2971 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
2976 ptep = &ptep[l2pte_index(va)];
2982 } else if ((prot & VM_PROT_WRITE) && (pte & L2_APX)) {
2986 switch (pte & L2_TYPE_MASK) {
2988 panic("extract and hold section mapping");
2991 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
2994 if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr))
2996 m = PHYS_TO_VM_PAGE(pa);
3003 PA_UNLOCK_COND(paddr);
3008 * Initialize a preallocated and zeroed pmap structure,
3009 * such as one in a vmspace structure.
3013 pmap_pinit(pmap_t pmap)
3015 PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap));
3017 PMAP_LOCK_INIT(pmap);
3018 pmap_alloc_l1(pmap);
3019 bzero(pmap->pm_l2, sizeof(pmap->pm_l2));
3021 CPU_ZERO(&pmap->pm_active);
3023 TAILQ_INIT(&pmap->pm_pvlist);
3024 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3025 pmap->pm_stats.resident_count = 1;
3026 if (vector_page < KERNBASE) {
3027 pmap_enter(pmap, vector_page,
3028 VM_PROT_READ, PHYS_TO_VM_PAGE(systempage.pv_pa),
3035 /***************************************************
3036 * page management routines.
3037 ***************************************************/
3041 pmap_free_pv_entry(pv_entry_t pv)
3044 uma_zfree(pvzone, pv);
3049 * get a new pv_entry, allocating a block from the system
3051 * the memory allocation is performed bypassing the malloc code
3052 * because of the possibility of allocations at interrupt time.
3055 pmap_get_pv_entry(void)
3057 pv_entry_t ret_value;
3060 if (pv_entry_count > pv_entry_high_water)
3061 pagedaemon_wakeup();
3062 ret_value = uma_zalloc(pvzone, M_NOWAIT);
3067 * Remove the given range of addresses from the specified map.
3069 * It is assumed that the start and end are properly
3070 * rounded to the page size.
3072 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3
3074 pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva)
3076 struct l2_bucket *l2b;
3077 vm_offset_t next_bucket;
3080 u_int mappings, is_exec, is_refd;
3085 * we lock in the pmap => pv_head direction
3088 rw_wlock(&pvh_global_lock);
3093 * Do one L2 bucket's worth at a time.
3095 next_bucket = L2_NEXT_BUCKET(sva);
3096 if (next_bucket > eva)
3099 l2b = pmap_get_l2_bucket(pm, sva);
3105 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3108 while (sva < next_bucket) {
3117 * Nothing here, move along
3124 pm->pm_stats.resident_count--;
3130 * Update flags. In a number of circumstances,
3131 * we could cluster a lot of these and do a
3132 * number of sequential pages in one go.
3134 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) {
3135 struct pv_entry *pve;
3137 pve = pmap_remove_pv(pg, pm, sva);
3139 is_exec = PV_BEEN_EXECD(pve->pv_flags);
3140 is_refd = PV_BEEN_REFD(pve->pv_flags);
3141 pmap_free_pv_entry(pve);
3145 if (pmap_is_current(pm)) {
3147 if (total < PMAP_REMOVE_CLEAN_LIST_SIZE) {
3149 cpu_tlb_flushID_SE(sva);
3151 cpu_tlb_flushD_SE(sva);
3152 } else if (total == PMAP_REMOVE_CLEAN_LIST_SIZE) {
3164 pmap_free_l2_bucket(pm, l2b, mappings);
3167 rw_wunlock(&pvh_global_lock);
3176 * Zero a given physical page by mapping it at a page hook point.
3177 * In doing the zero page op, the page we zero is mapped cachable, as with
3178 * StrongARM accesses to non-cached pages are non-burst making writing
3179 * _any_ bulk data very slow.
3182 pmap_zero_page_gen(vm_page_t pg, int off, int size)
3185 vm_paddr_t phys = VM_PAGE_TO_PHYS(pg);
3186 if (!TAILQ_EMPTY(&pg->md.pv_list))
3187 panic("pmap_zero_page: page has mappings");
3191 * Hook in the page, zero it, invalidate the TLB as needed.
3193 * Note the temporary zero-page mapping must be a non-cached page in
3194 * order to work without corruption when write-allocate is enabled.
3196 *cdst_pte = L2_S_PROTO | phys | pte_l2_s_cache_mode;
3197 pmap_set_prot(cdst_pte, VM_PROT_WRITE, 0);
3199 cpu_tlb_flushD_SE(cdstp);
3201 if (off || size != PAGE_SIZE)
3202 bzero((void *)(cdstp + off), size);
3207 * Although aliasing is not possible if we use
3208 * cdstp temporary mappings with memory that
3209 * will be mapped later as non-cached or with write-through
3210 * caches we might end up overwriting it when calling wbinv_all
3211 * So make sure caches are clean after copy operation
3213 cpu_idcache_wbinv_range(cdstp, size);
3214 pmap_l2cache_wbinv_range(cdstp, phys, size);
3220 * pmap_zero_page zeros the specified hardware page by mapping
3221 * the page into KVM and using bzero to clear its contents.
3224 pmap_zero_page(vm_page_t m)
3226 pmap_zero_page_gen(m, 0, PAGE_SIZE);
3231 * pmap_zero_page_area zeros the specified hardware page by mapping
3232 * the page into KVM and using bzero to clear its contents.
3234 * off and size may not cover an area beyond a single hardware page.
3237 pmap_zero_page_area(vm_page_t m, int off, int size)
3240 pmap_zero_page_gen(m, off, size);
3245 * pmap_zero_page_idle zeros the specified hardware page by mapping
3246 * the page into KVM and using bzero to clear its contents. This
3247 * is intended to be called from the vm_pagezero process only and
3251 pmap_zero_page_idle(vm_page_t m)
3258 * pmap_copy_page copies the specified (machine independent)
3259 * page by mapping the page into virtual memory and using
3260 * bcopy to copy the page, one machine dependent page at a
3267 * Copy one physical page into another, by mapping the pages into
3268 * hook points. The same comment regarding cachability as in
3269 * pmap_zero_page also applies here.
3272 pmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst)
3275 * Hold the source page's lock for the duration of the copy
3276 * so that no other mappings can be created while we have a
3277 * potentially aliased mapping.
3278 * Map the pages into the page hook points, copy them, and purge
3279 * the cache for the appropriate page. Invalidate the TLB
3284 /* For ARMv6 using System bit is deprecated and mapping with AP
3285 * bits set to 0x0 makes page not accessible. csrc_pte is mapped
3286 * read/write until proper mapping defines are created for ARMv6.
3288 *csrc_pte = L2_S_PROTO | src | pte_l2_s_cache_mode;
3289 pmap_set_prot(csrc_pte, VM_PROT_READ, 0);
3292 *cdst_pte = L2_S_PROTO | dst | pte_l2_s_cache_mode;
3293 pmap_set_prot(cdst_pte, VM_PROT_READ | VM_PROT_WRITE, 0);
3296 cpu_tlb_flushD_SE(csrcp);
3297 cpu_tlb_flushD_SE(cdstp);
3301 * Although aliasing is not possible if we use
3302 * cdstp temporary mappings with memory that
3303 * will be mapped later as non-cached or with write-through
3304 * caches we might end up overwriting it when calling wbinv_all
3305 * So make sure caches are clean after copy operation
3307 bcopy_page(csrcp, cdstp);
3309 cpu_idcache_wbinv_range(cdstp, PAGE_SIZE);
3310 pmap_l2cache_wbinv_range(cdstp, dst, PAGE_SIZE);
3315 int unmapped_buf_allowed = 1;
3318 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
3319 vm_offset_t b_offset, int xfersize)
3321 vm_page_t a_pg, b_pg;
3322 vm_offset_t a_pg_offset, b_pg_offset;
3326 while (xfersize > 0) {
3327 a_pg = ma[a_offset >> PAGE_SHIFT];
3328 a_pg_offset = a_offset & PAGE_MASK;
3329 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
3330 b_pg = mb[b_offset >> PAGE_SHIFT];
3331 b_pg_offset = b_offset & PAGE_MASK;
3332 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
3333 *csrc_pte = L2_S_PROTO | VM_PAGE_TO_PHYS(a_pg) |
3334 pte_l2_s_cache_mode;
3335 pmap_set_prot(csrc_pte, VM_PROT_READ, 0);
3337 *cdst_pte = L2_S_PROTO | VM_PAGE_TO_PHYS(b_pg) |
3338 pte_l2_s_cache_mode;
3339 pmap_set_prot(cdst_pte, VM_PROT_READ | VM_PROT_WRITE, 0);
3341 cpu_tlb_flushD_SE(csrcp);
3342 cpu_tlb_flushD_SE(cdstp);
3344 bcopy((char *)csrcp + a_pg_offset, (char *)cdstp + b_pg_offset,
3346 cpu_idcache_wbinv_range(cdstp + b_pg_offset, cnt);
3347 pmap_l2cache_wbinv_range(cdstp + b_pg_offset,
3348 VM_PAGE_TO_PHYS(b_pg) + b_pg_offset, cnt);
3357 pmap_copy_page(vm_page_t src, vm_page_t dst)
3360 if (_arm_memcpy && PAGE_SIZE >= _min_memcpy_size &&
3361 _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst),
3362 (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0)
3365 pmap_copy_page_generic(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst));
3369 * this routine returns true if a physical page resides
3370 * in the given pmap.
3373 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
3379 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3380 ("pmap_page_exists_quick: page %p is not managed", m));
3382 rw_wlock(&pvh_global_lock);
3383 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3384 if (pv->pv_pmap == pmap) {
3393 rw_wunlock(&pvh_global_lock);
3398 * pmap_page_wired_mappings:
3400 * Return the number of managed mappings to the given physical page
3404 pmap_page_wired_mappings(vm_page_t m)
3410 if ((m->flags & PG_FICTITIOUS) != 0)
3412 rw_wlock(&pvh_global_lock);
3413 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
3414 if ((pv->pv_flags & PVF_WIRED) != 0)
3416 rw_wunlock(&pvh_global_lock);
3421 * pmap_is_referenced:
3423 * Return whether or not the specified physical page was referenced
3424 * in any physical maps.
3427 pmap_is_referenced(vm_page_t m)
3430 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3431 ("pmap_is_referenced: page %p is not managed", m));
3432 return ((m->md.pvh_attrs & PVF_REF) != 0);
3436 * pmap_ts_referenced:
3438 * Return the count of reference bits for a page, clearing all of them.
3441 pmap_ts_referenced(vm_page_t m)
3444 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3445 ("pmap_ts_referenced: page %p is not managed", m));
3446 return (pmap_clearbit(m, PVF_REF));
3451 pmap_is_modified(vm_page_t m)
3454 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3455 ("pmap_is_modified: page %p is not managed", m));
3456 if (m->md.pvh_attrs & PVF_MOD)
3464 * Clear the modify bits on the specified physical page.
3467 pmap_clear_modify(vm_page_t m)
3470 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3471 ("pmap_clear_modify: page %p is not managed", m));
3472 VM_OBJECT_ASSERT_WLOCKED(m->object);
3473 KASSERT((m->oflags & VPO_BUSY) == 0,
3474 ("pmap_clear_modify: page %p is busy", m));
3477 * If the page is not PGA_WRITEABLE, then no mappings can be modified.
3478 * If the object containing the page is locked and the page is not
3479 * VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set.
3481 if ((m->aflags & PGA_WRITEABLE) == 0)
3484 if (m->md.pvh_attrs & PVF_MOD)
3485 pmap_clearbit(m, PVF_MOD);
3490 * pmap_clear_reference:
3492 * Clear the reference bit on the specified physical page.
3495 pmap_clear_reference(vm_page_t m)
3498 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3499 ("pmap_clear_reference: page %p is not managed", m));
3500 if (m->md.pvh_attrs & PVF_REF)
3501 pmap_clearbit(m, PVF_REF);
3506 * Clear the write and modified bits in each of the given page's mappings.
3509 pmap_remove_write(vm_page_t m)
3511 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3512 ("pmap_remove_write: page %p is not managed", m));
3515 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
3516 * another thread while the object is locked. Thus, if PGA_WRITEABLE
3517 * is clear, no page table entries need updating.
3519 VM_OBJECT_ASSERT_WLOCKED(m->object);
3520 if ((m->oflags & VPO_BUSY) != 0 ||
3521 (m->aflags & PGA_WRITEABLE) != 0)
3522 pmap_clearbit(m, PVF_WRITE);
3527 * perform the pmap work for mincore
3530 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
3532 struct l2_bucket *l2b;
3533 pt_entry_t *ptep, pte;
3541 l2b = pmap_get_l2_bucket(pmap, addr);
3546 ptep = &l2b->l2b_kva[l2pte_index(addr)];
3548 if (!l2pte_valid(pte)) {
3552 val = MINCORE_INCORE;
3553 if (L2_S_WRITABLE(pte))
3554 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
3557 m = PHYS_TO_VM_PAGE(pa);
3558 if (m != NULL && (m->oflags & VPO_UNMANAGED) == 0)
3562 * The ARM pmap tries to maintain a per-mapping
3563 * reference bit. The trouble is that it's kept in
3564 * the PV entry, not the PTE, so it's costly to access
3565 * here. You would need to acquire the pvh global
3566 * lock, call pmap_find_pv(), and introduce a custom
3567 * version of vm_page_pa_tryrelock() that releases and
3568 * reacquires the pvh global lock. In the end, I
3569 * doubt it's worthwhile. This may falsely report
3570 * the given address as referenced.
3572 if ((m->md.pvh_attrs & PVF_REF) != 0)
3573 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
3575 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
3576 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
3577 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
3578 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
3582 PA_UNLOCK_COND(*locked_pa);
3588 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
3593 * Increase the starting virtual address of the given mapping if a
3594 * different alignment might result in more superpage mappings.
3597 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
3598 vm_offset_t *addr, vm_size_t size)
3604 * Map a set of physical memory pages into the kernel virtual
3605 * address space. Return a pointer to where it is mapped. This
3606 * routine is intended to be used for mapping device memory,
3610 pmap_mapdev(vm_offset_t pa, vm_size_t size)
3612 vm_offset_t va, tmpva, offset;
3614 offset = pa & PAGE_MASK;
3615 size = roundup(size, PAGE_SIZE);
3619 va = kmem_alloc_nofault(kernel_map, size);
3621 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
3622 for (tmpva = va; size > 0;) {
3623 pmap_kenter_internal(tmpva, pa, 0);
3629 return ((void *)(va + offset));
3635 * Create a single section mapping.
3638 pmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
3639 int prot, int cache)
3641 pd_entry_t *pde = (pd_entry_t *) l1pt;
3644 KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2"));
3646 fl = l1_mem_types[cache];
3648 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
3649 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL);
3650 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
3656 * Link the L2 page table specified by l2pv.pv_pa into the L1
3657 * page table at the slot for "va".
3660 pmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv)
3662 pd_entry_t *pde = (pd_entry_t *) l1pt, proto;
3663 u_int slot = va >> L1_S_SHIFT;
3665 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO;
3667 #ifdef VERBOSE_INIT_ARM
3668 printf("pmap_link_l2pt: pa=0x%x va=0x%x\n", l2pv->pv_pa, l2pv->pv_va);
3671 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000);
3672 PTE_SYNC(&pde[slot]);
3674 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list);
3681 * Create a single page mapping.
3684 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot,
3687 pd_entry_t *pde = (pd_entry_t *) l1pt;
3691 KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin"));
3693 fl = l2s_mem_types[cache];
3695 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
3696 panic("pmap_map_entry: no L2 table for VA 0x%08x", va);
3698 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK);
3701 panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va);
3703 pte[l2pte_index(va)] = L2_S_PROTO | pa | fl;
3704 pmap_set_prot(&pte[l2pte_index(va)], prot, 0);
3705 PTE_SYNC(&pte[l2pte_index(va)]);
3711 * Map a chunk of memory using the most efficient mappings
3712 * possible (section. large page, small page) into the
3713 * provided L1 and L2 tables at the specified virtual address.
3716 pmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
3717 vm_size_t size, int prot, int type)
3719 pd_entry_t *pde = (pd_entry_t *) l1pt;
3720 pt_entry_t *pte, f1, f2s, f2l;
3724 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
3727 panic("pmap_map_chunk: no L1 table provided");
3729 #ifdef VERBOSE_INIT_ARM
3730 printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x "
3731 "prot=0x%x type=%d\n", pa, va, size, resid, prot, type);
3734 f1 = l1_mem_types[type];
3735 f2l = l2l_mem_types[type];
3736 f2s = l2s_mem_types[type];
3741 /* See if we can use a section mapping. */
3742 if (L1_S_MAPPABLE_P(va, pa, resid)) {
3743 #ifdef VERBOSE_INIT_ARM
3746 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
3747 L1_S_PROT(PTE_KERNEL, prot) | f1 |
3748 L1_S_DOM(PMAP_DOMAIN_KERNEL);
3749 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
3757 * Ok, we're going to use an L2 table. Make sure
3758 * one is actually in the corresponding L1 slot
3759 * for the current VA.
3761 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
3762 panic("pmap_map_chunk: no L2 table for VA 0x%08x", va);
3764 pte = (pt_entry_t *) kernel_pt_lookup(
3765 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
3767 panic("pmap_map_chunk: can't find L2 table for VA"
3769 /* See if we can use a L2 large page mapping. */
3770 if (L2_L_MAPPABLE_P(va, pa, resid)) {
3771 #ifdef VERBOSE_INIT_ARM
3774 for (i = 0; i < 16; i++) {
3775 pte[l2pte_index(va) + i] =
3777 L2_L_PROT(PTE_KERNEL, prot) | f2l;
3778 PTE_SYNC(&pte[l2pte_index(va) + i]);
3786 /* Use a small page mapping. */
3787 #ifdef VERBOSE_INIT_ARM
3790 pte[l2pte_index(va)] = L2_S_PROTO | pa | f2s;
3791 pmap_set_prot(&pte[l2pte_index(va)], prot, 0);
3792 PTE_SYNC(&pte[l2pte_index(va)]);
3797 #ifdef VERBOSE_INIT_ARM
3804 /********************** Static device map routines ***************************/
3806 static const struct pmap_devmap *pmap_devmap_table;
3809 * Register the devmap table. This is provided in case early console
3810 * initialization needs to register mappings created by bootstrap code
3811 * before pmap_devmap_bootstrap() is called.
3814 pmap_devmap_register(const struct pmap_devmap *table)
3817 pmap_devmap_table = table;
3821 * Map all of the static regions in the devmap table, and remember
3822 * the devmap table so other parts of the kernel can look up entries
3826 pmap_devmap_bootstrap(vm_offset_t l1pt, const struct pmap_devmap *table)
3830 pmap_devmap_table = table;
3832 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
3833 #ifdef VERBOSE_INIT_ARM
3834 printf("devmap: %08x -> %08x @ %08x\n",
3835 pmap_devmap_table[i].pd_pa,
3836 pmap_devmap_table[i].pd_pa +
3837 pmap_devmap_table[i].pd_size - 1,
3838 pmap_devmap_table[i].pd_va);
3840 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va,
3841 pmap_devmap_table[i].pd_pa,
3842 pmap_devmap_table[i].pd_size,
3843 pmap_devmap_table[i].pd_prot,
3844 pmap_devmap_table[i].pd_cache);
3848 const struct pmap_devmap *
3849 pmap_devmap_find_pa(vm_paddr_t pa, vm_size_t size)
3853 if (pmap_devmap_table == NULL)
3856 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
3857 if (pa >= pmap_devmap_table[i].pd_pa &&
3858 pa + size <= pmap_devmap_table[i].pd_pa +
3859 pmap_devmap_table[i].pd_size)
3860 return (&pmap_devmap_table[i]);
3866 const struct pmap_devmap *
3867 pmap_devmap_find_va(vm_offset_t va, vm_size_t size)
3871 if (pmap_devmap_table == NULL)
3874 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
3875 if (va >= pmap_devmap_table[i].pd_va &&
3876 va + size <= pmap_devmap_table[i].pd_va +
3877 pmap_devmap_table[i].pd_size)
3878 return (&pmap_devmap_table[i]);
3885 pmap_dmap_iscurrent(pmap_t pmap)
3887 return(pmap_is_current(pmap));
3891 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
3894 * Remember the memattr in a field that gets used to set the appropriate
3895 * bits in the PTEs as mappings are established.
3897 m->md.pv_memattr = ma;
3900 * It appears that this function can only be called before any mappings
3901 * for the page are established on ARM. If this ever changes, this code
3902 * will need to walk the pv_list and make each of the existing mappings
3903 * uncacheable, being careful to sync caches and PTEs (and maybe
3904 * invalidate TLB?) for any current mapping it modifies.
3906 if (m->md.pv_kva != 0 || TAILQ_FIRST(&m->md.pv_list) != NULL)
3907 panic("Can't change memattr on page with existing mappings");