2 * Copyright (c) 1991 Regents of the University of California.
3 * Copyright (c) 1994 John S. Dyson
4 * Copyright (c) 1994 David Greenman
5 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
6 * Copyright (c) 2014-2016 Svatopluk Kraus <skra@FreeBSD.org>
7 * Copyright (c) 2014-2016 Michal Meloun <mmel@FreeBSD.org>
10 * This code is derived from software contributed to Berkeley by
11 * the Systems Programming Group of the University of Utah Computer
12 * Science Department and William Jolitz of UUNET Technologies Inc.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
41 * Copyright (c) 2003 Networks Associates Technology, Inc.
42 * All rights reserved.
44 * This software was developed for the FreeBSD Project by Jake Burkholder,
45 * Safeport Network Services, and Network Associates Laboratories, the
46 * Security Research Division of Network Associates, Inc. under
47 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
48 * CHATS research program.
50 * Redistribution and use in source and binary forms, with or without
51 * modification, are permitted provided that the following conditions
53 * 1. Redistributions of source code must retain the above copyright
54 * notice, this list of conditions and the following disclaimer.
55 * 2. Redistributions in binary form must reproduce the above copyright
56 * notice, this list of conditions and the following disclaimer in the
57 * documentation and/or other materials provided with the distribution.
59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
62 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
72 #include <sys/cdefs.h>
73 __FBSDID("$FreeBSD$");
76 * Manages physical address maps.
78 * Since the information managed by this module is
79 * also stored by the logical address mapping module,
80 * this module may throw away valid virtual-to-physical
81 * mappings at almost any time. However, invalidations
82 * of virtual-to-physical mappings must be done as
85 * In order to cope with hardware architectures which
86 * make virtual-to-physical map invalidates expensive,
87 * this module may delay invalidate or reduced protection
88 * operations until such time as they are actually
89 * necessary. This module is given full information as
90 * to which processors are currently using which maps,
91 * and to when physical maps must be made correct.
98 #include <sys/param.h>
99 #include <sys/systm.h>
100 #include <sys/kernel.h>
102 #include <sys/lock.h>
103 #include <sys/proc.h>
104 #include <sys/rwlock.h>
105 #include <sys/malloc.h>
106 #include <sys/vmmeter.h>
107 #include <sys/malloc.h>
108 #include <sys/mman.h>
109 #include <sys/sf_buf.h>
111 #include <sys/sched.h>
112 #include <sys/sysctl.h>
116 #include <sys/cpuset.h>
123 #include <machine/physmem.h>
128 #include <vm/vm_param.h>
129 #include <vm/vm_kern.h>
130 #include <vm/vm_object.h>
131 #include <vm/vm_map.h>
132 #include <vm/vm_page.h>
133 #include <vm/vm_pageout.h>
134 #include <vm/vm_phys.h>
135 #include <vm/vm_extern.h>
136 #include <vm/vm_reserv.h>
137 #include <sys/lock.h>
138 #include <sys/mutex.h>
140 #include <machine/md_var.h>
141 #include <machine/pmap_var.h>
142 #include <machine/cpu.h>
143 #include <machine/pcb.h>
144 #include <machine/sf_buf.h>
146 #include <machine/smp.h>
149 #ifndef PMAP_SHPGPERPROC
150 #define PMAP_SHPGPERPROC 200
154 #define PMAP_INLINE __inline
160 static void pmap_zero_page_check(vm_page_t m);
161 void pmap_debug(int level);
162 int pmap_pid_dump(int pid);
164 #define PDEBUG(_lev_,_stat_) \
165 if (pmap_debug_level >= (_lev_)) \
167 #define dprintf printf
168 int pmap_debug_level = 1;
169 #else /* PMAP_DEBUG */
170 #define PDEBUG(_lev_,_stat_) /* Nothing */
171 #define dprintf(x, arg...)
172 #endif /* PMAP_DEBUG */
175 * Level 2 page tables map definion ('max' is excluded).
178 #define PT2V_MIN_ADDRESS ((vm_offset_t)PT2MAP)
179 #define PT2V_MAX_ADDRESS ((vm_offset_t)PT2MAP + PT2MAP_SIZE)
181 #define UPT2V_MIN_ADDRESS ((vm_offset_t)PT2MAP)
182 #define UPT2V_MAX_ADDRESS \
183 ((vm_offset_t)(PT2MAP + (KERNBASE >> PT2MAP_SHIFT)))
186 * Promotion to a 1MB (PTE1) page mapping requires that the corresponding
187 * 4KB (PTE2) page mappings have identical settings for the following fields:
189 #define PTE2_PROMOTE (PTE2_V | PTE2_A | PTE2_NM | PTE2_S | PTE2_NG | \
190 PTE2_NX | PTE2_RO | PTE2_U | PTE2_W | \
193 #define PTE1_PROMOTE (PTE1_V | PTE1_A | PTE1_NM | PTE1_S | PTE1_NG | \
194 PTE1_NX | PTE1_RO | PTE1_U | PTE1_W | \
197 #define ATTR_TO_L1(l2_attr) ((((l2_attr) & L2_TEX0) ? L1_S_TEX0 : 0) | \
198 (((l2_attr) & L2_C) ? L1_S_C : 0) | \
199 (((l2_attr) & L2_B) ? L1_S_B : 0) | \
200 (((l2_attr) & PTE2_A) ? PTE1_A : 0) | \
201 (((l2_attr) & PTE2_NM) ? PTE1_NM : 0) | \
202 (((l2_attr) & PTE2_S) ? PTE1_S : 0) | \
203 (((l2_attr) & PTE2_NG) ? PTE1_NG : 0) | \
204 (((l2_attr) & PTE2_NX) ? PTE1_NX : 0) | \
205 (((l2_attr) & PTE2_RO) ? PTE1_RO : 0) | \
206 (((l2_attr) & PTE2_U) ? PTE1_U : 0) | \
207 (((l2_attr) & PTE2_W) ? PTE1_W : 0))
209 #define ATTR_TO_L2(l1_attr) ((((l1_attr) & L1_S_TEX0) ? L2_TEX0 : 0) | \
210 (((l1_attr) & L1_S_C) ? L2_C : 0) | \
211 (((l1_attr) & L1_S_B) ? L2_B : 0) | \
212 (((l1_attr) & PTE1_A) ? PTE2_A : 0) | \
213 (((l1_attr) & PTE1_NM) ? PTE2_NM : 0) | \
214 (((l1_attr) & PTE1_S) ? PTE2_S : 0) | \
215 (((l1_attr) & PTE1_NG) ? PTE2_NG : 0) | \
216 (((l1_attr) & PTE1_NX) ? PTE2_NX : 0) | \
217 (((l1_attr) & PTE1_RO) ? PTE2_RO : 0) | \
218 (((l1_attr) & PTE1_U) ? PTE2_U : 0) | \
219 (((l1_attr) & PTE1_W) ? PTE2_W : 0))
222 * PTE2 descriptors creation macros.
224 #define PTE2_ATTR_DEFAULT vm_memattr_to_pte2(VM_MEMATTR_DEFAULT)
225 #define PTE2_ATTR_PT vm_memattr_to_pte2(pt_memattr)
227 #define PTE2_KPT(pa) PTE2_KERN(pa, PTE2_AP_KRW, PTE2_ATTR_PT)
228 #define PTE2_KPT_NG(pa) PTE2_KERN_NG(pa, PTE2_AP_KRW, PTE2_ATTR_PT)
230 #define PTE2_KRW(pa) PTE2_KERN(pa, PTE2_AP_KRW, PTE2_ATTR_DEFAULT)
231 #define PTE2_KRO(pa) PTE2_KERN(pa, PTE2_AP_KR, PTE2_ATTR_DEFAULT)
235 #define PV_STAT(x) do { x ; } while (0)
237 #define PV_STAT(x) do { } while (0)
241 * The boot_pt1 is used temporary in very early boot stage as L1 page table.
242 * We can init many things with no memory allocation thanks to its static
243 * allocation and this brings two main advantages:
244 * (1) other cores can be started very simply,
245 * (2) various boot loaders can be supported as its arguments can be processed
246 * in virtual address space and can be moved to safe location before
247 * first allocation happened.
248 * Only disadvantage is that boot_pt1 is used only in very early boot stage.
249 * However, the table is uninitialized and so lays in bss. Therefore kernel
250 * image size is not influenced.
252 * QQQ: In the future, maybe, boot_pt1 can be used for soft reset and
253 * CPU suspend/resume game.
255 extern pt1_entry_t boot_pt1[];
258 pt1_entry_t *kern_pt1;
259 pt2_entry_t *kern_pt2tab;
262 static uint32_t ttb_flags;
263 static vm_memattr_t pt_memattr;
264 ttb_entry_t pmap_kern_ttb;
266 struct pmap kernel_pmap_store;
267 LIST_HEAD(pmaplist, pmap);
268 static struct pmaplist allpmaps;
269 static struct mtx allpmaps_lock;
271 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
272 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
274 static vm_offset_t kernel_vm_end_new;
275 vm_offset_t kernel_vm_end = KERNBASE + NKPT2PG * NPT2_IN_PG * PTE1_SIZE;
276 vm_offset_t vm_max_kernel_address;
277 vm_paddr_t kernel_l1pa;
279 static struct rwlock __aligned(CACHE_LINE_SIZE) pvh_global_lock;
282 * Data for the pv entry allocation mechanism
284 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
285 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
286 static struct md_page *pv_table; /* XXX: Is it used only the list in md_page? */
287 static int shpgperproc = PMAP_SHPGPERPROC;
289 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
290 int pv_maxchunks; /* How many chunks we have KVA for */
291 vm_offset_t pv_vafree; /* freelist stored in the PTE */
293 vm_paddr_t first_managed_pa;
294 #define pa_to_pvh(pa) (&pv_table[pte1_index(pa - first_managed_pa)])
297 * All those kernel PT submaps that BSD is so fond of
308 static struct sysmaps sysmaps_pcpu[MAXCPU];
309 static pt2_entry_t *CMAP3;
310 static caddr_t CADDR3;
313 struct msgbuf *msgbufp = NULL; /* XXX move it to machdep.c */
318 static caddr_t crashdumpmap;
320 static pt2_entry_t *PMAP1 = NULL, *PMAP2;
321 static pt2_entry_t *PADDR1 = NULL, *PADDR2;
323 static pt2_entry_t *PMAP3;
324 static pt2_entry_t *PADDR3;
325 static int PMAP3cpu __unused; /* for SMP only */
329 static int PMAP1changedcpu;
330 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
332 "Number of times pmap_pte2_quick changed CPU with same PMAP1");
334 static int PMAP1changed;
335 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
337 "Number of times pmap_pte2_quick changed PMAP1");
338 static int PMAP1unchanged;
339 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
341 "Number of times pmap_pte2_quick didn't change PMAP1");
342 static struct mtx PMAP2mutex;
344 static __inline void pt2_wirecount_init(vm_page_t m);
345 static boolean_t pmap_demote_pte1(pmap_t pmap, pt1_entry_t *pte1p,
347 void cache_icache_sync_fresh(vm_offset_t va, vm_paddr_t pa, vm_size_t size);
350 * Function to set the debug level of the pmap code.
354 pmap_debug(int level)
357 pmap_debug_level = level;
358 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
360 #endif /* PMAP_DEBUG */
363 * This table must corespond with memory attribute configuration in vm.h.
364 * First entry is used for normal system mapping.
366 * Device memory is always marked as shared.
367 * Normal memory is shared only in SMP .
368 * Not outer shareable bits are not used yet.
369 * Class 6 cannot be used on ARM11.
371 #define TEXDEF_TYPE_SHIFT 0
372 #define TEXDEF_TYPE_MASK 0x3
373 #define TEXDEF_INNER_SHIFT 2
374 #define TEXDEF_INNER_MASK 0x3
375 #define TEXDEF_OUTER_SHIFT 4
376 #define TEXDEF_OUTER_MASK 0x3
377 #define TEXDEF_NOS_SHIFT 6
378 #define TEXDEF_NOS_MASK 0x1
380 #define TEX(t, i, o, s) \
381 ((t) << TEXDEF_TYPE_SHIFT) | \
382 ((i) << TEXDEF_INNER_SHIFT) | \
383 ((o) << TEXDEF_OUTER_SHIFT | \
384 ((s) << TEXDEF_NOS_SHIFT))
386 static uint32_t tex_class[8] = {
387 /* type inner cache outer cache */
388 TEX(PRRR_MEM, NMRR_WB_WA, NMRR_WB_WA, 0), /* 0 - ATTR_WB_WA */
389 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 1 - ATTR_NOCACHE */
390 TEX(PRRR_DEV, NMRR_NC, NMRR_NC, 0), /* 2 - ATTR_DEVICE */
391 TEX(PRRR_SO, NMRR_NC, NMRR_NC, 0), /* 3 - ATTR_SO */
392 TEX(PRRR_MEM, NMRR_WT, NMRR_WT, 0), /* 4 - ATTR_WT */
393 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 5 - NOT USED YET */
394 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 6 - NOT USED YET */
395 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 7 - NOT USED YET */
399 static uint32_t pte2_attr_tab[8] = {
400 PTE2_ATTR_WB_WA, /* 0 - VM_MEMATTR_WB_WA */
401 PTE2_ATTR_NOCACHE, /* 1 - VM_MEMATTR_NOCACHE */
402 PTE2_ATTR_DEVICE, /* 2 - VM_MEMATTR_DEVICE */
403 PTE2_ATTR_SO, /* 3 - VM_MEMATTR_SO */
404 PTE2_ATTR_WT, /* 4 - VM_MEMATTR_WRITE_THROUGH */
405 0, /* 5 - NOT USED YET */
406 0, /* 6 - NOT USED YET */
407 0 /* 7 - NOT USED YET */
409 CTASSERT(VM_MEMATTR_WB_WA == 0);
410 CTASSERT(VM_MEMATTR_NOCACHE == 1);
411 CTASSERT(VM_MEMATTR_DEVICE == 2);
412 CTASSERT(VM_MEMATTR_SO == 3);
413 CTASSERT(VM_MEMATTR_WRITE_THROUGH == 4);
415 static inline uint32_t
416 vm_memattr_to_pte2(vm_memattr_t ma)
419 KASSERT((u_int)ma < 5, ("%s: bad vm_memattr_t %d", __func__, ma));
420 return (pte2_attr_tab[(u_int)ma]);
423 static inline uint32_t
424 vm_page_pte2_attr(vm_page_t m)
427 return (vm_memattr_to_pte2(m->md.pat_mode));
431 * Convert TEX definition entry to TTB flags.
434 encode_ttb_flags(int idx)
436 uint32_t inner, outer, nos, reg;
438 inner = (tex_class[idx] >> TEXDEF_INNER_SHIFT) &
440 outer = (tex_class[idx] >> TEXDEF_OUTER_SHIFT) &
442 nos = (tex_class[idx] >> TEXDEF_NOS_SHIFT) &
447 if (cpuinfo.coherent_walk)
448 reg |= (inner & 0x1) << 6;
449 reg |= (inner & 0x2) >> 1;
457 * Set TEX remapping registers in current CPU.
463 uint32_t type, inner, outer, nos;
466 #ifdef PMAP_PTE_NOCACHE
468 if (cpuinfo.coherent_walk) {
469 pt_memattr = VM_MEMATTR_WB_WA;
470 ttb_flags = encode_ttb_flags(0);
473 pt_memattr = VM_MEMATTR_NOCACHE;
474 ttb_flags = encode_ttb_flags(1);
477 pt_memattr = VM_MEMATTR_WB_WA;
478 ttb_flags = encode_ttb_flags(0);
484 /* Build remapping register from TEX classes. */
485 for (i = 0; i < 8; i++) {
486 type = (tex_class[i] >> TEXDEF_TYPE_SHIFT) &
488 inner = (tex_class[i] >> TEXDEF_INNER_SHIFT) &
490 outer = (tex_class[i] >> TEXDEF_OUTER_SHIFT) &
492 nos = (tex_class[i] >> TEXDEF_NOS_SHIFT) &
495 prrr |= type << (i * 2);
496 prrr |= nos << (i + 24);
497 nmrr |= inner << (i * 2);
498 nmrr |= outer << (i * 2 + 16);
500 /* Add shareable bits for device memory. */
501 prrr |= PRRR_DS0 | PRRR_DS1;
503 /* Add shareable bits for normal memory in SMP case. */
510 /* Caches are disabled, so full TLB flush should be enough. */
511 tlb_flush_all_local();
515 * KERNBASE must be multiple of NPT2_IN_PG * PTE1_SIZE. In other words,
516 * KERNBASE is mapped by first L2 page table in L2 page table page. It
517 * meets same constrain due to PT2MAP being placed just under KERNBASE.
519 CTASSERT((KERNBASE & (NPT2_IN_PG * PTE1_SIZE - 1)) == 0);
520 CTASSERT((KERNBASE - VM_MAXUSER_ADDRESS) >= PT2MAP_SIZE);
523 * In crazy dreams, PAGE_SIZE could be a multiple of PTE2_SIZE in general.
524 * For now, anyhow, the following check must be fulfilled.
526 CTASSERT(PAGE_SIZE == PTE2_SIZE);
528 * We don't want to mess up MI code with all MMU and PMAP definitions,
529 * so some things, which depend on other ones, are defined independently.
530 * Now, it is time to check that we don't screw up something.
532 CTASSERT(PDRSHIFT == PTE1_SHIFT);
534 * Check L1 and L2 page table entries definitions consistency.
536 CTASSERT(NB_IN_PT1 == (sizeof(pt1_entry_t) * NPTE1_IN_PT1));
537 CTASSERT(NB_IN_PT2 == (sizeof(pt2_entry_t) * NPTE2_IN_PT2));
539 * Check L2 page tables page consistency.
541 CTASSERT(PAGE_SIZE == (NPT2_IN_PG * NB_IN_PT2));
542 CTASSERT((1 << PT2PG_SHIFT) == NPT2_IN_PG);
544 * Check PT2TAB consistency.
545 * PT2TAB_ENTRIES is defined as a division of NPTE1_IN_PT1 by NPT2_IN_PG.
546 * This should be done without remainder.
548 CTASSERT(NPTE1_IN_PT1 == (PT2TAB_ENTRIES * NPT2_IN_PG));
553 * All level 2 page tables (PT2s) are mapped continuously and accordingly
554 * into PT2MAP address space. As PT2 size is less than PAGE_SIZE, this can
555 * be done only if PAGE_SIZE is a multiple of PT2 size. All PT2s in one page
556 * must be used together, but not necessary at once. The first PT2 in a page
557 * must map things on correctly aligned address and the others must follow
560 #define NB_IN_PT2TAB (PT2TAB_ENTRIES * sizeof(pt2_entry_t))
561 #define NPT2_IN_PT2TAB (NB_IN_PT2TAB / NB_IN_PT2)
562 #define NPG_IN_PT2TAB (NB_IN_PT2TAB / PAGE_SIZE)
565 * Check PT2TAB consistency.
566 * NPT2_IN_PT2TAB is defined as a division of NB_IN_PT2TAB by NB_IN_PT2.
567 * NPG_IN_PT2TAB is defined as a division of NB_IN_PT2TAB by PAGE_SIZE.
568 * The both should be done without remainder.
570 CTASSERT(NB_IN_PT2TAB == (NPT2_IN_PT2TAB * NB_IN_PT2));
571 CTASSERT(NB_IN_PT2TAB == (NPG_IN_PT2TAB * PAGE_SIZE));
573 * The implementation was made general, however, with the assumption
574 * bellow in mind. In case of another value of NPG_IN_PT2TAB,
575 * the code should be once more rechecked.
577 CTASSERT(NPG_IN_PT2TAB == 1);
580 * Get offset of PT2 in a page
581 * associated with given PT1 index.
583 static __inline u_int
584 page_pt2off(u_int pt1_idx)
587 return ((pt1_idx & PT2PG_MASK) * NB_IN_PT2);
591 * Get physical address of PT2
592 * associated with given PT2s page and PT1 index.
594 static __inline vm_paddr_t
595 page_pt2pa(vm_paddr_t pgpa, u_int pt1_idx)
598 return (pgpa + page_pt2off(pt1_idx));
602 * Get first entry of PT2
603 * associated with given PT2s page and PT1 index.
605 static __inline pt2_entry_t *
606 page_pt2(vm_offset_t pgva, u_int pt1_idx)
609 return ((pt2_entry_t *)(pgva + page_pt2off(pt1_idx)));
613 * Get virtual address of PT2s page (mapped in PT2MAP)
614 * which holds PT2 which holds entry which maps given virtual address.
616 static __inline vm_offset_t
617 pt2map_pt2pg(vm_offset_t va)
620 va &= ~(NPT2_IN_PG * PTE1_SIZE - 1);
621 return ((vm_offset_t)pt2map_entry(va));
624 /*****************************************************************************
626 * THREE pmap initialization milestones exist:
629 * -> fundamental init (including MMU) in ASM
632 * -> fundamental init continues in C
633 * -> first available physical address is known
635 * pmap_bootstrap_prepare() -> FIRST PMAP MILESTONE (first epoch begins)
636 * -> basic (safe) interface for physical address allocation is made
637 * -> basic (safe) interface for virtual mapping is made
638 * -> limited not SMP coherent work is possible
640 * -> more fundamental init continues in C
641 * -> locks and some more things are available
642 * -> all fundamental allocations and mappings are done
644 * pmap_bootstrap() -> SECOND PMAP MILESTONE (second epoch begins)
645 * -> phys_avail[] and virtual_avail is set
646 * -> control is passed to vm subsystem
647 * -> physical and virtual address allocation are off limit
648 * -> low level mapping functions, some SMP coherent,
649 * are available, which cannot be used before vm subsystem
653 * -> vm subsystem is being inited
655 * pmap_init() -> THIRD PMAP MILESTONE (third epoch begins)
656 * -> pmap is fully inited
658 *****************************************************************************/
660 /*****************************************************************************
662 * PMAP first stage initialization and utility functions
663 * for pre-bootstrap epoch.
665 * After pmap_bootstrap_prepare() is called, the following functions
668 * (1) strictly only for this stage functions for physical page allocations,
669 * virtual space allocations, and mappings:
671 * vm_paddr_t pmap_preboot_get_pages(u_int num);
672 * void pmap_preboot_map_pages(vm_paddr_t pa, vm_offset_t va, u_int num);
673 * vm_offset_t pmap_preboot_reserve_pages(u_int num);
674 * vm_offset_t pmap_preboot_get_vpages(u_int num);
675 * void pmap_preboot_map_attr(vm_paddr_t pa, vm_offset_t va, vm_size_t size,
676 * vm_prot_t prot, vm_memattr_t attr);
678 * (2) for all stages:
680 * vm_paddr_t pmap_kextract(vm_offset_t va);
682 * NOTE: This is not SMP coherent stage.
684 *****************************************************************************/
686 #define KERNEL_P2V(pa) \
687 ((vm_offset_t)((pa) - arm_physmem_kernaddr + KERNVIRTADDR))
688 #define KERNEL_V2P(va) \
689 ((vm_paddr_t)((va) - KERNVIRTADDR + arm_physmem_kernaddr))
691 static vm_paddr_t last_paddr;
694 * Pre-bootstrap epoch page allocator.
697 pmap_preboot_get_pages(u_int num)
702 last_paddr += num * PAGE_SIZE;
708 * The fundamental initialization of PMAP stuff.
710 * Some things already happened in locore.S and some things could happen
711 * before pmap_bootstrap_prepare() is called, so let's recall what is done:
712 * 1. Caches are disabled.
713 * 2. We are running on virtual addresses already with 'boot_pt1'
715 * 3. So far, all virtual addresses can be converted to physical ones and
716 * vice versa by the following macros:
717 * KERNEL_P2V(pa) .... physical to virtual ones,
718 * KERNEL_V2P(va) .... virtual to physical ones.
720 * What is done herein:
721 * 1. The 'boot_pt1' is replaced by real kernel L1 page table 'kern_pt1'.
722 * 2. PT2MAP magic is brought to live.
723 * 3. Basic preboot functions for page allocations and mappings can be used.
724 * 4. Everything is prepared for L1 cache enabling.
727 * 1. To use second TTB register, so kernel and users page tables will be
728 * separated. This way process forking - pmap_pinit() - could be faster,
729 * it saves physical pages and KVA per a process, and it's simple change.
730 * However, it will lead, due to hardware matter, to the following:
731 * (a) 2G space for kernel and 2G space for users.
732 * (b) 1G space for kernel in low addresses and 3G for users above it.
733 * A question is: Is the case (b) really an option? Note that case (b)
734 * does save neither physical memory and KVA.
737 pmap_bootstrap_prepare(vm_paddr_t last)
739 vm_paddr_t pt2pg_pa, pt2tab_pa, pa, size;
740 vm_offset_t pt2pg_va;
744 uint32_t actlr_mask, actlr_set, l1_attr;
747 * Now, we are going to make real kernel mapping. Note that we are
748 * already running on some mapping made in locore.S and we expect
749 * that it's large enough to ensure nofault access to physical memory
750 * allocated herein before switch.
752 * As kernel image and everything needed before are and will be mapped
753 * by section mappings, we align last physical address to PTE1_SIZE.
755 last_paddr = pte1_roundup(last);
758 * Allocate and zero page(s) for kernel L1 page table.
760 * Note that it's first allocation on space which was PTE1_SIZE
761 * aligned and as such base_pt1 is aligned to NB_IN_PT1 too.
763 base_pt1 = pmap_preboot_get_pages(NPG_IN_PT1);
764 kern_pt1 = (pt1_entry_t *)KERNEL_P2V(base_pt1);
765 bzero((void*)kern_pt1, NB_IN_PT1);
766 pte1_sync_range(kern_pt1, NB_IN_PT1);
768 /* Allocate and zero page(s) for kernel PT2TAB. */
769 pt2tab_pa = pmap_preboot_get_pages(NPG_IN_PT2TAB);
770 kern_pt2tab = (pt2_entry_t *)KERNEL_P2V(pt2tab_pa);
771 bzero(kern_pt2tab, NB_IN_PT2TAB);
772 pte2_sync_range(kern_pt2tab, NB_IN_PT2TAB);
774 /* Allocate and zero page(s) for kernel L2 page tables. */
775 pt2pg_pa = pmap_preboot_get_pages(NKPT2PG);
776 pt2pg_va = KERNEL_P2V(pt2pg_pa);
777 size = NKPT2PG * PAGE_SIZE;
778 bzero((void*)pt2pg_va, size);
779 pte2_sync_range((pt2_entry_t *)pt2pg_va, size);
782 * Add a physical memory segment (vm_phys_seg) corresponding to the
783 * preallocated pages for kernel L2 page tables so that vm_page
784 * structures representing these pages will be created. The vm_page
785 * structures are required for promotion of the corresponding kernel
786 * virtual addresses to section mappings.
788 vm_phys_add_seg(pt2tab_pa, pmap_preboot_get_pages(0));
791 * Insert allocated L2 page table pages to PT2TAB and make
792 * link to all PT2s in L1 page table. See how kernel_vm_end
795 * We play simple and safe. So every KVA will have underlaying
796 * L2 page table, even kernel image mapped by sections.
798 pte2p = kern_pt2tab_entry(KERNBASE);
799 for (pa = pt2pg_pa; pa < pt2pg_pa + size; pa += PTE2_SIZE)
800 pt2tab_store(pte2p++, PTE2_KPT(pa));
802 pte1p = kern_pte1(KERNBASE);
803 for (pa = pt2pg_pa; pa < pt2pg_pa + size; pa += NB_IN_PT2)
804 pte1_store(pte1p++, PTE1_LINK(pa));
806 /* Make section mappings for kernel. */
807 l1_attr = ATTR_TO_L1(PTE2_ATTR_DEFAULT);
808 pte1p = kern_pte1(KERNBASE);
809 for (pa = KERNEL_V2P(KERNBASE); pa < last; pa += PTE1_SIZE)
810 pte1_store(pte1p++, PTE1_KERN(pa, PTE1_AP_KRW, l1_attr));
813 * Get free and aligned space for PT2MAP and make L1 page table links
814 * to L2 page tables held in PT2TAB.
816 * Note that pages holding PT2s are stored in PT2TAB as pt2_entry_t
817 * descriptors and PT2TAB page(s) itself is(are) used as PT2s. Thus
818 * each entry in PT2TAB maps all PT2s in a page. This implies that
819 * virtual address of PT2MAP must be aligned to NPT2_IN_PG * PTE1_SIZE.
821 PT2MAP = (pt2_entry_t *)(KERNBASE - PT2MAP_SIZE);
822 pte1p = kern_pte1((vm_offset_t)PT2MAP);
823 for (pa = pt2tab_pa, i = 0; i < NPT2_IN_PT2TAB; i++, pa += NB_IN_PT2) {
824 pte1_store(pte1p++, PTE1_LINK(pa));
828 * Store PT2TAB in PT2TAB itself, i.e. self reference mapping.
829 * Each pmap will hold own PT2TAB, so the mapping should be not global.
831 pte2p = kern_pt2tab_entry((vm_offset_t)PT2MAP);
832 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE) {
833 pt2tab_store(pte2p++, PTE2_KPT_NG(pa));
837 * Choose correct L2 page table and make mappings for allocations
838 * made herein which replaces temporary locore.S mappings after a while.
839 * Note that PT2MAP cannot be used until we switch to kern_pt1.
841 * Note, that these allocations started aligned on 1M section and
842 * kernel PT1 was allocated first. Making of mappings must follow
843 * order of physical allocations as we've used KERNEL_P2V() macro
844 * for virtual addresses resolution.
846 pte2p = kern_pt2tab_entry((vm_offset_t)kern_pt1);
847 pt2pg_va = KERNEL_P2V(pte2_pa(pte2_load(pte2p)));
849 pte2p = page_pt2(pt2pg_va, pte1_index((vm_offset_t)kern_pt1));
851 /* Make mapping for kernel L1 page table. */
852 for (pa = base_pt1, i = 0; i < NPG_IN_PT1; i++, pa += PTE2_SIZE)
853 pte2_store(pte2p++, PTE2_KPT(pa));
855 /* Make mapping for kernel PT2TAB. */
856 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE)
857 pte2_store(pte2p++, PTE2_KPT(pa));
859 /* Finally, switch from 'boot_pt1' to 'kern_pt1'. */
860 pmap_kern_ttb = base_pt1 | ttb_flags;
861 cpuinfo_get_actlr_modifier(&actlr_mask, &actlr_set);
862 reinit_mmu(pmap_kern_ttb, actlr_mask, actlr_set);
864 * Initialize the first available KVA. As kernel image is mapped by
865 * sections, we are leaving some gap behind.
867 virtual_avail = (vm_offset_t)kern_pt2tab + NPG_IN_PT2TAB * PAGE_SIZE;
871 * Setup L2 page table page for given KVA.
872 * Used in pre-bootstrap epoch.
874 * Note that we have allocated NKPT2PG pages for L2 page tables in advance
875 * and used them for mapping KVA starting from KERNBASE. However, this is not
876 * enough. Vectors and devices need L2 page tables too. Note that they are
877 * even above VM_MAX_KERNEL_ADDRESS.
879 static __inline vm_paddr_t
880 pmap_preboot_pt2pg_setup(vm_offset_t va)
882 pt2_entry_t *pte2p, pte2;
885 /* Get associated entry in PT2TAB. */
886 pte2p = kern_pt2tab_entry(va);
888 /* Just return, if PT2s page exists already. */
889 pte2 = pt2tab_load(pte2p);
890 if (pte2_is_valid(pte2))
891 return (pte2_pa(pte2));
893 KASSERT(va >= VM_MAX_KERNEL_ADDRESS,
894 ("%s: NKPT2PG too small", __func__));
897 * Allocate page for PT2s and insert it to PT2TAB.
898 * In other words, map it into PT2MAP space.
900 pt2pg_pa = pmap_preboot_get_pages(1);
901 pt2tab_store(pte2p, PTE2_KPT(pt2pg_pa));
903 /* Zero all PT2s in allocated page. */
904 bzero((void*)pt2map_pt2pg(va), PAGE_SIZE);
905 pte2_sync_range((pt2_entry_t *)pt2map_pt2pg(va), PAGE_SIZE);
911 * Setup L2 page table for given KVA.
912 * Used in pre-bootstrap epoch.
915 pmap_preboot_pt2_setup(vm_offset_t va)
918 vm_paddr_t pt2pg_pa, pt2_pa;
920 /* Setup PT2's page. */
921 pt2pg_pa = pmap_preboot_pt2pg_setup(va);
922 pt2_pa = page_pt2pa(pt2pg_pa, pte1_index(va));
924 /* Insert PT2 to PT1. */
925 pte1p = kern_pte1(va);
926 pte1_store(pte1p, PTE1_LINK(pt2_pa));
930 * Get L2 page entry associated with given KVA.
931 * Used in pre-bootstrap epoch.
933 static __inline pt2_entry_t*
934 pmap_preboot_vtopte2(vm_offset_t va)
938 /* Setup PT2 if needed. */
939 pte1p = kern_pte1(va);
940 if (!pte1_is_valid(pte1_load(pte1p))) /* XXX - sections ?! */
941 pmap_preboot_pt2_setup(va);
943 return (pt2map_entry(va));
947 * Pre-bootstrap epoch page(s) mapping(s).
950 pmap_preboot_map_pages(vm_paddr_t pa, vm_offset_t va, u_int num)
955 /* Map all the pages. */
956 for (i = 0; i < num; i++) {
957 pte2p = pmap_preboot_vtopte2(va);
958 pte2_store(pte2p, PTE2_KRW(pa));
965 * Pre-bootstrap epoch virtual space alocator.
968 pmap_preboot_reserve_pages(u_int num)
971 vm_offset_t start, va;
974 /* Allocate virtual space. */
975 start = va = virtual_avail;
976 virtual_avail += num * PAGE_SIZE;
978 /* Zero the mapping. */
979 for (i = 0; i < num; i++) {
980 pte2p = pmap_preboot_vtopte2(va);
981 pte2_store(pte2p, 0);
989 * Pre-bootstrap epoch page(s) allocation and mapping(s).
992 pmap_preboot_get_vpages(u_int num)
997 /* Allocate physical page(s). */
998 pa = pmap_preboot_get_pages(num);
1000 /* Allocate virtual space. */
1002 virtual_avail += num * PAGE_SIZE;
1004 /* Map and zero all. */
1005 pmap_preboot_map_pages(pa, va, num);
1006 bzero((void *)va, num * PAGE_SIZE);
1012 * Pre-bootstrap epoch page mapping(s) with attributes.
1015 pmap_preboot_map_attr(vm_paddr_t pa, vm_offset_t va, vm_size_t size,
1016 vm_prot_t prot, vm_memattr_t attr)
1019 u_int l1_attr, l1_prot, l2_prot, l2_attr;
1023 l2_prot = prot & VM_PROT_WRITE ? PTE2_AP_KRW : PTE2_AP_KR;
1024 l2_prot |= (prot & VM_PROT_EXECUTE) ? PTE2_X : PTE2_NX;
1025 l2_attr = vm_memattr_to_pte2(attr);
1026 l1_prot = ATTR_TO_L1(l2_prot);
1027 l1_attr = ATTR_TO_L1(l2_attr);
1029 /* Map all the pages. */
1030 num = round_page(size);
1032 if ((((va | pa) & PTE1_OFFSET) == 0) && (num >= PTE1_SIZE)) {
1033 pte1p = kern_pte1(va);
1034 pte1_store(pte1p, PTE1_KERN(pa, l1_prot, l1_attr));
1039 pte2p = pmap_preboot_vtopte2(va);
1040 pte2_store(pte2p, PTE2_KERN(pa, l2_prot, l2_attr));
1049 * Extract from the kernel page table the physical address
1050 * that is mapped by the given virtual address "va".
1053 pmap_kextract(vm_offset_t va)
1059 pte1 = pte1_load(kern_pte1(va));
1060 if (pte1_is_section(pte1)) {
1061 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1062 } else if (pte1_is_link(pte1)) {
1064 * We should beware of concurrent promotion that changes
1065 * pte1 at this point. However, it's not a problem as PT2
1066 * page is preserved by promotion in PT2TAB. So even if
1067 * it happens, using of PT2MAP is still safe.
1069 * QQQ: However, concurrent removing is a problem which
1070 * ends in abort on PT2MAP space. Locking must be used
1071 * to deal with this.
1073 pte2 = pte2_load(pt2map_entry(va));
1074 pa = pte2_pa(pte2) | (va & PTE2_OFFSET);
1077 panic("%s: va %#x pte1 %#x", __func__, va, pte1);
1083 * Extract from the kernel page table the physical address
1084 * that is mapped by the given virtual address "va". Also
1085 * return L2 page table entry which maps the address.
1087 * This is only intended to be used for panic dumps.
1090 pmap_dump_kextract(vm_offset_t va, pt2_entry_t *pte2p)
1096 pte1 = pte1_load(kern_pte1(va));
1097 if (pte1_is_section(pte1)) {
1098 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1099 pte2 = pa | ATTR_TO_L2(pte1) | PTE2_V;
1100 } else if (pte1_is_link(pte1)) {
1101 pte2 = pte2_load(pt2map_entry(va));
1112 /*****************************************************************************
1114 * PMAP second stage initialization and utility functions
1115 * for bootstrap epoch.
1117 * After pmap_bootstrap() is called, the following functions for
1118 * mappings can be used:
1120 * void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
1121 * void pmap_kremove(vm_offset_t va);
1122 * vm_offset_t pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end,
1125 * NOTE: This is not SMP coherent stage. And physical page allocation is not
1126 * allowed during this stage.
1128 *****************************************************************************/
1131 * Initialize kernel PMAP locks and lists, kernel_pmap itself, and
1132 * reserve various virtual spaces for temporary mappings.
1135 pmap_bootstrap(vm_offset_t firstaddr)
1137 pt2_entry_t *unused __unused;
1138 struct sysmaps *sysmaps;
1142 * Initialize the kernel pmap (which is statically allocated).
1144 PMAP_LOCK_INIT(kernel_pmap);
1145 kernel_l1pa = (vm_paddr_t)kern_pt1; /* for libkvm */
1146 kernel_pmap->pm_pt1 = kern_pt1;
1147 kernel_pmap->pm_pt2tab = kern_pt2tab;
1148 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1149 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1152 * Initialize the global pv list lock.
1154 rw_init(&pvh_global_lock, "pmap pv global");
1156 LIST_INIT(&allpmaps);
1159 * Request a spin mutex so that changes to allpmaps cannot be
1160 * preempted by smp_rendezvous_cpus().
1162 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
1163 mtx_lock_spin(&allpmaps_lock);
1164 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
1165 mtx_unlock_spin(&allpmaps_lock);
1168 * Reserve some special page table entries/VA space for temporary
1171 #define SYSMAP(c, p, v, n) do { \
1172 v = (c)pmap_preboot_reserve_pages(n); \
1173 p = pt2map_entry((vm_offset_t)v); \
1177 * Local CMAP1/CMAP2 are used for zeroing and copying pages.
1178 * Local CMAP3 is used for data cache cleaning.
1179 * Global CMAP3 is used for the idle process page zeroing.
1181 for (i = 0; i < MAXCPU; i++) {
1182 sysmaps = &sysmaps_pcpu[i];
1183 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF);
1184 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1);
1185 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1);
1186 SYSMAP(caddr_t, sysmaps->CMAP3, sysmaps->CADDR3, 1);
1188 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
1193 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS);
1196 * _tmppt is used for reading arbitrary physical pages via /dev/mem.
1198 SYSMAP(caddr_t, unused, _tmppt, 1);
1201 * PADDR1 and PADDR2 are used by pmap_pte2_quick() and pmap_pte2(),
1202 * respectively. PADDR3 is used by pmap_pte2_ddb().
1204 SYSMAP(pt2_entry_t *, PMAP1, PADDR1, 1);
1205 SYSMAP(pt2_entry_t *, PMAP2, PADDR2, 1);
1207 SYSMAP(pt2_entry_t *, PMAP3, PADDR3, 1);
1209 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
1212 * Note that in very short time in initarm(), we are going to
1213 * initialize phys_avail[] array and no further page allocation
1214 * can happen after that until vm subsystem will be initialized.
1216 kernel_vm_end_new = kernel_vm_end;
1217 virtual_end = vm_max_kernel_address;
1221 pmap_init_qpages(void)
1228 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE);
1229 if (pc->pc_qmap_addr == 0)
1230 panic("%s: unable to allocate KVA", __func__);
1233 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_qpages, NULL);
1236 * The function can already be use in second initialization stage.
1237 * As such, the function DOES NOT call pmap_growkernel() where PT2
1238 * allocation can happen. So if used, be sure that PT2 for given
1239 * virtual address is allocated already!
1241 * Add a wired page to the kva.
1242 * Note: not SMP coherent.
1244 static __inline void
1245 pmap_kenter_prot_attr(vm_offset_t va, vm_paddr_t pa, uint32_t prot,
1251 pte1p = kern_pte1(va);
1252 if (!pte1_is_valid(pte1_load(pte1p))) { /* XXX - sections ?! */
1254 * This is a very low level function, so PT2 and particularly
1255 * PT2PG associated with given virtual address must be already
1256 * allocated. It's a pain mainly during pmap initialization
1257 * stage. However, called after pmap initialization with
1258 * virtual address not under kernel_vm_end will lead to
1261 if (!pte2_is_valid(pte2_load(kern_pt2tab_entry(va))))
1262 panic("%s: kernel PT2 not allocated!", __func__);
1265 pte2p = pt2map_entry(va);
1266 pte2_store(pte2p, PTE2_KERN(pa, prot, attr));
1270 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1273 pmap_kenter_prot_attr(va, pa, PTE2_AP_KRW, PTE2_ATTR_DEFAULT);
1277 * Remove a page from the kernel pagetables.
1278 * Note: not SMP coherent.
1281 pmap_kremove(vm_offset_t va)
1285 pte2p = pt2map_entry(va);
1290 * Share new kernel PT2PG with all pmaps.
1291 * The caller is responsible for maintaining TLB consistency.
1294 pmap_kenter_pt2tab(vm_offset_t va, pt2_entry_t npte2)
1299 mtx_lock_spin(&allpmaps_lock);
1300 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1301 pte2p = pmap_pt2tab_entry(pmap, va);
1302 pt2tab_store(pte2p, npte2);
1304 mtx_unlock_spin(&allpmaps_lock);
1308 * Share new kernel PTE1 with all pmaps.
1309 * The caller is responsible for maintaining TLB consistency.
1312 pmap_kenter_pte1(vm_offset_t va, pt1_entry_t npte1)
1317 mtx_lock_spin(&allpmaps_lock);
1318 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1319 pte1p = pmap_pte1(pmap, va);
1320 pte1_store(pte1p, npte1);
1322 mtx_unlock_spin(&allpmaps_lock);
1326 * Used to map a range of physical addresses into kernel
1327 * virtual address space.
1329 * The value passed in '*virt' is a suggested virtual address for
1330 * the mapping. Architectures which can support a direct-mapped
1331 * physical to virtual region can return the appropriate address
1332 * within that region, leaving '*virt' unchanged. Other
1333 * architectures should map the pages starting at '*virt' and
1334 * update '*virt' with the first usable address after the mapped
1337 * NOTE: Read the comments above pmap_kenter_prot_attr() as
1338 * the function is used herein!
1341 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1343 vm_offset_t va, sva;
1344 vm_paddr_t pte1_offset;
1346 uint32_t l1prot, l2prot;
1347 uint32_t l1attr, l2attr;
1349 PDEBUG(1, printf("%s: virt = %#x, start = %#x, end = %#x (size = %#x),"
1350 " prot = %d\n", __func__, *virt, start, end, end - start, prot));
1352 l2prot = (prot & VM_PROT_WRITE) ? PTE2_AP_KRW : PTE2_AP_KR;
1353 l2prot |= (prot & VM_PROT_EXECUTE) ? PTE2_X : PTE2_NX;
1354 l1prot = ATTR_TO_L1(l2prot);
1356 l2attr = PTE2_ATTR_DEFAULT;
1357 l1attr = ATTR_TO_L1(l2attr);
1361 * Does the physical address range's size and alignment permit at
1362 * least one section mapping to be created?
1364 pte1_offset = start & PTE1_OFFSET;
1365 if ((end - start) - ((PTE1_SIZE - pte1_offset) & PTE1_OFFSET) >=
1368 * Increase the starting virtual address so that its alignment
1369 * does not preclude the use of section mappings.
1371 if ((va & PTE1_OFFSET) < pte1_offset)
1372 va = pte1_trunc(va) + pte1_offset;
1373 else if ((va & PTE1_OFFSET) > pte1_offset)
1374 va = pte1_roundup(va) + pte1_offset;
1377 while (start < end) {
1378 if ((start & PTE1_OFFSET) == 0 && end - start >= PTE1_SIZE) {
1379 KASSERT((va & PTE1_OFFSET) == 0,
1380 ("%s: misaligned va %#x", __func__, va));
1381 npte1 = PTE1_KERN(start, l1prot, l1attr);
1382 pmap_kenter_pte1(va, npte1);
1386 pmap_kenter_prot_attr(va, start, l2prot, l2attr);
1391 tlb_flush_range(sva, va - sva);
1397 * Make a temporary mapping for a physical address.
1398 * This is only intended to be used for panic dumps.
1401 pmap_kenter_temporary(vm_paddr_t pa, int i)
1405 /* QQQ: 'i' should be less or equal to MAXDUMPPGS. */
1407 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
1408 pmap_kenter(va, pa);
1409 tlb_flush_local(va);
1410 return ((void *)crashdumpmap);
1414 /*************************************
1416 * TLB & cache maintenance routines.
1418 *************************************/
1421 * We inline these within pmap.c for speed.
1424 pmap_tlb_flush(pmap_t pmap, vm_offset_t va)
1427 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1432 pmap_tlb_flush_range(pmap_t pmap, vm_offset_t sva, vm_size_t size)
1435 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1436 tlb_flush_range(sva, size);
1440 * Abuse the pte2 nodes for unmapped kva to thread a kva freelist through.
1442 * - Must deal with pages in order to ensure that none of the PTE2_* bits
1443 * are ever set, PTE2_V in particular.
1444 * - Assumes we can write to pte2s without pte2_store() atomic ops.
1445 * - Assumes nothing will ever test these addresses for 0 to indicate
1446 * no mapping instead of correctly checking PTE2_V.
1447 * - Assumes a vm_offset_t will fit in a pte2 (true for arm).
1448 * Because PTE2_V is never set, there can be no mappings to invalidate.
1451 pmap_pte2list_alloc(vm_offset_t *head)
1458 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
1459 pte2p = pt2map_entry(va);
1462 panic("%s: va with PTE2_V set!", __func__);
1468 pmap_pte2list_free(vm_offset_t *head, vm_offset_t va)
1473 panic("%s: freeing va with PTE2_V set!", __func__);
1474 pte2p = pt2map_entry(va);
1475 *pte2p = *head; /* virtual! PTE2_V is 0 though */
1480 pmap_pte2list_init(vm_offset_t *head, void *base, int npages)
1486 for (i = npages - 1; i >= 0; i--) {
1487 va = (vm_offset_t)base + i * PAGE_SIZE;
1488 pmap_pte2list_free(head, va);
1492 /*****************************************************************************
1494 * PMAP third and final stage initialization.
1496 * After pmap_init() is called, PMAP subsystem is fully initialized.
1498 *****************************************************************************/
1500 SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
1502 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
1503 "Max number of PV entries");
1504 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
1505 "Page share factor per proc");
1507 static u_long nkpt2pg = NKPT2PG;
1508 SYSCTL_ULONG(_vm_pmap, OID_AUTO, nkpt2pg, CTLFLAG_RD,
1509 &nkpt2pg, 0, "Pre-allocated pages for kernel PT2s");
1511 static int sp_enabled = 1;
1512 SYSCTL_INT(_vm_pmap, OID_AUTO, sp_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
1513 &sp_enabled, 0, "Are large page mappings enabled?");
1515 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pte1, CTLFLAG_RD, 0,
1516 "1MB page mapping counters");
1518 static u_long pmap_pte1_demotions;
1519 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, demotions, CTLFLAG_RD,
1520 &pmap_pte1_demotions, 0, "1MB page demotions");
1522 static u_long pmap_pte1_mappings;
1523 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, mappings, CTLFLAG_RD,
1524 &pmap_pte1_mappings, 0, "1MB page mappings");
1526 static u_long pmap_pte1_p_failures;
1527 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, p_failures, CTLFLAG_RD,
1528 &pmap_pte1_p_failures, 0, "1MB page promotion failures");
1530 static u_long pmap_pte1_promotions;
1531 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, promotions, CTLFLAG_RD,
1532 &pmap_pte1_promotions, 0, "1MB page promotions");
1534 static u_long pmap_pte1_kern_demotions;
1535 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, kern_demotions, CTLFLAG_RD,
1536 &pmap_pte1_kern_demotions, 0, "1MB page kernel demotions");
1538 static u_long pmap_pte1_kern_promotions;
1539 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, kern_promotions, CTLFLAG_RD,
1540 &pmap_pte1_kern_promotions, 0, "1MB page kernel promotions");
1542 static __inline ttb_entry_t
1543 pmap_ttb_get(pmap_t pmap)
1546 return (vtophys(pmap->pm_pt1) | ttb_flags);
1550 * Initialize a vm_page's machine-dependent fields.
1553 * 1. Pages for L2 page tables are always not managed. So, pv_list and
1554 * pt2_wirecount can share same physical space. However, proper
1555 * initialization on a page alloc for page tables and reinitialization
1556 * on the page free must be ensured.
1559 pmap_page_init(vm_page_t m)
1562 TAILQ_INIT(&m->md.pv_list);
1563 pt2_wirecount_init(m);
1564 m->md.pat_mode = VM_MEMATTR_DEFAULT;
1568 * Virtualization for faster way how to zero whole page.
1570 static __inline void
1571 pagezero(void *page)
1574 bzero(page, PAGE_SIZE);
1578 * Zero L2 page table page.
1579 * Use same KVA as in pmap_zero_page().
1581 static __inline vm_paddr_t
1582 pmap_pt2pg_zero(vm_page_t m)
1585 struct sysmaps *sysmaps;
1587 pa = VM_PAGE_TO_PHYS(m);
1590 * XXX: For now, we map whole page even if it's already zero,
1591 * to sync it even if the sync is only DSB.
1594 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
1595 mtx_lock(&sysmaps->lock);
1596 if (pte2_load(sysmaps->CMAP2) != 0)
1597 panic("%s: CMAP2 busy", __func__);
1598 pte2_store(sysmaps->CMAP2, PTE2_KERN_NG(pa, PTE2_AP_KRW,
1599 vm_page_pte2_attr(m)));
1600 /* Even VM_ALLOC_ZERO request is only advisory. */
1601 if ((m->flags & PG_ZERO) == 0)
1602 pagezero(sysmaps->CADDR2);
1603 pte2_sync_range((pt2_entry_t *)sysmaps->CADDR2, PAGE_SIZE);
1604 pte2_clear(sysmaps->CMAP2);
1605 tlb_flush((vm_offset_t)sysmaps->CADDR2);
1607 mtx_unlock(&sysmaps->lock);
1613 * Init just allocated page as L2 page table(s) holder
1614 * and return its physical address.
1616 static __inline vm_paddr_t
1617 pmap_pt2pg_init(pmap_t pmap, vm_offset_t va, vm_page_t m)
1622 /* Check page attributes. */
1623 if (m->md.pat_mode != pt_memattr)
1624 pmap_page_set_memattr(m, pt_memattr);
1626 /* Zero page and init wire counts. */
1627 pa = pmap_pt2pg_zero(m);
1628 pt2_wirecount_init(m);
1631 * Map page to PT2MAP address space for given pmap.
1632 * Note that PT2MAP space is shared with all pmaps.
1634 if (pmap == kernel_pmap)
1635 pmap_kenter_pt2tab(va, PTE2_KPT(pa));
1637 pte2p = pmap_pt2tab_entry(pmap, va);
1638 pt2tab_store(pte2p, PTE2_KPT_NG(pa));
1645 * Initialize the pmap module.
1646 * Called by vm_init, to initialize any structures that the pmap
1647 * system needs to map virtual memory.
1653 pt2_entry_t *pte2p, pte2;
1654 u_int i, pte1_idx, pv_npg;
1656 PDEBUG(1, printf("%s: phys_start = %#x\n", __func__, PHYSADDR));
1659 * Initialize the vm page array entries for kernel pmap's
1660 * L2 page table pages allocated in advance.
1662 pte1_idx = pte1_index(KERNBASE - PT2MAP_SIZE);
1663 pte2p = kern_pt2tab_entry(KERNBASE - PT2MAP_SIZE);
1664 for (i = 0; i < nkpt2pg + NPG_IN_PT2TAB; i++, pte2p++) {
1668 pte2 = pte2_load(pte2p);
1669 KASSERT(pte2_is_valid(pte2), ("%s: no valid entry", __func__));
1672 m = PHYS_TO_VM_PAGE(pa);
1673 KASSERT(m >= vm_page_array &&
1674 m < &vm_page_array[vm_page_array_size],
1675 ("%s: L2 page table page is out of range", __func__));
1677 m->pindex = pte1_idx;
1679 pte1_idx += NPT2_IN_PG;
1683 * Initialize the address space (zone) for the pv entries. Set a
1684 * high water mark so that the system can recover from excessive
1685 * numbers of pv entries.
1687 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1688 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1689 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1690 pv_entry_max = roundup(pv_entry_max, _NPCPV);
1691 pv_entry_high_water = 9 * (pv_entry_max / 10);
1694 * Are large page mappings enabled?
1696 TUNABLE_INT_FETCH("vm.pmap.sp_enabled", &sp_enabled);
1698 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1699 ("%s: can't assign to pagesizes[1]", __func__));
1700 pagesizes[1] = PTE1_SIZE;
1704 * Calculate the size of the pv head table for sections.
1705 * Handle the possibility that "vm_phys_segs[...].end" is zero.
1706 * Note that the table is only for sections which could be promoted.
1708 first_managed_pa = pte1_trunc(vm_phys_segs[0].start);
1709 pv_npg = (pte1_trunc(vm_phys_segs[vm_phys_nsegs - 1].end - PAGE_SIZE)
1710 - first_managed_pa) / PTE1_SIZE + 1;
1713 * Allocate memory for the pv head table for sections.
1715 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1717 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
1719 for (i = 0; i < pv_npg; i++)
1720 TAILQ_INIT(&pv_table[i].pv_list);
1722 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
1723 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
1724 if (pv_chunkbase == NULL)
1725 panic("%s: not enough kvm for pv chunks", __func__);
1726 pmap_pte2list_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
1730 * Add a list of wired pages to the kva
1731 * this routine is only used for temporary
1732 * kernel mappings that do not need to have
1733 * page modification or references recorded.
1734 * Note that old mappings are simply written
1735 * over. The page *must* be wired.
1736 * Note: SMP coherent. Uses a ranged shootdown IPI.
1739 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1742 pt2_entry_t *epte2p, *pte2p, pte2;
1747 pte2p = pt2map_entry(sva);
1748 epte2p = pte2p + count;
1749 while (pte2p < epte2p) {
1751 pa = VM_PAGE_TO_PHYS(m);
1752 pte2 = pte2_load(pte2p);
1753 if ((pte2_pa(pte2) != pa) ||
1754 (pte2_attr(pte2) != vm_page_pte2_attr(m))) {
1756 pte2_store(pte2p, PTE2_KERN(pa, PTE2_AP_KRW,
1757 vm_page_pte2_attr(m)));
1761 if (__predict_false(anychanged))
1762 tlb_flush_range(sva, count * PAGE_SIZE);
1766 * This routine tears out page mappings from the
1767 * kernel -- it is meant only for temporary mappings.
1768 * Note: SMP coherent. Uses a ranged shootdown IPI.
1771 pmap_qremove(vm_offset_t sva, int count)
1776 while (count-- > 0) {
1780 tlb_flush_range(sva, va - sva);
1784 * Are we current address space or kernel?
1787 pmap_is_current(pmap_t pmap)
1790 return (pmap == kernel_pmap ||
1791 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace)));
1795 * If the given pmap is not the current or kernel pmap, the returned
1796 * pte2 must be released by passing it to pmap_pte2_release().
1798 static pt2_entry_t *
1799 pmap_pte2(pmap_t pmap, vm_offset_t va)
1802 vm_paddr_t pt2pg_pa;
1804 pte1 = pte1_load(pmap_pte1(pmap, va));
1805 if (pte1_is_section(pte1))
1806 panic("%s: attempt to map PTE1", __func__);
1807 if (pte1_is_link(pte1)) {
1808 /* Are we current address space or kernel? */
1809 if (pmap_is_current(pmap))
1810 return (pt2map_entry(va));
1811 /* Note that L2 page table size is not equal to PAGE_SIZE. */
1812 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
1813 mtx_lock(&PMAP2mutex);
1814 if (pte2_pa(pte2_load(PMAP2)) != pt2pg_pa) {
1815 pte2_store(PMAP2, PTE2_KPT(pt2pg_pa));
1816 tlb_flush((vm_offset_t)PADDR2);
1818 return (PADDR2 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
1824 * Releases a pte2 that was obtained from pmap_pte2().
1825 * Be prepared for the pte2p being NULL.
1827 static __inline void
1828 pmap_pte2_release(pt2_entry_t *pte2p)
1831 if ((pt2_entry_t *)(trunc_page((vm_offset_t)pte2p)) == PADDR2) {
1832 mtx_unlock(&PMAP2mutex);
1837 * Super fast pmap_pte2 routine best used when scanning
1838 * the pv lists. This eliminates many coarse-grained
1839 * invltlb calls. Note that many of the pv list
1840 * scans are across different pmaps. It is very wasteful
1841 * to do an entire tlb flush for checking a single mapping.
1843 * If the given pmap is not the current pmap, pvh_global_lock
1844 * must be held and curthread pinned to a CPU.
1846 static pt2_entry_t *
1847 pmap_pte2_quick(pmap_t pmap, vm_offset_t va)
1850 vm_paddr_t pt2pg_pa;
1852 pte1 = pte1_load(pmap_pte1(pmap, va));
1853 if (pte1_is_section(pte1))
1854 panic("%s: attempt to map PTE1", __func__);
1855 if (pte1_is_link(pte1)) {
1856 /* Are we current address space or kernel? */
1857 if (pmap_is_current(pmap))
1858 return (pt2map_entry(va));
1859 rw_assert(&pvh_global_lock, RA_WLOCKED);
1860 KASSERT(curthread->td_pinned > 0,
1861 ("%s: curthread not pinned", __func__));
1862 /* Note that L2 page table size is not equal to PAGE_SIZE. */
1863 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
1864 if (pte2_pa(pte2_load(PMAP1)) != pt2pg_pa) {
1865 pte2_store(PMAP1, PTE2_KPT(pt2pg_pa));
1867 PMAP1cpu = PCPU_GET(cpuid);
1869 tlb_flush_local((vm_offset_t)PADDR1);
1873 if (PMAP1cpu != PCPU_GET(cpuid)) {
1874 PMAP1cpu = PCPU_GET(cpuid);
1875 tlb_flush_local((vm_offset_t)PADDR1);
1880 return (PADDR1 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
1886 * Routine: pmap_extract
1888 * Extract the physical page address associated
1889 * with the given map/virtual_address pair.
1892 pmap_extract(pmap_t pmap, vm_offset_t va)
1899 pte1 = pte1_load(pmap_pte1(pmap, va));
1900 if (pte1_is_section(pte1))
1901 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1902 else if (pte1_is_link(pte1)) {
1903 pte2p = pmap_pte2(pmap, va);
1904 pa = pte2_pa(pte2_load(pte2p)) | (va & PTE2_OFFSET);
1905 pmap_pte2_release(pte2p);
1913 * Routine: pmap_extract_and_hold
1915 * Atomically extract and hold the physical page
1916 * with the given pmap and virtual address pair
1917 * if that mapping permits the given protection.
1920 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1922 vm_paddr_t pa, lockpa;
1924 pt2_entry_t pte2, *pte2p;
1931 pte1 = pte1_load(pmap_pte1(pmap, va));
1932 if (pte1_is_section(pte1)) {
1933 if (!(pte1 & PTE1_RO) || !(prot & VM_PROT_WRITE)) {
1934 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1935 if (vm_page_pa_tryrelock(pmap, pa, &lockpa))
1937 m = PHYS_TO_VM_PAGE(pa);
1940 } else if (pte1_is_link(pte1)) {
1941 pte2p = pmap_pte2(pmap, va);
1942 pte2 = pte2_load(pte2p);
1943 pmap_pte2_release(pte2p);
1944 if (pte2_is_valid(pte2) &&
1945 (!(pte2 & PTE2_RO) || !(prot & VM_PROT_WRITE))) {
1947 if (vm_page_pa_tryrelock(pmap, pa, &lockpa))
1949 m = PHYS_TO_VM_PAGE(pa);
1953 PA_UNLOCK_COND(lockpa);
1959 * Grow the number of kernel L2 page table entries, if needed.
1962 pmap_growkernel(vm_offset_t addr)
1965 vm_paddr_t pt2pg_pa, pt2_pa;
1969 PDEBUG(1, printf("%s: addr = %#x\n", __func__, addr));
1971 * All the time kernel_vm_end is first KVA for which underlying
1972 * L2 page table is either not allocated or linked from L1 page table
1973 * (not considering sections). Except for two possible cases:
1975 * (1) in the very beginning as long as pmap_growkernel() was
1976 * not called, it could be first unused KVA (which is not
1977 * rounded up to PTE1_SIZE),
1979 * (2) when all KVA space is mapped and kernel_map->max_offset
1980 * address is not rounded up to PTE1_SIZE. (For example,
1981 * it could be 0xFFFFFFFF.)
1983 kernel_vm_end = pte1_roundup(kernel_vm_end);
1984 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1985 addr = roundup2(addr, PTE1_SIZE);
1986 if (addr - 1 >= kernel_map->max_offset)
1987 addr = kernel_map->max_offset;
1988 while (kernel_vm_end < addr) {
1989 pte1 = pte1_load(kern_pte1(kernel_vm_end));
1990 if (pte1_is_valid(pte1)) {
1991 kernel_vm_end += PTE1_SIZE;
1992 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1993 kernel_vm_end = kernel_map->max_offset;
2000 * kernel_vm_end_new is used in pmap_pinit() when kernel
2001 * mappings are entered to new pmap all at once to avoid race
2002 * between pmap_kenter_pte1() and kernel_vm_end increase.
2003 * The same aplies to pmap_kenter_pt2tab().
2005 kernel_vm_end_new = kernel_vm_end + PTE1_SIZE;
2007 pte2 = pt2tab_load(kern_pt2tab_entry(kernel_vm_end));
2008 if (!pte2_is_valid(pte2)) {
2010 * Install new PT2s page into kernel PT2TAB.
2012 m = vm_page_alloc(NULL,
2013 pte1_index(kernel_vm_end) & ~PT2PG_MASK,
2014 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2015 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2017 panic("%s: no memory to grow kernel", __func__);
2019 * QQQ: To link all new L2 page tables from L1 page
2020 * table now and so pmap_kenter_pte1() them
2021 * at once together with pmap_kenter_pt2tab()
2022 * could be nice speed up. However,
2023 * pmap_growkernel() does not happen so often...
2024 * QQQ: The other TTBR is another option.
2026 pt2pg_pa = pmap_pt2pg_init(kernel_pmap, kernel_vm_end,
2029 pt2pg_pa = pte2_pa(pte2);
2031 pt2_pa = page_pt2pa(pt2pg_pa, pte1_index(kernel_vm_end));
2032 pmap_kenter_pte1(kernel_vm_end, PTE1_LINK(pt2_pa));
2034 kernel_vm_end = kernel_vm_end_new;
2035 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2036 kernel_vm_end = kernel_map->max_offset;
2043 kvm_size(SYSCTL_HANDLER_ARGS)
2045 unsigned long ksize = vm_max_kernel_address - KERNBASE;
2047 return (sysctl_handle_long(oidp, &ksize, 0, req));
2049 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2050 0, 0, kvm_size, "IU", "Size of KVM");
2053 kvm_free(SYSCTL_HANDLER_ARGS)
2055 unsigned long kfree = vm_max_kernel_address - kernel_vm_end;
2057 return (sysctl_handle_long(oidp, &kfree, 0, req));
2059 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2060 0, 0, kvm_free, "IU", "Amount of KVM free");
2062 /***********************************************
2064 * Pmap allocation/deallocation routines.
2066 ***********************************************/
2069 * Initialize the pmap for the swapper process.
2072 pmap_pinit0(pmap_t pmap)
2074 PDEBUG(1, printf("%s: pmap = %p\n", __func__, pmap));
2076 PMAP_LOCK_INIT(pmap);
2079 * Kernel page table directory and pmap stuff around is already
2080 * initialized, we are using it right now and here. So, finish
2081 * only PMAP structures initialization for process0 ...
2083 * Since the L1 page table and PT2TAB is shared with the kernel pmap,
2084 * which is already included in the list "allpmaps", this pmap does
2085 * not need to be inserted into that list.
2087 pmap->pm_pt1 = kern_pt1;
2088 pmap->pm_pt2tab = kern_pt2tab;
2089 CPU_ZERO(&pmap->pm_active);
2090 PCPU_SET(curpmap, pmap);
2091 TAILQ_INIT(&pmap->pm_pvchunk);
2092 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2093 CPU_SET(0, &pmap->pm_active);
2096 static __inline void
2097 pte1_copy_nosync(pt1_entry_t *spte1p, pt1_entry_t *dpte1p, vm_offset_t sva,
2102 idx = pte1_index(sva);
2103 count = (pte1_index(eva) - idx + 1) * sizeof(pt1_entry_t);
2104 bcopy(spte1p + idx, dpte1p + idx, count);
2107 static __inline void
2108 pt2tab_copy_nosync(pt2_entry_t *spte2p, pt2_entry_t *dpte2p, vm_offset_t sva,
2113 idx = pt2tab_index(sva);
2114 count = (pt2tab_index(eva) - idx + 1) * sizeof(pt2_entry_t);
2115 bcopy(spte2p + idx, dpte2p + idx, count);
2119 * Initialize a preallocated and zeroed pmap structure,
2120 * such as one in a vmspace structure.
2123 pmap_pinit(pmap_t pmap)
2127 vm_paddr_t pa, pt2tab_pa;
2130 PDEBUG(6, printf("%s: pmap = %p, pm_pt1 = %p\n", __func__, pmap,
2134 * No need to allocate L2 page table space yet but we do need
2135 * a valid L1 page table and PT2TAB table.
2137 * Install shared kernel mappings to these tables. It's a little
2138 * tricky as some parts of KVA are reserved for vectors, devices,
2139 * and whatever else. These parts are supposed to be above
2140 * vm_max_kernel_address. Thus two regions should be installed:
2142 * (1) <KERNBASE, kernel_vm_end),
2143 * (2) <vm_max_kernel_address, 0xFFFFFFFF>.
2145 * QQQ: The second region should be stable enough to be installed
2146 * only once in time when the tables are allocated.
2147 * QQQ: Maybe copy of both regions at once could be faster ...
2148 * QQQ: Maybe the other TTBR is an option.
2150 * Finally, install own PT2TAB table to these tables.
2153 if (pmap->pm_pt1 == NULL) {
2154 pmap->pm_pt1 = (pt1_entry_t *)kmem_alloc_contig(kernel_arena,
2155 NB_IN_PT1, M_NOWAIT | M_ZERO, 0, -1UL, NB_IN_PT1, 0,
2157 if (pmap->pm_pt1 == NULL)
2160 if (pmap->pm_pt2tab == NULL) {
2162 * QQQ: (1) PT2TAB must be contiguous. If PT2TAB is one page
2163 * only, what should be the only size for 32 bit systems,
2164 * then we could allocate it with vm_page_alloc() and all
2165 * the stuff needed as other L2 page table pages.
2166 * (2) Note that a process PT2TAB is special L2 page table
2167 * page. Its mapping in kernel_arena is permanent and can
2168 * be used no matter which process is current. Its mapping
2169 * in PT2MAP can be used only for current process.
2171 pmap->pm_pt2tab = (pt2_entry_t *)kmem_alloc_attr(kernel_arena,
2172 NB_IN_PT2TAB, M_NOWAIT | M_ZERO, 0, -1UL, pt_memattr);
2173 if (pmap->pm_pt2tab == NULL) {
2175 * QQQ: As struct pmap is allocated from UMA with
2176 * UMA_ZONE_NOFREE flag, it's important to leave
2177 * no allocation in pmap if initialization failed.
2179 kmem_free(kernel_arena, (vm_offset_t)pmap->pm_pt1,
2181 pmap->pm_pt1 = NULL;
2185 * QQQ: Each L2 page table page vm_page_t has pindex set to
2186 * pte1 index of virtual address mapped by this page.
2187 * It's not valid for non kernel PT2TABs themselves.
2188 * The pindex of these pages can not be altered because
2189 * of the way how they are allocated now. However, it
2190 * should not be a problem.
2194 mtx_lock_spin(&allpmaps_lock);
2196 * To avoid race with pmap_kenter_pte1() and pmap_kenter_pt2tab(),
2197 * kernel_vm_end_new is used here instead of kernel_vm_end.
2199 pte1_copy_nosync(kern_pt1, pmap->pm_pt1, KERNBASE,
2200 kernel_vm_end_new - 1);
2201 pte1_copy_nosync(kern_pt1, pmap->pm_pt1, vm_max_kernel_address,
2203 pt2tab_copy_nosync(kern_pt2tab, pmap->pm_pt2tab, KERNBASE,
2204 kernel_vm_end_new - 1);
2205 pt2tab_copy_nosync(kern_pt2tab, pmap->pm_pt2tab, vm_max_kernel_address,
2207 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
2208 mtx_unlock_spin(&allpmaps_lock);
2211 * Store PT2MAP PT2 pages (a.k.a. PT2TAB) in PT2TAB itself.
2212 * I.e. self reference mapping. The PT2TAB is private, however mapped
2213 * into shared PT2MAP space, so the mapping should be not global.
2215 pt2tab_pa = vtophys(pmap->pm_pt2tab);
2216 pte2p = pmap_pt2tab_entry(pmap, (vm_offset_t)PT2MAP);
2217 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE) {
2218 pt2tab_store(pte2p++, PTE2_KPT_NG(pa));
2221 /* Insert PT2MAP PT2s into pmap PT1. */
2222 pte1p = pmap_pte1(pmap, (vm_offset_t)PT2MAP);
2223 for (pa = pt2tab_pa, i = 0; i < NPT2_IN_PT2TAB; i++, pa += NB_IN_PT2) {
2224 pte1_store(pte1p++, PTE1_LINK(pa));
2228 * Now synchronize new mapping which was made above.
2230 pte1_sync_range(pmap->pm_pt1, NB_IN_PT1);
2231 pte2_sync_range(pmap->pm_pt2tab, NB_IN_PT2TAB);
2233 CPU_ZERO(&pmap->pm_active);
2234 TAILQ_INIT(&pmap->pm_pvchunk);
2235 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2242 pt2tab_user_is_empty(pt2_entry_t *tab)
2246 end = pt2tab_index(VM_MAXUSER_ADDRESS);
2247 for (i = 0; i < end; i++)
2248 if (tab[i] != 0) return (FALSE);
2253 * Release any resources held by the given physical map.
2254 * Called when a pmap initialized by pmap_pinit is being released.
2255 * Should only be called if the map contains no valid mappings.
2258 pmap_release(pmap_t pmap)
2261 vm_offset_t start, end;
2263 KASSERT(pmap->pm_stats.resident_count == 0,
2264 ("%s: pmap resident count %ld != 0", __func__,
2265 pmap->pm_stats.resident_count));
2266 KASSERT(pt2tab_user_is_empty(pmap->pm_pt2tab),
2267 ("%s: has allocated user PT2(s)", __func__));
2268 KASSERT(CPU_EMPTY(&pmap->pm_active),
2269 ("%s: pmap %p is active on some CPU(s)", __func__, pmap));
2271 mtx_lock_spin(&allpmaps_lock);
2272 LIST_REMOVE(pmap, pm_list);
2273 mtx_unlock_spin(&allpmaps_lock);
2276 start = pte1_index(KERNBASE) * sizeof(pt1_entry_t);
2277 end = (pte1_index(0xFFFFFFFF) + 1) * sizeof(pt1_entry_t);
2278 bzero((char *)pmap->pm_pt1 + start, end - start);
2280 start = pt2tab_index(KERNBASE) * sizeof(pt2_entry_t);
2281 end = (pt2tab_index(0xFFFFFFFF) + 1) * sizeof(pt2_entry_t);
2282 bzero((char *)pmap->pm_pt2tab + start, end - start);
2285 * We are leaving PT1 and PT2TAB allocated on released pmap,
2286 * so hopefully UMA vmspace_zone will always be inited with
2287 * UMA_ZONE_NOFREE flag.
2291 /*********************************************************
2293 * L2 table pages and their pages management routines.
2295 *********************************************************/
2298 * Virtual interface for L2 page table wire counting.
2300 * Each L2 page table in a page has own counter which counts a number of
2301 * valid mappings in a table. Global page counter counts mappings in all
2302 * tables in a page plus a single itself mapping in PT2TAB.
2304 * During a promotion we leave the associated L2 page table counter
2305 * untouched, so the table (strictly speaking a page which holds it)
2306 * is never freed if promoted.
2308 * If a page m->wire_count == 1 then no valid mappings exist in any L2 page
2309 * table in the page and the page itself is only mapped in PT2TAB.
2312 static __inline void
2313 pt2_wirecount_init(vm_page_t m)
2318 * Note: A page m is allocated with VM_ALLOC_WIRED flag and
2319 * m->wire_count should be already set correctly.
2320 * So, there is no need to set it again herein.
2322 for (i = 0; i < NPT2_IN_PG; i++)
2323 m->md.pt2_wirecount[i] = 0;
2326 static __inline void
2327 pt2_wirecount_inc(vm_page_t m, uint32_t pte1_idx)
2331 * Note: A just modificated pte2 (i.e. already allocated)
2332 * is acquiring one extra reference which must be
2333 * explicitly cleared. It influences the KASSERTs herein.
2334 * All L2 page tables in a page always belong to the same
2335 * pmap, so we allow only one extra reference for the page.
2337 KASSERT(m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] < (NPTE2_IN_PT2 + 1),
2338 ("%s: PT2 is overflowing ...", __func__));
2339 KASSERT(m->wire_count <= (NPTE2_IN_PG + 1),
2340 ("%s: PT2PG is overflowing ...", __func__));
2343 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]++;
2346 static __inline void
2347 pt2_wirecount_dec(vm_page_t m, uint32_t pte1_idx)
2350 KASSERT(m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] != 0,
2351 ("%s: PT2 is underflowing ...", __func__));
2352 KASSERT(m->wire_count > 1,
2353 ("%s: PT2PG is underflowing ...", __func__));
2356 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]--;
2359 static __inline void
2360 pt2_wirecount_set(vm_page_t m, uint32_t pte1_idx, uint16_t count)
2363 KASSERT(count <= NPTE2_IN_PT2,
2364 ("%s: invalid count %u", __func__, count));
2365 KASSERT(m->wire_count > m->md.pt2_wirecount[pte1_idx & PT2PG_MASK],
2366 ("%s: PT2PG corrupting (%u, %u) ...", __func__, m->wire_count,
2367 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]));
2369 m->wire_count -= m->md.pt2_wirecount[pte1_idx & PT2PG_MASK];
2370 m->wire_count += count;
2371 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] = count;
2373 KASSERT(m->wire_count <= (NPTE2_IN_PG + 1),
2374 ("%s: PT2PG is overflowed (%u) ...", __func__, m->wire_count));
2377 static __inline uint32_t
2378 pt2_wirecount_get(vm_page_t m, uint32_t pte1_idx)
2381 return (m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]);
2384 static __inline boolean_t
2385 pt2_is_empty(vm_page_t m, vm_offset_t va)
2388 return (m->md.pt2_wirecount[pte1_index(va) & PT2PG_MASK] == 0);
2391 static __inline boolean_t
2392 pt2_is_full(vm_page_t m, vm_offset_t va)
2395 return (m->md.pt2_wirecount[pte1_index(va) & PT2PG_MASK] ==
2399 static __inline boolean_t
2400 pt2pg_is_empty(vm_page_t m)
2403 return (m->wire_count == 1);
2407 * This routine is called if the L2 page table
2408 * is not mapped correctly.
2411 _pmap_allocpte2(pmap_t pmap, vm_offset_t va, u_int flags)
2417 vm_paddr_t pt2pg_pa, pt2_pa;
2419 pte1_idx = pte1_index(va);
2420 pte1p = pmap->pm_pt1 + pte1_idx;
2422 KASSERT(pte1_load(pte1p) == 0,
2423 ("%s: pm_pt1[%#x] is not zero: %#x", __func__, pte1_idx,
2426 pte2 = pt2tab_load(pmap_pt2tab_entry(pmap, va));
2427 if (!pte2_is_valid(pte2)) {
2429 * Install new PT2s page into pmap PT2TAB.
2431 m = vm_page_alloc(NULL, pte1_idx & ~PT2PG_MASK,
2432 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2434 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2436 rw_wunlock(&pvh_global_lock);
2438 rw_wlock(&pvh_global_lock);
2443 * Indicate the need to retry. While waiting,
2444 * the L2 page table page may have been allocated.
2448 pmap->pm_stats.resident_count++;
2449 pt2pg_pa = pmap_pt2pg_init(pmap, va, m);
2451 pt2pg_pa = pte2_pa(pte2);
2452 m = PHYS_TO_VM_PAGE(pt2pg_pa);
2455 pt2_wirecount_inc(m, pte1_idx);
2456 pt2_pa = page_pt2pa(pt2pg_pa, pte1_idx);
2457 pte1_store(pte1p, PTE1_LINK(pt2_pa));
2463 pmap_allocpte2(pmap_t pmap, vm_offset_t va, u_int flags)
2466 pt1_entry_t *pte1p, pte1;
2469 pte1_idx = pte1_index(va);
2471 pte1p = pmap->pm_pt1 + pte1_idx;
2472 pte1 = pte1_load(pte1p);
2475 * This supports switching from a 1MB page to a
2478 if (pte1_is_section(pte1)) {
2479 (void)pmap_demote_pte1(pmap, pte1p, va);
2481 * Reload pte1 after demotion.
2483 * Note: Demotion can even fail as either PT2 is not find for
2484 * the virtual address or PT2PG can not be allocated.
2486 pte1 = pte1_load(pte1p);
2490 * If the L2 page table page is mapped, we just increment the
2491 * hold count, and activate it.
2493 if (pte1_is_link(pte1)) {
2494 m = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
2495 pt2_wirecount_inc(m, pte1_idx);
2498 * Here if the PT2 isn't mapped, or if it has
2501 m = _pmap_allocpte2(pmap, va, flags);
2502 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2509 static __inline void
2510 pmap_free_zero_pages(struct spglist *free)
2514 while ((m = SLIST_FIRST(free)) != NULL) {
2515 SLIST_REMOVE_HEAD(free, plinks.s.ss);
2516 /* Preserve the page's PG_ZERO setting. */
2517 vm_page_free_toq(m);
2522 * Schedule the specified unused L2 page table page to be freed. Specifically,
2523 * add the page to the specified list of pages that will be released to the
2524 * physical memory manager after the TLB has been updated.
2526 static __inline void
2527 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free)
2531 * Put page on a list so that it is released after
2532 * *ALL* TLB shootdown is done
2535 pmap_zero_page_check(m);
2537 m->flags |= PG_ZERO;
2538 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2542 * Unwire L2 page tables page.
2545 pmap_unwire_pt2pg(pmap_t pmap, vm_offset_t va, vm_page_t m)
2547 pt1_entry_t *pte1p, opte1 __unused;
2551 KASSERT(pt2pg_is_empty(m),
2552 ("%s: pmap %p PT2PG %p wired", __func__, pmap, m));
2555 * Unmap all L2 page tables in the page from L1 page table.
2557 * QQQ: Individual L2 page tables (except the last one) can be unmapped
2558 * earlier. However, we are doing that this way.
2560 KASSERT(m->pindex == (pte1_index(va) & ~PT2PG_MASK),
2561 ("%s: pmap %p va %#x PT2PG %p bad index", __func__, pmap, va, m));
2562 pte1p = pmap->pm_pt1 + m->pindex;
2563 for (i = 0; i < NPT2_IN_PG; i++, pte1p++) {
2564 KASSERT(m->md.pt2_wirecount[i] == 0,
2565 ("%s: pmap %p PT2 %u (PG %p) wired", __func__, pmap, i, m));
2566 opte1 = pte1_load(pte1p);
2567 if (pte1_is_link(opte1)) {
2570 * Flush intermediate TLB cache.
2572 pmap_tlb_flush(pmap, (m->pindex + i) << PTE1_SHIFT);
2576 KASSERT((opte1 == 0) || pte1_is_section(opte1),
2577 ("%s: pmap %p va %#x bad pte1 %x at %u", __func__,
2578 pmap, va, opte1, i));
2583 * Unmap the page from PT2TAB.
2585 pte2p = pmap_pt2tab_entry(pmap, va);
2586 (void)pt2tab_load_clear(pte2p);
2587 pmap_tlb_flush(pmap, pt2map_pt2pg(va));
2590 pmap->pm_stats.resident_count--;
2593 * This is a release store so that the ordinary store unmapping
2594 * the L2 page table page is globally performed before TLB shoot-
2597 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1);
2601 * Decrements a L2 page table page's wire count, which is used to record the
2602 * number of valid page table entries within the page. If the wire count
2603 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2604 * page table page was unmapped and FALSE otherwise.
2606 static __inline boolean_t
2607 pmap_unwire_pt2(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2609 pt2_wirecount_dec(m, pte1_index(va));
2610 if (pt2pg_is_empty(m)) {
2612 * QQQ: Wire count is zero, so whole page should be zero and
2613 * we can set PG_ZERO flag to it.
2614 * Note that when promotion is enabled, it takes some
2615 * more efforts. See pmap_unwire_pt2_all() below.
2617 pmap_unwire_pt2pg(pmap, va, m);
2618 pmap_add_delayed_free_list(m, free);
2625 * Drop a L2 page table page's wire count at once, which is used to record
2626 * the number of valid L2 page table entries within the page. If the wire
2627 * count drops to zero, then the L2 page table page is unmapped.
2629 static __inline void
2630 pmap_unwire_pt2_all(pmap_t pmap, vm_offset_t va, vm_page_t m,
2631 struct spglist *free)
2633 u_int pte1_idx = pte1_index(va);
2635 KASSERT(m->pindex == (pte1_idx & ~PT2PG_MASK),
2636 ("%s: PT2 page's pindex is wrong", __func__));
2637 KASSERT(m->wire_count > pt2_wirecount_get(m, pte1_idx),
2638 ("%s: bad pt2 wire count %u > %u", __func__, m->wire_count,
2639 pt2_wirecount_get(m, pte1_idx)));
2642 * It's possible that the L2 page table was never used.
2643 * It happened in case that a section was created without promotion.
2645 if (pt2_is_full(m, va)) {
2646 pt2_wirecount_set(m, pte1_idx, 0);
2649 * QQQ: We clear L2 page table now, so when L2 page table page
2650 * is going to be freed, we can set it PG_ZERO flag ...
2651 * This function is called only on section mappings, so
2652 * hopefully it's not to big overload.
2654 * XXX: If pmap is current, existing PT2MAP mapping could be
2657 pmap_zero_page_area(m, page_pt2off(pte1_idx), NB_IN_PT2);
2661 KASSERT(pt2_is_empty(m, va), ("%s: PT2 is not empty (%u)",
2662 __func__, pt2_wirecount_get(m, pte1_idx)));
2664 if (pt2pg_is_empty(m)) {
2665 pmap_unwire_pt2pg(pmap, va, m);
2666 pmap_add_delayed_free_list(m, free);
2671 * After removing a L2 page table entry, this routine is used to
2672 * conditionally free the page, and manage the hold/wire counts.
2675 pmap_unuse_pt2(pmap_t pmap, vm_offset_t va, struct spglist *free)
2680 if (va >= VM_MAXUSER_ADDRESS)
2682 pte1 = pte1_load(pmap_pte1(pmap, va));
2683 mpte = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
2684 return (pmap_unwire_pt2(pmap, va, mpte, free));
2687 /*************************************
2689 * Page management routines.
2691 *************************************/
2693 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2694 CTASSERT(_NPCM == 11);
2695 CTASSERT(_NPCPV == 336);
2697 static __inline struct pv_chunk *
2698 pv_to_chunk(pv_entry_t pv)
2701 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2704 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2706 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2707 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2709 static const uint32_t pc_freemask[_NPCM] = {
2710 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2711 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2712 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2713 PC_FREE0_9, PC_FREE10
2716 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2717 "Current number of pv entries");
2720 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2722 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2723 "Current number of pv entry chunks");
2724 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2725 "Current number of pv entry chunks allocated");
2726 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2727 "Current number of pv entry chunks frees");
2728 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail,
2729 0, "Number of times tried to get a chunk page but failed.");
2731 static long pv_entry_frees, pv_entry_allocs;
2732 static int pv_entry_spare;
2734 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2735 "Current number of pv entry frees");
2736 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs,
2737 0, "Current number of pv entry allocs");
2738 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2739 "Current number of spare pv entries");
2743 * Is given page managed?
2745 static __inline boolean_t
2746 is_managed(vm_paddr_t pa)
2752 if (pgnum >= first_page) {
2753 m = PHYS_TO_VM_PAGE(pa);
2756 if ((m->oflags & VPO_UNMANAGED) == 0)
2762 static __inline boolean_t
2763 pte1_is_managed(pt1_entry_t pte1)
2766 return (is_managed(pte1_pa(pte1)));
2769 static __inline boolean_t
2770 pte2_is_managed(pt2_entry_t pte2)
2773 return (is_managed(pte2_pa(pte2)));
2777 * We are in a serious low memory condition. Resort to
2778 * drastic measures to free some pages so we can allocate
2779 * another pv entry chunk.
2782 pmap_pv_reclaim(pmap_t locked_pmap)
2785 struct pv_chunk *pc;
2786 struct md_page *pvh;
2789 pt2_entry_t *pte2p, tpte2;
2793 struct spglist free;
2795 int bit, field, freed;
2797 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2801 TAILQ_INIT(&newtail);
2802 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2803 SLIST_EMPTY(&free))) {
2804 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2805 if (pmap != pc->pc_pmap) {
2807 if (pmap != locked_pmap)
2811 /* Avoid deadlock and lock recursion. */
2812 if (pmap > locked_pmap)
2814 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2816 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2822 * Destroy every non-wired, 4 KB page mapping in the chunk.
2825 for (field = 0; field < _NPCM; field++) {
2826 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2827 inuse != 0; inuse &= ~(1UL << bit)) {
2828 bit = ffs(inuse) - 1;
2829 pv = &pc->pc_pventry[field * 32 + bit];
2831 pte1p = pmap_pte1(pmap, va);
2832 if (pte1_is_section(pte1_load(pte1p)))
2834 pte2p = pmap_pte2(pmap, va);
2835 tpte2 = pte2_load(pte2p);
2836 if ((tpte2 & PTE2_W) == 0)
2837 tpte2 = pte2_load_clear(pte2p);
2838 pmap_pte2_release(pte2p);
2839 if ((tpte2 & PTE2_W) != 0)
2842 ("pmap_pv_reclaim: pmap %p va %#x zero pte",
2844 pmap_tlb_flush(pmap, va);
2845 m = PHYS_TO_VM_PAGE(pte2_pa(tpte2));
2846 if (pte2_is_dirty(tpte2))
2848 if ((tpte2 & PTE2_A) != 0)
2849 vm_page_aflag_set(m, PGA_REFERENCED);
2850 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2851 if (TAILQ_EMPTY(&m->md.pv_list) &&
2852 (m->flags & PG_FICTITIOUS) == 0) {
2853 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2854 if (TAILQ_EMPTY(&pvh->pv_list)) {
2855 vm_page_aflag_clear(m,
2859 pc->pc_map[field] |= 1UL << bit;
2860 pmap_unuse_pt2(pmap, va, &free);
2865 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2868 /* Every freed mapping is for a 4 KB page. */
2869 pmap->pm_stats.resident_count -= freed;
2870 PV_STAT(pv_entry_frees += freed);
2871 PV_STAT(pv_entry_spare += freed);
2872 pv_entry_count -= freed;
2873 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2874 for (field = 0; field < _NPCM; field++)
2875 if (pc->pc_map[field] != pc_freemask[field]) {
2876 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2878 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2881 * One freed pv entry in locked_pmap is
2884 if (pmap == locked_pmap)
2888 if (field == _NPCM) {
2889 PV_STAT(pv_entry_spare -= _NPCPV);
2890 PV_STAT(pc_chunk_count--);
2891 PV_STAT(pc_chunk_frees++);
2892 /* Entire chunk is free; return it. */
2893 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2894 pmap_qremove((vm_offset_t)pc, 1);
2895 pmap_pte2list_free(&pv_vafree, (vm_offset_t)pc);
2900 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2902 if (pmap != locked_pmap)
2905 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2906 m_pc = SLIST_FIRST(&free);
2907 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2908 /* Recycle a freed page table page. */
2909 m_pc->wire_count = 1;
2910 atomic_add_int(&vm_cnt.v_wire_count, 1);
2912 pmap_free_zero_pages(&free);
2917 free_pv_chunk(struct pv_chunk *pc)
2921 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2922 PV_STAT(pv_entry_spare -= _NPCPV);
2923 PV_STAT(pc_chunk_count--);
2924 PV_STAT(pc_chunk_frees++);
2925 /* entire chunk is free, return it */
2926 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2927 pmap_qremove((vm_offset_t)pc, 1);
2928 vm_page_unwire(m, PQ_NONE);
2930 pmap_pte2list_free(&pv_vafree, (vm_offset_t)pc);
2934 * Free the pv_entry back to the free list.
2937 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2939 struct pv_chunk *pc;
2940 int idx, field, bit;
2942 rw_assert(&pvh_global_lock, RA_WLOCKED);
2943 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2944 PV_STAT(pv_entry_frees++);
2945 PV_STAT(pv_entry_spare++);
2947 pc = pv_to_chunk(pv);
2948 idx = pv - &pc->pc_pventry[0];
2951 pc->pc_map[field] |= 1ul << bit;
2952 for (idx = 0; idx < _NPCM; idx++)
2953 if (pc->pc_map[idx] != pc_freemask[idx]) {
2955 * 98% of the time, pc is already at the head of the
2956 * list. If it isn't already, move it to the head.
2958 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2960 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2961 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2966 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2971 * Get a new pv_entry, allocating a block from the system
2975 get_pv_entry(pmap_t pmap, boolean_t try)
2977 static const struct timeval printinterval = { 60, 0 };
2978 static struct timeval lastprint;
2981 struct pv_chunk *pc;
2984 rw_assert(&pvh_global_lock, RA_WLOCKED);
2985 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2986 PV_STAT(pv_entry_allocs++);
2988 if (pv_entry_count > pv_entry_high_water)
2989 if (ratecheck(&lastprint, &printinterval))
2990 printf("Approaching the limit on PV entries, consider "
2991 "increasing either the vm.pmap.shpgperproc or the "
2992 "vm.pmap.pv_entry_max tunable.\n");
2994 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2996 for (field = 0; field < _NPCM; field++) {
2997 if (pc->pc_map[field]) {
2998 bit = ffs(pc->pc_map[field]) - 1;
3002 if (field < _NPCM) {
3003 pv = &pc->pc_pventry[field * 32 + bit];
3004 pc->pc_map[field] &= ~(1ul << bit);
3005 /* If this was the last item, move it to tail */
3006 for (field = 0; field < _NPCM; field++)
3007 if (pc->pc_map[field] != 0) {
3008 PV_STAT(pv_entry_spare--);
3009 return (pv); /* not full, return */
3011 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3012 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3013 PV_STAT(pv_entry_spare--);
3018 * Access to the pte2list "pv_vafree" is synchronized by the pvh
3019 * global lock. If "pv_vafree" is currently non-empty, it will
3020 * remain non-empty until pmap_pte2list_alloc() completes.
3022 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3023 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
3026 PV_STAT(pc_chunk_tryfail++);
3029 m = pmap_pv_reclaim(pmap);
3033 PV_STAT(pc_chunk_count++);
3034 PV_STAT(pc_chunk_allocs++);
3035 pc = (struct pv_chunk *)pmap_pte2list_alloc(&pv_vafree);
3036 pmap_qenter((vm_offset_t)pc, &m, 1);
3038 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
3039 for (field = 1; field < _NPCM; field++)
3040 pc->pc_map[field] = pc_freemask[field];
3041 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
3042 pv = &pc->pc_pventry[0];
3043 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3044 PV_STAT(pv_entry_spare += _NPCPV - 1);
3049 * Create a pv entry for page at pa for
3053 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
3057 rw_assert(&pvh_global_lock, RA_WLOCKED);
3058 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3059 pv = get_pv_entry(pmap, FALSE);
3061 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3064 static __inline pv_entry_t
3065 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3069 rw_assert(&pvh_global_lock, RA_WLOCKED);
3070 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3071 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3072 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3080 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3084 pv = pmap_pvh_remove(pvh, pmap, va);
3085 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3086 free_pv_entry(pmap, pv);
3090 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
3092 struct md_page *pvh;
3094 rw_assert(&pvh_global_lock, RA_WLOCKED);
3095 pmap_pvh_free(&m->md, pmap, va);
3096 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
3097 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3098 if (TAILQ_EMPTY(&pvh->pv_list))
3099 vm_page_aflag_clear(m, PGA_WRITEABLE);
3104 pmap_pv_demote_pte1(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3106 struct md_page *pvh;
3108 vm_offset_t va_last;
3111 rw_assert(&pvh_global_lock, RA_WLOCKED);
3112 KASSERT((pa & PTE1_OFFSET) == 0,
3113 ("pmap_pv_demote_pte1: pa is not 1mpage aligned"));
3116 * Transfer the 1mpage's pv entry for this mapping to the first
3119 pvh = pa_to_pvh(pa);
3120 va = pte1_trunc(va);
3121 pv = pmap_pvh_remove(pvh, pmap, va);
3122 KASSERT(pv != NULL, ("pmap_pv_demote_pte1: pv not found"));
3123 m = PHYS_TO_VM_PAGE(pa);
3124 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3125 /* Instantiate the remaining NPTE2_IN_PT2 - 1 pv entries. */
3126 va_last = va + PTE1_SIZE - PAGE_SIZE;
3129 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3130 ("pmap_pv_demote_pte1: page %p is not managed", m));
3132 pmap_insert_entry(pmap, va, m);
3133 } while (va < va_last);
3137 pmap_pv_promote_pte1(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3139 struct md_page *pvh;
3141 vm_offset_t va_last;
3144 rw_assert(&pvh_global_lock, RA_WLOCKED);
3145 KASSERT((pa & PTE1_OFFSET) == 0,
3146 ("pmap_pv_promote_pte1: pa is not 1mpage aligned"));
3149 * Transfer the first page's pv entry for this mapping to the
3150 * 1mpage's pv list. Aside from avoiding the cost of a call
3151 * to get_pv_entry(), a transfer avoids the possibility that
3152 * get_pv_entry() calls pmap_pv_reclaim() and that pmap_pv_reclaim()
3153 * removes one of the mappings that is being promoted.
3155 m = PHYS_TO_VM_PAGE(pa);
3156 va = pte1_trunc(va);
3157 pv = pmap_pvh_remove(&m->md, pmap, va);
3158 KASSERT(pv != NULL, ("pmap_pv_promote_pte1: pv not found"));
3159 pvh = pa_to_pvh(pa);
3160 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3161 /* Free the remaining NPTE2_IN_PT2 - 1 pv entries. */
3162 va_last = va + PTE1_SIZE - PAGE_SIZE;
3166 pmap_pvh_free(&m->md, pmap, va);
3167 } while (va < va_last);
3171 * Conditionally create a pv entry.
3174 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
3178 rw_assert(&pvh_global_lock, RA_WLOCKED);
3179 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3180 if (pv_entry_count < pv_entry_high_water &&
3181 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
3183 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3190 * Create the pv entries for each of the pages within a section.
3193 pmap_pv_insert_pte1(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3195 struct md_page *pvh;
3198 rw_assert(&pvh_global_lock, RA_WLOCKED);
3199 if (pv_entry_count < pv_entry_high_water &&
3200 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
3202 pvh = pa_to_pvh(pa);
3203 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3210 pmap_tlb_flush_pte1(pmap_t pmap, vm_offset_t va, pt1_entry_t npte1)
3213 /* Kill all the small mappings or the big one only. */
3214 if (pte1_is_section(npte1))
3215 pmap_tlb_flush_range(pmap, pte1_trunc(va), PTE1_SIZE);
3217 pmap_tlb_flush(pmap, pte1_trunc(va));
3221 * Update kernel pte1 on all pmaps.
3223 * The following function is called only on one cpu with disabled interrupts.
3224 * In SMP case, smp_rendezvous_cpus() is used to stop other cpus. This way
3225 * nobody can invoke explicit hardware table walk during the update of pte1.
3226 * Unsolicited hardware table walk can still happen, invoked by speculative
3227 * data or instruction prefetch or even by speculative hardware table walk.
3229 * The break-before-make approach should be implemented here. However, it's
3230 * not so easy to do that for kernel mappings as it would be unhappy to unmap
3231 * itself unexpectedly but voluntarily.
3234 pmap_update_pte1_kernel(vm_offset_t va, pt1_entry_t npte1)
3240 * Get current pmap. Interrupts should be disabled here
3241 * so PCPU_GET() is done atomically.
3243 pmap = PCPU_GET(curpmap);
3248 * (1) Change pte1 on current pmap.
3249 * (2) Flush all obsolete TLB entries on current CPU.
3250 * (3) Change pte1 on all pmaps.
3251 * (4) Flush all obsolete TLB entries on all CPUs in SMP case.
3254 pte1p = pmap_pte1(pmap, va);
3255 pte1_store(pte1p, npte1);
3257 /* Kill all the small mappings or the big one only. */
3258 if (pte1_is_section(npte1)) {
3259 pmap_pte1_kern_promotions++;
3260 tlb_flush_range_local(pte1_trunc(va), PTE1_SIZE);
3262 pmap_pte1_kern_demotions++;
3263 tlb_flush_local(pte1_trunc(va));
3267 * In SMP case, this function is called when all cpus are at smp
3268 * rendezvous, so there is no need to use 'allpmaps_lock' lock here.
3269 * In UP case, the function is called with this lock locked.
3271 LIST_FOREACH(pmap, &allpmaps, pm_list) {
3272 pte1p = pmap_pte1(pmap, va);
3273 pte1_store(pte1p, npte1);
3277 /* Kill all the small mappings or the big one only. */
3278 if (pte1_is_section(npte1))
3279 tlb_flush_range(pte1_trunc(va), PTE1_SIZE);
3281 tlb_flush(pte1_trunc(va));
3286 struct pte1_action {
3289 u_int update; /* CPU that updates the PTE1 */
3293 pmap_update_pte1_action(void *arg)
3295 struct pte1_action *act = arg;
3297 if (act->update == PCPU_GET(cpuid))
3298 pmap_update_pte1_kernel(act->va, act->npte1);
3302 * Change pte1 on current pmap.
3303 * Note that kernel pte1 must be changed on all pmaps.
3305 * According to the architecture reference manual published by ARM,
3306 * the behaviour is UNPREDICTABLE when two or more TLB entries map the same VA.
3307 * According to this manual, UNPREDICTABLE behaviours must never happen in
3308 * a viable system. In contrast, on x86 processors, it is not specified which
3309 * TLB entry mapping the virtual address will be used, but the MMU doesn't
3310 * generate a bogus translation the way it does on Cortex-A8 rev 2 (Beaglebone
3313 * It's a problem when either promotion or demotion is being done. The pte1
3314 * update and appropriate TLB flush must be done atomically in general.
3317 pmap_change_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va,
3321 if (pmap == kernel_pmap) {
3322 struct pte1_action act;
3327 act.update = PCPU_GET(cpuid);
3328 smp_rendezvous_cpus(all_cpus, smp_no_rendevous_barrier,
3329 pmap_update_pte1_action, NULL, &act);
3335 * Use break-before-make approach for changing userland
3336 * mappings. It can cause L1 translation aborts on other
3337 * cores in SMP case. So, special treatment is implemented
3338 * in pmap_fault(). To reduce the likelihood that another core
3339 * will be affected by the broken mapping, disable interrupts
3340 * until the mapping change is completed.
3342 cspr = disable_interrupts(PSR_I | PSR_F);
3344 pmap_tlb_flush_pte1(pmap, va, npte1);
3345 pte1_store(pte1p, npte1);
3346 restore_interrupts(cspr);
3351 pmap_change_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va,
3355 if (pmap == kernel_pmap) {
3356 mtx_lock_spin(&allpmaps_lock);
3357 pmap_update_pte1_kernel(va, npte1);
3358 mtx_unlock_spin(&allpmaps_lock);
3363 * Use break-before-make approach for changing userland
3364 * mappings. It's absolutely safe in UP case when interrupts
3367 cspr = disable_interrupts(PSR_I | PSR_F);
3369 pmap_tlb_flush_pte1(pmap, va, npte1);
3370 pte1_store(pte1p, npte1);
3371 restore_interrupts(cspr);
3377 * Tries to promote the NPTE2_IN_PT2, contiguous 4KB page mappings that are
3378 * within a single page table page (PT2) to a single 1MB page mapping.
3379 * For promotion to occur, two conditions must be met: (1) the 4KB page
3380 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3381 * mappings must have identical characteristics.
3383 * Managed (PG_MANAGED) mappings within the kernel address space are not
3384 * promoted. The reason is that kernel PTE1s are replicated in each pmap but
3385 * pmap_remove_write(), pmap_clear_modify(), and pmap_clear_reference() only
3386 * read the PTE1 from the kernel pmap.
3389 pmap_promote_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3392 pt2_entry_t *fpte2p, fpte2, fpte2_fav;
3393 pt2_entry_t *pte2p, pte2;
3394 vm_offset_t pteva __unused;
3395 vm_page_t m __unused;
3397 PDEBUG(6, printf("%s(%p): try for va %#x pte1 %#x at %p\n", __func__,
3398 pmap, va, pte1_load(pte1p), pte1p));
3400 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3403 * Examine the first PTE2 in the specified PT2. Abort if this PTE2 is
3404 * either invalid, unused, or does not map the first 4KB physical page
3405 * within a 1MB page.
3407 fpte2p = pmap_pte2_quick(pmap, pte1_trunc(va));
3408 fpte2 = pte2_load(fpte2p);
3409 if ((fpte2 & ((PTE2_FRAME & PTE1_OFFSET) | PTE2_A | PTE2_V)) !=
3410 (PTE2_A | PTE2_V)) {
3411 pmap_pte1_p_failures++;
3412 CTR3(KTR_PMAP, "%s: failure(1) for va %#x in pmap %p",
3413 __func__, va, pmap);
3416 if (pte2_is_managed(fpte2) && pmap == kernel_pmap) {
3417 pmap_pte1_p_failures++;
3418 CTR3(KTR_PMAP, "%s: failure(2) for va %#x in pmap %p",
3419 __func__, va, pmap);
3422 if ((fpte2 & (PTE2_NM | PTE2_RO)) == PTE2_NM) {
3424 * When page is not modified, PTE2_RO can be set without
3425 * a TLB invalidation.
3428 pte2_store(fpte2p, fpte2);
3432 * Examine each of the other PTE2s in the specified PT2. Abort if this
3433 * PTE2 maps an unexpected 4KB physical page or does not have identical
3434 * characteristics to the first PTE2.
3436 fpte2_fav = (fpte2 & (PTE2_FRAME | PTE2_A | PTE2_V));
3437 fpte2_fav += PTE1_SIZE - PTE2_SIZE; /* examine from the end */
3438 for (pte2p = fpte2p + NPTE2_IN_PT2 - 1; pte2p > fpte2p; pte2p--) {
3439 pte2 = pte2_load(pte2p);
3440 if ((pte2 & (PTE2_FRAME | PTE2_A | PTE2_V)) != fpte2_fav) {
3441 pmap_pte1_p_failures++;
3442 CTR3(KTR_PMAP, "%s: failure(3) for va %#x in pmap %p",
3443 __func__, va, pmap);
3446 if ((pte2 & (PTE2_NM | PTE2_RO)) == PTE2_NM) {
3448 * When page is not modified, PTE2_RO can be set
3449 * without a TLB invalidation. See note above.
3452 pte2_store(pte2p, pte2);
3453 pteva = pte1_trunc(va) | (pte2 & PTE1_OFFSET &
3455 CTR3(KTR_PMAP, "%s: protect for va %#x in pmap %p",
3456 __func__, pteva, pmap);
3458 if ((pte2 & PTE2_PROMOTE) != (fpte2 & PTE2_PROMOTE)) {
3459 pmap_pte1_p_failures++;
3460 CTR3(KTR_PMAP, "%s: failure(4) for va %#x in pmap %p",
3461 __func__, va, pmap);
3465 fpte2_fav -= PTE2_SIZE;
3468 * The page table page in its current state will stay in PT2TAB
3469 * until the PTE1 mapping the section is demoted by pmap_demote_pte1()
3470 * or destroyed by pmap_remove_pte1().
3472 * Note that L2 page table size is not equal to PAGE_SIZE.
3474 m = PHYS_TO_VM_PAGE(trunc_page(pte1_link_pa(pte1_load(pte1p))));
3475 KASSERT(m >= vm_page_array && m < &vm_page_array[vm_page_array_size],
3476 ("%s: PT2 page is out of range", __func__));
3477 KASSERT(m->pindex == (pte1_index(va) & ~PT2PG_MASK),
3478 ("%s: PT2 page's pindex is wrong", __func__));
3481 * Get pte1 from pte2 format.
3483 npte1 = (fpte2 & PTE1_FRAME) | ATTR_TO_L1(fpte2) | PTE1_V;
3486 * Promote the pv entries.
3488 if (pte2_is_managed(fpte2))
3489 pmap_pv_promote_pte1(pmap, va, pte1_pa(npte1));
3492 * Promote the mappings.
3494 pmap_change_pte1(pmap, pte1p, va, npte1);
3496 pmap_pte1_promotions++;
3497 CTR3(KTR_PMAP, "%s: success for va %#x in pmap %p",
3498 __func__, va, pmap);
3500 PDEBUG(6, printf("%s(%p): success for va %#x pte1 %#x(%#x) at %p\n",
3501 __func__, pmap, va, npte1, pte1_load(pte1p), pte1p));
3505 * Zero L2 page table page.
3507 static __inline void
3508 pmap_clear_pt2(pt2_entry_t *fpte2p)
3512 for (pte2p = fpte2p; pte2p < fpte2p + NPTE2_IN_PT2; pte2p++)
3518 * Removes a 1MB page mapping from the kernel pmap.
3521 pmap_remove_kernel_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3525 pt2_entry_t *fpte2p;
3528 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3529 m = pmap_pt2_page(pmap, va);
3532 * QQQ: Is this function called only on promoted pte1?
3533 * We certainly do section mappings directly
3534 * (without promotion) in kernel !!!
3536 panic("%s: missing pt2 page", __func__);
3538 pte1_idx = pte1_index(va);
3541 * Initialize the L2 page table.
3543 fpte2p = page_pt2(pt2map_pt2pg(va), pte1_idx);
3544 pmap_clear_pt2(fpte2p);
3547 * Remove the mapping.
3549 pt2_pa = page_pt2pa(VM_PAGE_TO_PHYS(m), pte1_idx);
3550 pmap_kenter_pte1(va, PTE1_LINK(pt2_pa));
3553 * QQQ: We do not need to invalidate PT2MAP mapping
3554 * as we did not change it. I.e. the L2 page table page
3555 * was and still is mapped the same way.
3560 * Do the things to unmap a section in a process
3563 pmap_remove_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t sva,
3564 struct spglist *free)
3567 struct md_page *pvh;
3568 vm_offset_t eva, va;
3571 PDEBUG(6, printf("%s(%p): va %#x pte1 %#x at %p\n", __func__, pmap, sva,
3572 pte1_load(pte1p), pte1p));
3574 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3575 KASSERT((sva & PTE1_OFFSET) == 0,
3576 ("%s: sva is not 1mpage aligned", __func__));
3579 * Clear and invalidate the mapping. It should occupy one and only TLB
3580 * entry. So, pmap_tlb_flush() called with aligned address should be
3583 opte1 = pte1_load_clear(pte1p);
3584 pmap_tlb_flush(pmap, sva);
3586 if (pte1_is_wired(opte1))
3587 pmap->pm_stats.wired_count -= PTE1_SIZE / PAGE_SIZE;
3588 pmap->pm_stats.resident_count -= PTE1_SIZE / PAGE_SIZE;
3589 if (pte1_is_managed(opte1)) {
3590 pvh = pa_to_pvh(pte1_pa(opte1));
3591 pmap_pvh_free(pvh, pmap, sva);
3592 eva = sva + PTE1_SIZE;
3593 for (va = sva, m = PHYS_TO_VM_PAGE(pte1_pa(opte1));
3594 va < eva; va += PAGE_SIZE, m++) {
3595 if (pte1_is_dirty(opte1))
3598 vm_page_aflag_set(m, PGA_REFERENCED);
3599 if (TAILQ_EMPTY(&m->md.pv_list) &&
3600 TAILQ_EMPTY(&pvh->pv_list))
3601 vm_page_aflag_clear(m, PGA_WRITEABLE);
3604 if (pmap == kernel_pmap) {
3606 * L2 page table(s) can't be removed from kernel map as
3607 * kernel counts on it (stuff around pmap_growkernel()).
3609 pmap_remove_kernel_pte1(pmap, pte1p, sva);
3612 * Get associated L2 page table page.
3613 * It's possible that the page was never allocated.
3615 m = pmap_pt2_page(pmap, sva);
3617 pmap_unwire_pt2_all(pmap, sva, m, free);
3622 * Fills L2 page table page with mappings to consecutive physical pages.
3624 static __inline void
3625 pmap_fill_pt2(pt2_entry_t *fpte2p, pt2_entry_t npte2)
3629 for (pte2p = fpte2p; pte2p < fpte2p + NPTE2_IN_PT2; pte2p++) {
3630 pte2_store(pte2p, npte2);
3636 * Tries to demote a 1MB page mapping. If demotion fails, the
3637 * 1MB page mapping is invalidated.
3640 pmap_demote_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3642 pt1_entry_t opte1, npte1;
3643 pt2_entry_t *fpte2p, npte2;
3644 vm_paddr_t pt2pg_pa, pt2_pa;
3646 struct spglist free;
3647 uint32_t pte1_idx, isnew = 0;
3649 PDEBUG(6, printf("%s(%p): try for va %#x pte1 %#x at %p\n", __func__,
3650 pmap, va, pte1_load(pte1p), pte1p));
3652 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3654 opte1 = pte1_load(pte1p);
3655 KASSERT(pte1_is_section(opte1), ("%s: opte1 not a section", __func__));
3657 if ((opte1 & PTE1_A) == 0 || (m = pmap_pt2_page(pmap, va)) == NULL) {
3658 KASSERT(!pte1_is_wired(opte1),
3659 ("%s: PT2 page for a wired mapping is missing", __func__));
3662 * Invalidate the 1MB page mapping and return
3663 * "failure" if the mapping was never accessed or the
3664 * allocation of the new page table page fails.
3666 if ((opte1 & PTE1_A) == 0 || (m = vm_page_alloc(NULL,
3667 pte1_index(va) & ~PT2PG_MASK, VM_ALLOC_NOOBJ |
3668 VM_ALLOC_NORMAL | VM_ALLOC_WIRED)) == NULL) {
3670 pmap_remove_pte1(pmap, pte1p, pte1_trunc(va), &free);
3671 pmap_free_zero_pages(&free);
3672 CTR3(KTR_PMAP, "%s: failure for va %#x in pmap %p",
3673 __func__, va, pmap);
3676 if (va < VM_MAXUSER_ADDRESS)
3677 pmap->pm_stats.resident_count++;
3682 * We init all L2 page tables in the page even if
3683 * we are going to change everything for one L2 page
3686 pt2pg_pa = pmap_pt2pg_init(pmap, va, m);
3688 if (va < VM_MAXUSER_ADDRESS) {
3689 if (pt2_is_empty(m, va))
3690 isnew = 1; /* Demoting section w/o promotion. */
3693 KASSERT(pt2_is_full(m, va), ("%s: bad PT2 wire"
3694 " count %u", __func__,
3695 pt2_wirecount_get(m, pte1_index(va))));
3700 pt2pg_pa = VM_PAGE_TO_PHYS(m);
3701 pte1_idx = pte1_index(va);
3703 * If the pmap is current, then the PT2MAP can provide access to
3704 * the page table page (promoted L2 page tables are not unmapped).
3705 * Otherwise, temporarily map the L2 page table page (m) into
3706 * the kernel's address space at either PADDR1 or PADDR2.
3708 * Note that L2 page table size is not equal to PAGE_SIZE.
3710 if (pmap_is_current(pmap))
3711 fpte2p = page_pt2(pt2map_pt2pg(va), pte1_idx);
3712 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
3713 if (pte2_pa(pte2_load(PMAP1)) != pt2pg_pa) {
3714 pte2_store(PMAP1, PTE2_KPT(pt2pg_pa));
3716 PMAP1cpu = PCPU_GET(cpuid);
3718 tlb_flush_local((vm_offset_t)PADDR1);
3722 if (PMAP1cpu != PCPU_GET(cpuid)) {
3723 PMAP1cpu = PCPU_GET(cpuid);
3724 tlb_flush_local((vm_offset_t)PADDR1);
3729 fpte2p = page_pt2((vm_offset_t)PADDR1, pte1_idx);
3731 mtx_lock(&PMAP2mutex);
3732 if (pte2_pa(pte2_load(PMAP2)) != pt2pg_pa) {
3733 pte2_store(PMAP2, PTE2_KPT(pt2pg_pa));
3734 tlb_flush((vm_offset_t)PADDR2);
3736 fpte2p = page_pt2((vm_offset_t)PADDR2, pte1_idx);
3738 pt2_pa = page_pt2pa(pt2pg_pa, pte1_idx);
3739 npte1 = PTE1_LINK(pt2_pa);
3741 KASSERT((opte1 & PTE1_A) != 0,
3742 ("%s: opte1 is missing PTE1_A", __func__));
3743 KASSERT((opte1 & (PTE1_NM | PTE1_RO)) != PTE1_NM,
3744 ("%s: opte1 has PTE1_NM", __func__));
3747 * Get pte2 from pte1 format.
3749 npte2 = pte1_pa(opte1) | ATTR_TO_L2(opte1) | PTE2_V;
3752 * If the L2 page table page is new, initialize it. If the mapping
3753 * has changed attributes, update the page table entries.
3756 pt2_wirecount_set(m, pte1_idx, NPTE2_IN_PT2);
3757 pmap_fill_pt2(fpte2p, npte2);
3758 } else if ((pte2_load(fpte2p) & PTE2_PROMOTE) !=
3759 (npte2 & PTE2_PROMOTE))
3760 pmap_fill_pt2(fpte2p, npte2);
3762 KASSERT(pte2_pa(pte2_load(fpte2p)) == pte2_pa(npte2),
3763 ("%s: fpte2p and npte2 map different physical addresses",
3766 if (fpte2p == PADDR2)
3767 mtx_unlock(&PMAP2mutex);
3770 * Demote the mapping. This pmap is locked. The old PTE1 has
3771 * PTE1_A set. If the old PTE1 has not PTE1_RO set, it also
3772 * has not PTE1_NM set. Thus, there is no danger of a race with
3773 * another processor changing the setting of PTE1_A and/or PTE1_NM
3774 * between the read above and the store below.
3776 pmap_change_pte1(pmap, pte1p, va, npte1);
3779 * Demote the pv entry. This depends on the earlier demotion
3780 * of the mapping. Specifically, the (re)creation of a per-
3781 * page pv entry might trigger the execution of pmap_pv_reclaim(),
3782 * which might reclaim a newly (re)created per-page pv entry
3783 * and destroy the associated mapping. In order to destroy
3784 * the mapping, the PTE1 must have already changed from mapping
3785 * the 1mpage to referencing the page table page.
3787 if (pte1_is_managed(opte1))
3788 pmap_pv_demote_pte1(pmap, va, pte1_pa(opte1));
3790 pmap_pte1_demotions++;
3791 CTR3(KTR_PMAP, "%s: success for va %#x in pmap %p",
3792 __func__, va, pmap);
3794 PDEBUG(6, printf("%s(%p): success for va %#x pte1 %#x(%#x) at %p\n",
3795 __func__, pmap, va, npte1, pte1_load(pte1p), pte1p));
3800 * Insert the given physical page (p) at
3801 * the specified virtual address (v) in the
3802 * target physical map with the protection requested.
3804 * If specified, the page will be wired down, meaning
3805 * that the related pte can not be reclaimed.
3807 * NB: This is the only routine which MAY NOT lazy-evaluate
3808 * or lose information. That is, this routine must actually
3809 * insert this page into the given map NOW.
3812 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3813 u_int flags, int8_t psind)
3817 pt2_entry_t npte2, opte2;
3820 vm_page_t mpte2, om;
3823 va = trunc_page(va);
3825 wired = (flags & PMAP_ENTER_WIRED) != 0;
3827 KASSERT(va <= vm_max_kernel_address, ("%s: toobig", __func__));
3828 KASSERT(va < UPT2V_MIN_ADDRESS || va >= UPT2V_MAX_ADDRESS,
3829 ("%s: invalid to pmap_enter page table pages (va: 0x%x)", __func__,
3831 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3832 VM_OBJECT_ASSERT_LOCKED(m->object);
3834 rw_wlock(&pvh_global_lock);
3839 * In the case that a page table page is not
3840 * resident, we are creating it here.
3842 if (va < VM_MAXUSER_ADDRESS) {
3843 mpte2 = pmap_allocpte2(pmap, va, flags);
3844 if (mpte2 == NULL) {
3845 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3846 ("pmap_allocpte2 failed with sleep allowed"));
3848 rw_wunlock(&pvh_global_lock);
3850 return (KERN_RESOURCE_SHORTAGE);
3853 pte1p = pmap_pte1(pmap, va);
3854 if (pte1_is_section(pte1_load(pte1p)))
3855 panic("%s: attempted on 1MB page", __func__);
3856 pte2p = pmap_pte2_quick(pmap, va);
3858 panic("%s: invalid L1 page table entry va=%#x", __func__, va);
3861 pa = VM_PAGE_TO_PHYS(m);
3862 opte2 = pte2_load(pte2p);
3863 opa = pte2_pa(opte2);
3865 * Mapping has not changed, must be protection or wiring change.
3867 if (pte2_is_valid(opte2) && (opa == pa)) {
3869 * Wiring change, just update stats. We don't worry about
3870 * wiring PT2 pages as they remain resident as long as there
3871 * are valid mappings in them. Hence, if a user page is wired,
3872 * the PT2 page will be also.
3874 if (wired && !pte2_is_wired(opte2))
3875 pmap->pm_stats.wired_count++;
3876 else if (!wired && pte2_is_wired(opte2))
3877 pmap->pm_stats.wired_count--;
3880 * Remove extra pte2 reference
3883 pt2_wirecount_dec(mpte2, pte1_index(va));
3884 if (pte2_is_managed(opte2))
3890 * QQQ: We think that changing physical address on writeable mapping
3891 * is not safe. Well, maybe on kernel address space with correct
3892 * locking, it can make a sense. However, we have no idea why
3893 * anyone should do that on user address space. Are we wrong?
3895 KASSERT((opa == 0) || (opa == pa) ||
3896 !pte2_is_valid(opte2) || ((opte2 & PTE2_RO) != 0),
3897 ("%s: pmap %p va %#x(%#x) opa %#x pa %#x - gotcha %#x %#x!",
3898 __func__, pmap, va, opte2, opa, pa, flags, prot));
3903 * Mapping has changed, invalidate old range and fall through to
3904 * handle validating new mapping.
3907 if (pte2_is_wired(opte2))
3908 pmap->pm_stats.wired_count--;
3909 if (pte2_is_managed(opte2)) {
3910 om = PHYS_TO_VM_PAGE(opa);
3911 pv = pmap_pvh_remove(&om->md, pmap, va);
3914 * Remove extra pte2 reference
3917 pt2_wirecount_dec(mpte2, va >> PTE1_SHIFT);
3919 pmap->pm_stats.resident_count++;
3922 * Enter on the PV list if part of our managed memory.
3924 if ((m->oflags & VPO_UNMANAGED) == 0) {
3925 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3926 ("%s: managed mapping within the clean submap", __func__));
3928 pv = get_pv_entry(pmap, FALSE);
3930 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3931 } else if (pv != NULL)
3932 free_pv_entry(pmap, pv);
3935 * Increment counters
3938 pmap->pm_stats.wired_count++;
3942 * Now validate mapping with desired protection/wiring.
3944 npte2 = PTE2(pa, PTE2_NM, vm_page_pte2_attr(m));
3945 if (prot & VM_PROT_WRITE) {
3946 if (pte2_is_managed(npte2))
3947 vm_page_aflag_set(m, PGA_WRITEABLE);
3951 if ((prot & VM_PROT_EXECUTE) == 0)
3955 if (va < VM_MAXUSER_ADDRESS)
3957 if (pmap != kernel_pmap)
3961 * If the mapping or permission bits are different, we need
3962 * to update the pte2.
3964 * QQQ: Think again and again what to do
3965 * if the mapping is going to be changed!
3967 if ((opte2 & ~(PTE2_NM | PTE2_A)) != (npte2 & ~(PTE2_NM | PTE2_A))) {
3969 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
3970 * is set. Do it now, before the mapping is stored and made
3971 * valid for hardware table walk. If done later, there is a race
3972 * for other threads of current process in lazy loading case.
3973 * Don't do it for kernel memory which is mapped with exec
3974 * permission even if the memory isn't going to hold executable
3975 * code. The only time when icache sync is needed is after
3976 * kernel module is loaded and the relocation info is processed.
3977 * And it's done in elf_cpu_load_file().
3979 * QQQ: (1) Does it exist any better way where
3980 * or how to sync icache?
3981 * (2) Now, we do it on a page basis.
3983 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3984 m->md.pat_mode == VM_MEMATTR_WB_WA &&
3985 (opa != pa || (opte2 & PTE2_NX)))
3986 cache_icache_sync_fresh(va, pa, PAGE_SIZE);
3989 if (flags & VM_PROT_WRITE)
3991 if (opte2 & PTE2_V) {
3992 /* Change mapping with break-before-make approach. */
3993 opte2 = pte2_load_clear(pte2p);
3994 pmap_tlb_flush(pmap, va);
3995 pte2_store(pte2p, npte2);
3996 if (opte2 & PTE2_A) {
3997 if (pte2_is_managed(opte2))
3998 vm_page_aflag_set(om, PGA_REFERENCED);
4000 if (pte2_is_dirty(opte2)) {
4001 if (pte2_is_managed(opte2))
4004 if (pte2_is_managed(opte2) &&
4005 TAILQ_EMPTY(&om->md.pv_list) &&
4006 ((om->flags & PG_FICTITIOUS) != 0 ||
4007 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
4008 vm_page_aflag_clear(om, PGA_WRITEABLE);
4010 pte2_store(pte2p, npte2);
4015 * QQQ: In time when both access and not mofified bits are
4016 * emulated by software, this should not happen. Some
4017 * analysis is need, if this really happen. Missing
4018 * tlb flush somewhere could be the reason.
4020 panic("%s: pmap %p va %#x opte2 %x npte2 %x !!", __func__, pmap,
4025 * If both the L2 page table page and the reservation are fully
4026 * populated, then attempt promotion.
4028 if ((mpte2 == NULL || pt2_is_full(mpte2, va)) &&
4029 sp_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
4030 vm_reserv_level_iffullpop(m) == 0)
4031 pmap_promote_pte1(pmap, pte1p, va);
4033 rw_wunlock(&pvh_global_lock);
4035 return (KERN_SUCCESS);
4039 * Do the things to unmap a page in a process.
4042 pmap_remove_pte2(pmap_t pmap, pt2_entry_t *pte2p, vm_offset_t va,
4043 struct spglist *free)
4048 rw_assert(&pvh_global_lock, RA_WLOCKED);
4049 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4051 /* Clear and invalidate the mapping. */
4052 opte2 = pte2_load_clear(pte2p);
4053 pmap_tlb_flush(pmap, va);
4055 KASSERT(pte2_is_valid(opte2), ("%s: pmap %p va %#x not link pte2 %#x",
4056 __func__, pmap, va, opte2));
4059 pmap->pm_stats.wired_count -= 1;
4060 pmap->pm_stats.resident_count -= 1;
4061 if (pte2_is_managed(opte2)) {
4062 m = PHYS_TO_VM_PAGE(pte2_pa(opte2));
4063 if (pte2_is_dirty(opte2))
4066 vm_page_aflag_set(m, PGA_REFERENCED);
4067 pmap_remove_entry(pmap, m, va);
4069 return (pmap_unuse_pt2(pmap, va, free));
4073 * Remove a single page from a process address space.
4076 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
4080 rw_assert(&pvh_global_lock, RA_WLOCKED);
4081 KASSERT(curthread->td_pinned > 0,
4082 ("%s: curthread not pinned", __func__));
4083 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4084 if ((pte2p = pmap_pte2_quick(pmap, va)) == NULL ||
4085 !pte2_is_valid(pte2_load(pte2p)))
4087 pmap_remove_pte2(pmap, pte2p, va, free);
4091 * Remove the given range of addresses from the specified map.
4093 * It is assumed that the start and end are properly
4094 * rounded to the page size.
4097 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4100 pt1_entry_t *pte1p, pte1;
4101 pt2_entry_t *pte2p, pte2;
4102 struct spglist free;
4105 * Perform an unsynchronized read. This is, however, safe.
4107 if (pmap->pm_stats.resident_count == 0)
4112 rw_wlock(&pvh_global_lock);
4117 * Special handling of removing one page. A very common
4118 * operation and easy to short circuit some code.
4120 if (sva + PAGE_SIZE == eva) {
4121 pte1 = pte1_load(pmap_pte1(pmap, sva));
4122 if (pte1_is_link(pte1)) {
4123 pmap_remove_page(pmap, sva, &free);
4128 for (; sva < eva; sva = nextva) {
4130 * Calculate address for next L2 page table.
4132 nextva = pte1_trunc(sva + PTE1_SIZE);
4135 if (pmap->pm_stats.resident_count == 0)
4138 pte1p = pmap_pte1(pmap, sva);
4139 pte1 = pte1_load(pte1p);
4142 * Weed out invalid mappings. Note: we assume that the L1 page
4143 * table is always allocated, and in kernel virtual.
4148 if (pte1_is_section(pte1)) {
4150 * Are we removing the entire large page? If not,
4151 * demote the mapping and fall through.
4153 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
4154 pmap_remove_pte1(pmap, pte1p, sva, &free);
4156 } else if (!pmap_demote_pte1(pmap, pte1p, sva)) {
4157 /* The large page mapping was destroyed. */
4162 /* Update pte1 after demotion. */
4163 pte1 = pte1_load(pte1p);
4168 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
4169 " is not link", __func__, pmap, sva, pte1, pte1p));
4172 * Limit our scan to either the end of the va represented
4173 * by the current L2 page table page, or to the end of the
4174 * range being removed.
4179 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva;
4180 pte2p++, sva += PAGE_SIZE) {
4181 pte2 = pte2_load(pte2p);
4182 if (!pte2_is_valid(pte2))
4184 if (pmap_remove_pte2(pmap, pte2p, sva, &free))
4190 rw_wunlock(&pvh_global_lock);
4192 pmap_free_zero_pages(&free);
4196 * Routine: pmap_remove_all
4198 * Removes this physical page from
4199 * all physical maps in which it resides.
4200 * Reflects back modify bits to the pager.
4203 * Original versions of this routine were very
4204 * inefficient because they iteratively called
4205 * pmap_remove (slow...)
4209 pmap_remove_all(vm_page_t m)
4211 struct md_page *pvh;
4214 pt2_entry_t *pte2p, opte2;
4217 struct spglist free;
4219 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4220 ("%s: page %p is not managed", __func__, m));
4222 rw_wlock(&pvh_global_lock);
4224 if ((m->flags & PG_FICTITIOUS) != 0)
4225 goto small_mappings;
4226 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4227 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
4231 pte1p = pmap_pte1(pmap, va);
4232 (void)pmap_demote_pte1(pmap, pte1p, va);
4236 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4239 pmap->pm_stats.resident_count--;
4240 pte1p = pmap_pte1(pmap, pv->pv_va);
4241 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found "
4242 "a 1mpage in page %p's pv list", __func__, m));
4243 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
4244 opte2 = pte2_load_clear(pte2p);
4245 pmap_tlb_flush(pmap, pv->pv_va);
4246 KASSERT(pte2_is_valid(opte2), ("%s: pmap %p va %x zero pte2",
4247 __func__, pmap, pv->pv_va));
4248 if (pte2_is_wired(opte2))
4249 pmap->pm_stats.wired_count--;
4251 vm_page_aflag_set(m, PGA_REFERENCED);
4254 * Update the vm_page_t clean and reference bits.
4256 if (pte2_is_dirty(opte2))
4258 pmap_unuse_pt2(pmap, pv->pv_va, &free);
4259 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4260 free_pv_entry(pmap, pv);
4263 vm_page_aflag_clear(m, PGA_WRITEABLE);
4265 rw_wunlock(&pvh_global_lock);
4266 pmap_free_zero_pages(&free);
4270 * Just subroutine for pmap_remove_pages() to reasonably satisfy
4271 * good coding style, a.k.a. 80 character line width limit hell.
4273 static __inline void
4274 pmap_remove_pte1_quick(pmap_t pmap, pt1_entry_t pte1, pv_entry_t pv,
4275 struct spglist *free)
4278 vm_page_t m, mt, mpt2pg;
4279 struct md_page *pvh;
4282 m = PHYS_TO_VM_PAGE(pa);
4284 KASSERT(m->phys_addr == pa, ("%s: vm_page_t %p addr mismatch %#x %#x",
4285 __func__, m, m->phys_addr, pa));
4286 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4287 m < &vm_page_array[vm_page_array_size],
4288 ("%s: bad pte1 %#x", __func__, pte1));
4290 if (pte1_is_dirty(pte1)) {
4291 for (mt = m; mt < &m[PTE1_SIZE / PAGE_SIZE]; mt++)
4295 pmap->pm_stats.resident_count -= PTE1_SIZE / PAGE_SIZE;
4296 pvh = pa_to_pvh(pa);
4297 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4298 if (TAILQ_EMPTY(&pvh->pv_list)) {
4299 for (mt = m; mt < &m[PTE1_SIZE / PAGE_SIZE]; mt++)
4300 if (TAILQ_EMPTY(&mt->md.pv_list))
4301 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4303 mpt2pg = pmap_pt2_page(pmap, pv->pv_va);
4305 pmap_unwire_pt2_all(pmap, pv->pv_va, mpt2pg, free);
4309 * Just subroutine for pmap_remove_pages() to reasonably satisfy
4310 * good coding style, a.k.a. 80 character line width limit hell.
4312 static __inline void
4313 pmap_remove_pte2_quick(pmap_t pmap, pt2_entry_t pte2, pv_entry_t pv,
4314 struct spglist *free)
4318 struct md_page *pvh;
4321 m = PHYS_TO_VM_PAGE(pa);
4323 KASSERT(m->phys_addr == pa, ("%s: vm_page_t %p addr mismatch %#x %#x",
4324 __func__, m, m->phys_addr, pa));
4325 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4326 m < &vm_page_array[vm_page_array_size],
4327 ("%s: bad pte2 %#x", __func__, pte2));
4329 if (pte2_is_dirty(pte2))
4332 pmap->pm_stats.resident_count--;
4333 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4334 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
4335 pvh = pa_to_pvh(pa);
4336 if (TAILQ_EMPTY(&pvh->pv_list))
4337 vm_page_aflag_clear(m, PGA_WRITEABLE);
4339 pmap_unuse_pt2(pmap, pv->pv_va, free);
4343 * Remove all pages from specified address space this aids process
4344 * exit speeds. Also, this code is special cased for current process
4345 * only, but can have the more generic (and slightly slower) mode enabled.
4346 * This is much faster than pmap_remove in the case of running down
4347 * an entire address space.
4350 pmap_remove_pages(pmap_t pmap)
4352 pt1_entry_t *pte1p, pte1;
4353 pt2_entry_t *pte2p, pte2;
4355 struct pv_chunk *pc, *npc;
4356 struct spglist free;
4359 uint32_t inuse, bitmask;
4363 * Assert that the given pmap is only active on the current
4364 * CPU. Unfortunately, we cannot block another CPU from
4365 * activating the pmap while this function is executing.
4367 KASSERT(pmap == vmspace_pmap(curthread->td_proc->p_vmspace),
4368 ("%s: non-current pmap %p", __func__, pmap));
4369 #if defined(SMP) && defined(INVARIANTS)
4371 cpuset_t other_cpus;
4374 other_cpus = pmap->pm_active;
4375 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
4377 KASSERT(CPU_EMPTY(&other_cpus),
4378 ("%s: pmap %p active on other cpus", __func__, pmap));
4382 rw_wlock(&pvh_global_lock);
4385 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4386 KASSERT(pc->pc_pmap == pmap, ("%s: wrong pmap %p %p",
4387 __func__, pmap, pc->pc_pmap));
4389 for (field = 0; field < _NPCM; field++) {
4390 inuse = (~(pc->pc_map[field])) & pc_freemask[field];
4391 while (inuse != 0) {
4392 bit = ffs(inuse) - 1;
4393 bitmask = 1UL << bit;
4394 idx = field * 32 + bit;
4395 pv = &pc->pc_pventry[idx];
4399 * Note that we cannot remove wired pages
4400 * from a process' mapping at this time
4402 pte1p = pmap_pte1(pmap, pv->pv_va);
4403 pte1 = pte1_load(pte1p);
4404 if (pte1_is_section(pte1)) {
4405 if (pte1_is_wired(pte1)) {
4410 pmap_remove_pte1_quick(pmap, pte1, pv,
4413 else if (pte1_is_link(pte1)) {
4414 pte2p = pt2map_entry(pv->pv_va);
4415 pte2 = pte2_load(pte2p);
4417 if (!pte2_is_valid(pte2)) {
4418 printf("%s: pmap %p va %#x "
4419 "pte2 %#x\n", __func__,
4420 pmap, pv->pv_va, pte2);
4424 if (pte2_is_wired(pte2)) {
4429 pmap_remove_pte2_quick(pmap, pte2, pv,
4432 printf("%s: pmap %p va %#x pte1 %#x\n",
4433 __func__, pmap, pv->pv_va, pte1);
4438 PV_STAT(pv_entry_frees++);
4439 PV_STAT(pv_entry_spare++);
4441 pc->pc_map[field] |= bitmask;
4445 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4449 tlb_flush_all_ng_local();
4451 rw_wunlock(&pvh_global_lock);
4453 pmap_free_zero_pages(&free);
4457 * This code makes some *MAJOR* assumptions:
4458 * 1. Current pmap & pmap exists.
4461 * 4. No L2 page table pages.
4462 * but is *MUCH* faster than pmap_enter...
4465 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4466 vm_prot_t prot, vm_page_t mpt2pg)
4468 pt2_entry_t *pte2p, pte2;
4470 struct spglist free;
4473 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
4474 (m->oflags & VPO_UNMANAGED) != 0,
4475 ("%s: managed mapping within the clean submap", __func__));
4476 rw_assert(&pvh_global_lock, RA_WLOCKED);
4477 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4480 * In the case that a L2 page table page is not
4481 * resident, we are creating it here.
4483 if (va < VM_MAXUSER_ADDRESS) {
4485 pt1_entry_t pte1, *pte1p;
4489 * Get L1 page table things.
4491 pte1_idx = pte1_index(va);
4492 pte1p = pmap_pte1(pmap, va);
4493 pte1 = pte1_load(pte1p);
4495 if (mpt2pg && (mpt2pg->pindex == (pte1_idx & ~PT2PG_MASK))) {
4497 * Each of NPT2_IN_PG L2 page tables on the page can
4498 * come here. Make sure that associated L1 page table
4499 * link is established.
4501 * QQQ: It comes that we don't establish all links to
4502 * L2 page tables for newly allocated L2 page
4505 KASSERT(!pte1_is_section(pte1),
4506 ("%s: pte1 %#x is section", __func__, pte1));
4507 if (!pte1_is_link(pte1)) {
4508 pt2_pa = page_pt2pa(VM_PAGE_TO_PHYS(mpt2pg),
4510 pte1_store(pte1p, PTE1_LINK(pt2_pa));
4512 pt2_wirecount_inc(mpt2pg, pte1_idx);
4515 * If the L2 page table page is mapped, we just
4516 * increment the hold count, and activate it.
4518 if (pte1_is_section(pte1)) {
4520 } else if (pte1_is_link(pte1)) {
4521 mpt2pg = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
4522 pt2_wirecount_inc(mpt2pg, pte1_idx);
4524 mpt2pg = _pmap_allocpte2(pmap, va,
4525 PMAP_ENTER_NOSLEEP);
4535 * This call to pt2map_entry() makes the assumption that we are
4536 * entering the page into the current pmap. In order to support
4537 * quick entry into any pmap, one would likely use pmap_pte2_quick().
4538 * But that isn't as quick as pt2map_entry().
4540 pte2p = pt2map_entry(va);
4541 pte2 = pte2_load(pte2p);
4542 if (pte2_is_valid(pte2)) {
4543 if (mpt2pg != NULL) {
4545 * Remove extra pte2 reference
4547 pt2_wirecount_dec(mpt2pg, pte1_index(va));
4554 * Enter on the PV list if part of our managed memory.
4556 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4557 !pmap_try_insert_pv_entry(pmap, va, m)) {
4558 if (mpt2pg != NULL) {
4560 if (pmap_unwire_pt2(pmap, va, mpt2pg, &free)) {
4561 pmap_tlb_flush(pmap, va);
4562 pmap_free_zero_pages(&free);
4571 * Increment counters
4573 pmap->pm_stats.resident_count++;
4576 * Now validate mapping with RO protection
4578 pa = VM_PAGE_TO_PHYS(m);
4579 l2prot = PTE2_RO | PTE2_NM;
4580 if (va < VM_MAXUSER_ADDRESS)
4581 l2prot |= PTE2_U | PTE2_NG;
4582 if ((prot & VM_PROT_EXECUTE) == 0)
4584 else if (m->md.pat_mode == VM_MEMATTR_WB_WA && pmap != kernel_pmap) {
4586 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4587 * is set. QQQ: For more info, see comments in pmap_enter().
4589 cache_icache_sync_fresh(va, pa, PAGE_SIZE);
4591 pte2_store(pte2p, PTE2(pa, l2prot, vm_page_pte2_attr(m)));
4597 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4600 rw_wlock(&pvh_global_lock);
4602 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
4603 rw_wunlock(&pvh_global_lock);
4608 * Tries to create 1MB page mapping. Returns TRUE if successful and
4609 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
4610 * blocking, (2) a mapping already exists at the specified virtual address, or
4611 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
4614 pmap_enter_pte1(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4620 rw_assert(&pvh_global_lock, RA_WLOCKED);
4621 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4622 pte1p = pmap_pte1(pmap, va);
4623 if (pte1_is_valid(pte1_load(pte1p))) {
4624 CTR3(KTR_PMAP, "%s: failure for va %#lx in pmap %p", __func__,
4628 if ((m->oflags & VPO_UNMANAGED) == 0) {
4630 * Abort this mapping if its PV entry could not be created.
4632 if (!pmap_pv_insert_pte1(pmap, va, VM_PAGE_TO_PHYS(m))) {
4633 CTR3(KTR_PMAP, "%s: failure for va %#lx in pmap %p",
4634 __func__, va, pmap);
4639 * Increment counters.
4641 pmap->pm_stats.resident_count += PTE1_SIZE / PAGE_SIZE;
4646 * QQQ: Why VM_PROT_WRITE is not evaluated and the mapping is
4649 pa = VM_PAGE_TO_PHYS(m);
4650 l1prot = PTE1_RO | PTE1_NM;
4651 if (va < VM_MAXUSER_ADDRESS)
4652 l1prot |= PTE1_U | PTE1_NG;
4653 if ((prot & VM_PROT_EXECUTE) == 0)
4655 else if (m->md.pat_mode == VM_MEMATTR_WB_WA && pmap != kernel_pmap) {
4657 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4658 * is set. QQQ: For more info, see comments in pmap_enter().
4660 cache_icache_sync_fresh(va, pa, PTE1_SIZE);
4662 pte1_store(pte1p, PTE1(pa, l1prot, ATTR_TO_L1(vm_page_pte2_attr(m))));
4664 pmap_pte1_mappings++;
4665 CTR3(KTR_PMAP, "%s: success for va %#lx in pmap %p", __func__, va,
4671 * Maps a sequence of resident pages belonging to the same object.
4672 * The sequence begins with the given page m_start. This page is
4673 * mapped at the given virtual address start. Each subsequent page is
4674 * mapped at a virtual address that is offset from start by the same
4675 * amount as the page is offset from m_start within the object. The
4676 * last page in the sequence is the page with the largest offset from
4677 * m_start that can be mapped at a virtual address less than the given
4678 * virtual address end. Not every virtual page between start and end
4679 * is mapped; only those for which a resident page exists with the
4680 * corresponding offset from m_start are mapped.
4683 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4684 vm_page_t m_start, vm_prot_t prot)
4687 vm_page_t m, mpt2pg;
4688 vm_pindex_t diff, psize;
4690 PDEBUG(6, printf("%s: pmap %p start %#x end %#x m %p prot %#x\n",
4691 __func__, pmap, start, end, m_start, prot));
4693 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4694 psize = atop(end - start);
4697 rw_wlock(&pvh_global_lock);
4699 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4700 va = start + ptoa(diff);
4701 if ((va & PTE1_OFFSET) == 0 && va + PTE1_SIZE <= end &&
4702 m->psind == 1 && sp_enabled &&
4703 pmap_enter_pte1(pmap, va, m, prot))
4704 m = &m[PTE1_SIZE / PAGE_SIZE - 1];
4706 mpt2pg = pmap_enter_quick_locked(pmap, va, m, prot,
4708 m = TAILQ_NEXT(m, listq);
4710 rw_wunlock(&pvh_global_lock);
4715 * This code maps large physical mmap regions into the
4716 * processor address space. Note that some shortcuts
4717 * are taken, but the code works.
4720 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4721 vm_pindex_t pindex, vm_size_t size)
4724 vm_paddr_t pa, pte2_pa;
4726 vm_memattr_t pat_mode;
4727 u_int l1attr, l1prot;
4729 VM_OBJECT_ASSERT_WLOCKED(object);
4730 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4731 ("%s: non-device object", __func__));
4732 if ((addr & PTE1_OFFSET) == 0 && (size & PTE1_OFFSET) == 0) {
4733 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4735 p = vm_page_lookup(object, pindex);
4736 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4737 ("%s: invalid page %p", __func__, p));
4738 pat_mode = p->md.pat_mode;
4741 * Abort the mapping if the first page is not physically
4742 * aligned to a 1MB page boundary.
4744 pte2_pa = VM_PAGE_TO_PHYS(p);
4745 if (pte2_pa & PTE1_OFFSET)
4749 * Skip the first page. Abort the mapping if the rest of
4750 * the pages are not physically contiguous or have differing
4751 * memory attributes.
4753 p = TAILQ_NEXT(p, listq);
4754 for (pa = pte2_pa + PAGE_SIZE; pa < pte2_pa + size;
4756 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4757 ("%s: invalid page %p", __func__, p));
4758 if (pa != VM_PAGE_TO_PHYS(p) ||
4759 pat_mode != p->md.pat_mode)
4761 p = TAILQ_NEXT(p, listq);
4765 * Map using 1MB pages.
4767 * QQQ: Well, we are mapping a section, so same condition must
4768 * be hold like during promotion. It looks that only RW mapping
4769 * is done here, so readonly mapping must be done elsewhere.
4771 l1prot = PTE1_U | PTE1_NG | PTE1_RW | PTE1_M | PTE1_A;
4772 l1attr = ATTR_TO_L1(vm_memattr_to_pte2(pat_mode));
4774 for (pa = pte2_pa; pa < pte2_pa + size; pa += PTE1_SIZE) {
4775 pte1p = pmap_pte1(pmap, addr);
4776 if (!pte1_is_valid(pte1_load(pte1p))) {
4777 pte1_store(pte1p, PTE1(pa, l1prot, l1attr));
4778 pmap->pm_stats.resident_count += PTE1_SIZE /
4780 pmap_pte1_mappings++;
4782 /* Else continue on if the PTE1 is already valid. */
4790 * Do the things to protect a 1mpage in a process.
4793 pmap_protect_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t sva,
4796 pt1_entry_t npte1, opte1;
4797 vm_offset_t eva, va;
4800 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4801 KASSERT((sva & PTE1_OFFSET) == 0,
4802 ("%s: sva is not 1mpage aligned", __func__));
4804 opte1 = npte1 = pte1_load(pte1p);
4805 if (pte1_is_managed(opte1)) {
4806 eva = sva + PTE1_SIZE;
4807 for (va = sva, m = PHYS_TO_VM_PAGE(pte1_pa(opte1));
4808 va < eva; va += PAGE_SIZE, m++)
4809 if (pte1_is_dirty(opte1))
4812 if ((prot & VM_PROT_WRITE) == 0)
4813 npte1 |= PTE1_RO | PTE1_NM;
4814 if ((prot & VM_PROT_EXECUTE) == 0)
4818 * QQQ: Herein, execute permission is never set.
4819 * It only can be cleared. So, no icache
4820 * syncing is needed.
4823 if (npte1 != opte1) {
4824 pte1_store(pte1p, npte1);
4825 pmap_tlb_flush(pmap, sva);
4830 * Set the physical protection on the
4831 * specified range of this map as requested.
4834 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
4836 boolean_t pv_lists_locked;
4838 pt1_entry_t *pte1p, pte1;
4839 pt2_entry_t *pte2p, opte2, npte2;
4841 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
4842 if (prot == VM_PROT_NONE) {
4843 pmap_remove(pmap, sva, eva);
4847 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
4848 (VM_PROT_WRITE | VM_PROT_EXECUTE))
4851 if (pmap_is_current(pmap))
4852 pv_lists_locked = FALSE;
4854 pv_lists_locked = TRUE;
4856 rw_wlock(&pvh_global_lock);
4861 for (; sva < eva; sva = nextva) {
4863 * Calculate address for next L2 page table.
4865 nextva = pte1_trunc(sva + PTE1_SIZE);
4869 pte1p = pmap_pte1(pmap, sva);
4870 pte1 = pte1_load(pte1p);
4873 * Weed out invalid mappings. Note: we assume that L1 page
4874 * page table is always allocated, and in kernel virtual.
4879 if (pte1_is_section(pte1)) {
4881 * Are we protecting the entire large page? If not,
4882 * demote the mapping and fall through.
4884 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
4885 pmap_protect_pte1(pmap, pte1p, sva, prot);
4888 if (!pv_lists_locked) {
4889 pv_lists_locked = TRUE;
4890 if (!rw_try_wlock(&pvh_global_lock)) {
4896 if (!pmap_demote_pte1(pmap, pte1p, sva)) {
4898 * The large page mapping
4905 /* Update pte1 after demotion */
4906 pte1 = pte1_load(pte1p);
4912 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
4913 " is not link", __func__, pmap, sva, pte1, pte1p));
4916 * Limit our scan to either the end of the va represented
4917 * by the current L2 page table page, or to the end of the
4918 * range being protected.
4923 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva; pte2p++,
4927 opte2 = npte2 = pte2_load(pte2p);
4928 if (!pte2_is_valid(opte2))
4931 if ((prot & VM_PROT_WRITE) == 0) {
4932 if (pte2_is_managed(opte2) &&
4933 pte2_is_dirty(opte2)) {
4934 m = PHYS_TO_VM_PAGE(pte2_pa(opte2));
4937 npte2 |= PTE2_RO | PTE2_NM;
4940 if ((prot & VM_PROT_EXECUTE) == 0)
4944 * QQQ: Herein, execute permission is never set.
4945 * It only can be cleared. So, no icache
4946 * syncing is needed.
4949 if (npte2 != opte2) {
4950 pte2_store(pte2p, npte2);
4951 pmap_tlb_flush(pmap, sva);
4955 if (pv_lists_locked) {
4957 rw_wunlock(&pvh_global_lock);
4963 * pmap_pvh_wired_mappings:
4965 * Return the updated number "count" of managed mappings that are wired.
4968 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4975 rw_assert(&pvh_global_lock, RA_WLOCKED);
4977 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4980 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
4981 if (pte1_is_section(pte1)) {
4982 if (pte1_is_wired(pte1))
4985 KASSERT(pte1_is_link(pte1),
4986 ("%s: pte1 %#x is not link", __func__, pte1));
4987 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
4988 if (pte2_is_wired(pte2))
4998 * pmap_page_wired_mappings:
5000 * Return the number of managed mappings to the given physical page
5004 pmap_page_wired_mappings(vm_page_t m)
5009 if ((m->oflags & VPO_UNMANAGED) != 0)
5011 rw_wlock(&pvh_global_lock);
5012 count = pmap_pvh_wired_mappings(&m->md, count);
5013 if ((m->flags & PG_FICTITIOUS) == 0) {
5014 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
5017 rw_wunlock(&pvh_global_lock);
5022 * Returns TRUE if any of the given mappings were used to modify
5023 * physical memory. Otherwise, returns FALSE. Both page and 1mpage
5024 * mappings are supported.
5027 pmap_is_modified_pvh(struct md_page *pvh)
5035 rw_assert(&pvh_global_lock, RA_WLOCKED);
5038 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5041 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5042 if (pte1_is_section(pte1)) {
5043 rv = pte1_is_dirty(pte1);
5045 KASSERT(pte1_is_link(pte1),
5046 ("%s: pte1 %#x is not link", __func__, pte1));
5047 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5048 rv = pte2_is_dirty(pte2);
5061 * Return whether or not the specified physical page was modified
5062 * in any physical maps.
5065 pmap_is_modified(vm_page_t m)
5069 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5070 ("%s: page %p is not managed", __func__, m));
5073 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5074 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
5075 * is clear, no PTE2s can have PG_M set.
5077 VM_OBJECT_ASSERT_WLOCKED(m->object);
5078 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5080 rw_wlock(&pvh_global_lock);
5081 rv = pmap_is_modified_pvh(&m->md) ||
5082 ((m->flags & PG_FICTITIOUS) == 0 &&
5083 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
5084 rw_wunlock(&pvh_global_lock);
5089 * pmap_is_prefaultable:
5091 * Return whether or not the specified virtual address is eligible
5095 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
5103 pte1 = pte1_load(pmap_pte1(pmap, addr));
5104 if (pte1_is_link(pte1)) {
5105 pte2 = pte2_load(pt2map_entry(addr));
5106 rv = !pte2_is_valid(pte2) ;
5113 * Returns TRUE if any of the given mappings were referenced and FALSE
5114 * otherwise. Both page and 1mpage mappings are supported.
5117 pmap_is_referenced_pvh(struct md_page *pvh)
5126 rw_assert(&pvh_global_lock, RA_WLOCKED);
5129 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5132 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5133 if (pte1_is_section(pte1)) {
5134 rv = (pte1 & (PTE1_A | PTE1_V)) == (PTE1_A | PTE1_V);
5136 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5137 rv = (pte2 & (PTE2_A | PTE2_V)) == (PTE2_A | PTE2_V);
5148 * pmap_is_referenced:
5150 * Return whether or not the specified physical page was referenced
5151 * in any physical maps.
5154 pmap_is_referenced(vm_page_t m)
5158 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5159 ("%s: page %p is not managed", __func__, m));
5160 rw_wlock(&pvh_global_lock);
5161 rv = pmap_is_referenced_pvh(&m->md) ||
5162 ((m->flags & PG_FICTITIOUS) == 0 &&
5163 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
5164 rw_wunlock(&pvh_global_lock);
5168 #define PMAP_TS_REFERENCED_MAX 5
5171 * pmap_ts_referenced:
5173 * Return a count of reference bits for a page, clearing those bits.
5174 * It is not necessary for every reference bit to be cleared, but it
5175 * is necessary that 0 only be returned when there are truly no
5176 * reference bits set.
5178 * XXX: The exact number of bits to check and clear is a matter that
5179 * should be tested and standardized at some point in the future for
5180 * optimal aging of shared pages.
5183 pmap_ts_referenced(vm_page_t m)
5185 struct md_page *pvh;
5188 pt1_entry_t *pte1p, opte1;
5193 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5194 ("%s: page %p is not managed", __func__, m));
5195 pa = VM_PAGE_TO_PHYS(m);
5196 pvh = pa_to_pvh(pa);
5197 rw_wlock(&pvh_global_lock);
5199 if ((m->flags & PG_FICTITIOUS) != 0 ||
5200 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5201 goto small_mappings;
5206 pte1p = pmap_pte1(pmap, pv->pv_va);
5207 opte1 = pte1_load(pte1p);
5208 if ((opte1 & PTE1_A) != 0) {
5210 * Since this reference bit is shared by 256 4KB pages,
5211 * it should not be cleared every time it is tested.
5212 * Apply a simple "hash" function on the physical page
5213 * number, the virtual section number, and the pmap
5214 * address to select one 4KB page out of the 256
5215 * on which testing the reference bit will result
5216 * in clearing that bit. This function is designed
5217 * to avoid the selection of the same 4KB page
5218 * for every 1MB page mapping.
5220 * On demotion, a mapping that hasn't been referenced
5221 * is simply destroyed. To avoid the possibility of a
5222 * subsequent page fault on a demoted wired mapping,
5223 * always leave its reference bit set. Moreover,
5224 * since the section is wired, the current state of
5225 * its reference bit won't affect page replacement.
5227 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PTE1_SHIFT) ^
5228 (uintptr_t)pmap) & (NPTE2_IN_PG - 1)) == 0 &&
5229 !pte1_is_wired(opte1)) {
5230 pte1_clear_bit(pte1p, PTE1_A);
5231 pmap_tlb_flush(pmap, pv->pv_va);
5236 /* Rotate the PV list if it has more than one entry. */
5237 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5238 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5239 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5241 if (rtval >= PMAP_TS_REFERENCED_MAX)
5243 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5245 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5251 pte1p = pmap_pte1(pmap, pv->pv_va);
5252 KASSERT(pte1_is_link(pte1_load(pte1p)),
5253 ("%s: not found a link in page %p's pv list", __func__, m));
5255 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5256 if ((pte2_load(pte2p) & PTE2_A) != 0) {
5257 pte2_clear_bit(pte2p, PTE2_A);
5258 pmap_tlb_flush(pmap, pv->pv_va);
5262 /* Rotate the PV list if it has more than one entry. */
5263 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5264 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5265 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5267 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
5268 PMAP_TS_REFERENCED_MAX);
5271 rw_wunlock(&pvh_global_lock);
5276 * Clear the wired attribute from the mappings for the specified range of
5277 * addresses in the given pmap. Every valid mapping within that range
5278 * must have the wired attribute set. In contrast, invalid mappings
5279 * cannot have the wired attribute set, so they are ignored.
5281 * The wired attribute of the page table entry is not a hardware feature,
5282 * so there is no need to invalidate any TLB entries.
5285 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5288 pt1_entry_t *pte1p, pte1;
5289 pt2_entry_t *pte2p, pte2;
5290 boolean_t pv_lists_locked;
5292 if (pmap_is_current(pmap))
5293 pv_lists_locked = FALSE;
5295 pv_lists_locked = TRUE;
5297 rw_wlock(&pvh_global_lock);
5301 for (; sva < eva; sva = nextva) {
5302 nextva = pte1_trunc(sva + PTE1_SIZE);
5306 pte1p = pmap_pte1(pmap, sva);
5307 pte1 = pte1_load(pte1p);
5310 * Weed out invalid mappings. Note: we assume that L1 page
5311 * page table is always allocated, and in kernel virtual.
5316 if (pte1_is_section(pte1)) {
5317 if (!pte1_is_wired(pte1))
5318 panic("%s: pte1 %#x not wired", __func__, pte1);
5321 * Are we unwiring the entire large page? If not,
5322 * demote the mapping and fall through.
5324 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
5325 pte1_clear_bit(pte1p, PTE1_W);
5326 pmap->pm_stats.wired_count -= PTE1_SIZE /
5330 if (!pv_lists_locked) {
5331 pv_lists_locked = TRUE;
5332 if (!rw_try_wlock(&pvh_global_lock)) {
5339 if (!pmap_demote_pte1(pmap, pte1p, sva))
5340 panic("%s: demotion failed", __func__);
5343 /* Update pte1 after demotion */
5344 pte1 = pte1_load(pte1p);
5350 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
5351 " is not link", __func__, pmap, sva, pte1, pte1p));
5354 * Limit our scan to either the end of the va represented
5355 * by the current L2 page table page, or to the end of the
5356 * range being protected.
5361 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva; pte2p++,
5363 pte2 = pte2_load(pte2p);
5364 if (!pte2_is_valid(pte2))
5366 if (!pte2_is_wired(pte2))
5367 panic("%s: pte2 %#x is missing PTE2_W",
5371 * PTE2_W must be cleared atomically. Although the pmap
5372 * lock synchronizes access to PTE2_W, another processor
5373 * could be changing PTE2_NM and/or PTE2_A concurrently.
5375 pte2_clear_bit(pte2p, PTE2_W);
5376 pmap->pm_stats.wired_count--;
5379 if (pv_lists_locked) {
5381 rw_wunlock(&pvh_global_lock);
5387 * Clear the write and modified bits in each of the given page's mappings.
5390 pmap_remove_write(vm_page_t m)
5392 struct md_page *pvh;
5393 pv_entry_t next_pv, pv;
5396 pt2_entry_t *pte2p, opte2;
5399 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5400 ("%s: page %p is not managed", __func__, m));
5403 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5404 * set by another thread while the object is locked. Thus,
5405 * if PGA_WRITEABLE is clear, no page table entries need updating.
5407 VM_OBJECT_ASSERT_WLOCKED(m->object);
5408 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5410 rw_wlock(&pvh_global_lock);
5412 if ((m->flags & PG_FICTITIOUS) != 0)
5413 goto small_mappings;
5414 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5415 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5419 pte1p = pmap_pte1(pmap, va);
5420 if (!(pte1_load(pte1p) & PTE1_RO))
5421 (void)pmap_demote_pte1(pmap, pte1p, va);
5425 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5428 pte1p = pmap_pte1(pmap, pv->pv_va);
5429 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found"
5430 " a section in page %p's pv list", __func__, m));
5431 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5432 opte2 = pte2_load(pte2p);
5433 if (!(opte2 & PTE2_RO)) {
5434 pte2_store(pte2p, opte2 | PTE2_RO | PTE2_NM);
5435 if (pte2_is_dirty(opte2))
5437 pmap_tlb_flush(pmap, pv->pv_va);
5441 vm_page_aflag_clear(m, PGA_WRITEABLE);
5443 rw_wunlock(&pvh_global_lock);
5447 * Apply the given advice to the specified range of addresses within the
5448 * given pmap. Depending on the advice, clear the referenced and/or
5449 * modified flags in each mapping and set the mapped page's dirty field.
5452 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5454 pt1_entry_t *pte1p, opte1;
5455 pt2_entry_t *pte2p, pte2;
5458 boolean_t pv_lists_locked;
5460 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5462 if (pmap_is_current(pmap))
5463 pv_lists_locked = FALSE;
5465 pv_lists_locked = TRUE;
5467 rw_wlock(&pvh_global_lock);
5471 for (; sva < eva; sva = pdnxt) {
5472 pdnxt = pte1_trunc(sva + PTE1_SIZE);
5475 pte1p = pmap_pte1(pmap, sva);
5476 opte1 = pte1_load(pte1p);
5477 if (!pte1_is_valid(opte1)) /* XXX */
5479 else if (pte1_is_section(opte1)) {
5480 if (!pte1_is_managed(opte1))
5482 if (!pv_lists_locked) {
5483 pv_lists_locked = TRUE;
5484 if (!rw_try_wlock(&pvh_global_lock)) {
5490 if (!pmap_demote_pte1(pmap, pte1p, sva)) {
5492 * The large page mapping was destroyed.
5498 * Unless the page mappings are wired, remove the
5499 * mapping to a single page so that a subsequent
5500 * access may repromote. Since the underlying L2 page
5501 * table is fully populated, this removal never
5502 * frees a L2 page table page.
5504 if (!pte1_is_wired(opte1)) {
5505 pte2p = pmap_pte2_quick(pmap, sva);
5506 KASSERT(pte2_is_valid(pte2_load(pte2p)),
5507 ("%s: invalid PTE2", __func__));
5508 pmap_remove_pte2(pmap, pte2p, sva, NULL);
5513 for (pte2p = pmap_pte2_quick(pmap, sva); sva != pdnxt; pte2p++,
5515 pte2 = pte2_load(pte2p);
5516 if (!pte2_is_valid(pte2) || !pte2_is_managed(pte2))
5518 else if (pte2_is_dirty(pte2)) {
5519 if (advice == MADV_DONTNEED) {
5521 * Future calls to pmap_is_modified()
5522 * can be avoided by making the page
5525 m = PHYS_TO_VM_PAGE(pte2_pa(pte2));
5528 pte2_set_bit(pte2p, PTE2_NM);
5529 pte2_clear_bit(pte2p, PTE2_A);
5530 } else if ((pte2 & PTE2_A) != 0)
5531 pte2_clear_bit(pte2p, PTE2_A);
5534 pmap_tlb_flush(pmap, sva);
5537 if (pv_lists_locked) {
5539 rw_wunlock(&pvh_global_lock);
5545 * Clear the modify bits on the specified physical page.
5548 pmap_clear_modify(vm_page_t m)
5550 struct md_page *pvh;
5551 pv_entry_t next_pv, pv;
5553 pt1_entry_t *pte1p, opte1;
5554 pt2_entry_t *pte2p, opte2;
5557 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5558 ("%s: page %p is not managed", __func__, m));
5559 VM_OBJECT_ASSERT_WLOCKED(m->object);
5560 KASSERT(!vm_page_xbusied(m),
5561 ("%s: page %p is exclusive busy", __func__, m));
5564 * If the page is not PGA_WRITEABLE, then no PTE2s can have PTE2_NM
5565 * cleared. If the object containing the page is locked and the page
5566 * is not exclusive busied, then PGA_WRITEABLE cannot be concurrently
5569 if ((m->flags & PGA_WRITEABLE) == 0)
5571 rw_wlock(&pvh_global_lock);
5573 if ((m->flags & PG_FICTITIOUS) != 0)
5574 goto small_mappings;
5575 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5576 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5580 pte1p = pmap_pte1(pmap, va);
5581 opte1 = pte1_load(pte1p);
5582 if (!(opte1 & PTE1_RO)) {
5583 if (pmap_demote_pte1(pmap, pte1p, va) &&
5584 !pte1_is_wired(opte1)) {
5586 * Write protect the mapping to a
5587 * single page so that a subsequent
5588 * write access may repromote.
5590 va += VM_PAGE_TO_PHYS(m) - pte1_pa(opte1);
5591 pte2p = pmap_pte2_quick(pmap, va);
5592 opte2 = pte2_load(pte2p);
5593 if ((opte2 & PTE2_V)) {
5594 pte2_set_bit(pte2p, PTE2_NM | PTE2_RO);
5596 pmap_tlb_flush(pmap, va);
5603 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5606 pte1p = pmap_pte1(pmap, pv->pv_va);
5607 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found"
5608 " a section in page %p's pv list", __func__, m));
5609 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5610 if (pte2_is_dirty(pte2_load(pte2p))) {
5611 pte2_set_bit(pte2p, PTE2_NM);
5612 pmap_tlb_flush(pmap, pv->pv_va);
5617 rw_wunlock(&pvh_global_lock);
5622 * Sets the memory attribute for the specified page.
5625 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5627 struct sysmaps *sysmaps;
5631 oma = m->md.pat_mode;
5632 m->md.pat_mode = ma;
5634 CTR5(KTR_PMAP, "%s: page %p - 0x%08X oma: %d, ma: %d", __func__, m,
5635 VM_PAGE_TO_PHYS(m), oma, ma);
5636 if ((m->flags & PG_FICTITIOUS) != 0)
5640 * If "m" is a normal page, flush it from the cache.
5642 * First, try to find an existing mapping of the page by sf
5643 * buffer. sf_buf_invalidate_cache() modifies mapping and
5644 * flushes the cache.
5646 if (sf_buf_invalidate_cache(m, oma))
5650 * If page is not mapped by sf buffer, map the page
5651 * transient and do invalidation.
5654 pa = VM_PAGE_TO_PHYS(m);
5656 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
5657 mtx_lock(&sysmaps->lock);
5658 if (*sysmaps->CMAP2)
5659 panic("%s: CMAP2 busy", __func__);
5660 pte2_store(sysmaps->CMAP2, PTE2_KERN_NG(pa, PTE2_AP_KRW,
5661 vm_memattr_to_pte2(ma)));
5662 dcache_wbinv_poc((vm_offset_t)sysmaps->CADDR2, pa, PAGE_SIZE);
5663 pte2_clear(sysmaps->CMAP2);
5664 tlb_flush((vm_offset_t)sysmaps->CADDR2);
5666 mtx_unlock(&sysmaps->lock);
5671 * Miscellaneous support routines follow
5675 * Returns TRUE if the given page is mapped individually or as part of
5676 * a 1mpage. Otherwise, returns FALSE.
5679 pmap_page_is_mapped(vm_page_t m)
5683 if ((m->oflags & VPO_UNMANAGED) != 0)
5685 rw_wlock(&pvh_global_lock);
5686 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5687 ((m->flags & PG_FICTITIOUS) == 0 &&
5688 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
5689 rw_wunlock(&pvh_global_lock);
5694 * Returns true if the pmap's pv is one of the first
5695 * 16 pvs linked to from this page. This count may
5696 * be changed upwards or downwards in the future; it
5697 * is only necessary that true be returned for a small
5698 * subset of pmaps for proper page aging.
5701 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5703 struct md_page *pvh;
5708 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5709 ("%s: page %p is not managed", __func__, m));
5711 rw_wlock(&pvh_global_lock);
5712 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5713 if (PV_PMAP(pv) == pmap) {
5721 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5722 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5723 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5724 if (PV_PMAP(pv) == pmap) {
5733 rw_wunlock(&pvh_global_lock);
5738 * pmap_zero_page zeros the specified hardware page by mapping
5739 * the page into KVM and using bzero to clear its contents.
5742 pmap_zero_page(vm_page_t m)
5744 struct sysmaps *sysmaps;
5747 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
5748 mtx_lock(&sysmaps->lock);
5749 if (pte2_load(sysmaps->CMAP2) != 0)
5750 panic("%s: CMAP2 busy", __func__);
5751 pte2_store(sysmaps->CMAP2, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5752 vm_page_pte2_attr(m)));
5753 pagezero(sysmaps->CADDR2);
5754 pte2_clear(sysmaps->CMAP2);
5755 tlb_flush((vm_offset_t)sysmaps->CADDR2);
5757 mtx_unlock(&sysmaps->lock);
5761 * pmap_zero_page_area zeros the specified hardware page by mapping
5762 * the page into KVM and using bzero to clear its contents.
5764 * off and size may not cover an area beyond a single hardware page.
5767 pmap_zero_page_area(vm_page_t m, int off, int size)
5769 struct sysmaps *sysmaps;
5772 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
5773 mtx_lock(&sysmaps->lock);
5774 if (pte2_load(sysmaps->CMAP2) != 0)
5775 panic("%s: CMAP2 busy", __func__);
5776 pte2_store(sysmaps->CMAP2, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5777 vm_page_pte2_attr(m)));
5778 if (off == 0 && size == PAGE_SIZE)
5779 pagezero(sysmaps->CADDR2);
5781 bzero(sysmaps->CADDR2 + off, size);
5782 pte2_clear(sysmaps->CMAP2);
5783 tlb_flush((vm_offset_t)sysmaps->CADDR2);
5785 mtx_unlock(&sysmaps->lock);
5789 * pmap_zero_page_idle zeros the specified hardware page by mapping
5790 * the page into KVM and using bzero to clear its contents. This
5791 * is intended to be called from the vm_pagezero process only and
5795 pmap_zero_page_idle(vm_page_t m)
5798 if (pte2_load(CMAP3) != 0)
5799 panic("%s: CMAP3 busy", __func__);
5801 pte2_store(CMAP3, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5802 vm_page_pte2_attr(m)));
5805 tlb_flush((vm_offset_t)CADDR3);
5810 * pmap_copy_page copies the specified (machine independent)
5811 * page by mapping the page into virtual memory and using
5812 * bcopy to copy the page, one machine dependent page at a
5816 pmap_copy_page(vm_page_t src, vm_page_t dst)
5818 struct sysmaps *sysmaps;
5821 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
5822 mtx_lock(&sysmaps->lock);
5823 if (pte2_load(sysmaps->CMAP1) != 0)
5824 panic("%s: CMAP1 busy", __func__);
5825 if (pte2_load(sysmaps->CMAP2) != 0)
5826 panic("%s: CMAP2 busy", __func__);
5827 pte2_store(sysmaps->CMAP1, PTE2_KERN_NG(VM_PAGE_TO_PHYS(src),
5828 PTE2_AP_KR | PTE2_NM, vm_page_pte2_attr(src)));
5829 pte2_store(sysmaps->CMAP2, PTE2_KERN_NG(VM_PAGE_TO_PHYS(dst),
5830 PTE2_AP_KRW, vm_page_pte2_attr(dst)));
5831 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE);
5832 pte2_clear(sysmaps->CMAP1);
5833 tlb_flush((vm_offset_t)sysmaps->CADDR1);
5834 pte2_clear(sysmaps->CMAP2);
5835 tlb_flush((vm_offset_t)sysmaps->CADDR2);
5837 mtx_unlock(&sysmaps->lock);
5840 int unmapped_buf_allowed = 1;
5843 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5844 vm_offset_t b_offset, int xfersize)
5846 struct sysmaps *sysmaps;
5847 vm_page_t a_pg, b_pg;
5849 vm_offset_t a_pg_offset, b_pg_offset;
5853 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
5854 mtx_lock(&sysmaps->lock);
5855 if (*sysmaps->CMAP1 != 0)
5856 panic("pmap_copy_pages: CMAP1 busy");
5857 if (*sysmaps->CMAP2 != 0)
5858 panic("pmap_copy_pages: CMAP2 busy");
5859 while (xfersize > 0) {
5860 a_pg = ma[a_offset >> PAGE_SHIFT];
5861 a_pg_offset = a_offset & PAGE_MASK;
5862 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5863 b_pg = mb[b_offset >> PAGE_SHIFT];
5864 b_pg_offset = b_offset & PAGE_MASK;
5865 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5866 pte2_store(sysmaps->CMAP1, PTE2_KERN_NG(VM_PAGE_TO_PHYS(a_pg),
5867 PTE2_AP_KR | PTE2_NM, vm_page_pte2_attr(a_pg)));
5868 tlb_flush_local((vm_offset_t)sysmaps->CADDR1);
5869 pte2_store(sysmaps->CMAP2, PTE2_KERN_NG(VM_PAGE_TO_PHYS(b_pg),
5870 PTE2_AP_KRW, vm_page_pte2_attr(b_pg)));
5871 tlb_flush_local((vm_offset_t)sysmaps->CADDR2);
5872 a_cp = sysmaps->CADDR1 + a_pg_offset;
5873 b_cp = sysmaps->CADDR2 + b_pg_offset;
5874 bcopy(a_cp, b_cp, cnt);
5879 pte2_clear(sysmaps->CMAP1);
5880 tlb_flush((vm_offset_t)sysmaps->CADDR1);
5881 pte2_clear(sysmaps->CMAP2);
5882 tlb_flush((vm_offset_t)sysmaps->CADDR2);
5884 mtx_unlock(&sysmaps->lock);
5888 pmap_quick_enter_page(vm_page_t m)
5891 vm_offset_t qmap_addr;
5894 qmap_addr = PCPU_GET(qmap_addr);
5895 pte2p = pt2map_entry(qmap_addr);
5897 KASSERT(pte2_load(pte2p) == 0, ("%s: PTE2 busy", __func__));
5899 pte2_store(pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5900 vm_page_pte2_attr(m)));
5905 pmap_quick_remove_page(vm_offset_t addr)
5908 vm_offset_t qmap_addr;
5910 qmap_addr = PCPU_GET(qmap_addr);
5911 pte2p = pt2map_entry(qmap_addr);
5913 KASSERT(addr == qmap_addr, ("%s: invalid address", __func__));
5914 KASSERT(pte2_load(pte2p) != 0, ("%s: PTE2 not in use", __func__));
5917 tlb_flush(qmap_addr);
5922 * Copy the range specified by src_addr/len
5923 * from the source map to the range dst_addr/len
5924 * in the destination map.
5926 * This routine is only advisory and need not do anything.
5929 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
5930 vm_offset_t src_addr)
5932 struct spglist free;
5934 vm_offset_t end_addr = src_addr + len;
5937 if (dst_addr != src_addr)
5940 if (!pmap_is_current(src_pmap))
5943 rw_wlock(&pvh_global_lock);
5944 if (dst_pmap < src_pmap) {
5945 PMAP_LOCK(dst_pmap);
5946 PMAP_LOCK(src_pmap);
5948 PMAP_LOCK(src_pmap);
5949 PMAP_LOCK(dst_pmap);
5952 for (addr = src_addr; addr < end_addr; addr = nextva) {
5953 pt2_entry_t *src_pte2p, *dst_pte2p;
5954 vm_page_t dst_mpt2pg, src_mpt2pg;
5955 pt1_entry_t src_pte1;
5958 KASSERT(addr < VM_MAXUSER_ADDRESS,
5959 ("%s: invalid to pmap_copy page tables", __func__));
5961 nextva = pte1_trunc(addr + PTE1_SIZE);
5965 pte1_idx = pte1_index(addr);
5966 src_pte1 = src_pmap->pm_pt1[pte1_idx];
5967 if (pte1_is_section(src_pte1)) {
5968 if ((addr & PTE1_OFFSET) != 0 ||
5969 (addr + PTE1_SIZE) > end_addr)
5971 if (dst_pmap->pm_pt1[pte1_idx] == 0 &&
5972 (!pte1_is_managed(src_pte1) ||
5973 pmap_pv_insert_pte1(dst_pmap, addr,
5974 pte1_pa(src_pte1)))) {
5975 dst_pmap->pm_pt1[pte1_idx] = src_pte1 &
5977 dst_pmap->pm_stats.resident_count +=
5978 PTE1_SIZE / PAGE_SIZE;
5979 pmap_pte1_mappings++;
5982 } else if (!pte1_is_link(src_pte1))
5985 src_mpt2pg = PHYS_TO_VM_PAGE(pte1_link_pa(src_pte1));
5988 * We leave PT2s to be linked from PT1 even if they are not
5989 * referenced until all PT2s in a page are without reference.
5991 * QQQ: It could be changed ...
5993 #if 0 /* single_pt2_link_is_cleared */
5994 KASSERT(pt2_wirecount_get(src_mpt2pg, pte1_idx) > 0,
5995 ("%s: source page table page is unused", __func__));
5997 if (pt2_wirecount_get(src_mpt2pg, pte1_idx) == 0)
6000 if (nextva > end_addr)
6003 src_pte2p = pt2map_entry(addr);
6004 while (addr < nextva) {
6005 pt2_entry_t temp_pte2;
6006 temp_pte2 = pte2_load(src_pte2p);
6008 * we only virtual copy managed pages
6010 if (pte2_is_managed(temp_pte2)) {
6011 dst_mpt2pg = pmap_allocpte2(dst_pmap, addr,
6012 PMAP_ENTER_NOSLEEP);
6013 if (dst_mpt2pg == NULL)
6015 dst_pte2p = pmap_pte2_quick(dst_pmap, addr);
6016 if (!pte2_is_valid(pte2_load(dst_pte2p)) &&
6017 pmap_try_insert_pv_entry(dst_pmap, addr,
6018 PHYS_TO_VM_PAGE(pte2_pa(temp_pte2)))) {
6020 * Clear the wired, modified, and
6021 * accessed (referenced) bits
6024 temp_pte2 &= ~(PTE2_W | PTE2_A);
6025 temp_pte2 |= PTE2_NM;
6026 pte2_store(dst_pte2p, temp_pte2);
6027 dst_pmap->pm_stats.resident_count++;
6030 if (pmap_unwire_pt2(dst_pmap, addr,
6031 dst_mpt2pg, &free)) {
6032 pmap_tlb_flush(dst_pmap, addr);
6033 pmap_free_zero_pages(&free);
6037 if (pt2_wirecount_get(dst_mpt2pg, pte1_idx) >=
6038 pt2_wirecount_get(src_mpt2pg, pte1_idx))
6047 rw_wunlock(&pvh_global_lock);
6048 PMAP_UNLOCK(src_pmap);
6049 PMAP_UNLOCK(dst_pmap);
6053 * Increase the starting virtual address of the given mapping if a
6054 * different alignment might result in more section mappings.
6057 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6058 vm_offset_t *addr, vm_size_t size)
6060 vm_offset_t pte1_offset;
6062 if (size < PTE1_SIZE)
6064 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6065 offset += ptoa(object->pg_color);
6066 pte1_offset = offset & PTE1_OFFSET;
6067 if (size - ((PTE1_SIZE - pte1_offset) & PTE1_OFFSET) < PTE1_SIZE ||
6068 (*addr & PTE1_OFFSET) == pte1_offset)
6070 if ((*addr & PTE1_OFFSET) < pte1_offset)
6071 *addr = pte1_trunc(*addr) + pte1_offset;
6073 *addr = pte1_roundup(*addr) + pte1_offset;
6077 pmap_activate(struct thread *td)
6079 pmap_t pmap, oldpmap;
6082 PDEBUG(9, printf("%s: td = %08x\n", __func__, (uint32_t)td));
6085 pmap = vmspace_pmap(td->td_proc->p_vmspace);
6086 oldpmap = PCPU_GET(curpmap);
6087 cpuid = PCPU_GET(cpuid);
6090 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
6091 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
6093 CPU_CLR(cpuid, &oldpmap->pm_active);
6094 CPU_SET(cpuid, &pmap->pm_active);
6097 ttb = pmap_ttb_get(pmap);
6100 * pmap_activate is for the current thread on the current cpu
6102 td->td_pcb->pcb_pagedir = ttb;
6104 PCPU_SET(curpmap, pmap);
6109 * Perform the pmap work for mincore.
6112 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
6114 pt1_entry_t *pte1p, pte1;
6115 pt2_entry_t *pte2p, pte2;
6122 pte1p = pmap_pte1(pmap, addr);
6123 pte1 = pte1_load(pte1p);
6124 if (pte1_is_section(pte1)) {
6125 pa = trunc_page(pte1_pa(pte1) | (addr & PTE1_OFFSET));
6126 managed = pte1_is_managed(pte1);
6127 val = MINCORE_SUPER | MINCORE_INCORE;
6128 if (pte1_is_dirty(pte1))
6129 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6131 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6132 } else if (pte1_is_link(pte1)) {
6133 pte2p = pmap_pte2(pmap, addr);
6134 pte2 = pte2_load(pte2p);
6135 pmap_pte2_release(pte2p);
6137 managed = pte2_is_managed(pte2);
6138 val = MINCORE_INCORE;
6139 if (pte2_is_dirty(pte2))
6140 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6142 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6147 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
6148 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
6149 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
6150 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
6153 PA_UNLOCK_COND(*locked_pa);
6159 pmap_kenter_device(vm_offset_t va, vm_size_t size, vm_paddr_t pa)
6164 KASSERT((size & PAGE_MASK) == 0,
6165 ("%s: device mapping not page-sized", __func__));
6168 l2attr = vm_memattr_to_pte2(VM_MEMATTR_DEVICE);
6170 pmap_kenter_prot_attr(va, pa, PTE2_AP_KRW, l2attr);
6175 tlb_flush_range(sva, va - sva);
6179 pmap_kremove_device(vm_offset_t va, vm_size_t size)
6183 KASSERT((size & PAGE_MASK) == 0,
6184 ("%s: device mapping not page-sized", __func__));
6192 tlb_flush_range(sva, va - sva);
6196 pmap_set_pcb_pagedir(pmap_t pmap, struct pcb *pcb)
6199 pcb->pcb_pagedir = pmap_ttb_get(pmap);
6204 * Clean L1 data cache range by physical address.
6205 * The range must be within a single page.
6208 pmap_dcache_wb_pou(vm_paddr_t pa, vm_size_t size, uint32_t attr)
6210 struct sysmaps *sysmaps;
6212 KASSERT(((pa & PAGE_MASK) + size) <= PAGE_SIZE,
6213 ("%s: not on single page", __func__));
6216 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
6217 mtx_lock(&sysmaps->lock);
6218 if (*sysmaps->CMAP3)
6219 panic("%s: CMAP3 busy", __func__);
6220 pte2_store(sysmaps->CMAP3, PTE2_KERN_NG(pa, PTE2_AP_KRW, attr));
6221 dcache_wb_pou((vm_offset_t)sysmaps->CADDR3 + (pa & PAGE_MASK), size);
6222 pte2_clear(sysmaps->CMAP3);
6223 tlb_flush((vm_offset_t)sysmaps->CADDR3);
6225 mtx_unlock(&sysmaps->lock);
6229 * Sync instruction cache range which is not mapped yet.
6232 cache_icache_sync_fresh(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
6234 uint32_t len, offset;
6237 /* Write back d-cache on given address range. */
6238 offset = pa & PAGE_MASK;
6239 for ( ; size != 0; size -= len, pa += len, offset = 0) {
6240 len = min(PAGE_SIZE - offset, size);
6241 m = PHYS_TO_VM_PAGE(pa);
6242 KASSERT(m != NULL, ("%s: vm_page_t is null for %#x",
6244 pmap_dcache_wb_pou(pa, len, vm_page_pte2_attr(m));
6247 * I-cache is VIPT. Only way how to flush all virtual mappings
6248 * on given physical address is to invalidate all i-cache.
6254 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t size)
6257 /* Write back d-cache on given address range. */
6258 if (va >= VM_MIN_KERNEL_ADDRESS) {
6259 dcache_wb_pou(va, size);
6261 uint32_t len, offset;
6265 offset = va & PAGE_MASK;
6266 for ( ; size != 0; size -= len, va += len, offset = 0) {
6267 pa = pmap_extract(pmap, va); /* offset is preserved */
6268 len = min(PAGE_SIZE - offset, size);
6269 m = PHYS_TO_VM_PAGE(pa);
6270 KASSERT(m != NULL, ("%s: vm_page_t is null for %#x",
6272 pmap_dcache_wb_pou(pa, len, vm_page_pte2_attr(m));
6276 * I-cache is VIPT. Only way how to flush all virtual mappings
6277 * on given physical address is to invalidate all i-cache.
6283 * The implementation of pmap_fault() uses IN_RANGE2() macro which
6284 * depends on the fact that given range size is a power of 2.
6286 CTASSERT(powerof2(NB_IN_PT1));
6287 CTASSERT(powerof2(PT2MAP_SIZE));
6289 #define IN_RANGE2(addr, start, size) \
6290 ((vm_offset_t)(start) == ((vm_offset_t)(addr) & ~((size) - 1)))
6293 * Handle access and R/W emulation faults.
6296 pmap_fault(pmap_t pmap, vm_offset_t far, uint32_t fsr, int idx, bool usermode)
6298 pt1_entry_t *pte1p, pte1;
6299 pt2_entry_t *pte2p, pte2;
6305 * In kernel, we should never get abort with FAR which is in range of
6306 * pmap->pm_pt1 or PT2MAP address spaces. If it happens, stop here
6307 * and print out a useful abort message and even get to the debugger
6308 * otherwise it likely ends with never ending loop of aborts.
6310 if (__predict_false(IN_RANGE2(far, pmap->pm_pt1, NB_IN_PT1))) {
6312 * All L1 tables should always be mapped and present.
6313 * However, we check only current one herein. For user mode,
6314 * only permission abort from malicious user is not fatal.
6315 * And alignment abort as it may have higher priority.
6317 if (!usermode || (idx != FAULT_ALIGN && idx != FAULT_PERM_L2)) {
6318 CTR4(KTR_PMAP, "%s: pmap %#x pm_pt1 %#x far %#x",
6319 __func__, pmap, pmap->pm_pt1, far);
6320 panic("%s: pm_pt1 abort", __func__);
6322 return (KERN_INVALID_ADDRESS);
6324 if (__predict_false(IN_RANGE2(far, PT2MAP, PT2MAP_SIZE))) {
6326 * PT2MAP should be always mapped and present in current
6327 * L1 table. However, only existing L2 tables are mapped
6328 * in PT2MAP. For user mode, only L2 translation abort and
6329 * permission abort from malicious user is not fatal.
6330 * And alignment abort as it may have higher priority.
6332 if (!usermode || (idx != FAULT_ALIGN &&
6333 idx != FAULT_TRAN_L2 && idx != FAULT_PERM_L2)) {
6334 CTR4(KTR_PMAP, "%s: pmap %#x PT2MAP %#x far %#x",
6335 __func__, pmap, PT2MAP, far);
6336 panic("%s: PT2MAP abort", __func__);
6338 return (KERN_INVALID_ADDRESS);
6342 * A pmap lock is used below for handling of access and R/W emulation
6343 * aborts. They were handled by atomic operations before so some
6344 * analysis of new situation is needed to answer the following question:
6345 * Is it safe to use the lock even for these aborts?
6347 * There may happen two cases in general:
6349 * (1) Aborts while the pmap lock is locked already - this should not
6350 * happen as pmap lock is not recursive. However, under pmap lock only
6351 * internal kernel data should be accessed and such data should be
6352 * mapped with A bit set and NM bit cleared. If double abort happens,
6353 * then a mapping of data which has caused it must be fixed. Further,
6354 * all new mappings are always made with A bit set and the bit can be
6355 * cleared only on managed mappings.
6357 * (2) Aborts while another lock(s) is/are locked - this already can
6358 * happen. However, there is no difference here if it's either access or
6359 * R/W emulation abort, or if it's some other abort.
6365 * Special treatment is due to break-before-make approach done when
6366 * pte1 is updated for userland mapping during section promotion or
6367 * demotion. If not caught here, pmap_enter() can find a section
6368 * mapping on faulting address. That is not allowed.
6370 if (idx == FAULT_TRAN_L1 && usermode && cp15_ats1cur_check(far) == 0) {
6372 return (KERN_SUCCESS);
6376 * Accesss bits for page and section. Note that the entry
6377 * is not in TLB yet, so TLB flush is not necessary.
6379 * QQQ: This is hardware emulation, we do not call userret()
6380 * for aborts from user mode.
6382 if (idx == FAULT_ACCESS_L2) {
6383 pte2p = pt2map_entry(far);
6384 pte2 = pte2_load(pte2p);
6385 if (pte2_is_valid(pte2)) {
6386 pte2_store(pte2p, pte2 | PTE2_A);
6388 return (KERN_SUCCESS);
6391 if (idx == FAULT_ACCESS_L1) {
6392 pte1p = pmap_pte1(pmap, far);
6393 pte1 = pte1_load(pte1p);
6394 if (pte1_is_section(pte1)) {
6395 pte1_store(pte1p, pte1 | PTE1_A);
6397 return (KERN_SUCCESS);
6402 * Handle modify bits for page and section. Note that the modify
6403 * bit is emulated by software. So PTEx_RO is software read only
6404 * bit and PTEx_NM flag is real hardware read only bit.
6406 * QQQ: This is hardware emulation, we do not call userret()
6407 * for aborts from user mode.
6409 if ((fsr & FSR_WNR) && (idx == FAULT_PERM_L2)) {
6410 pte2p = pt2map_entry(far);
6411 pte2 = pte2_load(pte2p);
6412 if (pte2_is_valid(pte2) && !(pte2 & PTE2_RO) &&
6414 pte2_store(pte2p, pte2 & ~PTE2_NM);
6415 tlb_flush(trunc_page(far));
6417 return (KERN_SUCCESS);
6420 if ((fsr & FSR_WNR) && (idx == FAULT_PERM_L1)) {
6421 pte1p = pmap_pte1(pmap, far);
6422 pte1 = pte1_load(pte1p);
6423 if (pte1_is_section(pte1) && !(pte1 & PTE1_RO) &&
6425 pte1_store(pte1p, pte1 & ~PTE1_NM);
6426 tlb_flush(pte1_trunc(far));
6428 return (KERN_SUCCESS);
6433 * QQQ: The previous code, mainly fast handling of access and
6434 * modify bits aborts, could be moved to ASM. Now we are
6435 * starting to deal with not fast aborts.
6440 * Read an entry in PT2TAB associated with both pmap and far.
6441 * It's safe because PT2TAB is always mapped.
6443 pte2 = pt2tab_load(pmap_pt2tab_entry(pmap, far));
6444 if (pte2_is_valid(pte2)) {
6446 * Now, when we know that L2 page table is allocated,
6447 * we can use PT2MAP to get L2 page table entry.
6449 pte2 = pte2_load(pt2map_entry(far));
6450 if (pte2_is_valid(pte2)) {
6452 * If L2 page table entry is valid, make sure that
6453 * L1 page table entry is valid too. Note that we
6454 * leave L2 page entries untouched when promoted.
6456 pte1 = pte1_load(pmap_pte1(pmap, far));
6457 if (!pte1_is_valid(pte1)) {
6458 panic("%s: missing L1 page entry (%p, %#x)",
6459 __func__, pmap, far);
6465 return (KERN_FAILURE);
6468 #if defined(PMAP_DEBUG)
6470 * Reusing of KVA used in pmap_zero_page function !!!
6473 pmap_zero_page_check(vm_page_t m)
6476 struct sysmaps *sysmaps;
6479 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
6480 mtx_lock(&sysmaps->lock);
6481 if (pte2_load(sysmaps->CMAP2) != 0)
6482 panic("%s: CMAP2 busy", __func__);
6483 pte2_store(sysmaps->CMAP2, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
6484 vm_page_pte2_attr(m)));
6485 end = (uint32_t*)(sysmaps->CADDR2 + PAGE_SIZE);
6486 for (p = (uint32_t*)sysmaps->CADDR2; p < end; p++)
6488 panic("%s: page %p not zero, va: %p", __func__, m,
6490 pte2_clear(sysmaps->CMAP2);
6491 tlb_flush((vm_offset_t)sysmaps->CADDR2);
6493 mtx_unlock(&sysmaps->lock);
6497 pmap_pid_dump(int pid)
6504 sx_slock(&allproc_lock);
6505 FOREACH_PROC_IN_SYSTEM(p) {
6506 if (p->p_pid != pid || p->p_vmspace == NULL)
6509 pmap = vmspace_pmap(p->p_vmspace);
6510 for (i = 0; i < NPTE1_IN_PT1; i++) {
6512 pt2_entry_t *pte2p, pte2;
6513 vm_offset_t base, va;
6517 base = i << PTE1_SHIFT;
6518 pte1 = pte1_load(&pmap->pm_pt1[i]);
6520 if (pte1_is_section(pte1)) {
6522 * QQQ: Do something here!
6524 } else if (pte1_is_link(pte1)) {
6525 for (j = 0; j < NPTE2_IN_PT2; j++) {
6526 va = base + (j << PAGE_SHIFT);
6527 if (va >= VM_MIN_KERNEL_ADDRESS) {
6532 sx_sunlock(&allproc_lock);
6535 pte2p = pmap_pte2(pmap, va);
6536 pte2 = pte2_load(pte2p);
6537 pmap_pte2_release(pte2p);
6538 if (!pte2_is_valid(pte2))
6542 m = PHYS_TO_VM_PAGE(pa);
6543 printf("va: 0x%x, pa: 0x%x, h: %d, w:"
6544 " %d, f: 0x%x", va, pa,
6545 m->hold_count, m->wire_count,
6559 sx_sunlock(&allproc_lock);
6566 static pt2_entry_t *
6567 pmap_pte2_ddb(pmap_t pmap, vm_offset_t va)
6570 vm_paddr_t pt2pg_pa;
6572 pte1 = pte1_load(pmap_pte1(pmap, va));
6573 if (!pte1_is_link(pte1))
6576 if (pmap_is_current(pmap))
6577 return (pt2map_entry(va));
6579 /* Note that L2 page table size is not equal to PAGE_SIZE. */
6580 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
6581 if (pte2_pa(pte2_load(PMAP3)) != pt2pg_pa) {
6582 pte2_store(PMAP3, PTE2_KPT(pt2pg_pa));
6584 PMAP3cpu = PCPU_GET(cpuid);
6586 tlb_flush_local((vm_offset_t)PADDR3);
6589 else if (PMAP3cpu != PCPU_GET(cpuid)) {
6590 PMAP3cpu = PCPU_GET(cpuid);
6591 tlb_flush_local((vm_offset_t)PADDR3);
6594 return (PADDR3 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
6598 dump_pmap(pmap_t pmap)
6601 printf("pmap %p\n", pmap);
6602 printf(" pm_pt1: %p\n", pmap->pm_pt1);
6603 printf(" pm_pt2tab: %p\n", pmap->pm_pt2tab);
6604 printf(" pm_active: 0x%08lX\n", pmap->pm_active.__bits[0]);
6607 DB_SHOW_COMMAND(pmaps, pmap_list_pmaps)
6611 LIST_FOREACH(pmap, &allpmaps, pm_list) {
6617 pte2_class(pt2_entry_t pte2)
6621 cls = (pte2 >> 2) & 0x03;
6622 cls |= (pte2 >> 4) & 0x04;
6627 dump_section(pmap_t pmap, uint32_t pte1_idx)
6632 dump_link(pmap_t pmap, uint32_t pte1_idx, boolean_t invalid_ok)
6636 pt2_entry_t *pte2p, pte2;
6639 va = pte1_idx << PTE1_SHIFT;
6640 pte2p = pmap_pte2_ddb(pmap, va);
6641 for (i = 0; i < NPTE2_IN_PT2; i++, pte2p++, va += PAGE_SIZE) {
6642 pte2 = pte2_load(pte2p);
6645 if (!pte2_is_valid(pte2)) {
6646 printf(" 0x%08X: 0x%08X", va, pte2);
6648 printf(" - not valid !!!");
6652 m = PHYS_TO_VM_PAGE(pte2_pa(pte2));
6653 printf(" 0x%08X: 0x%08X, TEX%d, s:%d, g:%d, m:%p", va , pte2,
6654 pte2_class(pte2), !!(pte2 & PTE2_S), !(pte2 & PTE2_NG), m);
6656 printf(" v:%d h:%d w:%d f:0x%04X\n", m->valid,
6657 m->hold_count, m->wire_count, m->flags);
6664 static __inline boolean_t
6665 is_pv_chunk_space(vm_offset_t va)
6668 if ((((vm_offset_t)pv_chunkbase) <= va) &&
6669 (va < ((vm_offset_t)pv_chunkbase + PAGE_SIZE * pv_maxchunks)))
6674 DB_SHOW_COMMAND(pmap, pmap_pmap_print)
6676 /* XXX convert args. */
6677 pmap_t pmap = (pmap_t)addr;
6680 vm_offset_t va, eva;
6683 boolean_t invalid_ok, dump_link_ok, dump_pv_chunk;
6688 LIST_FOREACH(pm, &allpmaps, pm_list)
6689 if (pm == pmap) break;
6691 printf("given pmap %p is not in allpmaps list\n", pmap);
6695 pmap = PCPU_GET(curpmap);
6697 eva = (modif[0] == 'u') ? VM_MAXUSER_ADDRESS : 0xFFFFFFFF;
6698 dump_pv_chunk = FALSE; /* XXX evaluate from modif[] */
6700 printf("pmap: 0x%08X\n", (uint32_t)pmap);
6701 printf("PT2MAP: 0x%08X\n", (uint32_t)PT2MAP);
6702 printf("pt2tab: 0x%08X\n", (uint32_t)pmap->pm_pt2tab);
6704 for(i = 0; i < NPTE1_IN_PT1; i++) {
6705 pte1 = pte1_load(&pmap->pm_pt1[i]);
6708 va = i << PTE1_SHIFT;
6712 if (pte1_is_section(pte1)) {
6713 printf("0x%08X: Section 0x%08X, s:%d g:%d\n", va, pte1,
6714 !!(pte1 & PTE1_S), !(pte1 & PTE1_NG));
6715 dump_section(pmap, i);
6716 } else if (pte1_is_link(pte1)) {
6717 dump_link_ok = TRUE;
6719 pte2 = pte2_load(pmap_pt2tab_entry(pmap, va));
6720 m = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
6721 printf("0x%08X: Link 0x%08X, pt2tab: 0x%08X m: %p",
6723 if (is_pv_chunk_space(va)) {
6724 printf(" - pv_chunk space");
6728 dump_link_ok = FALSE;
6731 printf(" w:%d w2:%u", m->wire_count,
6732 pt2_wirecount_get(m, pte1_index(va)));
6734 printf(" !!! pt2tab entry is ZERO");
6735 else if (pte2_pa(pte1) != pte2_pa(pte2))
6736 printf(" !!! pt2tab entry is DIFFERENT - m: %p",
6737 PHYS_TO_VM_PAGE(pte2_pa(pte2)));
6740 dump_link(pmap, i, invalid_ok);
6742 printf("0x%08X: Invalid entry 0x%08X\n", va, pte1);
6747 dump_pt2tab(pmap_t pmap)
6755 printf("PT2TAB:\n");
6756 for (i = 0; i < PT2TAB_ENTRIES; i++) {
6757 pte2 = pte2_load(&pmap->pm_pt2tab[i]);
6758 if (!pte2_is_valid(pte2))
6760 va = i << PT2TAB_SHIFT;
6762 m = PHYS_TO_VM_PAGE(pa);
6763 printf(" 0x%08X: 0x%08X, TEX%d, s:%d, m:%p", va, pte2,
6764 pte2_class(pte2), !!(pte2 & PTE2_S), m);
6766 printf(" , h: %d, w: %d, f: 0x%04X pidx: %lld",
6767 m->hold_count, m->wire_count, m->flags, m->pindex);
6772 DB_SHOW_COMMAND(pmap_pt2tab, pmap_pt2tab_print)
6774 /* XXX convert args. */
6775 pmap_t pmap = (pmap_t)addr;
6782 printf("supported only on current pmap\n");
6786 pmap = PCPU_GET(curpmap);
6787 printf("curpmap: 0x%08X\n", (uint32_t)pmap);
6788 printf("PT2MAP: 0x%08X\n", (uint32_t)PT2MAP);
6789 printf("pt2tab: 0x%08X\n", (uint32_t)pmap->pm_pt2tab);
6791 start = pte1_index((vm_offset_t)PT2MAP);
6792 for (i = start; i < (start + NPT2_IN_PT2TAB); i++) {
6793 pte1 = pte1_load(&pmap->pm_pt1[i]);
6796 va = i << PTE1_SHIFT;
6797 if (pte1_is_section(pte1)) {
6798 printf("0x%08X: Section 0x%08X, s:%d\n", va, pte1,
6800 dump_section(pmap, i);
6801 } else if (pte1_is_link(pte1)) {
6802 pte2 = pte2_load(pmap_pt2tab_entry(pmap, va));
6803 printf("0x%08X: Link 0x%08X, pt2tab: 0x%08X\n", va,
6806 printf(" !!! pt2tab entry is ZERO\n");
6808 printf("0x%08X: Invalid entry 0x%08X\n", va, pte1);