1 /* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */
3 * Copyright 2011 Semihalf
4 * Copyright 2004 Olivier Houchard.
5 * Copyright 2003 Wasabi Systems, Inc.
8 * Written by Steve C. Woodford for Wasabi Systems, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed for the NetBSD Project by
21 * Wasabi Systems, Inc.
22 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
23 * or promote products derived from this software without specific prior
26 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
38 * From: FreeBSD: src/sys/arm/arm/pmap.c,v 1.113 2009/07/24 13:50:29
42 * Copyright (c) 2002-2003 Wasabi Systems, Inc.
43 * Copyright (c) 2001 Richard Earnshaw
44 * Copyright (c) 2001-2002 Christopher Gilbert
45 * All rights reserved.
47 * 1. Redistributions of source code must retain the above copyright
48 * notice, this list of conditions and the following disclaimer.
49 * 2. Redistributions in binary form must reproduce the above copyright
50 * notice, this list of conditions and the following disclaimer in the
51 * documentation and/or other materials provided with the distribution.
52 * 3. The name of the company nor the name of the author may be used to
53 * endorse or promote products derived from this software without specific
54 * prior written permission.
56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
57 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
58 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
59 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
60 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
61 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
62 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
63 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
64 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
65 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
69 * Copyright (c) 1999 The NetBSD Foundation, Inc.
70 * All rights reserved.
72 * This code is derived from software contributed to The NetBSD Foundation
73 * by Charles M. Hannum.
75 * Redistribution and use in source and binary forms, with or without
76 * modification, are permitted provided that the following conditions
78 * 1. Redistributions of source code must retain the above copyright
79 * notice, this list of conditions and the following disclaimer.
80 * 2. Redistributions in binary form must reproduce the above copyright
81 * notice, this list of conditions and the following disclaimer in the
82 * documentation and/or other materials provided with the distribution.
84 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
85 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
86 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
87 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
88 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
89 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
90 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
91 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
92 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
93 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
94 * POSSIBILITY OF SUCH DAMAGE.
98 * Copyright (c) 1994-1998 Mark Brinicombe.
99 * Copyright (c) 1994 Brini.
100 * All rights reserved.
102 * This code is derived from software written for Brini by Mark Brinicombe
104 * Redistribution and use in source and binary forms, with or without
105 * modification, are permitted provided that the following conditions
107 * 1. Redistributions of source code must retain the above copyright
108 * notice, this list of conditions and the following disclaimer.
109 * 2. Redistributions in binary form must reproduce the above copyright
110 * notice, this list of conditions and the following disclaimer in the
111 * documentation and/or other materials provided with the distribution.
112 * 3. All advertising materials mentioning features or use of this software
113 * must display the following acknowledgement:
114 * This product includes software developed by Mark Brinicombe.
115 * 4. The name of the author may not be used to endorse or promote products
116 * derived from this software without specific prior written permission.
118 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
119 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
120 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
121 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
122 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
123 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
124 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
125 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
126 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
128 * RiscBSD kernel project
132 * Machine dependant vm stuff
138 * Special compilation symbols
139 * PMAP_DEBUG - Build in pmap_debug_level code
141 * Note that pmap_mapdev() and pmap_unmapdev() are implemented in arm/devmap.c
143 /* Include header files */
146 #include "opt_pmap.h"
148 #include <sys/cdefs.h>
149 __FBSDID("$FreeBSD$");
150 #include <sys/param.h>
151 #include <sys/systm.h>
152 #include <sys/kernel.h>
154 #include <sys/lock.h>
155 #include <sys/proc.h>
156 #include <sys/malloc.h>
157 #include <sys/msgbuf.h>
158 #include <sys/mutex.h>
159 #include <sys/vmmeter.h>
160 #include <sys/mman.h>
161 #include <sys/rwlock.h>
163 #include <sys/sched.h>
164 #include <sys/sysctl.h>
167 #include <vm/vm_param.h>
170 #include <vm/vm_kern.h>
171 #include <vm/vm_object.h>
172 #include <vm/vm_map.h>
173 #include <vm/vm_page.h>
174 #include <vm/vm_pageout.h>
175 #include <vm/vm_phys.h>
176 #include <vm/vm_extern.h>
177 #include <vm/vm_reserv.h>
179 #include <machine/md_var.h>
180 #include <machine/cpu.h>
181 #include <machine/cpufunc.h>
182 #include <machine/pcb.h>
185 extern int last_fault_code;
189 #define PDEBUG(_lev_,_stat_) \
190 if (pmap_debug_level >= (_lev_)) \
192 #define dprintf printf
194 int pmap_debug_level = 0;
196 #else /* PMAP_DEBUG */
197 #define PDEBUG(_lev_,_stat_) /* Nothing */
198 #define dprintf(x, arg...)
199 #define PMAP_INLINE __inline
200 #endif /* PMAP_DEBUG */
203 #define PV_STAT(x) do { x ; } while (0)
205 #define PV_STAT(x) do { } while (0)
208 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
211 #define pmap_l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range((pa), (size))
212 #define pmap_l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range((pa), (size))
214 #define pmap_l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range((va), (size))
215 #define pmap_l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range((va), (size))
218 extern struct pv_addr systempage;
221 * Internal function prototypes
225 struct pv_entry *pmap_find_pv(struct md_page *, pmap_t, vm_offset_t);
226 static void pmap_free_pv_chunk(struct pv_chunk *pc);
227 static void pmap_free_pv_entry(pmap_t pmap, pv_entry_t pv);
228 static pv_entry_t pmap_get_pv_entry(pmap_t pmap, boolean_t try);
229 static vm_page_t pmap_pv_reclaim(pmap_t locked_pmap);
230 static boolean_t pmap_pv_insert_section(pmap_t, vm_offset_t,
232 static struct pv_entry *pmap_remove_pv(struct vm_page *, pmap_t, vm_offset_t);
233 static int pmap_pvh_wired_mappings(struct md_page *, int);
235 static int pmap_enter_locked(pmap_t, vm_offset_t, vm_page_t,
237 static vm_paddr_t pmap_extract_locked(pmap_t pmap, vm_offset_t va);
238 static void pmap_alloc_l1(pmap_t);
239 static void pmap_free_l1(pmap_t);
241 static void pmap_map_section(pmap_t, vm_offset_t, vm_offset_t,
242 vm_prot_t, boolean_t);
243 static void pmap_promote_section(pmap_t, vm_offset_t);
244 static boolean_t pmap_demote_section(pmap_t, vm_offset_t);
245 static boolean_t pmap_enter_section(pmap_t, vm_offset_t, vm_page_t,
247 static void pmap_remove_section(pmap_t, vm_offset_t);
249 static int pmap_clearbit(struct vm_page *, u_int);
251 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t);
252 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t);
253 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int);
254 static vm_offset_t kernel_pt_lookup(vm_paddr_t);
256 static MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1");
258 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
259 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
260 vm_offset_t pmap_curmaxkvaddr;
261 vm_paddr_t kernel_l1pa;
263 vm_offset_t kernel_vm_end = 0;
265 vm_offset_t vm_max_kernel_address;
267 struct pmap kernel_pmap_store;
270 * Resources for quickly copying and zeroing pages using virtual address space
271 * and page table entries that are pre-allocated per-CPU by pmap_init().
280 static struct czpages cpu_czpages[MAXCPU];
282 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *);
284 * These routines are called when the CPU type is identified to set up
285 * the PTE prototypes, cache modes, etc.
287 * The variables are always here, just in case LKMs need to reference
288 * them (though, they shouldn't).
290 static void pmap_set_prot(pt_entry_t *pte, vm_prot_t prot, uint8_t user);
291 pt_entry_t pte_l1_s_cache_mode;
292 pt_entry_t pte_l1_s_cache_mode_pt;
294 pt_entry_t pte_l2_l_cache_mode;
295 pt_entry_t pte_l2_l_cache_mode_pt;
297 pt_entry_t pte_l2_s_cache_mode;
298 pt_entry_t pte_l2_s_cache_mode_pt;
300 struct msgbuf *msgbufp = 0;
305 static caddr_t crashdumpmap;
307 extern void bcopy_page(vm_offset_t, vm_offset_t);
308 extern void bzero_page(vm_offset_t);
313 * Metadata for L1 translation tables.
316 /* Entry on the L1 Table list */
317 SLIST_ENTRY(l1_ttable) l1_link;
319 /* Entry on the L1 Least Recently Used list */
320 TAILQ_ENTRY(l1_ttable) l1_lru;
322 /* Track how many domains are allocated from this L1 */
323 volatile u_int l1_domain_use_count;
326 * A free-list of domain numbers for this L1.
327 * We avoid using ffs() and a bitmap to track domains since ffs()
330 u_int8_t l1_domain_first;
331 u_int8_t l1_domain_free[PMAP_DOMAINS];
333 /* Physical address of this L1 page table */
334 vm_paddr_t l1_physaddr;
336 /* KVA of this L1 page table */
341 * Convert a virtual address into its L1 table index. That is, the
342 * index used to locate the L2 descriptor table pointer in an L1 table.
343 * This is basically used to index l1->l1_kva[].
345 * Each L2 descriptor table represents 1MB of VA space.
347 #define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT)
350 * L1 Page Tables are tracked using a Least Recently Used list.
351 * - New L1s are allocated from the HEAD.
352 * - Freed L1s are added to the TAIl.
353 * - Recently accessed L1s (where an 'access' is some change to one of
354 * the userland pmaps which owns this L1) are moved to the TAIL.
356 static TAILQ_HEAD(, l1_ttable) l1_lru_list;
358 * A list of all L1 tables
360 static SLIST_HEAD(, l1_ttable) l1_list;
361 static struct mtx l1_lru_lock;
364 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots.
366 * This is normally 16MB worth L2 page descriptors for any given pmap.
367 * Reference counts are maintained for L2 descriptors so they can be
371 /* The number of L2 page descriptors allocated to this l2_dtable */
374 /* List of L2 page descriptors */
376 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */
377 vm_paddr_t l2b_phys; /* Physical address of same */
378 u_short l2b_l1idx; /* This L2 table's L1 index */
379 u_short l2b_occupancy; /* How many active descriptors */
380 } l2_bucket[L2_BUCKET_SIZE];
383 /* pmap_kenter_internal flags */
384 #define KENTER_CACHE 0x1
385 #define KENTER_DEVICE 0x2
386 #define KENTER_USER 0x4
389 * Given an L1 table index, calculate the corresponding l2_dtable index
390 * and bucket index within the l2_dtable.
392 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \
394 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1))
397 * Given a virtual address, this macro returns the
398 * virtual address required to drop into the next L2 bucket.
400 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE)
403 * We try to map the page tables write-through, if possible. However, not
404 * all CPUs have a write-through cache mode, so on those we have to sync
405 * the cache when we frob page tables.
407 * We try to evaluate this at compile time, if possible. However, it's
408 * not always possible to do that, hence this run-time var.
410 int pmap_needs_pte_sync;
413 * Macro to determine if a mapping might be resident in the
414 * instruction cache and/or TLB
416 #define PTE_BEEN_EXECD(pte) (L2_S_EXECUTABLE(pte) && L2_S_REFERENCED(pte))
419 * Macro to determine if a mapping might be resident in the
420 * data cache and/or TLB
422 #define PTE_BEEN_REFD(pte) (L2_S_REFERENCED(pte))
424 #ifndef PMAP_SHPGPERPROC
425 #define PMAP_SHPGPERPROC 200
428 #define pmap_is_current(pm) ((pm) == pmap_kernel() || \
429 curproc->p_vmspace->vm_map.pmap == (pm))
432 * Data for the pv entry allocation mechanism
434 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
435 static int pv_entry_count, pv_entry_max, pv_entry_high_water;
436 static struct md_page *pv_table;
437 static int shpgperproc = PMAP_SHPGPERPROC;
439 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
440 int pv_maxchunks; /* How many chunks we have KVA for */
441 vm_offset_t pv_vafree; /* Freelist stored in the PTE */
443 static __inline struct pv_chunk *
444 pv_to_chunk(pv_entry_t pv)
447 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
450 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
452 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
453 CTASSERT(_NPCM == 8);
454 CTASSERT(_NPCPV == 252);
456 #define PC_FREE0_6 0xfffffffful /* Free values for index 0 through 6 */
457 #define PC_FREE7 0x0ffffffful /* Free values for index 7 */
459 static const uint32_t pc_freemask[_NPCM] = {
460 PC_FREE0_6, PC_FREE0_6, PC_FREE0_6,
461 PC_FREE0_6, PC_FREE0_6, PC_FREE0_6,
465 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
467 /* Superpages utilization enabled = 1 / disabled = 0 */
468 static int sp_enabled = 1;
469 SYSCTL_INT(_vm_pmap, OID_AUTO, sp_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &sp_enabled, 0,
470 "Are large page mappings enabled?");
472 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
473 "Current number of pv entries");
476 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
478 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
479 "Current number of pv entry chunks");
480 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
481 "Current number of pv entry chunks allocated");
482 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
483 "Current number of pv entry chunks frees");
484 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
485 "Number of times tried to get a chunk page but failed.");
487 static long pv_entry_frees, pv_entry_allocs;
488 static int pv_entry_spare;
490 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
491 "Current number of pv entry frees");
492 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
493 "Current number of pv entry allocs");
494 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
495 "Current number of spare pv entries");
499 static uma_zone_t l2table_zone;
500 static vm_offset_t pmap_kernel_l2dtable_kva;
501 static vm_offset_t pmap_kernel_l2ptp_kva;
502 static vm_paddr_t pmap_kernel_l2ptp_phys;
503 static struct rwlock pvh_global_lock;
505 int l1_mem_types[] = {
507 ARM_L1S_DEVICE_NOSHARE,
508 ARM_L1S_DEVICE_SHARE,
509 ARM_L1S_NRML_NOCACHE,
510 ARM_L1S_NRML_IWT_OWT,
511 ARM_L1S_NRML_IWB_OWB,
512 ARM_L1S_NRML_IWBA_OWBA
515 int l2l_mem_types[] = {
517 ARM_L2L_DEVICE_NOSHARE,
518 ARM_L2L_DEVICE_SHARE,
519 ARM_L2L_NRML_NOCACHE,
520 ARM_L2L_NRML_IWT_OWT,
521 ARM_L2L_NRML_IWB_OWB,
522 ARM_L2L_NRML_IWBA_OWBA
525 int l2s_mem_types[] = {
527 ARM_L2S_DEVICE_NOSHARE,
528 ARM_L2S_DEVICE_SHARE,
529 ARM_L2S_NRML_NOCACHE,
530 ARM_L2S_NRML_IWT_OWT,
531 ARM_L2S_NRML_IWB_OWB,
532 ARM_L2S_NRML_IWBA_OWBA
536 * This list exists for the benefit of pmap_map_chunk(). It keeps track
537 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can
538 * find them as necessary.
540 * Note that the data on this list MUST remain valid after initarm() returns,
541 * as pmap_bootstrap() uses it to contruct L2 table metadata.
543 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list);
546 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt)
551 l1->l1_domain_use_count = 0;
552 l1->l1_domain_first = 0;
554 for (i = 0; i < PMAP_DOMAINS; i++)
555 l1->l1_domain_free[i] = i + 1;
558 * Copy the kernel's L1 entries to each new L1.
560 if (l1pt != pmap_kernel()->pm_l1->l1_kva)
561 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE);
563 if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0)
564 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt);
565 SLIST_INSERT_HEAD(&l1_list, l1, l1_link);
566 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
570 kernel_pt_lookup(vm_paddr_t pa)
574 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) {
582 pmap_pte_init_mmu_v6(void)
585 if (PTE_PAGETABLE >= 3)
586 pmap_needs_pte_sync = 1;
587 pte_l1_s_cache_mode = l1_mem_types[PTE_CACHE];
588 pte_l2_l_cache_mode = l2l_mem_types[PTE_CACHE];
589 pte_l2_s_cache_mode = l2s_mem_types[PTE_CACHE];
591 pte_l1_s_cache_mode_pt = l1_mem_types[PTE_PAGETABLE];
592 pte_l2_l_cache_mode_pt = l2l_mem_types[PTE_PAGETABLE];
593 pte_l2_s_cache_mode_pt = l2s_mem_types[PTE_PAGETABLE];
598 * Allocate an L1 translation table for the specified pmap.
599 * This is called at pmap creation time.
602 pmap_alloc_l1(pmap_t pmap)
604 struct l1_ttable *l1;
608 * Remove the L1 at the head of the LRU list
610 mtx_lock(&l1_lru_lock);
611 l1 = TAILQ_FIRST(&l1_lru_list);
612 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
615 * Pick the first available domain number, and update
616 * the link to the next number.
618 domain = l1->l1_domain_first;
619 l1->l1_domain_first = l1->l1_domain_free[domain];
622 * If there are still free domain numbers in this L1,
623 * put it back on the TAIL of the LRU list.
625 if (++l1->l1_domain_use_count < PMAP_DOMAINS)
626 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
628 mtx_unlock(&l1_lru_lock);
631 * Fix up the relevant bits in the pmap structure
634 pmap->pm_domain = domain + 1;
638 * Free an L1 translation table.
639 * This is called at pmap destruction time.
642 pmap_free_l1(pmap_t pmap)
644 struct l1_ttable *l1 = pmap->pm_l1;
646 mtx_lock(&l1_lru_lock);
649 * If this L1 is currently on the LRU list, remove it.
651 if (l1->l1_domain_use_count < PMAP_DOMAINS)
652 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
655 * Free up the domain number which was allocated to the pmap
657 l1->l1_domain_free[pmap->pm_domain - 1] = l1->l1_domain_first;
658 l1->l1_domain_first = pmap->pm_domain - 1;
659 l1->l1_domain_use_count--;
662 * The L1 now must have at least 1 free domain, so add
663 * it back to the LRU list. If the use count is zero,
664 * put it at the head of the list, otherwise it goes
667 if (l1->l1_domain_use_count == 0) {
668 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru);
670 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
672 mtx_unlock(&l1_lru_lock);
676 * Returns a pointer to the L2 bucket associated with the specified pmap
677 * and VA, or NULL if no L2 bucket exists for the address.
679 static PMAP_INLINE struct l2_bucket *
680 pmap_get_l2_bucket(pmap_t pmap, vm_offset_t va)
682 struct l2_dtable *l2;
683 struct l2_bucket *l2b;
688 if ((l2 = pmap->pm_l2[L2_IDX(l1idx)]) == NULL ||
689 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL)
696 * Returns a pointer to the L2 bucket associated with the specified pmap
699 * If no L2 bucket exists, perform the necessary allocations to put an L2
700 * bucket/page table in place.
702 * Note that if a new L2 bucket/page was allocated, the caller *must*
703 * increment the bucket occupancy counter appropriately *before*
704 * releasing the pmap's lock to ensure no other thread or cpu deallocates
705 * the bucket/page in the meantime.
707 static struct l2_bucket *
708 pmap_alloc_l2_bucket(pmap_t pmap, vm_offset_t va)
710 struct l2_dtable *l2;
711 struct l2_bucket *l2b;
716 PMAP_ASSERT_LOCKED(pmap);
717 rw_assert(&pvh_global_lock, RA_WLOCKED);
718 if ((l2 = pmap->pm_l2[L2_IDX(l1idx)]) == NULL) {
720 * No mapping at this address, as there is
721 * no entry in the L1 table.
722 * Need to allocate a new l2_dtable.
725 rw_wunlock(&pvh_global_lock);
726 if ((l2 = uma_zalloc(l2table_zone, M_NOWAIT)) == NULL) {
727 rw_wlock(&pvh_global_lock);
731 rw_wlock(&pvh_global_lock);
733 if (pmap->pm_l2[L2_IDX(l1idx)] != NULL) {
735 * Someone already allocated the l2_dtable while
736 * we were doing the same.
738 uma_zfree(l2table_zone, l2);
739 l2 = pmap->pm_l2[L2_IDX(l1idx)];
741 bzero(l2, sizeof(*l2));
743 * Link it into the parent pmap
745 pmap->pm_l2[L2_IDX(l1idx)] = l2;
749 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
752 * Fetch pointer to the L2 page table associated with the address.
754 if (l2b->l2b_kva == NULL) {
758 * No L2 page table has been allocated. Chances are, this
759 * is because we just allocated the l2_dtable, above.
763 rw_wunlock(&pvh_global_lock);
764 ptep = uma_zalloc(l2zone, M_NOWAIT);
765 rw_wlock(&pvh_global_lock);
767 if (l2b->l2b_kva != 0) {
768 /* We lost the race. */
770 uma_zfree(l2zone, ptep);
773 l2b->l2b_phys = vtophys(ptep);
776 * Oops, no more L2 page tables available at this
777 * time. We may need to deallocate the l2_dtable
778 * if we allocated a new one above.
781 if (l2->l2_occupancy == 0) {
782 pmap->pm_l2[L2_IDX(l1idx)] = NULL;
783 uma_zfree(l2table_zone, l2);
789 l2b->l2b_l1idx = l1idx;
795 static PMAP_INLINE void
796 pmap_free_l2_ptp(pt_entry_t *l2)
798 uma_zfree(l2zone, l2);
801 * One or more mappings in the specified L2 descriptor table have just been
804 * Garbage collect the metadata and descriptor table itself if necessary.
806 * The pmap lock must be acquired when this is called (not necessary
807 * for the kernel pmap).
810 pmap_free_l2_bucket(pmap_t pmap, struct l2_bucket *l2b, u_int count)
812 struct l2_dtable *l2;
813 pd_entry_t *pl1pd, l1pd;
819 * Update the bucket's reference count according to how many
820 * PTEs the caller has just invalidated.
822 l2b->l2b_occupancy -= count;
827 * Level 2 page tables allocated to the kernel pmap are never freed
828 * as that would require checking all Level 1 page tables and
829 * removing any references to the Level 2 page table. See also the
830 * comment elsewhere about never freeing bootstrap L2 descriptors.
832 * We make do with just invalidating the mapping in the L2 table.
834 * This isn't really a big deal in practice and, in fact, leads
835 * to a performance win over time as we don't need to continually
838 if (l2b->l2b_occupancy > 0 || pmap == pmap_kernel())
842 * There are no more valid mappings in this level 2 page table.
843 * Go ahead and NULL-out the pointer in the bucket, then
844 * free the page table.
846 l1idx = l2b->l2b_l1idx;
850 pl1pd = &pmap->pm_l1->l1_kva[l1idx];
853 * If the L1 slot matches the pmap's domain
854 * number, then invalidate it.
856 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK);
857 if (l1pd == (L1_C_DOM(pmap->pm_domain) | L1_TYPE_C)) {
860 cpu_tlb_flushD_SE((vm_offset_t)ptep);
865 * Release the L2 descriptor table back to the pool cache.
867 pmap_free_l2_ptp(ptep);
870 * Update the reference count in the associated l2_dtable
872 l2 = pmap->pm_l2[L2_IDX(l1idx)];
873 if (--l2->l2_occupancy > 0)
877 * There are no more valid mappings in any of the Level 1
878 * slots managed by this l2_dtable. Go ahead and NULL-out
879 * the pointer in the parent pmap and free the l2_dtable.
881 pmap->pm_l2[L2_IDX(l1idx)] = NULL;
882 uma_zfree(l2table_zone, l2);
886 * Pool cache constructors for L2 descriptor tables, metadata and pmap
890 pmap_l2ptp_ctor(void *mem, int size, void *arg, int flags)
892 struct l2_bucket *l2b;
893 pt_entry_t *ptep, pte;
894 vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK;
897 * The mappings for these page tables were initially made using
898 * pmap_kenter() by the pool subsystem. Therefore, the cache-
899 * mode will not be right for page table mappings. To avoid
900 * polluting the pmap_kenter() code with a special case for
901 * page tables, we simply fix up the cache-mode here if it's not
904 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
905 ptep = &l2b->l2b_kva[l2pte_index(va)];
908 cpu_idcache_wbinv_range(va, PAGE_SIZE);
909 pmap_l2cache_wbinv_range(va, pte & L2_S_FRAME, PAGE_SIZE);
910 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
912 * Page tables must have the cache-mode set to
915 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
917 cpu_tlb_flushD_SE(va);
921 memset(mem, 0, L2_TABLE_SIZE_REAL);
926 * Modify pte bits for all ptes corresponding to the given physical address.
927 * We use `maskbits' rather than `clearbits' because we're always passing
928 * constants and the latter would require an extra inversion at run-time.
931 pmap_clearbit(struct vm_page *m, u_int maskbits)
933 struct l2_bucket *l2b;
934 struct pv_entry *pv, *pve, *next_pv;
937 pt_entry_t *ptep, npte, opte;
943 rw_wlock(&pvh_global_lock);
944 if ((m->flags & PG_FICTITIOUS) != 0)
947 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
948 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
952 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
953 KASSERT((*pl1pd & L1_TYPE_MASK) == L1_S_PROTO,
954 ("pmap_clearbit: valid section mapping expected"));
955 if ((maskbits & PVF_WRITE) && (pv->pv_flags & PVF_WRITE))
956 (void)pmap_demote_section(pmap, va);
957 else if ((maskbits & PVF_REF) && L1_S_REFERENCED(*pl1pd)) {
958 if (pmap_demote_section(pmap, va)) {
959 if ((pv->pv_flags & PVF_WIRED) == 0) {
961 * Remove the mapping to a single page
962 * so that a subsequent access may
963 * repromote. Since the underlying
964 * l2_bucket is fully populated, this
965 * removal never frees an entire
968 va += (VM_PAGE_TO_PHYS(m) &
970 l2b = pmap_get_l2_bucket(pmap, va);
972 ("pmap_clearbit: no l2 bucket for "
973 "va 0x%#x, pmap 0x%p", va, pmap));
974 ptep = &l2b->l2b_kva[l2pte_index(va)];
977 pmap_free_l2_bucket(pmap, l2b, 1);
978 pve = pmap_remove_pv(m, pmap, va);
979 KASSERT(pve != NULL, ("pmap_clearbit: "
980 "no PV entry for managed mapping"));
981 pmap_free_pv_entry(pmap, pve);
985 } else if ((maskbits & PVF_MOD) && L1_S_WRITABLE(*pl1pd)) {
986 if (pmap_demote_section(pmap, va)) {
987 if ((pv->pv_flags & PVF_WIRED) == 0) {
989 * Write protect the mapping to a
990 * single page so that a subsequent
991 * write access may repromote.
993 va += (VM_PAGE_TO_PHYS(m) &
995 l2b = pmap_get_l2_bucket(pmap, va);
997 ("pmap_clearbit: no l2 bucket for "
998 "va 0x%#x, pmap 0x%p", va, pmap));
999 ptep = &l2b->l2b_kva[l2pte_index(va)];
1000 if ((*ptep & L2_S_PROTO) != 0) {
1001 pve = pmap_find_pv(&m->md,
1003 KASSERT(pve != NULL,
1004 ("pmap_clearbit: no PV "
1005 "entry for managed mapping"));
1006 pve->pv_flags &= ~PVF_WRITE;
1017 if (TAILQ_EMPTY(&m->md.pv_list)) {
1018 rw_wunlock(&pvh_global_lock);
1023 * Loop over all current mappings setting/clearing as appropos
1025 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
1028 oflags = pv->pv_flags;
1029 pv->pv_flags &= ~maskbits;
1033 l2b = pmap_get_l2_bucket(pmap, va);
1034 KASSERT(l2b != NULL, ("pmap_clearbit: no l2 bucket for "
1035 "va 0x%#x, pmap 0x%p", va, pmap));
1037 ptep = &l2b->l2b_kva[l2pte_index(va)];
1038 npte = opte = *ptep;
1040 if (maskbits & (PVF_WRITE | PVF_MOD)) {
1041 /* make the pte read only */
1045 if (maskbits & PVF_REF) {
1047 * Clear referenced flag in PTE so that we
1048 * will take a flag fault the next time the mapping
1054 CTR4(KTR_PMAP,"clearbit: pmap:%p bits:%x pte:%x->%x",
1055 pmap, maskbits, opte, npte);
1060 /* Flush the TLB entry if a current pmap. */
1061 if (PTE_BEEN_EXECD(opte))
1062 cpu_tlb_flushID_SE(pv->pv_va);
1063 else if (PTE_BEEN_REFD(opte))
1064 cpu_tlb_flushD_SE(pv->pv_va);
1072 if (maskbits & PVF_WRITE)
1073 vm_page_aflag_clear(m, PGA_WRITEABLE);
1074 rw_wunlock(&pvh_global_lock);
1079 * main pv_entry manipulation functions:
1080 * pmap_enter_pv: enter a mapping onto a vm_page list
1081 * pmap_remove_pv: remove a mappiing from a vm_page list
1083 * NOTE: pmap_enter_pv expects to lock the pvh itself
1084 * pmap_remove_pv expects the caller to lock the pvh before calling
1088 * pmap_enter_pv: enter a mapping onto a vm_page's PV list
1090 * => caller should hold the proper lock on pvh_global_lock
1091 * => caller should have pmap locked
1092 * => we will (someday) gain the lock on the vm_page's PV list
1093 * => caller should adjust ptp's wire_count before calling
1094 * => caller should not adjust pmap's wire_count
1097 pmap_enter_pv(struct vm_page *m, struct pv_entry *pve, pmap_t pmap,
1098 vm_offset_t va, u_int flags)
1101 rw_assert(&pvh_global_lock, RA_WLOCKED);
1103 PMAP_ASSERT_LOCKED(pmap);
1105 pve->pv_flags = flags;
1107 TAILQ_INSERT_HEAD(&m->md.pv_list, pve, pv_list);
1108 if (pve->pv_flags & PVF_WIRED)
1109 ++pmap->pm_stats.wired_count;
1114 * pmap_find_pv: Find a pv entry
1116 * => caller should hold lock on vm_page
1118 static PMAP_INLINE struct pv_entry *
1119 pmap_find_pv(struct md_page *md, pmap_t pmap, vm_offset_t va)
1121 struct pv_entry *pv;
1123 rw_assert(&pvh_global_lock, RA_WLOCKED);
1124 TAILQ_FOREACH(pv, &md->pv_list, pv_list)
1125 if (pmap == PV_PMAP(pv) && va == pv->pv_va)
1132 * vector_page_setprot:
1134 * Manipulate the protection of the vector page.
1137 vector_page_setprot(int prot)
1139 struct l2_bucket *l2b;
1142 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page);
1144 ptep = &l2b->l2b_kva[l2pte_index(vector_page)];
1146 * Set referenced flag.
1147 * Vectors' page is always desired
1148 * to be allowed to reside in TLB.
1152 pmap_set_prot(ptep, prot|VM_PROT_EXECUTE, 0);
1154 cpu_tlb_flushID_SE(vector_page);
1159 pmap_set_prot(pt_entry_t *ptep, vm_prot_t prot, uint8_t user)
1162 *ptep &= ~(L2_S_PROT_MASK | L2_XN);
1164 if (!(prot & VM_PROT_EXECUTE))
1167 /* Set defaults first - kernel read access */
1169 *ptep |= L2_S_PROT_R;
1170 /* Now tune APs as desired */
1172 *ptep |= L2_S_PROT_U;
1174 if (prot & VM_PROT_WRITE)
1179 * pmap_remove_pv: try to remove a mapping from a pv_list
1181 * => caller should hold proper lock on pmap_main_lock
1182 * => pmap should be locked
1183 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1184 * => caller should adjust ptp's wire_count and free PTP if needed
1185 * => caller should NOT adjust pmap's wire_count
1186 * => we return the removed pve
1188 static struct pv_entry *
1189 pmap_remove_pv(struct vm_page *m, pmap_t pmap, vm_offset_t va)
1191 struct pv_entry *pve;
1193 rw_assert(&pvh_global_lock, RA_WLOCKED);
1194 PMAP_ASSERT_LOCKED(pmap);
1196 pve = pmap_find_pv(&m->md, pmap, va); /* find corresponding pve */
1198 TAILQ_REMOVE(&m->md.pv_list, pve, pv_list);
1199 if (pve->pv_flags & PVF_WIRED)
1200 --pmap->pm_stats.wired_count;
1202 if (TAILQ_EMPTY(&m->md.pv_list))
1203 vm_page_aflag_clear(m, PGA_WRITEABLE);
1205 return(pve); /* return removed pve */
1210 * pmap_modify_pv: Update pv flags
1212 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1213 * => caller should NOT adjust pmap's wire_count
1214 * => we return the old flags
1216 * Modify a physical-virtual mapping in the pv table
1219 pmap_modify_pv(struct vm_page *m, pmap_t pmap, vm_offset_t va,
1220 u_int clr_mask, u_int set_mask)
1222 struct pv_entry *npv;
1223 u_int flags, oflags;
1225 PMAP_ASSERT_LOCKED(pmap);
1226 rw_assert(&pvh_global_lock, RA_WLOCKED);
1227 if ((npv = pmap_find_pv(&m->md, pmap, va)) == NULL)
1231 * There is at least one VA mapping this page.
1233 oflags = npv->pv_flags;
1234 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask;
1236 if ((flags ^ oflags) & PVF_WIRED) {
1237 if (flags & PVF_WIRED)
1238 ++pmap->pm_stats.wired_count;
1240 --pmap->pm_stats.wired_count;
1246 /* Function to set the debug level of the pmap code */
1249 pmap_debug(int level)
1251 pmap_debug_level = level;
1252 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
1254 #endif /* PMAP_DEBUG */
1257 pmap_pinit0(struct pmap *pmap)
1259 PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap));
1261 bcopy(kernel_pmap, pmap, sizeof(*pmap));
1262 bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx));
1263 PMAP_LOCK_INIT(pmap);
1264 TAILQ_INIT(&pmap->pm_pvchunk);
1268 * Initialize a vm_page's machine-dependent fields.
1271 pmap_page_init(vm_page_t m)
1274 TAILQ_INIT(&m->md.pv_list);
1275 m->md.pv_memattr = VM_MEMATTR_DEFAULT;
1279 pmap_ptelist_alloc(vm_offset_t *head)
1286 return (va); /* Out of memory */
1289 if ((*head & L2_TYPE_MASK) != L2_TYPE_INV)
1290 panic("%s: va is not L2_TYPE_INV!", __func__);
1296 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
1300 if ((va & L2_TYPE_MASK) != L2_TYPE_INV)
1301 panic("%s: freeing va that is not L2_TYPE INV!", __func__);
1303 *pte = *head; /* virtual! L2_TYPE is L2_TYPE_INV though */
1308 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
1314 for (i = npages - 1; i >= 0; i--) {
1315 va = (vm_offset_t)base + i * PAGE_SIZE;
1316 pmap_ptelist_free(head, va);
1321 * Initialize the pmap module.
1322 * Called by vm_init, to initialize any structures that the pmap
1323 * system needs to map virtual memory.
1331 l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor,
1332 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1333 l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable), NULL,
1334 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1337 * Are large page mappings supported and enabled?
1339 TUNABLE_INT_FETCH("vm.pmap.sp_enabled", &sp_enabled);
1341 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1342 ("pmap_init: can't assign to pagesizes[1]"));
1343 pagesizes[1] = NBPDR;
1347 * Calculate the size of the pv head table for superpages.
1348 * Handle the possibility that "vm_phys_segs[...].end" is zero.
1350 pv_npg = trunc_1mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
1351 PAGE_SIZE) / NBPDR + 1;
1354 * Allocate memory for the pv head table for superpages.
1356 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1358 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
1360 for (i = 0; i < pv_npg; i++)
1361 TAILQ_INIT(&pv_table[i].pv_list);
1364 * Initialize the address space for the pv chunks.
1367 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1368 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1369 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1370 pv_entry_max = roundup(pv_entry_max, _NPCPV);
1371 pv_entry_high_water = 9 * (pv_entry_max / 10);
1373 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
1374 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
1376 if (pv_chunkbase == NULL)
1377 panic("pmap_init: not enough kvm for pv chunks");
1379 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
1382 * Now it is safe to enable pv_table recording.
1384 PDEBUG(1, printf("pmap_init: done!\n"));
1387 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
1388 "Max number of PV entries");
1389 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
1390 "Page share factor per proc");
1392 static SYSCTL_NODE(_vm_pmap, OID_AUTO, section, CTLFLAG_RD, 0,
1393 "1MB page mapping counters");
1395 static u_long pmap_section_demotions;
1396 SYSCTL_ULONG(_vm_pmap_section, OID_AUTO, demotions, CTLFLAG_RD,
1397 &pmap_section_demotions, 0, "1MB page demotions");
1399 static u_long pmap_section_mappings;
1400 SYSCTL_ULONG(_vm_pmap_section, OID_AUTO, mappings, CTLFLAG_RD,
1401 &pmap_section_mappings, 0, "1MB page mappings");
1403 static u_long pmap_section_p_failures;
1404 SYSCTL_ULONG(_vm_pmap_section, OID_AUTO, p_failures, CTLFLAG_RD,
1405 &pmap_section_p_failures, 0, "1MB page promotion failures");
1407 static u_long pmap_section_promotions;
1408 SYSCTL_ULONG(_vm_pmap_section, OID_AUTO, promotions, CTLFLAG_RD,
1409 &pmap_section_promotions, 0, "1MB page promotions");
1412 pmap_fault_fixup(pmap_t pmap, vm_offset_t va, vm_prot_t ftype, int user)
1414 struct l2_dtable *l2;
1415 struct l2_bucket *l2b;
1416 pd_entry_t *pl1pd, l1pd;
1417 pt_entry_t *ptep, pte;
1423 rw_wlock(&pvh_global_lock);
1426 * Check and possibly fix-up L1 section mapping
1427 * only when superpage mappings are enabled to speed up.
1430 pl1pd = &pmap->pm_l1->l1_kva[l1idx];
1432 if ((l1pd & L1_TYPE_MASK) == L1_S_PROTO) {
1433 /* Catch an access to the vectors section */
1434 if (l1idx == L1_IDX(vector_page))
1437 * Stay away from the kernel mappings.
1438 * None of them should fault from L1 entry.
1440 if (pmap == pmap_kernel())
1443 * Catch a forbidden userland access
1445 if (user && !(l1pd & L1_S_PROT_U))
1448 * Superpage is always either mapped read only
1449 * or it is modified and permitted to be written
1450 * by default. Therefore, process only reference
1451 * flag fault and demote page in case of write fault.
1453 if ((ftype & VM_PROT_WRITE) && !L1_S_WRITABLE(l1pd) &&
1454 L1_S_REFERENCED(l1pd)) {
1455 (void)pmap_demote_section(pmap, va);
1457 } else if (!L1_S_REFERENCED(l1pd)) {
1458 /* Mark the page "referenced" */
1459 *pl1pd = l1pd | L1_S_REF;
1461 goto l1_section_out;
1467 * If there is no l2_dtable for this address, then the process
1468 * has no business accessing it.
1470 * Note: This will catch userland processes trying to access
1473 l2 = pmap->pm_l2[L2_IDX(l1idx)];
1478 * Likewise if there is no L2 descriptor table
1480 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
1481 if (l2b->l2b_kva == NULL)
1485 * Check the PTE itself.
1487 ptep = &l2b->l2b_kva[l2pte_index(va)];
1493 * Catch a userland access to the vector page mapped at 0x0
1495 if (user && !(pte & L2_S_PROT_U))
1497 if (va == vector_page)
1501 CTR5(KTR_PMAP, "pmap_fault_fix: pmap:%p va:%x pte:0x%x ftype:%x user:%x",
1502 pmap, va, pte, ftype, user);
1503 if ((ftype & VM_PROT_WRITE) && !(L2_S_WRITABLE(pte)) &&
1504 L2_S_REFERENCED(pte)) {
1506 * This looks like a good candidate for "page modified"
1509 struct pv_entry *pv;
1512 /* Extract the physical address of the page */
1513 if ((m = PHYS_TO_VM_PAGE(pa)) == NULL) {
1516 /* Get the current flags for this page. */
1518 pv = pmap_find_pv(&m->md, pmap, va);
1524 * Do the flags say this page is writable? If not then it
1525 * is a genuine write fault. If yes then the write fault is
1526 * our fault as we did not reflect the write access in the
1527 * PTE. Now we know a write has occurred we can correct this
1528 * and also set the modified bit
1530 if ((pv->pv_flags & PVF_WRITE) == 0) {
1536 /* Re-enable write permissions for the page */
1537 *ptep = (pte & ~L2_APX);
1540 CTR1(KTR_PMAP, "pmap_fault_fix: new pte:0x%x", *ptep);
1541 } else if (!L2_S_REFERENCED(pte)) {
1543 * This looks like a good candidate for "page referenced"
1546 struct pv_entry *pv;
1549 /* Extract the physical address of the page */
1550 if ((m = PHYS_TO_VM_PAGE(pa)) == NULL)
1552 /* Get the current flags for this page. */
1553 pv = pmap_find_pv(&m->md, pmap, va);
1557 vm_page_aflag_set(m, PGA_REFERENCED);
1559 /* Mark the page "referenced" */
1560 *ptep = pte | L2_S_REF;
1563 CTR1(KTR_PMAP, "pmap_fault_fix: new pte:0x%x", *ptep);
1567 * We know there is a valid mapping here, so simply
1568 * fix up the L1 if necessary.
1570 pl1pd = &pmap->pm_l1->l1_kva[l1idx];
1571 l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) | L1_C_PROTO;
1572 if (*pl1pd != l1pd) {
1580 * If 'rv == 0' at this point, it generally indicates that there is a
1581 * stale TLB entry for the faulting address. This happens when two or
1582 * more processes are sharing an L1. Since we don't flush the TLB on
1583 * a context switch between such processes, we can take domain faults
1584 * for mappings which exist at the same VA in both processes. EVEN IF
1585 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for
1588 * This is extremely likely to happen if pmap_enter() updated the L1
1589 * entry for a recently entered mapping. In this case, the TLB is
1590 * flushed for the new mapping, but there may still be TLB entries for
1591 * other mappings belonging to other processes in the 1MB range
1592 * covered by the L1 entry.
1594 * Since 'rv == 0', we know that the L1 already contains the correct
1595 * value, so the fault must be due to a stale TLB entry.
1597 * Since we always need to flush the TLB anyway in the case where we
1598 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with
1599 * stale TLB entries dynamically.
1601 * However, the above condition can ONLY happen if the current L1 is
1602 * being shared. If it happens when the L1 is unshared, it indicates
1603 * that other parts of the pmap are not doing their job WRT managing
1606 if (rv == 0 && pmap->pm_l1->l1_domain_use_count == 1) {
1607 printf("fixup: pmap %p, va 0x%08x, ftype %d - nothing to do!\n",
1609 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n",
1610 l2, l2b, ptep, pl1pd);
1611 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n",
1612 pte, l1pd, last_fault_code);
1620 cpu_tlb_flushID_SE(va);
1626 rw_wunlock(&pvh_global_lock);
1634 struct l2_bucket *l2b;
1635 struct l1_ttable *l1;
1637 pt_entry_t *ptep, pte;
1638 vm_offset_t va, eva;
1641 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0);
1643 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK);
1645 for (loop = 0; loop < needed; loop++, l1++) {
1646 /* Allocate a L1 page table */
1647 va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0,
1648 0xffffffff, L1_TABLE_SIZE, 0);
1651 panic("Cannot allocate L1 KVM");
1653 eva = va + L1_TABLE_SIZE;
1654 pl1pt = (pd_entry_t *)va;
1657 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
1658 ptep = &l2b->l2b_kva[l2pte_index(va)];
1660 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
1663 cpu_tlb_flushID_SE(va);
1667 pmap_init_l1(l1, pl1pt);
1670 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n",
1676 * This is used to stuff certain critical values into the PCB where they
1677 * can be accessed quickly from cpu_switch() et al.
1680 pmap_set_pcb_pagedir(pmap_t pmap, struct pcb *pcb)
1682 struct l2_bucket *l2b;
1684 pcb->pcb_pagedir = pmap->pm_l1->l1_physaddr;
1685 pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) |
1686 (DOMAIN_CLIENT << (pmap->pm_domain * 2));
1688 if (vector_page < KERNBASE) {
1689 pcb->pcb_pl1vec = &pmap->pm_l1->l1_kva[L1_IDX(vector_page)];
1690 l2b = pmap_get_l2_bucket(pmap, vector_page);
1691 pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO |
1692 L1_C_DOM(pmap->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL);
1694 pcb->pcb_pl1vec = NULL;
1698 pmap_activate(struct thread *td)
1703 pmap = vmspace_pmap(td->td_proc->p_vmspace);
1707 pmap_set_pcb_pagedir(pmap, pcb);
1709 if (td == curthread) {
1710 u_int cur_dacr, cur_ttb;
1712 __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb));
1713 __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr));
1715 cur_ttb &= ~(L1_TABLE_SIZE - 1);
1717 if (cur_ttb == (u_int)pcb->pcb_pagedir &&
1718 cur_dacr == pcb->pcb_dacr) {
1720 * No need to switch address spaces.
1728 * We MUST, I repeat, MUST fix up the L1 entry corresponding
1729 * to 'vector_page' in the incoming L1 table before switching
1730 * to it otherwise subsequent interrupts/exceptions (including
1731 * domain faults!) will jump into hyperspace.
1733 if (pcb->pcb_pl1vec) {
1734 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
1737 cpu_domains(pcb->pcb_dacr);
1738 cpu_setttb(pcb->pcb_pagedir);
1744 pmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va)
1746 pd_entry_t *pdep, pde;
1747 pt_entry_t *ptep, pte;
1752 * Make sure the descriptor itself has the correct cache mode
1754 pdep = &kl1[L1_IDX(va)];
1757 if (l1pte_section_p(pde)) {
1758 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) {
1759 *pdep = (pde & ~L1_S_CACHE_MASK) |
1760 pte_l1_s_cache_mode_pt;
1765 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
1766 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
1768 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep);
1770 ptep = &ptep[l2pte_index(va)];
1772 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
1773 *ptep = (pte & ~L2_S_CACHE_MASK) |
1774 pte_l2_s_cache_mode_pt;
1784 pmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap,
1787 vm_offset_t va = *availp;
1788 struct l2_bucket *l2b;
1791 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
1793 panic("pmap_alloc_specials: no l2b for 0x%x", va);
1795 *ptep = &l2b->l2b_kva[l2pte_index(va)];
1799 *availp = va + (PAGE_SIZE * pages);
1803 * Bootstrap the system enough to run with virtual memory.
1805 * On the arm this is called after mapping has already been enabled
1806 * and just syncs the pmap module with what has already been done.
1807 * [We can't call it easily with mapping off since the kernel is not
1808 * mapped with PA == VA, hence we would have to relocate every address
1809 * from the linked base (virtual) address "KERNBASE" to the actual
1810 * (physical) address starting relative to 0]
1812 #define PMAP_STATIC_L2_SIZE 16
1815 pmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt)
1817 static struct l1_ttable static_l1;
1818 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE];
1819 struct l1_ttable *l1 = &static_l1;
1820 struct l2_dtable *l2;
1821 struct l2_bucket *l2b;
1822 struct czpages *czp;
1824 pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va;
1829 int i, l1idx, l2idx, l2next = 0;
1831 PDEBUG(1, printf("firstaddr = %08x, lastaddr = %08x\n",
1832 firstaddr, vm_max_kernel_address));
1834 virtual_avail = firstaddr;
1835 kernel_pmap->pm_l1 = l1;
1836 kernel_l1pa = l1pt->pv_pa;
1839 * Scan the L1 translation table created by initarm() and create
1840 * the required metadata for all valid mappings found in it.
1842 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) {
1843 pde = kernel_l1pt[l1idx];
1846 * We're only interested in Coarse mappings.
1847 * pmap_extract() can deal with section mappings without
1848 * recourse to checking L2 metadata.
1850 if ((pde & L1_TYPE_MASK) != L1_TYPE_C)
1854 * Lookup the KVA of this L2 descriptor table
1856 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
1857 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
1860 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx",
1861 (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa);
1865 * Fetch the associated L2 metadata structure.
1866 * Allocate a new one if necessary.
1868 if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) {
1869 if (l2next == PMAP_STATIC_L2_SIZE)
1870 panic("pmap_bootstrap: out of static L2s");
1871 kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 =
1872 &static_l2[l2next++];
1876 * One more L1 slot tracked...
1881 * Fill in the details of the L2 descriptor in the
1882 * appropriate bucket.
1884 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
1885 l2b->l2b_kva = ptep;
1887 l2b->l2b_l1idx = l1idx;
1890 * Establish an initial occupancy count for this descriptor
1893 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
1895 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) {
1896 l2b->l2b_occupancy++;
1901 * Make sure the descriptor itself has the correct cache mode.
1902 * If not, fix it, but whine about the problem. Port-meisters
1903 * should consider this a clue to fix up their initarm()
1906 if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) {
1907 printf("pmap_bootstrap: WARNING! wrong cache mode for "
1908 "L2 pte @ %p\n", ptep);
1914 * Ensure the primary (kernel) L1 has the correct cache mode for
1915 * a page table. Bitch if it is not correctly set.
1917 for (va = (vm_offset_t)kernel_l1pt;
1918 va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) {
1919 if (pmap_set_pt_cache_mode(kernel_l1pt, va))
1920 printf("pmap_bootstrap: WARNING! wrong cache mode for "
1921 "primary L1 @ 0x%x\n", va);
1924 cpu_dcache_wbinv_all();
1925 cpu_l2cache_wbinv_all();
1929 PMAP_LOCK_INIT(kernel_pmap);
1930 CPU_FILL(&kernel_pmap->pm_active);
1931 kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL;
1932 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1935 * Initialize the global pv list lock.
1937 rw_init(&pvh_global_lock, "pmap pv global");
1940 * Reserve some special page table entries/VA space for temporary
1941 * mapping of pages that are being copied or zeroed.
1943 for (czp = cpu_czpages, i = 0; i < MAXCPU; ++i, ++czp) {
1944 mtx_init(&czp->lock, "czpages", NULL, MTX_DEF);
1945 pmap_alloc_specials(&virtual_avail, 1, &czp->srcva, &czp->srcptep);
1946 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)czp->srcptep);
1947 pmap_alloc_specials(&virtual_avail, 1, &czp->dstva, &czp->dstptep);
1948 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)czp->dstptep);
1951 size = ((vm_max_kernel_address - pmap_curmaxkvaddr) + L1_S_OFFSET) /
1953 pmap_alloc_specials(&virtual_avail,
1954 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE,
1955 &pmap_kernel_l2ptp_kva, NULL);
1957 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE;
1958 pmap_alloc_specials(&virtual_avail,
1959 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE,
1960 &pmap_kernel_l2dtable_kva, NULL);
1962 pmap_alloc_specials(&virtual_avail,
1963 1, (vm_offset_t*)&_tmppt, NULL);
1964 pmap_alloc_specials(&virtual_avail,
1965 MAXDUMPPGS, (vm_offset_t *)&crashdumpmap, NULL);
1966 SLIST_INIT(&l1_list);
1967 TAILQ_INIT(&l1_lru_list);
1968 mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF);
1969 pmap_init_l1(l1, kernel_l1pt);
1970 cpu_dcache_wbinv_all();
1971 cpu_l2cache_wbinv_all();
1975 virtual_avail = round_page(virtual_avail);
1976 virtual_end = vm_max_kernel_address;
1977 kernel_vm_end = pmap_curmaxkvaddr;
1979 pmap_set_pcb_pagedir(kernel_pmap, thread0.td_pcb);
1982 /***************************************************
1983 * Pmap allocation/deallocation routines.
1984 ***************************************************/
1987 * Release any resources held by the given physical map.
1988 * Called when a pmap initialized by pmap_pinit is being released.
1989 * Should only be called if the map contains no valid mappings.
1992 pmap_release(pmap_t pmap)
1998 if (vector_page < KERNBASE) {
1999 struct pcb *curpcb = PCPU_GET(curpcb);
2000 pcb = thread0.td_pcb;
2001 if (pmap_is_current(pmap)) {
2003 * Frob the L1 entry corresponding to the vector
2004 * page so that it contains the kernel pmap's domain
2005 * number. This will ensure pmap_remove() does not
2006 * pull the current vector page out from under us.
2009 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2010 cpu_domains(pcb->pcb_dacr);
2011 cpu_setttb(pcb->pcb_pagedir);
2014 pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE);
2016 * Make sure cpu_switch(), et al, DTRT. This is safe to do
2017 * since this process has no remaining mappings of its own.
2019 curpcb->pcb_pl1vec = pcb->pcb_pl1vec;
2020 curpcb->pcb_l1vec = pcb->pcb_l1vec;
2021 curpcb->pcb_dacr = pcb->pcb_dacr;
2022 curpcb->pcb_pagedir = pcb->pcb_pagedir;
2027 dprintf("pmap_release()\n");
2033 * Helper function for pmap_grow_l2_bucket()
2036 pmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap)
2038 struct l2_bucket *l2b;
2043 m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
2046 pa = VM_PAGE_TO_PHYS(m);
2051 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2053 ptep = &l2b->l2b_kva[l2pte_index(va)];
2054 *ptep = L2_S_PROTO | pa | cache_mode | L2_S_REF;
2055 pmap_set_prot(ptep, VM_PROT_READ | VM_PROT_WRITE, 0);
2057 cpu_tlb_flushD_SE(va);
2064 * This is the same as pmap_alloc_l2_bucket(), except that it is only
2065 * used by pmap_growkernel().
2067 static __inline struct l2_bucket *
2068 pmap_grow_l2_bucket(pmap_t pmap, vm_offset_t va)
2070 struct l2_dtable *l2;
2071 struct l2_bucket *l2b;
2072 struct l1_ttable *l1;
2079 if ((l2 = pmap->pm_l2[L2_IDX(l1idx)]) == NULL) {
2081 * No mapping at this address, as there is
2082 * no entry in the L1 table.
2083 * Need to allocate a new l2_dtable.
2085 nva = pmap_kernel_l2dtable_kva;
2086 if ((nva & PAGE_MASK) == 0) {
2088 * Need to allocate a backing page
2090 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2094 l2 = (struct l2_dtable *)nva;
2095 nva += sizeof(struct l2_dtable);
2097 if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva &
2100 * The new l2_dtable straddles a page boundary.
2101 * Map in another page to cover it.
2103 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2107 pmap_kernel_l2dtable_kva = nva;
2110 * Link it into the parent pmap
2112 pmap->pm_l2[L2_IDX(l1idx)] = l2;
2113 memset(l2, 0, sizeof(*l2));
2116 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2119 * Fetch pointer to the L2 page table associated with the address.
2121 if (l2b->l2b_kva == NULL) {
2125 * No L2 page table has been allocated. Chances are, this
2126 * is because we just allocated the l2_dtable, above.
2128 nva = pmap_kernel_l2ptp_kva;
2129 ptep = (pt_entry_t *)nva;
2130 if ((nva & PAGE_MASK) == 0) {
2132 * Need to allocate a backing page
2134 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt,
2135 &pmap_kernel_l2ptp_phys))
2138 memset(ptep, 0, L2_TABLE_SIZE_REAL);
2140 l2b->l2b_kva = ptep;
2141 l2b->l2b_l1idx = l1idx;
2142 l2b->l2b_phys = pmap_kernel_l2ptp_phys;
2144 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL;
2145 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL;
2148 /* Distribute new L1 entry to all other L1s */
2149 SLIST_FOREACH(l1, &l1_list, l1_link) {
2150 pl1pd = &l1->l1_kva[L1_IDX(va)];
2151 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) |
2155 cpu_tlb_flushID_SE(va);
2163 * grow the number of kernel page table entries, if needed
2166 pmap_growkernel(vm_offset_t addr)
2168 pmap_t kpmap = pmap_kernel();
2170 if (addr <= pmap_curmaxkvaddr)
2171 return; /* we are OK */
2174 * whoops! we need to add kernel PTPs
2177 /* Map 1MB at a time */
2178 for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE)
2179 pmap_grow_l2_bucket(kpmap, pmap_curmaxkvaddr);
2181 kernel_vm_end = pmap_curmaxkvaddr;
2185 * Returns TRUE if the given page is mapped individually or as part of
2186 * a 1MB section. Otherwise, returns FALSE.
2189 pmap_page_is_mapped(vm_page_t m)
2193 if ((m->oflags & VPO_UNMANAGED) != 0)
2195 rw_wlock(&pvh_global_lock);
2196 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
2197 ((m->flags & PG_FICTITIOUS) == 0 &&
2198 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
2199 rw_wunlock(&pvh_global_lock);
2204 * Remove all pages from specified address space
2205 * this aids process exit speeds. Also, this code
2206 * is special cased for current process only, but
2207 * can have the more generic (and slightly slower)
2208 * mode enabled. This is much faster than pmap_remove
2209 * in the case of running down an entire address space.
2212 pmap_remove_pages(pmap_t pmap)
2214 struct pv_entry *pv;
2215 struct l2_bucket *l2b = NULL;
2216 struct pv_chunk *pc, *npc;
2217 struct md_page *pvh;
2218 pd_entry_t *pl1pd, l1pd;
2222 uint32_t inuse, bitmask;
2223 int allfree, bit, field, idx;
2225 rw_wlock(&pvh_global_lock);
2228 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
2230 for (field = 0; field < _NPCM; field++) {
2231 inuse = ~pc->pc_map[field] & pc_freemask[field];
2232 while (inuse != 0) {
2233 bit = ffs(inuse) - 1;
2234 bitmask = 1ul << bit;
2235 idx = field * sizeof(inuse) * NBBY + bit;
2236 pv = &pc->pc_pventry[idx];
2239 if (pv->pv_flags & PVF_WIRED) {
2240 /* Cannot remove wired pages now. */
2244 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
2246 l2b = pmap_get_l2_bucket(pmap, va);
2247 if ((l1pd & L1_TYPE_MASK) == L1_S_PROTO) {
2248 pvh = pa_to_pvh(l1pd & L1_S_FRAME);
2249 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
2250 if (TAILQ_EMPTY(&pvh->pv_list)) {
2251 m = PHYS_TO_VM_PAGE(l1pd & L1_S_FRAME);
2252 KASSERT((vm_offset_t)m >= KERNBASE,
2253 ("Trying to access non-existent page "
2254 "va %x l1pd %x", trunc_1mpage(va), l1pd));
2255 for (mt = m; mt < &m[L2_PTE_NUM_TOTAL]; mt++) {
2256 if (TAILQ_EMPTY(&mt->md.pv_list))
2257 vm_page_aflag_clear(mt, PGA_WRITEABLE);
2261 KASSERT(l2b->l2b_occupancy == L2_PTE_NUM_TOTAL,
2262 ("pmap_remove_pages: l2_bucket occupancy error"));
2263 pmap_free_l2_bucket(pmap, l2b, L2_PTE_NUM_TOTAL);
2265 pmap->pm_stats.resident_count -= L2_PTE_NUM_TOTAL;
2269 KASSERT(l2b != NULL,
2270 ("No L2 bucket in pmap_remove_pages"));
2271 ptep = &l2b->l2b_kva[l2pte_index(va)];
2272 m = PHYS_TO_VM_PAGE(l2pte_pa(*ptep));
2273 KASSERT((vm_offset_t)m >= KERNBASE,
2274 ("Trying to access non-existent page "
2275 "va %x pte %x", va, *ptep));
2276 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2277 if (TAILQ_EMPTY(&m->md.pv_list) &&
2278 (m->flags & PG_FICTITIOUS) == 0) {
2279 pvh = pa_to_pvh(l2pte_pa(*ptep));
2280 if (TAILQ_EMPTY(&pvh->pv_list))
2281 vm_page_aflag_clear(m, PGA_WRITEABLE);
2285 pmap_free_l2_bucket(pmap, l2b, 1);
2286 pmap->pm_stats.resident_count--;
2290 PV_STAT(pv_entry_frees++);
2291 PV_STAT(pv_entry_spare++);
2293 pc->pc_map[field] |= bitmask;
2297 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2298 pmap_free_pv_chunk(pc);
2303 rw_wunlock(&pvh_global_lock);
2310 /***************************************************
2311 * Low level mapping routines.....
2312 ***************************************************/
2314 #ifdef ARM_HAVE_SUPERSECTIONS
2315 /* Map a super section into the KVA. */
2318 pmap_kenter_supersection(vm_offset_t va, uint64_t pa, int flags)
2320 pd_entry_t pd = L1_S_PROTO | L1_S_SUPERSEC | (pa & L1_SUP_FRAME) |
2321 (((pa >> 32) & 0xf) << 20) | L1_S_PROT(PTE_KERNEL,
2322 VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE) |
2323 L1_S_DOM(PMAP_DOMAIN_KERNEL);
2324 struct l1_ttable *l1;
2325 vm_offset_t va0, va_end;
2327 KASSERT(((va | pa) & L1_SUP_OFFSET) == 0,
2328 ("Not a valid super section mapping"));
2329 if (flags & SECTION_CACHE)
2330 pd |= pte_l1_s_cache_mode;
2331 else if (flags & SECTION_PT)
2332 pd |= pte_l1_s_cache_mode_pt;
2334 va0 = va & L1_SUP_FRAME;
2335 va_end = va + L1_SUP_SIZE;
2336 SLIST_FOREACH(l1, &l1_list, l1_link) {
2338 for (; va < va_end; va += L1_S_SIZE) {
2339 l1->l1_kva[L1_IDX(va)] = pd;
2340 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2346 /* Map a section into the KVA. */
2349 pmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags)
2351 pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL,
2352 VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE) | L1_S_REF |
2353 L1_S_DOM(PMAP_DOMAIN_KERNEL);
2354 struct l1_ttable *l1;
2356 KASSERT(((va | pa) & L1_S_OFFSET) == 0,
2357 ("Not a valid section mapping"));
2358 if (flags & SECTION_CACHE)
2359 pd |= pte_l1_s_cache_mode;
2360 else if (flags & SECTION_PT)
2361 pd |= pte_l1_s_cache_mode_pt;
2363 SLIST_FOREACH(l1, &l1_list, l1_link) {
2364 l1->l1_kva[L1_IDX(va)] = pd;
2365 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2367 cpu_tlb_flushID_SE(va);
2372 * Make a temporary mapping for a physical address. This is only intended
2373 * to be used for panic dumps.
2376 pmap_kenter_temporary(vm_paddr_t pa, int i)
2380 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
2381 pmap_kenter(va, pa);
2382 return ((void *)crashdumpmap);
2386 * add a wired page to the kva
2387 * note that in order for the mapping to take effect -- you
2388 * should do a invltlb after doing the pmap_kenter...
2390 static PMAP_INLINE void
2391 pmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags)
2393 struct l2_bucket *l2b;
2397 PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n",
2398 (uint32_t) va, (uint32_t) pa));
2401 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2403 l2b = pmap_grow_l2_bucket(pmap_kernel(), va);
2404 KASSERT(l2b != NULL, ("No L2 Bucket"));
2406 ptep = &l2b->l2b_kva[l2pte_index(va)];
2409 if (flags & KENTER_CACHE)
2410 *ptep = L2_S_PROTO | l2s_mem_types[PTE_CACHE] | pa | L2_S_REF;
2411 else if (flags & KENTER_DEVICE)
2412 *ptep = L2_S_PROTO | l2s_mem_types[PTE_DEVICE] | pa | L2_S_REF;
2414 *ptep = L2_S_PROTO | l2s_mem_types[PTE_NOCACHE] | pa | L2_S_REF;
2416 if (flags & KENTER_CACHE) {
2417 pmap_set_prot(ptep, VM_PROT_READ | VM_PROT_WRITE,
2418 flags & KENTER_USER);
2420 pmap_set_prot(ptep, VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE,
2425 if (l2pte_valid(opte)) {
2426 if (L2_S_EXECUTABLE(opte) || L2_S_EXECUTABLE(*ptep))
2427 cpu_tlb_flushID_SE(va);
2429 cpu_tlb_flushD_SE(va);
2432 l2b->l2b_occupancy++;
2436 PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n",
2437 (uint32_t) ptep, opte, *ptep));
2441 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2443 pmap_kenter_internal(va, pa, KENTER_CACHE);
2447 pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa)
2450 pmap_kenter_internal(va, pa, 0);
2454 pmap_kenter_device(vm_offset_t va, vm_size_t size, vm_paddr_t pa)
2458 KASSERT((size & PAGE_MASK) == 0,
2459 ("%s: device mapping not page-sized", __func__));
2463 pmap_kenter_internal(va, pa, KENTER_DEVICE);
2471 pmap_kremove_device(vm_offset_t va, vm_size_t size)
2475 KASSERT((size & PAGE_MASK) == 0,
2476 ("%s: device mapping not page-sized", __func__));
2487 pmap_kenter_user(vm_offset_t va, vm_paddr_t pa)
2490 pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER);
2492 * Call pmap_fault_fixup now, to make sure we'll have no exception
2493 * at the first use of the new address, or bad things will happen,
2494 * as we use one of these addresses in the exception handlers.
2496 pmap_fault_fixup(pmap_kernel(), va, VM_PROT_READ|VM_PROT_WRITE, 1);
2500 pmap_kextract(vm_offset_t va)
2503 if (kernel_vm_end == 0)
2505 return (pmap_extract_locked(kernel_pmap, va));
2509 * remove a page from the kernel pagetables
2512 pmap_kremove(vm_offset_t va)
2514 struct l2_bucket *l2b;
2515 pt_entry_t *ptep, opte;
2517 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2520 KASSERT(l2b != NULL, ("No L2 Bucket"));
2521 ptep = &l2b->l2b_kva[l2pte_index(va)];
2523 if (l2pte_valid(opte)) {
2524 va = va & ~PAGE_MASK;
2527 if (L2_S_EXECUTABLE(opte))
2528 cpu_tlb_flushID_SE(va);
2530 cpu_tlb_flushD_SE(va);
2537 * Used to map a range of physical addresses into kernel
2538 * virtual address space.
2540 * The value passed in '*virt' is a suggested virtual address for
2541 * the mapping. Architectures which can support a direct-mapped
2542 * physical to virtual region can return the appropriate address
2543 * within that region, leaving '*virt' unchanged. Other
2544 * architectures should map the pages starting at '*virt' and
2545 * update '*virt' with the first usable address after the mapped
2549 pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot)
2551 vm_offset_t sva = *virt;
2552 vm_offset_t va = sva;
2554 PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, "
2555 "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end,
2558 while (start < end) {
2559 pmap_kenter(va, start);
2568 * Add a list of wired pages to the kva
2569 * this routine is only used for temporary
2570 * kernel mappings that do not need to have
2571 * page modification or references recorded.
2572 * Note that old mappings are simply written
2573 * over. The page *must* be wired.
2576 pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
2580 for (i = 0; i < count; i++) {
2581 pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]),
2589 * this routine jerks page mappings from the
2590 * kernel -- it is meant only for temporary mappings.
2593 pmap_qremove(vm_offset_t va, int count)
2597 for (i = 0; i < count; i++) {
2607 * pmap_object_init_pt preloads the ptes for a given object
2608 * into the specified pmap. This eliminates the blast of soft
2609 * faults on process startup and immediately after an mmap.
2612 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
2613 vm_pindex_t pindex, vm_size_t size)
2616 VM_OBJECT_ASSERT_WLOCKED(object);
2617 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2618 ("pmap_object_init_pt: non-device object"));
2623 * pmap_is_prefaultable:
2625 * Return whether or not the specified virtual address is elgible
2629 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
2634 if (!pmap_get_pde_pte(pmap, addr, &pdep, &ptep))
2636 KASSERT((pdep != NULL && (l1pte_section_p(*pdep) || ptep != NULL)),
2637 ("Valid mapping but no pte ?"));
2638 if (*pdep != 0 && !l1pte_section_p(*pdep))
2645 * Fetch pointers to the PDE/PTE for the given pmap/VA pair.
2646 * Returns TRUE if the mapping exists, else FALSE.
2648 * NOTE: This function is only used by a couple of arm-specific modules.
2649 * It is not safe to take any pmap locks here, since we could be right
2650 * in the middle of debugging the pmap anyway...
2652 * It is possible for this routine to return FALSE even though a valid
2653 * mapping does exist. This is because we don't lock, so the metadata
2654 * state may be inconsistent.
2656 * NOTE: We can return a NULL *ptp in the case where the L1 pde is
2657 * a "section" mapping.
2660 pmap_get_pde_pte(pmap_t pmap, vm_offset_t va, pd_entry_t **pdp,
2663 struct l2_dtable *l2;
2664 pd_entry_t *pl1pd, l1pd;
2668 if (pmap->pm_l1 == NULL)
2672 *pdp = pl1pd = &pmap->pm_l1->l1_kva[l1idx];
2675 if (l1pte_section_p(l1pd)) {
2680 if (pmap->pm_l2 == NULL)
2683 l2 = pmap->pm_l2[L2_IDX(l1idx)];
2686 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
2690 *ptp = &ptep[l2pte_index(va)];
2695 * Routine: pmap_remove_all
2697 * Removes this physical page from
2698 * all physical maps in which it resides.
2699 * Reflects back modify bits to the pager.
2702 * Original versions of this routine were very
2703 * inefficient because they iteratively called
2704 * pmap_remove (slow...)
2707 pmap_remove_all(vm_page_t m)
2709 struct md_page *pvh;
2713 struct l2_bucket *l2b;
2714 boolean_t flush = FALSE;
2718 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2719 ("pmap_remove_all: page %p is not managed", m));
2720 rw_wlock(&pvh_global_lock);
2721 if ((m->flags & PG_FICTITIOUS) != 0)
2722 goto small_mappings;
2723 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2724 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2728 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(pv->pv_va)];
2729 KASSERT((*pl1pd & L1_TYPE_MASK) == L1_S_PROTO,
2730 ("pmap_remove_all: valid section mapping expected"));
2731 (void)pmap_demote_section(pmap, pv->pv_va);
2735 curpmap = vmspace_pmap(curproc->p_vmspace);
2736 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2738 if (flush == FALSE && (pmap == curpmap ||
2739 pmap == pmap_kernel()))
2743 l2b = pmap_get_l2_bucket(pmap, pv->pv_va);
2744 KASSERT(l2b != NULL, ("No l2 bucket"));
2745 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
2746 is_exec |= PTE_BEEN_EXECD(*ptep);
2748 if (pmap_is_current(pmap))
2750 pmap_free_l2_bucket(pmap, l2b, 1);
2751 pmap->pm_stats.resident_count--;
2752 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2753 if (pv->pv_flags & PVF_WIRED)
2754 pmap->pm_stats.wired_count--;
2755 pmap_free_pv_entry(pmap, pv);
2766 vm_page_aflag_clear(m, PGA_WRITEABLE);
2767 rw_wunlock(&pvh_global_lock);
2771 pmap_change_attr(vm_offset_t sva, vm_size_t len, int mode)
2773 vm_offset_t base, offset, tmpva;
2775 struct l2_bucket *l2b;
2776 pt_entry_t *ptep, pte;
2777 vm_offset_t next_bucket;
2779 PMAP_LOCK(kernel_pmap);
2781 base = trunc_page(sva);
2782 offset = sva & PAGE_MASK;
2783 size = roundup(offset + len, PAGE_SIZE);
2785 for (tmpva = base; tmpva < base + size; ) {
2786 next_bucket = L2_NEXT_BUCKET(tmpva);
2787 if (next_bucket > base + size)
2788 next_bucket = base + size;
2790 l2b = pmap_get_l2_bucket(kernel_pmap, tmpva);
2792 tmpva = next_bucket;
2796 ptep = &l2b->l2b_kva[l2pte_index(tmpva)];
2799 PMAP_UNLOCK(kernel_pmap);
2803 pte = *ptep &~ L2_S_CACHE_MASK;
2804 cpu_idcache_wbinv_range(tmpva, PAGE_SIZE);
2805 pmap_l2cache_wbinv_range(tmpva, pte & L2_S_FRAME, PAGE_SIZE);
2807 cpu_tlb_flushID_SE(tmpva);
2810 dprintf("%s: for va:%x ptep:%x pte:%x\n",
2811 __func__, tmpva, (uint32_t)ptep, pte);
2815 PMAP_UNLOCK(kernel_pmap);
2821 * Set the physical protection on the
2822 * specified range of this map as requested.
2825 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2827 struct l2_bucket *l2b;
2828 struct md_page *pvh;
2829 struct pv_entry *pve;
2830 pd_entry_t *pl1pd, l1pd;
2831 pt_entry_t *ptep, pte;
2832 vm_offset_t next_bucket;
2833 u_int is_exec, is_refd;
2836 if ((prot & VM_PROT_READ) == 0) {
2837 pmap_remove(pmap, sva, eva);
2841 if (prot & VM_PROT_WRITE) {
2843 * If this is a read->write transition, just ignore it and let
2844 * vm_fault() take care of it later.
2849 rw_wlock(&pvh_global_lock);
2853 * OK, at this point, we know we're doing write-protect operation.
2854 * If the pmap is active, write-back the range.
2857 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1;
2858 is_exec = is_refd = 0;
2861 next_bucket = L2_NEXT_BUCKET(sva);
2863 * Check for large page.
2865 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(sva)];
2867 if ((l1pd & L1_TYPE_MASK) == L1_S_PROTO) {
2868 KASSERT(pmap != pmap_kernel(),
2869 ("pmap_protect: trying to modify "
2870 "kernel section protections"));
2872 * Are we protecting the entire large page? If not,
2873 * demote the mapping and fall through.
2875 if (sva + L1_S_SIZE == next_bucket &&
2876 eva >= next_bucket) {
2877 l1pd &= ~(L1_S_PROT_MASK | L1_S_XN);
2878 if (!(prot & VM_PROT_EXECUTE))
2881 * At this point we are always setting
2882 * write-protect bit.
2885 /* All managed superpages are user pages. */
2886 l1pd |= L1_S_PROT_U;
2889 pvh = pa_to_pvh(l1pd & L1_S_FRAME);
2890 pve = pmap_find_pv(pvh, pmap,
2892 pve->pv_flags &= ~PVF_WRITE;
2895 } else if (!pmap_demote_section(pmap, sva)) {
2896 /* The large page mapping was destroyed. */
2901 if (next_bucket > eva)
2903 l2b = pmap_get_l2_bucket(pmap, sva);
2909 ptep = &l2b->l2b_kva[l2pte_index(sva)];
2911 while (sva < next_bucket) {
2912 if ((pte = *ptep) != 0 && L2_S_WRITABLE(pte)) {
2915 m = PHYS_TO_VM_PAGE(l2pte_pa(pte));
2916 pmap_set_prot(ptep, prot,
2917 !(pmap == pmap_kernel()));
2920 pmap_modify_pv(m, pmap, sva, PVF_WRITE, 0);
2924 is_exec |= PTE_BEEN_EXECD(pte);
2925 is_refd |= PTE_BEEN_REFD(pte);
2927 if (PTE_BEEN_EXECD(pte))
2928 cpu_tlb_flushID_SE(sva);
2929 else if (PTE_BEEN_REFD(pte))
2930 cpu_tlb_flushD_SE(sva);
2948 rw_wunlock(&pvh_global_lock);
2955 * Insert the given physical page (p) at
2956 * the specified virtual address (v) in the
2957 * target physical map with the protection requested.
2959 * If specified, the page will be wired down, meaning
2960 * that the related pte can not be reclaimed.
2962 * NB: This is the only routine which MAY NOT lazy-evaluate
2963 * or lose information. That is, this routine must actually
2964 * insert this page into the given map NOW.
2968 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2969 u_int flags, int8_t psind __unused)
2971 struct l2_bucket *l2b;
2974 rw_wlock(&pvh_global_lock);
2976 rv = pmap_enter_locked(pmap, va, m, prot, flags);
2977 if (rv == KERN_SUCCESS) {
2979 * If both the l2b_occupancy and the reservation are fully
2980 * populated, then attempt promotion.
2982 l2b = pmap_get_l2_bucket(pmap, va);
2983 if (l2b != NULL && l2b->l2b_occupancy == L2_PTE_NUM_TOTAL &&
2984 sp_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
2985 vm_reserv_level_iffullpop(m) == 0)
2986 pmap_promote_section(pmap, va);
2989 rw_wunlock(&pvh_global_lock);
2994 * The pvh global and pmap locks must be held.
2997 pmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3000 struct l2_bucket *l2b = NULL;
3002 struct pv_entry *pve = NULL;
3003 pd_entry_t *pl1pd, l1pd;
3004 pt_entry_t *ptep, npte, opte;
3006 u_int is_exec, is_refd;
3010 PMAP_ASSERT_LOCKED(pmap);
3011 rw_assert(&pvh_global_lock, RA_WLOCKED);
3012 if (va == vector_page) {
3013 pa = systempage.pv_pa;
3016 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3017 VM_OBJECT_ASSERT_LOCKED(m->object);
3018 pa = VM_PAGE_TO_PHYS(m);
3021 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
3022 if ((va < VM_MAXUSER_ADDRESS) &&
3023 (*pl1pd & L1_TYPE_MASK) == L1_S_PROTO) {
3024 (void)pmap_demote_section(pmap, va);
3029 * Make sure userland mappings get the right permissions
3031 if (pmap != pmap_kernel() && va != vector_page)
3036 if (prot & VM_PROT_WRITE)
3037 nflags |= PVF_WRITE;
3038 if ((flags & PMAP_ENTER_WIRED) != 0)
3039 nflags |= PVF_WIRED;
3041 PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, "
3042 "prot = %x, flags = %x\n", (uint32_t) pmap, va, (uint32_t) m,
3045 if (pmap == pmap_kernel()) {
3046 l2b = pmap_get_l2_bucket(pmap, va);
3048 l2b = pmap_grow_l2_bucket(pmap, va);
3051 l2b = pmap_alloc_l2_bucket(pmap, va);
3053 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
3055 rw_wunlock(&pvh_global_lock);
3057 rw_wlock(&pvh_global_lock);
3061 return (KERN_RESOURCE_SHORTAGE);
3065 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
3066 if ((*pl1pd & L1_TYPE_MASK) == L1_S_PROTO)
3067 panic("pmap_enter: attempt to enter on 1MB page, va: %#x", va);
3069 ptep = &l2b->l2b_kva[l2pte_index(va)];
3073 is_exec = is_refd = 0;
3076 if (l2pte_pa(opte) == pa) {
3078 * We're changing the attrs of an existing mapping.
3081 pmap_modify_pv(m, pmap, va,
3082 PVF_WRITE | PVF_WIRED, nflags);
3083 is_exec |= PTE_BEEN_EXECD(opte);
3084 is_refd |= PTE_BEEN_REFD(opte);
3087 if ((om = PHYS_TO_VM_PAGE(l2pte_pa(opte)))) {
3089 * Replacing an existing mapping with a new one.
3090 * It is part of our managed memory so we
3091 * must remove it from the PV list
3093 if ((pve = pmap_remove_pv(om, pmap, va))) {
3094 is_exec |= PTE_BEEN_EXECD(opte);
3095 is_refd |= PTE_BEEN_REFD(opte);
3097 if (m && ((m->oflags & VPO_UNMANAGED)))
3098 pmap_free_pv_entry(pmap, pve);
3104 * Keep the stats up to date
3106 l2b->l2b_occupancy++;
3107 pmap->pm_stats.resident_count++;
3111 * Enter on the PV list if part of our managed memory.
3113 if ((m && !(m->oflags & VPO_UNMANAGED))) {
3114 if ((!pve) && (pve = pmap_get_pv_entry(pmap, FALSE)) == NULL)
3115 panic("pmap_enter: no pv entries");
3117 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3118 ("pmap_enter: managed mapping within the clean submap"));
3119 KASSERT(pve != NULL, ("No pv"));
3120 pmap_enter_pv(m, pve, pmap, va, nflags);
3124 /* Make the new PTE valid */
3129 /* Set defaults first - kernel read access */
3131 npte |= L2_S_PROT_R;
3132 /* Set "referenced" flag */
3135 /* Now tune APs as desired */
3137 npte |= L2_S_PROT_U;
3139 * If this is not a vector_page
3140 * then continue setting mapping parameters
3143 if ((m->oflags & VPO_UNMANAGED) == 0) {
3144 if (prot & (VM_PROT_ALL)) {
3145 vm_page_aflag_set(m, PGA_REFERENCED);
3148 * Need to do page referenced emulation.
3154 if (prot & VM_PROT_WRITE) {
3155 if ((m->oflags & VPO_UNMANAGED) == 0) {
3156 vm_page_aflag_set(m, PGA_WRITEABLE);
3158 * XXX: Skip modified bit emulation for now.
3159 * The emulation reveals problems
3160 * that result in random failures
3161 * during memory allocation on some
3163 * Therefore, the page is marked RW
3171 if (!(prot & VM_PROT_EXECUTE))
3174 if (m->md.pv_memattr != VM_MEMATTR_UNCACHEABLE)
3175 npte |= pte_l2_s_cache_mode;
3178 CTR5(KTR_PMAP,"enter: pmap:%p va:%x prot:%x pte:%x->%x",
3179 pmap, va, prot, opte, npte);
3181 * If this is just a wiring change, the two PTEs will be
3182 * identical, so there's no need to update the page table.
3185 boolean_t is_cached = pmap_is_current(pmap);
3191 * We only need to frob the cache/tlb if this pmap
3194 if (L1_IDX(va) != L1_IDX(vector_page) &&
3195 l2pte_valid(npte)) {
3197 * This mapping is likely to be accessed as
3198 * soon as we return to userland. Fix up the
3199 * L1 entry to avoid taking another
3200 * page/domain fault.
3202 l1pd = l2b->l2b_phys |
3203 L1_C_DOM(pmap->pm_domain) | L1_C_PROTO;
3204 if (*pl1pd != l1pd) {
3212 cpu_tlb_flushID_SE(va);
3214 cpu_tlb_flushD_SE(va);
3218 if ((pmap != pmap_kernel()) && (pmap == &curproc->p_vmspace->vm_pmap))
3219 cpu_icache_sync_range(va, PAGE_SIZE);
3220 return (KERN_SUCCESS);
3224 * Maps a sequence of resident pages belonging to the same object.
3225 * The sequence begins with the given page m_start. This page is
3226 * mapped at the given virtual address start. Each subsequent page is
3227 * mapped at a virtual address that is offset from start by the same
3228 * amount as the page is offset from m_start within the object. The
3229 * last page in the sequence is the page with the largest offset from
3230 * m_start that can be mapped at a virtual address less than the given
3231 * virtual address end. Not every virtual page between start and end
3232 * is mapped; only those for which a resident page exists with the
3233 * corresponding offset from m_start are mapped.
3236 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3237 vm_page_t m_start, vm_prot_t prot)
3241 vm_pindex_t diff, psize;
3243 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3245 psize = atop(end - start);
3247 prot &= VM_PROT_READ | VM_PROT_EXECUTE;
3248 rw_wlock(&pvh_global_lock);
3250 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3251 va = start + ptoa(diff);
3252 if ((va & L1_S_OFFSET) == 0 && L2_NEXT_BUCKET(va) <= end &&
3253 m->psind == 1 && sp_enabled &&
3254 pmap_enter_section(pmap, va, m, prot))
3255 m = &m[L1_S_SIZE / PAGE_SIZE - 1];
3257 pmap_enter_locked(pmap, va, m, prot,
3258 PMAP_ENTER_NOSLEEP);
3259 m = TAILQ_NEXT(m, listq);
3262 rw_wunlock(&pvh_global_lock);
3266 * this code makes some *MAJOR* assumptions:
3267 * 1. Current pmap & pmap exists.
3270 * 4. No page table pages.
3271 * but is *MUCH* faster than pmap_enter...
3275 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3278 prot &= VM_PROT_READ | VM_PROT_EXECUTE;
3279 rw_wlock(&pvh_global_lock);
3281 pmap_enter_locked(pmap, va, m, prot, PMAP_ENTER_NOSLEEP);
3283 rw_wunlock(&pvh_global_lock);
3287 * Clear the wired attribute from the mappings for the specified range of
3288 * addresses in the given pmap. Every valid mapping within that range
3289 * must have the wired attribute set. In contrast, invalid mappings
3290 * cannot have the wired attribute set, so they are ignored.
3292 * XXX Wired mappings of unmanaged pages cannot be counted by this pmap
3296 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3298 struct l2_bucket *l2b;
3299 struct md_page *pvh;
3301 pt_entry_t *ptep, pte;
3303 vm_offset_t next_bucket;
3307 rw_wlock(&pvh_global_lock);
3310 next_bucket = L2_NEXT_BUCKET(sva);
3311 l1pd = pmap->pm_l1->l1_kva[L1_IDX(sva)];
3312 if ((l1pd & L1_TYPE_MASK) == L1_S_PROTO) {
3313 pa = l1pd & L1_S_FRAME;
3314 m = PHYS_TO_VM_PAGE(pa);
3315 KASSERT(m != NULL && (m->oflags & VPO_UNMANAGED) == 0,
3316 ("pmap_unwire: unmanaged 1mpage %p", m));
3317 pvh = pa_to_pvh(pa);
3318 pv = pmap_find_pv(pvh, pmap, trunc_1mpage(sva));
3319 if ((pv->pv_flags & PVF_WIRED) == 0)
3320 panic("pmap_unwire: pv %p isn't wired", pv);
3323 * Are we unwiring the entire large page? If not,
3324 * demote the mapping and fall through.
3326 if (sva + L1_S_SIZE == next_bucket &&
3327 eva >= next_bucket) {
3328 pv->pv_flags &= ~PVF_WIRED;
3329 pmap->pm_stats.wired_count -= L2_PTE_NUM_TOTAL;
3332 } else if (!pmap_demote_section(pmap, sva))
3333 panic("pmap_unwire: demotion failed");
3335 if (next_bucket > eva)
3337 l2b = pmap_get_l2_bucket(pmap, sva);
3342 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; sva < next_bucket;
3343 sva += PAGE_SIZE, ptep++) {
3344 if ((pte = *ptep) == 0 ||
3345 (m = PHYS_TO_VM_PAGE(l2pte_pa(pte))) == NULL ||
3346 (m->oflags & VPO_UNMANAGED) != 0)
3348 pv = pmap_find_pv(&m->md, pmap, sva);
3349 if ((pv->pv_flags & PVF_WIRED) == 0)
3350 panic("pmap_unwire: pv %p isn't wired", pv);
3351 pv->pv_flags &= ~PVF_WIRED;
3352 pmap->pm_stats.wired_count--;
3355 rw_wunlock(&pvh_global_lock);
3361 * Copy the range specified by src_addr/len
3362 * from the source map to the range dst_addr/len
3363 * in the destination map.
3365 * This routine is only advisory and need not do anything.
3368 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
3369 vm_size_t len, vm_offset_t src_addr)
3375 * Routine: pmap_extract
3377 * Extract the physical page address associated
3378 * with the given map/virtual_address pair.
3381 pmap_extract(pmap_t pmap, vm_offset_t va)
3386 pa = pmap_extract_locked(pmap, va);
3392 pmap_extract_locked(pmap_t pmap, vm_offset_t va)
3394 struct l2_dtable *l2;
3396 pt_entry_t *ptep, pte;
3400 if (kernel_vm_end != 0 && pmap != kernel_pmap)
3401 PMAP_ASSERT_LOCKED(pmap);
3403 l1pd = pmap->pm_l1->l1_kva[l1idx];
3404 if (l1pte_section_p(l1pd)) {
3405 /* XXX: what to do about the bits > 32 ? */
3406 if (l1pd & L1_S_SUPERSEC)
3407 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3409 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3412 * Note that we can't rely on the validity of the L1
3413 * descriptor as an indication that a mapping exists.
3414 * We have to look it up in the L2 dtable.
3416 l2 = pmap->pm_l2[L2_IDX(l1idx)];
3418 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL)
3420 pte = ptep[l2pte_index(va)];
3423 switch (pte & L2_TYPE_MASK) {
3425 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3428 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3436 * Atomically extract and hold the physical page with the given
3437 * pmap and virtual address pair if that mapping permits the given
3442 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3444 struct l2_dtable *l2;
3446 pt_entry_t *ptep, pte;
3447 vm_paddr_t pa, paddr;
3455 l1pd = pmap->pm_l1->l1_kva[l1idx];
3456 if (l1pte_section_p(l1pd)) {
3457 /* XXX: what to do about the bits > 32 ? */
3458 if (l1pd & L1_S_SUPERSEC)
3459 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3461 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3462 if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr))
3464 if (L1_S_WRITABLE(l1pd) || (prot & VM_PROT_WRITE) == 0) {
3465 m = PHYS_TO_VM_PAGE(pa);
3470 * Note that we can't rely on the validity of the L1
3471 * descriptor as an indication that a mapping exists.
3472 * We have to look it up in the L2 dtable.
3474 l2 = pmap->pm_l2[L2_IDX(l1idx)];
3477 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3482 ptep = &ptep[l2pte_index(va)];
3488 } else if ((prot & VM_PROT_WRITE) && (pte & L2_APX)) {
3492 switch (pte & L2_TYPE_MASK) {
3494 panic("extract and hold section mapping");
3497 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3500 if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr))
3502 m = PHYS_TO_VM_PAGE(pa);
3509 PA_UNLOCK_COND(paddr);
3514 * Initialize a preallocated and zeroed pmap structure,
3515 * such as one in a vmspace structure.
3519 pmap_pinit(pmap_t pmap)
3521 PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap));
3523 pmap_alloc_l1(pmap);
3524 bzero(pmap->pm_l2, sizeof(pmap->pm_l2));
3526 CPU_ZERO(&pmap->pm_active);
3528 TAILQ_INIT(&pmap->pm_pvchunk);
3529 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3530 pmap->pm_stats.resident_count = 1;
3531 if (vector_page < KERNBASE) {
3532 pmap_enter(pmap, vector_page,
3533 PHYS_TO_VM_PAGE(systempage.pv_pa), VM_PROT_READ,
3534 PMAP_ENTER_WIRED, 0);
3540 /***************************************************
3541 * Superpage management routines.
3542 ***************************************************/
3544 static PMAP_INLINE struct pv_entry *
3545 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3549 rw_assert(&pvh_global_lock, RA_WLOCKED);
3551 pv = pmap_find_pv(pvh, pmap, va);
3553 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
3559 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3563 pv = pmap_pvh_remove(pvh, pmap, va);
3564 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3565 pmap_free_pv_entry(pmap, pv);
3569 pmap_pv_insert_section(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3571 struct md_page *pvh;
3574 rw_assert(&pvh_global_lock, RA_WLOCKED);
3575 if (pv_entry_count < pv_entry_high_water &&
3576 (pv = pmap_get_pv_entry(pmap, TRUE)) != NULL) {
3578 pvh = pa_to_pvh(pa);
3579 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list);
3586 * Create the pv entries for each of the pages within a superpage.
3589 pmap_pv_demote_section(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3591 struct md_page *pvh;
3593 vm_offset_t va_last;
3596 rw_assert(&pvh_global_lock, RA_WLOCKED);
3597 KASSERT((pa & L1_S_OFFSET) == 0,
3598 ("pmap_pv_demote_section: pa is not 1mpage aligned"));
3601 * Transfer the 1mpage's pv entry for this mapping to the first
3604 pvh = pa_to_pvh(pa);
3605 va = trunc_1mpage(va);
3606 pv = pmap_pvh_remove(pvh, pmap, va);
3607 KASSERT(pv != NULL, ("pmap_pv_demote_section: pv not found"));
3608 m = PHYS_TO_VM_PAGE(pa);
3609 TAILQ_INSERT_HEAD(&m->md.pv_list, pv, pv_list);
3610 /* Instantiate the remaining pv entries. */
3611 va_last = L2_NEXT_BUCKET(va) - PAGE_SIZE;
3614 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3615 ("pmap_pv_demote_section: page %p is not managed", m));
3617 pve = pmap_get_pv_entry(pmap, FALSE);
3618 pmap_enter_pv(m, pve, pmap, va, pv->pv_flags);
3619 } while (va < va_last);
3623 pmap_pv_promote_section(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3625 struct md_page *pvh;
3627 vm_offset_t va_last;
3630 rw_assert(&pvh_global_lock, RA_WLOCKED);
3631 KASSERT((pa & L1_S_OFFSET) == 0,
3632 ("pmap_pv_promote_section: pa is not 1mpage aligned"));
3635 * Transfer the first page's pv entry for this mapping to the
3636 * 1mpage's pv list. Aside from avoiding the cost of a call
3637 * to get_pv_entry(), a transfer avoids the possibility that
3638 * get_pv_entry() calls pmap_pv_reclaim() and that pmap_pv_reclaim()
3639 * removes one of the mappings that is being promoted.
3641 m = PHYS_TO_VM_PAGE(pa);
3642 va = trunc_1mpage(va);
3643 pv = pmap_pvh_remove(&m->md, pmap, va);
3644 KASSERT(pv != NULL, ("pmap_pv_promote_section: pv not found"));
3645 pvh = pa_to_pvh(pa);
3646 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list);
3647 /* Free the remaining pv entries in the newly mapped section pages */
3648 va_last = L2_NEXT_BUCKET(va) - PAGE_SIZE;
3653 * Don't care the flags, first pv contains sufficient
3654 * information for all of the pages so nothing is really lost.
3656 pmap_pvh_free(&m->md, pmap, va);
3657 } while (va < va_last);
3661 * Tries to create a 1MB page mapping. Returns TRUE if successful and
3662 * FALSE otherwise. Fails if (1) page is unmanageg, kernel pmap or vectors
3663 * page, (2) a mapping already exists at the specified virtual address, or
3664 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3667 pmap_enter_section(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3671 struct l2_bucket *l2b;
3673 rw_assert(&pvh_global_lock, RA_WLOCKED);
3674 PMAP_ASSERT_LOCKED(pmap);
3676 /* Skip kernel, vectors page and unmanaged mappings */
3677 if ((pmap == pmap_kernel()) || (L1_IDX(va) == L1_IDX(vector_page)) ||
3678 ((m->oflags & VPO_UNMANAGED) != 0)) {
3679 CTR2(KTR_PMAP, "pmap_enter_section: failure for va %#lx"
3680 " in pmap %p", va, pmap);
3684 * Check whether this is a valid section superpage entry or
3685 * there is a l2_bucket associated with that L1 page directory.
3687 va = trunc_1mpage(va);
3688 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
3689 l2b = pmap_get_l2_bucket(pmap, va);
3690 if ((*pl1pd & L1_S_PROTO) || (l2b != NULL)) {
3691 CTR2(KTR_PMAP, "pmap_enter_section: failure for va %#lx"
3692 " in pmap %p", va, pmap);
3695 pa = VM_PAGE_TO_PHYS(m);
3697 * Abort this mapping if its PV entry could not be created.
3699 if (!pmap_pv_insert_section(pmap, va, VM_PAGE_TO_PHYS(m))) {
3700 CTR2(KTR_PMAP, "pmap_enter_section: failure for va %#lx"
3701 " in pmap %p", va, pmap);
3705 * Increment counters.
3707 pmap->pm_stats.resident_count += L2_PTE_NUM_TOTAL;
3709 * Despite permissions, mark the superpage read-only.
3711 prot &= ~VM_PROT_WRITE;
3713 * Map the superpage.
3715 pmap_map_section(pmap, va, pa, prot, FALSE);
3717 pmap_section_mappings++;
3718 CTR2(KTR_PMAP, "pmap_enter_section: success for va %#lx"
3719 " in pmap %p", va, pmap);
3724 * pmap_remove_section: do the things to unmap a superpage in a process
3727 pmap_remove_section(pmap_t pmap, vm_offset_t sva)
3729 struct md_page *pvh;
3730 struct l2_bucket *l2b;
3731 pd_entry_t *pl1pd, l1pd;
3732 vm_offset_t eva, va;
3735 PMAP_ASSERT_LOCKED(pmap);
3736 if ((pmap == pmap_kernel()) || (L1_IDX(sva) == L1_IDX(vector_page)))
3739 KASSERT((sva & L1_S_OFFSET) == 0,
3740 ("pmap_remove_section: sva is not 1mpage aligned"));
3742 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(sva)];
3745 m = PHYS_TO_VM_PAGE(l1pd & L1_S_FRAME);
3746 KASSERT((m != NULL && ((m->oflags & VPO_UNMANAGED) == 0)),
3747 ("pmap_remove_section: no corresponding vm_page or "
3750 pmap->pm_stats.resident_count -= L2_PTE_NUM_TOTAL;
3751 pvh = pa_to_pvh(l1pd & L1_S_FRAME);
3752 pmap_pvh_free(pvh, pmap, sva);
3753 eva = L2_NEXT_BUCKET(sva);
3754 for (va = sva, m = PHYS_TO_VM_PAGE(l1pd & L1_S_FRAME);
3755 va < eva; va += PAGE_SIZE, m++) {
3757 * Mark base pages referenced but skip marking them dirty.
3758 * If the superpage is writeable, hence all base pages were
3759 * already marked as dirty in pmap_fault_fixup() before
3760 * promotion. Reference bit however, might not have been set
3761 * for each base page when the superpage was created at once,
3762 * not as a result of promotion.
3764 if (L1_S_REFERENCED(l1pd))
3765 vm_page_aflag_set(m, PGA_REFERENCED);
3766 if (TAILQ_EMPTY(&m->md.pv_list) &&
3767 TAILQ_EMPTY(&pvh->pv_list))
3768 vm_page_aflag_clear(m, PGA_WRITEABLE);
3771 l2b = pmap_get_l2_bucket(pmap, sva);
3773 KASSERT(l2b->l2b_occupancy == L2_PTE_NUM_TOTAL,
3774 ("pmap_remove_section: l2_bucket occupancy error"));
3775 pmap_free_l2_bucket(pmap, l2b, L2_PTE_NUM_TOTAL);
3777 /* Now invalidate L1 slot */
3780 if (L1_S_EXECUTABLE(l1pd))
3781 cpu_tlb_flushID_SE(sva);
3783 cpu_tlb_flushD_SE(sva);
3788 * Tries to promote the 256, contiguous 4KB page mappings that are
3789 * within a single l2_bucket to a single 1MB section mapping.
3790 * For promotion to occur, two conditions must be met: (1) the 4KB page
3791 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3792 * mappings must have identical characteristics.
3795 pmap_promote_section(pmap_t pmap, vm_offset_t va)
3797 pt_entry_t *firstptep, firstpte, oldpte, pa, *pte;
3799 vm_offset_t first_va, old_va;
3800 struct l2_bucket *l2b = NULL;
3802 struct pv_entry *pve, *first_pve;
3804 PMAP_ASSERT_LOCKED(pmap);
3808 * Skip promoting kernel pages. This is justified by following:
3809 * 1. Kernel is already mapped using section mappings in each pmap
3810 * 2. Managed mappings within the kernel are not to be promoted anyway
3812 if (pmap == pmap_kernel()) {
3813 pmap_section_p_failures++;
3814 CTR2(KTR_PMAP, "pmap_promote_section: failure for va %#x"
3815 " in pmap %p", va, pmap);
3818 /* Do not attemp to promote vectors pages */
3819 if (L1_IDX(va) == L1_IDX(vector_page)) {
3820 pmap_section_p_failures++;
3821 CTR2(KTR_PMAP, "pmap_promote_section: failure for va %#x"
3822 " in pmap %p", va, pmap);
3826 * Examine the first PTE in the specified l2_bucket. Abort if this PTE
3827 * is either invalid, unused, or does not map the first 4KB physical
3828 * page within 1MB page.
3830 first_va = trunc_1mpage(va);
3831 l2b = pmap_get_l2_bucket(pmap, first_va);
3832 KASSERT(l2b != NULL, ("pmap_promote_section: trying to promote "
3833 "not existing l2 bucket"));
3834 firstptep = &l2b->l2b_kva[0];
3836 firstpte = *firstptep;
3837 if ((l2pte_pa(firstpte) & L1_S_OFFSET) != 0) {
3838 pmap_section_p_failures++;
3839 CTR2(KTR_PMAP, "pmap_promote_section: failure for va %#x"
3840 " in pmap %p", va, pmap);
3844 if ((firstpte & (L2_S_PROTO | L2_S_REF)) != (L2_S_PROTO | L2_S_REF)) {
3845 pmap_section_p_failures++;
3846 CTR2(KTR_PMAP, "pmap_promote_section: failure for va %#x"
3847 " in pmap %p", va, pmap);
3851 * ARM uses pv_entry to mark particular mapping WIRED so don't promote
3852 * unmanaged pages since it is impossible to determine, whether the
3853 * page is wired or not if there is no corresponding pv_entry.
3855 m = PHYS_TO_VM_PAGE(l2pte_pa(firstpte));
3856 if (m && ((m->oflags & VPO_UNMANAGED) != 0)) {
3857 pmap_section_p_failures++;
3858 CTR2(KTR_PMAP, "pmap_promote_section: failure for va %#x"
3859 " in pmap %p", va, pmap);
3862 first_pve = pmap_find_pv(&m->md, pmap, first_va);
3864 * PTE is modified only on write due to modified bit
3865 * emulation. If the entry is referenced and writable
3866 * then it is modified and we don't clear write enable.
3867 * Otherwise, writing is disabled in PTE anyway and
3868 * we just configure protections for the section mapping
3869 * that is going to be created.
3871 if ((first_pve->pv_flags & PVF_WRITE) != 0) {
3872 if (!L2_S_WRITABLE(firstpte)) {
3873 first_pve->pv_flags &= ~PVF_WRITE;
3874 prot &= ~VM_PROT_WRITE;
3877 prot &= ~VM_PROT_WRITE;
3879 if (!L2_S_EXECUTABLE(firstpte))
3880 prot &= ~VM_PROT_EXECUTE;
3883 * Examine each of the other PTEs in the specified l2_bucket.
3884 * Abort if this PTE maps an unexpected 4KB physical page or
3885 * does not have identical characteristics to the first PTE.
3887 pa = l2pte_pa(firstpte) + ((L2_PTE_NUM_TOTAL - 1) * PAGE_SIZE);
3888 old_va = L2_NEXT_BUCKET(first_va) - PAGE_SIZE;
3890 for (pte = (firstptep + L2_PTE_NUM_TOTAL - 1); pte > firstptep; pte--) {
3892 if (l2pte_pa(oldpte) != pa) {
3893 pmap_section_p_failures++;
3894 CTR2(KTR_PMAP, "pmap_promote_section: failure for "
3895 "va %#x in pmap %p", va, pmap);
3898 if ((oldpte & L2_S_PROMOTE) != (firstpte & L2_S_PROMOTE)) {
3899 pmap_section_p_failures++;
3900 CTR2(KTR_PMAP, "pmap_promote_section: failure for "
3901 "va %#x in pmap %p", va, pmap);
3904 oldm = PHYS_TO_VM_PAGE(l2pte_pa(oldpte));
3905 if (oldm && ((oldm->oflags & VPO_UNMANAGED) != 0)) {
3906 pmap_section_p_failures++;
3907 CTR2(KTR_PMAP, "pmap_promote_section: failure for "
3908 "va %#x in pmap %p", va, pmap);
3912 pve = pmap_find_pv(&oldm->md, pmap, old_va);
3914 pmap_section_p_failures++;
3915 CTR2(KTR_PMAP, "pmap_promote_section: failure for "
3916 "va %#x old_va %x - no pve", va, old_va);
3920 if (!L2_S_WRITABLE(oldpte) && (pve->pv_flags & PVF_WRITE))
3921 pve->pv_flags &= ~PVF_WRITE;
3922 if (pve->pv_flags != first_pve->pv_flags) {
3923 pmap_section_p_failures++;
3924 CTR2(KTR_PMAP, "pmap_promote_section: failure for "
3925 "va %#x in pmap %p", va, pmap);
3929 old_va -= PAGE_SIZE;
3933 * Promote the pv entries.
3935 pmap_pv_promote_section(pmap, first_va, l2pte_pa(firstpte));
3937 * Map the superpage.
3939 pmap_map_section(pmap, first_va, l2pte_pa(firstpte), prot, TRUE);
3941 * Invalidate all possible TLB mappings for small
3942 * pages within the newly created superpage.
3943 * Rely on the first PTE's attributes since they
3944 * have to be consistent across all of the base pages
3945 * within the superpage. If page is not executable it
3946 * is at least referenced.
3947 * The fastest way to do that is to invalidate whole
3948 * TLB at once instead of executing 256 CP15 TLB
3949 * invalidations by single entry. TLBs usually maintain
3950 * several dozen entries so loss of unrelated entries is
3951 * still a less agresive approach.
3953 if (L2_S_EXECUTABLE(firstpte))
3959 pmap_section_promotions++;
3960 CTR2(KTR_PMAP, "pmap_promote_section: success for va %#x"
3961 " in pmap %p", first_va, pmap);
3965 * Fills a l2_bucket with mappings to consecutive physical pages.
3968 pmap_fill_l2b(struct l2_bucket *l2b, pt_entry_t newpte)
3973 for (i = 0; i < L2_PTE_NUM_TOTAL; i++) {
3974 ptep = &l2b->l2b_kva[i];
3978 newpte += PAGE_SIZE;
3981 l2b->l2b_occupancy = L2_PTE_NUM_TOTAL;
3985 * Tries to demote a 1MB section mapping. If demotion fails, the
3986 * 1MB section mapping is invalidated.
3989 pmap_demote_section(pmap_t pmap, vm_offset_t va)
3991 struct l2_bucket *l2b;
3992 struct pv_entry *l1pdpve;
3993 struct md_page *pvh;
3994 pd_entry_t *pl1pd, l1pd, newl1pd;
3995 pt_entry_t *firstptep, newpte;
3999 PMAP_ASSERT_LOCKED(pmap);
4001 * According to assumptions described in pmap_promote_section,
4002 * kernel is and always should be mapped using 1MB section mappings.
4003 * What more, managed kernel pages were not to be promoted.
4005 KASSERT(pmap != pmap_kernel() && L1_IDX(va) != L1_IDX(vector_page),
4006 ("pmap_demote_section: forbidden section mapping"));
4008 va = trunc_1mpage(va);
4009 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
4011 KASSERT((l1pd & L1_TYPE_MASK) == L1_S_PROTO,
4012 ("pmap_demote_section: not section or invalid section"));
4014 pa = l1pd & L1_S_FRAME;
4015 m = PHYS_TO_VM_PAGE(pa);
4016 KASSERT((m != NULL && (m->oflags & VPO_UNMANAGED) == 0),
4017 ("pmap_demote_section: no vm_page for selected superpage or"
4020 pvh = pa_to_pvh(pa);
4021 l1pdpve = pmap_find_pv(pvh, pmap, va);
4022 KASSERT(l1pdpve != NULL, ("pmap_demote_section: no pv entry for "
4025 l2b = pmap_get_l2_bucket(pmap, va);
4027 KASSERT((l1pdpve->pv_flags & PVF_WIRED) == 0,
4028 ("pmap_demote_section: No l2_bucket for wired mapping"));
4030 * Invalidate the 1MB section mapping and return
4031 * "failure" if the mapping was never accessed or the
4032 * allocation of the new l2_bucket fails.
4034 if (!L1_S_REFERENCED(l1pd) ||
4035 (l2b = pmap_alloc_l2_bucket(pmap, va)) == NULL) {
4036 /* Unmap and invalidate superpage. */
4037 pmap_remove_section(pmap, trunc_1mpage(va));
4038 CTR2(KTR_PMAP, "pmap_demote_section: failure for "
4039 "va %#x in pmap %p", va, pmap);
4045 * Now we should have corresponding l2_bucket available.
4046 * Let's process it to recreate 256 PTEs for each base page
4049 newpte = pa | L1_S_DEMOTE(l1pd);
4050 if (m->md.pv_memattr != VM_MEMATTR_UNCACHEABLE)
4051 newpte |= pte_l2_s_cache_mode;
4054 * If the l2_bucket is new, initialize it.
4056 if (l2b->l2b_occupancy == 0)
4057 pmap_fill_l2b(l2b, newpte);
4059 firstptep = &l2b->l2b_kva[0];
4060 KASSERT(l2pte_pa(*firstptep) == (pa),
4061 ("pmap_demote_section: firstpte and newpte map different "
4062 "physical addresses"));
4064 * If the mapping has changed attributes, update the page table
4067 if ((*firstptep & L2_S_PROMOTE) != (L1_S_DEMOTE(l1pd)))
4068 pmap_fill_l2b(l2b, newpte);
4070 /* Demote PV entry */
4071 pmap_pv_demote_section(pmap, va, pa);
4074 newl1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) | L1_C_PROTO;
4077 /* Invalidate old TLB mapping */
4078 if (L1_S_EXECUTABLE(l1pd))
4079 cpu_tlb_flushID_SE(va);
4080 else if (L1_S_REFERENCED(l1pd))
4081 cpu_tlb_flushD_SE(va);
4084 pmap_section_demotions++;
4085 CTR2(KTR_PMAP, "pmap_demote_section: success for va %#x"
4086 " in pmap %p", va, pmap);
4090 /***************************************************
4091 * page management routines.
4092 ***************************************************/
4095 * We are in a serious low memory condition. Resort to
4096 * drastic measures to free some pages so we can allocate
4097 * another pv entry chunk.
4100 pmap_pv_reclaim(pmap_t locked_pmap)
4103 struct pv_chunk *pc;
4104 struct l2_bucket *l2b = NULL;
4110 vm_page_t free, m, m_pc;
4112 int bit, field, freed, idx;
4114 PMAP_ASSERT_LOCKED(locked_pmap);
4117 TAILQ_INIT(&newtail);
4118 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
4120 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
4121 if (pmap != pc->pc_pmap) {
4125 if (pmap != locked_pmap)
4129 /* Avoid deadlock and lock recursion. */
4130 if (pmap > locked_pmap)
4132 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
4134 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
4140 * Destroy every non-wired, 4 KB page mapping in the chunk.
4143 for (field = 0; field < _NPCM; field++) {
4144 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
4145 inuse != 0; inuse &= ~(1UL << bit)) {
4146 bit = ffs(inuse) - 1;
4147 idx = field * sizeof(inuse) * NBBY + bit;
4148 pv = &pc->pc_pventry[idx];
4151 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
4152 if ((*pl1pd & L1_TYPE_MASK) == L1_S_PROTO)
4154 if (pv->pv_flags & PVF_WIRED)
4157 l2b = pmap_get_l2_bucket(pmap, va);
4158 KASSERT(l2b != NULL, ("No l2 bucket"));
4159 ptep = &l2b->l2b_kva[l2pte_index(va)];
4160 m = PHYS_TO_VM_PAGE(l2pte_pa(*ptep));
4161 KASSERT((vm_offset_t)m >= KERNBASE,
4162 ("Trying to access non-existent page "
4163 "va %x pte %x", va, *ptep));
4166 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
4167 if (TAILQ_EMPTY(&m->md.pv_list))
4168 vm_page_aflag_clear(m, PGA_WRITEABLE);
4169 pc->pc_map[field] |= 1UL << bit;
4175 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
4178 /* Every freed mapping is for a 4 KB page. */
4179 pmap->pm_stats.resident_count -= freed;
4180 PV_STAT(pv_entry_frees += freed);
4181 PV_STAT(pv_entry_spare += freed);
4182 pv_entry_count -= freed;
4183 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4184 for (field = 0; field < _NPCM; field++)
4185 if (pc->pc_map[field] != pc_freemask[field]) {
4186 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
4188 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
4191 * One freed pv entry in locked_pmap is
4194 if (pmap == locked_pmap)
4198 if (field == _NPCM) {
4199 PV_STAT(pv_entry_spare -= _NPCPV);
4200 PV_STAT(pc_chunk_count--);
4201 PV_STAT(pc_chunk_frees++);
4202 /* Entire chunk is free; return it. */
4203 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
4204 pmap_qremove((vm_offset_t)pc, 1);
4205 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
4210 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
4214 if (pmap != locked_pmap)
4221 * free the pv_entry back to the free list
4224 pmap_free_pv_entry(pmap_t pmap, pv_entry_t pv)
4226 struct pv_chunk *pc;
4227 int bit, field, idx;
4229 rw_assert(&pvh_global_lock, RA_WLOCKED);
4230 PMAP_ASSERT_LOCKED(pmap);
4231 PV_STAT(pv_entry_frees++);
4232 PV_STAT(pv_entry_spare++);
4234 pc = pv_to_chunk(pv);
4235 idx = pv - &pc->pc_pventry[0];
4236 field = idx / (sizeof(u_long) * NBBY);
4237 bit = idx % (sizeof(u_long) * NBBY);
4238 pc->pc_map[field] |= 1ul << bit;
4239 for (idx = 0; idx < _NPCM; idx++)
4240 if (pc->pc_map[idx] != pc_freemask[idx]) {
4242 * 98% of the time, pc is already at the head of the
4243 * list. If it isn't already, move it to the head.
4245 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
4247 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4248 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
4253 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4254 pmap_free_pv_chunk(pc);
4258 pmap_free_pv_chunk(struct pv_chunk *pc)
4262 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
4263 PV_STAT(pv_entry_spare -= _NPCPV);
4264 PV_STAT(pc_chunk_count--);
4265 PV_STAT(pc_chunk_frees++);
4266 /* entire chunk is free, return it */
4267 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
4268 pmap_qremove((vm_offset_t)pc, 1);
4269 vm_page_unwire(m, PQ_INACTIVE);
4271 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
4276 pmap_get_pv_entry(pmap_t pmap, boolean_t try)
4278 static const struct timeval printinterval = { 60, 0 };
4279 static struct timeval lastprint;
4280 struct pv_chunk *pc;
4283 int bit, field, idx;
4285 rw_assert(&pvh_global_lock, RA_WLOCKED);
4286 PMAP_ASSERT_LOCKED(pmap);
4287 PV_STAT(pv_entry_allocs++);
4290 if (pv_entry_count > pv_entry_high_water)
4291 if (ratecheck(&lastprint, &printinterval))
4292 printf("%s: Approaching the limit on PV entries.\n",
4295 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4297 for (field = 0; field < _NPCM; field++) {
4298 if (pc->pc_map[field]) {
4299 bit = ffs(pc->pc_map[field]) - 1;
4303 if (field < _NPCM) {
4304 idx = field * sizeof(pc->pc_map[field]) * NBBY + bit;
4305 pv = &pc->pc_pventry[idx];
4306 pc->pc_map[field] &= ~(1ul << bit);
4307 /* If this was the last item, move it to tail */
4308 for (field = 0; field < _NPCM; field++)
4309 if (pc->pc_map[field] != 0) {
4310 PV_STAT(pv_entry_spare--);
4311 return (pv); /* not full, return */
4313 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4314 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4315 PV_STAT(pv_entry_spare--);
4320 * Access to the ptelist "pv_vafree" is synchronized by the pvh
4321 * global lock. If "pv_vafree" is currently non-empty, it will
4322 * remain non-empty until pmap_ptelist_alloc() completes.
4324 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
4325 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
4328 PV_STAT(pc_chunk_tryfail++);
4331 m = pmap_pv_reclaim(pmap);
4335 PV_STAT(pc_chunk_count++);
4336 PV_STAT(pc_chunk_allocs++);
4337 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
4338 pmap_qenter((vm_offset_t)pc, &m, 1);
4340 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
4341 for (field = 1; field < _NPCM; field++)
4342 pc->pc_map[field] = pc_freemask[field];
4343 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
4344 pv = &pc->pc_pventry[0];
4345 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4346 PV_STAT(pv_entry_spare += _NPCPV - 1);
4351 * Remove the given range of addresses from the specified map.
4353 * It is assumed that the start and end are properly
4354 * rounded to the page size.
4356 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3
4358 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4360 struct l2_bucket *l2b;
4361 vm_offset_t next_bucket;
4365 u_int mappings, is_exec, is_refd;
4370 * we lock in the pmap => pv_head direction
4373 rw_wlock(&pvh_global_lock);
4377 next_bucket = L2_NEXT_BUCKET(sva);
4380 * Check for large page.
4382 l1pd = pmap->pm_l1->l1_kva[L1_IDX(sva)];
4383 if ((l1pd & L1_TYPE_MASK) == L1_S_PROTO) {
4384 KASSERT((l1pd & L1_S_DOM_MASK) !=
4385 L1_S_DOM(PMAP_DOMAIN_KERNEL), ("pmap_remove: "
4386 "Trying to remove kernel section mapping"));
4388 * Are we removing the entire large page? If not,
4389 * demote the mapping and fall through.
4391 if (sva + L1_S_SIZE == next_bucket &&
4392 eva >= next_bucket) {
4393 pmap_remove_section(pmap, sva);
4396 } else if (!pmap_demote_section(pmap, sva)) {
4397 /* The large page mapping was destroyed. */
4403 * Do one L2 bucket's worth at a time.
4405 if (next_bucket > eva)
4408 l2b = pmap_get_l2_bucket(pmap, sva);
4414 ptep = &l2b->l2b_kva[l2pte_index(sva)];
4417 while (sva < next_bucket) {
4426 * Nothing here, move along
4433 pmap->pm_stats.resident_count--;
4439 * Update flags. In a number of circumstances,
4440 * we could cluster a lot of these and do a
4441 * number of sequential pages in one go.
4443 if ((m = PHYS_TO_VM_PAGE(pa)) != NULL) {
4444 struct pv_entry *pve;
4446 pve = pmap_remove_pv(m, pmap, sva);
4448 is_exec = PTE_BEEN_EXECD(pte);
4449 is_refd = PTE_BEEN_REFD(pte);
4450 pmap_free_pv_entry(pmap, pve);
4456 if (pmap_is_current(pmap)) {
4458 if (total < PMAP_REMOVE_CLEAN_LIST_SIZE) {
4460 cpu_tlb_flushID_SE(sva);
4462 cpu_tlb_flushD_SE(sva);
4463 } else if (total == PMAP_REMOVE_CLEAN_LIST_SIZE)
4472 pmap_free_l2_bucket(pmap, l2b, mappings);
4475 rw_wunlock(&pvh_global_lock);
4486 * Zero a given physical page by mapping it at a page hook point.
4487 * In doing the zero page op, the page we zero is mapped cachable, as with
4488 * StrongARM accesses to non-cached pages are non-burst making writing
4489 * _any_ bulk data very slow.
4492 pmap_zero_page_gen(vm_page_t m, int off, int size)
4494 struct czpages *czp;
4496 KASSERT(TAILQ_EMPTY(&m->md.pv_list),
4497 ("pmap_zero_page_gen: page has mappings"));
4499 vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
4502 czp = &cpu_czpages[PCPU_GET(cpuid)];
4503 mtx_lock(&czp->lock);
4506 * Hook in the page, zero it.
4508 *czp->dstptep = L2_S_PROTO | phys | pte_l2_s_cache_mode | L2_S_REF;
4509 pmap_set_prot(czp->dstptep, VM_PROT_WRITE, 0);
4510 PTE_SYNC(czp->dstptep);
4511 cpu_tlb_flushD_SE(czp->dstva);
4514 if (off || size != PAGE_SIZE)
4515 bzero((void *)(czp->dstva + off), size);
4517 bzero_page(czp->dstva);
4520 * Although aliasing is not possible, if we use temporary mappings with
4521 * memory that will be mapped later as non-cached or with write-through
4522 * caches, we might end up overwriting it when calling wbinv_all. So
4523 * make sure caches are clean after the operation.
4525 cpu_idcache_wbinv_range(czp->dstva, size);
4526 pmap_l2cache_wbinv_range(czp->dstva, phys, size);
4528 mtx_unlock(&czp->lock);
4533 * pmap_zero_page zeros the specified hardware page by mapping
4534 * the page into KVM and using bzero to clear its contents.
4537 pmap_zero_page(vm_page_t m)
4539 pmap_zero_page_gen(m, 0, PAGE_SIZE);
4544 * pmap_zero_page_area zeros the specified hardware page by mapping
4545 * the page into KVM and using bzero to clear its contents.
4547 * off and size may not cover an area beyond a single hardware page.
4550 pmap_zero_page_area(vm_page_t m, int off, int size)
4553 pmap_zero_page_gen(m, off, size);
4558 * pmap_zero_page_idle zeros the specified hardware page by mapping
4559 * the page into KVM and using bzero to clear its contents. This
4560 * is intended to be called from the vm_pagezero process only and
4564 pmap_zero_page_idle(vm_page_t m)
4571 * pmap_copy_page copies the specified (machine independent)
4572 * page by mapping the page into virtual memory and using
4573 * bcopy to copy the page, one machine dependent page at a
4580 * Copy one physical page into another, by mapping the pages into
4581 * hook points. The same comment regarding cachability as in
4582 * pmap_zero_page also applies here.
4585 pmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst)
4587 struct czpages *czp;
4590 czp = &cpu_czpages[PCPU_GET(cpuid)];
4591 mtx_lock(&czp->lock);
4594 * Map the pages into the page hook points, copy them, and purge the
4595 * cache for the appropriate page.
4597 *czp->srcptep = L2_S_PROTO | src | pte_l2_s_cache_mode | L2_S_REF;
4598 pmap_set_prot(czp->srcptep, VM_PROT_READ, 0);
4599 PTE_SYNC(czp->srcptep);
4600 cpu_tlb_flushD_SE(czp->srcva);
4601 *czp->dstptep = L2_S_PROTO | dst | pte_l2_s_cache_mode | L2_S_REF;
4602 pmap_set_prot(czp->dstptep, VM_PROT_READ | VM_PROT_WRITE, 0);
4603 PTE_SYNC(czp->dstptep);
4604 cpu_tlb_flushD_SE(czp->dstva);
4607 bcopy_page(czp->srcva, czp->dstva);
4610 * Although aliasing is not possible, if we use temporary mappings with
4611 * memory that will be mapped later as non-cached or with write-through
4612 * caches, we might end up overwriting it when calling wbinv_all. So
4613 * make sure caches are clean after the operation.
4615 cpu_idcache_wbinv_range(czp->dstva, PAGE_SIZE);
4616 pmap_l2cache_wbinv_range(czp->dstva, dst, PAGE_SIZE);
4618 mtx_unlock(&czp->lock);
4622 int unmapped_buf_allowed = 1;
4625 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4626 vm_offset_t b_offset, int xfersize)
4628 vm_page_t a_pg, b_pg;
4629 vm_offset_t a_pg_offset, b_pg_offset;
4631 struct czpages *czp;
4634 czp = &cpu_czpages[PCPU_GET(cpuid)];
4635 mtx_lock(&czp->lock);
4637 while (xfersize > 0) {
4638 a_pg = ma[a_offset >> PAGE_SHIFT];
4639 a_pg_offset = a_offset & PAGE_MASK;
4640 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4641 b_pg = mb[b_offset >> PAGE_SHIFT];
4642 b_pg_offset = b_offset & PAGE_MASK;
4643 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4644 *czp->srcptep = L2_S_PROTO | VM_PAGE_TO_PHYS(a_pg) |
4645 pte_l2_s_cache_mode | L2_S_REF;
4646 pmap_set_prot(czp->srcptep, VM_PROT_READ, 0);
4647 PTE_SYNC(czp->srcptep);
4648 cpu_tlb_flushD_SE(czp->srcva);
4649 *czp->dstptep = L2_S_PROTO | VM_PAGE_TO_PHYS(b_pg) |
4650 pte_l2_s_cache_mode | L2_S_REF;
4651 pmap_set_prot(czp->dstptep, VM_PROT_READ | VM_PROT_WRITE, 0);
4652 PTE_SYNC(czp->dstptep);
4653 cpu_tlb_flushD_SE(czp->dstva);
4655 bcopy((char *)czp->srcva + a_pg_offset, (char *)czp->dstva + b_pg_offset,
4657 cpu_idcache_wbinv_range(czp->dstva + b_pg_offset, cnt);
4658 pmap_l2cache_wbinv_range(czp->dstva + b_pg_offset,
4659 VM_PAGE_TO_PHYS(b_pg) + b_pg_offset, cnt);
4665 mtx_unlock(&czp->lock);
4670 pmap_copy_page(vm_page_t src, vm_page_t dst)
4673 if (_arm_memcpy && PAGE_SIZE >= _min_memcpy_size &&
4674 _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst),
4675 (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0)
4678 pmap_copy_page_generic(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst));
4682 * this routine returns true if a physical page resides
4683 * in the given pmap.
4686 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4688 struct md_page *pvh;
4693 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4694 ("pmap_page_exists_quick: page %p is not managed", m));
4696 rw_wlock(&pvh_global_lock);
4697 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4698 if (PV_PMAP(pv) == pmap) {
4706 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4707 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4708 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4709 if (PV_PMAP(pv) == pmap) {
4718 rw_wunlock(&pvh_global_lock);
4723 * pmap_page_wired_mappings:
4725 * Return the number of managed mappings to the given physical page
4729 pmap_page_wired_mappings(vm_page_t m)
4734 if ((m->oflags & VPO_UNMANAGED) != 0)
4736 rw_wlock(&pvh_global_lock);
4737 count = pmap_pvh_wired_mappings(&m->md, count);
4738 if ((m->flags & PG_FICTITIOUS) == 0) {
4739 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4742 rw_wunlock(&pvh_global_lock);
4747 * pmap_pvh_wired_mappings:
4749 * Return the updated number "count" of managed mappings that are wired.
4752 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4756 rw_assert(&pvh_global_lock, RA_WLOCKED);
4757 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4758 if ((pv->pv_flags & PVF_WIRED) != 0)
4765 * Returns TRUE if any of the given mappings were referenced and FALSE
4766 * otherwise. Both page and section mappings are supported.
4769 pmap_is_referenced_pvh(struct md_page *pvh)
4771 struct l2_bucket *l2b;
4778 rw_assert(&pvh_global_lock, RA_WLOCKED);
4780 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4783 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(pv->pv_va)];
4784 if ((*pl1pd & L1_TYPE_MASK) == L1_S_PROTO)
4785 rv = L1_S_REFERENCED(*pl1pd);
4787 l2b = pmap_get_l2_bucket(pmap, pv->pv_va);
4788 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
4789 rv = L2_S_REFERENCED(*ptep);
4799 * pmap_is_referenced:
4801 * Return whether or not the specified physical page was referenced
4802 * in any physical maps.
4805 pmap_is_referenced(vm_page_t m)
4809 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4810 ("pmap_is_referenced: page %p is not managed", m));
4811 rw_wlock(&pvh_global_lock);
4812 rv = pmap_is_referenced_pvh(&m->md) ||
4813 ((m->flags & PG_FICTITIOUS) == 0 &&
4814 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4815 rw_wunlock(&pvh_global_lock);
4820 * pmap_ts_referenced:
4822 * Return the count of reference bits for a page, clearing all of them.
4825 pmap_ts_referenced(vm_page_t m)
4828 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4829 ("pmap_ts_referenced: page %p is not managed", m));
4830 return (pmap_clearbit(m, PVF_REF));
4834 * Returns TRUE if any of the given mappings were used to modify
4835 * physical memory. Otherwise, returns FALSE. Both page and 1MB section
4836 * mappings are supported.
4839 pmap_is_modified_pvh(struct md_page *pvh)
4842 struct l2_bucket *l2b;
4848 rw_assert(&pvh_global_lock, RA_WLOCKED);
4851 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4854 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(pv->pv_va)];
4855 if ((*pl1pd & L1_TYPE_MASK) == L1_S_PROTO)
4856 rv = L1_S_WRITABLE(*pl1pd);
4858 l2b = pmap_get_l2_bucket(pmap, pv->pv_va);
4859 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
4860 rv = L2_S_WRITABLE(*ptep);
4871 pmap_is_modified(vm_page_t m)
4875 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4876 ("pmap_is_modified: page %p is not managed", m));
4878 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4879 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4880 * is clear, no PTEs can have APX cleared.
4882 VM_OBJECT_ASSERT_WLOCKED(m->object);
4883 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4885 rw_wlock(&pvh_global_lock);
4886 rv = pmap_is_modified_pvh(&m->md) ||
4887 ((m->flags & PG_FICTITIOUS) == 0 &&
4888 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4889 rw_wunlock(&pvh_global_lock);
4894 * Apply the given advice to the specified range of addresses within the
4895 * given pmap. Depending on the advice, clear the referenced and/or
4896 * modified flags in each mapping.
4899 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4901 struct l2_bucket *l2b;
4902 struct pv_entry *pve;
4904 pt_entry_t *ptep, opte, pte;
4905 vm_offset_t next_bucket;
4908 if (advice != MADV_DONTNEED && advice != MADV_FREE)
4910 rw_wlock(&pvh_global_lock);
4912 for (; sva < eva; sva = next_bucket) {
4913 next_bucket = L2_NEXT_BUCKET(sva);
4914 if (next_bucket < sva)
4916 l1pd = pmap->pm_l1->l1_kva[L1_IDX(sva)];
4917 if ((l1pd & L1_TYPE_MASK) == L1_S_PROTO) {
4918 if (pmap == pmap_kernel())
4920 if (!pmap_demote_section(pmap, sva)) {
4922 * The large page mapping was destroyed.
4927 * Unless the page mappings are wired, remove the
4928 * mapping to a single page so that a subsequent
4929 * access may repromote. Since the underlying
4930 * l2_bucket is fully populated, this removal
4931 * never frees an entire l2_bucket.
4933 l2b = pmap_get_l2_bucket(pmap, sva);
4934 KASSERT(l2b != NULL,
4935 ("pmap_advise: no l2 bucket for "
4936 "va 0x%#x, pmap 0x%p", sva, pmap));
4937 ptep = &l2b->l2b_kva[l2pte_index(sva)];
4939 m = PHYS_TO_VM_PAGE(l2pte_pa(*ptep));
4941 ("pmap_advise: no vm_page for demoted superpage"));
4942 pve = pmap_find_pv(&m->md, pmap, sva);
4943 KASSERT(pve != NULL,
4944 ("pmap_advise: no PV entry for managed mapping"));
4945 if ((pve->pv_flags & PVF_WIRED) == 0) {
4946 pmap_free_l2_bucket(pmap, l2b, 1);
4947 pve = pmap_remove_pv(m, pmap, sva);
4948 pmap_free_pv_entry(pmap, pve);
4951 if (pmap_is_current(pmap)) {
4952 if (PTE_BEEN_EXECD(opte))
4953 cpu_tlb_flushID_SE(sva);
4954 else if (PTE_BEEN_REFD(opte))
4955 cpu_tlb_flushD_SE(sva);
4959 if (next_bucket > eva)
4961 l2b = pmap_get_l2_bucket(pmap, sva);
4964 for (ptep = &l2b->l2b_kva[l2pte_index(sva)];
4965 sva != next_bucket; ptep++, sva += PAGE_SIZE) {
4967 if ((opte & L2_S_PROTO) == 0)
4969 m = PHYS_TO_VM_PAGE(l2pte_pa(opte));
4970 if (m == NULL || (m->oflags & VPO_UNMANAGED) != 0)
4972 else if (L2_S_WRITABLE(opte)) {
4973 if (advice == MADV_DONTNEED) {
4975 * Don't need to mark the page
4976 * dirty as it was already marked as
4977 * such in pmap_fault_fixup() or
4978 * pmap_enter_locked().
4979 * Just clear the state.
4987 } else if (L2_S_REFERENCED(opte)) {
4993 if (pmap_is_current(pmap)) {
4994 if (PTE_BEEN_EXECD(opte))
4995 cpu_tlb_flushID_SE(sva);
4996 else if (PTE_BEEN_REFD(opte))
4997 cpu_tlb_flushD_SE(sva);
5002 rw_wunlock(&pvh_global_lock);
5007 * Clear the modify bits on the specified physical page.
5010 pmap_clear_modify(vm_page_t m)
5013 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5014 ("pmap_clear_modify: page %p is not managed", m));
5015 VM_OBJECT_ASSERT_WLOCKED(m->object);
5016 KASSERT(!vm_page_xbusied(m),
5017 ("pmap_clear_modify: page %p is exclusive busied", m));
5020 * If the page is not PGA_WRITEABLE, then no mappings can be modified.
5021 * If the object containing the page is locked and the page is not
5022 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5024 if ((m->aflags & PGA_WRITEABLE) == 0)
5026 if (pmap_is_modified(m))
5027 pmap_clearbit(m, PVF_MOD);
5032 * Clear the write and modified bits in each of the given page's mappings.
5035 pmap_remove_write(vm_page_t m)
5037 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5038 ("pmap_remove_write: page %p is not managed", m));
5041 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5042 * set by another thread while the object is locked. Thus,
5043 * if PGA_WRITEABLE is clear, no page table entries need updating.
5045 VM_OBJECT_ASSERT_WLOCKED(m->object);
5046 if (vm_page_xbusied(m) || (m->aflags & PGA_WRITEABLE) != 0)
5047 pmap_clearbit(m, PVF_WRITE);
5052 * perform the pmap work for mincore
5055 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5057 struct l2_bucket *l2b;
5058 pd_entry_t *pl1pd, l1pd;
5059 pt_entry_t *ptep, pte;
5067 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(addr)];
5069 if ((l1pd & L1_TYPE_MASK) == L1_S_PROTO) {
5070 pa = (l1pd & L1_S_FRAME);
5071 val = MINCORE_SUPER | MINCORE_INCORE;
5072 if (L1_S_WRITABLE(l1pd))
5073 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5075 m = PHYS_TO_VM_PAGE(pa);
5076 if (m != NULL && (m->oflags & VPO_UNMANAGED) == 0)
5079 if (L1_S_REFERENCED(l1pd))
5080 val |= MINCORE_REFERENCED |
5081 MINCORE_REFERENCED_OTHER;
5084 l2b = pmap_get_l2_bucket(pmap, addr);
5089 ptep = &l2b->l2b_kva[l2pte_index(addr)];
5091 if (!l2pte_valid(pte)) {
5095 val = MINCORE_INCORE;
5096 if (L2_S_WRITABLE(pte))
5097 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5100 m = PHYS_TO_VM_PAGE(pa);
5101 if (m != NULL && (m->oflags & VPO_UNMANAGED) == 0)
5104 if (L2_S_REFERENCED(pte))
5105 val |= MINCORE_REFERENCED |
5106 MINCORE_REFERENCED_OTHER;
5109 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5110 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
5111 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5112 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5116 PA_UNLOCK_COND(*locked_pa);
5122 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
5127 * Increase the starting virtual address of the given mapping if a
5128 * different alignment might result in more superpage mappings.
5131 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5132 vm_offset_t *addr, vm_size_t size)
5134 vm_offset_t superpage_offset;
5138 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5139 offset += ptoa(object->pg_color);
5140 superpage_offset = offset & PDRMASK;
5141 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5142 (*addr & PDRMASK) == superpage_offset)
5144 if ((*addr & PDRMASK) < superpage_offset)
5145 *addr = (*addr & ~PDRMASK) + superpage_offset;
5147 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5153 * Create a single section mapping.
5156 pmap_map_section(pmap_t pmap, vm_offset_t va, vm_offset_t pa, vm_prot_t prot,
5159 pd_entry_t *pl1pd, l1pd;
5162 KASSERT(((va | pa) & L1_S_OFFSET) == 0,
5163 ("Not a valid section mapping"));
5165 fl = pte_l1_s_cache_mode;
5167 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
5168 l1pd = L1_S_PROTO | pa | L1_S_PROT(PTE_USER, prot) | fl |
5169 L1_S_DOM(pmap->pm_domain);
5171 /* Mark page referenced if this section is a result of a promotion. */
5184 * Link the L2 page table specified by l2pv.pv_pa into the L1
5185 * page table at the slot for "va".
5188 pmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv)
5190 pd_entry_t *pde = (pd_entry_t *) l1pt, proto;
5191 u_int slot = va >> L1_S_SHIFT;
5193 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO;
5195 #ifdef VERBOSE_INIT_ARM
5196 printf("pmap_link_l2pt: pa=0x%x va=0x%x\n", l2pv->pv_pa, l2pv->pv_va);
5199 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000);
5200 PTE_SYNC(&pde[slot]);
5202 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list);
5209 * Create a single page mapping.
5212 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot,
5215 pd_entry_t *pde = (pd_entry_t *) l1pt;
5219 KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin"));
5221 fl = l2s_mem_types[cache];
5223 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
5224 panic("pmap_map_entry: no L2 table for VA 0x%08x", va);
5226 ptep = (pt_entry_t *)kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK);
5229 panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va);
5231 ptep[l2pte_index(va)] = L2_S_PROTO | pa | fl | L2_S_REF;
5232 pmap_set_prot(&ptep[l2pte_index(va)], prot, 0);
5233 PTE_SYNC(&ptep[l2pte_index(va)]);
5239 * Map a chunk of memory using the most efficient mappings
5240 * possible (section. large page, small page) into the
5241 * provided L1 and L2 tables at the specified virtual address.
5244 pmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
5245 vm_size_t size, int prot, int type)
5247 pd_entry_t *pde = (pd_entry_t *) l1pt;
5248 pt_entry_t *ptep, f1, f2s, f2l;
5252 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
5255 panic("pmap_map_chunk: no L1 table provided");
5257 #ifdef VERBOSE_INIT_ARM
5258 printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x "
5259 "prot=0x%x type=%d\n", pa, va, size, resid, prot, type);
5262 f1 = l1_mem_types[type];
5263 f2l = l2l_mem_types[type];
5264 f2s = l2s_mem_types[type];
5269 /* See if we can use a section mapping. */
5270 if (L1_S_MAPPABLE_P(va, pa, resid)) {
5271 #ifdef VERBOSE_INIT_ARM
5274 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
5275 L1_S_PROT(PTE_KERNEL, prot | VM_PROT_EXECUTE) |
5276 f1 | L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_S_REF;
5277 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
5285 * Ok, we're going to use an L2 table. Make sure
5286 * one is actually in the corresponding L1 slot
5287 * for the current VA.
5289 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
5290 panic("pmap_map_chunk: no L2 table for VA 0x%08x", va);
5292 ptep = (pt_entry_t *) kernel_pt_lookup(
5293 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
5295 panic("pmap_map_chunk: can't find L2 table for VA"
5297 /* See if we can use a L2 large page mapping. */
5298 if (L2_L_MAPPABLE_P(va, pa, resid)) {
5299 #ifdef VERBOSE_INIT_ARM
5302 for (i = 0; i < 16; i++) {
5303 ptep[l2pte_index(va) + i] =
5305 L2_L_PROT(PTE_KERNEL, prot) | f2l;
5306 PTE_SYNC(&ptep[l2pte_index(va) + i]);
5314 /* Use a small page mapping. */
5315 #ifdef VERBOSE_INIT_ARM
5318 ptep[l2pte_index(va)] = L2_S_PROTO | pa | f2s | L2_S_REF;
5319 pmap_set_prot(&ptep[l2pte_index(va)], prot, 0);
5320 PTE_SYNC(&ptep[l2pte_index(va)]);
5325 #ifdef VERBOSE_INIT_ARM
5333 pmap_dmap_iscurrent(pmap_t pmap)
5335 return(pmap_is_current(pmap));
5339 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5342 * Remember the memattr in a field that gets used to set the appropriate
5343 * bits in the PTEs as mappings are established.
5345 m->md.pv_memattr = ma;
5348 * It appears that this function can only be called before any mappings
5349 * for the page are established on ARM. If this ever changes, this code
5350 * will need to walk the pv_list and make each of the existing mappings
5351 * uncacheable, being careful to sync caches and PTEs (and maybe
5352 * invalidate TLB?) for any current mapping it modifies.
5354 if (TAILQ_FIRST(&m->md.pv_list) != NULL)
5355 panic("Can't change memattr on page with existing mappings");