1 /* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */
3 * Copyright 2011 Semihalf
4 * Copyright 2004 Olivier Houchard.
5 * Copyright 2003 Wasabi Systems, Inc.
8 * Written by Steve C. Woodford for Wasabi Systems, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed for the NetBSD Project by
21 * Wasabi Systems, Inc.
22 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
23 * or promote products derived from this software without specific prior
26 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
38 * From: FreeBSD: src/sys/arm/arm/pmap.c,v 1.113 2009/07/24 13:50:29
42 * Copyright (c) 2002-2003 Wasabi Systems, Inc.
43 * Copyright (c) 2001 Richard Earnshaw
44 * Copyright (c) 2001-2002 Christopher Gilbert
45 * All rights reserved.
47 * 1. Redistributions of source code must retain the above copyright
48 * notice, this list of conditions and the following disclaimer.
49 * 2. Redistributions in binary form must reproduce the above copyright
50 * notice, this list of conditions and the following disclaimer in the
51 * documentation and/or other materials provided with the distribution.
52 * 3. The name of the company nor the name of the author may be used to
53 * endorse or promote products derived from this software without specific
54 * prior written permission.
56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
57 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
58 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
59 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
60 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
61 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
62 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
63 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
64 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
65 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
69 * Copyright (c) 1999 The NetBSD Foundation, Inc.
70 * All rights reserved.
72 * This code is derived from software contributed to The NetBSD Foundation
73 * by Charles M. Hannum.
75 * Redistribution and use in source and binary forms, with or without
76 * modification, are permitted provided that the following conditions
78 * 1. Redistributions of source code must retain the above copyright
79 * notice, this list of conditions and the following disclaimer.
80 * 2. Redistributions in binary form must reproduce the above copyright
81 * notice, this list of conditions and the following disclaimer in the
82 * documentation and/or other materials provided with the distribution.
84 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
85 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
86 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
87 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
88 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
89 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
90 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
91 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
92 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
93 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
94 * POSSIBILITY OF SUCH DAMAGE.
98 * Copyright (c) 1994-1998 Mark Brinicombe.
99 * Copyright (c) 1994 Brini.
100 * All rights reserved.
102 * This code is derived from software written for Brini by Mark Brinicombe
104 * Redistribution and use in source and binary forms, with or without
105 * modification, are permitted provided that the following conditions
107 * 1. Redistributions of source code must retain the above copyright
108 * notice, this list of conditions and the following disclaimer.
109 * 2. Redistributions in binary form must reproduce the above copyright
110 * notice, this list of conditions and the following disclaimer in the
111 * documentation and/or other materials provided with the distribution.
112 * 3. All advertising materials mentioning features or use of this software
113 * must display the following acknowledgement:
114 * This product includes software developed by Mark Brinicombe.
115 * 4. The name of the author may not be used to endorse or promote products
116 * derived from this software without specific prior written permission.
118 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
119 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
120 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
121 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
122 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
123 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
124 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
125 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
126 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
128 * RiscBSD kernel project
132 * Machine dependant vm stuff
138 * Special compilation symbols
139 * PMAP_DEBUG - Build in pmap_debug_level code
141 /* Include header files */
145 #include <sys/cdefs.h>
146 __FBSDID("$FreeBSD$");
147 #include <sys/param.h>
148 #include <sys/systm.h>
149 #include <sys/kernel.h>
151 #include <sys/lock.h>
152 #include <sys/proc.h>
153 #include <sys/malloc.h>
154 #include <sys/msgbuf.h>
155 #include <sys/mutex.h>
156 #include <sys/vmmeter.h>
157 #include <sys/mman.h>
158 #include <sys/rwlock.h>
160 #include <sys/sched.h>
163 #include <vm/vm_param.h>
166 #include <vm/vm_kern.h>
167 #include <vm/vm_object.h>
168 #include <vm/vm_map.h>
169 #include <vm/vm_page.h>
170 #include <vm/vm_pageout.h>
171 #include <vm/vm_extern.h>
173 #include <machine/md_var.h>
174 #include <machine/cpu.h>
175 #include <machine/cpufunc.h>
176 #include <machine/pcb.h>
179 extern int last_fault_code;
183 #define PDEBUG(_lev_,_stat_) \
184 if (pmap_debug_level >= (_lev_)) \
186 #define dprintf printf
188 int pmap_debug_level = 0;
190 #else /* PMAP_DEBUG */
191 #define PDEBUG(_lev_,_stat_) /* Nothing */
192 #define dprintf(x, arg...)
193 #define PMAP_INLINE __inline
194 #endif /* PMAP_DEBUG */
196 extern struct pv_addr systempage;
199 * Internal function prototypes
201 static void pmap_free_pv_entry (pv_entry_t);
202 static pv_entry_t pmap_get_pv_entry(void);
204 static void pmap_enter_locked(pmap_t, vm_offset_t, vm_page_t,
205 vm_prot_t, boolean_t, int);
206 static vm_paddr_t pmap_extract_locked(pmap_t pmap, vm_offset_t va);
207 static void pmap_alloc_l1(pmap_t);
208 static void pmap_free_l1(pmap_t);
210 static int pmap_clearbit(struct vm_page *, u_int);
212 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t);
213 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t);
214 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int);
215 static vm_offset_t kernel_pt_lookup(vm_paddr_t);
217 static MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1");
219 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
220 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
221 vm_offset_t pmap_curmaxkvaddr;
222 vm_paddr_t kernel_l1pa;
224 vm_offset_t kernel_vm_end = 0;
226 struct pmap kernel_pmap_store;
228 static pt_entry_t *csrc_pte, *cdst_pte;
229 static vm_offset_t csrcp, cdstp;
230 static struct mtx cmtx;
232 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *);
234 * These routines are called when the CPU type is identified to set up
235 * the PTE prototypes, cache modes, etc.
237 * The variables are always here, just in case LKMs need to reference
238 * them (though, they shouldn't).
240 static void pmap_set_prot(pt_entry_t *pte, vm_prot_t prot, uint8_t user);
241 pt_entry_t pte_l1_s_cache_mode;
242 pt_entry_t pte_l1_s_cache_mode_pt;
244 pt_entry_t pte_l2_l_cache_mode;
245 pt_entry_t pte_l2_l_cache_mode_pt;
247 pt_entry_t pte_l2_s_cache_mode;
248 pt_entry_t pte_l2_s_cache_mode_pt;
250 struct msgbuf *msgbufp = 0;
255 static caddr_t crashdumpmap;
257 extern void bcopy_page(vm_offset_t, vm_offset_t);
258 extern void bzero_page(vm_offset_t);
263 * Metadata for L1 translation tables.
266 /* Entry on the L1 Table list */
267 SLIST_ENTRY(l1_ttable) l1_link;
269 /* Entry on the L1 Least Recently Used list */
270 TAILQ_ENTRY(l1_ttable) l1_lru;
272 /* Track how many domains are allocated from this L1 */
273 volatile u_int l1_domain_use_count;
276 * A free-list of domain numbers for this L1.
277 * We avoid using ffs() and a bitmap to track domains since ffs()
280 u_int8_t l1_domain_first;
281 u_int8_t l1_domain_free[PMAP_DOMAINS];
283 /* Physical address of this L1 page table */
284 vm_paddr_t l1_physaddr;
286 /* KVA of this L1 page table */
291 * Convert a virtual address into its L1 table index. That is, the
292 * index used to locate the L2 descriptor table pointer in an L1 table.
293 * This is basically used to index l1->l1_kva[].
295 * Each L2 descriptor table represents 1MB of VA space.
297 #define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT)
300 * L1 Page Tables are tracked using a Least Recently Used list.
301 * - New L1s are allocated from the HEAD.
302 * - Freed L1s are added to the TAIl.
303 * - Recently accessed L1s (where an 'access' is some change to one of
304 * the userland pmaps which owns this L1) are moved to the TAIL.
306 static TAILQ_HEAD(, l1_ttable) l1_lru_list;
308 * A list of all L1 tables
310 static SLIST_HEAD(, l1_ttable) l1_list;
311 static struct mtx l1_lru_lock;
314 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots.
316 * This is normally 16MB worth L2 page descriptors for any given pmap.
317 * Reference counts are maintained for L2 descriptors so they can be
321 /* The number of L2 page descriptors allocated to this l2_dtable */
324 /* List of L2 page descriptors */
326 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */
327 vm_paddr_t l2b_phys; /* Physical address of same */
328 u_short l2b_l1idx; /* This L2 table's L1 index */
329 u_short l2b_occupancy; /* How many active descriptors */
330 } l2_bucket[L2_BUCKET_SIZE];
333 /* pmap_kenter_internal flags */
334 #define KENTER_CACHE 0x1
335 #define KENTER_USER 0x2
338 * Given an L1 table index, calculate the corresponding l2_dtable index
339 * and bucket index within the l2_dtable.
341 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \
343 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1))
346 * Given a virtual address, this macro returns the
347 * virtual address required to drop into the next L2 bucket.
349 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE)
352 * We try to map the page tables write-through, if possible. However, not
353 * all CPUs have a write-through cache mode, so on those we have to sync
354 * the cache when we frob page tables.
356 * We try to evaluate this at compile time, if possible. However, it's
357 * not always possible to do that, hence this run-time var.
359 int pmap_needs_pte_sync;
362 * Macro to determine if a mapping might be resident in the
363 * instruction cache and/or TLB
365 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC))
368 * Macro to determine if a mapping might be resident in the
369 * data cache and/or TLB
371 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0)
373 #ifndef PMAP_SHPGPERPROC
374 #define PMAP_SHPGPERPROC 200
377 #define pmap_is_current(pm) ((pm) == pmap_kernel() || \
378 curproc->p_vmspace->vm_map.pmap == (pm))
379 static uma_zone_t pvzone = NULL;
381 static uma_zone_t l2table_zone;
382 static vm_offset_t pmap_kernel_l2dtable_kva;
383 static vm_offset_t pmap_kernel_l2ptp_kva;
384 static vm_paddr_t pmap_kernel_l2ptp_phys;
385 static struct vm_object pvzone_obj;
386 static int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0;
387 static struct rwlock pvh_global_lock;
389 int l1_mem_types[] = {
391 ARM_L1S_DEVICE_NOSHARE,
392 ARM_L1S_DEVICE_SHARE,
393 ARM_L1S_NRML_NOCACHE,
394 ARM_L1S_NRML_IWT_OWT,
395 ARM_L1S_NRML_IWB_OWB,
396 ARM_L1S_NRML_IWBA_OWBA
399 int l2l_mem_types[] = {
401 ARM_L2L_DEVICE_NOSHARE,
402 ARM_L2L_DEVICE_SHARE,
403 ARM_L2L_NRML_NOCACHE,
404 ARM_L2L_NRML_IWT_OWT,
405 ARM_L2L_NRML_IWB_OWB,
406 ARM_L2L_NRML_IWBA_OWBA
409 int l2s_mem_types[] = {
411 ARM_L2S_DEVICE_NOSHARE,
412 ARM_L2S_DEVICE_SHARE,
413 ARM_L2S_NRML_NOCACHE,
414 ARM_L2S_NRML_IWT_OWT,
415 ARM_L2S_NRML_IWB_OWB,
416 ARM_L2S_NRML_IWBA_OWBA
420 * This list exists for the benefit of pmap_map_chunk(). It keeps track
421 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can
422 * find them as necessary.
424 * Note that the data on this list MUST remain valid after initarm() returns,
425 * as pmap_bootstrap() uses it to contruct L2 table metadata.
427 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list);
430 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt)
435 l1->l1_domain_use_count = 0;
436 l1->l1_domain_first = 0;
438 for (i = 0; i < PMAP_DOMAINS; i++)
439 l1->l1_domain_free[i] = i + 1;
442 * Copy the kernel's L1 entries to each new L1.
444 if (l1pt != pmap_kernel()->pm_l1->l1_kva)
445 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE);
447 if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0)
448 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt);
449 SLIST_INSERT_HEAD(&l1_list, l1, l1_link);
450 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
454 kernel_pt_lookup(vm_paddr_t pa)
458 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) {
466 pmap_pte_init_mmu_v6(void)
469 if (PTE_PAGETABLE >= 3)
470 pmap_needs_pte_sync = 1;
471 pte_l1_s_cache_mode = l1_mem_types[PTE_CACHE];
472 pte_l2_l_cache_mode = l2l_mem_types[PTE_CACHE];
473 pte_l2_s_cache_mode = l2s_mem_types[PTE_CACHE];
475 pte_l1_s_cache_mode_pt = l1_mem_types[PTE_PAGETABLE];
476 pte_l2_l_cache_mode_pt = l2l_mem_types[PTE_PAGETABLE];
477 pte_l2_s_cache_mode_pt = l2s_mem_types[PTE_PAGETABLE];
482 * Allocate an L1 translation table for the specified pmap.
483 * This is called at pmap creation time.
486 pmap_alloc_l1(pmap_t pm)
488 struct l1_ttable *l1;
492 * Remove the L1 at the head of the LRU list
494 mtx_lock(&l1_lru_lock);
495 l1 = TAILQ_FIRST(&l1_lru_list);
496 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
499 * Pick the first available domain number, and update
500 * the link to the next number.
502 domain = l1->l1_domain_first;
503 l1->l1_domain_first = l1->l1_domain_free[domain];
506 * If there are still free domain numbers in this L1,
507 * put it back on the TAIL of the LRU list.
509 if (++l1->l1_domain_use_count < PMAP_DOMAINS)
510 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
512 mtx_unlock(&l1_lru_lock);
515 * Fix up the relevant bits in the pmap structure
518 pm->pm_domain = domain + 1;
522 * Free an L1 translation table.
523 * This is called at pmap destruction time.
526 pmap_free_l1(pmap_t pm)
528 struct l1_ttable *l1 = pm->pm_l1;
530 mtx_lock(&l1_lru_lock);
533 * If this L1 is currently on the LRU list, remove it.
535 if (l1->l1_domain_use_count < PMAP_DOMAINS)
536 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
539 * Free up the domain number which was allocated to the pmap
541 l1->l1_domain_free[pm->pm_domain - 1] = l1->l1_domain_first;
542 l1->l1_domain_first = pm->pm_domain - 1;
543 l1->l1_domain_use_count--;
546 * The L1 now must have at least 1 free domain, so add
547 * it back to the LRU list. If the use count is zero,
548 * put it at the head of the list, otherwise it goes
551 if (l1->l1_domain_use_count == 0) {
552 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru);
554 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
556 mtx_unlock(&l1_lru_lock);
560 * Returns a pointer to the L2 bucket associated with the specified pmap
561 * and VA, or NULL if no L2 bucket exists for the address.
563 static PMAP_INLINE struct l2_bucket *
564 pmap_get_l2_bucket(pmap_t pm, vm_offset_t va)
566 struct l2_dtable *l2;
567 struct l2_bucket *l2b;
572 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL ||
573 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL)
580 * Returns a pointer to the L2 bucket associated with the specified pmap
583 * If no L2 bucket exists, perform the necessary allocations to put an L2
584 * bucket/page table in place.
586 * Note that if a new L2 bucket/page was allocated, the caller *must*
587 * increment the bucket occupancy counter appropriately *before*
588 * releasing the pmap's lock to ensure no other thread or cpu deallocates
589 * the bucket/page in the meantime.
591 static struct l2_bucket *
592 pmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va)
594 struct l2_dtable *l2;
595 struct l2_bucket *l2b;
600 PMAP_ASSERT_LOCKED(pm);
601 rw_assert(&pvh_global_lock, RA_WLOCKED);
602 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
604 * No mapping at this address, as there is
605 * no entry in the L1 table.
606 * Need to allocate a new l2_dtable.
609 rw_wunlock(&pvh_global_lock);
610 if ((l2 = uma_zalloc(l2table_zone, M_NOWAIT)) == NULL) {
611 rw_wlock(&pvh_global_lock);
615 rw_wlock(&pvh_global_lock);
617 if (pm->pm_l2[L2_IDX(l1idx)] != NULL) {
619 * Someone already allocated the l2_dtable while
620 * we were doing the same.
622 uma_zfree(l2table_zone, l2);
623 l2 = pm->pm_l2[L2_IDX(l1idx)];
625 bzero(l2, sizeof(*l2));
627 * Link it into the parent pmap
629 pm->pm_l2[L2_IDX(l1idx)] = l2;
633 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
636 * Fetch pointer to the L2 page table associated with the address.
638 if (l2b->l2b_kva == NULL) {
642 * No L2 page table has been allocated. Chances are, this
643 * is because we just allocated the l2_dtable, above.
646 rw_wunlock(&pvh_global_lock);
647 ptep = uma_zalloc(l2zone, M_NOWAIT);
648 rw_wlock(&pvh_global_lock);
650 if (l2b->l2b_kva != 0) {
651 /* We lost the race. */
652 uma_zfree(l2zone, ptep);
655 l2b->l2b_phys = vtophys(ptep);
658 * Oops, no more L2 page tables available at this
659 * time. We may need to deallocate the l2_dtable
660 * if we allocated a new one above.
662 if (l2->l2_occupancy == 0) {
663 pm->pm_l2[L2_IDX(l1idx)] = NULL;
664 uma_zfree(l2table_zone, l2);
671 l2b->l2b_l1idx = l1idx;
677 static PMAP_INLINE void
678 pmap_free_l2_ptp(pt_entry_t *l2)
680 uma_zfree(l2zone, l2);
683 * One or more mappings in the specified L2 descriptor table have just been
686 * Garbage collect the metadata and descriptor table itself if necessary.
688 * The pmap lock must be acquired when this is called (not necessary
689 * for the kernel pmap).
692 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count)
694 struct l2_dtable *l2;
695 pd_entry_t *pl1pd, l1pd;
701 * Update the bucket's reference count according to how many
702 * PTEs the caller has just invalidated.
704 l2b->l2b_occupancy -= count;
709 * Level 2 page tables allocated to the kernel pmap are never freed
710 * as that would require checking all Level 1 page tables and
711 * removing any references to the Level 2 page table. See also the
712 * comment elsewhere about never freeing bootstrap L2 descriptors.
714 * We make do with just invalidating the mapping in the L2 table.
716 * This isn't really a big deal in practice and, in fact, leads
717 * to a performance win over time as we don't need to continually
720 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel())
724 * There are no more valid mappings in this level 2 page table.
725 * Go ahead and NULL-out the pointer in the bucket, then
726 * free the page table.
728 l1idx = l2b->l2b_l1idx;
732 pl1pd = &pm->pm_l1->l1_kva[l1idx];
735 * If the L1 slot matches the pmap's domain
736 * number, then invalidate it.
738 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK);
739 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) {
745 * Release the L2 descriptor table back to the pool cache.
747 pmap_free_l2_ptp(ptep);
750 * Update the reference count in the associated l2_dtable
752 l2 = pm->pm_l2[L2_IDX(l1idx)];
753 if (--l2->l2_occupancy > 0)
757 * There are no more valid mappings in any of the Level 1
758 * slots managed by this l2_dtable. Go ahead and NULL-out
759 * the pointer in the parent pmap and free the l2_dtable.
761 pm->pm_l2[L2_IDX(l1idx)] = NULL;
762 uma_zfree(l2table_zone, l2);
766 * Pool cache constructors for L2 descriptor tables, metadata and pmap
770 pmap_l2ptp_ctor(void *mem, int size, void *arg, int flags)
772 struct l2_bucket *l2b;
773 pt_entry_t *ptep, pte;
774 vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK;
777 * The mappings for these page tables were initially made using
778 * pmap_kenter() by the pool subsystem. Therefore, the cache-
779 * mode will not be right for page table mappings. To avoid
780 * polluting the pmap_kenter() code with a special case for
781 * page tables, we simply fix up the cache-mode here if it's not
784 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
785 ptep = &l2b->l2b_kva[l2pte_index(va)];
788 cpu_idcache_wbinv_range(va, PAGE_SIZE);
790 cpu_l2cache_wbinv_range(pte & L2_S_FRAME, PAGE_SIZE);
792 cpu_l2cache_wbinv_range(va, PAGE_SIZE);
794 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
796 * Page tables must have the cache-mode set to
799 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
801 cpu_tlb_flushD_SE(va);
805 memset(mem, 0, L2_TABLE_SIZE_REAL);
810 * Modify pte bits for all ptes corresponding to the given physical address.
811 * We use `maskbits' rather than `clearbits' because we're always passing
812 * constants and the latter would require an extra inversion at run-time.
815 pmap_clearbit(struct vm_page *pg, u_int maskbits)
817 struct l2_bucket *l2b;
819 pt_entry_t *ptep, npte, opte;
825 rw_wlock(&pvh_global_lock);
827 if (maskbits & PVF_WRITE)
830 * Clear saved attributes (modify, reference)
832 pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF));
834 if (TAILQ_EMPTY(&pg->md.pv_list)) {
835 rw_wunlock(&pvh_global_lock);
840 * Loop over all current mappings setting/clearing as appropos
842 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
845 oflags = pv->pv_flags;
846 pv->pv_flags &= ~maskbits;
850 l2b = pmap_get_l2_bucket(pm, va);
852 ptep = &l2b->l2b_kva[l2pte_index(va)];
855 if ((maskbits & (PVF_WRITE|PVF_MOD)) && L2_S_WRITABLE(opte)) {
858 /* make the pte read only */
862 if (maskbits & PVF_REF) {
864 * Make the PTE invalid so that we will take a
865 * page fault the next time the mapping is
868 npte &= ~L2_TYPE_MASK;
872 CTR4(KTR_PMAP,"clearbit: pmap:%p bits:%x pte:%x->%x",
873 pm, maskbits, opte, npte);
878 /* Flush the TLB entry if a current pmap. */
879 if (PV_BEEN_EXECD(oflags))
880 cpu_tlb_flushID_SE(pv->pv_va);
881 else if (PV_BEEN_REFD(oflags))
882 cpu_tlb_flushD_SE(pv->pv_va);
889 if (maskbits & PVF_WRITE)
890 vm_page_aflag_clear(pg, PGA_WRITEABLE);
891 rw_wunlock(&pvh_global_lock);
896 * main pv_entry manipulation functions:
897 * pmap_enter_pv: enter a mapping onto a vm_page list
898 * pmap_remove_pv: remove a mappiing from a vm_page list
900 * NOTE: pmap_enter_pv expects to lock the pvh itself
901 * pmap_remove_pv expects the caller to lock the pvh before calling
905 * pmap_enter_pv: enter a mapping onto a vm_page's PV list
907 * => caller should hold the proper lock on pvh_global_lock
908 * => caller should have pmap locked
909 * => we will (someday) gain the lock on the vm_page's PV list
910 * => caller should adjust ptp's wire_count before calling
911 * => caller should not adjust pmap's wire_count
914 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm,
915 vm_offset_t va, u_int flags)
918 rw_assert(&pvh_global_lock, RA_WLOCKED);
920 PMAP_ASSERT_LOCKED(pm);
923 pve->pv_flags = flags;
925 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list);
926 TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist);
927 pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD);
928 if (pve->pv_flags & PVF_WIRED)
929 ++pm->pm_stats.wired_count;
930 vm_page_aflag_set(pg, PGA_REFERENCED);
935 * pmap_find_pv: Find a pv entry
937 * => caller should hold lock on vm_page
939 static PMAP_INLINE struct pv_entry *
940 pmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
944 rw_assert(&pvh_global_lock, RA_WLOCKED);
945 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list)
946 if (pm == pv->pv_pmap && va == pv->pv_va)
952 * vector_page_setprot:
954 * Manipulate the protection of the vector page.
957 vector_page_setprot(int prot)
959 struct l2_bucket *l2b;
962 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page);
964 ptep = &l2b->l2b_kva[l2pte_index(vector_page)];
966 pmap_set_prot(ptep, prot|VM_PROT_EXECUTE, 0);
968 cpu_tlb_flushD_SE(vector_page);
973 pmap_set_prot(pt_entry_t *ptep, vm_prot_t prot, uint8_t user)
976 *ptep &= ~L2_S_PROT_MASK;
978 if (!(prot & VM_PROT_EXECUTE))
981 *ptep |= L2_S_PROT_R;
984 *ptep |= L2_S_PROT_U;
986 if (prot & VM_PROT_WRITE)
991 * pmap_remove_pv: try to remove a mapping from a pv_list
993 * => caller should hold proper lock on pmap_main_lock
994 * => pmap should be locked
995 * => caller should hold lock on vm_page [so that attrs can be adjusted]
996 * => caller should adjust ptp's wire_count and free PTP if needed
997 * => caller should NOT adjust pmap's wire_count
998 * => we return the removed pve
1002 pmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve)
1005 rw_assert(&pvh_global_lock, RA_WLOCKED);
1006 PMAP_ASSERT_LOCKED(pm);
1008 TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list);
1009 TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist);
1011 if (pve->pv_flags & PVF_WIRED)
1012 --pm->pm_stats.wired_count;
1014 if (pg->md.pvh_attrs & PVF_MOD)
1017 if (TAILQ_FIRST(&pg->md.pv_list) == NULL)
1018 pg->md.pvh_attrs &= ~PVF_REF;
1020 vm_page_aflag_set(pg, PGA_REFERENCED);
1022 if (pve->pv_flags & PVF_WRITE) {
1023 TAILQ_FOREACH(pve, &pg->md.pv_list, pv_list)
1024 if (pve->pv_flags & PVF_WRITE)
1027 pg->md.pvh_attrs &= ~PVF_MOD;
1028 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1033 static struct pv_entry *
1034 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1036 struct pv_entry *pve;
1038 rw_assert(&pvh_global_lock, RA_WLOCKED);
1039 pve = TAILQ_FIRST(&pg->md.pv_list);
1042 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */
1043 pmap_nuke_pv(pg, pm, pve);
1046 pve = TAILQ_NEXT(pve, pv_list);
1049 return(pve); /* return removed pve */
1054 * pmap_modify_pv: Update pv flags
1056 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1057 * => caller should NOT adjust pmap's wire_count
1058 * => we return the old flags
1060 * Modify a physical-virtual mapping in the pv table
1063 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va,
1064 u_int clr_mask, u_int set_mask)
1066 struct pv_entry *npv;
1067 u_int flags, oflags;
1069 PMAP_ASSERT_LOCKED(pm);
1070 rw_assert(&pvh_global_lock, RA_WLOCKED);
1071 if ((npv = pmap_find_pv(pg, pm, va)) == NULL)
1075 * There is at least one VA mapping this page.
1078 if (clr_mask & (PVF_REF | PVF_MOD))
1079 pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD);
1081 oflags = npv->pv_flags;
1082 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask;
1084 if ((flags ^ oflags) & PVF_WIRED) {
1085 if (flags & PVF_WIRED)
1086 ++pm->pm_stats.wired_count;
1088 --pm->pm_stats.wired_count;
1090 if ((oflags & PVF_WRITE) && !(flags & PVF_WRITE)) {
1091 TAILQ_FOREACH(npv, &pg->md.pv_list, pv_list) {
1092 if (npv->pv_flags & PVF_WRITE)
1096 pg->md.pvh_attrs &= ~PVF_MOD;
1097 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1104 /* Function to set the debug level of the pmap code */
1107 pmap_debug(int level)
1109 pmap_debug_level = level;
1110 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
1112 #endif /* PMAP_DEBUG */
1115 pmap_pinit0(struct pmap *pmap)
1117 PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap));
1119 dprintf("pmap_pinit0: pmap = %08x, pm_pdir = %08x\n",
1120 (u_int32_t) pmap, (u_int32_t) pmap->pm_pdir);
1121 bcopy(kernel_pmap, pmap, sizeof(*pmap));
1122 bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx));
1123 PMAP_LOCK_INIT(pmap);
1127 * Initialize a vm_page's machine-dependent fields.
1130 pmap_page_init(vm_page_t m)
1133 TAILQ_INIT(&m->md.pv_list);
1134 m->md.pv_memattr = VM_MEMATTR_DEFAULT;
1138 * Initialize the pmap module.
1139 * Called by vm_init, to initialize any structures that the pmap
1140 * system needs to map virtual memory.
1145 int shpgperproc = PMAP_SHPGPERPROC;
1147 PDEBUG(1, printf("pmap_init: phys_start = %08x\n", PHYSADDR));
1149 l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor,
1150 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1151 l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable), NULL,
1152 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1155 * Initialize the PV entry allocator.
1157 pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL,
1158 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1159 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1160 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
1161 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max);
1162 pv_entry_high_water = 9 * (pv_entry_max / 10);
1165 * Now it is safe to enable pv_table recording.
1167 PDEBUG(1, printf("pmap_init: done!\n"));
1171 pmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user)
1173 struct l2_dtable *l2;
1174 struct l2_bucket *l2b;
1175 pd_entry_t *pl1pd, l1pd;
1176 pt_entry_t *ptep, pte;
1182 rw_wlock(&pvh_global_lock);
1186 * If there is no l2_dtable for this address, then the process
1187 * has no business accessing it.
1189 * Note: This will catch userland processes trying to access
1192 l2 = pm->pm_l2[L2_IDX(l1idx)];
1197 * Likewise if there is no L2 descriptor table
1199 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
1200 if (l2b->l2b_kva == NULL)
1204 * Check the PTE itself.
1206 ptep = &l2b->l2b_kva[l2pte_index(va)];
1212 * Catch a userland access to the vector page mapped at 0x0
1214 if (user && ((pte & L2_S_PROT_MASK) == L2_S_PROT_U))
1216 if (va == vector_page)
1220 CTR5(KTR_PMAP, "pmap_fault_fix: pmap:%p va:%x pte:0x%x ftype:%x user:%x",
1221 pm, va, pte, ftype, user);
1222 if ((ftype & VM_PROT_WRITE) && !(L2_S_WRITABLE(pte))) {
1224 * This looks like a good candidate for "page modified"
1227 struct pv_entry *pv;
1230 /* Extract the physical address of the page */
1231 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) {
1234 /* Get the current flags for this page. */
1236 pv = pmap_find_pv(pg, pm, va);
1242 * Do the flags say this page is writable? If not then it
1243 * is a genuine write fault. If yes then the write fault is
1244 * our fault as we did not reflect the write access in the
1245 * PTE. Now we know a write has occurred we can correct this
1246 * and also set the modified bit
1248 if ((pv->pv_flags & PVF_WRITE) == 0) {
1251 pg->md.pvh_attrs |= PVF_REF | PVF_MOD;
1253 pv->pv_flags |= PVF_REF | PVF_MOD;
1255 /* Re-enable write permissions for the page */
1256 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO;
1257 pmap_set_prot(ptep, VM_PROT_WRITE, *ptep & L2_S_PROT_U);
1258 CTR1(KTR_PMAP, "pmap_fault_fix: new pte:0x%x", pte);
1261 } else if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) {
1263 * This looks like a good candidate for "page referenced"
1266 struct pv_entry *pv;
1269 /* Extract the physical address of the page */
1270 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL)
1272 /* Get the current flags for this page. */
1274 pv = pmap_find_pv(pg, pm, va);
1278 pg->md.pvh_attrs |= PVF_REF;
1279 pv->pv_flags |= PVF_REF;
1282 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO;
1288 * We know there is a valid mapping here, so simply
1289 * fix up the L1 if necessary.
1291 pl1pd = &pm->pm_l1->l1_kva[l1idx];
1292 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO;
1293 if (*pl1pd != l1pd) {
1301 * If 'rv == 0' at this point, it generally indicates that there is a
1302 * stale TLB entry for the faulting address. This happens when two or
1303 * more processes are sharing an L1. Since we don't flush the TLB on
1304 * a context switch between such processes, we can take domain faults
1305 * for mappings which exist at the same VA in both processes. EVEN IF
1306 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for
1309 * This is extremely likely to happen if pmap_enter() updated the L1
1310 * entry for a recently entered mapping. In this case, the TLB is
1311 * flushed for the new mapping, but there may still be TLB entries for
1312 * other mappings belonging to other processes in the 1MB range
1313 * covered by the L1 entry.
1315 * Since 'rv == 0', we know that the L1 already contains the correct
1316 * value, so the fault must be due to a stale TLB entry.
1318 * Since we always need to flush the TLB anyway in the case where we
1319 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with
1320 * stale TLB entries dynamically.
1322 * However, the above condition can ONLY happen if the current L1 is
1323 * being shared. If it happens when the L1 is unshared, it indicates
1324 * that other parts of the pmap are not doing their job WRT managing
1327 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) {
1328 printf("fixup: pm %p, va 0x%08x, ftype %d - nothing to do!\n",
1330 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n",
1331 l2, l2b, ptep, pl1pd);
1332 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n",
1333 pte, l1pd, last_fault_code);
1340 cpu_tlb_flushID_SE(va);
1346 rw_wunlock(&pvh_global_lock);
1354 struct l2_bucket *l2b;
1355 struct l1_ttable *l1;
1357 pt_entry_t *ptep, pte;
1358 vm_offset_t va, eva;
1361 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0);
1363 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK);
1365 for (loop = 0; loop < needed; loop++, l1++) {
1366 /* Allocate a L1 page table */
1367 va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0,
1368 0xffffffff, L1_TABLE_SIZE, 0);
1371 panic("Cannot allocate L1 KVM");
1373 eva = va + L1_TABLE_SIZE;
1374 pl1pt = (pd_entry_t *)va;
1377 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
1378 ptep = &l2b->l2b_kva[l2pte_index(va)];
1380 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
1383 cpu_tlb_flushD_SE(va);
1387 pmap_init_l1(l1, pl1pt);
1390 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n",
1396 * This is used to stuff certain critical values into the PCB where they
1397 * can be accessed quickly from cpu_switch() et al.
1400 pmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb)
1402 struct l2_bucket *l2b;
1404 pcb->pcb_pagedir = pm->pm_l1->l1_physaddr;
1405 pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) |
1406 (DOMAIN_CLIENT << (pm->pm_domain * 2));
1408 if (vector_page < KERNBASE) {
1409 pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)];
1410 l2b = pmap_get_l2_bucket(pm, vector_page);
1411 pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO |
1412 L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL);
1414 pcb->pcb_pl1vec = NULL;
1418 pmap_activate(struct thread *td)
1423 pm = vmspace_pmap(td->td_proc->p_vmspace);
1427 pmap_set_pcb_pagedir(pm, pcb);
1429 if (td == curthread) {
1430 u_int cur_dacr, cur_ttb;
1432 __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb));
1433 __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr));
1435 cur_ttb &= ~(L1_TABLE_SIZE - 1);
1437 if (cur_ttb == (u_int)pcb->pcb_pagedir &&
1438 cur_dacr == pcb->pcb_dacr) {
1440 * No need to switch address spaces.
1448 * We MUST, I repeat, MUST fix up the L1 entry corresponding
1449 * to 'vector_page' in the incoming L1 table before switching
1450 * to it otherwise subsequent interrupts/exceptions (including
1451 * domain faults!) will jump into hyperspace.
1453 if (pcb->pcb_pl1vec) {
1454 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
1457 cpu_domains(pcb->pcb_dacr);
1458 cpu_setttb(pcb->pcb_pagedir);
1464 pmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va)
1466 pd_entry_t *pdep, pde;
1467 pt_entry_t *ptep, pte;
1472 * Make sure the descriptor itself has the correct cache mode
1474 pdep = &kl1[L1_IDX(va)];
1477 if (l1pte_section_p(pde)) {
1478 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) {
1479 *pdep = (pde & ~L1_S_CACHE_MASK) |
1480 pte_l1_s_cache_mode_pt;
1485 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
1486 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
1488 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep);
1490 ptep = &ptep[l2pte_index(va)];
1492 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
1493 *ptep = (pte & ~L2_S_CACHE_MASK) |
1494 pte_l2_s_cache_mode_pt;
1504 pmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap,
1507 vm_offset_t va = *availp;
1508 struct l2_bucket *l2b;
1511 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
1513 panic("pmap_alloc_specials: no l2b for 0x%x", va);
1515 *ptep = &l2b->l2b_kva[l2pte_index(va)];
1519 *availp = va + (PAGE_SIZE * pages);
1523 * Bootstrap the system enough to run with virtual memory.
1525 * On the arm this is called after mapping has already been enabled
1526 * and just syncs the pmap module with what has already been done.
1527 * [We can't call it easily with mapping off since the kernel is not
1528 * mapped with PA == VA, hence we would have to relocate every address
1529 * from the linked base (virtual) address "KERNBASE" to the actual
1530 * (physical) address starting relative to 0]
1532 #define PMAP_STATIC_L2_SIZE 16
1535 pmap_bootstrap(vm_offset_t firstaddr, vm_offset_t lastaddr, struct pv_addr *l1pt)
1537 static struct l1_ttable static_l1;
1538 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE];
1539 struct l1_ttable *l1 = &static_l1;
1540 struct l2_dtable *l2;
1541 struct l2_bucket *l2b;
1543 pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va;
1548 int l1idx, l2idx, l2next = 0;
1550 PDEBUG(1, printf("firstaddr = %08x, lastaddr = %08x\n",
1551 firstaddr, lastaddr));
1553 virtual_avail = firstaddr;
1554 kernel_pmap->pm_l1 = l1;
1555 kernel_l1pa = l1pt->pv_pa;
1558 * Scan the L1 translation table created by initarm() and create
1559 * the required metadata for all valid mappings found in it.
1561 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) {
1562 pde = kernel_l1pt[l1idx];
1565 * We're only interested in Coarse mappings.
1566 * pmap_extract() can deal with section mappings without
1567 * recourse to checking L2 metadata.
1569 if ((pde & L1_TYPE_MASK) != L1_TYPE_C)
1573 * Lookup the KVA of this L2 descriptor table
1575 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
1576 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
1579 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx",
1580 (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa);
1584 * Fetch the associated L2 metadata structure.
1585 * Allocate a new one if necessary.
1587 if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) {
1588 if (l2next == PMAP_STATIC_L2_SIZE)
1589 panic("pmap_bootstrap: out of static L2s");
1590 kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 =
1591 &static_l2[l2next++];
1595 * One more L1 slot tracked...
1600 * Fill in the details of the L2 descriptor in the
1601 * appropriate bucket.
1603 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
1604 l2b->l2b_kva = ptep;
1606 l2b->l2b_l1idx = l1idx;
1609 * Establish an initial occupancy count for this descriptor
1612 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
1614 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) {
1615 l2b->l2b_occupancy++;
1620 * Make sure the descriptor itself has the correct cache mode.
1621 * If not, fix it, but whine about the problem. Port-meisters
1622 * should consider this a clue to fix up their initarm()
1625 if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) {
1626 printf("pmap_bootstrap: WARNING! wrong cache mode for "
1627 "L2 pte @ %p\n", ptep);
1633 * Ensure the primary (kernel) L1 has the correct cache mode for
1634 * a page table. Bitch if it is not correctly set.
1636 for (va = (vm_offset_t)kernel_l1pt;
1637 va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) {
1638 if (pmap_set_pt_cache_mode(kernel_l1pt, va))
1639 printf("pmap_bootstrap: WARNING! wrong cache mode for "
1640 "primary L1 @ 0x%x\n", va);
1643 cpu_dcache_wbinv_all();
1644 cpu_l2cache_wbinv_all();
1648 PMAP_LOCK_INIT(kernel_pmap);
1649 CPU_FILL(&kernel_pmap->pm_active);
1650 kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL;
1651 TAILQ_INIT(&kernel_pmap->pm_pvlist);
1654 * Initialize the global pv list lock.
1656 rw_init(&pvh_global_lock, "pmap pv global");
1659 * Reserve some special page table entries/VA space for temporary
1663 pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte);
1664 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte);
1665 pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte);
1666 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte);
1667 size = ((lastaddr - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE;
1668 pmap_alloc_specials(&virtual_avail,
1669 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE,
1670 &pmap_kernel_l2ptp_kva, NULL);
1672 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE;
1673 pmap_alloc_specials(&virtual_avail,
1674 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE,
1675 &pmap_kernel_l2dtable_kva, NULL);
1677 pmap_alloc_specials(&virtual_avail,
1678 1, (vm_offset_t*)&_tmppt, NULL);
1679 pmap_alloc_specials(&virtual_avail,
1680 MAXDUMPPGS, (vm_offset_t *)&crashdumpmap, NULL);
1681 SLIST_INIT(&l1_list);
1682 TAILQ_INIT(&l1_lru_list);
1683 mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF);
1684 pmap_init_l1(l1, kernel_l1pt);
1685 cpu_dcache_wbinv_all();
1686 cpu_l2cache_wbinv_all();
1688 virtual_avail = round_page(virtual_avail);
1689 virtual_end = lastaddr;
1690 kernel_vm_end = pmap_curmaxkvaddr;
1691 arm_nocache_startaddr = lastaddr;
1692 mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF);
1694 pmap_set_pcb_pagedir(kernel_pmap, thread0.td_pcb);
1697 /***************************************************
1698 * Pmap allocation/deallocation routines.
1699 ***************************************************/
1702 * Release any resources held by the given physical map.
1703 * Called when a pmap initialized by pmap_pinit is being released.
1704 * Should only be called if the map contains no valid mappings.
1707 pmap_release(pmap_t pmap)
1711 cpu_idcache_wbinv_all();
1712 cpu_l2cache_wbinv_all();
1715 if (vector_page < KERNBASE) {
1716 struct pcb *curpcb = PCPU_GET(curpcb);
1717 pcb = thread0.td_pcb;
1718 if (pmap_is_current(pmap)) {
1720 * Frob the L1 entry corresponding to the vector
1721 * page so that it contains the kernel pmap's domain
1722 * number. This will ensure pmap_remove() does not
1723 * pull the current vector page out from under us.
1726 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
1727 cpu_domains(pcb->pcb_dacr);
1728 cpu_setttb(pcb->pcb_pagedir);
1731 pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE);
1733 * Make sure cpu_switch(), et al, DTRT. This is safe to do
1734 * since this process has no remaining mappings of its own.
1736 curpcb->pcb_pl1vec = pcb->pcb_pl1vec;
1737 curpcb->pcb_l1vec = pcb->pcb_l1vec;
1738 curpcb->pcb_dacr = pcb->pcb_dacr;
1739 curpcb->pcb_pagedir = pcb->pcb_pagedir;
1743 PMAP_LOCK_DESTROY(pmap);
1745 dprintf("pmap_release()\n");
1751 * Helper function for pmap_grow_l2_bucket()
1754 pmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap)
1756 struct l2_bucket *l2b;
1761 pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
1764 pa = VM_PAGE_TO_PHYS(pg);
1769 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
1771 ptep = &l2b->l2b_kva[l2pte_index(va)];
1772 *ptep = L2_S_PROTO | pa | cache_mode;
1773 pmap_set_prot(ptep, VM_PROT_READ | VM_PROT_WRITE, 0);
1780 * This is the same as pmap_alloc_l2_bucket(), except that it is only
1781 * used by pmap_growkernel().
1783 static __inline struct l2_bucket *
1784 pmap_grow_l2_bucket(pmap_t pm, vm_offset_t va)
1786 struct l2_dtable *l2;
1787 struct l2_bucket *l2b;
1788 struct l1_ttable *l1;
1795 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
1797 * No mapping at this address, as there is
1798 * no entry in the L1 table.
1799 * Need to allocate a new l2_dtable.
1801 nva = pmap_kernel_l2dtable_kva;
1802 if ((nva & PAGE_MASK) == 0) {
1804 * Need to allocate a backing page
1806 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
1810 l2 = (struct l2_dtable *)nva;
1811 nva += sizeof(struct l2_dtable);
1813 if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva &
1816 * The new l2_dtable straddles a page boundary.
1817 * Map in another page to cover it.
1819 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
1823 pmap_kernel_l2dtable_kva = nva;
1826 * Link it into the parent pmap
1828 pm->pm_l2[L2_IDX(l1idx)] = l2;
1829 memset(l2, 0, sizeof(*l2));
1832 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
1835 * Fetch pointer to the L2 page table associated with the address.
1837 if (l2b->l2b_kva == NULL) {
1841 * No L2 page table has been allocated. Chances are, this
1842 * is because we just allocated the l2_dtable, above.
1844 nva = pmap_kernel_l2ptp_kva;
1845 ptep = (pt_entry_t *)nva;
1846 if ((nva & PAGE_MASK) == 0) {
1848 * Need to allocate a backing page
1850 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt,
1851 &pmap_kernel_l2ptp_phys))
1854 memset(ptep, 0, L2_TABLE_SIZE_REAL);
1856 l2b->l2b_kva = ptep;
1857 l2b->l2b_l1idx = l1idx;
1858 l2b->l2b_phys = pmap_kernel_l2ptp_phys;
1860 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL;
1861 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL;
1864 /* Distribute new L1 entry to all other L1s */
1865 SLIST_FOREACH(l1, &l1_list, l1_link) {
1866 pl1pd = &l1->l1_kva[L1_IDX(va)];
1867 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) |
1877 * grow the number of kernel page table entries, if needed
1880 pmap_growkernel(vm_offset_t addr)
1882 pmap_t kpm = pmap_kernel();
1884 if (addr <= pmap_curmaxkvaddr)
1885 return; /* we are OK */
1888 * whoops! we need to add kernel PTPs
1891 /* Map 1MB at a time */
1892 for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE)
1893 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr);
1896 * flush out the cache, expensive but growkernel will happen so
1899 cpu_dcache_wbinv_all();
1900 cpu_l2cache_wbinv_all();
1903 kernel_vm_end = pmap_curmaxkvaddr;
1908 * Remove all pages from specified address space
1909 * this aids process exit speeds. Also, this code
1910 * is special cased for current process only, but
1911 * can have the more generic (and slightly slower)
1912 * mode enabled. This is much faster than pmap_remove
1913 * in the case of running down an entire address space.
1916 pmap_remove_pages(pmap_t pmap)
1918 struct pv_entry *pv, *npv;
1919 struct l2_bucket *l2b = NULL;
1923 rw_wlock(&pvh_global_lock);
1925 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) {
1926 if (pv->pv_flags & PVF_WIRED) {
1927 /* Cannot remove wired pages now. */
1928 npv = TAILQ_NEXT(pv, pv_plist);
1931 pmap->pm_stats.resident_count--;
1932 l2b = pmap_get_l2_bucket(pmap, pv->pv_va);
1933 KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages"));
1934 pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
1935 m = PHYS_TO_VM_PAGE(*pt & L2_ADDR_MASK);
1936 KASSERT((vm_offset_t)m >= KERNBASE, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt));
1939 npv = TAILQ_NEXT(pv, pv_plist);
1940 pmap_nuke_pv(m, pmap, pv);
1941 if (TAILQ_EMPTY(&m->md.pv_list))
1942 vm_page_aflag_clear(m, PGA_WRITEABLE);
1943 pmap_free_pv_entry(pv);
1944 pmap_free_l2_bucket(pmap, l2b, 1);
1946 rw_wunlock(&pvh_global_lock);
1953 /***************************************************
1954 * Low level mapping routines.....
1955 ***************************************************/
1957 #ifdef ARM_HAVE_SUPERSECTIONS
1958 /* Map a super section into the KVA. */
1961 pmap_kenter_supersection(vm_offset_t va, uint64_t pa, int flags)
1963 pd_entry_t pd = L1_S_PROTO | L1_S_SUPERSEC | (pa & L1_SUP_FRAME) |
1964 (((pa >> 32) & 0xf) << 20) | L1_S_PROT(PTE_KERNEL,
1965 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
1966 struct l1_ttable *l1;
1967 vm_offset_t va0, va_end;
1969 KASSERT(((va | pa) & L1_SUP_OFFSET) == 0,
1970 ("Not a valid super section mapping"));
1971 if (flags & SECTION_CACHE)
1972 pd |= pte_l1_s_cache_mode;
1973 else if (flags & SECTION_PT)
1974 pd |= pte_l1_s_cache_mode_pt;
1976 va0 = va & L1_SUP_FRAME;
1977 va_end = va + L1_SUP_SIZE;
1978 SLIST_FOREACH(l1, &l1_list, l1_link) {
1980 for (; va < va_end; va += L1_S_SIZE) {
1981 l1->l1_kva[L1_IDX(va)] = pd;
1982 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
1988 /* Map a section into the KVA. */
1991 pmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags)
1993 pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL,
1994 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
1995 struct l1_ttable *l1;
1997 KASSERT(((va | pa) & L1_S_OFFSET) == 0,
1998 ("Not a valid section mapping"));
1999 if (flags & SECTION_CACHE)
2000 pd |= pte_l1_s_cache_mode;
2001 else if (flags & SECTION_PT)
2002 pd |= pte_l1_s_cache_mode_pt;
2004 SLIST_FOREACH(l1, &l1_list, l1_link) {
2005 l1->l1_kva[L1_IDX(va)] = pd;
2006 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2011 * Make a temporary mapping for a physical address. This is only intended
2012 * to be used for panic dumps.
2015 pmap_kenter_temp(vm_paddr_t pa, int i)
2019 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
2020 pmap_kenter(va, pa);
2021 return ((void *)crashdumpmap);
2025 * add a wired page to the kva
2026 * note that in order for the mapping to take effect -- you
2027 * should do a invltlb after doing the pmap_kenter...
2029 static PMAP_INLINE void
2030 pmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags)
2032 struct l2_bucket *l2b;
2036 PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n",
2037 (uint32_t) va, (uint32_t) pa));
2040 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2042 l2b = pmap_grow_l2_bucket(pmap_kernel(), va);
2043 KASSERT(l2b != NULL, ("No L2 Bucket"));
2045 pte = &l2b->l2b_kva[l2pte_index(va)];
2047 if (l2pte_valid(opte)) {
2048 cpu_tlb_flushD_SE(va);
2052 l2b->l2b_occupancy++;
2055 if (flags & KENTER_CACHE) {
2056 *pte = L2_S_PROTO | pa | pte_l2_s_cache_mode;
2057 pmap_set_prot(pte, VM_PROT_READ | VM_PROT_WRITE,
2058 flags & KENTER_USER);
2060 *pte = L2_S_PROTO | pa;
2061 pmap_set_prot(pte, VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE,
2065 PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n",
2066 (uint32_t) pte, opte, *pte));
2072 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2074 pmap_kenter_internal(va, pa, KENTER_CACHE);
2078 pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa)
2081 pmap_kenter_internal(va, pa, 0);
2085 pmap_kenter_user(vm_offset_t va, vm_paddr_t pa)
2088 pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER);
2090 * Call pmap_fault_fixup now, to make sure we'll have no exception
2091 * at the first use of the new address, or bad things will happen,
2092 * as we use one of these addresses in the exception handlers.
2094 pmap_fault_fixup(pmap_kernel(), va, VM_PROT_READ|VM_PROT_WRITE, 1);
2098 pmap_kextract(vm_offset_t va)
2101 return (pmap_extract_locked(kernel_pmap, va));
2105 * remove a page from the kernel pagetables
2108 pmap_kremove(vm_offset_t va)
2110 struct l2_bucket *l2b;
2111 pt_entry_t *pte, opte;
2113 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2116 KASSERT(l2b != NULL, ("No L2 Bucket"));
2117 pte = &l2b->l2b_kva[l2pte_index(va)];
2119 if (l2pte_valid(opte)) {
2120 va = va & ~PAGE_MASK;
2121 cpu_tlb_flushD_SE(va);
2129 * Used to map a range of physical addresses into kernel
2130 * virtual address space.
2132 * The value passed in '*virt' is a suggested virtual address for
2133 * the mapping. Architectures which can support a direct-mapped
2134 * physical to virtual region can return the appropriate address
2135 * within that region, leaving '*virt' unchanged. Other
2136 * architectures should map the pages starting at '*virt' and
2137 * update '*virt' with the first usable address after the mapped
2141 pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot)
2143 vm_offset_t sva = *virt;
2144 vm_offset_t va = sva;
2146 PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, "
2147 "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end,
2150 while (start < end) {
2151 pmap_kenter(va, start);
2160 * Add a list of wired pages to the kva
2161 * this routine is only used for temporary
2162 * kernel mappings that do not need to have
2163 * page modification or references recorded.
2164 * Note that old mappings are simply written
2165 * over. The page *must* be wired.
2168 pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
2172 for (i = 0; i < count; i++) {
2173 pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]),
2181 * this routine jerks page mappings from the
2182 * kernel -- it is meant only for temporary mappings.
2185 pmap_qremove(vm_offset_t va, int count)
2189 for (i = 0; i < count; i++) {
2199 * pmap_object_init_pt preloads the ptes for a given object
2200 * into the specified pmap. This eliminates the blast of soft
2201 * faults on process startup and immediately after an mmap.
2204 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
2205 vm_pindex_t pindex, vm_size_t size)
2208 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
2209 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2210 ("pmap_object_init_pt: non-device object"));
2215 * pmap_is_prefaultable:
2217 * Return whether or not the specified virtual address is elgible
2221 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
2226 if (!pmap_get_pde_pte(pmap, addr, &pde, &pte))
2228 KASSERT(pte != NULL, ("Valid mapping but no pte ?"));
2235 * Fetch pointers to the PDE/PTE for the given pmap/VA pair.
2236 * Returns TRUE if the mapping exists, else FALSE.
2238 * NOTE: This function is only used by a couple of arm-specific modules.
2239 * It is not safe to take any pmap locks here, since we could be right
2240 * in the middle of debugging the pmap anyway...
2242 * It is possible for this routine to return FALSE even though a valid
2243 * mapping does exist. This is because we don't lock, so the metadata
2244 * state may be inconsistent.
2246 * NOTE: We can return a NULL *ptp in the case where the L1 pde is
2247 * a "section" mapping.
2250 pmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp)
2252 struct l2_dtable *l2;
2253 pd_entry_t *pl1pd, l1pd;
2257 if (pm->pm_l1 == NULL)
2261 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx];
2264 if (l1pte_section_p(l1pd)) {
2269 if (pm->pm_l2 == NULL)
2272 l2 = pm->pm_l2[L2_IDX(l1idx)];
2275 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
2279 *ptp = &ptep[l2pte_index(va)];
2284 * Routine: pmap_remove_all
2286 * Removes this physical page from
2287 * all physical maps in which it resides.
2288 * Reflects back modify bits to the pager.
2291 * Original versions of this routine were very
2292 * inefficient because they iteratively called
2293 * pmap_remove (slow...)
2296 pmap_remove_all(vm_page_t m)
2300 struct l2_bucket *l2b;
2301 boolean_t flush = FALSE;
2305 KASSERT((m->flags & PG_FICTITIOUS) == 0,
2306 ("pmap_remove_all: page %p is fictitious", m));
2308 if (TAILQ_EMPTY(&m->md.pv_list))
2310 rw_wlock(&pvh_global_lock);
2311 curpm = vmspace_pmap(curproc->p_vmspace);
2312 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2313 if (flush == FALSE && (pv->pv_pmap == curpm ||
2314 pv->pv_pmap == pmap_kernel()))
2317 PMAP_LOCK(pv->pv_pmap);
2318 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
2319 KASSERT(l2b != NULL, ("No l2 bucket"));
2320 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
2321 if (L2_S_WRITABLE(*ptep))
2324 if (pmap_is_current(pv->pv_pmap))
2326 pmap_free_l2_bucket(pv->pv_pmap, l2b, 1);
2327 pv->pv_pmap->pm_stats.resident_count--;
2328 flags |= pv->pv_flags;
2329 pmap_nuke_pv(m, pv->pv_pmap, pv);
2330 PMAP_UNLOCK(pv->pv_pmap);
2331 pmap_free_pv_entry(pv);
2333 m->md.pvh_attrs &= ~(PVF_MOD | PVF_REF);
2336 if (PV_BEEN_EXECD(flags))
2341 vm_page_aflag_clear(m, PGA_WRITEABLE);
2342 rw_wunlock(&pvh_global_lock);
2346 pmap_change_attr(vm_offset_t sva, vm_size_t len, int mode)
2348 vm_offset_t base, offset, tmpva;
2350 struct l2_bucket *l2b;
2351 pt_entry_t *ptep, pte;
2352 vm_offset_t next_bucket;
2354 PMAP_LOCK(kernel_pmap);
2356 base = trunc_page(sva);
2357 offset = sva & PAGE_MASK;
2358 size = roundup(offset + len, PAGE_SIZE);
2362 * Only supported on kernel virtual addresses, including the direct
2363 * map but excluding the recursive map.
2365 if (base < DMAP_MIN_ADDRESS) {
2366 PMAP_UNLOCK(kernel_pmap);
2370 for (tmpva = base; tmpva < base + size; ) {
2371 next_bucket = L2_NEXT_BUCKET(tmpva);
2372 if (next_bucket > base + size)
2373 next_bucket = base + size;
2375 l2b = pmap_get_l2_bucket(kernel_pmap, tmpva);
2377 tmpva = next_bucket;
2381 ptep = &l2b->l2b_kva[l2pte_index(tmpva)];
2384 PMAP_UNLOCK(kernel_pmap);
2388 pte = *ptep &~ L2_S_CACHE_MASK;
2389 cpu_idcache_wbinv_range(tmpva, PAGE_SIZE);
2391 cpu_l2cache_wbinv_range(pte & L2_S_FRAME, PAGE_SIZE);
2393 cpu_l2cache_wbinv_range(tmpva, PAGE_SIZE);
2396 cpu_tlb_flushID_SE(tmpva);
2398 dprintf("%s: for va:%x ptep:%x pte:%x\n",
2399 __func__, tmpva, (uint32_t)ptep, pte);
2403 PMAP_UNLOCK(kernel_pmap);
2409 * Set the physical protection on the
2410 * specified range of this map as requested.
2413 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2415 struct l2_bucket *l2b;
2416 pt_entry_t *ptep, pte;
2417 vm_offset_t next_bucket;
2421 if ((prot & VM_PROT_READ) == 0) {
2422 pmap_remove(pm, sva, eva);
2426 if (prot & VM_PROT_WRITE) {
2428 * If this is a read->write transition, just ignore it and let
2429 * vm_fault() take care of it later.
2434 rw_wlock(&pvh_global_lock);
2438 * OK, at this point, we know we're doing write-protect operation.
2439 * If the pmap is active, write-back the range.
2442 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1;
2446 next_bucket = L2_NEXT_BUCKET(sva);
2447 if (next_bucket > eva)
2450 l2b = pmap_get_l2_bucket(pm, sva);
2456 ptep = &l2b->l2b_kva[l2pte_index(sva)];
2458 while (sva < next_bucket) {
2459 if ((pte = *ptep) != 0 && L2_S_WRITABLE(pte)) {
2463 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
2464 pmap_set_prot(ptep, prot, !(pm == pmap_kernel()));
2467 f = pmap_modify_pv(pg, pm, sva,
2476 if (PV_BEEN_EXECD(f))
2477 cpu_tlb_flushID_SE(sva);
2479 if (PV_BEEN_REFD(f))
2480 cpu_tlb_flushD_SE(sva);
2490 if (PV_BEEN_EXECD(flags))
2493 if (PV_BEEN_REFD(flags))
2496 rw_wunlock(&pvh_global_lock);
2503 * Insert the given physical page (p) at
2504 * the specified virtual address (v) in the
2505 * target physical map with the protection requested.
2507 * If specified, the page will be wired down, meaning
2508 * that the related pte can not be reclaimed.
2510 * NB: This is the only routine which MAY NOT lazy-evaluate
2511 * or lose information. That is, this routine must actually
2512 * insert this page into the given map NOW.
2516 pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
2517 vm_prot_t prot, boolean_t wired)
2520 rw_wlock(&pvh_global_lock);
2522 pmap_enter_locked(pmap, va, m, prot, wired, M_WAITOK);
2524 rw_wunlock(&pvh_global_lock);
2528 * The pvh global and pmap locks must be held.
2531 pmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2532 boolean_t wired, int flags)
2534 struct l2_bucket *l2b = NULL;
2535 struct vm_page *opg;
2536 struct pv_entry *pve = NULL;
2537 pt_entry_t *ptep, npte, opte;
2543 PMAP_ASSERT_LOCKED(pmap);
2544 rw_assert(&pvh_global_lock, RA_WLOCKED);
2545 if (va == vector_page) {
2546 pa = systempage.pv_pa;
2549 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 ||
2550 (flags & M_NOWAIT) != 0,
2551 ("pmap_enter_locked: page %p is not busy", m));
2552 pa = VM_PAGE_TO_PHYS(m);
2557 * Make sure userland mappings get the right permissions
2559 if (pmap != pmap_kernel() && va != vector_page)
2564 if (prot & VM_PROT_WRITE)
2565 nflags |= PVF_WRITE;
2566 if (prot & VM_PROT_EXECUTE)
2569 nflags |= PVF_WIRED;
2571 PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, "
2572 "wired = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, wired));
2574 if (pmap == pmap_kernel()) {
2575 l2b = pmap_get_l2_bucket(pmap, va);
2577 l2b = pmap_grow_l2_bucket(pmap, va);
2580 l2b = pmap_alloc_l2_bucket(pmap, va);
2582 if (flags & M_WAITOK) {
2584 rw_wunlock(&pvh_global_lock);
2586 rw_wlock(&pvh_global_lock);
2594 ptep = &l2b->l2b_kva[l2pte_index(va)];
2601 * There is already a mapping at this address.
2602 * If the physical address is different, lookup the
2605 if (l2pte_pa(opte) != pa)
2606 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte));
2612 if ((prot & (VM_PROT_ALL)) ||
2613 (!m || m->md.pvh_attrs & PVF_REF)) {
2615 * - The access type indicates that we don't need
2616 * to do referenced emulation.
2618 * - The physical page has already been referenced
2619 * so no need to re-do referenced emulation here.
2628 if (m && ((prot & VM_PROT_WRITE) != 0 ||
2629 (m->md.pvh_attrs & PVF_MOD))) {
2631 * This is a writable mapping, and the
2632 * page's mod state indicates it has
2633 * already been modified. Make it
2634 * writable from the outset.
2637 if (!(m->md.pvh_attrs & PVF_MOD))
2641 vm_page_aflag_set(m, PGA_REFERENCED);
2644 * Need to do page referenced emulation.
2646 npte |= L2_TYPE_INV;
2649 npte |= L2_S_PROT_R;
2651 if (prot & VM_PROT_WRITE) {
2655 (m->oflags & VPO_UNMANAGED) == 0)
2656 vm_page_aflag_set(m, PGA_WRITEABLE);
2660 npte |= L2_S_PROT_U;
2663 if (!(prot & VM_PROT_EXECUTE) && m)
2666 if (!(m->md.pv_memattr & VM_MEMATTR_UNCACHEABLE))
2667 npte |= pte_l2_s_cache_mode;
2669 if (m && m == opg) {
2671 * We're changing the attrs of an existing mapping.
2673 oflags = pmap_modify_pv(m, pmap, va,
2674 PVF_WRITE | PVF_EXEC | PVF_WIRED |
2675 PVF_MOD | PVF_REF, nflags);
2678 * New mapping, or changing the backing page
2679 * of an existing mapping.
2683 * Replacing an existing mapping with a new one.
2684 * It is part of our managed memory so we
2685 * must remove it from the PV list
2687 if ((pve = pmap_remove_pv(opg, pmap, va))) {
2688 oflags = pve->pv_flags;
2690 if (m && ((m->oflags & VPO_UNMANAGED))) {
2691 pmap_free_pv_entry(pve);
2697 if ((m && !(m->oflags & VPO_UNMANAGED))) {
2698 if ((!pve) && (pve = pmap_get_pv_entry()) == NULL)
2699 panic("pmap_enter: no pv entries");
2701 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
2702 ("pmap_enter: managed mapping within the clean submap"));
2703 KASSERT(pve != NULL, ("No pv"));
2704 pmap_enter_pv(m, pve, pmap, va, nflags);
2709 * Keep the stats up to date
2712 l2b->l2b_occupancy++;
2713 pmap->pm_stats.resident_count++;
2716 CTR5(KTR_PMAP,"enter: pmap:%p va:%x prot:%x pte:%x->%x",
2717 pmap, va, prot, opte, npte);
2719 * If this is just a wiring change, the two PTEs will be
2720 * identical, so there's no need to update the page table.
2723 boolean_t is_cached = pmap_is_current(pmap);
2729 * We only need to frob the cache/tlb if this pmap
2732 if (L1_IDX(va) != L1_IDX(vector_page) &&
2733 l2pte_valid(npte)) {
2735 * This mapping is likely to be accessed as
2736 * soon as we return to userland. Fix up the
2737 * L1 entry to avoid taking another
2738 * page/domain fault.
2740 pd_entry_t *pl1pd, l1pd;
2742 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
2743 l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) |
2745 if (*pl1pd != l1pd) {
2752 if (PV_BEEN_EXECD(oflags))
2753 cpu_tlb_flushID_SE(va);
2754 else if (PV_BEEN_REFD(oflags))
2755 cpu_tlb_flushD_SE(va);
2760 * Maps a sequence of resident pages belonging to the same object.
2761 * The sequence begins with the given page m_start. This page is
2762 * mapped at the given virtual address start. Each subsequent page is
2763 * mapped at a virtual address that is offset from start by the same
2764 * amount as the page is offset from m_start within the object. The
2765 * last page in the sequence is the page with the largest offset from
2766 * m_start that can be mapped at a virtual address less than the given
2767 * virtual address end. Not every virtual page between start and end
2768 * is mapped; only those for which a resident page exists with the
2769 * corresponding offset from m_start are mapped.
2772 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
2773 vm_page_t m_start, vm_prot_t prot)
2776 vm_pindex_t diff, psize;
2778 psize = atop(end - start);
2780 rw_wlock(&pvh_global_lock);
2782 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
2783 pmap_enter_locked(pmap, start + ptoa(diff), m, prot &
2784 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE, M_NOWAIT);
2785 m = TAILQ_NEXT(m, listq);
2788 rw_wunlock(&pvh_global_lock);
2792 * this code makes some *MAJOR* assumptions:
2793 * 1. Current pmap & pmap exists.
2796 * 4. No page table pages.
2797 * but is *MUCH* faster than pmap_enter...
2801 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
2804 rw_wlock(&pvh_global_lock);
2806 pmap_enter_locked(pmap, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
2809 rw_wunlock(&pvh_global_lock);
2813 * Routine: pmap_change_wiring
2814 * Function: Change the wiring attribute for a map/virtual-address
2816 * In/out conditions:
2817 * The mapping must already exist in the pmap.
2820 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
2822 struct l2_bucket *l2b;
2823 pt_entry_t *ptep, pte;
2826 rw_wlock(&pvh_global_lock);
2828 l2b = pmap_get_l2_bucket(pmap, va);
2829 KASSERT(l2b, ("No l2b bucket in pmap_change_wiring"));
2830 ptep = &l2b->l2b_kva[l2pte_index(va)];
2832 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
2834 pmap_modify_pv(pg, pmap, va, PVF_WIRED, wired);
2835 rw_wunlock(&pvh_global_lock);
2841 * Copy the range specified by src_addr/len
2842 * from the source map to the range dst_addr/len
2843 * in the destination map.
2845 * This routine is only advisory and need not do anything.
2848 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
2849 vm_size_t len, vm_offset_t src_addr)
2855 * Routine: pmap_extract
2857 * Extract the physical page address associated
2858 * with the given map/virtual_address pair.
2861 pmap_extract(pmap_t pmap, vm_offset_t va)
2866 pa = pmap_extract_locked(pmap, va);
2872 pmap_extract_locked(pmap_t pmap, vm_offset_t va)
2874 struct l2_dtable *l2;
2876 pt_entry_t *ptep, pte;
2880 if (pmap != kernel_pmap)
2881 PMAP_ASSERT_LOCKED(pmap);
2883 l1pd = pmap->pm_l1->l1_kva[l1idx];
2884 if (l1pte_section_p(l1pd)) {
2886 * These should only happen for the kernel pmap.
2888 KASSERT(pmap == kernel_pmap, ("unexpected section"));
2889 /* XXX: what to do about the bits > 32 ? */
2890 if (l1pd & L1_S_SUPERSEC)
2891 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
2893 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
2896 * Note that we can't rely on the validity of the L1
2897 * descriptor as an indication that a mapping exists.
2898 * We have to look it up in the L2 dtable.
2900 l2 = pmap->pm_l2[L2_IDX(l1idx)];
2902 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL)
2904 pte = ptep[l2pte_index(va)];
2907 switch (pte & L2_TYPE_MASK) {
2909 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
2912 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
2920 * Atomically extract and hold the physical page with the given
2921 * pmap and virtual address pair if that mapping permits the given
2926 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
2928 struct l2_dtable *l2;
2930 pt_entry_t *ptep, pte;
2931 vm_paddr_t pa, paddr;
2939 l1pd = pmap->pm_l1->l1_kva[l1idx];
2940 if (l1pte_section_p(l1pd)) {
2942 * These should only happen for pmap_kernel()
2944 KASSERT(pmap == pmap_kernel(), ("huh"));
2945 /* XXX: what to do about the bits > 32 ? */
2946 if (l1pd & L1_S_SUPERSEC)
2947 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
2949 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
2950 if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr))
2952 if (L1_S_WRITABLE(l1pd) || (prot & VM_PROT_WRITE) == 0) {
2953 m = PHYS_TO_VM_PAGE(pa);
2958 * Note that we can't rely on the validity of the L1
2959 * descriptor as an indication that a mapping exists.
2960 * We have to look it up in the L2 dtable.
2962 l2 = pmap->pm_l2[L2_IDX(l1idx)];
2965 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
2970 ptep = &ptep[l2pte_index(va)];
2976 } else if ((prot & VM_PROT_WRITE) && (pte & L2_APX)) {
2980 switch (pte & L2_TYPE_MASK) {
2982 panic("extract and hold section mapping");
2985 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
2988 if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr))
2990 m = PHYS_TO_VM_PAGE(pa);
2997 PA_UNLOCK_COND(paddr);
3002 * Initialize a preallocated and zeroed pmap structure,
3003 * such as one in a vmspace structure.
3007 pmap_pinit(pmap_t pmap)
3009 PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap));
3011 PMAP_LOCK_INIT(pmap);
3012 pmap_alloc_l1(pmap);
3013 bzero(pmap->pm_l2, sizeof(pmap->pm_l2));
3015 CPU_ZERO(&pmap->pm_active);
3017 TAILQ_INIT(&pmap->pm_pvlist);
3018 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3019 pmap->pm_stats.resident_count = 1;
3020 if (vector_page < KERNBASE) {
3021 pmap_enter(pmap, vector_page,
3022 VM_PROT_READ, PHYS_TO_VM_PAGE(systempage.pv_pa),
3029 /***************************************************
3030 * page management routines.
3031 ***************************************************/
3035 pmap_free_pv_entry(pv_entry_t pv)
3038 uma_zfree(pvzone, pv);
3043 * get a new pv_entry, allocating a block from the system
3045 * the memory allocation is performed bypassing the malloc code
3046 * because of the possibility of allocations at interrupt time.
3049 pmap_get_pv_entry(void)
3051 pv_entry_t ret_value;
3054 if (pv_entry_count > pv_entry_high_water)
3055 pagedaemon_wakeup();
3056 ret_value = uma_zalloc(pvzone, M_NOWAIT);
3061 * Remove the given range of addresses from the specified map.
3063 * It is assumed that the start and end are properly
3064 * rounded to the page size.
3066 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3
3068 pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva)
3070 struct l2_bucket *l2b;
3071 vm_offset_t next_bucket;
3074 u_int mappings, is_exec, is_refd;
3079 * we lock in the pmap => pv_head direction
3082 rw_wlock(&pvh_global_lock);
3087 * Do one L2 bucket's worth at a time.
3089 next_bucket = L2_NEXT_BUCKET(sva);
3090 if (next_bucket > eva)
3093 l2b = pmap_get_l2_bucket(pm, sva);
3099 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3102 while (sva < next_bucket) {
3111 * Nothing here, move along
3118 pm->pm_stats.resident_count--;
3124 * Update flags. In a number of circumstances,
3125 * we could cluster a lot of these and do a
3126 * number of sequential pages in one go.
3128 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) {
3129 struct pv_entry *pve;
3131 pve = pmap_remove_pv(pg, pm, sva);
3133 is_exec = PV_BEEN_EXECD(pve->pv_flags);
3134 is_refd = PV_BEEN_REFD(pve->pv_flags);
3135 pmap_free_pv_entry(pve);
3139 if (pmap_is_current(pm)) {
3141 if (total < PMAP_REMOVE_CLEAN_LIST_SIZE) {
3143 cpu_tlb_flushID_SE(sva);
3145 cpu_tlb_flushD_SE(sva);
3146 } else if (total == PMAP_REMOVE_CLEAN_LIST_SIZE) {
3158 pmap_free_l2_bucket(pm, l2b, mappings);
3161 rw_wunlock(&pvh_global_lock);
3170 * Zero a given physical page by mapping it at a page hook point.
3171 * In doing the zero page op, the page we zero is mapped cachable, as with
3172 * StrongARM accesses to non-cached pages are non-burst making writing
3173 * _any_ bulk data very slow.
3176 pmap_zero_page_gen(vm_page_t pg, int off, int size)
3179 vm_paddr_t phys = VM_PAGE_TO_PHYS(pg);
3180 if (!TAILQ_EMPTY(&pg->md.pv_list))
3181 panic("pmap_zero_page: page has mappings");
3185 * Hook in the page, zero it, invalidate the TLB as needed.
3187 * Note the temporary zero-page mapping must be a non-cached page in
3188 * order to work without corruption when write-allocate is enabled.
3190 *cdst_pte = L2_S_PROTO | phys | pte_l2_s_cache_mode;
3191 pmap_set_prot(cdst_pte, VM_PROT_WRITE, 0);
3193 cpu_tlb_flushD_SE(cdstp);
3195 if (off || size != PAGE_SIZE)
3196 bzero((void *)(cdstp + off), size);
3204 * pmap_zero_page zeros the specified hardware page by mapping
3205 * the page into KVM and using bzero to clear its contents.
3208 pmap_zero_page(vm_page_t m)
3210 pmap_zero_page_gen(m, 0, PAGE_SIZE);
3215 * pmap_zero_page_area zeros the specified hardware page by mapping
3216 * the page into KVM and using bzero to clear its contents.
3218 * off and size may not cover an area beyond a single hardware page.
3221 pmap_zero_page_area(vm_page_t m, int off, int size)
3224 pmap_zero_page_gen(m, off, size);
3229 * pmap_zero_page_idle zeros the specified hardware page by mapping
3230 * the page into KVM and using bzero to clear its contents. This
3231 * is intended to be called from the vm_pagezero process only and
3235 pmap_zero_page_idle(vm_page_t m)
3242 * pmap_copy_page copies the specified (machine independent)
3243 * page by mapping the page into virtual memory and using
3244 * bcopy to copy the page, one machine dependent page at a
3251 * Copy one physical page into another, by mapping the pages into
3252 * hook points. The same comment regarding cachability as in
3253 * pmap_zero_page also applies here.
3256 pmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst)
3259 * Hold the source page's lock for the duration of the copy
3260 * so that no other mappings can be created while we have a
3261 * potentially aliased mapping.
3262 * Map the pages into the page hook points, copy them, and purge
3263 * the cache for the appropriate page. Invalidate the TLB
3268 /* For ARMv6 using System bit is deprecated and mapping with AP
3269 * bits set to 0x0 makes page not accessible. csrc_pte is mapped
3270 * read/write until proper mapping defines are created for ARMv6.
3272 *csrc_pte = L2_S_PROTO | src | pte_l2_s_cache_mode;
3273 pmap_set_prot(csrc_pte, VM_PROT_READ, 0);
3276 *cdst_pte = L2_S_PROTO | dst | pte_l2_s_cache_mode;
3277 pmap_set_prot(cdst_pte, VM_PROT_READ | VM_PROT_WRITE, 0);
3279 cpu_tlb_flushD_SE(csrcp);
3280 cpu_tlb_flushD_SE(cdstp);
3283 bcopy_page(csrcp, cdstp);
3289 pmap_copy_page(vm_page_t src, vm_page_t dst)
3292 if (_arm_memcpy && PAGE_SIZE >= _min_memcpy_size &&
3293 _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst),
3294 (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0)
3297 pmap_copy_page_generic(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst));
3301 * this routine returns true if a physical page resides
3302 * in the given pmap.
3305 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
3311 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3312 ("pmap_page_exists_quick: page %p is not managed", m));
3314 rw_wlock(&pvh_global_lock);
3315 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3316 if (pv->pv_pmap == pmap) {
3325 rw_wunlock(&pvh_global_lock);
3330 * pmap_page_wired_mappings:
3332 * Return the number of managed mappings to the given physical page
3336 pmap_page_wired_mappings(vm_page_t m)
3342 if ((m->flags & PG_FICTITIOUS) != 0)
3344 rw_wlock(&pvh_global_lock);
3345 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
3346 if ((pv->pv_flags & PVF_WIRED) != 0)
3348 rw_wunlock(&pvh_global_lock);
3353 * pmap_is_referenced:
3355 * Return whether or not the specified physical page was referenced
3356 * in any physical maps.
3359 pmap_is_referenced(vm_page_t m)
3362 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3363 ("pmap_is_referenced: page %p is not managed", m));
3364 return ((m->md.pvh_attrs & PVF_REF) != 0);
3368 * pmap_ts_referenced:
3370 * Return the count of reference bits for a page, clearing all of them.
3373 pmap_ts_referenced(vm_page_t m)
3376 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3377 ("pmap_ts_referenced: page %p is not managed", m));
3378 return (pmap_clearbit(m, PVF_REF));
3383 pmap_is_modified(vm_page_t m)
3386 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3387 ("pmap_is_modified: page %p is not managed", m));
3388 if (m->md.pvh_attrs & PVF_MOD)
3396 * Clear the modify bits on the specified physical page.
3399 pmap_clear_modify(vm_page_t m)
3402 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3403 ("pmap_clear_modify: page %p is not managed", m));
3404 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
3405 KASSERT((m->oflags & VPO_BUSY) == 0,
3406 ("pmap_clear_modify: page %p is busy", m));
3409 * If the page is not PGA_WRITEABLE, then no mappings can be modified.
3410 * If the object containing the page is locked and the page is not
3411 * VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set.
3413 if ((m->aflags & PGA_WRITEABLE) == 0)
3416 if (m->md.pvh_attrs & PVF_MOD)
3417 pmap_clearbit(m, PVF_MOD);
3422 * pmap_clear_reference:
3424 * Clear the reference bit on the specified physical page.
3427 pmap_clear_reference(vm_page_t m)
3430 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3431 ("pmap_clear_reference: page %p is not managed", m));
3432 if (m->md.pvh_attrs & PVF_REF)
3433 pmap_clearbit(m, PVF_REF);
3438 * Clear the write and modified bits in each of the given page's mappings.
3441 pmap_remove_write(vm_page_t m)
3443 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3444 ("pmap_remove_write: page %p is not managed", m));
3447 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
3448 * another thread while the object is locked. Thus, if PGA_WRITEABLE
3449 * is clear, no page table entries need updating.
3451 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
3452 if ((m->oflags & VPO_BUSY) != 0 ||
3453 (m->aflags & PGA_WRITEABLE) != 0)
3454 pmap_clearbit(m, PVF_WRITE);
3459 * perform the pmap work for mincore
3462 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
3464 struct l2_bucket *l2b;
3465 pt_entry_t *ptep, pte;
3473 l2b = pmap_get_l2_bucket(pmap, addr);
3478 ptep = &l2b->l2b_kva[l2pte_index(addr)];
3480 if (!l2pte_valid(pte)) {
3484 val = MINCORE_INCORE;
3485 if (L2_S_WRITABLE(pte))
3486 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
3489 m = PHYS_TO_VM_PAGE(pa);
3490 if (m != NULL && (m->oflags & VPO_UNMANAGED) == 0)
3494 * The ARM pmap tries to maintain a per-mapping
3495 * reference bit. The trouble is that it's kept in
3496 * the PV entry, not the PTE, so it's costly to access
3497 * here. You would need to acquire the pvh global
3498 * lock, call pmap_find_pv(), and introduce a custom
3499 * version of vm_page_pa_tryrelock() that releases and
3500 * reacquires the pvh global lock. In the end, I
3501 * doubt it's worthwhile. This may falsely report
3502 * the given address as referenced.
3504 if ((m->md.pvh_attrs & PVF_REF) != 0)
3505 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
3507 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
3508 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
3509 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
3510 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
3514 PA_UNLOCK_COND(*locked_pa);
3520 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
3525 * Increase the starting virtual address of the given mapping if a
3526 * different alignment might result in more superpage mappings.
3529 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
3530 vm_offset_t *addr, vm_size_t size)
3536 * Map a set of physical memory pages into the kernel virtual
3537 * address space. Return a pointer to where it is mapped. This
3538 * routine is intended to be used for mapping device memory,
3542 pmap_mapdev(vm_offset_t pa, vm_size_t size)
3544 vm_offset_t va, tmpva, offset;
3546 offset = pa & PAGE_MASK;
3547 size = roundup(size, PAGE_SIZE);
3551 va = kmem_alloc_nofault(kernel_map, size);
3553 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
3554 for (tmpva = va; size > 0;) {
3555 pmap_kenter_internal(tmpva, pa, 0);
3561 return ((void *)(va + offset));
3567 * Create a single section mapping.
3570 pmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
3571 int prot, int cache)
3573 pd_entry_t *pde = (pd_entry_t *) l1pt;
3576 KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2"));
3578 fl = l1_mem_types[cache];
3580 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
3581 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL);
3582 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
3588 * Link the L2 page table specified by l2pv.pv_pa into the L1
3589 * page table at the slot for "va".
3592 pmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv)
3594 pd_entry_t *pde = (pd_entry_t *) l1pt, proto;
3595 u_int slot = va >> L1_S_SHIFT;
3597 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO;
3599 #ifdef VERBOSE_INIT_ARM
3600 printf("pmap_link_l2pt: pa=0x%x va=0x%x\n", l2pv->pv_pa, l2pv->pv_va);
3603 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000);
3604 PTE_SYNC(&pde[slot]);
3606 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list);
3613 * Create a single page mapping.
3616 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot,
3619 pd_entry_t *pde = (pd_entry_t *) l1pt;
3623 KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin"));
3625 fl = l2s_mem_types[cache];
3627 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
3628 panic("pmap_map_entry: no L2 table for VA 0x%08x", va);
3630 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK);
3633 panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va);
3635 pte[l2pte_index(va)] = L2_S_PROTO | pa | fl;
3636 pmap_set_prot(&pte[l2pte_index(va)], prot, 0);
3637 PTE_SYNC(&pte[l2pte_index(va)]);
3643 * Map a chunk of memory using the most efficient mappings
3644 * possible (section. large page, small page) into the
3645 * provided L1 and L2 tables at the specified virtual address.
3648 pmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
3649 vm_size_t size, int prot, int type)
3651 pd_entry_t *pde = (pd_entry_t *) l1pt;
3652 pt_entry_t *pte, f1, f2s, f2l;
3656 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
3659 panic("pmap_map_chunk: no L1 table provided");
3661 #ifdef VERBOSE_INIT_ARM
3662 printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x "
3663 "prot=0x%x type=%d\n", pa, va, size, resid, prot, type);
3666 f1 = l1_mem_types[type];
3667 f2l = l2l_mem_types[type];
3668 f2s = l2s_mem_types[type];
3673 /* See if we can use a section mapping. */
3674 if (L1_S_MAPPABLE_P(va, pa, resid)) {
3675 #ifdef VERBOSE_INIT_ARM
3678 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
3679 L1_S_PROT(PTE_KERNEL, prot) | f1 |
3680 L1_S_DOM(PMAP_DOMAIN_KERNEL);
3681 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
3689 * Ok, we're going to use an L2 table. Make sure
3690 * one is actually in the corresponding L1 slot
3691 * for the current VA.
3693 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
3694 panic("pmap_map_chunk: no L2 table for VA 0x%08x", va);
3696 pte = (pt_entry_t *) kernel_pt_lookup(
3697 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
3699 panic("pmap_map_chunk: can't find L2 table for VA"
3701 /* See if we can use a L2 large page mapping. */
3702 if (L2_L_MAPPABLE_P(va, pa, resid)) {
3703 #ifdef VERBOSE_INIT_ARM
3706 for (i = 0; i < 16; i++) {
3707 pte[l2pte_index(va) + i] =
3709 L2_L_PROT(PTE_KERNEL, prot) | f2l;
3710 PTE_SYNC(&pte[l2pte_index(va) + i]);
3718 /* Use a small page mapping. */
3719 #ifdef VERBOSE_INIT_ARM
3722 pte[l2pte_index(va)] = L2_S_PROTO | pa | f2s;
3723 pmap_set_prot(&pte[l2pte_index(va)], prot, 0);
3724 PTE_SYNC(&pte[l2pte_index(va)]);
3729 #ifdef VERBOSE_INIT_ARM
3736 /********************** Static device map routines ***************************/
3738 static const struct pmap_devmap *pmap_devmap_table;
3741 * Register the devmap table. This is provided in case early console
3742 * initialization needs to register mappings created by bootstrap code
3743 * before pmap_devmap_bootstrap() is called.
3746 pmap_devmap_register(const struct pmap_devmap *table)
3749 pmap_devmap_table = table;
3753 * Map all of the static regions in the devmap table, and remember
3754 * the devmap table so other parts of the kernel can look up entries
3758 pmap_devmap_bootstrap(vm_offset_t l1pt, const struct pmap_devmap *table)
3762 pmap_devmap_table = table;
3764 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
3765 #ifdef VERBOSE_INIT_ARM
3766 printf("devmap: %08x -> %08x @ %08x\n",
3767 pmap_devmap_table[i].pd_pa,
3768 pmap_devmap_table[i].pd_pa +
3769 pmap_devmap_table[i].pd_size - 1,
3770 pmap_devmap_table[i].pd_va);
3772 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va,
3773 pmap_devmap_table[i].pd_pa,
3774 pmap_devmap_table[i].pd_size,
3775 pmap_devmap_table[i].pd_prot,
3776 pmap_devmap_table[i].pd_cache);
3780 const struct pmap_devmap *
3781 pmap_devmap_find_pa(vm_paddr_t pa, vm_size_t size)
3785 if (pmap_devmap_table == NULL)
3788 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
3789 if (pa >= pmap_devmap_table[i].pd_pa &&
3790 pa + size <= pmap_devmap_table[i].pd_pa +
3791 pmap_devmap_table[i].pd_size)
3792 return (&pmap_devmap_table[i]);
3798 const struct pmap_devmap *
3799 pmap_devmap_find_va(vm_offset_t va, vm_size_t size)
3803 if (pmap_devmap_table == NULL)
3806 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
3807 if (va >= pmap_devmap_table[i].pd_va &&
3808 va + size <= pmap_devmap_table[i].pd_va +
3809 pmap_devmap_table[i].pd_size)
3810 return (&pmap_devmap_table[i]);
3817 pmap_dmap_iscurrent(pmap_t pmap)
3819 return(pmap_is_current(pmap));
3823 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
3826 * Remember the memattr in a field that gets used to set the appropriate
3827 * bits in the PTEs as mappings are established.
3829 m->md.pv_memattr = ma;
3832 * It appears that this function can only be called before any mappings
3833 * for the page are established on ARM. If this ever changes, this code
3834 * will need to walk the pv_list and make each of the existing mappings
3835 * uncacheable, being careful to sync caches and PTEs (and maybe
3836 * invalidate TLB?) for any current mapping it modifies.
3838 if (m->md.pv_kva != 0 || TAILQ_FIRST(&m->md.pv_list) != NULL)
3839 panic("Can't change memattr on page with existing mappings");