2 * Copyright (c) 1991 Regents of the University of California.
3 * Copyright (c) 1994 John S. Dyson
4 * Copyright (c) 1994 David Greenman
5 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
6 * Copyright (c) 2014-2016 Svatopluk Kraus <skra@FreeBSD.org>
7 * Copyright (c) 2014-2016 Michal Meloun <mmel@FreeBSD.org>
10 * This code is derived from software contributed to Berkeley by
11 * the Systems Programming Group of the University of Utah Computer
12 * Science Department and William Jolitz of UUNET Technologies Inc.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
41 * Copyright (c) 2003 Networks Associates Technology, Inc.
42 * All rights reserved.
44 * This software was developed for the FreeBSD Project by Jake Burkholder,
45 * Safeport Network Services, and Network Associates Laboratories, the
46 * Security Research Division of Network Associates, Inc. under
47 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
48 * CHATS research program.
50 * Redistribution and use in source and binary forms, with or without
51 * modification, are permitted provided that the following conditions
53 * 1. Redistributions of source code must retain the above copyright
54 * notice, this list of conditions and the following disclaimer.
55 * 2. Redistributions in binary form must reproduce the above copyright
56 * notice, this list of conditions and the following disclaimer in the
57 * documentation and/or other materials provided with the distribution.
59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
62 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
72 #include <sys/cdefs.h>
73 __FBSDID("$FreeBSD$");
76 * Manages physical address maps.
78 * Since the information managed by this module is
79 * also stored by the logical address mapping module,
80 * this module may throw away valid virtual-to-physical
81 * mappings at almost any time. However, invalidations
82 * of virtual-to-physical mappings must be done as
85 * In order to cope with hardware architectures which
86 * make virtual-to-physical map invalidates expensive,
87 * this module may delay invalidate or reduced protection
88 * operations until such time as they are actually
89 * necessary. This module is given full information as
90 * to which processors are currently using which maps,
91 * and to when physical maps must be made correct.
98 #include <sys/param.h>
99 #include <sys/systm.h>
100 #include <sys/kernel.h>
102 #include <sys/lock.h>
103 #include <sys/proc.h>
104 #include <sys/rwlock.h>
105 #include <sys/malloc.h>
106 #include <sys/vmmeter.h>
107 #include <sys/malloc.h>
108 #include <sys/mman.h>
109 #include <sys/sf_buf.h>
111 #include <sys/sched.h>
112 #include <sys/sysctl.h>
118 #include <machine/physmem.h>
123 #include <vm/vm_param.h>
124 #include <vm/vm_kern.h>
125 #include <vm/vm_object.h>
126 #include <vm/vm_map.h>
127 #include <vm/vm_page.h>
128 #include <vm/vm_pageout.h>
129 #include <vm/vm_phys.h>
130 #include <vm/vm_extern.h>
131 #include <vm/vm_reserv.h>
132 #include <sys/lock.h>
133 #include <sys/mutex.h>
135 #include <machine/md_var.h>
136 #include <machine/pmap_var.h>
137 #include <machine/cpu.h>
138 #include <machine/pcb.h>
139 #include <machine/sf_buf.h>
141 #include <machine/smp.h>
143 #ifndef PMAP_SHPGPERPROC
144 #define PMAP_SHPGPERPROC 200
148 #define PMAP_INLINE __inline
154 static void pmap_zero_page_check(vm_page_t m);
155 void pmap_debug(int level);
156 int pmap_pid_dump(int pid);
158 #define PDEBUG(_lev_,_stat_) \
159 if (pmap_debug_level >= (_lev_)) \
161 #define dprintf printf
162 int pmap_debug_level = 1;
163 #else /* PMAP_DEBUG */
164 #define PDEBUG(_lev_,_stat_) /* Nothing */
165 #define dprintf(x, arg...)
166 #endif /* PMAP_DEBUG */
169 * Level 2 page tables map definion ('max' is excluded).
172 #define PT2V_MIN_ADDRESS ((vm_offset_t)PT2MAP)
173 #define PT2V_MAX_ADDRESS ((vm_offset_t)PT2MAP + PT2MAP_SIZE)
175 #define UPT2V_MIN_ADDRESS ((vm_offset_t)PT2MAP)
176 #define UPT2V_MAX_ADDRESS \
177 ((vm_offset_t)(PT2MAP + (KERNBASE >> PT2MAP_SHIFT)))
180 * Promotion to a 1MB (PTE1) page mapping requires that the corresponding
181 * 4KB (PTE2) page mappings have identical settings for the following fields:
183 #define PTE2_PROMOTE (PTE2_V | PTE2_A | PTE2_NM | PTE2_S | PTE2_NG | \
184 PTE2_NX | PTE2_RO | PTE2_U | PTE2_W | \
187 #define PTE1_PROMOTE (PTE1_V | PTE1_A | PTE1_NM | PTE1_S | PTE1_NG | \
188 PTE1_NX | PTE1_RO | PTE1_U | PTE1_W | \
191 #define ATTR_TO_L1(l2_attr) ((((l2_attr) & L2_TEX0) ? L1_S_TEX0 : 0) | \
192 (((l2_attr) & L2_C) ? L1_S_C : 0) | \
193 (((l2_attr) & L2_B) ? L1_S_B : 0) | \
194 (((l2_attr) & PTE2_A) ? PTE1_A : 0) | \
195 (((l2_attr) & PTE2_NM) ? PTE1_NM : 0) | \
196 (((l2_attr) & PTE2_S) ? PTE1_S : 0) | \
197 (((l2_attr) & PTE2_NG) ? PTE1_NG : 0) | \
198 (((l2_attr) & PTE2_NX) ? PTE1_NX : 0) | \
199 (((l2_attr) & PTE2_RO) ? PTE1_RO : 0) | \
200 (((l2_attr) & PTE2_U) ? PTE1_U : 0) | \
201 (((l2_attr) & PTE2_W) ? PTE1_W : 0))
203 #define ATTR_TO_L2(l1_attr) ((((l1_attr) & L1_S_TEX0) ? L2_TEX0 : 0) | \
204 (((l1_attr) & L1_S_C) ? L2_C : 0) | \
205 (((l1_attr) & L1_S_B) ? L2_B : 0) | \
206 (((l1_attr) & PTE1_A) ? PTE2_A : 0) | \
207 (((l1_attr) & PTE1_NM) ? PTE2_NM : 0) | \
208 (((l1_attr) & PTE1_S) ? PTE2_S : 0) | \
209 (((l1_attr) & PTE1_NG) ? PTE2_NG : 0) | \
210 (((l1_attr) & PTE1_NX) ? PTE2_NX : 0) | \
211 (((l1_attr) & PTE1_RO) ? PTE2_RO : 0) | \
212 (((l1_attr) & PTE1_U) ? PTE2_U : 0) | \
213 (((l1_attr) & PTE1_W) ? PTE2_W : 0))
216 * PTE2 descriptors creation macros.
218 #define PTE2_ATTR_DEFAULT vm_memattr_to_pte2(VM_MEMATTR_DEFAULT)
219 #define PTE2_ATTR_PT vm_memattr_to_pte2(pt_memattr)
221 #define PTE2_KPT(pa) PTE2_KERN(pa, PTE2_AP_KRW, PTE2_ATTR_PT)
222 #define PTE2_KPT_NG(pa) PTE2_KERN_NG(pa, PTE2_AP_KRW, PTE2_ATTR_PT)
224 #define PTE2_KRW(pa) PTE2_KERN(pa, PTE2_AP_KRW, PTE2_ATTR_DEFAULT)
225 #define PTE2_KRO(pa) PTE2_KERN(pa, PTE2_AP_KR, PTE2_ATTR_DEFAULT)
229 #define PV_STAT(x) do { x ; } while (0)
231 #define PV_STAT(x) do { } while (0)
235 * The boot_pt1 is used temporary in very early boot stage as L1 page table.
236 * We can init many things with no memory allocation thanks to its static
237 * allocation and this brings two main advantages:
238 * (1) other cores can be started very simply,
239 * (2) various boot loaders can be supported as its arguments can be processed
240 * in virtual address space and can be moved to safe location before
241 * first allocation happened.
242 * Only disadvantage is that boot_pt1 is used only in very early boot stage.
243 * However, the table is uninitialized and so lays in bss. Therefore kernel
244 * image size is not influenced.
246 * QQQ: In the future, maybe, boot_pt1 can be used for soft reset and
247 * CPU suspend/resume game.
249 extern pt1_entry_t boot_pt1[];
252 pt1_entry_t *kern_pt1;
253 pt2_entry_t *kern_pt2tab;
256 static uint32_t ttb_flags;
257 static vm_memattr_t pt_memattr;
258 ttb_entry_t pmap_kern_ttb;
260 struct pmap kernel_pmap_store;
261 LIST_HEAD(pmaplist, pmap);
262 static struct pmaplist allpmaps;
263 static struct mtx allpmaps_lock;
265 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
266 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
268 static vm_offset_t kernel_vm_end_new;
269 vm_offset_t kernel_vm_end = KERNBASE + NKPT2PG * NPT2_IN_PG * PTE1_SIZE;
270 vm_offset_t vm_max_kernel_address;
271 vm_paddr_t kernel_l1pa;
273 static struct rwlock __aligned(CACHE_LINE_SIZE) pvh_global_lock;
276 * Data for the pv entry allocation mechanism
278 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
279 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
280 static struct md_page *pv_table; /* XXX: Is it used only the list in md_page? */
281 static int shpgperproc = PMAP_SHPGPERPROC;
283 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
284 int pv_maxchunks; /* How many chunks we have KVA for */
285 vm_offset_t pv_vafree; /* freelist stored in the PTE */
287 vm_paddr_t first_managed_pa;
288 #define pa_to_pvh(pa) (&pv_table[pte1_index(pa - first_managed_pa)])
291 * All those kernel PT submaps that BSD is so fond of
295 struct msgbuf *msgbufp = NULL; /* XXX move it to machdep.c */
300 static caddr_t crashdumpmap;
302 static pt2_entry_t *PMAP1 = NULL, *PMAP2;
303 static pt2_entry_t *PADDR1 = NULL, *PADDR2;
305 static pt2_entry_t *PMAP3;
306 static pt2_entry_t *PADDR3;
307 static int PMAP3cpu __unused; /* for SMP only */
311 static int PMAP1changedcpu;
312 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
314 "Number of times pmap_pte2_quick changed CPU with same PMAP1");
316 static int PMAP1changed;
317 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
319 "Number of times pmap_pte2_quick changed PMAP1");
320 static int PMAP1unchanged;
321 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
323 "Number of times pmap_pte2_quick didn't change PMAP1");
324 static struct mtx PMAP2mutex;
326 static __inline void pt2_wirecount_init(vm_page_t m);
327 static boolean_t pmap_demote_pte1(pmap_t pmap, pt1_entry_t *pte1p,
329 void cache_icache_sync_fresh(vm_offset_t va, vm_paddr_t pa, vm_size_t size);
332 * Function to set the debug level of the pmap code.
336 pmap_debug(int level)
339 pmap_debug_level = level;
340 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
342 #endif /* PMAP_DEBUG */
345 * This table must corespond with memory attribute configuration in vm.h.
346 * First entry is used for normal system mapping.
348 * Device memory is always marked as shared.
349 * Normal memory is shared only in SMP .
350 * Not outer shareable bits are not used yet.
351 * Class 6 cannot be used on ARM11.
353 #define TEXDEF_TYPE_SHIFT 0
354 #define TEXDEF_TYPE_MASK 0x3
355 #define TEXDEF_INNER_SHIFT 2
356 #define TEXDEF_INNER_MASK 0x3
357 #define TEXDEF_OUTER_SHIFT 4
358 #define TEXDEF_OUTER_MASK 0x3
359 #define TEXDEF_NOS_SHIFT 6
360 #define TEXDEF_NOS_MASK 0x1
362 #define TEX(t, i, o, s) \
363 ((t) << TEXDEF_TYPE_SHIFT) | \
364 ((i) << TEXDEF_INNER_SHIFT) | \
365 ((o) << TEXDEF_OUTER_SHIFT | \
366 ((s) << TEXDEF_NOS_SHIFT))
368 static uint32_t tex_class[8] = {
369 /* type inner cache outer cache */
370 TEX(PRRR_MEM, NMRR_WB_WA, NMRR_WB_WA, 0), /* 0 - ATTR_WB_WA */
371 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 1 - ATTR_NOCACHE */
372 TEX(PRRR_DEV, NMRR_NC, NMRR_NC, 0), /* 2 - ATTR_DEVICE */
373 TEX(PRRR_SO, NMRR_NC, NMRR_NC, 0), /* 3 - ATTR_SO */
374 TEX(PRRR_MEM, NMRR_WT, NMRR_WT, 0), /* 4 - ATTR_WT */
375 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 5 - NOT USED YET */
376 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 6 - NOT USED YET */
377 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 7 - NOT USED YET */
381 static uint32_t pte2_attr_tab[8] = {
382 PTE2_ATTR_WB_WA, /* 0 - VM_MEMATTR_WB_WA */
383 PTE2_ATTR_NOCACHE, /* 1 - VM_MEMATTR_NOCACHE */
384 PTE2_ATTR_DEVICE, /* 2 - VM_MEMATTR_DEVICE */
385 PTE2_ATTR_SO, /* 3 - VM_MEMATTR_SO */
386 PTE2_ATTR_WT, /* 4 - VM_MEMATTR_WRITE_THROUGH */
387 0, /* 5 - NOT USED YET */
388 0, /* 6 - NOT USED YET */
389 0 /* 7 - NOT USED YET */
391 CTASSERT(VM_MEMATTR_WB_WA == 0);
392 CTASSERT(VM_MEMATTR_NOCACHE == 1);
393 CTASSERT(VM_MEMATTR_DEVICE == 2);
394 CTASSERT(VM_MEMATTR_SO == 3);
395 CTASSERT(VM_MEMATTR_WRITE_THROUGH == 4);
397 static inline uint32_t
398 vm_memattr_to_pte2(vm_memattr_t ma)
401 KASSERT((u_int)ma < 5, ("%s: bad vm_memattr_t %d", __func__, ma));
402 return (pte2_attr_tab[(u_int)ma]);
405 static inline uint32_t
406 vm_page_pte2_attr(vm_page_t m)
409 return (vm_memattr_to_pte2(m->md.pat_mode));
413 * Convert TEX definition entry to TTB flags.
416 encode_ttb_flags(int idx)
418 uint32_t inner, outer, nos, reg;
420 inner = (tex_class[idx] >> TEXDEF_INNER_SHIFT) &
422 outer = (tex_class[idx] >> TEXDEF_OUTER_SHIFT) &
424 nos = (tex_class[idx] >> TEXDEF_NOS_SHIFT) &
429 if (cpuinfo.coherent_walk)
430 reg |= (inner & 0x1) << 6;
431 reg |= (inner & 0x2) >> 1;
441 * Set TEX remapping registers in current CPU.
447 uint32_t type, inner, outer, nos;
450 #ifdef PMAP_PTE_NOCACHE
452 if (cpuinfo.coherent_walk) {
453 pt_memattr = VM_MEMATTR_WB_WA;
454 ttb_flags = encode_ttb_flags(0);
457 pt_memattr = VM_MEMATTR_NOCACHE;
458 ttb_flags = encode_ttb_flags(1);
461 pt_memattr = VM_MEMATTR_WB_WA;
462 ttb_flags = encode_ttb_flags(0);
468 /* Build remapping register from TEX classes. */
469 for (i = 0; i < 8; i++) {
470 type = (tex_class[i] >> TEXDEF_TYPE_SHIFT) &
472 inner = (tex_class[i] >> TEXDEF_INNER_SHIFT) &
474 outer = (tex_class[i] >> TEXDEF_OUTER_SHIFT) &
476 nos = (tex_class[i] >> TEXDEF_NOS_SHIFT) &
479 prrr |= type << (i * 2);
480 prrr |= nos << (i + 24);
481 nmrr |= inner << (i * 2);
482 nmrr |= outer << (i * 2 + 16);
484 /* Add shareable bits for device memory. */
485 prrr |= PRRR_DS0 | PRRR_DS1;
487 /* Add shareable bits for normal memory in SMP case. */
496 /* Caches are disabled, so full TLB flush should be enough. */
497 tlb_flush_all_local();
501 * Remap one vm_meattr class to another one. This can be useful as
502 * workaround for SOC errata, e.g. if devices must be accessed using
505 * !!! Please note that this function is absolutely last resort thing.
506 * It should not be used under normal circumstances. !!!
509 * - it shall be called after pmap_bootstrap_prepare() and before
510 * cpu_mp_start() (thus only on boot CPU). In practice, it's expected
511 * to be called from platform_attach() or platform_late_init().
513 * - if remapping doesn't change caching mode, or until uncached class
514 * is remapped to any kind of cached one, then no other restriction exists.
516 * - if pmap_remap_vm_attr() changes caching mode, but both (original and
517 * remapped) remain cached, then caller is resposible for calling
518 * of dcache_wbinv_poc_all().
520 * - remapping of any kind of cached class to uncached is not permitted.
523 pmap_remap_vm_attr(vm_memattr_t old_attr, vm_memattr_t new_attr)
525 int old_idx, new_idx;
527 /* Map VM memattrs to indexes to tex_class table. */
528 old_idx = pte2_attr_tab[(int)old_attr];
529 new_idx = pte2_attr_tab[(int)new_attr];
531 /* Replace TEX attribute and apply it. */
532 tex_class[old_idx] = tex_class[new_idx];
537 * KERNBASE must be multiple of NPT2_IN_PG * PTE1_SIZE. In other words,
538 * KERNBASE is mapped by first L2 page table in L2 page table page. It
539 * meets same constrain due to PT2MAP being placed just under KERNBASE.
541 CTASSERT((KERNBASE & (NPT2_IN_PG * PTE1_SIZE - 1)) == 0);
542 CTASSERT((KERNBASE - VM_MAXUSER_ADDRESS) >= PT2MAP_SIZE);
545 * In crazy dreams, PAGE_SIZE could be a multiple of PTE2_SIZE in general.
546 * For now, anyhow, the following check must be fulfilled.
548 CTASSERT(PAGE_SIZE == PTE2_SIZE);
550 * We don't want to mess up MI code with all MMU and PMAP definitions,
551 * so some things, which depend on other ones, are defined independently.
552 * Now, it is time to check that we don't screw up something.
554 CTASSERT(PDRSHIFT == PTE1_SHIFT);
556 * Check L1 and L2 page table entries definitions consistency.
558 CTASSERT(NB_IN_PT1 == (sizeof(pt1_entry_t) * NPTE1_IN_PT1));
559 CTASSERT(NB_IN_PT2 == (sizeof(pt2_entry_t) * NPTE2_IN_PT2));
561 * Check L2 page tables page consistency.
563 CTASSERT(PAGE_SIZE == (NPT2_IN_PG * NB_IN_PT2));
564 CTASSERT((1 << PT2PG_SHIFT) == NPT2_IN_PG);
566 * Check PT2TAB consistency.
567 * PT2TAB_ENTRIES is defined as a division of NPTE1_IN_PT1 by NPT2_IN_PG.
568 * This should be done without remainder.
570 CTASSERT(NPTE1_IN_PT1 == (PT2TAB_ENTRIES * NPT2_IN_PG));
575 * All level 2 page tables (PT2s) are mapped continuously and accordingly
576 * into PT2MAP address space. As PT2 size is less than PAGE_SIZE, this can
577 * be done only if PAGE_SIZE is a multiple of PT2 size. All PT2s in one page
578 * must be used together, but not necessary at once. The first PT2 in a page
579 * must map things on correctly aligned address and the others must follow
582 #define NB_IN_PT2TAB (PT2TAB_ENTRIES * sizeof(pt2_entry_t))
583 #define NPT2_IN_PT2TAB (NB_IN_PT2TAB / NB_IN_PT2)
584 #define NPG_IN_PT2TAB (NB_IN_PT2TAB / PAGE_SIZE)
587 * Check PT2TAB consistency.
588 * NPT2_IN_PT2TAB is defined as a division of NB_IN_PT2TAB by NB_IN_PT2.
589 * NPG_IN_PT2TAB is defined as a division of NB_IN_PT2TAB by PAGE_SIZE.
590 * The both should be done without remainder.
592 CTASSERT(NB_IN_PT2TAB == (NPT2_IN_PT2TAB * NB_IN_PT2));
593 CTASSERT(NB_IN_PT2TAB == (NPG_IN_PT2TAB * PAGE_SIZE));
595 * The implementation was made general, however, with the assumption
596 * bellow in mind. In case of another value of NPG_IN_PT2TAB,
597 * the code should be once more rechecked.
599 CTASSERT(NPG_IN_PT2TAB == 1);
602 * Get offset of PT2 in a page
603 * associated with given PT1 index.
605 static __inline u_int
606 page_pt2off(u_int pt1_idx)
609 return ((pt1_idx & PT2PG_MASK) * NB_IN_PT2);
613 * Get physical address of PT2
614 * associated with given PT2s page and PT1 index.
616 static __inline vm_paddr_t
617 page_pt2pa(vm_paddr_t pgpa, u_int pt1_idx)
620 return (pgpa + page_pt2off(pt1_idx));
624 * Get first entry of PT2
625 * associated with given PT2s page and PT1 index.
627 static __inline pt2_entry_t *
628 page_pt2(vm_offset_t pgva, u_int pt1_idx)
631 return ((pt2_entry_t *)(pgva + page_pt2off(pt1_idx)));
635 * Get virtual address of PT2s page (mapped in PT2MAP)
636 * which holds PT2 which holds entry which maps given virtual address.
638 static __inline vm_offset_t
639 pt2map_pt2pg(vm_offset_t va)
642 va &= ~(NPT2_IN_PG * PTE1_SIZE - 1);
643 return ((vm_offset_t)pt2map_entry(va));
646 /*****************************************************************************
648 * THREE pmap initialization milestones exist:
651 * -> fundamental init (including MMU) in ASM
654 * -> fundamental init continues in C
655 * -> first available physical address is known
657 * pmap_bootstrap_prepare() -> FIRST PMAP MILESTONE (first epoch begins)
658 * -> basic (safe) interface for physical address allocation is made
659 * -> basic (safe) interface for virtual mapping is made
660 * -> limited not SMP coherent work is possible
662 * -> more fundamental init continues in C
663 * -> locks and some more things are available
664 * -> all fundamental allocations and mappings are done
666 * pmap_bootstrap() -> SECOND PMAP MILESTONE (second epoch begins)
667 * -> phys_avail[] and virtual_avail is set
668 * -> control is passed to vm subsystem
669 * -> physical and virtual address allocation are off limit
670 * -> low level mapping functions, some SMP coherent,
671 * are available, which cannot be used before vm subsystem
675 * -> vm subsystem is being inited
677 * pmap_init() -> THIRD PMAP MILESTONE (third epoch begins)
678 * -> pmap is fully inited
680 *****************************************************************************/
682 /*****************************************************************************
684 * PMAP first stage initialization and utility functions
685 * for pre-bootstrap epoch.
687 * After pmap_bootstrap_prepare() is called, the following functions
690 * (1) strictly only for this stage functions for physical page allocations,
691 * virtual space allocations, and mappings:
693 * vm_paddr_t pmap_preboot_get_pages(u_int num);
694 * void pmap_preboot_map_pages(vm_paddr_t pa, vm_offset_t va, u_int num);
695 * vm_offset_t pmap_preboot_reserve_pages(u_int num);
696 * vm_offset_t pmap_preboot_get_vpages(u_int num);
697 * void pmap_preboot_map_attr(vm_paddr_t pa, vm_offset_t va, vm_size_t size,
698 * vm_prot_t prot, vm_memattr_t attr);
700 * (2) for all stages:
702 * vm_paddr_t pmap_kextract(vm_offset_t va);
704 * NOTE: This is not SMP coherent stage.
706 *****************************************************************************/
708 #define KERNEL_P2V(pa) \
709 ((vm_offset_t)((pa) - arm_physmem_kernaddr + KERNVIRTADDR))
710 #define KERNEL_V2P(va) \
711 ((vm_paddr_t)((va) - KERNVIRTADDR + arm_physmem_kernaddr))
713 static vm_paddr_t last_paddr;
716 * Pre-bootstrap epoch page allocator.
719 pmap_preboot_get_pages(u_int num)
724 last_paddr += num * PAGE_SIZE;
730 * The fundamental initialization of PMAP stuff.
732 * Some things already happened in locore.S and some things could happen
733 * before pmap_bootstrap_prepare() is called, so let's recall what is done:
734 * 1. Caches are disabled.
735 * 2. We are running on virtual addresses already with 'boot_pt1'
737 * 3. So far, all virtual addresses can be converted to physical ones and
738 * vice versa by the following macros:
739 * KERNEL_P2V(pa) .... physical to virtual ones,
740 * KERNEL_V2P(va) .... virtual to physical ones.
742 * What is done herein:
743 * 1. The 'boot_pt1' is replaced by real kernel L1 page table 'kern_pt1'.
744 * 2. PT2MAP magic is brought to live.
745 * 3. Basic preboot functions for page allocations and mappings can be used.
746 * 4. Everything is prepared for L1 cache enabling.
749 * 1. To use second TTB register, so kernel and users page tables will be
750 * separated. This way process forking - pmap_pinit() - could be faster,
751 * it saves physical pages and KVA per a process, and it's simple change.
752 * However, it will lead, due to hardware matter, to the following:
753 * (a) 2G space for kernel and 2G space for users.
754 * (b) 1G space for kernel in low addresses and 3G for users above it.
755 * A question is: Is the case (b) really an option? Note that case (b)
756 * does save neither physical memory and KVA.
759 pmap_bootstrap_prepare(vm_paddr_t last)
761 vm_paddr_t pt2pg_pa, pt2tab_pa, pa, size;
762 vm_offset_t pt2pg_va;
766 uint32_t actlr_mask, actlr_set, l1_attr;
769 * Now, we are going to make real kernel mapping. Note that we are
770 * already running on some mapping made in locore.S and we expect
771 * that it's large enough to ensure nofault access to physical memory
772 * allocated herein before switch.
774 * As kernel image and everything needed before are and will be mapped
775 * by section mappings, we align last physical address to PTE1_SIZE.
777 last_paddr = pte1_roundup(last);
780 * Allocate and zero page(s) for kernel L1 page table.
782 * Note that it's first allocation on space which was PTE1_SIZE
783 * aligned and as such base_pt1 is aligned to NB_IN_PT1 too.
785 base_pt1 = pmap_preboot_get_pages(NPG_IN_PT1);
786 kern_pt1 = (pt1_entry_t *)KERNEL_P2V(base_pt1);
787 bzero((void*)kern_pt1, NB_IN_PT1);
788 pte1_sync_range(kern_pt1, NB_IN_PT1);
790 /* Allocate and zero page(s) for kernel PT2TAB. */
791 pt2tab_pa = pmap_preboot_get_pages(NPG_IN_PT2TAB);
792 kern_pt2tab = (pt2_entry_t *)KERNEL_P2V(pt2tab_pa);
793 bzero(kern_pt2tab, NB_IN_PT2TAB);
794 pte2_sync_range(kern_pt2tab, NB_IN_PT2TAB);
796 /* Allocate and zero page(s) for kernel L2 page tables. */
797 pt2pg_pa = pmap_preboot_get_pages(NKPT2PG);
798 pt2pg_va = KERNEL_P2V(pt2pg_pa);
799 size = NKPT2PG * PAGE_SIZE;
800 bzero((void*)pt2pg_va, size);
801 pte2_sync_range((pt2_entry_t *)pt2pg_va, size);
804 * Add a physical memory segment (vm_phys_seg) corresponding to the
805 * preallocated pages for kernel L2 page tables so that vm_page
806 * structures representing these pages will be created. The vm_page
807 * structures are required for promotion of the corresponding kernel
808 * virtual addresses to section mappings.
810 vm_phys_add_seg(pt2tab_pa, pmap_preboot_get_pages(0));
813 * Insert allocated L2 page table pages to PT2TAB and make
814 * link to all PT2s in L1 page table. See how kernel_vm_end
817 * We play simple and safe. So every KVA will have underlaying
818 * L2 page table, even kernel image mapped by sections.
820 pte2p = kern_pt2tab_entry(KERNBASE);
821 for (pa = pt2pg_pa; pa < pt2pg_pa + size; pa += PTE2_SIZE)
822 pt2tab_store(pte2p++, PTE2_KPT(pa));
824 pte1p = kern_pte1(KERNBASE);
825 for (pa = pt2pg_pa; pa < pt2pg_pa + size; pa += NB_IN_PT2)
826 pte1_store(pte1p++, PTE1_LINK(pa));
828 /* Make section mappings for kernel. */
829 l1_attr = ATTR_TO_L1(PTE2_ATTR_DEFAULT);
830 pte1p = kern_pte1(KERNBASE);
831 for (pa = KERNEL_V2P(KERNBASE); pa < last; pa += PTE1_SIZE)
832 pte1_store(pte1p++, PTE1_KERN(pa, PTE1_AP_KRW, l1_attr));
835 * Get free and aligned space for PT2MAP and make L1 page table links
836 * to L2 page tables held in PT2TAB.
838 * Note that pages holding PT2s are stored in PT2TAB as pt2_entry_t
839 * descriptors and PT2TAB page(s) itself is(are) used as PT2s. Thus
840 * each entry in PT2TAB maps all PT2s in a page. This implies that
841 * virtual address of PT2MAP must be aligned to NPT2_IN_PG * PTE1_SIZE.
843 PT2MAP = (pt2_entry_t *)(KERNBASE - PT2MAP_SIZE);
844 pte1p = kern_pte1((vm_offset_t)PT2MAP);
845 for (pa = pt2tab_pa, i = 0; i < NPT2_IN_PT2TAB; i++, pa += NB_IN_PT2) {
846 pte1_store(pte1p++, PTE1_LINK(pa));
850 * Store PT2TAB in PT2TAB itself, i.e. self reference mapping.
851 * Each pmap will hold own PT2TAB, so the mapping should be not global.
853 pte2p = kern_pt2tab_entry((vm_offset_t)PT2MAP);
854 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE) {
855 pt2tab_store(pte2p++, PTE2_KPT_NG(pa));
859 * Choose correct L2 page table and make mappings for allocations
860 * made herein which replaces temporary locore.S mappings after a while.
861 * Note that PT2MAP cannot be used until we switch to kern_pt1.
863 * Note, that these allocations started aligned on 1M section and
864 * kernel PT1 was allocated first. Making of mappings must follow
865 * order of physical allocations as we've used KERNEL_P2V() macro
866 * for virtual addresses resolution.
868 pte2p = kern_pt2tab_entry((vm_offset_t)kern_pt1);
869 pt2pg_va = KERNEL_P2V(pte2_pa(pte2_load(pte2p)));
871 pte2p = page_pt2(pt2pg_va, pte1_index((vm_offset_t)kern_pt1));
873 /* Make mapping for kernel L1 page table. */
874 for (pa = base_pt1, i = 0; i < NPG_IN_PT1; i++, pa += PTE2_SIZE)
875 pte2_store(pte2p++, PTE2_KPT(pa));
877 /* Make mapping for kernel PT2TAB. */
878 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE)
879 pte2_store(pte2p++, PTE2_KPT(pa));
881 /* Finally, switch from 'boot_pt1' to 'kern_pt1'. */
882 pmap_kern_ttb = base_pt1 | ttb_flags;
883 cpuinfo_get_actlr_modifier(&actlr_mask, &actlr_set);
884 reinit_mmu(pmap_kern_ttb, actlr_mask, actlr_set);
886 * Initialize the first available KVA. As kernel image is mapped by
887 * sections, we are leaving some gap behind.
889 virtual_avail = (vm_offset_t)kern_pt2tab + NPG_IN_PT2TAB * PAGE_SIZE;
893 * Setup L2 page table page for given KVA.
894 * Used in pre-bootstrap epoch.
896 * Note that we have allocated NKPT2PG pages for L2 page tables in advance
897 * and used them for mapping KVA starting from KERNBASE. However, this is not
898 * enough. Vectors and devices need L2 page tables too. Note that they are
899 * even above VM_MAX_KERNEL_ADDRESS.
901 static __inline vm_paddr_t
902 pmap_preboot_pt2pg_setup(vm_offset_t va)
904 pt2_entry_t *pte2p, pte2;
907 /* Get associated entry in PT2TAB. */
908 pte2p = kern_pt2tab_entry(va);
910 /* Just return, if PT2s page exists already. */
911 pte2 = pt2tab_load(pte2p);
912 if (pte2_is_valid(pte2))
913 return (pte2_pa(pte2));
915 KASSERT(va >= VM_MAX_KERNEL_ADDRESS,
916 ("%s: NKPT2PG too small", __func__));
919 * Allocate page for PT2s and insert it to PT2TAB.
920 * In other words, map it into PT2MAP space.
922 pt2pg_pa = pmap_preboot_get_pages(1);
923 pt2tab_store(pte2p, PTE2_KPT(pt2pg_pa));
925 /* Zero all PT2s in allocated page. */
926 bzero((void*)pt2map_pt2pg(va), PAGE_SIZE);
927 pte2_sync_range((pt2_entry_t *)pt2map_pt2pg(va), PAGE_SIZE);
933 * Setup L2 page table for given KVA.
934 * Used in pre-bootstrap epoch.
937 pmap_preboot_pt2_setup(vm_offset_t va)
940 vm_paddr_t pt2pg_pa, pt2_pa;
942 /* Setup PT2's page. */
943 pt2pg_pa = pmap_preboot_pt2pg_setup(va);
944 pt2_pa = page_pt2pa(pt2pg_pa, pte1_index(va));
946 /* Insert PT2 to PT1. */
947 pte1p = kern_pte1(va);
948 pte1_store(pte1p, PTE1_LINK(pt2_pa));
952 * Get L2 page entry associated with given KVA.
953 * Used in pre-bootstrap epoch.
955 static __inline pt2_entry_t*
956 pmap_preboot_vtopte2(vm_offset_t va)
960 /* Setup PT2 if needed. */
961 pte1p = kern_pte1(va);
962 if (!pte1_is_valid(pte1_load(pte1p))) /* XXX - sections ?! */
963 pmap_preboot_pt2_setup(va);
965 return (pt2map_entry(va));
969 * Pre-bootstrap epoch page(s) mapping(s).
972 pmap_preboot_map_pages(vm_paddr_t pa, vm_offset_t va, u_int num)
977 /* Map all the pages. */
978 for (i = 0; i < num; i++) {
979 pte2p = pmap_preboot_vtopte2(va);
980 pte2_store(pte2p, PTE2_KRW(pa));
987 * Pre-bootstrap epoch virtual space alocator.
990 pmap_preboot_reserve_pages(u_int num)
993 vm_offset_t start, va;
996 /* Allocate virtual space. */
997 start = va = virtual_avail;
998 virtual_avail += num * PAGE_SIZE;
1000 /* Zero the mapping. */
1001 for (i = 0; i < num; i++) {
1002 pte2p = pmap_preboot_vtopte2(va);
1003 pte2_store(pte2p, 0);
1011 * Pre-bootstrap epoch page(s) allocation and mapping(s).
1014 pmap_preboot_get_vpages(u_int num)
1019 /* Allocate physical page(s). */
1020 pa = pmap_preboot_get_pages(num);
1022 /* Allocate virtual space. */
1024 virtual_avail += num * PAGE_SIZE;
1026 /* Map and zero all. */
1027 pmap_preboot_map_pages(pa, va, num);
1028 bzero((void *)va, num * PAGE_SIZE);
1034 * Pre-bootstrap epoch page mapping(s) with attributes.
1037 pmap_preboot_map_attr(vm_paddr_t pa, vm_offset_t va, vm_size_t size,
1038 vm_prot_t prot, vm_memattr_t attr)
1041 u_int l1_attr, l1_prot, l2_prot, l2_attr;
1045 l2_prot = prot & VM_PROT_WRITE ? PTE2_AP_KRW : PTE2_AP_KR;
1046 l2_prot |= (prot & VM_PROT_EXECUTE) ? PTE2_X : PTE2_NX;
1047 l2_attr = vm_memattr_to_pte2(attr);
1048 l1_prot = ATTR_TO_L1(l2_prot);
1049 l1_attr = ATTR_TO_L1(l2_attr);
1051 /* Map all the pages. */
1052 num = round_page(size);
1054 if ((((va | pa) & PTE1_OFFSET) == 0) && (num >= PTE1_SIZE)) {
1055 pte1p = kern_pte1(va);
1056 pte1_store(pte1p, PTE1_KERN(pa, l1_prot, l1_attr));
1061 pte2p = pmap_preboot_vtopte2(va);
1062 pte2_store(pte2p, PTE2_KERN(pa, l2_prot, l2_attr));
1071 * Extract from the kernel page table the physical address
1072 * that is mapped by the given virtual address "va".
1075 pmap_kextract(vm_offset_t va)
1081 pte1 = pte1_load(kern_pte1(va));
1082 if (pte1_is_section(pte1)) {
1083 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1084 } else if (pte1_is_link(pte1)) {
1086 * We should beware of concurrent promotion that changes
1087 * pte1 at this point. However, it's not a problem as PT2
1088 * page is preserved by promotion in PT2TAB. So even if
1089 * it happens, using of PT2MAP is still safe.
1091 * QQQ: However, concurrent removing is a problem which
1092 * ends in abort on PT2MAP space. Locking must be used
1093 * to deal with this.
1095 pte2 = pte2_load(pt2map_entry(va));
1096 pa = pte2_pa(pte2) | (va & PTE2_OFFSET);
1099 panic("%s: va %#x pte1 %#x", __func__, va, pte1);
1105 * Extract from the kernel page table the physical address
1106 * that is mapped by the given virtual address "va". Also
1107 * return L2 page table entry which maps the address.
1109 * This is only intended to be used for panic dumps.
1112 pmap_dump_kextract(vm_offset_t va, pt2_entry_t *pte2p)
1118 pte1 = pte1_load(kern_pte1(va));
1119 if (pte1_is_section(pte1)) {
1120 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1121 pte2 = pa | ATTR_TO_L2(pte1) | PTE2_V;
1122 } else if (pte1_is_link(pte1)) {
1123 pte2 = pte2_load(pt2map_entry(va));
1134 /*****************************************************************************
1136 * PMAP second stage initialization and utility functions
1137 * for bootstrap epoch.
1139 * After pmap_bootstrap() is called, the following functions for
1140 * mappings can be used:
1142 * void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
1143 * void pmap_kremove(vm_offset_t va);
1144 * vm_offset_t pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end,
1147 * NOTE: This is not SMP coherent stage. And physical page allocation is not
1148 * allowed during this stage.
1150 *****************************************************************************/
1153 * Initialize kernel PMAP locks and lists, kernel_pmap itself, and
1154 * reserve various virtual spaces for temporary mappings.
1157 pmap_bootstrap(vm_offset_t firstaddr)
1159 pt2_entry_t *unused __unused;
1163 * Initialize the kernel pmap (which is statically allocated).
1165 PMAP_LOCK_INIT(kernel_pmap);
1166 kernel_l1pa = (vm_paddr_t)kern_pt1; /* for libkvm */
1167 kernel_pmap->pm_pt1 = kern_pt1;
1168 kernel_pmap->pm_pt2tab = kern_pt2tab;
1169 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1170 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1173 * Initialize the global pv list lock.
1175 rw_init(&pvh_global_lock, "pmap pv global");
1177 LIST_INIT(&allpmaps);
1180 * Request a spin mutex so that changes to allpmaps cannot be
1181 * preempted by smp_rendezvous_cpus().
1183 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
1184 mtx_lock_spin(&allpmaps_lock);
1185 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
1186 mtx_unlock_spin(&allpmaps_lock);
1189 * Reserve some special page table entries/VA space for temporary
1192 #define SYSMAP(c, p, v, n) do { \
1193 v = (c)pmap_preboot_reserve_pages(n); \
1194 p = pt2map_entry((vm_offset_t)v); \
1198 * Local CMAP1/CMAP2 are used for zeroing and copying pages.
1199 * Local CMAP2 is also used for data cache cleaning.
1202 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
1203 SYSMAP(caddr_t, pc->pc_cmap1_pte2p, pc->pc_cmap1_addr, 1);
1204 SYSMAP(caddr_t, pc->pc_cmap2_pte2p, pc->pc_cmap2_addr, 1);
1205 SYSMAP(vm_offset_t, pc->pc_qmap_pte2p, pc->pc_qmap_addr, 1);
1210 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS);
1213 * _tmppt is used for reading arbitrary physical pages via /dev/mem.
1215 SYSMAP(caddr_t, unused, _tmppt, 1);
1218 * PADDR1 and PADDR2 are used by pmap_pte2_quick() and pmap_pte2(),
1219 * respectively. PADDR3 is used by pmap_pte2_ddb().
1221 SYSMAP(pt2_entry_t *, PMAP1, PADDR1, 1);
1222 SYSMAP(pt2_entry_t *, PMAP2, PADDR2, 1);
1224 SYSMAP(pt2_entry_t *, PMAP3, PADDR3, 1);
1226 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
1229 * Note that in very short time in initarm(), we are going to
1230 * initialize phys_avail[] array and no further page allocation
1231 * can happen after that until vm subsystem will be initialized.
1233 kernel_vm_end_new = kernel_vm_end;
1234 virtual_end = vm_max_kernel_address;
1238 pmap_init_reserved_pages(void)
1247 * Skip if the mapping has already been initialized,
1248 * i.e. this is the BSP.
1250 if (pc->pc_cmap1_addr != 0)
1252 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
1253 pages = kva_alloc(PAGE_SIZE * 3);
1255 panic("%s: unable to allocate KVA", __func__);
1256 pc->pc_cmap1_pte2p = pt2map_entry(pages);
1257 pc->pc_cmap2_pte2p = pt2map_entry(pages + PAGE_SIZE);
1258 pc->pc_qmap_pte2p = pt2map_entry(pages + (PAGE_SIZE * 2));
1259 pc->pc_cmap1_addr = (caddr_t)pages;
1260 pc->pc_cmap2_addr = (caddr_t)(pages + PAGE_SIZE);
1261 pc->pc_qmap_addr = pages + (PAGE_SIZE * 2);
1264 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
1267 * The function can already be use in second initialization stage.
1268 * As such, the function DOES NOT call pmap_growkernel() where PT2
1269 * allocation can happen. So if used, be sure that PT2 for given
1270 * virtual address is allocated already!
1272 * Add a wired page to the kva.
1273 * Note: not SMP coherent.
1275 static __inline void
1276 pmap_kenter_prot_attr(vm_offset_t va, vm_paddr_t pa, uint32_t prot,
1282 pte1p = kern_pte1(va);
1283 if (!pte1_is_valid(pte1_load(pte1p))) { /* XXX - sections ?! */
1285 * This is a very low level function, so PT2 and particularly
1286 * PT2PG associated with given virtual address must be already
1287 * allocated. It's a pain mainly during pmap initialization
1288 * stage. However, called after pmap initialization with
1289 * virtual address not under kernel_vm_end will lead to
1292 if (!pte2_is_valid(pte2_load(kern_pt2tab_entry(va))))
1293 panic("%s: kernel PT2 not allocated!", __func__);
1296 pte2p = pt2map_entry(va);
1297 pte2_store(pte2p, PTE2_KERN(pa, prot, attr));
1301 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1304 pmap_kenter_prot_attr(va, pa, PTE2_AP_KRW, PTE2_ATTR_DEFAULT);
1308 * Remove a page from the kernel pagetables.
1309 * Note: not SMP coherent.
1312 pmap_kremove(vm_offset_t va)
1316 pte2p = pt2map_entry(va);
1321 * Share new kernel PT2PG with all pmaps.
1322 * The caller is responsible for maintaining TLB consistency.
1325 pmap_kenter_pt2tab(vm_offset_t va, pt2_entry_t npte2)
1330 mtx_lock_spin(&allpmaps_lock);
1331 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1332 pte2p = pmap_pt2tab_entry(pmap, va);
1333 pt2tab_store(pte2p, npte2);
1335 mtx_unlock_spin(&allpmaps_lock);
1339 * Share new kernel PTE1 with all pmaps.
1340 * The caller is responsible for maintaining TLB consistency.
1343 pmap_kenter_pte1(vm_offset_t va, pt1_entry_t npte1)
1348 mtx_lock_spin(&allpmaps_lock);
1349 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1350 pte1p = pmap_pte1(pmap, va);
1351 pte1_store(pte1p, npte1);
1353 mtx_unlock_spin(&allpmaps_lock);
1357 * Used to map a range of physical addresses into kernel
1358 * virtual address space.
1360 * The value passed in '*virt' is a suggested virtual address for
1361 * the mapping. Architectures which can support a direct-mapped
1362 * physical to virtual region can return the appropriate address
1363 * within that region, leaving '*virt' unchanged. Other
1364 * architectures should map the pages starting at '*virt' and
1365 * update '*virt' with the first usable address after the mapped
1368 * NOTE: Read the comments above pmap_kenter_prot_attr() as
1369 * the function is used herein!
1372 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1374 vm_offset_t va, sva;
1375 vm_paddr_t pte1_offset;
1377 uint32_t l1prot, l2prot;
1378 uint32_t l1attr, l2attr;
1380 PDEBUG(1, printf("%s: virt = %#x, start = %#x, end = %#x (size = %#x),"
1381 " prot = %d\n", __func__, *virt, start, end, end - start, prot));
1383 l2prot = (prot & VM_PROT_WRITE) ? PTE2_AP_KRW : PTE2_AP_KR;
1384 l2prot |= (prot & VM_PROT_EXECUTE) ? PTE2_X : PTE2_NX;
1385 l1prot = ATTR_TO_L1(l2prot);
1387 l2attr = PTE2_ATTR_DEFAULT;
1388 l1attr = ATTR_TO_L1(l2attr);
1392 * Does the physical address range's size and alignment permit at
1393 * least one section mapping to be created?
1395 pte1_offset = start & PTE1_OFFSET;
1396 if ((end - start) - ((PTE1_SIZE - pte1_offset) & PTE1_OFFSET) >=
1399 * Increase the starting virtual address so that its alignment
1400 * does not preclude the use of section mappings.
1402 if ((va & PTE1_OFFSET) < pte1_offset)
1403 va = pte1_trunc(va) + pte1_offset;
1404 else if ((va & PTE1_OFFSET) > pte1_offset)
1405 va = pte1_roundup(va) + pte1_offset;
1408 while (start < end) {
1409 if ((start & PTE1_OFFSET) == 0 && end - start >= PTE1_SIZE) {
1410 KASSERT((va & PTE1_OFFSET) == 0,
1411 ("%s: misaligned va %#x", __func__, va));
1412 npte1 = PTE1_KERN(start, l1prot, l1attr);
1413 pmap_kenter_pte1(va, npte1);
1417 pmap_kenter_prot_attr(va, start, l2prot, l2attr);
1422 tlb_flush_range(sva, va - sva);
1428 * Make a temporary mapping for a physical address.
1429 * This is only intended to be used for panic dumps.
1432 pmap_kenter_temporary(vm_paddr_t pa, int i)
1436 /* QQQ: 'i' should be less or equal to MAXDUMPPGS. */
1438 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
1439 pmap_kenter(va, pa);
1440 tlb_flush_local(va);
1441 return ((void *)crashdumpmap);
1445 /*************************************
1447 * TLB & cache maintenance routines.
1449 *************************************/
1452 * We inline these within pmap.c for speed.
1455 pmap_tlb_flush(pmap_t pmap, vm_offset_t va)
1458 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1463 pmap_tlb_flush_range(pmap_t pmap, vm_offset_t sva, vm_size_t size)
1466 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1467 tlb_flush_range(sva, size);
1471 * Abuse the pte2 nodes for unmapped kva to thread a kva freelist through.
1473 * - Must deal with pages in order to ensure that none of the PTE2_* bits
1474 * are ever set, PTE2_V in particular.
1475 * - Assumes we can write to pte2s without pte2_store() atomic ops.
1476 * - Assumes nothing will ever test these addresses for 0 to indicate
1477 * no mapping instead of correctly checking PTE2_V.
1478 * - Assumes a vm_offset_t will fit in a pte2 (true for arm).
1479 * Because PTE2_V is never set, there can be no mappings to invalidate.
1482 pmap_pte2list_alloc(vm_offset_t *head)
1489 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
1490 pte2p = pt2map_entry(va);
1493 panic("%s: va with PTE2_V set!", __func__);
1499 pmap_pte2list_free(vm_offset_t *head, vm_offset_t va)
1504 panic("%s: freeing va with PTE2_V set!", __func__);
1505 pte2p = pt2map_entry(va);
1506 *pte2p = *head; /* virtual! PTE2_V is 0 though */
1511 pmap_pte2list_init(vm_offset_t *head, void *base, int npages)
1517 for (i = npages - 1; i >= 0; i--) {
1518 va = (vm_offset_t)base + i * PAGE_SIZE;
1519 pmap_pte2list_free(head, va);
1523 /*****************************************************************************
1525 * PMAP third and final stage initialization.
1527 * After pmap_init() is called, PMAP subsystem is fully initialized.
1529 *****************************************************************************/
1531 SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
1533 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
1534 "Max number of PV entries");
1535 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
1536 "Page share factor per proc");
1538 static u_long nkpt2pg = NKPT2PG;
1539 SYSCTL_ULONG(_vm_pmap, OID_AUTO, nkpt2pg, CTLFLAG_RD,
1540 &nkpt2pg, 0, "Pre-allocated pages for kernel PT2s");
1542 static int sp_enabled = 1;
1543 SYSCTL_INT(_vm_pmap, OID_AUTO, sp_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
1544 &sp_enabled, 0, "Are large page mappings enabled?");
1546 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pte1, CTLFLAG_RD, 0,
1547 "1MB page mapping counters");
1549 static u_long pmap_pte1_demotions;
1550 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, demotions, CTLFLAG_RD,
1551 &pmap_pte1_demotions, 0, "1MB page demotions");
1553 static u_long pmap_pte1_mappings;
1554 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, mappings, CTLFLAG_RD,
1555 &pmap_pte1_mappings, 0, "1MB page mappings");
1557 static u_long pmap_pte1_p_failures;
1558 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, p_failures, CTLFLAG_RD,
1559 &pmap_pte1_p_failures, 0, "1MB page promotion failures");
1561 static u_long pmap_pte1_promotions;
1562 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, promotions, CTLFLAG_RD,
1563 &pmap_pte1_promotions, 0, "1MB page promotions");
1565 static u_long pmap_pte1_kern_demotions;
1566 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, kern_demotions, CTLFLAG_RD,
1567 &pmap_pte1_kern_demotions, 0, "1MB page kernel demotions");
1569 static u_long pmap_pte1_kern_promotions;
1570 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, kern_promotions, CTLFLAG_RD,
1571 &pmap_pte1_kern_promotions, 0, "1MB page kernel promotions");
1573 static __inline ttb_entry_t
1574 pmap_ttb_get(pmap_t pmap)
1577 return (vtophys(pmap->pm_pt1) | ttb_flags);
1581 * Initialize a vm_page's machine-dependent fields.
1584 * 1. Pages for L2 page tables are always not managed. So, pv_list and
1585 * pt2_wirecount can share same physical space. However, proper
1586 * initialization on a page alloc for page tables and reinitialization
1587 * on the page free must be ensured.
1590 pmap_page_init(vm_page_t m)
1593 TAILQ_INIT(&m->md.pv_list);
1594 pt2_wirecount_init(m);
1595 m->md.pat_mode = VM_MEMATTR_DEFAULT;
1599 * Virtualization for faster way how to zero whole page.
1601 static __inline void
1602 pagezero(void *page)
1605 bzero(page, PAGE_SIZE);
1609 * Zero L2 page table page.
1610 * Use same KVA as in pmap_zero_page().
1612 static __inline vm_paddr_t
1613 pmap_pt2pg_zero(vm_page_t m)
1615 pt2_entry_t *cmap2_pte2p;
1619 pa = VM_PAGE_TO_PHYS(m);
1622 * XXX: For now, we map whole page even if it's already zero,
1623 * to sync it even if the sync is only DSB.
1627 cmap2_pte2p = pc->pc_cmap2_pte2p;
1628 mtx_lock(&pc->pc_cmap_lock);
1629 if (pte2_load(cmap2_pte2p) != 0)
1630 panic("%s: CMAP2 busy", __func__);
1631 pte2_store(cmap2_pte2p, PTE2_KERN_NG(pa, PTE2_AP_KRW,
1632 vm_page_pte2_attr(m)));
1633 /* Even VM_ALLOC_ZERO request is only advisory. */
1634 if ((m->flags & PG_ZERO) == 0)
1635 pagezero(pc->pc_cmap2_addr);
1636 pte2_sync_range((pt2_entry_t *)pc->pc_cmap2_addr, PAGE_SIZE);
1637 pte2_clear(cmap2_pte2p);
1638 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
1641 * Unpin the thread before releasing the lock. Otherwise the thread
1642 * could be rescheduled while still bound to the current CPU, only
1643 * to unpin itself immediately upon resuming execution.
1646 mtx_unlock(&pc->pc_cmap_lock);
1652 * Init just allocated page as L2 page table(s) holder
1653 * and return its physical address.
1655 static __inline vm_paddr_t
1656 pmap_pt2pg_init(pmap_t pmap, vm_offset_t va, vm_page_t m)
1661 /* Check page attributes. */
1662 if (m->md.pat_mode != pt_memattr)
1663 pmap_page_set_memattr(m, pt_memattr);
1665 /* Zero page and init wire counts. */
1666 pa = pmap_pt2pg_zero(m);
1667 pt2_wirecount_init(m);
1670 * Map page to PT2MAP address space for given pmap.
1671 * Note that PT2MAP space is shared with all pmaps.
1673 if (pmap == kernel_pmap)
1674 pmap_kenter_pt2tab(va, PTE2_KPT(pa));
1676 pte2p = pmap_pt2tab_entry(pmap, va);
1677 pt2tab_store(pte2p, PTE2_KPT_NG(pa));
1684 * Initialize the pmap module.
1685 * Called by vm_init, to initialize any structures that the pmap
1686 * system needs to map virtual memory.
1692 pt2_entry_t *pte2p, pte2;
1693 u_int i, pte1_idx, pv_npg;
1695 PDEBUG(1, printf("%s: phys_start = %#x\n", __func__, PHYSADDR));
1698 * Initialize the vm page array entries for kernel pmap's
1699 * L2 page table pages allocated in advance.
1701 pte1_idx = pte1_index(KERNBASE - PT2MAP_SIZE);
1702 pte2p = kern_pt2tab_entry(KERNBASE - PT2MAP_SIZE);
1703 for (i = 0; i < nkpt2pg + NPG_IN_PT2TAB; i++, pte2p++) {
1707 pte2 = pte2_load(pte2p);
1708 KASSERT(pte2_is_valid(pte2), ("%s: no valid entry", __func__));
1711 m = PHYS_TO_VM_PAGE(pa);
1712 KASSERT(m >= vm_page_array &&
1713 m < &vm_page_array[vm_page_array_size],
1714 ("%s: L2 page table page is out of range", __func__));
1716 m->pindex = pte1_idx;
1718 pte1_idx += NPT2_IN_PG;
1722 * Initialize the address space (zone) for the pv entries. Set a
1723 * high water mark so that the system can recover from excessive
1724 * numbers of pv entries.
1726 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1727 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1728 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1729 pv_entry_max = roundup(pv_entry_max, _NPCPV);
1730 pv_entry_high_water = 9 * (pv_entry_max / 10);
1733 * Are large page mappings enabled?
1735 TUNABLE_INT_FETCH("vm.pmap.sp_enabled", &sp_enabled);
1737 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1738 ("%s: can't assign to pagesizes[1]", __func__));
1739 pagesizes[1] = PTE1_SIZE;
1743 * Calculate the size of the pv head table for sections.
1744 * Handle the possibility that "vm_phys_segs[...].end" is zero.
1745 * Note that the table is only for sections which could be promoted.
1747 first_managed_pa = pte1_trunc(vm_phys_segs[0].start);
1748 pv_npg = (pte1_trunc(vm_phys_segs[vm_phys_nsegs - 1].end - PAGE_SIZE)
1749 - first_managed_pa) / PTE1_SIZE + 1;
1752 * Allocate memory for the pv head table for sections.
1754 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1756 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
1758 for (i = 0; i < pv_npg; i++)
1759 TAILQ_INIT(&pv_table[i].pv_list);
1761 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
1762 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
1763 if (pv_chunkbase == NULL)
1764 panic("%s: not enough kvm for pv chunks", __func__);
1765 pmap_pte2list_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
1769 * Add a list of wired pages to the kva
1770 * this routine is only used for temporary
1771 * kernel mappings that do not need to have
1772 * page modification or references recorded.
1773 * Note that old mappings are simply written
1774 * over. The page *must* be wired.
1775 * Note: SMP coherent. Uses a ranged shootdown IPI.
1778 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1781 pt2_entry_t *epte2p, *pte2p, pte2;
1786 pte2p = pt2map_entry(sva);
1787 epte2p = pte2p + count;
1788 while (pte2p < epte2p) {
1790 pa = VM_PAGE_TO_PHYS(m);
1791 pte2 = pte2_load(pte2p);
1792 if ((pte2_pa(pte2) != pa) ||
1793 (pte2_attr(pte2) != vm_page_pte2_attr(m))) {
1795 pte2_store(pte2p, PTE2_KERN(pa, PTE2_AP_KRW,
1796 vm_page_pte2_attr(m)));
1800 if (__predict_false(anychanged))
1801 tlb_flush_range(sva, count * PAGE_SIZE);
1805 * This routine tears out page mappings from the
1806 * kernel -- it is meant only for temporary mappings.
1807 * Note: SMP coherent. Uses a ranged shootdown IPI.
1810 pmap_qremove(vm_offset_t sva, int count)
1815 while (count-- > 0) {
1819 tlb_flush_range(sva, va - sva);
1823 * Are we current address space or kernel?
1826 pmap_is_current(pmap_t pmap)
1829 return (pmap == kernel_pmap ||
1830 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace)));
1834 * If the given pmap is not the current or kernel pmap, the returned
1835 * pte2 must be released by passing it to pmap_pte2_release().
1837 static pt2_entry_t *
1838 pmap_pte2(pmap_t pmap, vm_offset_t va)
1841 vm_paddr_t pt2pg_pa;
1843 pte1 = pte1_load(pmap_pte1(pmap, va));
1844 if (pte1_is_section(pte1))
1845 panic("%s: attempt to map PTE1", __func__);
1846 if (pte1_is_link(pte1)) {
1847 /* Are we current address space or kernel? */
1848 if (pmap_is_current(pmap))
1849 return (pt2map_entry(va));
1850 /* Note that L2 page table size is not equal to PAGE_SIZE. */
1851 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
1852 mtx_lock(&PMAP2mutex);
1853 if (pte2_pa(pte2_load(PMAP2)) != pt2pg_pa) {
1854 pte2_store(PMAP2, PTE2_KPT(pt2pg_pa));
1855 tlb_flush((vm_offset_t)PADDR2);
1857 return (PADDR2 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
1863 * Releases a pte2 that was obtained from pmap_pte2().
1864 * Be prepared for the pte2p being NULL.
1866 static __inline void
1867 pmap_pte2_release(pt2_entry_t *pte2p)
1870 if ((pt2_entry_t *)(trunc_page((vm_offset_t)pte2p)) == PADDR2) {
1871 mtx_unlock(&PMAP2mutex);
1876 * Super fast pmap_pte2 routine best used when scanning
1877 * the pv lists. This eliminates many coarse-grained
1878 * invltlb calls. Note that many of the pv list
1879 * scans are across different pmaps. It is very wasteful
1880 * to do an entire tlb flush for checking a single mapping.
1882 * If the given pmap is not the current pmap, pvh_global_lock
1883 * must be held and curthread pinned to a CPU.
1885 static pt2_entry_t *
1886 pmap_pte2_quick(pmap_t pmap, vm_offset_t va)
1889 vm_paddr_t pt2pg_pa;
1891 pte1 = pte1_load(pmap_pte1(pmap, va));
1892 if (pte1_is_section(pte1))
1893 panic("%s: attempt to map PTE1", __func__);
1894 if (pte1_is_link(pte1)) {
1895 /* Are we current address space or kernel? */
1896 if (pmap_is_current(pmap))
1897 return (pt2map_entry(va));
1898 rw_assert(&pvh_global_lock, RA_WLOCKED);
1899 KASSERT(curthread->td_pinned > 0,
1900 ("%s: curthread not pinned", __func__));
1901 /* Note that L2 page table size is not equal to PAGE_SIZE. */
1902 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
1903 if (pte2_pa(pte2_load(PMAP1)) != pt2pg_pa) {
1904 pte2_store(PMAP1, PTE2_KPT(pt2pg_pa));
1906 PMAP1cpu = PCPU_GET(cpuid);
1908 tlb_flush_local((vm_offset_t)PADDR1);
1912 if (PMAP1cpu != PCPU_GET(cpuid)) {
1913 PMAP1cpu = PCPU_GET(cpuid);
1914 tlb_flush_local((vm_offset_t)PADDR1);
1919 return (PADDR1 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
1925 * Routine: pmap_extract
1927 * Extract the physical page address associated
1928 * with the given map/virtual_address pair.
1931 pmap_extract(pmap_t pmap, vm_offset_t va)
1938 pte1 = pte1_load(pmap_pte1(pmap, va));
1939 if (pte1_is_section(pte1))
1940 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1941 else if (pte1_is_link(pte1)) {
1942 pte2p = pmap_pte2(pmap, va);
1943 pa = pte2_pa(pte2_load(pte2p)) | (va & PTE2_OFFSET);
1944 pmap_pte2_release(pte2p);
1952 * Routine: pmap_extract_and_hold
1954 * Atomically extract and hold the physical page
1955 * with the given pmap and virtual address pair
1956 * if that mapping permits the given protection.
1959 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1961 vm_paddr_t pa, lockpa;
1963 pt2_entry_t pte2, *pte2p;
1970 pte1 = pte1_load(pmap_pte1(pmap, va));
1971 if (pte1_is_section(pte1)) {
1972 if (!(pte1 & PTE1_RO) || !(prot & VM_PROT_WRITE)) {
1973 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1974 if (vm_page_pa_tryrelock(pmap, pa, &lockpa))
1976 m = PHYS_TO_VM_PAGE(pa);
1979 } else if (pte1_is_link(pte1)) {
1980 pte2p = pmap_pte2(pmap, va);
1981 pte2 = pte2_load(pte2p);
1982 pmap_pte2_release(pte2p);
1983 if (pte2_is_valid(pte2) &&
1984 (!(pte2 & PTE2_RO) || !(prot & VM_PROT_WRITE))) {
1986 if (vm_page_pa_tryrelock(pmap, pa, &lockpa))
1988 m = PHYS_TO_VM_PAGE(pa);
1992 PA_UNLOCK_COND(lockpa);
1998 * Grow the number of kernel L2 page table entries, if needed.
2001 pmap_growkernel(vm_offset_t addr)
2004 vm_paddr_t pt2pg_pa, pt2_pa;
2008 PDEBUG(1, printf("%s: addr = %#x\n", __func__, addr));
2010 * All the time kernel_vm_end is first KVA for which underlying
2011 * L2 page table is either not allocated or linked from L1 page table
2012 * (not considering sections). Except for two possible cases:
2014 * (1) in the very beginning as long as pmap_growkernel() was
2015 * not called, it could be first unused KVA (which is not
2016 * rounded up to PTE1_SIZE),
2018 * (2) when all KVA space is mapped and kernel_map->max_offset
2019 * address is not rounded up to PTE1_SIZE. (For example,
2020 * it could be 0xFFFFFFFF.)
2022 kernel_vm_end = pte1_roundup(kernel_vm_end);
2023 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2024 addr = roundup2(addr, PTE1_SIZE);
2025 if (addr - 1 >= kernel_map->max_offset)
2026 addr = kernel_map->max_offset;
2027 while (kernel_vm_end < addr) {
2028 pte1 = pte1_load(kern_pte1(kernel_vm_end));
2029 if (pte1_is_valid(pte1)) {
2030 kernel_vm_end += PTE1_SIZE;
2031 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2032 kernel_vm_end = kernel_map->max_offset;
2039 * kernel_vm_end_new is used in pmap_pinit() when kernel
2040 * mappings are entered to new pmap all at once to avoid race
2041 * between pmap_kenter_pte1() and kernel_vm_end increase.
2042 * The same aplies to pmap_kenter_pt2tab().
2044 kernel_vm_end_new = kernel_vm_end + PTE1_SIZE;
2046 pte2 = pt2tab_load(kern_pt2tab_entry(kernel_vm_end));
2047 if (!pte2_is_valid(pte2)) {
2049 * Install new PT2s page into kernel PT2TAB.
2051 m = vm_page_alloc(NULL,
2052 pte1_index(kernel_vm_end) & ~PT2PG_MASK,
2053 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2054 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2056 panic("%s: no memory to grow kernel", __func__);
2058 * QQQ: To link all new L2 page tables from L1 page
2059 * table now and so pmap_kenter_pte1() them
2060 * at once together with pmap_kenter_pt2tab()
2061 * could be nice speed up. However,
2062 * pmap_growkernel() does not happen so often...
2063 * QQQ: The other TTBR is another option.
2065 pt2pg_pa = pmap_pt2pg_init(kernel_pmap, kernel_vm_end,
2068 pt2pg_pa = pte2_pa(pte2);
2070 pt2_pa = page_pt2pa(pt2pg_pa, pte1_index(kernel_vm_end));
2071 pmap_kenter_pte1(kernel_vm_end, PTE1_LINK(pt2_pa));
2073 kernel_vm_end = kernel_vm_end_new;
2074 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2075 kernel_vm_end = kernel_map->max_offset;
2082 kvm_size(SYSCTL_HANDLER_ARGS)
2084 unsigned long ksize = vm_max_kernel_address - KERNBASE;
2086 return (sysctl_handle_long(oidp, &ksize, 0, req));
2088 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2089 0, 0, kvm_size, "IU", "Size of KVM");
2092 kvm_free(SYSCTL_HANDLER_ARGS)
2094 unsigned long kfree = vm_max_kernel_address - kernel_vm_end;
2096 return (sysctl_handle_long(oidp, &kfree, 0, req));
2098 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2099 0, 0, kvm_free, "IU", "Amount of KVM free");
2101 /***********************************************
2103 * Pmap allocation/deallocation routines.
2105 ***********************************************/
2108 * Initialize the pmap for the swapper process.
2111 pmap_pinit0(pmap_t pmap)
2113 PDEBUG(1, printf("%s: pmap = %p\n", __func__, pmap));
2115 PMAP_LOCK_INIT(pmap);
2118 * Kernel page table directory and pmap stuff around is already
2119 * initialized, we are using it right now and here. So, finish
2120 * only PMAP structures initialization for process0 ...
2122 * Since the L1 page table and PT2TAB is shared with the kernel pmap,
2123 * which is already included in the list "allpmaps", this pmap does
2124 * not need to be inserted into that list.
2126 pmap->pm_pt1 = kern_pt1;
2127 pmap->pm_pt2tab = kern_pt2tab;
2128 CPU_ZERO(&pmap->pm_active);
2129 PCPU_SET(curpmap, pmap);
2130 TAILQ_INIT(&pmap->pm_pvchunk);
2131 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2132 CPU_SET(0, &pmap->pm_active);
2135 static __inline void
2136 pte1_copy_nosync(pt1_entry_t *spte1p, pt1_entry_t *dpte1p, vm_offset_t sva,
2141 idx = pte1_index(sva);
2142 count = (pte1_index(eva) - idx + 1) * sizeof(pt1_entry_t);
2143 bcopy(spte1p + idx, dpte1p + idx, count);
2146 static __inline void
2147 pt2tab_copy_nosync(pt2_entry_t *spte2p, pt2_entry_t *dpte2p, vm_offset_t sva,
2152 idx = pt2tab_index(sva);
2153 count = (pt2tab_index(eva) - idx + 1) * sizeof(pt2_entry_t);
2154 bcopy(spte2p + idx, dpte2p + idx, count);
2158 * Initialize a preallocated and zeroed pmap structure,
2159 * such as one in a vmspace structure.
2162 pmap_pinit(pmap_t pmap)
2166 vm_paddr_t pa, pt2tab_pa;
2169 PDEBUG(6, printf("%s: pmap = %p, pm_pt1 = %p\n", __func__, pmap,
2173 * No need to allocate L2 page table space yet but we do need
2174 * a valid L1 page table and PT2TAB table.
2176 * Install shared kernel mappings to these tables. It's a little
2177 * tricky as some parts of KVA are reserved for vectors, devices,
2178 * and whatever else. These parts are supposed to be above
2179 * vm_max_kernel_address. Thus two regions should be installed:
2181 * (1) <KERNBASE, kernel_vm_end),
2182 * (2) <vm_max_kernel_address, 0xFFFFFFFF>.
2184 * QQQ: The second region should be stable enough to be installed
2185 * only once in time when the tables are allocated.
2186 * QQQ: Maybe copy of both regions at once could be faster ...
2187 * QQQ: Maybe the other TTBR is an option.
2189 * Finally, install own PT2TAB table to these tables.
2192 if (pmap->pm_pt1 == NULL) {
2193 pmap->pm_pt1 = (pt1_entry_t *)kmem_alloc_contig(kernel_arena,
2194 NB_IN_PT1, M_NOWAIT | M_ZERO, 0, -1UL, NB_IN_PT1, 0,
2196 if (pmap->pm_pt1 == NULL)
2199 if (pmap->pm_pt2tab == NULL) {
2201 * QQQ: (1) PT2TAB must be contiguous. If PT2TAB is one page
2202 * only, what should be the only size for 32 bit systems,
2203 * then we could allocate it with vm_page_alloc() and all
2204 * the stuff needed as other L2 page table pages.
2205 * (2) Note that a process PT2TAB is special L2 page table
2206 * page. Its mapping in kernel_arena is permanent and can
2207 * be used no matter which process is current. Its mapping
2208 * in PT2MAP can be used only for current process.
2210 pmap->pm_pt2tab = (pt2_entry_t *)kmem_alloc_attr(kernel_arena,
2211 NB_IN_PT2TAB, M_NOWAIT | M_ZERO, 0, -1UL, pt_memattr);
2212 if (pmap->pm_pt2tab == NULL) {
2214 * QQQ: As struct pmap is allocated from UMA with
2215 * UMA_ZONE_NOFREE flag, it's important to leave
2216 * no allocation in pmap if initialization failed.
2218 kmem_free(kernel_arena, (vm_offset_t)pmap->pm_pt1,
2220 pmap->pm_pt1 = NULL;
2224 * QQQ: Each L2 page table page vm_page_t has pindex set to
2225 * pte1 index of virtual address mapped by this page.
2226 * It's not valid for non kernel PT2TABs themselves.
2227 * The pindex of these pages can not be altered because
2228 * of the way how they are allocated now. However, it
2229 * should not be a problem.
2233 mtx_lock_spin(&allpmaps_lock);
2235 * To avoid race with pmap_kenter_pte1() and pmap_kenter_pt2tab(),
2236 * kernel_vm_end_new is used here instead of kernel_vm_end.
2238 pte1_copy_nosync(kern_pt1, pmap->pm_pt1, KERNBASE,
2239 kernel_vm_end_new - 1);
2240 pte1_copy_nosync(kern_pt1, pmap->pm_pt1, vm_max_kernel_address,
2242 pt2tab_copy_nosync(kern_pt2tab, pmap->pm_pt2tab, KERNBASE,
2243 kernel_vm_end_new - 1);
2244 pt2tab_copy_nosync(kern_pt2tab, pmap->pm_pt2tab, vm_max_kernel_address,
2246 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
2247 mtx_unlock_spin(&allpmaps_lock);
2250 * Store PT2MAP PT2 pages (a.k.a. PT2TAB) in PT2TAB itself.
2251 * I.e. self reference mapping. The PT2TAB is private, however mapped
2252 * into shared PT2MAP space, so the mapping should be not global.
2254 pt2tab_pa = vtophys(pmap->pm_pt2tab);
2255 pte2p = pmap_pt2tab_entry(pmap, (vm_offset_t)PT2MAP);
2256 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE) {
2257 pt2tab_store(pte2p++, PTE2_KPT_NG(pa));
2260 /* Insert PT2MAP PT2s into pmap PT1. */
2261 pte1p = pmap_pte1(pmap, (vm_offset_t)PT2MAP);
2262 for (pa = pt2tab_pa, i = 0; i < NPT2_IN_PT2TAB; i++, pa += NB_IN_PT2) {
2263 pte1_store(pte1p++, PTE1_LINK(pa));
2267 * Now synchronize new mapping which was made above.
2269 pte1_sync_range(pmap->pm_pt1, NB_IN_PT1);
2270 pte2_sync_range(pmap->pm_pt2tab, NB_IN_PT2TAB);
2272 CPU_ZERO(&pmap->pm_active);
2273 TAILQ_INIT(&pmap->pm_pvchunk);
2274 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2281 pt2tab_user_is_empty(pt2_entry_t *tab)
2285 end = pt2tab_index(VM_MAXUSER_ADDRESS);
2286 for (i = 0; i < end; i++)
2287 if (tab[i] != 0) return (FALSE);
2292 * Release any resources held by the given physical map.
2293 * Called when a pmap initialized by pmap_pinit is being released.
2294 * Should only be called if the map contains no valid mappings.
2297 pmap_release(pmap_t pmap)
2300 vm_offset_t start, end;
2302 KASSERT(pmap->pm_stats.resident_count == 0,
2303 ("%s: pmap resident count %ld != 0", __func__,
2304 pmap->pm_stats.resident_count));
2305 KASSERT(pt2tab_user_is_empty(pmap->pm_pt2tab),
2306 ("%s: has allocated user PT2(s)", __func__));
2307 KASSERT(CPU_EMPTY(&pmap->pm_active),
2308 ("%s: pmap %p is active on some CPU(s)", __func__, pmap));
2310 mtx_lock_spin(&allpmaps_lock);
2311 LIST_REMOVE(pmap, pm_list);
2312 mtx_unlock_spin(&allpmaps_lock);
2315 start = pte1_index(KERNBASE) * sizeof(pt1_entry_t);
2316 end = (pte1_index(0xFFFFFFFF) + 1) * sizeof(pt1_entry_t);
2317 bzero((char *)pmap->pm_pt1 + start, end - start);
2319 start = pt2tab_index(KERNBASE) * sizeof(pt2_entry_t);
2320 end = (pt2tab_index(0xFFFFFFFF) + 1) * sizeof(pt2_entry_t);
2321 bzero((char *)pmap->pm_pt2tab + start, end - start);
2324 * We are leaving PT1 and PT2TAB allocated on released pmap,
2325 * so hopefully UMA vmspace_zone will always be inited with
2326 * UMA_ZONE_NOFREE flag.
2330 /*********************************************************
2332 * L2 table pages and their pages management routines.
2334 *********************************************************/
2337 * Virtual interface for L2 page table wire counting.
2339 * Each L2 page table in a page has own counter which counts a number of
2340 * valid mappings in a table. Global page counter counts mappings in all
2341 * tables in a page plus a single itself mapping in PT2TAB.
2343 * During a promotion we leave the associated L2 page table counter
2344 * untouched, so the table (strictly speaking a page which holds it)
2345 * is never freed if promoted.
2347 * If a page m->wire_count == 1 then no valid mappings exist in any L2 page
2348 * table in the page and the page itself is only mapped in PT2TAB.
2351 static __inline void
2352 pt2_wirecount_init(vm_page_t m)
2357 * Note: A page m is allocated with VM_ALLOC_WIRED flag and
2358 * m->wire_count should be already set correctly.
2359 * So, there is no need to set it again herein.
2361 for (i = 0; i < NPT2_IN_PG; i++)
2362 m->md.pt2_wirecount[i] = 0;
2365 static __inline void
2366 pt2_wirecount_inc(vm_page_t m, uint32_t pte1_idx)
2370 * Note: A just modificated pte2 (i.e. already allocated)
2371 * is acquiring one extra reference which must be
2372 * explicitly cleared. It influences the KASSERTs herein.
2373 * All L2 page tables in a page always belong to the same
2374 * pmap, so we allow only one extra reference for the page.
2376 KASSERT(m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] < (NPTE2_IN_PT2 + 1),
2377 ("%s: PT2 is overflowing ...", __func__));
2378 KASSERT(m->wire_count <= (NPTE2_IN_PG + 1),
2379 ("%s: PT2PG is overflowing ...", __func__));
2382 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]++;
2385 static __inline void
2386 pt2_wirecount_dec(vm_page_t m, uint32_t pte1_idx)
2389 KASSERT(m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] != 0,
2390 ("%s: PT2 is underflowing ...", __func__));
2391 KASSERT(m->wire_count > 1,
2392 ("%s: PT2PG is underflowing ...", __func__));
2395 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]--;
2398 static __inline void
2399 pt2_wirecount_set(vm_page_t m, uint32_t pte1_idx, uint16_t count)
2402 KASSERT(count <= NPTE2_IN_PT2,
2403 ("%s: invalid count %u", __func__, count));
2404 KASSERT(m->wire_count > m->md.pt2_wirecount[pte1_idx & PT2PG_MASK],
2405 ("%s: PT2PG corrupting (%u, %u) ...", __func__, m->wire_count,
2406 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]));
2408 m->wire_count -= m->md.pt2_wirecount[pte1_idx & PT2PG_MASK];
2409 m->wire_count += count;
2410 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] = count;
2412 KASSERT(m->wire_count <= (NPTE2_IN_PG + 1),
2413 ("%s: PT2PG is overflowed (%u) ...", __func__, m->wire_count));
2416 static __inline uint32_t
2417 pt2_wirecount_get(vm_page_t m, uint32_t pte1_idx)
2420 return (m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]);
2423 static __inline boolean_t
2424 pt2_is_empty(vm_page_t m, vm_offset_t va)
2427 return (m->md.pt2_wirecount[pte1_index(va) & PT2PG_MASK] == 0);
2430 static __inline boolean_t
2431 pt2_is_full(vm_page_t m, vm_offset_t va)
2434 return (m->md.pt2_wirecount[pte1_index(va) & PT2PG_MASK] ==
2438 static __inline boolean_t
2439 pt2pg_is_empty(vm_page_t m)
2442 return (m->wire_count == 1);
2446 * This routine is called if the L2 page table
2447 * is not mapped correctly.
2450 _pmap_allocpte2(pmap_t pmap, vm_offset_t va, u_int flags)
2456 vm_paddr_t pt2pg_pa, pt2_pa;
2458 pte1_idx = pte1_index(va);
2459 pte1p = pmap->pm_pt1 + pte1_idx;
2461 KASSERT(pte1_load(pte1p) == 0,
2462 ("%s: pm_pt1[%#x] is not zero: %#x", __func__, pte1_idx,
2465 pte2 = pt2tab_load(pmap_pt2tab_entry(pmap, va));
2466 if (!pte2_is_valid(pte2)) {
2468 * Install new PT2s page into pmap PT2TAB.
2470 m = vm_page_alloc(NULL, pte1_idx & ~PT2PG_MASK,
2471 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2473 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2475 rw_wunlock(&pvh_global_lock);
2477 rw_wlock(&pvh_global_lock);
2482 * Indicate the need to retry. While waiting,
2483 * the L2 page table page may have been allocated.
2487 pmap->pm_stats.resident_count++;
2488 pt2pg_pa = pmap_pt2pg_init(pmap, va, m);
2490 pt2pg_pa = pte2_pa(pte2);
2491 m = PHYS_TO_VM_PAGE(pt2pg_pa);
2494 pt2_wirecount_inc(m, pte1_idx);
2495 pt2_pa = page_pt2pa(pt2pg_pa, pte1_idx);
2496 pte1_store(pte1p, PTE1_LINK(pt2_pa));
2502 pmap_allocpte2(pmap_t pmap, vm_offset_t va, u_int flags)
2505 pt1_entry_t *pte1p, pte1;
2508 pte1_idx = pte1_index(va);
2510 pte1p = pmap->pm_pt1 + pte1_idx;
2511 pte1 = pte1_load(pte1p);
2514 * This supports switching from a 1MB page to a
2517 if (pte1_is_section(pte1)) {
2518 (void)pmap_demote_pte1(pmap, pte1p, va);
2520 * Reload pte1 after demotion.
2522 * Note: Demotion can even fail as either PT2 is not find for
2523 * the virtual address or PT2PG can not be allocated.
2525 pte1 = pte1_load(pte1p);
2529 * If the L2 page table page is mapped, we just increment the
2530 * hold count, and activate it.
2532 if (pte1_is_link(pte1)) {
2533 m = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
2534 pt2_wirecount_inc(m, pte1_idx);
2537 * Here if the PT2 isn't mapped, or if it has
2540 m = _pmap_allocpte2(pmap, va, flags);
2541 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2548 static __inline void
2549 pmap_free_zero_pages(struct spglist *free)
2553 while ((m = SLIST_FIRST(free)) != NULL) {
2554 SLIST_REMOVE_HEAD(free, plinks.s.ss);
2555 /* Preserve the page's PG_ZERO setting. */
2556 vm_page_free_toq(m);
2561 * Schedule the specified unused L2 page table page to be freed. Specifically,
2562 * add the page to the specified list of pages that will be released to the
2563 * physical memory manager after the TLB has been updated.
2565 static __inline void
2566 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free)
2570 * Put page on a list so that it is released after
2571 * *ALL* TLB shootdown is done
2574 pmap_zero_page_check(m);
2576 m->flags |= PG_ZERO;
2577 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2581 * Unwire L2 page tables page.
2584 pmap_unwire_pt2pg(pmap_t pmap, vm_offset_t va, vm_page_t m)
2586 pt1_entry_t *pte1p, opte1 __unused;
2590 KASSERT(pt2pg_is_empty(m),
2591 ("%s: pmap %p PT2PG %p wired", __func__, pmap, m));
2594 * Unmap all L2 page tables in the page from L1 page table.
2596 * QQQ: Individual L2 page tables (except the last one) can be unmapped
2597 * earlier. However, we are doing that this way.
2599 KASSERT(m->pindex == (pte1_index(va) & ~PT2PG_MASK),
2600 ("%s: pmap %p va %#x PT2PG %p bad index", __func__, pmap, va, m));
2601 pte1p = pmap->pm_pt1 + m->pindex;
2602 for (i = 0; i < NPT2_IN_PG; i++, pte1p++) {
2603 KASSERT(m->md.pt2_wirecount[i] == 0,
2604 ("%s: pmap %p PT2 %u (PG %p) wired", __func__, pmap, i, m));
2605 opte1 = pte1_load(pte1p);
2606 if (pte1_is_link(opte1)) {
2609 * Flush intermediate TLB cache.
2611 pmap_tlb_flush(pmap, (m->pindex + i) << PTE1_SHIFT);
2615 KASSERT((opte1 == 0) || pte1_is_section(opte1),
2616 ("%s: pmap %p va %#x bad pte1 %x at %u", __func__,
2617 pmap, va, opte1, i));
2622 * Unmap the page from PT2TAB.
2624 pte2p = pmap_pt2tab_entry(pmap, va);
2625 (void)pt2tab_load_clear(pte2p);
2626 pmap_tlb_flush(pmap, pt2map_pt2pg(va));
2629 pmap->pm_stats.resident_count--;
2632 * This is a release store so that the ordinary store unmapping
2633 * the L2 page table page is globally performed before TLB shoot-
2636 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1);
2640 * Decrements a L2 page table page's wire count, which is used to record the
2641 * number of valid page table entries within the page. If the wire count
2642 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2643 * page table page was unmapped and FALSE otherwise.
2645 static __inline boolean_t
2646 pmap_unwire_pt2(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2648 pt2_wirecount_dec(m, pte1_index(va));
2649 if (pt2pg_is_empty(m)) {
2651 * QQQ: Wire count is zero, so whole page should be zero and
2652 * we can set PG_ZERO flag to it.
2653 * Note that when promotion is enabled, it takes some
2654 * more efforts. See pmap_unwire_pt2_all() below.
2656 pmap_unwire_pt2pg(pmap, va, m);
2657 pmap_add_delayed_free_list(m, free);
2664 * Drop a L2 page table page's wire count at once, which is used to record
2665 * the number of valid L2 page table entries within the page. If the wire
2666 * count drops to zero, then the L2 page table page is unmapped.
2668 static __inline void
2669 pmap_unwire_pt2_all(pmap_t pmap, vm_offset_t va, vm_page_t m,
2670 struct spglist *free)
2672 u_int pte1_idx = pte1_index(va);
2674 KASSERT(m->pindex == (pte1_idx & ~PT2PG_MASK),
2675 ("%s: PT2 page's pindex is wrong", __func__));
2676 KASSERT(m->wire_count > pt2_wirecount_get(m, pte1_idx),
2677 ("%s: bad pt2 wire count %u > %u", __func__, m->wire_count,
2678 pt2_wirecount_get(m, pte1_idx)));
2681 * It's possible that the L2 page table was never used.
2682 * It happened in case that a section was created without promotion.
2684 if (pt2_is_full(m, va)) {
2685 pt2_wirecount_set(m, pte1_idx, 0);
2688 * QQQ: We clear L2 page table now, so when L2 page table page
2689 * is going to be freed, we can set it PG_ZERO flag ...
2690 * This function is called only on section mappings, so
2691 * hopefully it's not to big overload.
2693 * XXX: If pmap is current, existing PT2MAP mapping could be
2696 pmap_zero_page_area(m, page_pt2off(pte1_idx), NB_IN_PT2);
2700 KASSERT(pt2_is_empty(m, va), ("%s: PT2 is not empty (%u)",
2701 __func__, pt2_wirecount_get(m, pte1_idx)));
2703 if (pt2pg_is_empty(m)) {
2704 pmap_unwire_pt2pg(pmap, va, m);
2705 pmap_add_delayed_free_list(m, free);
2710 * After removing a L2 page table entry, this routine is used to
2711 * conditionally free the page, and manage the hold/wire counts.
2714 pmap_unuse_pt2(pmap_t pmap, vm_offset_t va, struct spglist *free)
2719 if (va >= VM_MAXUSER_ADDRESS)
2721 pte1 = pte1_load(pmap_pte1(pmap, va));
2722 mpte = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
2723 return (pmap_unwire_pt2(pmap, va, mpte, free));
2726 /*************************************
2728 * Page management routines.
2730 *************************************/
2732 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2733 CTASSERT(_NPCM == 11);
2734 CTASSERT(_NPCPV == 336);
2736 static __inline struct pv_chunk *
2737 pv_to_chunk(pv_entry_t pv)
2740 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2743 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2745 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2746 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2748 static const uint32_t pc_freemask[_NPCM] = {
2749 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2750 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2751 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2752 PC_FREE0_9, PC_FREE10
2755 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2756 "Current number of pv entries");
2759 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2761 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2762 "Current number of pv entry chunks");
2763 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2764 "Current number of pv entry chunks allocated");
2765 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2766 "Current number of pv entry chunks frees");
2767 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail,
2768 0, "Number of times tried to get a chunk page but failed.");
2770 static long pv_entry_frees, pv_entry_allocs;
2771 static int pv_entry_spare;
2773 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2774 "Current number of pv entry frees");
2775 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs,
2776 0, "Current number of pv entry allocs");
2777 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2778 "Current number of spare pv entries");
2782 * Is given page managed?
2784 static __inline bool
2785 is_managed(vm_paddr_t pa)
2789 m = PHYS_TO_VM_PAGE(pa);
2792 return ((m->oflags & VPO_UNMANAGED) == 0);
2795 static __inline bool
2796 pte1_is_managed(pt1_entry_t pte1)
2799 return (is_managed(pte1_pa(pte1)));
2802 static __inline bool
2803 pte2_is_managed(pt2_entry_t pte2)
2806 return (is_managed(pte2_pa(pte2)));
2810 * We are in a serious low memory condition. Resort to
2811 * drastic measures to free some pages so we can allocate
2812 * another pv entry chunk.
2815 pmap_pv_reclaim(pmap_t locked_pmap)
2818 struct pv_chunk *pc;
2819 struct md_page *pvh;
2822 pt2_entry_t *pte2p, tpte2;
2826 struct spglist free;
2828 int bit, field, freed;
2830 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2834 TAILQ_INIT(&newtail);
2835 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2836 SLIST_EMPTY(&free))) {
2837 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2838 if (pmap != pc->pc_pmap) {
2840 if (pmap != locked_pmap)
2844 /* Avoid deadlock and lock recursion. */
2845 if (pmap > locked_pmap)
2847 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2849 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2855 * Destroy every non-wired, 4 KB page mapping in the chunk.
2858 for (field = 0; field < _NPCM; field++) {
2859 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2860 inuse != 0; inuse &= ~(1UL << bit)) {
2861 bit = ffs(inuse) - 1;
2862 pv = &pc->pc_pventry[field * 32 + bit];
2864 pte1p = pmap_pte1(pmap, va);
2865 if (pte1_is_section(pte1_load(pte1p)))
2867 pte2p = pmap_pte2(pmap, va);
2868 tpte2 = pte2_load(pte2p);
2869 if ((tpte2 & PTE2_W) == 0)
2870 tpte2 = pte2_load_clear(pte2p);
2871 pmap_pte2_release(pte2p);
2872 if ((tpte2 & PTE2_W) != 0)
2875 ("pmap_pv_reclaim: pmap %p va %#x zero pte",
2877 pmap_tlb_flush(pmap, va);
2878 m = PHYS_TO_VM_PAGE(pte2_pa(tpte2));
2879 if (pte2_is_dirty(tpte2))
2881 if ((tpte2 & PTE2_A) != 0)
2882 vm_page_aflag_set(m, PGA_REFERENCED);
2883 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2884 if (TAILQ_EMPTY(&m->md.pv_list) &&
2885 (m->flags & PG_FICTITIOUS) == 0) {
2886 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2887 if (TAILQ_EMPTY(&pvh->pv_list)) {
2888 vm_page_aflag_clear(m,
2892 pc->pc_map[field] |= 1UL << bit;
2893 pmap_unuse_pt2(pmap, va, &free);
2898 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2901 /* Every freed mapping is for a 4 KB page. */
2902 pmap->pm_stats.resident_count -= freed;
2903 PV_STAT(pv_entry_frees += freed);
2904 PV_STAT(pv_entry_spare += freed);
2905 pv_entry_count -= freed;
2906 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2907 for (field = 0; field < _NPCM; field++)
2908 if (pc->pc_map[field] != pc_freemask[field]) {
2909 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2911 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2914 * One freed pv entry in locked_pmap is
2917 if (pmap == locked_pmap)
2921 if (field == _NPCM) {
2922 PV_STAT(pv_entry_spare -= _NPCPV);
2923 PV_STAT(pc_chunk_count--);
2924 PV_STAT(pc_chunk_frees++);
2925 /* Entire chunk is free; return it. */
2926 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2927 pmap_qremove((vm_offset_t)pc, 1);
2928 pmap_pte2list_free(&pv_vafree, (vm_offset_t)pc);
2933 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2935 if (pmap != locked_pmap)
2938 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2939 m_pc = SLIST_FIRST(&free);
2940 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2941 /* Recycle a freed page table page. */
2942 m_pc->wire_count = 1;
2943 atomic_add_int(&vm_cnt.v_wire_count, 1);
2945 pmap_free_zero_pages(&free);
2950 free_pv_chunk(struct pv_chunk *pc)
2954 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2955 PV_STAT(pv_entry_spare -= _NPCPV);
2956 PV_STAT(pc_chunk_count--);
2957 PV_STAT(pc_chunk_frees++);
2958 /* entire chunk is free, return it */
2959 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2960 pmap_qremove((vm_offset_t)pc, 1);
2961 vm_page_unwire(m, PQ_NONE);
2963 pmap_pte2list_free(&pv_vafree, (vm_offset_t)pc);
2967 * Free the pv_entry back to the free list.
2970 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2972 struct pv_chunk *pc;
2973 int idx, field, bit;
2975 rw_assert(&pvh_global_lock, RA_WLOCKED);
2976 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2977 PV_STAT(pv_entry_frees++);
2978 PV_STAT(pv_entry_spare++);
2980 pc = pv_to_chunk(pv);
2981 idx = pv - &pc->pc_pventry[0];
2984 pc->pc_map[field] |= 1ul << bit;
2985 for (idx = 0; idx < _NPCM; idx++)
2986 if (pc->pc_map[idx] != pc_freemask[idx]) {
2988 * 98% of the time, pc is already at the head of the
2989 * list. If it isn't already, move it to the head.
2991 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2993 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2994 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2999 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3004 * Get a new pv_entry, allocating a block from the system
3008 get_pv_entry(pmap_t pmap, boolean_t try)
3010 static const struct timeval printinterval = { 60, 0 };
3011 static struct timeval lastprint;
3014 struct pv_chunk *pc;
3017 rw_assert(&pvh_global_lock, RA_WLOCKED);
3018 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3019 PV_STAT(pv_entry_allocs++);
3021 if (pv_entry_count > pv_entry_high_water)
3022 if (ratecheck(&lastprint, &printinterval))
3023 printf("Approaching the limit on PV entries, consider "
3024 "increasing either the vm.pmap.shpgperproc or the "
3025 "vm.pmap.pv_entry_max tunable.\n");
3027 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3029 for (field = 0; field < _NPCM; field++) {
3030 if (pc->pc_map[field]) {
3031 bit = ffs(pc->pc_map[field]) - 1;
3035 if (field < _NPCM) {
3036 pv = &pc->pc_pventry[field * 32 + bit];
3037 pc->pc_map[field] &= ~(1ul << bit);
3038 /* If this was the last item, move it to tail */
3039 for (field = 0; field < _NPCM; field++)
3040 if (pc->pc_map[field] != 0) {
3041 PV_STAT(pv_entry_spare--);
3042 return (pv); /* not full, return */
3044 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3045 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3046 PV_STAT(pv_entry_spare--);
3051 * Access to the pte2list "pv_vafree" is synchronized by the pvh
3052 * global lock. If "pv_vafree" is currently non-empty, it will
3053 * remain non-empty until pmap_pte2list_alloc() completes.
3055 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3056 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
3059 PV_STAT(pc_chunk_tryfail++);
3062 m = pmap_pv_reclaim(pmap);
3066 PV_STAT(pc_chunk_count++);
3067 PV_STAT(pc_chunk_allocs++);
3068 pc = (struct pv_chunk *)pmap_pte2list_alloc(&pv_vafree);
3069 pmap_qenter((vm_offset_t)pc, &m, 1);
3071 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
3072 for (field = 1; field < _NPCM; field++)
3073 pc->pc_map[field] = pc_freemask[field];
3074 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
3075 pv = &pc->pc_pventry[0];
3076 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3077 PV_STAT(pv_entry_spare += _NPCPV - 1);
3082 * Create a pv entry for page at pa for
3086 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
3090 rw_assert(&pvh_global_lock, RA_WLOCKED);
3091 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3092 pv = get_pv_entry(pmap, FALSE);
3094 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3097 static __inline pv_entry_t
3098 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3102 rw_assert(&pvh_global_lock, RA_WLOCKED);
3103 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3104 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3105 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3113 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3117 pv = pmap_pvh_remove(pvh, pmap, va);
3118 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3119 free_pv_entry(pmap, pv);
3123 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
3125 struct md_page *pvh;
3127 rw_assert(&pvh_global_lock, RA_WLOCKED);
3128 pmap_pvh_free(&m->md, pmap, va);
3129 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
3130 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3131 if (TAILQ_EMPTY(&pvh->pv_list))
3132 vm_page_aflag_clear(m, PGA_WRITEABLE);
3137 pmap_pv_demote_pte1(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3139 struct md_page *pvh;
3141 vm_offset_t va_last;
3144 rw_assert(&pvh_global_lock, RA_WLOCKED);
3145 KASSERT((pa & PTE1_OFFSET) == 0,
3146 ("pmap_pv_demote_pte1: pa is not 1mpage aligned"));
3149 * Transfer the 1mpage's pv entry for this mapping to the first
3152 pvh = pa_to_pvh(pa);
3153 va = pte1_trunc(va);
3154 pv = pmap_pvh_remove(pvh, pmap, va);
3155 KASSERT(pv != NULL, ("pmap_pv_demote_pte1: pv not found"));
3156 m = PHYS_TO_VM_PAGE(pa);
3157 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3158 /* Instantiate the remaining NPTE2_IN_PT2 - 1 pv entries. */
3159 va_last = va + PTE1_SIZE - PAGE_SIZE;
3162 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3163 ("pmap_pv_demote_pte1: page %p is not managed", m));
3165 pmap_insert_entry(pmap, va, m);
3166 } while (va < va_last);
3170 pmap_pv_promote_pte1(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3172 struct md_page *pvh;
3174 vm_offset_t va_last;
3177 rw_assert(&pvh_global_lock, RA_WLOCKED);
3178 KASSERT((pa & PTE1_OFFSET) == 0,
3179 ("pmap_pv_promote_pte1: pa is not 1mpage aligned"));
3182 * Transfer the first page's pv entry for this mapping to the
3183 * 1mpage's pv list. Aside from avoiding the cost of a call
3184 * to get_pv_entry(), a transfer avoids the possibility that
3185 * get_pv_entry() calls pmap_pv_reclaim() and that pmap_pv_reclaim()
3186 * removes one of the mappings that is being promoted.
3188 m = PHYS_TO_VM_PAGE(pa);
3189 va = pte1_trunc(va);
3190 pv = pmap_pvh_remove(&m->md, pmap, va);
3191 KASSERT(pv != NULL, ("pmap_pv_promote_pte1: pv not found"));
3192 pvh = pa_to_pvh(pa);
3193 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3194 /* Free the remaining NPTE2_IN_PT2 - 1 pv entries. */
3195 va_last = va + PTE1_SIZE - PAGE_SIZE;
3199 pmap_pvh_free(&m->md, pmap, va);
3200 } while (va < va_last);
3204 * Conditionally create a pv entry.
3207 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
3211 rw_assert(&pvh_global_lock, RA_WLOCKED);
3212 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3213 if (pv_entry_count < pv_entry_high_water &&
3214 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
3216 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3223 * Create the pv entries for each of the pages within a section.
3226 pmap_pv_insert_pte1(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3228 struct md_page *pvh;
3231 rw_assert(&pvh_global_lock, RA_WLOCKED);
3232 if (pv_entry_count < pv_entry_high_water &&
3233 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
3235 pvh = pa_to_pvh(pa);
3236 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3243 pmap_tlb_flush_pte1(pmap_t pmap, vm_offset_t va, pt1_entry_t npte1)
3246 /* Kill all the small mappings or the big one only. */
3247 if (pte1_is_section(npte1))
3248 pmap_tlb_flush_range(pmap, pte1_trunc(va), PTE1_SIZE);
3250 pmap_tlb_flush(pmap, pte1_trunc(va));
3254 * Update kernel pte1 on all pmaps.
3256 * The following function is called only on one cpu with disabled interrupts.
3257 * In SMP case, smp_rendezvous_cpus() is used to stop other cpus. This way
3258 * nobody can invoke explicit hardware table walk during the update of pte1.
3259 * Unsolicited hardware table walk can still happen, invoked by speculative
3260 * data or instruction prefetch or even by speculative hardware table walk.
3262 * The break-before-make approach should be implemented here. However, it's
3263 * not so easy to do that for kernel mappings as it would be unhappy to unmap
3264 * itself unexpectedly but voluntarily.
3267 pmap_update_pte1_kernel(vm_offset_t va, pt1_entry_t npte1)
3273 * Get current pmap. Interrupts should be disabled here
3274 * so PCPU_GET() is done atomically.
3276 pmap = PCPU_GET(curpmap);
3281 * (1) Change pte1 on current pmap.
3282 * (2) Flush all obsolete TLB entries on current CPU.
3283 * (3) Change pte1 on all pmaps.
3284 * (4) Flush all obsolete TLB entries on all CPUs in SMP case.
3287 pte1p = pmap_pte1(pmap, va);
3288 pte1_store(pte1p, npte1);
3290 /* Kill all the small mappings or the big one only. */
3291 if (pte1_is_section(npte1)) {
3292 pmap_pte1_kern_promotions++;
3293 tlb_flush_range_local(pte1_trunc(va), PTE1_SIZE);
3295 pmap_pte1_kern_demotions++;
3296 tlb_flush_local(pte1_trunc(va));
3300 * In SMP case, this function is called when all cpus are at smp
3301 * rendezvous, so there is no need to use 'allpmaps_lock' lock here.
3302 * In UP case, the function is called with this lock locked.
3304 LIST_FOREACH(pmap, &allpmaps, pm_list) {
3305 pte1p = pmap_pte1(pmap, va);
3306 pte1_store(pte1p, npte1);
3310 /* Kill all the small mappings or the big one only. */
3311 if (pte1_is_section(npte1))
3312 tlb_flush_range(pte1_trunc(va), PTE1_SIZE);
3314 tlb_flush(pte1_trunc(va));
3319 struct pte1_action {
3322 u_int update; /* CPU that updates the PTE1 */
3326 pmap_update_pte1_action(void *arg)
3328 struct pte1_action *act = arg;
3330 if (act->update == PCPU_GET(cpuid))
3331 pmap_update_pte1_kernel(act->va, act->npte1);
3335 * Change pte1 on current pmap.
3336 * Note that kernel pte1 must be changed on all pmaps.
3338 * According to the architecture reference manual published by ARM,
3339 * the behaviour is UNPREDICTABLE when two or more TLB entries map the same VA.
3340 * According to this manual, UNPREDICTABLE behaviours must never happen in
3341 * a viable system. In contrast, on x86 processors, it is not specified which
3342 * TLB entry mapping the virtual address will be used, but the MMU doesn't
3343 * generate a bogus translation the way it does on Cortex-A8 rev 2 (Beaglebone
3346 * It's a problem when either promotion or demotion is being done. The pte1
3347 * update and appropriate TLB flush must be done atomically in general.
3350 pmap_change_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va,
3354 if (pmap == kernel_pmap) {
3355 struct pte1_action act;
3360 act.update = PCPU_GET(cpuid);
3361 smp_rendezvous_cpus(all_cpus, smp_no_rendezvous_barrier,
3362 pmap_update_pte1_action, NULL, &act);
3368 * Use break-before-make approach for changing userland
3369 * mappings. It can cause L1 translation aborts on other
3370 * cores in SMP case. So, special treatment is implemented
3371 * in pmap_fault(). To reduce the likelihood that another core
3372 * will be affected by the broken mapping, disable interrupts
3373 * until the mapping change is completed.
3375 cspr = disable_interrupts(PSR_I | PSR_F);
3377 pmap_tlb_flush_pte1(pmap, va, npte1);
3378 pte1_store(pte1p, npte1);
3379 restore_interrupts(cspr);
3384 pmap_change_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va,
3388 if (pmap == kernel_pmap) {
3389 mtx_lock_spin(&allpmaps_lock);
3390 pmap_update_pte1_kernel(va, npte1);
3391 mtx_unlock_spin(&allpmaps_lock);
3396 * Use break-before-make approach for changing userland
3397 * mappings. It's absolutely safe in UP case when interrupts
3400 cspr = disable_interrupts(PSR_I | PSR_F);
3402 pmap_tlb_flush_pte1(pmap, va, npte1);
3403 pte1_store(pte1p, npte1);
3404 restore_interrupts(cspr);
3410 * Tries to promote the NPTE2_IN_PT2, contiguous 4KB page mappings that are
3411 * within a single page table page (PT2) to a single 1MB page mapping.
3412 * For promotion to occur, two conditions must be met: (1) the 4KB page
3413 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3414 * mappings must have identical characteristics.
3416 * Managed (PG_MANAGED) mappings within the kernel address space are not
3417 * promoted. The reason is that kernel PTE1s are replicated in each pmap but
3418 * pmap_remove_write(), pmap_clear_modify(), and pmap_clear_reference() only
3419 * read the PTE1 from the kernel pmap.
3422 pmap_promote_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3425 pt2_entry_t *fpte2p, fpte2, fpte2_fav;
3426 pt2_entry_t *pte2p, pte2;
3427 vm_offset_t pteva __unused;
3428 vm_page_t m __unused;
3430 PDEBUG(6, printf("%s(%p): try for va %#x pte1 %#x at %p\n", __func__,
3431 pmap, va, pte1_load(pte1p), pte1p));
3433 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3436 * Examine the first PTE2 in the specified PT2. Abort if this PTE2 is
3437 * either invalid, unused, or does not map the first 4KB physical page
3438 * within a 1MB page.
3440 fpte2p = pmap_pte2_quick(pmap, pte1_trunc(va));
3441 fpte2 = pte2_load(fpte2p);
3442 if ((fpte2 & ((PTE2_FRAME & PTE1_OFFSET) | PTE2_A | PTE2_V)) !=
3443 (PTE2_A | PTE2_V)) {
3444 pmap_pte1_p_failures++;
3445 CTR3(KTR_PMAP, "%s: failure(1) for va %#x in pmap %p",
3446 __func__, va, pmap);
3449 if (pte2_is_managed(fpte2) && pmap == kernel_pmap) {
3450 pmap_pte1_p_failures++;
3451 CTR3(KTR_PMAP, "%s: failure(2) for va %#x in pmap %p",
3452 __func__, va, pmap);
3455 if ((fpte2 & (PTE2_NM | PTE2_RO)) == PTE2_NM) {
3457 * When page is not modified, PTE2_RO can be set without
3458 * a TLB invalidation.
3461 pte2_store(fpte2p, fpte2);
3465 * Examine each of the other PTE2s in the specified PT2. Abort if this
3466 * PTE2 maps an unexpected 4KB physical page or does not have identical
3467 * characteristics to the first PTE2.
3469 fpte2_fav = (fpte2 & (PTE2_FRAME | PTE2_A | PTE2_V));
3470 fpte2_fav += PTE1_SIZE - PTE2_SIZE; /* examine from the end */
3471 for (pte2p = fpte2p + NPTE2_IN_PT2 - 1; pte2p > fpte2p; pte2p--) {
3472 pte2 = pte2_load(pte2p);
3473 if ((pte2 & (PTE2_FRAME | PTE2_A | PTE2_V)) != fpte2_fav) {
3474 pmap_pte1_p_failures++;
3475 CTR3(KTR_PMAP, "%s: failure(3) for va %#x in pmap %p",
3476 __func__, va, pmap);
3479 if ((pte2 & (PTE2_NM | PTE2_RO)) == PTE2_NM) {
3481 * When page is not modified, PTE2_RO can be set
3482 * without a TLB invalidation. See note above.
3485 pte2_store(pte2p, pte2);
3486 pteva = pte1_trunc(va) | (pte2 & PTE1_OFFSET &
3488 CTR3(KTR_PMAP, "%s: protect for va %#x in pmap %p",
3489 __func__, pteva, pmap);
3491 if ((pte2 & PTE2_PROMOTE) != (fpte2 & PTE2_PROMOTE)) {
3492 pmap_pte1_p_failures++;
3493 CTR3(KTR_PMAP, "%s: failure(4) for va %#x in pmap %p",
3494 __func__, va, pmap);
3498 fpte2_fav -= PTE2_SIZE;
3501 * The page table page in its current state will stay in PT2TAB
3502 * until the PTE1 mapping the section is demoted by pmap_demote_pte1()
3503 * or destroyed by pmap_remove_pte1().
3505 * Note that L2 page table size is not equal to PAGE_SIZE.
3507 m = PHYS_TO_VM_PAGE(trunc_page(pte1_link_pa(pte1_load(pte1p))));
3508 KASSERT(m >= vm_page_array && m < &vm_page_array[vm_page_array_size],
3509 ("%s: PT2 page is out of range", __func__));
3510 KASSERT(m->pindex == (pte1_index(va) & ~PT2PG_MASK),
3511 ("%s: PT2 page's pindex is wrong", __func__));
3514 * Get pte1 from pte2 format.
3516 npte1 = (fpte2 & PTE1_FRAME) | ATTR_TO_L1(fpte2) | PTE1_V;
3519 * Promote the pv entries.
3521 if (pte2_is_managed(fpte2))
3522 pmap_pv_promote_pte1(pmap, va, pte1_pa(npte1));
3525 * Promote the mappings.
3527 pmap_change_pte1(pmap, pte1p, va, npte1);
3529 pmap_pte1_promotions++;
3530 CTR3(KTR_PMAP, "%s: success for va %#x in pmap %p",
3531 __func__, va, pmap);
3533 PDEBUG(6, printf("%s(%p): success for va %#x pte1 %#x(%#x) at %p\n",
3534 __func__, pmap, va, npte1, pte1_load(pte1p), pte1p));
3538 * Zero L2 page table page.
3540 static __inline void
3541 pmap_clear_pt2(pt2_entry_t *fpte2p)
3545 for (pte2p = fpte2p; pte2p < fpte2p + NPTE2_IN_PT2; pte2p++)
3551 * Removes a 1MB page mapping from the kernel pmap.
3554 pmap_remove_kernel_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3558 pt2_entry_t *fpte2p;
3561 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3562 m = pmap_pt2_page(pmap, va);
3565 * QQQ: Is this function called only on promoted pte1?
3566 * We certainly do section mappings directly
3567 * (without promotion) in kernel !!!
3569 panic("%s: missing pt2 page", __func__);
3571 pte1_idx = pte1_index(va);
3574 * Initialize the L2 page table.
3576 fpte2p = page_pt2(pt2map_pt2pg(va), pte1_idx);
3577 pmap_clear_pt2(fpte2p);
3580 * Remove the mapping.
3582 pt2_pa = page_pt2pa(VM_PAGE_TO_PHYS(m), pte1_idx);
3583 pmap_kenter_pte1(va, PTE1_LINK(pt2_pa));
3586 * QQQ: We do not need to invalidate PT2MAP mapping
3587 * as we did not change it. I.e. the L2 page table page
3588 * was and still is mapped the same way.
3593 * Do the things to unmap a section in a process
3596 pmap_remove_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t sva,
3597 struct spglist *free)
3600 struct md_page *pvh;
3601 vm_offset_t eva, va;
3604 PDEBUG(6, printf("%s(%p): va %#x pte1 %#x at %p\n", __func__, pmap, sva,
3605 pte1_load(pte1p), pte1p));
3607 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3608 KASSERT((sva & PTE1_OFFSET) == 0,
3609 ("%s: sva is not 1mpage aligned", __func__));
3612 * Clear and invalidate the mapping. It should occupy one and only TLB
3613 * entry. So, pmap_tlb_flush() called with aligned address should be
3616 opte1 = pte1_load_clear(pte1p);
3617 pmap_tlb_flush(pmap, sva);
3619 if (pte1_is_wired(opte1))
3620 pmap->pm_stats.wired_count -= PTE1_SIZE / PAGE_SIZE;
3621 pmap->pm_stats.resident_count -= PTE1_SIZE / PAGE_SIZE;
3622 if (pte1_is_managed(opte1)) {
3623 pvh = pa_to_pvh(pte1_pa(opte1));
3624 pmap_pvh_free(pvh, pmap, sva);
3625 eva = sva + PTE1_SIZE;
3626 for (va = sva, m = PHYS_TO_VM_PAGE(pte1_pa(opte1));
3627 va < eva; va += PAGE_SIZE, m++) {
3628 if (pte1_is_dirty(opte1))
3631 vm_page_aflag_set(m, PGA_REFERENCED);
3632 if (TAILQ_EMPTY(&m->md.pv_list) &&
3633 TAILQ_EMPTY(&pvh->pv_list))
3634 vm_page_aflag_clear(m, PGA_WRITEABLE);
3637 if (pmap == kernel_pmap) {
3639 * L2 page table(s) can't be removed from kernel map as
3640 * kernel counts on it (stuff around pmap_growkernel()).
3642 pmap_remove_kernel_pte1(pmap, pte1p, sva);
3645 * Get associated L2 page table page.
3646 * It's possible that the page was never allocated.
3648 m = pmap_pt2_page(pmap, sva);
3650 pmap_unwire_pt2_all(pmap, sva, m, free);
3655 * Fills L2 page table page with mappings to consecutive physical pages.
3657 static __inline void
3658 pmap_fill_pt2(pt2_entry_t *fpte2p, pt2_entry_t npte2)
3662 for (pte2p = fpte2p; pte2p < fpte2p + NPTE2_IN_PT2; pte2p++) {
3663 pte2_store(pte2p, npte2);
3669 * Tries to demote a 1MB page mapping. If demotion fails, the
3670 * 1MB page mapping is invalidated.
3673 pmap_demote_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3675 pt1_entry_t opte1, npte1;
3676 pt2_entry_t *fpte2p, npte2;
3677 vm_paddr_t pt2pg_pa, pt2_pa;
3679 struct spglist free;
3680 uint32_t pte1_idx, isnew = 0;
3682 PDEBUG(6, printf("%s(%p): try for va %#x pte1 %#x at %p\n", __func__,
3683 pmap, va, pte1_load(pte1p), pte1p));
3685 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3687 opte1 = pte1_load(pte1p);
3688 KASSERT(pte1_is_section(opte1), ("%s: opte1 not a section", __func__));
3690 if ((opte1 & PTE1_A) == 0 || (m = pmap_pt2_page(pmap, va)) == NULL) {
3691 KASSERT(!pte1_is_wired(opte1),
3692 ("%s: PT2 page for a wired mapping is missing", __func__));
3695 * Invalidate the 1MB page mapping and return
3696 * "failure" if the mapping was never accessed or the
3697 * allocation of the new page table page fails.
3699 if ((opte1 & PTE1_A) == 0 || (m = vm_page_alloc(NULL,
3700 pte1_index(va) & ~PT2PG_MASK, VM_ALLOC_NOOBJ |
3701 VM_ALLOC_NORMAL | VM_ALLOC_WIRED)) == NULL) {
3703 pmap_remove_pte1(pmap, pte1p, pte1_trunc(va), &free);
3704 pmap_free_zero_pages(&free);
3705 CTR3(KTR_PMAP, "%s: failure for va %#x in pmap %p",
3706 __func__, va, pmap);
3709 if (va < VM_MAXUSER_ADDRESS)
3710 pmap->pm_stats.resident_count++;
3715 * We init all L2 page tables in the page even if
3716 * we are going to change everything for one L2 page
3719 pt2pg_pa = pmap_pt2pg_init(pmap, va, m);
3721 if (va < VM_MAXUSER_ADDRESS) {
3722 if (pt2_is_empty(m, va))
3723 isnew = 1; /* Demoting section w/o promotion. */
3726 KASSERT(pt2_is_full(m, va), ("%s: bad PT2 wire"
3727 " count %u", __func__,
3728 pt2_wirecount_get(m, pte1_index(va))));
3733 pt2pg_pa = VM_PAGE_TO_PHYS(m);
3734 pte1_idx = pte1_index(va);
3736 * If the pmap is current, then the PT2MAP can provide access to
3737 * the page table page (promoted L2 page tables are not unmapped).
3738 * Otherwise, temporarily map the L2 page table page (m) into
3739 * the kernel's address space at either PADDR1 or PADDR2.
3741 * Note that L2 page table size is not equal to PAGE_SIZE.
3743 if (pmap_is_current(pmap))
3744 fpte2p = page_pt2(pt2map_pt2pg(va), pte1_idx);
3745 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
3746 if (pte2_pa(pte2_load(PMAP1)) != pt2pg_pa) {
3747 pte2_store(PMAP1, PTE2_KPT(pt2pg_pa));
3749 PMAP1cpu = PCPU_GET(cpuid);
3751 tlb_flush_local((vm_offset_t)PADDR1);
3755 if (PMAP1cpu != PCPU_GET(cpuid)) {
3756 PMAP1cpu = PCPU_GET(cpuid);
3757 tlb_flush_local((vm_offset_t)PADDR1);
3762 fpte2p = page_pt2((vm_offset_t)PADDR1, pte1_idx);
3764 mtx_lock(&PMAP2mutex);
3765 if (pte2_pa(pte2_load(PMAP2)) != pt2pg_pa) {
3766 pte2_store(PMAP2, PTE2_KPT(pt2pg_pa));
3767 tlb_flush((vm_offset_t)PADDR2);
3769 fpte2p = page_pt2((vm_offset_t)PADDR2, pte1_idx);
3771 pt2_pa = page_pt2pa(pt2pg_pa, pte1_idx);
3772 npte1 = PTE1_LINK(pt2_pa);
3774 KASSERT((opte1 & PTE1_A) != 0,
3775 ("%s: opte1 is missing PTE1_A", __func__));
3776 KASSERT((opte1 & (PTE1_NM | PTE1_RO)) != PTE1_NM,
3777 ("%s: opte1 has PTE1_NM", __func__));
3780 * Get pte2 from pte1 format.
3782 npte2 = pte1_pa(opte1) | ATTR_TO_L2(opte1) | PTE2_V;
3785 * If the L2 page table page is new, initialize it. If the mapping
3786 * has changed attributes, update the page table entries.
3789 pt2_wirecount_set(m, pte1_idx, NPTE2_IN_PT2);
3790 pmap_fill_pt2(fpte2p, npte2);
3791 } else if ((pte2_load(fpte2p) & PTE2_PROMOTE) !=
3792 (npte2 & PTE2_PROMOTE))
3793 pmap_fill_pt2(fpte2p, npte2);
3795 KASSERT(pte2_pa(pte2_load(fpte2p)) == pte2_pa(npte2),
3796 ("%s: fpte2p and npte2 map different physical addresses",
3799 if (fpte2p == PADDR2)
3800 mtx_unlock(&PMAP2mutex);
3803 * Demote the mapping. This pmap is locked. The old PTE1 has
3804 * PTE1_A set. If the old PTE1 has not PTE1_RO set, it also
3805 * has not PTE1_NM set. Thus, there is no danger of a race with
3806 * another processor changing the setting of PTE1_A and/or PTE1_NM
3807 * between the read above and the store below.
3809 pmap_change_pte1(pmap, pte1p, va, npte1);
3812 * Demote the pv entry. This depends on the earlier demotion
3813 * of the mapping. Specifically, the (re)creation of a per-
3814 * page pv entry might trigger the execution of pmap_pv_reclaim(),
3815 * which might reclaim a newly (re)created per-page pv entry
3816 * and destroy the associated mapping. In order to destroy
3817 * the mapping, the PTE1 must have already changed from mapping
3818 * the 1mpage to referencing the page table page.
3820 if (pte1_is_managed(opte1))
3821 pmap_pv_demote_pte1(pmap, va, pte1_pa(opte1));
3823 pmap_pte1_demotions++;
3824 CTR3(KTR_PMAP, "%s: success for va %#x in pmap %p",
3825 __func__, va, pmap);
3827 PDEBUG(6, printf("%s(%p): success for va %#x pte1 %#x(%#x) at %p\n",
3828 __func__, pmap, va, npte1, pte1_load(pte1p), pte1p));
3833 * Insert the given physical page (p) at
3834 * the specified virtual address (v) in the
3835 * target physical map with the protection requested.
3837 * If specified, the page will be wired down, meaning
3838 * that the related pte can not be reclaimed.
3840 * NB: This is the only routine which MAY NOT lazy-evaluate
3841 * or lose information. That is, this routine must actually
3842 * insert this page into the given map NOW.
3845 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3846 u_int flags, int8_t psind)
3850 pt2_entry_t npte2, opte2;
3853 vm_page_t mpte2, om;
3856 va = trunc_page(va);
3858 wired = (flags & PMAP_ENTER_WIRED) != 0;
3860 KASSERT(va <= vm_max_kernel_address, ("%s: toobig", __func__));
3861 KASSERT(va < UPT2V_MIN_ADDRESS || va >= UPT2V_MAX_ADDRESS,
3862 ("%s: invalid to pmap_enter page table pages (va: 0x%x)", __func__,
3864 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3865 VM_OBJECT_ASSERT_LOCKED(m->object);
3867 rw_wlock(&pvh_global_lock);
3872 * In the case that a page table page is not
3873 * resident, we are creating it here.
3875 if (va < VM_MAXUSER_ADDRESS) {
3876 mpte2 = pmap_allocpte2(pmap, va, flags);
3877 if (mpte2 == NULL) {
3878 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3879 ("pmap_allocpte2 failed with sleep allowed"));
3881 rw_wunlock(&pvh_global_lock);
3883 return (KERN_RESOURCE_SHORTAGE);
3886 pte1p = pmap_pte1(pmap, va);
3887 if (pte1_is_section(pte1_load(pte1p)))
3888 panic("%s: attempted on 1MB page", __func__);
3889 pte2p = pmap_pte2_quick(pmap, va);
3891 panic("%s: invalid L1 page table entry va=%#x", __func__, va);
3894 pa = VM_PAGE_TO_PHYS(m);
3895 opte2 = pte2_load(pte2p);
3896 opa = pte2_pa(opte2);
3898 * Mapping has not changed, must be protection or wiring change.
3900 if (pte2_is_valid(opte2) && (opa == pa)) {
3902 * Wiring change, just update stats. We don't worry about
3903 * wiring PT2 pages as they remain resident as long as there
3904 * are valid mappings in them. Hence, if a user page is wired,
3905 * the PT2 page will be also.
3907 if (wired && !pte2_is_wired(opte2))
3908 pmap->pm_stats.wired_count++;
3909 else if (!wired && pte2_is_wired(opte2))
3910 pmap->pm_stats.wired_count--;
3913 * Remove extra pte2 reference
3916 pt2_wirecount_dec(mpte2, pte1_index(va));
3917 if (pte2_is_managed(opte2))
3923 * QQQ: We think that changing physical address on writeable mapping
3924 * is not safe. Well, maybe on kernel address space with correct
3925 * locking, it can make a sense. However, we have no idea why
3926 * anyone should do that on user address space. Are we wrong?
3928 KASSERT((opa == 0) || (opa == pa) ||
3929 !pte2_is_valid(opte2) || ((opte2 & PTE2_RO) != 0),
3930 ("%s: pmap %p va %#x(%#x) opa %#x pa %#x - gotcha %#x %#x!",
3931 __func__, pmap, va, opte2, opa, pa, flags, prot));
3936 * Mapping has changed, invalidate old range and fall through to
3937 * handle validating new mapping.
3940 if (pte2_is_wired(opte2))
3941 pmap->pm_stats.wired_count--;
3942 if (pte2_is_managed(opte2)) {
3943 om = PHYS_TO_VM_PAGE(opa);
3944 pv = pmap_pvh_remove(&om->md, pmap, va);
3947 * Remove extra pte2 reference
3950 pt2_wirecount_dec(mpte2, va >> PTE1_SHIFT);
3952 pmap->pm_stats.resident_count++;
3955 * Enter on the PV list if part of our managed memory.
3957 if ((m->oflags & VPO_UNMANAGED) == 0) {
3958 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3959 ("%s: managed mapping within the clean submap", __func__));
3961 pv = get_pv_entry(pmap, FALSE);
3963 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3964 } else if (pv != NULL)
3965 free_pv_entry(pmap, pv);
3968 * Increment counters
3971 pmap->pm_stats.wired_count++;
3975 * Now validate mapping with desired protection/wiring.
3977 npte2 = PTE2(pa, PTE2_NM, vm_page_pte2_attr(m));
3978 if (prot & VM_PROT_WRITE) {
3979 if (pte2_is_managed(npte2))
3980 vm_page_aflag_set(m, PGA_WRITEABLE);
3984 if ((prot & VM_PROT_EXECUTE) == 0)
3988 if (va < VM_MAXUSER_ADDRESS)
3990 if (pmap != kernel_pmap)
3994 * If the mapping or permission bits are different, we need
3995 * to update the pte2.
3997 * QQQ: Think again and again what to do
3998 * if the mapping is going to be changed!
4000 if ((opte2 & ~(PTE2_NM | PTE2_A)) != (npte2 & ~(PTE2_NM | PTE2_A))) {
4002 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4003 * is set. Do it now, before the mapping is stored and made
4004 * valid for hardware table walk. If done later, there is a race
4005 * for other threads of current process in lazy loading case.
4006 * Don't do it for kernel memory which is mapped with exec
4007 * permission even if the memory isn't going to hold executable
4008 * code. The only time when icache sync is needed is after
4009 * kernel module is loaded and the relocation info is processed.
4010 * And it's done in elf_cpu_load_file().
4012 * QQQ: (1) Does it exist any better way where
4013 * or how to sync icache?
4014 * (2) Now, we do it on a page basis.
4016 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
4017 m->md.pat_mode == VM_MEMATTR_WB_WA &&
4018 (opa != pa || (opte2 & PTE2_NX)))
4019 cache_icache_sync_fresh(va, pa, PAGE_SIZE);
4022 if (flags & VM_PROT_WRITE)
4024 if (opte2 & PTE2_V) {
4025 /* Change mapping with break-before-make approach. */
4026 opte2 = pte2_load_clear(pte2p);
4027 pmap_tlb_flush(pmap, va);
4028 pte2_store(pte2p, npte2);
4029 if (opte2 & PTE2_A) {
4030 if (pte2_is_managed(opte2))
4031 vm_page_aflag_set(om, PGA_REFERENCED);
4033 if (pte2_is_dirty(opte2)) {
4034 if (pte2_is_managed(opte2))
4037 if (pte2_is_managed(opte2) &&
4038 TAILQ_EMPTY(&om->md.pv_list) &&
4039 ((om->flags & PG_FICTITIOUS) != 0 ||
4040 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
4041 vm_page_aflag_clear(om, PGA_WRITEABLE);
4043 pte2_store(pte2p, npte2);
4048 * QQQ: In time when both access and not mofified bits are
4049 * emulated by software, this should not happen. Some
4050 * analysis is need, if this really happen. Missing
4051 * tlb flush somewhere could be the reason.
4053 panic("%s: pmap %p va %#x opte2 %x npte2 %x !!", __func__, pmap,
4058 * If both the L2 page table page and the reservation are fully
4059 * populated, then attempt promotion.
4061 if ((mpte2 == NULL || pt2_is_full(mpte2, va)) &&
4062 sp_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
4063 vm_reserv_level_iffullpop(m) == 0)
4064 pmap_promote_pte1(pmap, pte1p, va);
4066 rw_wunlock(&pvh_global_lock);
4068 return (KERN_SUCCESS);
4072 * Do the things to unmap a page in a process.
4075 pmap_remove_pte2(pmap_t pmap, pt2_entry_t *pte2p, vm_offset_t va,
4076 struct spglist *free)
4081 rw_assert(&pvh_global_lock, RA_WLOCKED);
4082 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4084 /* Clear and invalidate the mapping. */
4085 opte2 = pte2_load_clear(pte2p);
4086 pmap_tlb_flush(pmap, va);
4088 KASSERT(pte2_is_valid(opte2), ("%s: pmap %p va %#x not link pte2 %#x",
4089 __func__, pmap, va, opte2));
4092 pmap->pm_stats.wired_count -= 1;
4093 pmap->pm_stats.resident_count -= 1;
4094 if (pte2_is_managed(opte2)) {
4095 m = PHYS_TO_VM_PAGE(pte2_pa(opte2));
4096 if (pte2_is_dirty(opte2))
4099 vm_page_aflag_set(m, PGA_REFERENCED);
4100 pmap_remove_entry(pmap, m, va);
4102 return (pmap_unuse_pt2(pmap, va, free));
4106 * Remove a single page from a process address space.
4109 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
4113 rw_assert(&pvh_global_lock, RA_WLOCKED);
4114 KASSERT(curthread->td_pinned > 0,
4115 ("%s: curthread not pinned", __func__));
4116 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4117 if ((pte2p = pmap_pte2_quick(pmap, va)) == NULL ||
4118 !pte2_is_valid(pte2_load(pte2p)))
4120 pmap_remove_pte2(pmap, pte2p, va, free);
4124 * Remove the given range of addresses from the specified map.
4126 * It is assumed that the start and end are properly
4127 * rounded to the page size.
4130 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4133 pt1_entry_t *pte1p, pte1;
4134 pt2_entry_t *pte2p, pte2;
4135 struct spglist free;
4138 * Perform an unsynchronized read. This is, however, safe.
4140 if (pmap->pm_stats.resident_count == 0)
4145 rw_wlock(&pvh_global_lock);
4150 * Special handling of removing one page. A very common
4151 * operation and easy to short circuit some code.
4153 if (sva + PAGE_SIZE == eva) {
4154 pte1 = pte1_load(pmap_pte1(pmap, sva));
4155 if (pte1_is_link(pte1)) {
4156 pmap_remove_page(pmap, sva, &free);
4161 for (; sva < eva; sva = nextva) {
4163 * Calculate address for next L2 page table.
4165 nextva = pte1_trunc(sva + PTE1_SIZE);
4168 if (pmap->pm_stats.resident_count == 0)
4171 pte1p = pmap_pte1(pmap, sva);
4172 pte1 = pte1_load(pte1p);
4175 * Weed out invalid mappings. Note: we assume that the L1 page
4176 * table is always allocated, and in kernel virtual.
4181 if (pte1_is_section(pte1)) {
4183 * Are we removing the entire large page? If not,
4184 * demote the mapping and fall through.
4186 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
4187 pmap_remove_pte1(pmap, pte1p, sva, &free);
4189 } else if (!pmap_demote_pte1(pmap, pte1p, sva)) {
4190 /* The large page mapping was destroyed. */
4195 /* Update pte1 after demotion. */
4196 pte1 = pte1_load(pte1p);
4201 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
4202 " is not link", __func__, pmap, sva, pte1, pte1p));
4205 * Limit our scan to either the end of the va represented
4206 * by the current L2 page table page, or to the end of the
4207 * range being removed.
4212 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva;
4213 pte2p++, sva += PAGE_SIZE) {
4214 pte2 = pte2_load(pte2p);
4215 if (!pte2_is_valid(pte2))
4217 if (pmap_remove_pte2(pmap, pte2p, sva, &free))
4223 rw_wunlock(&pvh_global_lock);
4225 pmap_free_zero_pages(&free);
4229 * Routine: pmap_remove_all
4231 * Removes this physical page from
4232 * all physical maps in which it resides.
4233 * Reflects back modify bits to the pager.
4236 * Original versions of this routine were very
4237 * inefficient because they iteratively called
4238 * pmap_remove (slow...)
4242 pmap_remove_all(vm_page_t m)
4244 struct md_page *pvh;
4247 pt2_entry_t *pte2p, opte2;
4250 struct spglist free;
4252 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4253 ("%s: page %p is not managed", __func__, m));
4255 rw_wlock(&pvh_global_lock);
4257 if ((m->flags & PG_FICTITIOUS) != 0)
4258 goto small_mappings;
4259 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4260 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
4264 pte1p = pmap_pte1(pmap, va);
4265 (void)pmap_demote_pte1(pmap, pte1p, va);
4269 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4272 pmap->pm_stats.resident_count--;
4273 pte1p = pmap_pte1(pmap, pv->pv_va);
4274 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found "
4275 "a 1mpage in page %p's pv list", __func__, m));
4276 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
4277 opte2 = pte2_load_clear(pte2p);
4278 pmap_tlb_flush(pmap, pv->pv_va);
4279 KASSERT(pte2_is_valid(opte2), ("%s: pmap %p va %x zero pte2",
4280 __func__, pmap, pv->pv_va));
4281 if (pte2_is_wired(opte2))
4282 pmap->pm_stats.wired_count--;
4284 vm_page_aflag_set(m, PGA_REFERENCED);
4287 * Update the vm_page_t clean and reference bits.
4289 if (pte2_is_dirty(opte2))
4291 pmap_unuse_pt2(pmap, pv->pv_va, &free);
4292 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4293 free_pv_entry(pmap, pv);
4296 vm_page_aflag_clear(m, PGA_WRITEABLE);
4298 rw_wunlock(&pvh_global_lock);
4299 pmap_free_zero_pages(&free);
4303 * Just subroutine for pmap_remove_pages() to reasonably satisfy
4304 * good coding style, a.k.a. 80 character line width limit hell.
4306 static __inline void
4307 pmap_remove_pte1_quick(pmap_t pmap, pt1_entry_t pte1, pv_entry_t pv,
4308 struct spglist *free)
4311 vm_page_t m, mt, mpt2pg;
4312 struct md_page *pvh;
4315 m = PHYS_TO_VM_PAGE(pa);
4317 KASSERT(m->phys_addr == pa, ("%s: vm_page_t %p addr mismatch %#x %#x",
4318 __func__, m, m->phys_addr, pa));
4319 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4320 m < &vm_page_array[vm_page_array_size],
4321 ("%s: bad pte1 %#x", __func__, pte1));
4323 if (pte1_is_dirty(pte1)) {
4324 for (mt = m; mt < &m[PTE1_SIZE / PAGE_SIZE]; mt++)
4328 pmap->pm_stats.resident_count -= PTE1_SIZE / PAGE_SIZE;
4329 pvh = pa_to_pvh(pa);
4330 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4331 if (TAILQ_EMPTY(&pvh->pv_list)) {
4332 for (mt = m; mt < &m[PTE1_SIZE / PAGE_SIZE]; mt++)
4333 if (TAILQ_EMPTY(&mt->md.pv_list))
4334 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4336 mpt2pg = pmap_pt2_page(pmap, pv->pv_va);
4338 pmap_unwire_pt2_all(pmap, pv->pv_va, mpt2pg, free);
4342 * Just subroutine for pmap_remove_pages() to reasonably satisfy
4343 * good coding style, a.k.a. 80 character line width limit hell.
4345 static __inline void
4346 pmap_remove_pte2_quick(pmap_t pmap, pt2_entry_t pte2, pv_entry_t pv,
4347 struct spglist *free)
4351 struct md_page *pvh;
4354 m = PHYS_TO_VM_PAGE(pa);
4356 KASSERT(m->phys_addr == pa, ("%s: vm_page_t %p addr mismatch %#x %#x",
4357 __func__, m, m->phys_addr, pa));
4358 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4359 m < &vm_page_array[vm_page_array_size],
4360 ("%s: bad pte2 %#x", __func__, pte2));
4362 if (pte2_is_dirty(pte2))
4365 pmap->pm_stats.resident_count--;
4366 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4367 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
4368 pvh = pa_to_pvh(pa);
4369 if (TAILQ_EMPTY(&pvh->pv_list))
4370 vm_page_aflag_clear(m, PGA_WRITEABLE);
4372 pmap_unuse_pt2(pmap, pv->pv_va, free);
4376 * Remove all pages from specified address space this aids process
4377 * exit speeds. Also, this code is special cased for current process
4378 * only, but can have the more generic (and slightly slower) mode enabled.
4379 * This is much faster than pmap_remove in the case of running down
4380 * an entire address space.
4383 pmap_remove_pages(pmap_t pmap)
4385 pt1_entry_t *pte1p, pte1;
4386 pt2_entry_t *pte2p, pte2;
4388 struct pv_chunk *pc, *npc;
4389 struct spglist free;
4392 uint32_t inuse, bitmask;
4396 * Assert that the given pmap is only active on the current
4397 * CPU. Unfortunately, we cannot block another CPU from
4398 * activating the pmap while this function is executing.
4400 KASSERT(pmap == vmspace_pmap(curthread->td_proc->p_vmspace),
4401 ("%s: non-current pmap %p", __func__, pmap));
4402 #if defined(SMP) && defined(INVARIANTS)
4404 cpuset_t other_cpus;
4407 other_cpus = pmap->pm_active;
4408 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
4410 KASSERT(CPU_EMPTY(&other_cpus),
4411 ("%s: pmap %p active on other cpus", __func__, pmap));
4415 rw_wlock(&pvh_global_lock);
4418 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4419 KASSERT(pc->pc_pmap == pmap, ("%s: wrong pmap %p %p",
4420 __func__, pmap, pc->pc_pmap));
4422 for (field = 0; field < _NPCM; field++) {
4423 inuse = (~(pc->pc_map[field])) & pc_freemask[field];
4424 while (inuse != 0) {
4425 bit = ffs(inuse) - 1;
4426 bitmask = 1UL << bit;
4427 idx = field * 32 + bit;
4428 pv = &pc->pc_pventry[idx];
4432 * Note that we cannot remove wired pages
4433 * from a process' mapping at this time
4435 pte1p = pmap_pte1(pmap, pv->pv_va);
4436 pte1 = pte1_load(pte1p);
4437 if (pte1_is_section(pte1)) {
4438 if (pte1_is_wired(pte1)) {
4443 pmap_remove_pte1_quick(pmap, pte1, pv,
4446 else if (pte1_is_link(pte1)) {
4447 pte2p = pt2map_entry(pv->pv_va);
4448 pte2 = pte2_load(pte2p);
4450 if (!pte2_is_valid(pte2)) {
4451 printf("%s: pmap %p va %#x "
4452 "pte2 %#x\n", __func__,
4453 pmap, pv->pv_va, pte2);
4457 if (pte2_is_wired(pte2)) {
4462 pmap_remove_pte2_quick(pmap, pte2, pv,
4465 printf("%s: pmap %p va %#x pte1 %#x\n",
4466 __func__, pmap, pv->pv_va, pte1);
4471 PV_STAT(pv_entry_frees++);
4472 PV_STAT(pv_entry_spare++);
4474 pc->pc_map[field] |= bitmask;
4478 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4482 tlb_flush_all_ng_local();
4484 rw_wunlock(&pvh_global_lock);
4486 pmap_free_zero_pages(&free);
4490 * This code makes some *MAJOR* assumptions:
4491 * 1. Current pmap & pmap exists.
4494 * 4. No L2 page table pages.
4495 * but is *MUCH* faster than pmap_enter...
4498 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4499 vm_prot_t prot, vm_page_t mpt2pg)
4501 pt2_entry_t *pte2p, pte2;
4503 struct spglist free;
4506 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
4507 (m->oflags & VPO_UNMANAGED) != 0,
4508 ("%s: managed mapping within the clean submap", __func__));
4509 rw_assert(&pvh_global_lock, RA_WLOCKED);
4510 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4513 * In the case that a L2 page table page is not
4514 * resident, we are creating it here.
4516 if (va < VM_MAXUSER_ADDRESS) {
4518 pt1_entry_t pte1, *pte1p;
4522 * Get L1 page table things.
4524 pte1_idx = pte1_index(va);
4525 pte1p = pmap_pte1(pmap, va);
4526 pte1 = pte1_load(pte1p);
4528 if (mpt2pg && (mpt2pg->pindex == (pte1_idx & ~PT2PG_MASK))) {
4530 * Each of NPT2_IN_PG L2 page tables on the page can
4531 * come here. Make sure that associated L1 page table
4532 * link is established.
4534 * QQQ: It comes that we don't establish all links to
4535 * L2 page tables for newly allocated L2 page
4538 KASSERT(!pte1_is_section(pte1),
4539 ("%s: pte1 %#x is section", __func__, pte1));
4540 if (!pte1_is_link(pte1)) {
4541 pt2_pa = page_pt2pa(VM_PAGE_TO_PHYS(mpt2pg),
4543 pte1_store(pte1p, PTE1_LINK(pt2_pa));
4545 pt2_wirecount_inc(mpt2pg, pte1_idx);
4548 * If the L2 page table page is mapped, we just
4549 * increment the hold count, and activate it.
4551 if (pte1_is_section(pte1)) {
4553 } else if (pte1_is_link(pte1)) {
4554 mpt2pg = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
4555 pt2_wirecount_inc(mpt2pg, pte1_idx);
4557 mpt2pg = _pmap_allocpte2(pmap, va,
4558 PMAP_ENTER_NOSLEEP);
4568 * This call to pt2map_entry() makes the assumption that we are
4569 * entering the page into the current pmap. In order to support
4570 * quick entry into any pmap, one would likely use pmap_pte2_quick().
4571 * But that isn't as quick as pt2map_entry().
4573 pte2p = pt2map_entry(va);
4574 pte2 = pte2_load(pte2p);
4575 if (pte2_is_valid(pte2)) {
4576 if (mpt2pg != NULL) {
4578 * Remove extra pte2 reference
4580 pt2_wirecount_dec(mpt2pg, pte1_index(va));
4587 * Enter on the PV list if part of our managed memory.
4589 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4590 !pmap_try_insert_pv_entry(pmap, va, m)) {
4591 if (mpt2pg != NULL) {
4593 if (pmap_unwire_pt2(pmap, va, mpt2pg, &free)) {
4594 pmap_tlb_flush(pmap, va);
4595 pmap_free_zero_pages(&free);
4604 * Increment counters
4606 pmap->pm_stats.resident_count++;
4609 * Now validate mapping with RO protection
4611 pa = VM_PAGE_TO_PHYS(m);
4612 l2prot = PTE2_RO | PTE2_NM;
4613 if (va < VM_MAXUSER_ADDRESS)
4614 l2prot |= PTE2_U | PTE2_NG;
4615 if ((prot & VM_PROT_EXECUTE) == 0)
4617 else if (m->md.pat_mode == VM_MEMATTR_WB_WA && pmap != kernel_pmap) {
4619 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4620 * is set. QQQ: For more info, see comments in pmap_enter().
4622 cache_icache_sync_fresh(va, pa, PAGE_SIZE);
4624 pte2_store(pte2p, PTE2(pa, l2prot, vm_page_pte2_attr(m)));
4630 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4633 rw_wlock(&pvh_global_lock);
4635 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
4636 rw_wunlock(&pvh_global_lock);
4641 * Tries to create 1MB page mapping. Returns TRUE if successful and
4642 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
4643 * blocking, (2) a mapping already exists at the specified virtual address, or
4644 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
4647 pmap_enter_pte1(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4653 rw_assert(&pvh_global_lock, RA_WLOCKED);
4654 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4655 pte1p = pmap_pte1(pmap, va);
4656 if (pte1_is_valid(pte1_load(pte1p))) {
4657 CTR3(KTR_PMAP, "%s: failure for va %#lx in pmap %p", __func__,
4661 if ((m->oflags & VPO_UNMANAGED) == 0) {
4663 * Abort this mapping if its PV entry could not be created.
4665 if (!pmap_pv_insert_pte1(pmap, va, VM_PAGE_TO_PHYS(m))) {
4666 CTR3(KTR_PMAP, "%s: failure for va %#lx in pmap %p",
4667 __func__, va, pmap);
4672 * Increment counters.
4674 pmap->pm_stats.resident_count += PTE1_SIZE / PAGE_SIZE;
4679 * QQQ: Why VM_PROT_WRITE is not evaluated and the mapping is
4682 pa = VM_PAGE_TO_PHYS(m);
4683 l1prot = PTE1_RO | PTE1_NM;
4684 if (va < VM_MAXUSER_ADDRESS)
4685 l1prot |= PTE1_U | PTE1_NG;
4686 if ((prot & VM_PROT_EXECUTE) == 0)
4688 else if (m->md.pat_mode == VM_MEMATTR_WB_WA && pmap != kernel_pmap) {
4690 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4691 * is set. QQQ: For more info, see comments in pmap_enter().
4693 cache_icache_sync_fresh(va, pa, PTE1_SIZE);
4695 pte1_store(pte1p, PTE1(pa, l1prot, ATTR_TO_L1(vm_page_pte2_attr(m))));
4697 pmap_pte1_mappings++;
4698 CTR3(KTR_PMAP, "%s: success for va %#lx in pmap %p", __func__, va,
4704 * Maps a sequence of resident pages belonging to the same object.
4705 * The sequence begins with the given page m_start. This page is
4706 * mapped at the given virtual address start. Each subsequent page is
4707 * mapped at a virtual address that is offset from start by the same
4708 * amount as the page is offset from m_start within the object. The
4709 * last page in the sequence is the page with the largest offset from
4710 * m_start that can be mapped at a virtual address less than the given
4711 * virtual address end. Not every virtual page between start and end
4712 * is mapped; only those for which a resident page exists with the
4713 * corresponding offset from m_start are mapped.
4716 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4717 vm_page_t m_start, vm_prot_t prot)
4720 vm_page_t m, mpt2pg;
4721 vm_pindex_t diff, psize;
4723 PDEBUG(6, printf("%s: pmap %p start %#x end %#x m %p prot %#x\n",
4724 __func__, pmap, start, end, m_start, prot));
4726 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4727 psize = atop(end - start);
4730 rw_wlock(&pvh_global_lock);
4732 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4733 va = start + ptoa(diff);
4734 if ((va & PTE1_OFFSET) == 0 && va + PTE1_SIZE <= end &&
4735 m->psind == 1 && sp_enabled &&
4736 pmap_enter_pte1(pmap, va, m, prot))
4737 m = &m[PTE1_SIZE / PAGE_SIZE - 1];
4739 mpt2pg = pmap_enter_quick_locked(pmap, va, m, prot,
4741 m = TAILQ_NEXT(m, listq);
4743 rw_wunlock(&pvh_global_lock);
4748 * This code maps large physical mmap regions into the
4749 * processor address space. Note that some shortcuts
4750 * are taken, but the code works.
4753 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4754 vm_pindex_t pindex, vm_size_t size)
4757 vm_paddr_t pa, pte2_pa;
4759 vm_memattr_t pat_mode;
4760 u_int l1attr, l1prot;
4762 VM_OBJECT_ASSERT_WLOCKED(object);
4763 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4764 ("%s: non-device object", __func__));
4765 if ((addr & PTE1_OFFSET) == 0 && (size & PTE1_OFFSET) == 0) {
4766 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4768 p = vm_page_lookup(object, pindex);
4769 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4770 ("%s: invalid page %p", __func__, p));
4771 pat_mode = p->md.pat_mode;
4774 * Abort the mapping if the first page is not physically
4775 * aligned to a 1MB page boundary.
4777 pte2_pa = VM_PAGE_TO_PHYS(p);
4778 if (pte2_pa & PTE1_OFFSET)
4782 * Skip the first page. Abort the mapping if the rest of
4783 * the pages are not physically contiguous or have differing
4784 * memory attributes.
4786 p = TAILQ_NEXT(p, listq);
4787 for (pa = pte2_pa + PAGE_SIZE; pa < pte2_pa + size;
4789 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4790 ("%s: invalid page %p", __func__, p));
4791 if (pa != VM_PAGE_TO_PHYS(p) ||
4792 pat_mode != p->md.pat_mode)
4794 p = TAILQ_NEXT(p, listq);
4798 * Map using 1MB pages.
4800 * QQQ: Well, we are mapping a section, so same condition must
4801 * be hold like during promotion. It looks that only RW mapping
4802 * is done here, so readonly mapping must be done elsewhere.
4804 l1prot = PTE1_U | PTE1_NG | PTE1_RW | PTE1_M | PTE1_A;
4805 l1attr = ATTR_TO_L1(vm_memattr_to_pte2(pat_mode));
4807 for (pa = pte2_pa; pa < pte2_pa + size; pa += PTE1_SIZE) {
4808 pte1p = pmap_pte1(pmap, addr);
4809 if (!pte1_is_valid(pte1_load(pte1p))) {
4810 pte1_store(pte1p, PTE1(pa, l1prot, l1attr));
4811 pmap->pm_stats.resident_count += PTE1_SIZE /
4813 pmap_pte1_mappings++;
4815 /* Else continue on if the PTE1 is already valid. */
4823 * Do the things to protect a 1mpage in a process.
4826 pmap_protect_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t sva,
4829 pt1_entry_t npte1, opte1;
4830 vm_offset_t eva, va;
4833 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4834 KASSERT((sva & PTE1_OFFSET) == 0,
4835 ("%s: sva is not 1mpage aligned", __func__));
4837 opte1 = npte1 = pte1_load(pte1p);
4838 if (pte1_is_managed(opte1) && pte1_is_dirty(opte1)) {
4839 eva = sva + PTE1_SIZE;
4840 for (va = sva, m = PHYS_TO_VM_PAGE(pte1_pa(opte1));
4841 va < eva; va += PAGE_SIZE, m++)
4844 if ((prot & VM_PROT_WRITE) == 0)
4845 npte1 |= PTE1_RO | PTE1_NM;
4846 if ((prot & VM_PROT_EXECUTE) == 0)
4850 * QQQ: Herein, execute permission is never set.
4851 * It only can be cleared. So, no icache
4852 * syncing is needed.
4855 if (npte1 != opte1) {
4856 pte1_store(pte1p, npte1);
4857 pmap_tlb_flush(pmap, sva);
4862 * Set the physical protection on the
4863 * specified range of this map as requested.
4866 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
4868 boolean_t pv_lists_locked;
4870 pt1_entry_t *pte1p, pte1;
4871 pt2_entry_t *pte2p, opte2, npte2;
4873 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
4874 if (prot == VM_PROT_NONE) {
4875 pmap_remove(pmap, sva, eva);
4879 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
4880 (VM_PROT_WRITE | VM_PROT_EXECUTE))
4883 if (pmap_is_current(pmap))
4884 pv_lists_locked = FALSE;
4886 pv_lists_locked = TRUE;
4888 rw_wlock(&pvh_global_lock);
4893 for (; sva < eva; sva = nextva) {
4895 * Calculate address for next L2 page table.
4897 nextva = pte1_trunc(sva + PTE1_SIZE);
4901 pte1p = pmap_pte1(pmap, sva);
4902 pte1 = pte1_load(pte1p);
4905 * Weed out invalid mappings. Note: we assume that L1 page
4906 * page table is always allocated, and in kernel virtual.
4911 if (pte1_is_section(pte1)) {
4913 * Are we protecting the entire large page? If not,
4914 * demote the mapping and fall through.
4916 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
4917 pmap_protect_pte1(pmap, pte1p, sva, prot);
4920 if (!pv_lists_locked) {
4921 pv_lists_locked = TRUE;
4922 if (!rw_try_wlock(&pvh_global_lock)) {
4928 if (!pmap_demote_pte1(pmap, pte1p, sva)) {
4930 * The large page mapping
4937 /* Update pte1 after demotion */
4938 pte1 = pte1_load(pte1p);
4944 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
4945 " is not link", __func__, pmap, sva, pte1, pte1p));
4948 * Limit our scan to either the end of the va represented
4949 * by the current L2 page table page, or to the end of the
4950 * range being protected.
4955 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva; pte2p++,
4959 opte2 = npte2 = pte2_load(pte2p);
4960 if (!pte2_is_valid(opte2))
4963 if ((prot & VM_PROT_WRITE) == 0) {
4964 if (pte2_is_managed(opte2) &&
4965 pte2_is_dirty(opte2)) {
4966 m = PHYS_TO_VM_PAGE(pte2_pa(opte2));
4969 npte2 |= PTE2_RO | PTE2_NM;
4972 if ((prot & VM_PROT_EXECUTE) == 0)
4976 * QQQ: Herein, execute permission is never set.
4977 * It only can be cleared. So, no icache
4978 * syncing is needed.
4981 if (npte2 != opte2) {
4982 pte2_store(pte2p, npte2);
4983 pmap_tlb_flush(pmap, sva);
4987 if (pv_lists_locked) {
4989 rw_wunlock(&pvh_global_lock);
4995 * pmap_pvh_wired_mappings:
4997 * Return the updated number "count" of managed mappings that are wired.
5000 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
5007 rw_assert(&pvh_global_lock, RA_WLOCKED);
5009 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5012 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5013 if (pte1_is_section(pte1)) {
5014 if (pte1_is_wired(pte1))
5017 KASSERT(pte1_is_link(pte1),
5018 ("%s: pte1 %#x is not link", __func__, pte1));
5019 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5020 if (pte2_is_wired(pte2))
5030 * pmap_page_wired_mappings:
5032 * Return the number of managed mappings to the given physical page
5036 pmap_page_wired_mappings(vm_page_t m)
5041 if ((m->oflags & VPO_UNMANAGED) != 0)
5043 rw_wlock(&pvh_global_lock);
5044 count = pmap_pvh_wired_mappings(&m->md, count);
5045 if ((m->flags & PG_FICTITIOUS) == 0) {
5046 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
5049 rw_wunlock(&pvh_global_lock);
5054 * Returns TRUE if any of the given mappings were used to modify
5055 * physical memory. Otherwise, returns FALSE. Both page and 1mpage
5056 * mappings are supported.
5059 pmap_is_modified_pvh(struct md_page *pvh)
5067 rw_assert(&pvh_global_lock, RA_WLOCKED);
5070 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5073 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5074 if (pte1_is_section(pte1)) {
5075 rv = pte1_is_dirty(pte1);
5077 KASSERT(pte1_is_link(pte1),
5078 ("%s: pte1 %#x is not link", __func__, pte1));
5079 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5080 rv = pte2_is_dirty(pte2);
5093 * Return whether or not the specified physical page was modified
5094 * in any physical maps.
5097 pmap_is_modified(vm_page_t m)
5101 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5102 ("%s: page %p is not managed", __func__, m));
5105 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5106 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
5107 * is clear, no PTE2s can have PG_M set.
5109 VM_OBJECT_ASSERT_WLOCKED(m->object);
5110 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5112 rw_wlock(&pvh_global_lock);
5113 rv = pmap_is_modified_pvh(&m->md) ||
5114 ((m->flags & PG_FICTITIOUS) == 0 &&
5115 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
5116 rw_wunlock(&pvh_global_lock);
5121 * pmap_is_prefaultable:
5123 * Return whether or not the specified virtual address is eligible
5127 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
5135 pte1 = pte1_load(pmap_pte1(pmap, addr));
5136 if (pte1_is_link(pte1)) {
5137 pte2 = pte2_load(pt2map_entry(addr));
5138 rv = !pte2_is_valid(pte2) ;
5145 * Returns TRUE if any of the given mappings were referenced and FALSE
5146 * otherwise. Both page and 1mpage mappings are supported.
5149 pmap_is_referenced_pvh(struct md_page *pvh)
5158 rw_assert(&pvh_global_lock, RA_WLOCKED);
5161 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5164 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5165 if (pte1_is_section(pte1)) {
5166 rv = (pte1 & (PTE1_A | PTE1_V)) == (PTE1_A | PTE1_V);
5168 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5169 rv = (pte2 & (PTE2_A | PTE2_V)) == (PTE2_A | PTE2_V);
5180 * pmap_is_referenced:
5182 * Return whether or not the specified physical page was referenced
5183 * in any physical maps.
5186 pmap_is_referenced(vm_page_t m)
5190 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5191 ("%s: page %p is not managed", __func__, m));
5192 rw_wlock(&pvh_global_lock);
5193 rv = pmap_is_referenced_pvh(&m->md) ||
5194 ((m->flags & PG_FICTITIOUS) == 0 &&
5195 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
5196 rw_wunlock(&pvh_global_lock);
5201 * pmap_ts_referenced:
5203 * Return a count of reference bits for a page, clearing those bits.
5204 * It is not necessary for every reference bit to be cleared, but it
5205 * is necessary that 0 only be returned when there are truly no
5206 * reference bits set.
5208 * As an optimization, update the page's dirty field if a modified bit is
5209 * found while counting reference bits. This opportunistic update can be
5210 * performed at low cost and can eliminate the need for some future calls
5211 * to pmap_is_modified(). However, since this function stops after
5212 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5213 * dirty pages. Those dirty pages will only be detected by a future call
5214 * to pmap_is_modified().
5217 pmap_ts_referenced(vm_page_t m)
5219 struct md_page *pvh;
5222 pt1_entry_t *pte1p, opte1;
5223 pt2_entry_t *pte2p, opte2;
5227 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5228 ("%s: page %p is not managed", __func__, m));
5229 pa = VM_PAGE_TO_PHYS(m);
5230 pvh = pa_to_pvh(pa);
5231 rw_wlock(&pvh_global_lock);
5233 if ((m->flags & PG_FICTITIOUS) != 0 ||
5234 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5235 goto small_mappings;
5240 pte1p = pmap_pte1(pmap, pv->pv_va);
5241 opte1 = pte1_load(pte1p);
5242 if (pte1_is_dirty(opte1)) {
5244 * Although "opte1" is mapping a 1MB page, because
5245 * this function is called at a 4KB page granularity,
5246 * we only update the 4KB page under test.
5250 if ((opte1 & PTE1_A) != 0) {
5252 * Since this reference bit is shared by 256 4KB pages,
5253 * it should not be cleared every time it is tested.
5254 * Apply a simple "hash" function on the physical page
5255 * number, the virtual section number, and the pmap
5256 * address to select one 4KB page out of the 256
5257 * on which testing the reference bit will result
5258 * in clearing that bit. This function is designed
5259 * to avoid the selection of the same 4KB page
5260 * for every 1MB page mapping.
5262 * On demotion, a mapping that hasn't been referenced
5263 * is simply destroyed. To avoid the possibility of a
5264 * subsequent page fault on a demoted wired mapping,
5265 * always leave its reference bit set. Moreover,
5266 * since the section is wired, the current state of
5267 * its reference bit won't affect page replacement.
5269 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PTE1_SHIFT) ^
5270 (uintptr_t)pmap) & (NPTE2_IN_PG - 1)) == 0 &&
5271 !pte1_is_wired(opte1)) {
5272 pte1_clear_bit(pte1p, PTE1_A);
5273 pmap_tlb_flush(pmap, pv->pv_va);
5278 /* Rotate the PV list if it has more than one entry. */
5279 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5280 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5281 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5283 if (rtval >= PMAP_TS_REFERENCED_MAX)
5285 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5287 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5293 pte1p = pmap_pte1(pmap, pv->pv_va);
5294 KASSERT(pte1_is_link(pte1_load(pte1p)),
5295 ("%s: not found a link in page %p's pv list", __func__, m));
5297 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5298 opte2 = pte2_load(pte2p);
5299 if (pte2_is_dirty(opte2))
5301 if ((opte2 & PTE2_A) != 0) {
5302 pte2_clear_bit(pte2p, PTE2_A);
5303 pmap_tlb_flush(pmap, pv->pv_va);
5307 /* Rotate the PV list if it has more than one entry. */
5308 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5309 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5310 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5312 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
5313 PMAP_TS_REFERENCED_MAX);
5316 rw_wunlock(&pvh_global_lock);
5321 * Clear the wired attribute from the mappings for the specified range of
5322 * addresses in the given pmap. Every valid mapping within that range
5323 * must have the wired attribute set. In contrast, invalid mappings
5324 * cannot have the wired attribute set, so they are ignored.
5326 * The wired attribute of the page table entry is not a hardware feature,
5327 * so there is no need to invalidate any TLB entries.
5330 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5333 pt1_entry_t *pte1p, pte1;
5334 pt2_entry_t *pte2p, pte2;
5335 boolean_t pv_lists_locked;
5337 if (pmap_is_current(pmap))
5338 pv_lists_locked = FALSE;
5340 pv_lists_locked = TRUE;
5342 rw_wlock(&pvh_global_lock);
5346 for (; sva < eva; sva = nextva) {
5347 nextva = pte1_trunc(sva + PTE1_SIZE);
5351 pte1p = pmap_pte1(pmap, sva);
5352 pte1 = pte1_load(pte1p);
5355 * Weed out invalid mappings. Note: we assume that L1 page
5356 * page table is always allocated, and in kernel virtual.
5361 if (pte1_is_section(pte1)) {
5362 if (!pte1_is_wired(pte1))
5363 panic("%s: pte1 %#x not wired", __func__, pte1);
5366 * Are we unwiring the entire large page? If not,
5367 * demote the mapping and fall through.
5369 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
5370 pte1_clear_bit(pte1p, PTE1_W);
5371 pmap->pm_stats.wired_count -= PTE1_SIZE /
5375 if (!pv_lists_locked) {
5376 pv_lists_locked = TRUE;
5377 if (!rw_try_wlock(&pvh_global_lock)) {
5384 if (!pmap_demote_pte1(pmap, pte1p, sva))
5385 panic("%s: demotion failed", __func__);
5388 /* Update pte1 after demotion */
5389 pte1 = pte1_load(pte1p);
5395 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
5396 " is not link", __func__, pmap, sva, pte1, pte1p));
5399 * Limit our scan to either the end of the va represented
5400 * by the current L2 page table page, or to the end of the
5401 * range being protected.
5406 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva; pte2p++,
5408 pte2 = pte2_load(pte2p);
5409 if (!pte2_is_valid(pte2))
5411 if (!pte2_is_wired(pte2))
5412 panic("%s: pte2 %#x is missing PTE2_W",
5416 * PTE2_W must be cleared atomically. Although the pmap
5417 * lock synchronizes access to PTE2_W, another processor
5418 * could be changing PTE2_NM and/or PTE2_A concurrently.
5420 pte2_clear_bit(pte2p, PTE2_W);
5421 pmap->pm_stats.wired_count--;
5424 if (pv_lists_locked) {
5426 rw_wunlock(&pvh_global_lock);
5432 * Clear the write and modified bits in each of the given page's mappings.
5435 pmap_remove_write(vm_page_t m)
5437 struct md_page *pvh;
5438 pv_entry_t next_pv, pv;
5441 pt2_entry_t *pte2p, opte2;
5444 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5445 ("%s: page %p is not managed", __func__, m));
5448 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5449 * set by another thread while the object is locked. Thus,
5450 * if PGA_WRITEABLE is clear, no page table entries need updating.
5452 VM_OBJECT_ASSERT_WLOCKED(m->object);
5453 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5455 rw_wlock(&pvh_global_lock);
5457 if ((m->flags & PG_FICTITIOUS) != 0)
5458 goto small_mappings;
5459 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5460 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5464 pte1p = pmap_pte1(pmap, va);
5465 if (!(pte1_load(pte1p) & PTE1_RO))
5466 (void)pmap_demote_pte1(pmap, pte1p, va);
5470 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5473 pte1p = pmap_pte1(pmap, pv->pv_va);
5474 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found"
5475 " a section in page %p's pv list", __func__, m));
5476 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5477 opte2 = pte2_load(pte2p);
5478 if (!(opte2 & PTE2_RO)) {
5479 pte2_store(pte2p, opte2 | PTE2_RO | PTE2_NM);
5480 if (pte2_is_dirty(opte2))
5482 pmap_tlb_flush(pmap, pv->pv_va);
5486 vm_page_aflag_clear(m, PGA_WRITEABLE);
5488 rw_wunlock(&pvh_global_lock);
5492 * Apply the given advice to the specified range of addresses within the
5493 * given pmap. Depending on the advice, clear the referenced and/or
5494 * modified flags in each mapping and set the mapped page's dirty field.
5497 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5499 pt1_entry_t *pte1p, opte1;
5500 pt2_entry_t *pte2p, pte2;
5503 boolean_t pv_lists_locked;
5505 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5507 if (pmap_is_current(pmap))
5508 pv_lists_locked = FALSE;
5510 pv_lists_locked = TRUE;
5512 rw_wlock(&pvh_global_lock);
5516 for (; sva < eva; sva = pdnxt) {
5517 pdnxt = pte1_trunc(sva + PTE1_SIZE);
5520 pte1p = pmap_pte1(pmap, sva);
5521 opte1 = pte1_load(pte1p);
5522 if (!pte1_is_valid(opte1)) /* XXX */
5524 else if (pte1_is_section(opte1)) {
5525 if (!pte1_is_managed(opte1))
5527 if (!pv_lists_locked) {
5528 pv_lists_locked = TRUE;
5529 if (!rw_try_wlock(&pvh_global_lock)) {
5535 if (!pmap_demote_pte1(pmap, pte1p, sva)) {
5537 * The large page mapping was destroyed.
5543 * Unless the page mappings are wired, remove the
5544 * mapping to a single page so that a subsequent
5545 * access may repromote. Since the underlying L2 page
5546 * table is fully populated, this removal never
5547 * frees a L2 page table page.
5549 if (!pte1_is_wired(opte1)) {
5550 pte2p = pmap_pte2_quick(pmap, sva);
5551 KASSERT(pte2_is_valid(pte2_load(pte2p)),
5552 ("%s: invalid PTE2", __func__));
5553 pmap_remove_pte2(pmap, pte2p, sva, NULL);
5558 for (pte2p = pmap_pte2_quick(pmap, sva); sva != pdnxt; pte2p++,
5560 pte2 = pte2_load(pte2p);
5561 if (!pte2_is_valid(pte2) || !pte2_is_managed(pte2))
5563 else if (pte2_is_dirty(pte2)) {
5564 if (advice == MADV_DONTNEED) {
5566 * Future calls to pmap_is_modified()
5567 * can be avoided by making the page
5570 m = PHYS_TO_VM_PAGE(pte2_pa(pte2));
5573 pte2_set_bit(pte2p, PTE2_NM);
5574 pte2_clear_bit(pte2p, PTE2_A);
5575 } else if ((pte2 & PTE2_A) != 0)
5576 pte2_clear_bit(pte2p, PTE2_A);
5579 pmap_tlb_flush(pmap, sva);
5582 if (pv_lists_locked) {
5584 rw_wunlock(&pvh_global_lock);
5590 * Clear the modify bits on the specified physical page.
5593 pmap_clear_modify(vm_page_t m)
5595 struct md_page *pvh;
5596 pv_entry_t next_pv, pv;
5598 pt1_entry_t *pte1p, opte1;
5599 pt2_entry_t *pte2p, opte2;
5602 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5603 ("%s: page %p is not managed", __func__, m));
5604 VM_OBJECT_ASSERT_WLOCKED(m->object);
5605 KASSERT(!vm_page_xbusied(m),
5606 ("%s: page %p is exclusive busy", __func__, m));
5609 * If the page is not PGA_WRITEABLE, then no PTE2s can have PTE2_NM
5610 * cleared. If the object containing the page is locked and the page
5611 * is not exclusive busied, then PGA_WRITEABLE cannot be concurrently
5614 if ((m->flags & PGA_WRITEABLE) == 0)
5616 rw_wlock(&pvh_global_lock);
5618 if ((m->flags & PG_FICTITIOUS) != 0)
5619 goto small_mappings;
5620 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5621 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5625 pte1p = pmap_pte1(pmap, va);
5626 opte1 = pte1_load(pte1p);
5627 if (!(opte1 & PTE1_RO)) {
5628 if (pmap_demote_pte1(pmap, pte1p, va) &&
5629 !pte1_is_wired(opte1)) {
5631 * Write protect the mapping to a
5632 * single page so that a subsequent
5633 * write access may repromote.
5635 va += VM_PAGE_TO_PHYS(m) - pte1_pa(opte1);
5636 pte2p = pmap_pte2_quick(pmap, va);
5637 opte2 = pte2_load(pte2p);
5638 if ((opte2 & PTE2_V)) {
5639 pte2_set_bit(pte2p, PTE2_NM | PTE2_RO);
5641 pmap_tlb_flush(pmap, va);
5648 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5651 pte1p = pmap_pte1(pmap, pv->pv_va);
5652 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found"
5653 " a section in page %p's pv list", __func__, m));
5654 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5655 if (pte2_is_dirty(pte2_load(pte2p))) {
5656 pte2_set_bit(pte2p, PTE2_NM);
5657 pmap_tlb_flush(pmap, pv->pv_va);
5662 rw_wunlock(&pvh_global_lock);
5667 * Sets the memory attribute for the specified page.
5670 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5672 pt2_entry_t *cmap2_pte2p;
5677 oma = m->md.pat_mode;
5678 m->md.pat_mode = ma;
5680 CTR5(KTR_PMAP, "%s: page %p - 0x%08X oma: %d, ma: %d", __func__, m,
5681 VM_PAGE_TO_PHYS(m), oma, ma);
5682 if ((m->flags & PG_FICTITIOUS) != 0)
5686 * If "m" is a normal page, flush it from the cache.
5688 * First, try to find an existing mapping of the page by sf
5689 * buffer. sf_buf_invalidate_cache() modifies mapping and
5690 * flushes the cache.
5692 if (sf_buf_invalidate_cache(m, oma))
5696 * If page is not mapped by sf buffer, map the page
5697 * transient and do invalidation.
5700 pa = VM_PAGE_TO_PHYS(m);
5703 cmap2_pte2p = pc->pc_cmap2_pte2p;
5704 mtx_lock(&pc->pc_cmap_lock);
5705 if (pte2_load(cmap2_pte2p) != 0)
5706 panic("%s: CMAP2 busy", __func__);
5707 pte2_store(cmap2_pte2p, PTE2_KERN_NG(pa, PTE2_AP_KRW,
5708 vm_memattr_to_pte2(ma)));
5709 dcache_wbinv_poc((vm_offset_t)pc->pc_cmap2_addr, pa, PAGE_SIZE);
5710 pte2_clear(cmap2_pte2p);
5711 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5713 mtx_unlock(&pc->pc_cmap_lock);
5718 * Miscellaneous support routines follow
5722 * Returns TRUE if the given page is mapped individually or as part of
5723 * a 1mpage. Otherwise, returns FALSE.
5726 pmap_page_is_mapped(vm_page_t m)
5730 if ((m->oflags & VPO_UNMANAGED) != 0)
5732 rw_wlock(&pvh_global_lock);
5733 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5734 ((m->flags & PG_FICTITIOUS) == 0 &&
5735 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
5736 rw_wunlock(&pvh_global_lock);
5741 * Returns true if the pmap's pv is one of the first
5742 * 16 pvs linked to from this page. This count may
5743 * be changed upwards or downwards in the future; it
5744 * is only necessary that true be returned for a small
5745 * subset of pmaps for proper page aging.
5748 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5750 struct md_page *pvh;
5755 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5756 ("%s: page %p is not managed", __func__, m));
5758 rw_wlock(&pvh_global_lock);
5759 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5760 if (PV_PMAP(pv) == pmap) {
5768 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5769 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5770 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5771 if (PV_PMAP(pv) == pmap) {
5780 rw_wunlock(&pvh_global_lock);
5785 * pmap_zero_page zeros the specified hardware page by mapping
5786 * the page into KVM and using bzero to clear its contents.
5789 pmap_zero_page(vm_page_t m)
5791 pt2_entry_t *cmap2_pte2p;
5796 cmap2_pte2p = pc->pc_cmap2_pte2p;
5797 mtx_lock(&pc->pc_cmap_lock);
5798 if (pte2_load(cmap2_pte2p) != 0)
5799 panic("%s: CMAP2 busy", __func__);
5800 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5801 vm_page_pte2_attr(m)));
5802 pagezero(pc->pc_cmap2_addr);
5803 pte2_clear(cmap2_pte2p);
5804 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5806 mtx_unlock(&pc->pc_cmap_lock);
5810 * pmap_zero_page_area zeros the specified hardware page by mapping
5811 * the page into KVM and using bzero to clear its contents.
5813 * off and size may not cover an area beyond a single hardware page.
5816 pmap_zero_page_area(vm_page_t m, int off, int size)
5818 pt2_entry_t *cmap2_pte2p;
5823 cmap2_pte2p = pc->pc_cmap2_pte2p;
5824 mtx_lock(&pc->pc_cmap_lock);
5825 if (pte2_load(cmap2_pte2p) != 0)
5826 panic("%s: CMAP2 busy", __func__);
5827 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5828 vm_page_pte2_attr(m)));
5829 if (off == 0 && size == PAGE_SIZE)
5830 pagezero(pc->pc_cmap2_addr);
5832 bzero(pc->pc_cmap2_addr + off, size);
5833 pte2_clear(cmap2_pte2p);
5834 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5836 mtx_unlock(&pc->pc_cmap_lock);
5840 * pmap_copy_page copies the specified (machine independent)
5841 * page by mapping the page into virtual memory and using
5842 * bcopy to copy the page, one machine dependent page at a
5846 pmap_copy_page(vm_page_t src, vm_page_t dst)
5848 pt2_entry_t *cmap1_pte2p, *cmap2_pte2p;
5853 cmap1_pte2p = pc->pc_cmap1_pte2p;
5854 cmap2_pte2p = pc->pc_cmap2_pte2p;
5855 mtx_lock(&pc->pc_cmap_lock);
5856 if (pte2_load(cmap1_pte2p) != 0)
5857 panic("%s: CMAP1 busy", __func__);
5858 if (pte2_load(cmap2_pte2p) != 0)
5859 panic("%s: CMAP2 busy", __func__);
5860 pte2_store(cmap1_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(src),
5861 PTE2_AP_KR | PTE2_NM, vm_page_pte2_attr(src)));
5862 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(dst),
5863 PTE2_AP_KRW, vm_page_pte2_attr(dst)));
5864 bcopy(pc->pc_cmap1_addr, pc->pc_cmap2_addr, PAGE_SIZE);
5865 pte2_clear(cmap1_pte2p);
5866 tlb_flush((vm_offset_t)pc->pc_cmap1_addr);
5867 pte2_clear(cmap2_pte2p);
5868 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5870 mtx_unlock(&pc->pc_cmap_lock);
5873 int unmapped_buf_allowed = 1;
5876 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5877 vm_offset_t b_offset, int xfersize)
5879 pt2_entry_t *cmap1_pte2p, *cmap2_pte2p;
5880 vm_page_t a_pg, b_pg;
5882 vm_offset_t a_pg_offset, b_pg_offset;
5888 cmap1_pte2p = pc->pc_cmap1_pte2p;
5889 cmap2_pte2p = pc->pc_cmap2_pte2p;
5890 mtx_lock(&pc->pc_cmap_lock);
5891 if (pte2_load(cmap1_pte2p) != 0)
5892 panic("pmap_copy_pages: CMAP1 busy");
5893 if (pte2_load(cmap2_pte2p) != 0)
5894 panic("pmap_copy_pages: CMAP2 busy");
5895 while (xfersize > 0) {
5896 a_pg = ma[a_offset >> PAGE_SHIFT];
5897 a_pg_offset = a_offset & PAGE_MASK;
5898 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5899 b_pg = mb[b_offset >> PAGE_SHIFT];
5900 b_pg_offset = b_offset & PAGE_MASK;
5901 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5902 pte2_store(cmap1_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(a_pg),
5903 PTE2_AP_KR | PTE2_NM, vm_page_pte2_attr(a_pg)));
5904 tlb_flush_local((vm_offset_t)pc->pc_cmap1_addr);
5905 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(b_pg),
5906 PTE2_AP_KRW, vm_page_pte2_attr(b_pg)));
5907 tlb_flush_local((vm_offset_t)pc->pc_cmap2_addr);
5908 a_cp = pc->pc_cmap1_addr + a_pg_offset;
5909 b_cp = pc->pc_cmap2_addr + b_pg_offset;
5910 bcopy(a_cp, b_cp, cnt);
5915 pte2_clear(cmap1_pte2p);
5916 tlb_flush((vm_offset_t)pc->pc_cmap1_addr);
5917 pte2_clear(cmap2_pte2p);
5918 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5920 mtx_unlock(&pc->pc_cmap_lock);
5924 pmap_quick_enter_page(vm_page_t m)
5931 pte2p = pc->pc_qmap_pte2p;
5933 KASSERT(pte2_load(pte2p) == 0, ("%s: PTE2 busy", __func__));
5935 pte2_store(pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5936 vm_page_pte2_attr(m)));
5937 return (pc->pc_qmap_addr);
5941 pmap_quick_remove_page(vm_offset_t addr)
5947 pte2p = pc->pc_qmap_pte2p;
5949 KASSERT(addr == pc->pc_qmap_addr, ("%s: invalid address", __func__));
5950 KASSERT(pte2_load(pte2p) != 0, ("%s: PTE2 not in use", __func__));
5953 tlb_flush(pc->pc_qmap_addr);
5958 * Copy the range specified by src_addr/len
5959 * from the source map to the range dst_addr/len
5960 * in the destination map.
5962 * This routine is only advisory and need not do anything.
5965 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
5966 vm_offset_t src_addr)
5968 struct spglist free;
5970 vm_offset_t end_addr = src_addr + len;
5973 if (dst_addr != src_addr)
5976 if (!pmap_is_current(src_pmap))
5979 rw_wlock(&pvh_global_lock);
5980 if (dst_pmap < src_pmap) {
5981 PMAP_LOCK(dst_pmap);
5982 PMAP_LOCK(src_pmap);
5984 PMAP_LOCK(src_pmap);
5985 PMAP_LOCK(dst_pmap);
5988 for (addr = src_addr; addr < end_addr; addr = nextva) {
5989 pt2_entry_t *src_pte2p, *dst_pte2p;
5990 vm_page_t dst_mpt2pg, src_mpt2pg;
5991 pt1_entry_t src_pte1;
5994 KASSERT(addr < VM_MAXUSER_ADDRESS,
5995 ("%s: invalid to pmap_copy page tables", __func__));
5997 nextva = pte1_trunc(addr + PTE1_SIZE);
6001 pte1_idx = pte1_index(addr);
6002 src_pte1 = src_pmap->pm_pt1[pte1_idx];
6003 if (pte1_is_section(src_pte1)) {
6004 if ((addr & PTE1_OFFSET) != 0 ||
6005 (addr + PTE1_SIZE) > end_addr)
6007 if (dst_pmap->pm_pt1[pte1_idx] == 0 &&
6008 (!pte1_is_managed(src_pte1) ||
6009 pmap_pv_insert_pte1(dst_pmap, addr,
6010 pte1_pa(src_pte1)))) {
6011 dst_pmap->pm_pt1[pte1_idx] = src_pte1 &
6013 dst_pmap->pm_stats.resident_count +=
6014 PTE1_SIZE / PAGE_SIZE;
6015 pmap_pte1_mappings++;
6018 } else if (!pte1_is_link(src_pte1))
6021 src_mpt2pg = PHYS_TO_VM_PAGE(pte1_link_pa(src_pte1));
6024 * We leave PT2s to be linked from PT1 even if they are not
6025 * referenced until all PT2s in a page are without reference.
6027 * QQQ: It could be changed ...
6029 #if 0 /* single_pt2_link_is_cleared */
6030 KASSERT(pt2_wirecount_get(src_mpt2pg, pte1_idx) > 0,
6031 ("%s: source page table page is unused", __func__));
6033 if (pt2_wirecount_get(src_mpt2pg, pte1_idx) == 0)
6036 if (nextva > end_addr)
6039 src_pte2p = pt2map_entry(addr);
6040 while (addr < nextva) {
6041 pt2_entry_t temp_pte2;
6042 temp_pte2 = pte2_load(src_pte2p);
6044 * we only virtual copy managed pages
6046 if (pte2_is_managed(temp_pte2)) {
6047 dst_mpt2pg = pmap_allocpte2(dst_pmap, addr,
6048 PMAP_ENTER_NOSLEEP);
6049 if (dst_mpt2pg == NULL)
6051 dst_pte2p = pmap_pte2_quick(dst_pmap, addr);
6052 if (!pte2_is_valid(pte2_load(dst_pte2p)) &&
6053 pmap_try_insert_pv_entry(dst_pmap, addr,
6054 PHYS_TO_VM_PAGE(pte2_pa(temp_pte2)))) {
6056 * Clear the wired, modified, and
6057 * accessed (referenced) bits
6060 temp_pte2 &= ~(PTE2_W | PTE2_A);
6061 temp_pte2 |= PTE2_NM;
6062 pte2_store(dst_pte2p, temp_pte2);
6063 dst_pmap->pm_stats.resident_count++;
6066 if (pmap_unwire_pt2(dst_pmap, addr,
6067 dst_mpt2pg, &free)) {
6068 pmap_tlb_flush(dst_pmap, addr);
6069 pmap_free_zero_pages(&free);
6073 if (pt2_wirecount_get(dst_mpt2pg, pte1_idx) >=
6074 pt2_wirecount_get(src_mpt2pg, pte1_idx))
6083 rw_wunlock(&pvh_global_lock);
6084 PMAP_UNLOCK(src_pmap);
6085 PMAP_UNLOCK(dst_pmap);
6089 * Increase the starting virtual address of the given mapping if a
6090 * different alignment might result in more section mappings.
6093 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6094 vm_offset_t *addr, vm_size_t size)
6096 vm_offset_t pte1_offset;
6098 if (size < PTE1_SIZE)
6100 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6101 offset += ptoa(object->pg_color);
6102 pte1_offset = offset & PTE1_OFFSET;
6103 if (size - ((PTE1_SIZE - pte1_offset) & PTE1_OFFSET) < PTE1_SIZE ||
6104 (*addr & PTE1_OFFSET) == pte1_offset)
6106 if ((*addr & PTE1_OFFSET) < pte1_offset)
6107 *addr = pte1_trunc(*addr) + pte1_offset;
6109 *addr = pte1_roundup(*addr) + pte1_offset;
6113 pmap_activate(struct thread *td)
6115 pmap_t pmap, oldpmap;
6118 PDEBUG(9, printf("%s: td = %08x\n", __func__, (uint32_t)td));
6121 pmap = vmspace_pmap(td->td_proc->p_vmspace);
6122 oldpmap = PCPU_GET(curpmap);
6123 cpuid = PCPU_GET(cpuid);
6126 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
6127 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
6129 CPU_CLR(cpuid, &oldpmap->pm_active);
6130 CPU_SET(cpuid, &pmap->pm_active);
6133 ttb = pmap_ttb_get(pmap);
6136 * pmap_activate is for the current thread on the current cpu
6138 td->td_pcb->pcb_pagedir = ttb;
6140 PCPU_SET(curpmap, pmap);
6145 * Perform the pmap work for mincore.
6148 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
6150 pt1_entry_t *pte1p, pte1;
6151 pt2_entry_t *pte2p, pte2;
6158 pte1p = pmap_pte1(pmap, addr);
6159 pte1 = pte1_load(pte1p);
6160 if (pte1_is_section(pte1)) {
6161 pa = trunc_page(pte1_pa(pte1) | (addr & PTE1_OFFSET));
6162 managed = pte1_is_managed(pte1);
6163 val = MINCORE_SUPER | MINCORE_INCORE;
6164 if (pte1_is_dirty(pte1))
6165 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6167 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6168 } else if (pte1_is_link(pte1)) {
6169 pte2p = pmap_pte2(pmap, addr);
6170 pte2 = pte2_load(pte2p);
6171 pmap_pte2_release(pte2p);
6173 managed = pte2_is_managed(pte2);
6174 val = MINCORE_INCORE;
6175 if (pte2_is_dirty(pte2))
6176 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6178 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6183 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
6184 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
6185 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
6186 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
6189 PA_UNLOCK_COND(*locked_pa);
6195 pmap_kenter_device(vm_offset_t va, vm_size_t size, vm_paddr_t pa)
6200 KASSERT((size & PAGE_MASK) == 0,
6201 ("%s: device mapping not page-sized", __func__));
6204 l2attr = vm_memattr_to_pte2(VM_MEMATTR_DEVICE);
6206 pmap_kenter_prot_attr(va, pa, PTE2_AP_KRW, l2attr);
6211 tlb_flush_range(sva, va - sva);
6215 pmap_kremove_device(vm_offset_t va, vm_size_t size)
6219 KASSERT((size & PAGE_MASK) == 0,
6220 ("%s: device mapping not page-sized", __func__));
6228 tlb_flush_range(sva, va - sva);
6232 pmap_set_pcb_pagedir(pmap_t pmap, struct pcb *pcb)
6235 pcb->pcb_pagedir = pmap_ttb_get(pmap);
6240 * Clean L1 data cache range by physical address.
6241 * The range must be within a single page.
6244 pmap_dcache_wb_pou(vm_paddr_t pa, vm_size_t size, uint32_t attr)
6246 pt2_entry_t *cmap2_pte2p;
6249 KASSERT(((pa & PAGE_MASK) + size) <= PAGE_SIZE,
6250 ("%s: not on single page", __func__));
6254 cmap2_pte2p = pc->pc_cmap2_pte2p;
6255 mtx_lock(&pc->pc_cmap_lock);
6256 if (pte2_load(cmap2_pte2p) != 0)
6257 panic("%s: CMAP2 busy", __func__);
6258 pte2_store(cmap2_pte2p, PTE2_KERN_NG(pa, PTE2_AP_KRW, attr));
6259 dcache_wb_pou((vm_offset_t)pc->pc_cmap2_addr + (pa & PAGE_MASK), size);
6260 pte2_clear(cmap2_pte2p);
6261 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
6263 mtx_unlock(&pc->pc_cmap_lock);
6267 * Sync instruction cache range which is not mapped yet.
6270 cache_icache_sync_fresh(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
6272 uint32_t len, offset;
6275 /* Write back d-cache on given address range. */
6276 offset = pa & PAGE_MASK;
6277 for ( ; size != 0; size -= len, pa += len, offset = 0) {
6278 len = min(PAGE_SIZE - offset, size);
6279 m = PHYS_TO_VM_PAGE(pa);
6280 KASSERT(m != NULL, ("%s: vm_page_t is null for %#x",
6282 pmap_dcache_wb_pou(pa, len, vm_page_pte2_attr(m));
6285 * I-cache is VIPT. Only way how to flush all virtual mappings
6286 * on given physical address is to invalidate all i-cache.
6292 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t size)
6295 /* Write back d-cache on given address range. */
6296 if (va >= VM_MIN_KERNEL_ADDRESS) {
6297 dcache_wb_pou(va, size);
6299 uint32_t len, offset;
6303 offset = va & PAGE_MASK;
6304 for ( ; size != 0; size -= len, va += len, offset = 0) {
6305 pa = pmap_extract(pmap, va); /* offset is preserved */
6306 len = min(PAGE_SIZE - offset, size);
6307 m = PHYS_TO_VM_PAGE(pa);
6308 KASSERT(m != NULL, ("%s: vm_page_t is null for %#x",
6310 pmap_dcache_wb_pou(pa, len, vm_page_pte2_attr(m));
6314 * I-cache is VIPT. Only way how to flush all virtual mappings
6315 * on given physical address is to invalidate all i-cache.
6321 * The implementation of pmap_fault() uses IN_RANGE2() macro which
6322 * depends on the fact that given range size is a power of 2.
6324 CTASSERT(powerof2(NB_IN_PT1));
6325 CTASSERT(powerof2(PT2MAP_SIZE));
6327 #define IN_RANGE2(addr, start, size) \
6328 ((vm_offset_t)(start) == ((vm_offset_t)(addr) & ~((size) - 1)))
6331 * Handle access and R/W emulation faults.
6334 pmap_fault(pmap_t pmap, vm_offset_t far, uint32_t fsr, int idx, bool usermode)
6336 pt1_entry_t *pte1p, pte1;
6337 pt2_entry_t *pte2p, pte2;
6343 * In kernel, we should never get abort with FAR which is in range of
6344 * pmap->pm_pt1 or PT2MAP address spaces. If it happens, stop here
6345 * and print out a useful abort message and even get to the debugger
6346 * otherwise it likely ends with never ending loop of aborts.
6348 if (__predict_false(IN_RANGE2(far, pmap->pm_pt1, NB_IN_PT1))) {
6350 * All L1 tables should always be mapped and present.
6351 * However, we check only current one herein. For user mode,
6352 * only permission abort from malicious user is not fatal.
6353 * And alignment abort as it may have higher priority.
6355 if (!usermode || (idx != FAULT_ALIGN && idx != FAULT_PERM_L2)) {
6356 CTR4(KTR_PMAP, "%s: pmap %#x pm_pt1 %#x far %#x",
6357 __func__, pmap, pmap->pm_pt1, far);
6358 panic("%s: pm_pt1 abort", __func__);
6360 return (KERN_INVALID_ADDRESS);
6362 if (__predict_false(IN_RANGE2(far, PT2MAP, PT2MAP_SIZE))) {
6364 * PT2MAP should be always mapped and present in current
6365 * L1 table. However, only existing L2 tables are mapped
6366 * in PT2MAP. For user mode, only L2 translation abort and
6367 * permission abort from malicious user is not fatal.
6368 * And alignment abort as it may have higher priority.
6370 if (!usermode || (idx != FAULT_ALIGN &&
6371 idx != FAULT_TRAN_L2 && idx != FAULT_PERM_L2)) {
6372 CTR4(KTR_PMAP, "%s: pmap %#x PT2MAP %#x far %#x",
6373 __func__, pmap, PT2MAP, far);
6374 panic("%s: PT2MAP abort", __func__);
6376 return (KERN_INVALID_ADDRESS);
6380 * A pmap lock is used below for handling of access and R/W emulation
6381 * aborts. They were handled by atomic operations before so some
6382 * analysis of new situation is needed to answer the following question:
6383 * Is it safe to use the lock even for these aborts?
6385 * There may happen two cases in general:
6387 * (1) Aborts while the pmap lock is locked already - this should not
6388 * happen as pmap lock is not recursive. However, under pmap lock only
6389 * internal kernel data should be accessed and such data should be
6390 * mapped with A bit set and NM bit cleared. If double abort happens,
6391 * then a mapping of data which has caused it must be fixed. Further,
6392 * all new mappings are always made with A bit set and the bit can be
6393 * cleared only on managed mappings.
6395 * (2) Aborts while another lock(s) is/are locked - this already can
6396 * happen. However, there is no difference here if it's either access or
6397 * R/W emulation abort, or if it's some other abort.
6403 * Special treatment is due to break-before-make approach done when
6404 * pte1 is updated for userland mapping during section promotion or
6405 * demotion. If not caught here, pmap_enter() can find a section
6406 * mapping on faulting address. That is not allowed.
6408 if (idx == FAULT_TRAN_L1 && usermode && cp15_ats1cur_check(far) == 0) {
6410 return (KERN_SUCCESS);
6414 * Accesss bits for page and section. Note that the entry
6415 * is not in TLB yet, so TLB flush is not necessary.
6417 * QQQ: This is hardware emulation, we do not call userret()
6418 * for aborts from user mode.
6420 if (idx == FAULT_ACCESS_L2) {
6421 pte2p = pt2map_entry(far);
6422 pte2 = pte2_load(pte2p);
6423 if (pte2_is_valid(pte2)) {
6424 pte2_store(pte2p, pte2 | PTE2_A);
6426 return (KERN_SUCCESS);
6429 if (idx == FAULT_ACCESS_L1) {
6430 pte1p = pmap_pte1(pmap, far);
6431 pte1 = pte1_load(pte1p);
6432 if (pte1_is_section(pte1)) {
6433 pte1_store(pte1p, pte1 | PTE1_A);
6435 return (KERN_SUCCESS);
6440 * Handle modify bits for page and section. Note that the modify
6441 * bit is emulated by software. So PTEx_RO is software read only
6442 * bit and PTEx_NM flag is real hardware read only bit.
6444 * QQQ: This is hardware emulation, we do not call userret()
6445 * for aborts from user mode.
6447 if ((fsr & FSR_WNR) && (idx == FAULT_PERM_L2)) {
6448 pte2p = pt2map_entry(far);
6449 pte2 = pte2_load(pte2p);
6450 if (pte2_is_valid(pte2) && !(pte2 & PTE2_RO) &&
6452 pte2_store(pte2p, pte2 & ~PTE2_NM);
6453 tlb_flush(trunc_page(far));
6455 return (KERN_SUCCESS);
6458 if ((fsr & FSR_WNR) && (idx == FAULT_PERM_L1)) {
6459 pte1p = pmap_pte1(pmap, far);
6460 pte1 = pte1_load(pte1p);
6461 if (pte1_is_section(pte1) && !(pte1 & PTE1_RO) &&
6463 pte1_store(pte1p, pte1 & ~PTE1_NM);
6464 tlb_flush(pte1_trunc(far));
6466 return (KERN_SUCCESS);
6471 * QQQ: The previous code, mainly fast handling of access and
6472 * modify bits aborts, could be moved to ASM. Now we are
6473 * starting to deal with not fast aborts.
6478 * Read an entry in PT2TAB associated with both pmap and far.
6479 * It's safe because PT2TAB is always mapped.
6481 pte2 = pt2tab_load(pmap_pt2tab_entry(pmap, far));
6482 if (pte2_is_valid(pte2)) {
6484 * Now, when we know that L2 page table is allocated,
6485 * we can use PT2MAP to get L2 page table entry.
6487 pte2 = pte2_load(pt2map_entry(far));
6488 if (pte2_is_valid(pte2)) {
6490 * If L2 page table entry is valid, make sure that
6491 * L1 page table entry is valid too. Note that we
6492 * leave L2 page entries untouched when promoted.
6494 pte1 = pte1_load(pmap_pte1(pmap, far));
6495 if (!pte1_is_valid(pte1)) {
6496 panic("%s: missing L1 page entry (%p, %#x)",
6497 __func__, pmap, far);
6503 return (KERN_FAILURE);
6506 #if defined(PMAP_DEBUG)
6508 * Reusing of KVA used in pmap_zero_page function !!!
6511 pmap_zero_page_check(vm_page_t m)
6513 pt2_entry_t *cmap2_pte2p;
6519 cmap2_pte2p = pc->pc_cmap2_pte2p;
6520 mtx_lock(&pc->pc_cmap_lock);
6521 if (pte2_load(cmap2_pte2p) != 0)
6522 panic("%s: CMAP2 busy", __func__);
6523 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
6524 vm_page_pte2_attr(m)));
6525 end = (uint32_t*)(pc->pc_cmap2_addr + PAGE_SIZE);
6526 for (p = (uint32_t*)pc->pc_cmap2_addr; p < end; p++)
6528 panic("%s: page %p not zero, va: %p", __func__, m,
6530 pte2_clear(cmap2_pte2p);
6531 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
6533 mtx_unlock(&pc->pc_cmap_lock);
6537 pmap_pid_dump(int pid)
6544 sx_slock(&allproc_lock);
6545 FOREACH_PROC_IN_SYSTEM(p) {
6546 if (p->p_pid != pid || p->p_vmspace == NULL)
6549 pmap = vmspace_pmap(p->p_vmspace);
6550 for (i = 0; i < NPTE1_IN_PT1; i++) {
6552 pt2_entry_t *pte2p, pte2;
6553 vm_offset_t base, va;
6557 base = i << PTE1_SHIFT;
6558 pte1 = pte1_load(&pmap->pm_pt1[i]);
6560 if (pte1_is_section(pte1)) {
6562 * QQQ: Do something here!
6564 } else if (pte1_is_link(pte1)) {
6565 for (j = 0; j < NPTE2_IN_PT2; j++) {
6566 va = base + (j << PAGE_SHIFT);
6567 if (va >= VM_MIN_KERNEL_ADDRESS) {
6572 sx_sunlock(&allproc_lock);
6575 pte2p = pmap_pte2(pmap, va);
6576 pte2 = pte2_load(pte2p);
6577 pmap_pte2_release(pte2p);
6578 if (!pte2_is_valid(pte2))
6582 m = PHYS_TO_VM_PAGE(pa);
6583 printf("va: 0x%x, pa: 0x%x, h: %d, w:"
6584 " %d, f: 0x%x", va, pa,
6585 m->hold_count, m->wire_count,
6599 sx_sunlock(&allproc_lock);
6606 static pt2_entry_t *
6607 pmap_pte2_ddb(pmap_t pmap, vm_offset_t va)
6610 vm_paddr_t pt2pg_pa;
6612 pte1 = pte1_load(pmap_pte1(pmap, va));
6613 if (!pte1_is_link(pte1))
6616 if (pmap_is_current(pmap))
6617 return (pt2map_entry(va));
6619 /* Note that L2 page table size is not equal to PAGE_SIZE. */
6620 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
6621 if (pte2_pa(pte2_load(PMAP3)) != pt2pg_pa) {
6622 pte2_store(PMAP3, PTE2_KPT(pt2pg_pa));
6624 PMAP3cpu = PCPU_GET(cpuid);
6626 tlb_flush_local((vm_offset_t)PADDR3);
6629 else if (PMAP3cpu != PCPU_GET(cpuid)) {
6630 PMAP3cpu = PCPU_GET(cpuid);
6631 tlb_flush_local((vm_offset_t)PADDR3);
6634 return (PADDR3 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
6638 dump_pmap(pmap_t pmap)
6641 printf("pmap %p\n", pmap);
6642 printf(" pm_pt1: %p\n", pmap->pm_pt1);
6643 printf(" pm_pt2tab: %p\n", pmap->pm_pt2tab);
6644 printf(" pm_active: 0x%08lX\n", pmap->pm_active.__bits[0]);
6647 DB_SHOW_COMMAND(pmaps, pmap_list_pmaps)
6651 LIST_FOREACH(pmap, &allpmaps, pm_list) {
6657 pte2_class(pt2_entry_t pte2)
6661 cls = (pte2 >> 2) & 0x03;
6662 cls |= (pte2 >> 4) & 0x04;
6667 dump_section(pmap_t pmap, uint32_t pte1_idx)
6672 dump_link(pmap_t pmap, uint32_t pte1_idx, boolean_t invalid_ok)
6676 pt2_entry_t *pte2p, pte2;
6679 va = pte1_idx << PTE1_SHIFT;
6680 pte2p = pmap_pte2_ddb(pmap, va);
6681 for (i = 0; i < NPTE2_IN_PT2; i++, pte2p++, va += PAGE_SIZE) {
6682 pte2 = pte2_load(pte2p);
6685 if (!pte2_is_valid(pte2)) {
6686 printf(" 0x%08X: 0x%08X", va, pte2);
6688 printf(" - not valid !!!");
6692 m = PHYS_TO_VM_PAGE(pte2_pa(pte2));
6693 printf(" 0x%08X: 0x%08X, TEX%d, s:%d, g:%d, m:%p", va , pte2,
6694 pte2_class(pte2), !!(pte2 & PTE2_S), !(pte2 & PTE2_NG), m);
6696 printf(" v:%d h:%d w:%d f:0x%04X\n", m->valid,
6697 m->hold_count, m->wire_count, m->flags);
6704 static __inline boolean_t
6705 is_pv_chunk_space(vm_offset_t va)
6708 if ((((vm_offset_t)pv_chunkbase) <= va) &&
6709 (va < ((vm_offset_t)pv_chunkbase + PAGE_SIZE * pv_maxchunks)))
6714 DB_SHOW_COMMAND(pmap, pmap_pmap_print)
6716 /* XXX convert args. */
6717 pmap_t pmap = (pmap_t)addr;
6720 vm_offset_t va, eva;
6723 boolean_t invalid_ok, dump_link_ok, dump_pv_chunk;
6728 LIST_FOREACH(pm, &allpmaps, pm_list)
6729 if (pm == pmap) break;
6731 printf("given pmap %p is not in allpmaps list\n", pmap);
6735 pmap = PCPU_GET(curpmap);
6737 eva = (modif[0] == 'u') ? VM_MAXUSER_ADDRESS : 0xFFFFFFFF;
6738 dump_pv_chunk = FALSE; /* XXX evaluate from modif[] */
6740 printf("pmap: 0x%08X\n", (uint32_t)pmap);
6741 printf("PT2MAP: 0x%08X\n", (uint32_t)PT2MAP);
6742 printf("pt2tab: 0x%08X\n", (uint32_t)pmap->pm_pt2tab);
6744 for(i = 0; i < NPTE1_IN_PT1; i++) {
6745 pte1 = pte1_load(&pmap->pm_pt1[i]);
6748 va = i << PTE1_SHIFT;
6752 if (pte1_is_section(pte1)) {
6753 printf("0x%08X: Section 0x%08X, s:%d g:%d\n", va, pte1,
6754 !!(pte1 & PTE1_S), !(pte1 & PTE1_NG));
6755 dump_section(pmap, i);
6756 } else if (pte1_is_link(pte1)) {
6757 dump_link_ok = TRUE;
6759 pte2 = pte2_load(pmap_pt2tab_entry(pmap, va));
6760 m = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
6761 printf("0x%08X: Link 0x%08X, pt2tab: 0x%08X m: %p",
6763 if (is_pv_chunk_space(va)) {
6764 printf(" - pv_chunk space");
6768 dump_link_ok = FALSE;
6771 printf(" w:%d w2:%u", m->wire_count,
6772 pt2_wirecount_get(m, pte1_index(va)));
6774 printf(" !!! pt2tab entry is ZERO");
6775 else if (pte2_pa(pte1) != pte2_pa(pte2))
6776 printf(" !!! pt2tab entry is DIFFERENT - m: %p",
6777 PHYS_TO_VM_PAGE(pte2_pa(pte2)));
6780 dump_link(pmap, i, invalid_ok);
6782 printf("0x%08X: Invalid entry 0x%08X\n", va, pte1);
6787 dump_pt2tab(pmap_t pmap)
6795 printf("PT2TAB:\n");
6796 for (i = 0; i < PT2TAB_ENTRIES; i++) {
6797 pte2 = pte2_load(&pmap->pm_pt2tab[i]);
6798 if (!pte2_is_valid(pte2))
6800 va = i << PT2TAB_SHIFT;
6802 m = PHYS_TO_VM_PAGE(pa);
6803 printf(" 0x%08X: 0x%08X, TEX%d, s:%d, m:%p", va, pte2,
6804 pte2_class(pte2), !!(pte2 & PTE2_S), m);
6806 printf(" , h: %d, w: %d, f: 0x%04X pidx: %lld",
6807 m->hold_count, m->wire_count, m->flags, m->pindex);
6812 DB_SHOW_COMMAND(pmap_pt2tab, pmap_pt2tab_print)
6814 /* XXX convert args. */
6815 pmap_t pmap = (pmap_t)addr;
6822 printf("supported only on current pmap\n");
6826 pmap = PCPU_GET(curpmap);
6827 printf("curpmap: 0x%08X\n", (uint32_t)pmap);
6828 printf("PT2MAP: 0x%08X\n", (uint32_t)PT2MAP);
6829 printf("pt2tab: 0x%08X\n", (uint32_t)pmap->pm_pt2tab);
6831 start = pte1_index((vm_offset_t)PT2MAP);
6832 for (i = start; i < (start + NPT2_IN_PT2TAB); i++) {
6833 pte1 = pte1_load(&pmap->pm_pt1[i]);
6836 va = i << PTE1_SHIFT;
6837 if (pte1_is_section(pte1)) {
6838 printf("0x%08X: Section 0x%08X, s:%d\n", va, pte1,
6840 dump_section(pmap, i);
6841 } else if (pte1_is_link(pte1)) {
6842 pte2 = pte2_load(pmap_pt2tab_entry(pmap, va));
6843 printf("0x%08X: Link 0x%08X, pt2tab: 0x%08X\n", va,
6846 printf(" !!! pt2tab entry is ZERO\n");
6848 printf("0x%08X: Invalid entry 0x%08X\n", va, pte1);