2 * SPDX-License-Identifier: BSD-3-Clause AND BSD-2-Clause-FreeBSD
4 * Copyright (c) 1991 Regents of the University of California.
5 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
7 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
8 * Copyright (c) 2014-2016 Svatopluk Kraus <skra@FreeBSD.org>
9 * Copyright (c) 2014-2016 Michal Meloun <mmel@FreeBSD.org>
10 * All rights reserved.
12 * This code is derived from software contributed to Berkeley by
13 * the Systems Programming Group of the University of Utah Computer
14 * Science Department and William Jolitz of UUNET Technologies Inc.
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions
19 * 1. Redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution.
24 * 3. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
43 * Copyright (c) 2003 Networks Associates Technology, Inc.
44 * All rights reserved.
46 * This software was developed for the FreeBSD Project by Jake Burkholder,
47 * Safeport Network Services, and Network Associates Laboratories, the
48 * Security Research Division of Network Associates, Inc. under
49 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
50 * CHATS research program.
52 * Redistribution and use in source and binary forms, with or without
53 * modification, are permitted provided that the following conditions
55 * 1. Redistributions of source code must retain the above copyright
56 * notice, this list of conditions and the following disclaimer.
57 * 2. Redistributions in binary form must reproduce the above copyright
58 * notice, this list of conditions and the following disclaimer in the
59 * documentation and/or other materials provided with the distribution.
61 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
62 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
64 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
74 #include <sys/cdefs.h>
75 __FBSDID("$FreeBSD$");
78 * Manages physical address maps.
80 * Since the information managed by this module is
81 * also stored by the logical address mapping module,
82 * this module may throw away valid virtual-to-physical
83 * mappings at almost any time. However, invalidations
84 * of virtual-to-physical mappings must be done as
87 * In order to cope with hardware architectures which
88 * make virtual-to-physical map invalidates expensive,
89 * this module may delay invalidate or reduced protection
90 * operations until such time as they are actually
91 * necessary. This module is given full information as
92 * to which processors are currently using which maps,
93 * and to when physical maps must be made correct.
100 #include <sys/param.h>
101 #include <sys/systm.h>
102 #include <sys/kernel.h>
104 #include <sys/lock.h>
105 #include <sys/proc.h>
106 #include <sys/rwlock.h>
107 #include <sys/malloc.h>
108 #include <sys/vmmeter.h>
109 #include <sys/malloc.h>
110 #include <sys/mman.h>
111 #include <sys/sf_buf.h>
113 #include <sys/sched.h>
114 #include <sys/sysctl.h>
120 #include <machine/physmem.h>
125 #include <vm/vm_param.h>
126 #include <vm/vm_kern.h>
127 #include <vm/vm_object.h>
128 #include <vm/vm_map.h>
129 #include <vm/vm_page.h>
130 #include <vm/vm_pageout.h>
131 #include <vm/vm_phys.h>
132 #include <vm/vm_extern.h>
133 #include <vm/vm_reserv.h>
134 #include <sys/lock.h>
135 #include <sys/mutex.h>
137 #include <machine/md_var.h>
138 #include <machine/pmap_var.h>
139 #include <machine/cpu.h>
140 #include <machine/pcb.h>
141 #include <machine/sf_buf.h>
143 #include <machine/smp.h>
145 #ifndef PMAP_SHPGPERPROC
146 #define PMAP_SHPGPERPROC 200
150 #define PMAP_INLINE __inline
156 static void pmap_zero_page_check(vm_page_t m);
157 void pmap_debug(int level);
158 int pmap_pid_dump(int pid);
160 #define PDEBUG(_lev_,_stat_) \
161 if (pmap_debug_level >= (_lev_)) \
163 #define dprintf printf
164 int pmap_debug_level = 1;
165 #else /* PMAP_DEBUG */
166 #define PDEBUG(_lev_,_stat_) /* Nothing */
167 #define dprintf(x, arg...)
168 #endif /* PMAP_DEBUG */
171 * Level 2 page tables map definion ('max' is excluded).
174 #define PT2V_MIN_ADDRESS ((vm_offset_t)PT2MAP)
175 #define PT2V_MAX_ADDRESS ((vm_offset_t)PT2MAP + PT2MAP_SIZE)
177 #define UPT2V_MIN_ADDRESS ((vm_offset_t)PT2MAP)
178 #define UPT2V_MAX_ADDRESS \
179 ((vm_offset_t)(PT2MAP + (KERNBASE >> PT2MAP_SHIFT)))
182 * Promotion to a 1MB (PTE1) page mapping requires that the corresponding
183 * 4KB (PTE2) page mappings have identical settings for the following fields:
185 #define PTE2_PROMOTE (PTE2_V | PTE2_A | PTE2_NM | PTE2_S | PTE2_NG | \
186 PTE2_NX | PTE2_RO | PTE2_U | PTE2_W | \
189 #define PTE1_PROMOTE (PTE1_V | PTE1_A | PTE1_NM | PTE1_S | PTE1_NG | \
190 PTE1_NX | PTE1_RO | PTE1_U | PTE1_W | \
193 #define ATTR_TO_L1(l2_attr) ((((l2_attr) & L2_TEX0) ? L1_S_TEX0 : 0) | \
194 (((l2_attr) & L2_C) ? L1_S_C : 0) | \
195 (((l2_attr) & L2_B) ? L1_S_B : 0) | \
196 (((l2_attr) & PTE2_A) ? PTE1_A : 0) | \
197 (((l2_attr) & PTE2_NM) ? PTE1_NM : 0) | \
198 (((l2_attr) & PTE2_S) ? PTE1_S : 0) | \
199 (((l2_attr) & PTE2_NG) ? PTE1_NG : 0) | \
200 (((l2_attr) & PTE2_NX) ? PTE1_NX : 0) | \
201 (((l2_attr) & PTE2_RO) ? PTE1_RO : 0) | \
202 (((l2_attr) & PTE2_U) ? PTE1_U : 0) | \
203 (((l2_attr) & PTE2_W) ? PTE1_W : 0))
205 #define ATTR_TO_L2(l1_attr) ((((l1_attr) & L1_S_TEX0) ? L2_TEX0 : 0) | \
206 (((l1_attr) & L1_S_C) ? L2_C : 0) | \
207 (((l1_attr) & L1_S_B) ? L2_B : 0) | \
208 (((l1_attr) & PTE1_A) ? PTE2_A : 0) | \
209 (((l1_attr) & PTE1_NM) ? PTE2_NM : 0) | \
210 (((l1_attr) & PTE1_S) ? PTE2_S : 0) | \
211 (((l1_attr) & PTE1_NG) ? PTE2_NG : 0) | \
212 (((l1_attr) & PTE1_NX) ? PTE2_NX : 0) | \
213 (((l1_attr) & PTE1_RO) ? PTE2_RO : 0) | \
214 (((l1_attr) & PTE1_U) ? PTE2_U : 0) | \
215 (((l1_attr) & PTE1_W) ? PTE2_W : 0))
218 * PTE2 descriptors creation macros.
220 #define PTE2_ATTR_DEFAULT vm_memattr_to_pte2(VM_MEMATTR_DEFAULT)
221 #define PTE2_ATTR_PT vm_memattr_to_pte2(pt_memattr)
223 #define PTE2_KPT(pa) PTE2_KERN(pa, PTE2_AP_KRW, PTE2_ATTR_PT)
224 #define PTE2_KPT_NG(pa) PTE2_KERN_NG(pa, PTE2_AP_KRW, PTE2_ATTR_PT)
226 #define PTE2_KRW(pa) PTE2_KERN(pa, PTE2_AP_KRW, PTE2_ATTR_DEFAULT)
227 #define PTE2_KRO(pa) PTE2_KERN(pa, PTE2_AP_KR, PTE2_ATTR_DEFAULT)
231 #define PV_STAT(x) do { x ; } while (0)
233 #define PV_STAT(x) do { } while (0)
237 * The boot_pt1 is used temporary in very early boot stage as L1 page table.
238 * We can init many things with no memory allocation thanks to its static
239 * allocation and this brings two main advantages:
240 * (1) other cores can be started very simply,
241 * (2) various boot loaders can be supported as its arguments can be processed
242 * in virtual address space and can be moved to safe location before
243 * first allocation happened.
244 * Only disadvantage is that boot_pt1 is used only in very early boot stage.
245 * However, the table is uninitialized and so lays in bss. Therefore kernel
246 * image size is not influenced.
248 * QQQ: In the future, maybe, boot_pt1 can be used for soft reset and
249 * CPU suspend/resume game.
251 extern pt1_entry_t boot_pt1[];
254 pt1_entry_t *kern_pt1;
255 pt2_entry_t *kern_pt2tab;
258 static uint32_t ttb_flags;
259 static vm_memattr_t pt_memattr;
260 ttb_entry_t pmap_kern_ttb;
262 struct pmap kernel_pmap_store;
263 LIST_HEAD(pmaplist, pmap);
264 static struct pmaplist allpmaps;
265 static struct mtx allpmaps_lock;
267 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
268 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
270 static vm_offset_t kernel_vm_end_new;
271 vm_offset_t kernel_vm_end = KERNBASE + NKPT2PG * NPT2_IN_PG * PTE1_SIZE;
272 vm_offset_t vm_max_kernel_address;
273 vm_paddr_t kernel_l1pa;
275 static struct rwlock __aligned(CACHE_LINE_SIZE) pvh_global_lock;
278 * Data for the pv entry allocation mechanism
280 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
281 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
282 static struct md_page *pv_table; /* XXX: Is it used only the list in md_page? */
283 static int shpgperproc = PMAP_SHPGPERPROC;
285 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
286 int pv_maxchunks; /* How many chunks we have KVA for */
287 vm_offset_t pv_vafree; /* freelist stored in the PTE */
289 vm_paddr_t first_managed_pa;
290 #define pa_to_pvh(pa) (&pv_table[pte1_index(pa - first_managed_pa)])
293 * All those kernel PT submaps that BSD is so fond of
297 struct msgbuf *msgbufp = NULL; /* XXX move it to machdep.c */
302 static caddr_t crashdumpmap;
304 static pt2_entry_t *PMAP1 = NULL, *PMAP2;
305 static pt2_entry_t *PADDR1 = NULL, *PADDR2;
307 static pt2_entry_t *PMAP3;
308 static pt2_entry_t *PADDR3;
309 static int PMAP3cpu __unused; /* for SMP only */
313 static int PMAP1changedcpu;
314 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
316 "Number of times pmap_pte2_quick changed CPU with same PMAP1");
318 static int PMAP1changed;
319 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
321 "Number of times pmap_pte2_quick changed PMAP1");
322 static int PMAP1unchanged;
323 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
325 "Number of times pmap_pte2_quick didn't change PMAP1");
326 static struct mtx PMAP2mutex;
328 static __inline void pt2_wirecount_init(vm_page_t m);
329 static boolean_t pmap_demote_pte1(pmap_t pmap, pt1_entry_t *pte1p,
331 void cache_icache_sync_fresh(vm_offset_t va, vm_paddr_t pa, vm_size_t size);
334 * Function to set the debug level of the pmap code.
338 pmap_debug(int level)
341 pmap_debug_level = level;
342 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
344 #endif /* PMAP_DEBUG */
347 * This table must corespond with memory attribute configuration in vm.h.
348 * First entry is used for normal system mapping.
350 * Device memory is always marked as shared.
351 * Normal memory is shared only in SMP .
352 * Not outer shareable bits are not used yet.
353 * Class 6 cannot be used on ARM11.
355 #define TEXDEF_TYPE_SHIFT 0
356 #define TEXDEF_TYPE_MASK 0x3
357 #define TEXDEF_INNER_SHIFT 2
358 #define TEXDEF_INNER_MASK 0x3
359 #define TEXDEF_OUTER_SHIFT 4
360 #define TEXDEF_OUTER_MASK 0x3
361 #define TEXDEF_NOS_SHIFT 6
362 #define TEXDEF_NOS_MASK 0x1
364 #define TEX(t, i, o, s) \
365 ((t) << TEXDEF_TYPE_SHIFT) | \
366 ((i) << TEXDEF_INNER_SHIFT) | \
367 ((o) << TEXDEF_OUTER_SHIFT | \
368 ((s) << TEXDEF_NOS_SHIFT))
370 static uint32_t tex_class[8] = {
371 /* type inner cache outer cache */
372 TEX(PRRR_MEM, NMRR_WB_WA, NMRR_WB_WA, 0), /* 0 - ATTR_WB_WA */
373 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 1 - ATTR_NOCACHE */
374 TEX(PRRR_DEV, NMRR_NC, NMRR_NC, 0), /* 2 - ATTR_DEVICE */
375 TEX(PRRR_SO, NMRR_NC, NMRR_NC, 0), /* 3 - ATTR_SO */
376 TEX(PRRR_MEM, NMRR_WT, NMRR_WT, 0), /* 4 - ATTR_WT */
377 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 5 - NOT USED YET */
378 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 6 - NOT USED YET */
379 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 7 - NOT USED YET */
383 static uint32_t pte2_attr_tab[8] = {
384 PTE2_ATTR_WB_WA, /* 0 - VM_MEMATTR_WB_WA */
385 PTE2_ATTR_NOCACHE, /* 1 - VM_MEMATTR_NOCACHE */
386 PTE2_ATTR_DEVICE, /* 2 - VM_MEMATTR_DEVICE */
387 PTE2_ATTR_SO, /* 3 - VM_MEMATTR_SO */
388 PTE2_ATTR_WT, /* 4 - VM_MEMATTR_WRITE_THROUGH */
389 0, /* 5 - NOT USED YET */
390 0, /* 6 - NOT USED YET */
391 0 /* 7 - NOT USED YET */
393 CTASSERT(VM_MEMATTR_WB_WA == 0);
394 CTASSERT(VM_MEMATTR_NOCACHE == 1);
395 CTASSERT(VM_MEMATTR_DEVICE == 2);
396 CTASSERT(VM_MEMATTR_SO == 3);
397 CTASSERT(VM_MEMATTR_WRITE_THROUGH == 4);
399 static inline uint32_t
400 vm_memattr_to_pte2(vm_memattr_t ma)
403 KASSERT((u_int)ma < 5, ("%s: bad vm_memattr_t %d", __func__, ma));
404 return (pte2_attr_tab[(u_int)ma]);
407 static inline uint32_t
408 vm_page_pte2_attr(vm_page_t m)
411 return (vm_memattr_to_pte2(m->md.pat_mode));
415 * Convert TEX definition entry to TTB flags.
418 encode_ttb_flags(int idx)
420 uint32_t inner, outer, nos, reg;
422 inner = (tex_class[idx] >> TEXDEF_INNER_SHIFT) &
424 outer = (tex_class[idx] >> TEXDEF_OUTER_SHIFT) &
426 nos = (tex_class[idx] >> TEXDEF_NOS_SHIFT) &
431 if (cpuinfo.coherent_walk)
432 reg |= (inner & 0x1) << 6;
433 reg |= (inner & 0x2) >> 1;
443 * Set TEX remapping registers in current CPU.
449 uint32_t type, inner, outer, nos;
452 #ifdef PMAP_PTE_NOCACHE
454 if (cpuinfo.coherent_walk) {
455 pt_memattr = VM_MEMATTR_WB_WA;
456 ttb_flags = encode_ttb_flags(0);
459 pt_memattr = VM_MEMATTR_NOCACHE;
460 ttb_flags = encode_ttb_flags(1);
463 pt_memattr = VM_MEMATTR_WB_WA;
464 ttb_flags = encode_ttb_flags(0);
470 /* Build remapping register from TEX classes. */
471 for (i = 0; i < 8; i++) {
472 type = (tex_class[i] >> TEXDEF_TYPE_SHIFT) &
474 inner = (tex_class[i] >> TEXDEF_INNER_SHIFT) &
476 outer = (tex_class[i] >> TEXDEF_OUTER_SHIFT) &
478 nos = (tex_class[i] >> TEXDEF_NOS_SHIFT) &
481 prrr |= type << (i * 2);
482 prrr |= nos << (i + 24);
483 nmrr |= inner << (i * 2);
484 nmrr |= outer << (i * 2 + 16);
486 /* Add shareable bits for device memory. */
487 prrr |= PRRR_DS0 | PRRR_DS1;
489 /* Add shareable bits for normal memory in SMP case. */
498 /* Caches are disabled, so full TLB flush should be enough. */
499 tlb_flush_all_local();
503 * Remap one vm_meattr class to another one. This can be useful as
504 * workaround for SOC errata, e.g. if devices must be accessed using
507 * !!! Please note that this function is absolutely last resort thing.
508 * It should not be used under normal circumstances. !!!
511 * - it shall be called after pmap_bootstrap_prepare() and before
512 * cpu_mp_start() (thus only on boot CPU). In practice, it's expected
513 * to be called from platform_attach() or platform_late_init().
515 * - if remapping doesn't change caching mode, or until uncached class
516 * is remapped to any kind of cached one, then no other restriction exists.
518 * - if pmap_remap_vm_attr() changes caching mode, but both (original and
519 * remapped) remain cached, then caller is resposible for calling
520 * of dcache_wbinv_poc_all().
522 * - remapping of any kind of cached class to uncached is not permitted.
525 pmap_remap_vm_attr(vm_memattr_t old_attr, vm_memattr_t new_attr)
527 int old_idx, new_idx;
529 /* Map VM memattrs to indexes to tex_class table. */
530 old_idx = PTE2_ATTR2IDX(pte2_attr_tab[(int)old_attr]);
531 new_idx = PTE2_ATTR2IDX(pte2_attr_tab[(int)new_attr]);
533 /* Replace TEX attribute and apply it. */
534 tex_class[old_idx] = tex_class[new_idx];
539 * KERNBASE must be multiple of NPT2_IN_PG * PTE1_SIZE. In other words,
540 * KERNBASE is mapped by first L2 page table in L2 page table page. It
541 * meets same constrain due to PT2MAP being placed just under KERNBASE.
543 CTASSERT((KERNBASE & (NPT2_IN_PG * PTE1_SIZE - 1)) == 0);
544 CTASSERT((KERNBASE - VM_MAXUSER_ADDRESS) >= PT2MAP_SIZE);
547 * In crazy dreams, PAGE_SIZE could be a multiple of PTE2_SIZE in general.
548 * For now, anyhow, the following check must be fulfilled.
550 CTASSERT(PAGE_SIZE == PTE2_SIZE);
552 * We don't want to mess up MI code with all MMU and PMAP definitions,
553 * so some things, which depend on other ones, are defined independently.
554 * Now, it is time to check that we don't screw up something.
556 CTASSERT(PDRSHIFT == PTE1_SHIFT);
558 * Check L1 and L2 page table entries definitions consistency.
560 CTASSERT(NB_IN_PT1 == (sizeof(pt1_entry_t) * NPTE1_IN_PT1));
561 CTASSERT(NB_IN_PT2 == (sizeof(pt2_entry_t) * NPTE2_IN_PT2));
563 * Check L2 page tables page consistency.
565 CTASSERT(PAGE_SIZE == (NPT2_IN_PG * NB_IN_PT2));
566 CTASSERT((1 << PT2PG_SHIFT) == NPT2_IN_PG);
568 * Check PT2TAB consistency.
569 * PT2TAB_ENTRIES is defined as a division of NPTE1_IN_PT1 by NPT2_IN_PG.
570 * This should be done without remainder.
572 CTASSERT(NPTE1_IN_PT1 == (PT2TAB_ENTRIES * NPT2_IN_PG));
577 * All level 2 page tables (PT2s) are mapped continuously and accordingly
578 * into PT2MAP address space. As PT2 size is less than PAGE_SIZE, this can
579 * be done only if PAGE_SIZE is a multiple of PT2 size. All PT2s in one page
580 * must be used together, but not necessary at once. The first PT2 in a page
581 * must map things on correctly aligned address and the others must follow
584 #define NB_IN_PT2TAB (PT2TAB_ENTRIES * sizeof(pt2_entry_t))
585 #define NPT2_IN_PT2TAB (NB_IN_PT2TAB / NB_IN_PT2)
586 #define NPG_IN_PT2TAB (NB_IN_PT2TAB / PAGE_SIZE)
589 * Check PT2TAB consistency.
590 * NPT2_IN_PT2TAB is defined as a division of NB_IN_PT2TAB by NB_IN_PT2.
591 * NPG_IN_PT2TAB is defined as a division of NB_IN_PT2TAB by PAGE_SIZE.
592 * The both should be done without remainder.
594 CTASSERT(NB_IN_PT2TAB == (NPT2_IN_PT2TAB * NB_IN_PT2));
595 CTASSERT(NB_IN_PT2TAB == (NPG_IN_PT2TAB * PAGE_SIZE));
597 * The implementation was made general, however, with the assumption
598 * bellow in mind. In case of another value of NPG_IN_PT2TAB,
599 * the code should be once more rechecked.
601 CTASSERT(NPG_IN_PT2TAB == 1);
604 * Get offset of PT2 in a page
605 * associated with given PT1 index.
607 static __inline u_int
608 page_pt2off(u_int pt1_idx)
611 return ((pt1_idx & PT2PG_MASK) * NB_IN_PT2);
615 * Get physical address of PT2
616 * associated with given PT2s page and PT1 index.
618 static __inline vm_paddr_t
619 page_pt2pa(vm_paddr_t pgpa, u_int pt1_idx)
622 return (pgpa + page_pt2off(pt1_idx));
626 * Get first entry of PT2
627 * associated with given PT2s page and PT1 index.
629 static __inline pt2_entry_t *
630 page_pt2(vm_offset_t pgva, u_int pt1_idx)
633 return ((pt2_entry_t *)(pgva + page_pt2off(pt1_idx)));
637 * Get virtual address of PT2s page (mapped in PT2MAP)
638 * which holds PT2 which holds entry which maps given virtual address.
640 static __inline vm_offset_t
641 pt2map_pt2pg(vm_offset_t va)
644 va &= ~(NPT2_IN_PG * PTE1_SIZE - 1);
645 return ((vm_offset_t)pt2map_entry(va));
648 /*****************************************************************************
650 * THREE pmap initialization milestones exist:
653 * -> fundamental init (including MMU) in ASM
656 * -> fundamental init continues in C
657 * -> first available physical address is known
659 * pmap_bootstrap_prepare() -> FIRST PMAP MILESTONE (first epoch begins)
660 * -> basic (safe) interface for physical address allocation is made
661 * -> basic (safe) interface for virtual mapping is made
662 * -> limited not SMP coherent work is possible
664 * -> more fundamental init continues in C
665 * -> locks and some more things are available
666 * -> all fundamental allocations and mappings are done
668 * pmap_bootstrap() -> SECOND PMAP MILESTONE (second epoch begins)
669 * -> phys_avail[] and virtual_avail is set
670 * -> control is passed to vm subsystem
671 * -> physical and virtual address allocation are off limit
672 * -> low level mapping functions, some SMP coherent,
673 * are available, which cannot be used before vm subsystem
677 * -> vm subsystem is being inited
679 * pmap_init() -> THIRD PMAP MILESTONE (third epoch begins)
680 * -> pmap is fully inited
682 *****************************************************************************/
684 /*****************************************************************************
686 * PMAP first stage initialization and utility functions
687 * for pre-bootstrap epoch.
689 * After pmap_bootstrap_prepare() is called, the following functions
692 * (1) strictly only for this stage functions for physical page allocations,
693 * virtual space allocations, and mappings:
695 * vm_paddr_t pmap_preboot_get_pages(u_int num);
696 * void pmap_preboot_map_pages(vm_paddr_t pa, vm_offset_t va, u_int num);
697 * vm_offset_t pmap_preboot_reserve_pages(u_int num);
698 * vm_offset_t pmap_preboot_get_vpages(u_int num);
699 * void pmap_preboot_map_attr(vm_paddr_t pa, vm_offset_t va, vm_size_t size,
700 * vm_prot_t prot, vm_memattr_t attr);
702 * (2) for all stages:
704 * vm_paddr_t pmap_kextract(vm_offset_t va);
706 * NOTE: This is not SMP coherent stage.
708 *****************************************************************************/
710 #define KERNEL_P2V(pa) \
711 ((vm_offset_t)((pa) - arm_physmem_kernaddr + KERNVIRTADDR))
712 #define KERNEL_V2P(va) \
713 ((vm_paddr_t)((va) - KERNVIRTADDR + arm_physmem_kernaddr))
715 static vm_paddr_t last_paddr;
718 * Pre-bootstrap epoch page allocator.
721 pmap_preboot_get_pages(u_int num)
726 last_paddr += num * PAGE_SIZE;
732 * The fundamental initialization of PMAP stuff.
734 * Some things already happened in locore.S and some things could happen
735 * before pmap_bootstrap_prepare() is called, so let's recall what is done:
736 * 1. Caches are disabled.
737 * 2. We are running on virtual addresses already with 'boot_pt1'
739 * 3. So far, all virtual addresses can be converted to physical ones and
740 * vice versa by the following macros:
741 * KERNEL_P2V(pa) .... physical to virtual ones,
742 * KERNEL_V2P(va) .... virtual to physical ones.
744 * What is done herein:
745 * 1. The 'boot_pt1' is replaced by real kernel L1 page table 'kern_pt1'.
746 * 2. PT2MAP magic is brought to live.
747 * 3. Basic preboot functions for page allocations and mappings can be used.
748 * 4. Everything is prepared for L1 cache enabling.
751 * 1. To use second TTB register, so kernel and users page tables will be
752 * separated. This way process forking - pmap_pinit() - could be faster,
753 * it saves physical pages and KVA per a process, and it's simple change.
754 * However, it will lead, due to hardware matter, to the following:
755 * (a) 2G space for kernel and 2G space for users.
756 * (b) 1G space for kernel in low addresses and 3G for users above it.
757 * A question is: Is the case (b) really an option? Note that case (b)
758 * does save neither physical memory and KVA.
761 pmap_bootstrap_prepare(vm_paddr_t last)
763 vm_paddr_t pt2pg_pa, pt2tab_pa, pa, size;
764 vm_offset_t pt2pg_va;
771 * Now, we are going to make real kernel mapping. Note that we are
772 * already running on some mapping made in locore.S and we expect
773 * that it's large enough to ensure nofault access to physical memory
774 * allocated herein before switch.
776 * As kernel image and everything needed before are and will be mapped
777 * by section mappings, we align last physical address to PTE1_SIZE.
779 last_paddr = pte1_roundup(last);
782 * Allocate and zero page(s) for kernel L1 page table.
784 * Note that it's first allocation on space which was PTE1_SIZE
785 * aligned and as such base_pt1 is aligned to NB_IN_PT1 too.
787 base_pt1 = pmap_preboot_get_pages(NPG_IN_PT1);
788 kern_pt1 = (pt1_entry_t *)KERNEL_P2V(base_pt1);
789 bzero((void*)kern_pt1, NB_IN_PT1);
790 pte1_sync_range(kern_pt1, NB_IN_PT1);
792 /* Allocate and zero page(s) for kernel PT2TAB. */
793 pt2tab_pa = pmap_preboot_get_pages(NPG_IN_PT2TAB);
794 kern_pt2tab = (pt2_entry_t *)KERNEL_P2V(pt2tab_pa);
795 bzero(kern_pt2tab, NB_IN_PT2TAB);
796 pte2_sync_range(kern_pt2tab, NB_IN_PT2TAB);
798 /* Allocate and zero page(s) for kernel L2 page tables. */
799 pt2pg_pa = pmap_preboot_get_pages(NKPT2PG);
800 pt2pg_va = KERNEL_P2V(pt2pg_pa);
801 size = NKPT2PG * PAGE_SIZE;
802 bzero((void*)pt2pg_va, size);
803 pte2_sync_range((pt2_entry_t *)pt2pg_va, size);
806 * Add a physical memory segment (vm_phys_seg) corresponding to the
807 * preallocated pages for kernel L2 page tables so that vm_page
808 * structures representing these pages will be created. The vm_page
809 * structures are required for promotion of the corresponding kernel
810 * virtual addresses to section mappings.
812 vm_phys_add_seg(pt2tab_pa, pmap_preboot_get_pages(0));
815 * Insert allocated L2 page table pages to PT2TAB and make
816 * link to all PT2s in L1 page table. See how kernel_vm_end
819 * We play simple and safe. So every KVA will have underlaying
820 * L2 page table, even kernel image mapped by sections.
822 pte2p = kern_pt2tab_entry(KERNBASE);
823 for (pa = pt2pg_pa; pa < pt2pg_pa + size; pa += PTE2_SIZE)
824 pt2tab_store(pte2p++, PTE2_KPT(pa));
826 pte1p = kern_pte1(KERNBASE);
827 for (pa = pt2pg_pa; pa < pt2pg_pa + size; pa += NB_IN_PT2)
828 pte1_store(pte1p++, PTE1_LINK(pa));
830 /* Make section mappings for kernel. */
831 l1_attr = ATTR_TO_L1(PTE2_ATTR_DEFAULT);
832 pte1p = kern_pte1(KERNBASE);
833 for (pa = KERNEL_V2P(KERNBASE); pa < last; pa += PTE1_SIZE)
834 pte1_store(pte1p++, PTE1_KERN(pa, PTE1_AP_KRW, l1_attr));
837 * Get free and aligned space for PT2MAP and make L1 page table links
838 * to L2 page tables held in PT2TAB.
840 * Note that pages holding PT2s are stored in PT2TAB as pt2_entry_t
841 * descriptors and PT2TAB page(s) itself is(are) used as PT2s. Thus
842 * each entry in PT2TAB maps all PT2s in a page. This implies that
843 * virtual address of PT2MAP must be aligned to NPT2_IN_PG * PTE1_SIZE.
845 PT2MAP = (pt2_entry_t *)(KERNBASE - PT2MAP_SIZE);
846 pte1p = kern_pte1((vm_offset_t)PT2MAP);
847 for (pa = pt2tab_pa, i = 0; i < NPT2_IN_PT2TAB; i++, pa += NB_IN_PT2) {
848 pte1_store(pte1p++, PTE1_LINK(pa));
852 * Store PT2TAB in PT2TAB itself, i.e. self reference mapping.
853 * Each pmap will hold own PT2TAB, so the mapping should be not global.
855 pte2p = kern_pt2tab_entry((vm_offset_t)PT2MAP);
856 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE) {
857 pt2tab_store(pte2p++, PTE2_KPT_NG(pa));
861 * Choose correct L2 page table and make mappings for allocations
862 * made herein which replaces temporary locore.S mappings after a while.
863 * Note that PT2MAP cannot be used until we switch to kern_pt1.
865 * Note, that these allocations started aligned on 1M section and
866 * kernel PT1 was allocated first. Making of mappings must follow
867 * order of physical allocations as we've used KERNEL_P2V() macro
868 * for virtual addresses resolution.
870 pte2p = kern_pt2tab_entry((vm_offset_t)kern_pt1);
871 pt2pg_va = KERNEL_P2V(pte2_pa(pte2_load(pte2p)));
873 pte2p = page_pt2(pt2pg_va, pte1_index((vm_offset_t)kern_pt1));
875 /* Make mapping for kernel L1 page table. */
876 for (pa = base_pt1, i = 0; i < NPG_IN_PT1; i++, pa += PTE2_SIZE)
877 pte2_store(pte2p++, PTE2_KPT(pa));
879 /* Make mapping for kernel PT2TAB. */
880 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE)
881 pte2_store(pte2p++, PTE2_KPT(pa));
883 /* Finally, switch from 'boot_pt1' to 'kern_pt1'. */
884 pmap_kern_ttb = base_pt1 | ttb_flags;
885 cpuinfo_reinit_mmu(pmap_kern_ttb);
887 * Initialize the first available KVA. As kernel image is mapped by
888 * sections, we are leaving some gap behind.
890 virtual_avail = (vm_offset_t)kern_pt2tab + NPG_IN_PT2TAB * PAGE_SIZE;
894 * Setup L2 page table page for given KVA.
895 * Used in pre-bootstrap epoch.
897 * Note that we have allocated NKPT2PG pages for L2 page tables in advance
898 * and used them for mapping KVA starting from KERNBASE. However, this is not
899 * enough. Vectors and devices need L2 page tables too. Note that they are
900 * even above VM_MAX_KERNEL_ADDRESS.
902 static __inline vm_paddr_t
903 pmap_preboot_pt2pg_setup(vm_offset_t va)
905 pt2_entry_t *pte2p, pte2;
908 /* Get associated entry in PT2TAB. */
909 pte2p = kern_pt2tab_entry(va);
911 /* Just return, if PT2s page exists already. */
912 pte2 = pt2tab_load(pte2p);
913 if (pte2_is_valid(pte2))
914 return (pte2_pa(pte2));
916 KASSERT(va >= VM_MAX_KERNEL_ADDRESS,
917 ("%s: NKPT2PG too small", __func__));
920 * Allocate page for PT2s and insert it to PT2TAB.
921 * In other words, map it into PT2MAP space.
923 pt2pg_pa = pmap_preboot_get_pages(1);
924 pt2tab_store(pte2p, PTE2_KPT(pt2pg_pa));
926 /* Zero all PT2s in allocated page. */
927 bzero((void*)pt2map_pt2pg(va), PAGE_SIZE);
928 pte2_sync_range((pt2_entry_t *)pt2map_pt2pg(va), PAGE_SIZE);
934 * Setup L2 page table for given KVA.
935 * Used in pre-bootstrap epoch.
938 pmap_preboot_pt2_setup(vm_offset_t va)
941 vm_paddr_t pt2pg_pa, pt2_pa;
943 /* Setup PT2's page. */
944 pt2pg_pa = pmap_preboot_pt2pg_setup(va);
945 pt2_pa = page_pt2pa(pt2pg_pa, pte1_index(va));
947 /* Insert PT2 to PT1. */
948 pte1p = kern_pte1(va);
949 pte1_store(pte1p, PTE1_LINK(pt2_pa));
953 * Get L2 page entry associated with given KVA.
954 * Used in pre-bootstrap epoch.
956 static __inline pt2_entry_t*
957 pmap_preboot_vtopte2(vm_offset_t va)
961 /* Setup PT2 if needed. */
962 pte1p = kern_pte1(va);
963 if (!pte1_is_valid(pte1_load(pte1p))) /* XXX - sections ?! */
964 pmap_preboot_pt2_setup(va);
966 return (pt2map_entry(va));
970 * Pre-bootstrap epoch page(s) mapping(s).
973 pmap_preboot_map_pages(vm_paddr_t pa, vm_offset_t va, u_int num)
978 /* Map all the pages. */
979 for (i = 0; i < num; i++) {
980 pte2p = pmap_preboot_vtopte2(va);
981 pte2_store(pte2p, PTE2_KRW(pa));
988 * Pre-bootstrap epoch virtual space alocator.
991 pmap_preboot_reserve_pages(u_int num)
994 vm_offset_t start, va;
997 /* Allocate virtual space. */
998 start = va = virtual_avail;
999 virtual_avail += num * PAGE_SIZE;
1001 /* Zero the mapping. */
1002 for (i = 0; i < num; i++) {
1003 pte2p = pmap_preboot_vtopte2(va);
1004 pte2_store(pte2p, 0);
1012 * Pre-bootstrap epoch page(s) allocation and mapping(s).
1015 pmap_preboot_get_vpages(u_int num)
1020 /* Allocate physical page(s). */
1021 pa = pmap_preboot_get_pages(num);
1023 /* Allocate virtual space. */
1025 virtual_avail += num * PAGE_SIZE;
1027 /* Map and zero all. */
1028 pmap_preboot_map_pages(pa, va, num);
1029 bzero((void *)va, num * PAGE_SIZE);
1035 * Pre-bootstrap epoch page mapping(s) with attributes.
1038 pmap_preboot_map_attr(vm_paddr_t pa, vm_offset_t va, vm_size_t size,
1039 vm_prot_t prot, vm_memattr_t attr)
1042 u_int l1_attr, l1_prot, l2_prot, l2_attr;
1046 l2_prot = prot & VM_PROT_WRITE ? PTE2_AP_KRW : PTE2_AP_KR;
1047 l2_prot |= (prot & VM_PROT_EXECUTE) ? PTE2_X : PTE2_NX;
1048 l2_attr = vm_memattr_to_pte2(attr);
1049 l1_prot = ATTR_TO_L1(l2_prot);
1050 l1_attr = ATTR_TO_L1(l2_attr);
1052 /* Map all the pages. */
1053 num = round_page(size);
1055 if ((((va | pa) & PTE1_OFFSET) == 0) && (num >= PTE1_SIZE)) {
1056 pte1p = kern_pte1(va);
1057 pte1_store(pte1p, PTE1_KERN(pa, l1_prot, l1_attr));
1062 pte2p = pmap_preboot_vtopte2(va);
1063 pte2_store(pte2p, PTE2_KERN(pa, l2_prot, l2_attr));
1072 * Extract from the kernel page table the physical address
1073 * that is mapped by the given virtual address "va".
1076 pmap_kextract(vm_offset_t va)
1082 pte1 = pte1_load(kern_pte1(va));
1083 if (pte1_is_section(pte1)) {
1084 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1085 } else if (pte1_is_link(pte1)) {
1087 * We should beware of concurrent promotion that changes
1088 * pte1 at this point. However, it's not a problem as PT2
1089 * page is preserved by promotion in PT2TAB. So even if
1090 * it happens, using of PT2MAP is still safe.
1092 * QQQ: However, concurrent removing is a problem which
1093 * ends in abort on PT2MAP space. Locking must be used
1094 * to deal with this.
1096 pte2 = pte2_load(pt2map_entry(va));
1097 pa = pte2_pa(pte2) | (va & PTE2_OFFSET);
1100 panic("%s: va %#x pte1 %#x", __func__, va, pte1);
1106 * Extract from the kernel page table the physical address
1107 * that is mapped by the given virtual address "va". Also
1108 * return L2 page table entry which maps the address.
1110 * This is only intended to be used for panic dumps.
1113 pmap_dump_kextract(vm_offset_t va, pt2_entry_t *pte2p)
1119 pte1 = pte1_load(kern_pte1(va));
1120 if (pte1_is_section(pte1)) {
1121 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1122 pte2 = pa | ATTR_TO_L2(pte1) | PTE2_V;
1123 } else if (pte1_is_link(pte1)) {
1124 pte2 = pte2_load(pt2map_entry(va));
1135 /*****************************************************************************
1137 * PMAP second stage initialization and utility functions
1138 * for bootstrap epoch.
1140 * After pmap_bootstrap() is called, the following functions for
1141 * mappings can be used:
1143 * void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
1144 * void pmap_kremove(vm_offset_t va);
1145 * vm_offset_t pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end,
1148 * NOTE: This is not SMP coherent stage. And physical page allocation is not
1149 * allowed during this stage.
1151 *****************************************************************************/
1154 * Initialize kernel PMAP locks and lists, kernel_pmap itself, and
1155 * reserve various virtual spaces for temporary mappings.
1158 pmap_bootstrap(vm_offset_t firstaddr)
1160 pt2_entry_t *unused __unused;
1164 * Initialize the kernel pmap (which is statically allocated).
1166 PMAP_LOCK_INIT(kernel_pmap);
1167 kernel_l1pa = (vm_paddr_t)kern_pt1; /* for libkvm */
1168 kernel_pmap->pm_pt1 = kern_pt1;
1169 kernel_pmap->pm_pt2tab = kern_pt2tab;
1170 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1171 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1174 * Initialize the global pv list lock.
1176 rw_init(&pvh_global_lock, "pmap pv global");
1178 LIST_INIT(&allpmaps);
1181 * Request a spin mutex so that changes to allpmaps cannot be
1182 * preempted by smp_rendezvous_cpus().
1184 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
1185 mtx_lock_spin(&allpmaps_lock);
1186 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
1187 mtx_unlock_spin(&allpmaps_lock);
1190 * Reserve some special page table entries/VA space for temporary
1193 #define SYSMAP(c, p, v, n) do { \
1194 v = (c)pmap_preboot_reserve_pages(n); \
1195 p = pt2map_entry((vm_offset_t)v); \
1199 * Local CMAP1/CMAP2 are used for zeroing and copying pages.
1200 * Local CMAP2 is also used for data cache cleaning.
1203 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
1204 SYSMAP(caddr_t, pc->pc_cmap1_pte2p, pc->pc_cmap1_addr, 1);
1205 SYSMAP(caddr_t, pc->pc_cmap2_pte2p, pc->pc_cmap2_addr, 1);
1206 SYSMAP(vm_offset_t, pc->pc_qmap_pte2p, pc->pc_qmap_addr, 1);
1211 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS);
1214 * _tmppt is used for reading arbitrary physical pages via /dev/mem.
1216 SYSMAP(caddr_t, unused, _tmppt, 1);
1219 * PADDR1 and PADDR2 are used by pmap_pte2_quick() and pmap_pte2(),
1220 * respectively. PADDR3 is used by pmap_pte2_ddb().
1222 SYSMAP(pt2_entry_t *, PMAP1, PADDR1, 1);
1223 SYSMAP(pt2_entry_t *, PMAP2, PADDR2, 1);
1225 SYSMAP(pt2_entry_t *, PMAP3, PADDR3, 1);
1227 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
1230 * Note that in very short time in initarm(), we are going to
1231 * initialize phys_avail[] array and no further page allocation
1232 * can happen after that until vm subsystem will be initialized.
1234 kernel_vm_end_new = kernel_vm_end;
1235 virtual_end = vm_max_kernel_address;
1239 pmap_init_reserved_pages(void)
1248 * Skip if the mapping has already been initialized,
1249 * i.e. this is the BSP.
1251 if (pc->pc_cmap1_addr != 0)
1253 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
1254 pages = kva_alloc(PAGE_SIZE * 3);
1256 panic("%s: unable to allocate KVA", __func__);
1257 pc->pc_cmap1_pte2p = pt2map_entry(pages);
1258 pc->pc_cmap2_pte2p = pt2map_entry(pages + PAGE_SIZE);
1259 pc->pc_qmap_pte2p = pt2map_entry(pages + (PAGE_SIZE * 2));
1260 pc->pc_cmap1_addr = (caddr_t)pages;
1261 pc->pc_cmap2_addr = (caddr_t)(pages + PAGE_SIZE);
1262 pc->pc_qmap_addr = pages + (PAGE_SIZE * 2);
1265 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
1268 * The function can already be use in second initialization stage.
1269 * As such, the function DOES NOT call pmap_growkernel() where PT2
1270 * allocation can happen. So if used, be sure that PT2 for given
1271 * virtual address is allocated already!
1273 * Add a wired page to the kva.
1274 * Note: not SMP coherent.
1276 static __inline void
1277 pmap_kenter_prot_attr(vm_offset_t va, vm_paddr_t pa, uint32_t prot,
1283 pte1p = kern_pte1(va);
1284 if (!pte1_is_valid(pte1_load(pte1p))) { /* XXX - sections ?! */
1286 * This is a very low level function, so PT2 and particularly
1287 * PT2PG associated with given virtual address must be already
1288 * allocated. It's a pain mainly during pmap initialization
1289 * stage. However, called after pmap initialization with
1290 * virtual address not under kernel_vm_end will lead to
1293 if (!pte2_is_valid(pte2_load(kern_pt2tab_entry(va))))
1294 panic("%s: kernel PT2 not allocated!", __func__);
1297 pte2p = pt2map_entry(va);
1298 pte2_store(pte2p, PTE2_KERN(pa, prot, attr));
1302 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1305 pmap_kenter_prot_attr(va, pa, PTE2_AP_KRW, PTE2_ATTR_DEFAULT);
1309 * Remove a page from the kernel pagetables.
1310 * Note: not SMP coherent.
1313 pmap_kremove(vm_offset_t va)
1317 pte2p = pt2map_entry(va);
1322 * Share new kernel PT2PG with all pmaps.
1323 * The caller is responsible for maintaining TLB consistency.
1326 pmap_kenter_pt2tab(vm_offset_t va, pt2_entry_t npte2)
1331 mtx_lock_spin(&allpmaps_lock);
1332 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1333 pte2p = pmap_pt2tab_entry(pmap, va);
1334 pt2tab_store(pte2p, npte2);
1336 mtx_unlock_spin(&allpmaps_lock);
1340 * Share new kernel PTE1 with all pmaps.
1341 * The caller is responsible for maintaining TLB consistency.
1344 pmap_kenter_pte1(vm_offset_t va, pt1_entry_t npte1)
1349 mtx_lock_spin(&allpmaps_lock);
1350 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1351 pte1p = pmap_pte1(pmap, va);
1352 pte1_store(pte1p, npte1);
1354 mtx_unlock_spin(&allpmaps_lock);
1358 * Used to map a range of physical addresses into kernel
1359 * virtual address space.
1361 * The value passed in '*virt' is a suggested virtual address for
1362 * the mapping. Architectures which can support a direct-mapped
1363 * physical to virtual region can return the appropriate address
1364 * within that region, leaving '*virt' unchanged. Other
1365 * architectures should map the pages starting at '*virt' and
1366 * update '*virt' with the first usable address after the mapped
1369 * NOTE: Read the comments above pmap_kenter_prot_attr() as
1370 * the function is used herein!
1373 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1375 vm_offset_t va, sva;
1376 vm_paddr_t pte1_offset;
1378 uint32_t l1prot, l2prot;
1379 uint32_t l1attr, l2attr;
1381 PDEBUG(1, printf("%s: virt = %#x, start = %#x, end = %#x (size = %#x),"
1382 " prot = %d\n", __func__, *virt, start, end, end - start, prot));
1384 l2prot = (prot & VM_PROT_WRITE) ? PTE2_AP_KRW : PTE2_AP_KR;
1385 l2prot |= (prot & VM_PROT_EXECUTE) ? PTE2_X : PTE2_NX;
1386 l1prot = ATTR_TO_L1(l2prot);
1388 l2attr = PTE2_ATTR_DEFAULT;
1389 l1attr = ATTR_TO_L1(l2attr);
1393 * Does the physical address range's size and alignment permit at
1394 * least one section mapping to be created?
1396 pte1_offset = start & PTE1_OFFSET;
1397 if ((end - start) - ((PTE1_SIZE - pte1_offset) & PTE1_OFFSET) >=
1400 * Increase the starting virtual address so that its alignment
1401 * does not preclude the use of section mappings.
1403 if ((va & PTE1_OFFSET) < pte1_offset)
1404 va = pte1_trunc(va) + pte1_offset;
1405 else if ((va & PTE1_OFFSET) > pte1_offset)
1406 va = pte1_roundup(va) + pte1_offset;
1409 while (start < end) {
1410 if ((start & PTE1_OFFSET) == 0 && end - start >= PTE1_SIZE) {
1411 KASSERT((va & PTE1_OFFSET) == 0,
1412 ("%s: misaligned va %#x", __func__, va));
1413 npte1 = PTE1_KERN(start, l1prot, l1attr);
1414 pmap_kenter_pte1(va, npte1);
1418 pmap_kenter_prot_attr(va, start, l2prot, l2attr);
1423 tlb_flush_range(sva, va - sva);
1429 * Make a temporary mapping for a physical address.
1430 * This is only intended to be used for panic dumps.
1433 pmap_kenter_temporary(vm_paddr_t pa, int i)
1437 /* QQQ: 'i' should be less or equal to MAXDUMPPGS. */
1439 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
1440 pmap_kenter(va, pa);
1441 tlb_flush_local(va);
1442 return ((void *)crashdumpmap);
1446 /*************************************
1448 * TLB & cache maintenance routines.
1450 *************************************/
1453 * We inline these within pmap.c for speed.
1456 pmap_tlb_flush(pmap_t pmap, vm_offset_t va)
1459 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1464 pmap_tlb_flush_range(pmap_t pmap, vm_offset_t sva, vm_size_t size)
1467 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1468 tlb_flush_range(sva, size);
1472 * Abuse the pte2 nodes for unmapped kva to thread a kva freelist through.
1474 * - Must deal with pages in order to ensure that none of the PTE2_* bits
1475 * are ever set, PTE2_V in particular.
1476 * - Assumes we can write to pte2s without pte2_store() atomic ops.
1477 * - Assumes nothing will ever test these addresses for 0 to indicate
1478 * no mapping instead of correctly checking PTE2_V.
1479 * - Assumes a vm_offset_t will fit in a pte2 (true for arm).
1480 * Because PTE2_V is never set, there can be no mappings to invalidate.
1483 pmap_pte2list_alloc(vm_offset_t *head)
1490 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
1491 pte2p = pt2map_entry(va);
1494 panic("%s: va with PTE2_V set!", __func__);
1500 pmap_pte2list_free(vm_offset_t *head, vm_offset_t va)
1505 panic("%s: freeing va with PTE2_V set!", __func__);
1506 pte2p = pt2map_entry(va);
1507 *pte2p = *head; /* virtual! PTE2_V is 0 though */
1512 pmap_pte2list_init(vm_offset_t *head, void *base, int npages)
1518 for (i = npages - 1; i >= 0; i--) {
1519 va = (vm_offset_t)base + i * PAGE_SIZE;
1520 pmap_pte2list_free(head, va);
1524 /*****************************************************************************
1526 * PMAP third and final stage initialization.
1528 * After pmap_init() is called, PMAP subsystem is fully initialized.
1530 *****************************************************************************/
1532 SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
1534 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
1535 "Max number of PV entries");
1536 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
1537 "Page share factor per proc");
1539 static u_long nkpt2pg = NKPT2PG;
1540 SYSCTL_ULONG(_vm_pmap, OID_AUTO, nkpt2pg, CTLFLAG_RD,
1541 &nkpt2pg, 0, "Pre-allocated pages for kernel PT2s");
1543 static int sp_enabled = 1;
1544 SYSCTL_INT(_vm_pmap, OID_AUTO, sp_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
1545 &sp_enabled, 0, "Are large page mappings enabled?");
1547 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pte1, CTLFLAG_RD, 0,
1548 "1MB page mapping counters");
1550 static u_long pmap_pte1_demotions;
1551 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, demotions, CTLFLAG_RD,
1552 &pmap_pte1_demotions, 0, "1MB page demotions");
1554 static u_long pmap_pte1_mappings;
1555 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, mappings, CTLFLAG_RD,
1556 &pmap_pte1_mappings, 0, "1MB page mappings");
1558 static u_long pmap_pte1_p_failures;
1559 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, p_failures, CTLFLAG_RD,
1560 &pmap_pte1_p_failures, 0, "1MB page promotion failures");
1562 static u_long pmap_pte1_promotions;
1563 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, promotions, CTLFLAG_RD,
1564 &pmap_pte1_promotions, 0, "1MB page promotions");
1566 static u_long pmap_pte1_kern_demotions;
1567 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, kern_demotions, CTLFLAG_RD,
1568 &pmap_pte1_kern_demotions, 0, "1MB page kernel demotions");
1570 static u_long pmap_pte1_kern_promotions;
1571 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, kern_promotions, CTLFLAG_RD,
1572 &pmap_pte1_kern_promotions, 0, "1MB page kernel promotions");
1574 static __inline ttb_entry_t
1575 pmap_ttb_get(pmap_t pmap)
1578 return (vtophys(pmap->pm_pt1) | ttb_flags);
1582 * Initialize a vm_page's machine-dependent fields.
1585 * 1. Pages for L2 page tables are always not managed. So, pv_list and
1586 * pt2_wirecount can share same physical space. However, proper
1587 * initialization on a page alloc for page tables and reinitialization
1588 * on the page free must be ensured.
1591 pmap_page_init(vm_page_t m)
1594 TAILQ_INIT(&m->md.pv_list);
1595 pt2_wirecount_init(m);
1596 m->md.pat_mode = VM_MEMATTR_DEFAULT;
1600 * Virtualization for faster way how to zero whole page.
1602 static __inline void
1603 pagezero(void *page)
1606 bzero(page, PAGE_SIZE);
1610 * Zero L2 page table page.
1611 * Use same KVA as in pmap_zero_page().
1613 static __inline vm_paddr_t
1614 pmap_pt2pg_zero(vm_page_t m)
1616 pt2_entry_t *cmap2_pte2p;
1620 pa = VM_PAGE_TO_PHYS(m);
1623 * XXX: For now, we map whole page even if it's already zero,
1624 * to sync it even if the sync is only DSB.
1628 cmap2_pte2p = pc->pc_cmap2_pte2p;
1629 mtx_lock(&pc->pc_cmap_lock);
1630 if (pte2_load(cmap2_pte2p) != 0)
1631 panic("%s: CMAP2 busy", __func__);
1632 pte2_store(cmap2_pte2p, PTE2_KERN_NG(pa, PTE2_AP_KRW,
1633 vm_page_pte2_attr(m)));
1634 /* Even VM_ALLOC_ZERO request is only advisory. */
1635 if ((m->flags & PG_ZERO) == 0)
1636 pagezero(pc->pc_cmap2_addr);
1637 pte2_sync_range((pt2_entry_t *)pc->pc_cmap2_addr, PAGE_SIZE);
1638 pte2_clear(cmap2_pte2p);
1639 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
1642 * Unpin the thread before releasing the lock. Otherwise the thread
1643 * could be rescheduled while still bound to the current CPU, only
1644 * to unpin itself immediately upon resuming execution.
1647 mtx_unlock(&pc->pc_cmap_lock);
1653 * Init just allocated page as L2 page table(s) holder
1654 * and return its physical address.
1656 static __inline vm_paddr_t
1657 pmap_pt2pg_init(pmap_t pmap, vm_offset_t va, vm_page_t m)
1662 /* Check page attributes. */
1663 if (m->md.pat_mode != pt_memattr)
1664 pmap_page_set_memattr(m, pt_memattr);
1666 /* Zero page and init wire counts. */
1667 pa = pmap_pt2pg_zero(m);
1668 pt2_wirecount_init(m);
1671 * Map page to PT2MAP address space for given pmap.
1672 * Note that PT2MAP space is shared with all pmaps.
1674 if (pmap == kernel_pmap)
1675 pmap_kenter_pt2tab(va, PTE2_KPT(pa));
1677 pte2p = pmap_pt2tab_entry(pmap, va);
1678 pt2tab_store(pte2p, PTE2_KPT_NG(pa));
1685 * Initialize the pmap module.
1686 * Called by vm_init, to initialize any structures that the pmap
1687 * system needs to map virtual memory.
1693 pt2_entry_t *pte2p, pte2;
1694 u_int i, pte1_idx, pv_npg;
1696 PDEBUG(1, printf("%s: phys_start = %#x\n", __func__, PHYSADDR));
1699 * Initialize the vm page array entries for kernel pmap's
1700 * L2 page table pages allocated in advance.
1702 pte1_idx = pte1_index(KERNBASE - PT2MAP_SIZE);
1703 pte2p = kern_pt2tab_entry(KERNBASE - PT2MAP_SIZE);
1704 for (i = 0; i < nkpt2pg + NPG_IN_PT2TAB; i++, pte2p++) {
1708 pte2 = pte2_load(pte2p);
1709 KASSERT(pte2_is_valid(pte2), ("%s: no valid entry", __func__));
1712 m = PHYS_TO_VM_PAGE(pa);
1713 KASSERT(m >= vm_page_array &&
1714 m < &vm_page_array[vm_page_array_size],
1715 ("%s: L2 page table page is out of range", __func__));
1717 m->pindex = pte1_idx;
1719 pte1_idx += NPT2_IN_PG;
1723 * Initialize the address space (zone) for the pv entries. Set a
1724 * high water mark so that the system can recover from excessive
1725 * numbers of pv entries.
1727 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1728 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1729 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1730 pv_entry_max = roundup(pv_entry_max, _NPCPV);
1731 pv_entry_high_water = 9 * (pv_entry_max / 10);
1734 * Are large page mappings enabled?
1736 TUNABLE_INT_FETCH("vm.pmap.sp_enabled", &sp_enabled);
1738 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1739 ("%s: can't assign to pagesizes[1]", __func__));
1740 pagesizes[1] = PTE1_SIZE;
1744 * Calculate the size of the pv head table for sections.
1745 * Handle the possibility that "vm_phys_segs[...].end" is zero.
1746 * Note that the table is only for sections which could be promoted.
1748 first_managed_pa = pte1_trunc(vm_phys_segs[0].start);
1749 pv_npg = (pte1_trunc(vm_phys_segs[vm_phys_nsegs - 1].end - PAGE_SIZE)
1750 - first_managed_pa) / PTE1_SIZE + 1;
1753 * Allocate memory for the pv head table for sections.
1755 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1757 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
1759 for (i = 0; i < pv_npg; i++)
1760 TAILQ_INIT(&pv_table[i].pv_list);
1762 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
1763 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
1764 if (pv_chunkbase == NULL)
1765 panic("%s: not enough kvm for pv chunks", __func__);
1766 pmap_pte2list_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
1770 * Add a list of wired pages to the kva
1771 * this routine is only used for temporary
1772 * kernel mappings that do not need to have
1773 * page modification or references recorded.
1774 * Note that old mappings are simply written
1775 * over. The page *must* be wired.
1776 * Note: SMP coherent. Uses a ranged shootdown IPI.
1779 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1782 pt2_entry_t *epte2p, *pte2p, pte2;
1787 pte2p = pt2map_entry(sva);
1788 epte2p = pte2p + count;
1789 while (pte2p < epte2p) {
1791 pa = VM_PAGE_TO_PHYS(m);
1792 pte2 = pte2_load(pte2p);
1793 if ((pte2_pa(pte2) != pa) ||
1794 (pte2_attr(pte2) != vm_page_pte2_attr(m))) {
1796 pte2_store(pte2p, PTE2_KERN(pa, PTE2_AP_KRW,
1797 vm_page_pte2_attr(m)));
1801 if (__predict_false(anychanged))
1802 tlb_flush_range(sva, count * PAGE_SIZE);
1806 * This routine tears out page mappings from the
1807 * kernel -- it is meant only for temporary mappings.
1808 * Note: SMP coherent. Uses a ranged shootdown IPI.
1811 pmap_qremove(vm_offset_t sva, int count)
1816 while (count-- > 0) {
1820 tlb_flush_range(sva, va - sva);
1824 * Are we current address space or kernel?
1827 pmap_is_current(pmap_t pmap)
1830 return (pmap == kernel_pmap ||
1831 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace)));
1835 * If the given pmap is not the current or kernel pmap, the returned
1836 * pte2 must be released by passing it to pmap_pte2_release().
1838 static pt2_entry_t *
1839 pmap_pte2(pmap_t pmap, vm_offset_t va)
1842 vm_paddr_t pt2pg_pa;
1844 pte1 = pte1_load(pmap_pte1(pmap, va));
1845 if (pte1_is_section(pte1))
1846 panic("%s: attempt to map PTE1", __func__);
1847 if (pte1_is_link(pte1)) {
1848 /* Are we current address space or kernel? */
1849 if (pmap_is_current(pmap))
1850 return (pt2map_entry(va));
1851 /* Note that L2 page table size is not equal to PAGE_SIZE. */
1852 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
1853 mtx_lock(&PMAP2mutex);
1854 if (pte2_pa(pte2_load(PMAP2)) != pt2pg_pa) {
1855 pte2_store(PMAP2, PTE2_KPT(pt2pg_pa));
1856 tlb_flush((vm_offset_t)PADDR2);
1858 return (PADDR2 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
1864 * Releases a pte2 that was obtained from pmap_pte2().
1865 * Be prepared for the pte2p being NULL.
1867 static __inline void
1868 pmap_pte2_release(pt2_entry_t *pte2p)
1871 if ((pt2_entry_t *)(trunc_page((vm_offset_t)pte2p)) == PADDR2) {
1872 mtx_unlock(&PMAP2mutex);
1877 * Super fast pmap_pte2 routine best used when scanning
1878 * the pv lists. This eliminates many coarse-grained
1879 * invltlb calls. Note that many of the pv list
1880 * scans are across different pmaps. It is very wasteful
1881 * to do an entire tlb flush for checking a single mapping.
1883 * If the given pmap is not the current pmap, pvh_global_lock
1884 * must be held and curthread pinned to a CPU.
1886 static pt2_entry_t *
1887 pmap_pte2_quick(pmap_t pmap, vm_offset_t va)
1890 vm_paddr_t pt2pg_pa;
1892 pte1 = pte1_load(pmap_pte1(pmap, va));
1893 if (pte1_is_section(pte1))
1894 panic("%s: attempt to map PTE1", __func__);
1895 if (pte1_is_link(pte1)) {
1896 /* Are we current address space or kernel? */
1897 if (pmap_is_current(pmap))
1898 return (pt2map_entry(va));
1899 rw_assert(&pvh_global_lock, RA_WLOCKED);
1900 KASSERT(curthread->td_pinned > 0,
1901 ("%s: curthread not pinned", __func__));
1902 /* Note that L2 page table size is not equal to PAGE_SIZE. */
1903 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
1904 if (pte2_pa(pte2_load(PMAP1)) != pt2pg_pa) {
1905 pte2_store(PMAP1, PTE2_KPT(pt2pg_pa));
1907 PMAP1cpu = PCPU_GET(cpuid);
1909 tlb_flush_local((vm_offset_t)PADDR1);
1913 if (PMAP1cpu != PCPU_GET(cpuid)) {
1914 PMAP1cpu = PCPU_GET(cpuid);
1915 tlb_flush_local((vm_offset_t)PADDR1);
1920 return (PADDR1 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
1926 * Routine: pmap_extract
1928 * Extract the physical page address associated
1929 * with the given map/virtual_address pair.
1932 pmap_extract(pmap_t pmap, vm_offset_t va)
1939 pte1 = pte1_load(pmap_pte1(pmap, va));
1940 if (pte1_is_section(pte1))
1941 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1942 else if (pte1_is_link(pte1)) {
1943 pte2p = pmap_pte2(pmap, va);
1944 pa = pte2_pa(pte2_load(pte2p)) | (va & PTE2_OFFSET);
1945 pmap_pte2_release(pte2p);
1953 * Routine: pmap_extract_and_hold
1955 * Atomically extract and hold the physical page
1956 * with the given pmap and virtual address pair
1957 * if that mapping permits the given protection.
1960 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1962 vm_paddr_t pa, lockpa;
1964 pt2_entry_t pte2, *pte2p;
1971 pte1 = pte1_load(pmap_pte1(pmap, va));
1972 if (pte1_is_section(pte1)) {
1973 if (!(pte1 & PTE1_RO) || !(prot & VM_PROT_WRITE)) {
1974 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1975 if (vm_page_pa_tryrelock(pmap, pa, &lockpa))
1977 m = PHYS_TO_VM_PAGE(pa);
1980 } else if (pte1_is_link(pte1)) {
1981 pte2p = pmap_pte2(pmap, va);
1982 pte2 = pte2_load(pte2p);
1983 pmap_pte2_release(pte2p);
1984 if (pte2_is_valid(pte2) &&
1985 (!(pte2 & PTE2_RO) || !(prot & VM_PROT_WRITE))) {
1987 if (vm_page_pa_tryrelock(pmap, pa, &lockpa))
1989 m = PHYS_TO_VM_PAGE(pa);
1993 PA_UNLOCK_COND(lockpa);
1999 * Grow the number of kernel L2 page table entries, if needed.
2002 pmap_growkernel(vm_offset_t addr)
2005 vm_paddr_t pt2pg_pa, pt2_pa;
2009 PDEBUG(1, printf("%s: addr = %#x\n", __func__, addr));
2011 * All the time kernel_vm_end is first KVA for which underlying
2012 * L2 page table is either not allocated or linked from L1 page table
2013 * (not considering sections). Except for two possible cases:
2015 * (1) in the very beginning as long as pmap_growkernel() was
2016 * not called, it could be first unused KVA (which is not
2017 * rounded up to PTE1_SIZE),
2019 * (2) when all KVA space is mapped and kernel_map->max_offset
2020 * address is not rounded up to PTE1_SIZE. (For example,
2021 * it could be 0xFFFFFFFF.)
2023 kernel_vm_end = pte1_roundup(kernel_vm_end);
2024 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2025 addr = roundup2(addr, PTE1_SIZE);
2026 if (addr - 1 >= kernel_map->max_offset)
2027 addr = kernel_map->max_offset;
2028 while (kernel_vm_end < addr) {
2029 pte1 = pte1_load(kern_pte1(kernel_vm_end));
2030 if (pte1_is_valid(pte1)) {
2031 kernel_vm_end += PTE1_SIZE;
2032 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2033 kernel_vm_end = kernel_map->max_offset;
2040 * kernel_vm_end_new is used in pmap_pinit() when kernel
2041 * mappings are entered to new pmap all at once to avoid race
2042 * between pmap_kenter_pte1() and kernel_vm_end increase.
2043 * The same aplies to pmap_kenter_pt2tab().
2045 kernel_vm_end_new = kernel_vm_end + PTE1_SIZE;
2047 pte2 = pt2tab_load(kern_pt2tab_entry(kernel_vm_end));
2048 if (!pte2_is_valid(pte2)) {
2050 * Install new PT2s page into kernel PT2TAB.
2052 m = vm_page_alloc(NULL,
2053 pte1_index(kernel_vm_end) & ~PT2PG_MASK,
2054 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2055 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2057 panic("%s: no memory to grow kernel", __func__);
2059 * QQQ: To link all new L2 page tables from L1 page
2060 * table now and so pmap_kenter_pte1() them
2061 * at once together with pmap_kenter_pt2tab()
2062 * could be nice speed up. However,
2063 * pmap_growkernel() does not happen so often...
2064 * QQQ: The other TTBR is another option.
2066 pt2pg_pa = pmap_pt2pg_init(kernel_pmap, kernel_vm_end,
2069 pt2pg_pa = pte2_pa(pte2);
2071 pt2_pa = page_pt2pa(pt2pg_pa, pte1_index(kernel_vm_end));
2072 pmap_kenter_pte1(kernel_vm_end, PTE1_LINK(pt2_pa));
2074 kernel_vm_end = kernel_vm_end_new;
2075 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2076 kernel_vm_end = kernel_map->max_offset;
2083 kvm_size(SYSCTL_HANDLER_ARGS)
2085 unsigned long ksize = vm_max_kernel_address - KERNBASE;
2087 return (sysctl_handle_long(oidp, &ksize, 0, req));
2089 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2090 0, 0, kvm_size, "IU", "Size of KVM");
2093 kvm_free(SYSCTL_HANDLER_ARGS)
2095 unsigned long kfree = vm_max_kernel_address - kernel_vm_end;
2097 return (sysctl_handle_long(oidp, &kfree, 0, req));
2099 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2100 0, 0, kvm_free, "IU", "Amount of KVM free");
2102 /***********************************************
2104 * Pmap allocation/deallocation routines.
2106 ***********************************************/
2109 * Initialize the pmap for the swapper process.
2112 pmap_pinit0(pmap_t pmap)
2114 PDEBUG(1, printf("%s: pmap = %p\n", __func__, pmap));
2116 PMAP_LOCK_INIT(pmap);
2119 * Kernel page table directory and pmap stuff around is already
2120 * initialized, we are using it right now and here. So, finish
2121 * only PMAP structures initialization for process0 ...
2123 * Since the L1 page table and PT2TAB is shared with the kernel pmap,
2124 * which is already included in the list "allpmaps", this pmap does
2125 * not need to be inserted into that list.
2127 pmap->pm_pt1 = kern_pt1;
2128 pmap->pm_pt2tab = kern_pt2tab;
2129 CPU_ZERO(&pmap->pm_active);
2130 PCPU_SET(curpmap, pmap);
2131 TAILQ_INIT(&pmap->pm_pvchunk);
2132 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2133 CPU_SET(0, &pmap->pm_active);
2136 static __inline void
2137 pte1_copy_nosync(pt1_entry_t *spte1p, pt1_entry_t *dpte1p, vm_offset_t sva,
2142 idx = pte1_index(sva);
2143 count = (pte1_index(eva) - idx + 1) * sizeof(pt1_entry_t);
2144 bcopy(spte1p + idx, dpte1p + idx, count);
2147 static __inline void
2148 pt2tab_copy_nosync(pt2_entry_t *spte2p, pt2_entry_t *dpte2p, vm_offset_t sva,
2153 idx = pt2tab_index(sva);
2154 count = (pt2tab_index(eva) - idx + 1) * sizeof(pt2_entry_t);
2155 bcopy(spte2p + idx, dpte2p + idx, count);
2159 * Initialize a preallocated and zeroed pmap structure,
2160 * such as one in a vmspace structure.
2163 pmap_pinit(pmap_t pmap)
2167 vm_paddr_t pa, pt2tab_pa;
2170 PDEBUG(6, printf("%s: pmap = %p, pm_pt1 = %p\n", __func__, pmap,
2174 * No need to allocate L2 page table space yet but we do need
2175 * a valid L1 page table and PT2TAB table.
2177 * Install shared kernel mappings to these tables. It's a little
2178 * tricky as some parts of KVA are reserved for vectors, devices,
2179 * and whatever else. These parts are supposed to be above
2180 * vm_max_kernel_address. Thus two regions should be installed:
2182 * (1) <KERNBASE, kernel_vm_end),
2183 * (2) <vm_max_kernel_address, 0xFFFFFFFF>.
2185 * QQQ: The second region should be stable enough to be installed
2186 * only once in time when the tables are allocated.
2187 * QQQ: Maybe copy of both regions at once could be faster ...
2188 * QQQ: Maybe the other TTBR is an option.
2190 * Finally, install own PT2TAB table to these tables.
2193 if (pmap->pm_pt1 == NULL) {
2194 pmap->pm_pt1 = (pt1_entry_t *)kmem_alloc_contig(kernel_arena,
2195 NB_IN_PT1, M_NOWAIT | M_ZERO, 0, -1UL, NB_IN_PT1, 0,
2197 if (pmap->pm_pt1 == NULL)
2200 if (pmap->pm_pt2tab == NULL) {
2202 * QQQ: (1) PT2TAB must be contiguous. If PT2TAB is one page
2203 * only, what should be the only size for 32 bit systems,
2204 * then we could allocate it with vm_page_alloc() and all
2205 * the stuff needed as other L2 page table pages.
2206 * (2) Note that a process PT2TAB is special L2 page table
2207 * page. Its mapping in kernel_arena is permanent and can
2208 * be used no matter which process is current. Its mapping
2209 * in PT2MAP can be used only for current process.
2211 pmap->pm_pt2tab = (pt2_entry_t *)kmem_alloc_attr(kernel_arena,
2212 NB_IN_PT2TAB, M_NOWAIT | M_ZERO, 0, -1UL, pt_memattr);
2213 if (pmap->pm_pt2tab == NULL) {
2215 * QQQ: As struct pmap is allocated from UMA with
2216 * UMA_ZONE_NOFREE flag, it's important to leave
2217 * no allocation in pmap if initialization failed.
2219 kmem_free(kernel_arena, (vm_offset_t)pmap->pm_pt1,
2221 pmap->pm_pt1 = NULL;
2225 * QQQ: Each L2 page table page vm_page_t has pindex set to
2226 * pte1 index of virtual address mapped by this page.
2227 * It's not valid for non kernel PT2TABs themselves.
2228 * The pindex of these pages can not be altered because
2229 * of the way how they are allocated now. However, it
2230 * should not be a problem.
2234 mtx_lock_spin(&allpmaps_lock);
2236 * To avoid race with pmap_kenter_pte1() and pmap_kenter_pt2tab(),
2237 * kernel_vm_end_new is used here instead of kernel_vm_end.
2239 pte1_copy_nosync(kern_pt1, pmap->pm_pt1, KERNBASE,
2240 kernel_vm_end_new - 1);
2241 pte1_copy_nosync(kern_pt1, pmap->pm_pt1, vm_max_kernel_address,
2243 pt2tab_copy_nosync(kern_pt2tab, pmap->pm_pt2tab, KERNBASE,
2244 kernel_vm_end_new - 1);
2245 pt2tab_copy_nosync(kern_pt2tab, pmap->pm_pt2tab, vm_max_kernel_address,
2247 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
2248 mtx_unlock_spin(&allpmaps_lock);
2251 * Store PT2MAP PT2 pages (a.k.a. PT2TAB) in PT2TAB itself.
2252 * I.e. self reference mapping. The PT2TAB is private, however mapped
2253 * into shared PT2MAP space, so the mapping should be not global.
2255 pt2tab_pa = vtophys(pmap->pm_pt2tab);
2256 pte2p = pmap_pt2tab_entry(pmap, (vm_offset_t)PT2MAP);
2257 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE) {
2258 pt2tab_store(pte2p++, PTE2_KPT_NG(pa));
2261 /* Insert PT2MAP PT2s into pmap PT1. */
2262 pte1p = pmap_pte1(pmap, (vm_offset_t)PT2MAP);
2263 for (pa = pt2tab_pa, i = 0; i < NPT2_IN_PT2TAB; i++, pa += NB_IN_PT2) {
2264 pte1_store(pte1p++, PTE1_LINK(pa));
2268 * Now synchronize new mapping which was made above.
2270 pte1_sync_range(pmap->pm_pt1, NB_IN_PT1);
2271 pte2_sync_range(pmap->pm_pt2tab, NB_IN_PT2TAB);
2273 CPU_ZERO(&pmap->pm_active);
2274 TAILQ_INIT(&pmap->pm_pvchunk);
2275 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2282 pt2tab_user_is_empty(pt2_entry_t *tab)
2286 end = pt2tab_index(VM_MAXUSER_ADDRESS);
2287 for (i = 0; i < end; i++)
2288 if (tab[i] != 0) return (FALSE);
2293 * Release any resources held by the given physical map.
2294 * Called when a pmap initialized by pmap_pinit is being released.
2295 * Should only be called if the map contains no valid mappings.
2298 pmap_release(pmap_t pmap)
2301 vm_offset_t start, end;
2303 KASSERT(pmap->pm_stats.resident_count == 0,
2304 ("%s: pmap resident count %ld != 0", __func__,
2305 pmap->pm_stats.resident_count));
2306 KASSERT(pt2tab_user_is_empty(pmap->pm_pt2tab),
2307 ("%s: has allocated user PT2(s)", __func__));
2308 KASSERT(CPU_EMPTY(&pmap->pm_active),
2309 ("%s: pmap %p is active on some CPU(s)", __func__, pmap));
2311 mtx_lock_spin(&allpmaps_lock);
2312 LIST_REMOVE(pmap, pm_list);
2313 mtx_unlock_spin(&allpmaps_lock);
2316 start = pte1_index(KERNBASE) * sizeof(pt1_entry_t);
2317 end = (pte1_index(0xFFFFFFFF) + 1) * sizeof(pt1_entry_t);
2318 bzero((char *)pmap->pm_pt1 + start, end - start);
2320 start = pt2tab_index(KERNBASE) * sizeof(pt2_entry_t);
2321 end = (pt2tab_index(0xFFFFFFFF) + 1) * sizeof(pt2_entry_t);
2322 bzero((char *)pmap->pm_pt2tab + start, end - start);
2325 * We are leaving PT1 and PT2TAB allocated on released pmap,
2326 * so hopefully UMA vmspace_zone will always be inited with
2327 * UMA_ZONE_NOFREE flag.
2331 /*********************************************************
2333 * L2 table pages and their pages management routines.
2335 *********************************************************/
2338 * Virtual interface for L2 page table wire counting.
2340 * Each L2 page table in a page has own counter which counts a number of
2341 * valid mappings in a table. Global page counter counts mappings in all
2342 * tables in a page plus a single itself mapping in PT2TAB.
2344 * During a promotion we leave the associated L2 page table counter
2345 * untouched, so the table (strictly speaking a page which holds it)
2346 * is never freed if promoted.
2348 * If a page m->wire_count == 1 then no valid mappings exist in any L2 page
2349 * table in the page and the page itself is only mapped in PT2TAB.
2352 static __inline void
2353 pt2_wirecount_init(vm_page_t m)
2358 * Note: A page m is allocated with VM_ALLOC_WIRED flag and
2359 * m->wire_count should be already set correctly.
2360 * So, there is no need to set it again herein.
2362 for (i = 0; i < NPT2_IN_PG; i++)
2363 m->md.pt2_wirecount[i] = 0;
2366 static __inline void
2367 pt2_wirecount_inc(vm_page_t m, uint32_t pte1_idx)
2371 * Note: A just modificated pte2 (i.e. already allocated)
2372 * is acquiring one extra reference which must be
2373 * explicitly cleared. It influences the KASSERTs herein.
2374 * All L2 page tables in a page always belong to the same
2375 * pmap, so we allow only one extra reference for the page.
2377 KASSERT(m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] < (NPTE2_IN_PT2 + 1),
2378 ("%s: PT2 is overflowing ...", __func__));
2379 KASSERT(m->wire_count <= (NPTE2_IN_PG + 1),
2380 ("%s: PT2PG is overflowing ...", __func__));
2383 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]++;
2386 static __inline void
2387 pt2_wirecount_dec(vm_page_t m, uint32_t pte1_idx)
2390 KASSERT(m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] != 0,
2391 ("%s: PT2 is underflowing ...", __func__));
2392 KASSERT(m->wire_count > 1,
2393 ("%s: PT2PG is underflowing ...", __func__));
2396 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]--;
2399 static __inline void
2400 pt2_wirecount_set(vm_page_t m, uint32_t pte1_idx, uint16_t count)
2403 KASSERT(count <= NPTE2_IN_PT2,
2404 ("%s: invalid count %u", __func__, count));
2405 KASSERT(m->wire_count > m->md.pt2_wirecount[pte1_idx & PT2PG_MASK],
2406 ("%s: PT2PG corrupting (%u, %u) ...", __func__, m->wire_count,
2407 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]));
2409 m->wire_count -= m->md.pt2_wirecount[pte1_idx & PT2PG_MASK];
2410 m->wire_count += count;
2411 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] = count;
2413 KASSERT(m->wire_count <= (NPTE2_IN_PG + 1),
2414 ("%s: PT2PG is overflowed (%u) ...", __func__, m->wire_count));
2417 static __inline uint32_t
2418 pt2_wirecount_get(vm_page_t m, uint32_t pte1_idx)
2421 return (m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]);
2424 static __inline boolean_t
2425 pt2_is_empty(vm_page_t m, vm_offset_t va)
2428 return (m->md.pt2_wirecount[pte1_index(va) & PT2PG_MASK] == 0);
2431 static __inline boolean_t
2432 pt2_is_full(vm_page_t m, vm_offset_t va)
2435 return (m->md.pt2_wirecount[pte1_index(va) & PT2PG_MASK] ==
2439 static __inline boolean_t
2440 pt2pg_is_empty(vm_page_t m)
2443 return (m->wire_count == 1);
2447 * This routine is called if the L2 page table
2448 * is not mapped correctly.
2451 _pmap_allocpte2(pmap_t pmap, vm_offset_t va, u_int flags)
2457 vm_paddr_t pt2pg_pa, pt2_pa;
2459 pte1_idx = pte1_index(va);
2460 pte1p = pmap->pm_pt1 + pte1_idx;
2462 KASSERT(pte1_load(pte1p) == 0,
2463 ("%s: pm_pt1[%#x] is not zero: %#x", __func__, pte1_idx,
2466 pte2 = pt2tab_load(pmap_pt2tab_entry(pmap, va));
2467 if (!pte2_is_valid(pte2)) {
2469 * Install new PT2s page into pmap PT2TAB.
2471 m = vm_page_alloc(NULL, pte1_idx & ~PT2PG_MASK,
2472 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2474 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2476 rw_wunlock(&pvh_global_lock);
2478 rw_wlock(&pvh_global_lock);
2483 * Indicate the need to retry. While waiting,
2484 * the L2 page table page may have been allocated.
2488 pmap->pm_stats.resident_count++;
2489 pt2pg_pa = pmap_pt2pg_init(pmap, va, m);
2491 pt2pg_pa = pte2_pa(pte2);
2492 m = PHYS_TO_VM_PAGE(pt2pg_pa);
2495 pt2_wirecount_inc(m, pte1_idx);
2496 pt2_pa = page_pt2pa(pt2pg_pa, pte1_idx);
2497 pte1_store(pte1p, PTE1_LINK(pt2_pa));
2503 pmap_allocpte2(pmap_t pmap, vm_offset_t va, u_int flags)
2506 pt1_entry_t *pte1p, pte1;
2509 pte1_idx = pte1_index(va);
2511 pte1p = pmap->pm_pt1 + pte1_idx;
2512 pte1 = pte1_load(pte1p);
2515 * This supports switching from a 1MB page to a
2518 if (pte1_is_section(pte1)) {
2519 (void)pmap_demote_pte1(pmap, pte1p, va);
2521 * Reload pte1 after demotion.
2523 * Note: Demotion can even fail as either PT2 is not find for
2524 * the virtual address or PT2PG can not be allocated.
2526 pte1 = pte1_load(pte1p);
2530 * If the L2 page table page is mapped, we just increment the
2531 * hold count, and activate it.
2533 if (pte1_is_link(pte1)) {
2534 m = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
2535 pt2_wirecount_inc(m, pte1_idx);
2538 * Here if the PT2 isn't mapped, or if it has
2541 m = _pmap_allocpte2(pmap, va, flags);
2542 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2549 static __inline void
2550 pmap_free_zero_pages(struct spglist *free)
2554 while ((m = SLIST_FIRST(free)) != NULL) {
2555 SLIST_REMOVE_HEAD(free, plinks.s.ss);
2556 /* Preserve the page's PG_ZERO setting. */
2557 vm_page_free_toq(m);
2562 * Schedule the specified unused L2 page table page to be freed. Specifically,
2563 * add the page to the specified list of pages that will be released to the
2564 * physical memory manager after the TLB has been updated.
2566 static __inline void
2567 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free)
2571 * Put page on a list so that it is released after
2572 * *ALL* TLB shootdown is done
2575 pmap_zero_page_check(m);
2577 m->flags |= PG_ZERO;
2578 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2582 * Unwire L2 page tables page.
2585 pmap_unwire_pt2pg(pmap_t pmap, vm_offset_t va, vm_page_t m)
2587 pt1_entry_t *pte1p, opte1 __unused;
2591 KASSERT(pt2pg_is_empty(m),
2592 ("%s: pmap %p PT2PG %p wired", __func__, pmap, m));
2595 * Unmap all L2 page tables in the page from L1 page table.
2597 * QQQ: Individual L2 page tables (except the last one) can be unmapped
2598 * earlier. However, we are doing that this way.
2600 KASSERT(m->pindex == (pte1_index(va) & ~PT2PG_MASK),
2601 ("%s: pmap %p va %#x PT2PG %p bad index", __func__, pmap, va, m));
2602 pte1p = pmap->pm_pt1 + m->pindex;
2603 for (i = 0; i < NPT2_IN_PG; i++, pte1p++) {
2604 KASSERT(m->md.pt2_wirecount[i] == 0,
2605 ("%s: pmap %p PT2 %u (PG %p) wired", __func__, pmap, i, m));
2606 opte1 = pte1_load(pte1p);
2607 if (pte1_is_link(opte1)) {
2610 * Flush intermediate TLB cache.
2612 pmap_tlb_flush(pmap, (m->pindex + i) << PTE1_SHIFT);
2616 KASSERT((opte1 == 0) || pte1_is_section(opte1),
2617 ("%s: pmap %p va %#x bad pte1 %x at %u", __func__,
2618 pmap, va, opte1, i));
2623 * Unmap the page from PT2TAB.
2625 pte2p = pmap_pt2tab_entry(pmap, va);
2626 (void)pt2tab_load_clear(pte2p);
2627 pmap_tlb_flush(pmap, pt2map_pt2pg(va));
2630 pmap->pm_stats.resident_count--;
2633 * This is a release store so that the ordinary store unmapping
2634 * the L2 page table page is globally performed before TLB shoot-
2637 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1);
2641 * Decrements a L2 page table page's wire count, which is used to record the
2642 * number of valid page table entries within the page. If the wire count
2643 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2644 * page table page was unmapped and FALSE otherwise.
2646 static __inline boolean_t
2647 pmap_unwire_pt2(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2649 pt2_wirecount_dec(m, pte1_index(va));
2650 if (pt2pg_is_empty(m)) {
2652 * QQQ: Wire count is zero, so whole page should be zero and
2653 * we can set PG_ZERO flag to it.
2654 * Note that when promotion is enabled, it takes some
2655 * more efforts. See pmap_unwire_pt2_all() below.
2657 pmap_unwire_pt2pg(pmap, va, m);
2658 pmap_add_delayed_free_list(m, free);
2665 * Drop a L2 page table page's wire count at once, which is used to record
2666 * the number of valid L2 page table entries within the page. If the wire
2667 * count drops to zero, then the L2 page table page is unmapped.
2669 static __inline void
2670 pmap_unwire_pt2_all(pmap_t pmap, vm_offset_t va, vm_page_t m,
2671 struct spglist *free)
2673 u_int pte1_idx = pte1_index(va);
2675 KASSERT(m->pindex == (pte1_idx & ~PT2PG_MASK),
2676 ("%s: PT2 page's pindex is wrong", __func__));
2677 KASSERT(m->wire_count > pt2_wirecount_get(m, pte1_idx),
2678 ("%s: bad pt2 wire count %u > %u", __func__, m->wire_count,
2679 pt2_wirecount_get(m, pte1_idx)));
2682 * It's possible that the L2 page table was never used.
2683 * It happened in case that a section was created without promotion.
2685 if (pt2_is_full(m, va)) {
2686 pt2_wirecount_set(m, pte1_idx, 0);
2689 * QQQ: We clear L2 page table now, so when L2 page table page
2690 * is going to be freed, we can set it PG_ZERO flag ...
2691 * This function is called only on section mappings, so
2692 * hopefully it's not to big overload.
2694 * XXX: If pmap is current, existing PT2MAP mapping could be
2697 pmap_zero_page_area(m, page_pt2off(pte1_idx), NB_IN_PT2);
2701 KASSERT(pt2_is_empty(m, va), ("%s: PT2 is not empty (%u)",
2702 __func__, pt2_wirecount_get(m, pte1_idx)));
2704 if (pt2pg_is_empty(m)) {
2705 pmap_unwire_pt2pg(pmap, va, m);
2706 pmap_add_delayed_free_list(m, free);
2711 * After removing a L2 page table entry, this routine is used to
2712 * conditionally free the page, and manage the hold/wire counts.
2715 pmap_unuse_pt2(pmap_t pmap, vm_offset_t va, struct spglist *free)
2720 if (va >= VM_MAXUSER_ADDRESS)
2722 pte1 = pte1_load(pmap_pte1(pmap, va));
2723 mpte = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
2724 return (pmap_unwire_pt2(pmap, va, mpte, free));
2727 /*************************************
2729 * Page management routines.
2731 *************************************/
2733 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2734 CTASSERT(_NPCM == 11);
2735 CTASSERT(_NPCPV == 336);
2737 static __inline struct pv_chunk *
2738 pv_to_chunk(pv_entry_t pv)
2741 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2744 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2746 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2747 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2749 static const uint32_t pc_freemask[_NPCM] = {
2750 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2751 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2752 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2753 PC_FREE0_9, PC_FREE10
2756 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2757 "Current number of pv entries");
2760 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2762 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2763 "Current number of pv entry chunks");
2764 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2765 "Current number of pv entry chunks allocated");
2766 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2767 "Current number of pv entry chunks frees");
2768 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail,
2769 0, "Number of times tried to get a chunk page but failed.");
2771 static long pv_entry_frees, pv_entry_allocs;
2772 static int pv_entry_spare;
2774 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2775 "Current number of pv entry frees");
2776 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs,
2777 0, "Current number of pv entry allocs");
2778 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2779 "Current number of spare pv entries");
2783 * Is given page managed?
2785 static __inline bool
2786 is_managed(vm_paddr_t pa)
2790 m = PHYS_TO_VM_PAGE(pa);
2793 return ((m->oflags & VPO_UNMANAGED) == 0);
2796 static __inline bool
2797 pte1_is_managed(pt1_entry_t pte1)
2800 return (is_managed(pte1_pa(pte1)));
2803 static __inline bool
2804 pte2_is_managed(pt2_entry_t pte2)
2807 return (is_managed(pte2_pa(pte2)));
2811 * We are in a serious low memory condition. Resort to
2812 * drastic measures to free some pages so we can allocate
2813 * another pv entry chunk.
2816 pmap_pv_reclaim(pmap_t locked_pmap)
2819 struct pv_chunk *pc;
2820 struct md_page *pvh;
2823 pt2_entry_t *pte2p, tpte2;
2827 struct spglist free;
2829 int bit, field, freed;
2831 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2835 TAILQ_INIT(&newtail);
2836 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2837 SLIST_EMPTY(&free))) {
2838 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2839 if (pmap != pc->pc_pmap) {
2841 if (pmap != locked_pmap)
2845 /* Avoid deadlock and lock recursion. */
2846 if (pmap > locked_pmap)
2848 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2850 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2856 * Destroy every non-wired, 4 KB page mapping in the chunk.
2859 for (field = 0; field < _NPCM; field++) {
2860 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2861 inuse != 0; inuse &= ~(1UL << bit)) {
2862 bit = ffs(inuse) - 1;
2863 pv = &pc->pc_pventry[field * 32 + bit];
2865 pte1p = pmap_pte1(pmap, va);
2866 if (pte1_is_section(pte1_load(pte1p)))
2868 pte2p = pmap_pte2(pmap, va);
2869 tpte2 = pte2_load(pte2p);
2870 if ((tpte2 & PTE2_W) == 0)
2871 tpte2 = pte2_load_clear(pte2p);
2872 pmap_pte2_release(pte2p);
2873 if ((tpte2 & PTE2_W) != 0)
2876 ("pmap_pv_reclaim: pmap %p va %#x zero pte",
2878 pmap_tlb_flush(pmap, va);
2879 m = PHYS_TO_VM_PAGE(pte2_pa(tpte2));
2880 if (pte2_is_dirty(tpte2))
2882 if ((tpte2 & PTE2_A) != 0)
2883 vm_page_aflag_set(m, PGA_REFERENCED);
2884 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2885 if (TAILQ_EMPTY(&m->md.pv_list) &&
2886 (m->flags & PG_FICTITIOUS) == 0) {
2887 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2888 if (TAILQ_EMPTY(&pvh->pv_list)) {
2889 vm_page_aflag_clear(m,
2893 pc->pc_map[field] |= 1UL << bit;
2894 pmap_unuse_pt2(pmap, va, &free);
2899 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2902 /* Every freed mapping is for a 4 KB page. */
2903 pmap->pm_stats.resident_count -= freed;
2904 PV_STAT(pv_entry_frees += freed);
2905 PV_STAT(pv_entry_spare += freed);
2906 pv_entry_count -= freed;
2907 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2908 for (field = 0; field < _NPCM; field++)
2909 if (pc->pc_map[field] != pc_freemask[field]) {
2910 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2912 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2915 * One freed pv entry in locked_pmap is
2918 if (pmap == locked_pmap)
2922 if (field == _NPCM) {
2923 PV_STAT(pv_entry_spare -= _NPCPV);
2924 PV_STAT(pc_chunk_count--);
2925 PV_STAT(pc_chunk_frees++);
2926 /* Entire chunk is free; return it. */
2927 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2928 pmap_qremove((vm_offset_t)pc, 1);
2929 pmap_pte2list_free(&pv_vafree, (vm_offset_t)pc);
2934 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2936 if (pmap != locked_pmap)
2939 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2940 m_pc = SLIST_FIRST(&free);
2941 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2942 /* Recycle a freed page table page. */
2943 m_pc->wire_count = 1;
2944 atomic_add_int(&vm_cnt.v_wire_count, 1);
2946 pmap_free_zero_pages(&free);
2951 free_pv_chunk(struct pv_chunk *pc)
2955 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2956 PV_STAT(pv_entry_spare -= _NPCPV);
2957 PV_STAT(pc_chunk_count--);
2958 PV_STAT(pc_chunk_frees++);
2959 /* entire chunk is free, return it */
2960 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2961 pmap_qremove((vm_offset_t)pc, 1);
2962 vm_page_unwire(m, PQ_NONE);
2964 pmap_pte2list_free(&pv_vafree, (vm_offset_t)pc);
2968 * Free the pv_entry back to the free list.
2971 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2973 struct pv_chunk *pc;
2974 int idx, field, bit;
2976 rw_assert(&pvh_global_lock, RA_WLOCKED);
2977 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2978 PV_STAT(pv_entry_frees++);
2979 PV_STAT(pv_entry_spare++);
2981 pc = pv_to_chunk(pv);
2982 idx = pv - &pc->pc_pventry[0];
2985 pc->pc_map[field] |= 1ul << bit;
2986 for (idx = 0; idx < _NPCM; idx++)
2987 if (pc->pc_map[idx] != pc_freemask[idx]) {
2989 * 98% of the time, pc is already at the head of the
2990 * list. If it isn't already, move it to the head.
2992 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2994 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2995 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
3000 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3005 * Get a new pv_entry, allocating a block from the system
3009 get_pv_entry(pmap_t pmap, boolean_t try)
3011 static const struct timeval printinterval = { 60, 0 };
3012 static struct timeval lastprint;
3015 struct pv_chunk *pc;
3018 rw_assert(&pvh_global_lock, RA_WLOCKED);
3019 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3020 PV_STAT(pv_entry_allocs++);
3022 if (pv_entry_count > pv_entry_high_water)
3023 if (ratecheck(&lastprint, &printinterval))
3024 printf("Approaching the limit on PV entries, consider "
3025 "increasing either the vm.pmap.shpgperproc or the "
3026 "vm.pmap.pv_entry_max tunable.\n");
3028 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3030 for (field = 0; field < _NPCM; field++) {
3031 if (pc->pc_map[field]) {
3032 bit = ffs(pc->pc_map[field]) - 1;
3036 if (field < _NPCM) {
3037 pv = &pc->pc_pventry[field * 32 + bit];
3038 pc->pc_map[field] &= ~(1ul << bit);
3039 /* If this was the last item, move it to tail */
3040 for (field = 0; field < _NPCM; field++)
3041 if (pc->pc_map[field] != 0) {
3042 PV_STAT(pv_entry_spare--);
3043 return (pv); /* not full, return */
3045 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3046 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3047 PV_STAT(pv_entry_spare--);
3052 * Access to the pte2list "pv_vafree" is synchronized by the pvh
3053 * global lock. If "pv_vafree" is currently non-empty, it will
3054 * remain non-empty until pmap_pte2list_alloc() completes.
3056 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3057 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
3060 PV_STAT(pc_chunk_tryfail++);
3063 m = pmap_pv_reclaim(pmap);
3067 PV_STAT(pc_chunk_count++);
3068 PV_STAT(pc_chunk_allocs++);
3069 pc = (struct pv_chunk *)pmap_pte2list_alloc(&pv_vafree);
3070 pmap_qenter((vm_offset_t)pc, &m, 1);
3072 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
3073 for (field = 1; field < _NPCM; field++)
3074 pc->pc_map[field] = pc_freemask[field];
3075 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
3076 pv = &pc->pc_pventry[0];
3077 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3078 PV_STAT(pv_entry_spare += _NPCPV - 1);
3083 * Create a pv entry for page at pa for
3087 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
3091 rw_assert(&pvh_global_lock, RA_WLOCKED);
3092 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3093 pv = get_pv_entry(pmap, FALSE);
3095 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3098 static __inline pv_entry_t
3099 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3103 rw_assert(&pvh_global_lock, RA_WLOCKED);
3104 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3105 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3106 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3114 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3118 pv = pmap_pvh_remove(pvh, pmap, va);
3119 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3120 free_pv_entry(pmap, pv);
3124 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
3126 struct md_page *pvh;
3128 rw_assert(&pvh_global_lock, RA_WLOCKED);
3129 pmap_pvh_free(&m->md, pmap, va);
3130 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
3131 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3132 if (TAILQ_EMPTY(&pvh->pv_list))
3133 vm_page_aflag_clear(m, PGA_WRITEABLE);
3138 pmap_pv_demote_pte1(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3140 struct md_page *pvh;
3142 vm_offset_t va_last;
3145 rw_assert(&pvh_global_lock, RA_WLOCKED);
3146 KASSERT((pa & PTE1_OFFSET) == 0,
3147 ("pmap_pv_demote_pte1: pa is not 1mpage aligned"));
3150 * Transfer the 1mpage's pv entry for this mapping to the first
3153 pvh = pa_to_pvh(pa);
3154 va = pte1_trunc(va);
3155 pv = pmap_pvh_remove(pvh, pmap, va);
3156 KASSERT(pv != NULL, ("pmap_pv_demote_pte1: pv not found"));
3157 m = PHYS_TO_VM_PAGE(pa);
3158 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3159 /* Instantiate the remaining NPTE2_IN_PT2 - 1 pv entries. */
3160 va_last = va + PTE1_SIZE - PAGE_SIZE;
3163 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3164 ("pmap_pv_demote_pte1: page %p is not managed", m));
3166 pmap_insert_entry(pmap, va, m);
3167 } while (va < va_last);
3170 #if VM_NRESERVLEVEL > 0
3172 pmap_pv_promote_pte1(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3174 struct md_page *pvh;
3176 vm_offset_t va_last;
3179 rw_assert(&pvh_global_lock, RA_WLOCKED);
3180 KASSERT((pa & PTE1_OFFSET) == 0,
3181 ("pmap_pv_promote_pte1: pa is not 1mpage aligned"));
3184 * Transfer the first page's pv entry for this mapping to the
3185 * 1mpage's pv list. Aside from avoiding the cost of a call
3186 * to get_pv_entry(), a transfer avoids the possibility that
3187 * get_pv_entry() calls pmap_pv_reclaim() and that pmap_pv_reclaim()
3188 * removes one of the mappings that is being promoted.
3190 m = PHYS_TO_VM_PAGE(pa);
3191 va = pte1_trunc(va);
3192 pv = pmap_pvh_remove(&m->md, pmap, va);
3193 KASSERT(pv != NULL, ("pmap_pv_promote_pte1: pv not found"));
3194 pvh = pa_to_pvh(pa);
3195 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3196 /* Free the remaining NPTE2_IN_PT2 - 1 pv entries. */
3197 va_last = va + PTE1_SIZE - PAGE_SIZE;
3201 pmap_pvh_free(&m->md, pmap, va);
3202 } while (va < va_last);
3207 * Conditionally create a pv entry.
3210 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
3214 rw_assert(&pvh_global_lock, RA_WLOCKED);
3215 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3216 if (pv_entry_count < pv_entry_high_water &&
3217 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
3219 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3226 * Create the pv entries for each of the pages within a section.
3229 pmap_pv_insert_pte1(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3231 struct md_page *pvh;
3234 rw_assert(&pvh_global_lock, RA_WLOCKED);
3235 if (pv_entry_count < pv_entry_high_water &&
3236 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
3238 pvh = pa_to_pvh(pa);
3239 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3246 pmap_tlb_flush_pte1(pmap_t pmap, vm_offset_t va, pt1_entry_t npte1)
3249 /* Kill all the small mappings or the big one only. */
3250 if (pte1_is_section(npte1))
3251 pmap_tlb_flush_range(pmap, pte1_trunc(va), PTE1_SIZE);
3253 pmap_tlb_flush(pmap, pte1_trunc(va));
3257 * Update kernel pte1 on all pmaps.
3259 * The following function is called only on one cpu with disabled interrupts.
3260 * In SMP case, smp_rendezvous_cpus() is used to stop other cpus. This way
3261 * nobody can invoke explicit hardware table walk during the update of pte1.
3262 * Unsolicited hardware table walk can still happen, invoked by speculative
3263 * data or instruction prefetch or even by speculative hardware table walk.
3265 * The break-before-make approach should be implemented here. However, it's
3266 * not so easy to do that for kernel mappings as it would be unhappy to unmap
3267 * itself unexpectedly but voluntarily.
3270 pmap_update_pte1_kernel(vm_offset_t va, pt1_entry_t npte1)
3276 * Get current pmap. Interrupts should be disabled here
3277 * so PCPU_GET() is done atomically.
3279 pmap = PCPU_GET(curpmap);
3284 * (1) Change pte1 on current pmap.
3285 * (2) Flush all obsolete TLB entries on current CPU.
3286 * (3) Change pte1 on all pmaps.
3287 * (4) Flush all obsolete TLB entries on all CPUs in SMP case.
3290 pte1p = pmap_pte1(pmap, va);
3291 pte1_store(pte1p, npte1);
3293 /* Kill all the small mappings or the big one only. */
3294 if (pte1_is_section(npte1)) {
3295 pmap_pte1_kern_promotions++;
3296 tlb_flush_range_local(pte1_trunc(va), PTE1_SIZE);
3298 pmap_pte1_kern_demotions++;
3299 tlb_flush_local(pte1_trunc(va));
3303 * In SMP case, this function is called when all cpus are at smp
3304 * rendezvous, so there is no need to use 'allpmaps_lock' lock here.
3305 * In UP case, the function is called with this lock locked.
3307 LIST_FOREACH(pmap, &allpmaps, pm_list) {
3308 pte1p = pmap_pte1(pmap, va);
3309 pte1_store(pte1p, npte1);
3313 /* Kill all the small mappings or the big one only. */
3314 if (pte1_is_section(npte1))
3315 tlb_flush_range(pte1_trunc(va), PTE1_SIZE);
3317 tlb_flush(pte1_trunc(va));
3322 struct pte1_action {
3325 u_int update; /* CPU that updates the PTE1 */
3329 pmap_update_pte1_action(void *arg)
3331 struct pte1_action *act = arg;
3333 if (act->update == PCPU_GET(cpuid))
3334 pmap_update_pte1_kernel(act->va, act->npte1);
3338 * Change pte1 on current pmap.
3339 * Note that kernel pte1 must be changed on all pmaps.
3341 * According to the architecture reference manual published by ARM,
3342 * the behaviour is UNPREDICTABLE when two or more TLB entries map the same VA.
3343 * According to this manual, UNPREDICTABLE behaviours must never happen in
3344 * a viable system. In contrast, on x86 processors, it is not specified which
3345 * TLB entry mapping the virtual address will be used, but the MMU doesn't
3346 * generate a bogus translation the way it does on Cortex-A8 rev 2 (Beaglebone
3349 * It's a problem when either promotion or demotion is being done. The pte1
3350 * update and appropriate TLB flush must be done atomically in general.
3353 pmap_change_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va,
3357 if (pmap == kernel_pmap) {
3358 struct pte1_action act;
3363 act.update = PCPU_GET(cpuid);
3364 smp_rendezvous_cpus(all_cpus, smp_no_rendezvous_barrier,
3365 pmap_update_pte1_action, NULL, &act);
3371 * Use break-before-make approach for changing userland
3372 * mappings. It can cause L1 translation aborts on other
3373 * cores in SMP case. So, special treatment is implemented
3374 * in pmap_fault(). To reduce the likelihood that another core
3375 * will be affected by the broken mapping, disable interrupts
3376 * until the mapping change is completed.
3378 cspr = disable_interrupts(PSR_I | PSR_F);
3380 pmap_tlb_flush_pte1(pmap, va, npte1);
3381 pte1_store(pte1p, npte1);
3382 restore_interrupts(cspr);
3387 pmap_change_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va,
3391 if (pmap == kernel_pmap) {
3392 mtx_lock_spin(&allpmaps_lock);
3393 pmap_update_pte1_kernel(va, npte1);
3394 mtx_unlock_spin(&allpmaps_lock);
3399 * Use break-before-make approach for changing userland
3400 * mappings. It's absolutely safe in UP case when interrupts
3403 cspr = disable_interrupts(PSR_I | PSR_F);
3405 pmap_tlb_flush_pte1(pmap, va, npte1);
3406 pte1_store(pte1p, npte1);
3407 restore_interrupts(cspr);
3412 #if VM_NRESERVLEVEL > 0
3414 * Tries to promote the NPTE2_IN_PT2, contiguous 4KB page mappings that are
3415 * within a single page table page (PT2) to a single 1MB page mapping.
3416 * For promotion to occur, two conditions must be met: (1) the 4KB page
3417 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3418 * mappings must have identical characteristics.
3420 * Managed (PG_MANAGED) mappings within the kernel address space are not
3421 * promoted. The reason is that kernel PTE1s are replicated in each pmap but
3422 * pmap_remove_write(), pmap_clear_modify(), and pmap_clear_reference() only
3423 * read the PTE1 from the kernel pmap.
3426 pmap_promote_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3429 pt2_entry_t *fpte2p, fpte2, fpte2_fav;
3430 pt2_entry_t *pte2p, pte2;
3431 vm_offset_t pteva __unused;
3432 vm_page_t m __unused;
3434 PDEBUG(6, printf("%s(%p): try for va %#x pte1 %#x at %p\n", __func__,
3435 pmap, va, pte1_load(pte1p), pte1p));
3437 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3440 * Examine the first PTE2 in the specified PT2. Abort if this PTE2 is
3441 * either invalid, unused, or does not map the first 4KB physical page
3442 * within a 1MB page.
3444 fpte2p = pmap_pte2_quick(pmap, pte1_trunc(va));
3445 fpte2 = pte2_load(fpte2p);
3446 if ((fpte2 & ((PTE2_FRAME & PTE1_OFFSET) | PTE2_A | PTE2_V)) !=
3447 (PTE2_A | PTE2_V)) {
3448 pmap_pte1_p_failures++;
3449 CTR3(KTR_PMAP, "%s: failure(1) for va %#x in pmap %p",
3450 __func__, va, pmap);
3453 if (pte2_is_managed(fpte2) && pmap == kernel_pmap) {
3454 pmap_pte1_p_failures++;
3455 CTR3(KTR_PMAP, "%s: failure(2) for va %#x in pmap %p",
3456 __func__, va, pmap);
3459 if ((fpte2 & (PTE2_NM | PTE2_RO)) == PTE2_NM) {
3461 * When page is not modified, PTE2_RO can be set without
3462 * a TLB invalidation.
3465 pte2_store(fpte2p, fpte2);
3469 * Examine each of the other PTE2s in the specified PT2. Abort if this
3470 * PTE2 maps an unexpected 4KB physical page or does not have identical
3471 * characteristics to the first PTE2.
3473 fpte2_fav = (fpte2 & (PTE2_FRAME | PTE2_A | PTE2_V));
3474 fpte2_fav += PTE1_SIZE - PTE2_SIZE; /* examine from the end */
3475 for (pte2p = fpte2p + NPTE2_IN_PT2 - 1; pte2p > fpte2p; pte2p--) {
3476 pte2 = pte2_load(pte2p);
3477 if ((pte2 & (PTE2_FRAME | PTE2_A | PTE2_V)) != fpte2_fav) {
3478 pmap_pte1_p_failures++;
3479 CTR3(KTR_PMAP, "%s: failure(3) for va %#x in pmap %p",
3480 __func__, va, pmap);
3483 if ((pte2 & (PTE2_NM | PTE2_RO)) == PTE2_NM) {
3485 * When page is not modified, PTE2_RO can be set
3486 * without a TLB invalidation. See note above.
3489 pte2_store(pte2p, pte2);
3490 pteva = pte1_trunc(va) | (pte2 & PTE1_OFFSET &
3492 CTR3(KTR_PMAP, "%s: protect for va %#x in pmap %p",
3493 __func__, pteva, pmap);
3495 if ((pte2 & PTE2_PROMOTE) != (fpte2 & PTE2_PROMOTE)) {
3496 pmap_pte1_p_failures++;
3497 CTR3(KTR_PMAP, "%s: failure(4) for va %#x in pmap %p",
3498 __func__, va, pmap);
3502 fpte2_fav -= PTE2_SIZE;
3505 * The page table page in its current state will stay in PT2TAB
3506 * until the PTE1 mapping the section is demoted by pmap_demote_pte1()
3507 * or destroyed by pmap_remove_pte1().
3509 * Note that L2 page table size is not equal to PAGE_SIZE.
3511 m = PHYS_TO_VM_PAGE(trunc_page(pte1_link_pa(pte1_load(pte1p))));
3512 KASSERT(m >= vm_page_array && m < &vm_page_array[vm_page_array_size],
3513 ("%s: PT2 page is out of range", __func__));
3514 KASSERT(m->pindex == (pte1_index(va) & ~PT2PG_MASK),
3515 ("%s: PT2 page's pindex is wrong", __func__));
3518 * Get pte1 from pte2 format.
3520 npte1 = (fpte2 & PTE1_FRAME) | ATTR_TO_L1(fpte2) | PTE1_V;
3523 * Promote the pv entries.
3525 if (pte2_is_managed(fpte2))
3526 pmap_pv_promote_pte1(pmap, va, pte1_pa(npte1));
3529 * Promote the mappings.
3531 pmap_change_pte1(pmap, pte1p, va, npte1);
3533 pmap_pte1_promotions++;
3534 CTR3(KTR_PMAP, "%s: success for va %#x in pmap %p",
3535 __func__, va, pmap);
3537 PDEBUG(6, printf("%s(%p): success for va %#x pte1 %#x(%#x) at %p\n",
3538 __func__, pmap, va, npte1, pte1_load(pte1p), pte1p));
3540 #endif /* VM_NRESERVLEVEL > 0 */
3543 * Zero L2 page table page.
3545 static __inline void
3546 pmap_clear_pt2(pt2_entry_t *fpte2p)
3550 for (pte2p = fpte2p; pte2p < fpte2p + NPTE2_IN_PT2; pte2p++)
3556 * Removes a 1MB page mapping from the kernel pmap.
3559 pmap_remove_kernel_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3563 pt2_entry_t *fpte2p;
3566 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3567 m = pmap_pt2_page(pmap, va);
3570 * QQQ: Is this function called only on promoted pte1?
3571 * We certainly do section mappings directly
3572 * (without promotion) in kernel !!!
3574 panic("%s: missing pt2 page", __func__);
3576 pte1_idx = pte1_index(va);
3579 * Initialize the L2 page table.
3581 fpte2p = page_pt2(pt2map_pt2pg(va), pte1_idx);
3582 pmap_clear_pt2(fpte2p);
3585 * Remove the mapping.
3587 pt2_pa = page_pt2pa(VM_PAGE_TO_PHYS(m), pte1_idx);
3588 pmap_kenter_pte1(va, PTE1_LINK(pt2_pa));
3591 * QQQ: We do not need to invalidate PT2MAP mapping
3592 * as we did not change it. I.e. the L2 page table page
3593 * was and still is mapped the same way.
3598 * Do the things to unmap a section in a process
3601 pmap_remove_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t sva,
3602 struct spglist *free)
3605 struct md_page *pvh;
3606 vm_offset_t eva, va;
3609 PDEBUG(6, printf("%s(%p): va %#x pte1 %#x at %p\n", __func__, pmap, sva,
3610 pte1_load(pte1p), pte1p));
3612 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3613 KASSERT((sva & PTE1_OFFSET) == 0,
3614 ("%s: sva is not 1mpage aligned", __func__));
3617 * Clear and invalidate the mapping. It should occupy one and only TLB
3618 * entry. So, pmap_tlb_flush() called with aligned address should be
3621 opte1 = pte1_load_clear(pte1p);
3622 pmap_tlb_flush(pmap, sva);
3624 if (pte1_is_wired(opte1))
3625 pmap->pm_stats.wired_count -= PTE1_SIZE / PAGE_SIZE;
3626 pmap->pm_stats.resident_count -= PTE1_SIZE / PAGE_SIZE;
3627 if (pte1_is_managed(opte1)) {
3628 pvh = pa_to_pvh(pte1_pa(opte1));
3629 pmap_pvh_free(pvh, pmap, sva);
3630 eva = sva + PTE1_SIZE;
3631 for (va = sva, m = PHYS_TO_VM_PAGE(pte1_pa(opte1));
3632 va < eva; va += PAGE_SIZE, m++) {
3633 if (pte1_is_dirty(opte1))
3636 vm_page_aflag_set(m, PGA_REFERENCED);
3637 if (TAILQ_EMPTY(&m->md.pv_list) &&
3638 TAILQ_EMPTY(&pvh->pv_list))
3639 vm_page_aflag_clear(m, PGA_WRITEABLE);
3642 if (pmap == kernel_pmap) {
3644 * L2 page table(s) can't be removed from kernel map as
3645 * kernel counts on it (stuff around pmap_growkernel()).
3647 pmap_remove_kernel_pte1(pmap, pte1p, sva);
3650 * Get associated L2 page table page.
3651 * It's possible that the page was never allocated.
3653 m = pmap_pt2_page(pmap, sva);
3655 pmap_unwire_pt2_all(pmap, sva, m, free);
3660 * Fills L2 page table page with mappings to consecutive physical pages.
3662 static __inline void
3663 pmap_fill_pt2(pt2_entry_t *fpte2p, pt2_entry_t npte2)
3667 for (pte2p = fpte2p; pte2p < fpte2p + NPTE2_IN_PT2; pte2p++) {
3668 pte2_store(pte2p, npte2);
3674 * Tries to demote a 1MB page mapping. If demotion fails, the
3675 * 1MB page mapping is invalidated.
3678 pmap_demote_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3680 pt1_entry_t opte1, npte1;
3681 pt2_entry_t *fpte2p, npte2;
3682 vm_paddr_t pt2pg_pa, pt2_pa;
3684 struct spglist free;
3685 uint32_t pte1_idx, isnew = 0;
3687 PDEBUG(6, printf("%s(%p): try for va %#x pte1 %#x at %p\n", __func__,
3688 pmap, va, pte1_load(pte1p), pte1p));
3690 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3692 opte1 = pte1_load(pte1p);
3693 KASSERT(pte1_is_section(opte1), ("%s: opte1 not a section", __func__));
3695 if ((opte1 & PTE1_A) == 0 || (m = pmap_pt2_page(pmap, va)) == NULL) {
3696 KASSERT(!pte1_is_wired(opte1),
3697 ("%s: PT2 page for a wired mapping is missing", __func__));
3700 * Invalidate the 1MB page mapping and return
3701 * "failure" if the mapping was never accessed or the
3702 * allocation of the new page table page fails.
3704 if ((opte1 & PTE1_A) == 0 || (m = vm_page_alloc(NULL,
3705 pte1_index(va) & ~PT2PG_MASK, VM_ALLOC_NOOBJ |
3706 VM_ALLOC_NORMAL | VM_ALLOC_WIRED)) == NULL) {
3708 pmap_remove_pte1(pmap, pte1p, pte1_trunc(va), &free);
3709 pmap_free_zero_pages(&free);
3710 CTR3(KTR_PMAP, "%s: failure for va %#x in pmap %p",
3711 __func__, va, pmap);
3714 if (va < VM_MAXUSER_ADDRESS)
3715 pmap->pm_stats.resident_count++;
3720 * We init all L2 page tables in the page even if
3721 * we are going to change everything for one L2 page
3724 pt2pg_pa = pmap_pt2pg_init(pmap, va, m);
3726 if (va < VM_MAXUSER_ADDRESS) {
3727 if (pt2_is_empty(m, va))
3728 isnew = 1; /* Demoting section w/o promotion. */
3731 KASSERT(pt2_is_full(m, va), ("%s: bad PT2 wire"
3732 " count %u", __func__,
3733 pt2_wirecount_get(m, pte1_index(va))));
3738 pt2pg_pa = VM_PAGE_TO_PHYS(m);
3739 pte1_idx = pte1_index(va);
3741 * If the pmap is current, then the PT2MAP can provide access to
3742 * the page table page (promoted L2 page tables are not unmapped).
3743 * Otherwise, temporarily map the L2 page table page (m) into
3744 * the kernel's address space at either PADDR1 or PADDR2.
3746 * Note that L2 page table size is not equal to PAGE_SIZE.
3748 if (pmap_is_current(pmap))
3749 fpte2p = page_pt2(pt2map_pt2pg(va), pte1_idx);
3750 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
3751 if (pte2_pa(pte2_load(PMAP1)) != pt2pg_pa) {
3752 pte2_store(PMAP1, PTE2_KPT(pt2pg_pa));
3754 PMAP1cpu = PCPU_GET(cpuid);
3756 tlb_flush_local((vm_offset_t)PADDR1);
3760 if (PMAP1cpu != PCPU_GET(cpuid)) {
3761 PMAP1cpu = PCPU_GET(cpuid);
3762 tlb_flush_local((vm_offset_t)PADDR1);
3767 fpte2p = page_pt2((vm_offset_t)PADDR1, pte1_idx);
3769 mtx_lock(&PMAP2mutex);
3770 if (pte2_pa(pte2_load(PMAP2)) != pt2pg_pa) {
3771 pte2_store(PMAP2, PTE2_KPT(pt2pg_pa));
3772 tlb_flush((vm_offset_t)PADDR2);
3774 fpte2p = page_pt2((vm_offset_t)PADDR2, pte1_idx);
3776 pt2_pa = page_pt2pa(pt2pg_pa, pte1_idx);
3777 npte1 = PTE1_LINK(pt2_pa);
3779 KASSERT((opte1 & PTE1_A) != 0,
3780 ("%s: opte1 is missing PTE1_A", __func__));
3781 KASSERT((opte1 & (PTE1_NM | PTE1_RO)) != PTE1_NM,
3782 ("%s: opte1 has PTE1_NM", __func__));
3785 * Get pte2 from pte1 format.
3787 npte2 = pte1_pa(opte1) | ATTR_TO_L2(opte1) | PTE2_V;
3790 * If the L2 page table page is new, initialize it. If the mapping
3791 * has changed attributes, update the page table entries.
3794 pt2_wirecount_set(m, pte1_idx, NPTE2_IN_PT2);
3795 pmap_fill_pt2(fpte2p, npte2);
3796 } else if ((pte2_load(fpte2p) & PTE2_PROMOTE) !=
3797 (npte2 & PTE2_PROMOTE))
3798 pmap_fill_pt2(fpte2p, npte2);
3800 KASSERT(pte2_pa(pte2_load(fpte2p)) == pte2_pa(npte2),
3801 ("%s: fpte2p and npte2 map different physical addresses",
3804 if (fpte2p == PADDR2)
3805 mtx_unlock(&PMAP2mutex);
3808 * Demote the mapping. This pmap is locked. The old PTE1 has
3809 * PTE1_A set. If the old PTE1 has not PTE1_RO set, it also
3810 * has not PTE1_NM set. Thus, there is no danger of a race with
3811 * another processor changing the setting of PTE1_A and/or PTE1_NM
3812 * between the read above and the store below.
3814 pmap_change_pte1(pmap, pte1p, va, npte1);
3817 * Demote the pv entry. This depends on the earlier demotion
3818 * of the mapping. Specifically, the (re)creation of a per-
3819 * page pv entry might trigger the execution of pmap_pv_reclaim(),
3820 * which might reclaim a newly (re)created per-page pv entry
3821 * and destroy the associated mapping. In order to destroy
3822 * the mapping, the PTE1 must have already changed from mapping
3823 * the 1mpage to referencing the page table page.
3825 if (pte1_is_managed(opte1))
3826 pmap_pv_demote_pte1(pmap, va, pte1_pa(opte1));
3828 pmap_pte1_demotions++;
3829 CTR3(KTR_PMAP, "%s: success for va %#x in pmap %p",
3830 __func__, va, pmap);
3832 PDEBUG(6, printf("%s(%p): success for va %#x pte1 %#x(%#x) at %p\n",
3833 __func__, pmap, va, npte1, pte1_load(pte1p), pte1p));
3838 * Insert the given physical page (p) at
3839 * the specified virtual address (v) in the
3840 * target physical map with the protection requested.
3842 * If specified, the page will be wired down, meaning
3843 * that the related pte can not be reclaimed.
3845 * NB: This is the only routine which MAY NOT lazy-evaluate
3846 * or lose information. That is, this routine must actually
3847 * insert this page into the given map NOW.
3850 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3851 u_int flags, int8_t psind)
3855 pt2_entry_t npte2, opte2;
3858 vm_page_t mpte2, om;
3861 va = trunc_page(va);
3863 wired = (flags & PMAP_ENTER_WIRED) != 0;
3865 KASSERT(va <= vm_max_kernel_address, ("%s: toobig", __func__));
3866 KASSERT(va < UPT2V_MIN_ADDRESS || va >= UPT2V_MAX_ADDRESS,
3867 ("%s: invalid to pmap_enter page table pages (va: 0x%x)", __func__,
3869 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3870 VM_OBJECT_ASSERT_LOCKED(m->object);
3872 rw_wlock(&pvh_global_lock);
3877 * In the case that a page table page is not
3878 * resident, we are creating it here.
3880 if (va < VM_MAXUSER_ADDRESS) {
3881 mpte2 = pmap_allocpte2(pmap, va, flags);
3882 if (mpte2 == NULL) {
3883 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3884 ("pmap_allocpte2 failed with sleep allowed"));
3886 rw_wunlock(&pvh_global_lock);
3888 return (KERN_RESOURCE_SHORTAGE);
3891 pte1p = pmap_pte1(pmap, va);
3892 if (pte1_is_section(pte1_load(pte1p)))
3893 panic("%s: attempted on 1MB page", __func__);
3894 pte2p = pmap_pte2_quick(pmap, va);
3896 panic("%s: invalid L1 page table entry va=%#x", __func__, va);
3899 pa = VM_PAGE_TO_PHYS(m);
3900 opte2 = pte2_load(pte2p);
3901 opa = pte2_pa(opte2);
3903 * Mapping has not changed, must be protection or wiring change.
3905 if (pte2_is_valid(opte2) && (opa == pa)) {
3907 * Wiring change, just update stats. We don't worry about
3908 * wiring PT2 pages as they remain resident as long as there
3909 * are valid mappings in them. Hence, if a user page is wired,
3910 * the PT2 page will be also.
3912 if (wired && !pte2_is_wired(opte2))
3913 pmap->pm_stats.wired_count++;
3914 else if (!wired && pte2_is_wired(opte2))
3915 pmap->pm_stats.wired_count--;
3918 * Remove extra pte2 reference
3921 pt2_wirecount_dec(mpte2, pte1_index(va));
3922 if (pte2_is_managed(opte2))
3928 * QQQ: We think that changing physical address on writeable mapping
3929 * is not safe. Well, maybe on kernel address space with correct
3930 * locking, it can make a sense. However, we have no idea why
3931 * anyone should do that on user address space. Are we wrong?
3933 KASSERT((opa == 0) || (opa == pa) ||
3934 !pte2_is_valid(opte2) || ((opte2 & PTE2_RO) != 0),
3935 ("%s: pmap %p va %#x(%#x) opa %#x pa %#x - gotcha %#x %#x!",
3936 __func__, pmap, va, opte2, opa, pa, flags, prot));
3941 * Mapping has changed, invalidate old range and fall through to
3942 * handle validating new mapping.
3945 if (pte2_is_wired(opte2))
3946 pmap->pm_stats.wired_count--;
3947 if (pte2_is_managed(opte2)) {
3948 om = PHYS_TO_VM_PAGE(opa);
3949 pv = pmap_pvh_remove(&om->md, pmap, va);
3952 * Remove extra pte2 reference
3955 pt2_wirecount_dec(mpte2, va >> PTE1_SHIFT);
3957 pmap->pm_stats.resident_count++;
3960 * Enter on the PV list if part of our managed memory.
3962 if ((m->oflags & VPO_UNMANAGED) == 0) {
3963 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3964 ("%s: managed mapping within the clean submap", __func__));
3966 pv = get_pv_entry(pmap, FALSE);
3968 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3969 } else if (pv != NULL)
3970 free_pv_entry(pmap, pv);
3973 * Increment counters
3976 pmap->pm_stats.wired_count++;
3980 * Now validate mapping with desired protection/wiring.
3982 npte2 = PTE2(pa, PTE2_NM, vm_page_pte2_attr(m));
3983 if (prot & VM_PROT_WRITE) {
3984 if (pte2_is_managed(npte2))
3985 vm_page_aflag_set(m, PGA_WRITEABLE);
3989 if ((prot & VM_PROT_EXECUTE) == 0)
3993 if (va < VM_MAXUSER_ADDRESS)
3995 if (pmap != kernel_pmap)
3999 * If the mapping or permission bits are different, we need
4000 * to update the pte2.
4002 * QQQ: Think again and again what to do
4003 * if the mapping is going to be changed!
4005 if ((opte2 & ~(PTE2_NM | PTE2_A)) != (npte2 & ~(PTE2_NM | PTE2_A))) {
4007 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4008 * is set. Do it now, before the mapping is stored and made
4009 * valid for hardware table walk. If done later, there is a race
4010 * for other threads of current process in lazy loading case.
4011 * Don't do it for kernel memory which is mapped with exec
4012 * permission even if the memory isn't going to hold executable
4013 * code. The only time when icache sync is needed is after
4014 * kernel module is loaded and the relocation info is processed.
4015 * And it's done in elf_cpu_load_file().
4017 * QQQ: (1) Does it exist any better way where
4018 * or how to sync icache?
4019 * (2) Now, we do it on a page basis.
4021 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
4022 m->md.pat_mode == VM_MEMATTR_WB_WA &&
4023 (opa != pa || (opte2 & PTE2_NX)))
4024 cache_icache_sync_fresh(va, pa, PAGE_SIZE);
4027 if (flags & VM_PROT_WRITE)
4029 if (opte2 & PTE2_V) {
4030 /* Change mapping with break-before-make approach. */
4031 opte2 = pte2_load_clear(pte2p);
4032 pmap_tlb_flush(pmap, va);
4033 pte2_store(pte2p, npte2);
4034 if (opte2 & PTE2_A) {
4035 if (pte2_is_managed(opte2))
4036 vm_page_aflag_set(om, PGA_REFERENCED);
4038 if (pte2_is_dirty(opte2)) {
4039 if (pte2_is_managed(opte2))
4042 if (pte2_is_managed(opte2) &&
4043 TAILQ_EMPTY(&om->md.pv_list) &&
4044 ((om->flags & PG_FICTITIOUS) != 0 ||
4045 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
4046 vm_page_aflag_clear(om, PGA_WRITEABLE);
4048 pte2_store(pte2p, npte2);
4053 * QQQ: In time when both access and not mofified bits are
4054 * emulated by software, this should not happen. Some
4055 * analysis is need, if this really happen. Missing
4056 * tlb flush somewhere could be the reason.
4058 panic("%s: pmap %p va %#x opte2 %x npte2 %x !!", __func__, pmap,
4063 #if VM_NRESERVLEVEL > 0
4065 * If both the L2 page table page and the reservation are fully
4066 * populated, then attempt promotion.
4068 if ((mpte2 == NULL || pt2_is_full(mpte2, va)) &&
4069 sp_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
4070 vm_reserv_level_iffullpop(m) == 0)
4071 pmap_promote_pte1(pmap, pte1p, va);
4074 rw_wunlock(&pvh_global_lock);
4076 return (KERN_SUCCESS);
4080 * Do the things to unmap a page in a process.
4083 pmap_remove_pte2(pmap_t pmap, pt2_entry_t *pte2p, vm_offset_t va,
4084 struct spglist *free)
4089 rw_assert(&pvh_global_lock, RA_WLOCKED);
4090 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4092 /* Clear and invalidate the mapping. */
4093 opte2 = pte2_load_clear(pte2p);
4094 pmap_tlb_flush(pmap, va);
4096 KASSERT(pte2_is_valid(opte2), ("%s: pmap %p va %#x not link pte2 %#x",
4097 __func__, pmap, va, opte2));
4100 pmap->pm_stats.wired_count -= 1;
4101 pmap->pm_stats.resident_count -= 1;
4102 if (pte2_is_managed(opte2)) {
4103 m = PHYS_TO_VM_PAGE(pte2_pa(opte2));
4104 if (pte2_is_dirty(opte2))
4107 vm_page_aflag_set(m, PGA_REFERENCED);
4108 pmap_remove_entry(pmap, m, va);
4110 return (pmap_unuse_pt2(pmap, va, free));
4114 * Remove a single page from a process address space.
4117 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
4121 rw_assert(&pvh_global_lock, RA_WLOCKED);
4122 KASSERT(curthread->td_pinned > 0,
4123 ("%s: curthread not pinned", __func__));
4124 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4125 if ((pte2p = pmap_pte2_quick(pmap, va)) == NULL ||
4126 !pte2_is_valid(pte2_load(pte2p)))
4128 pmap_remove_pte2(pmap, pte2p, va, free);
4132 * Remove the given range of addresses from the specified map.
4134 * It is assumed that the start and end are properly
4135 * rounded to the page size.
4138 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4141 pt1_entry_t *pte1p, pte1;
4142 pt2_entry_t *pte2p, pte2;
4143 struct spglist free;
4146 * Perform an unsynchronized read. This is, however, safe.
4148 if (pmap->pm_stats.resident_count == 0)
4153 rw_wlock(&pvh_global_lock);
4158 * Special handling of removing one page. A very common
4159 * operation and easy to short circuit some code.
4161 if (sva + PAGE_SIZE == eva) {
4162 pte1 = pte1_load(pmap_pte1(pmap, sva));
4163 if (pte1_is_link(pte1)) {
4164 pmap_remove_page(pmap, sva, &free);
4169 for (; sva < eva; sva = nextva) {
4171 * Calculate address for next L2 page table.
4173 nextva = pte1_trunc(sva + PTE1_SIZE);
4176 if (pmap->pm_stats.resident_count == 0)
4179 pte1p = pmap_pte1(pmap, sva);
4180 pte1 = pte1_load(pte1p);
4183 * Weed out invalid mappings. Note: we assume that the L1 page
4184 * table is always allocated, and in kernel virtual.
4189 if (pte1_is_section(pte1)) {
4191 * Are we removing the entire large page? If not,
4192 * demote the mapping and fall through.
4194 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
4195 pmap_remove_pte1(pmap, pte1p, sva, &free);
4197 } else if (!pmap_demote_pte1(pmap, pte1p, sva)) {
4198 /* The large page mapping was destroyed. */
4203 /* Update pte1 after demotion. */
4204 pte1 = pte1_load(pte1p);
4209 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
4210 " is not link", __func__, pmap, sva, pte1, pte1p));
4213 * Limit our scan to either the end of the va represented
4214 * by the current L2 page table page, or to the end of the
4215 * range being removed.
4220 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva;
4221 pte2p++, sva += PAGE_SIZE) {
4222 pte2 = pte2_load(pte2p);
4223 if (!pte2_is_valid(pte2))
4225 if (pmap_remove_pte2(pmap, pte2p, sva, &free))
4231 rw_wunlock(&pvh_global_lock);
4233 pmap_free_zero_pages(&free);
4237 * Routine: pmap_remove_all
4239 * Removes this physical page from
4240 * all physical maps in which it resides.
4241 * Reflects back modify bits to the pager.
4244 * Original versions of this routine were very
4245 * inefficient because they iteratively called
4246 * pmap_remove (slow...)
4250 pmap_remove_all(vm_page_t m)
4252 struct md_page *pvh;
4255 pt2_entry_t *pte2p, opte2;
4258 struct spglist free;
4260 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4261 ("%s: page %p is not managed", __func__, m));
4263 rw_wlock(&pvh_global_lock);
4265 if ((m->flags & PG_FICTITIOUS) != 0)
4266 goto small_mappings;
4267 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4268 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
4272 pte1p = pmap_pte1(pmap, va);
4273 (void)pmap_demote_pte1(pmap, pte1p, va);
4277 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4280 pmap->pm_stats.resident_count--;
4281 pte1p = pmap_pte1(pmap, pv->pv_va);
4282 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found "
4283 "a 1mpage in page %p's pv list", __func__, m));
4284 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
4285 opte2 = pte2_load_clear(pte2p);
4286 pmap_tlb_flush(pmap, pv->pv_va);
4287 KASSERT(pte2_is_valid(opte2), ("%s: pmap %p va %x zero pte2",
4288 __func__, pmap, pv->pv_va));
4289 if (pte2_is_wired(opte2))
4290 pmap->pm_stats.wired_count--;
4292 vm_page_aflag_set(m, PGA_REFERENCED);
4295 * Update the vm_page_t clean and reference bits.
4297 if (pte2_is_dirty(opte2))
4299 pmap_unuse_pt2(pmap, pv->pv_va, &free);
4300 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4301 free_pv_entry(pmap, pv);
4304 vm_page_aflag_clear(m, PGA_WRITEABLE);
4306 rw_wunlock(&pvh_global_lock);
4307 pmap_free_zero_pages(&free);
4311 * Just subroutine for pmap_remove_pages() to reasonably satisfy
4312 * good coding style, a.k.a. 80 character line width limit hell.
4314 static __inline void
4315 pmap_remove_pte1_quick(pmap_t pmap, pt1_entry_t pte1, pv_entry_t pv,
4316 struct spglist *free)
4319 vm_page_t m, mt, mpt2pg;
4320 struct md_page *pvh;
4323 m = PHYS_TO_VM_PAGE(pa);
4325 KASSERT(m->phys_addr == pa, ("%s: vm_page_t %p addr mismatch %#x %#x",
4326 __func__, m, m->phys_addr, pa));
4327 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4328 m < &vm_page_array[vm_page_array_size],
4329 ("%s: bad pte1 %#x", __func__, pte1));
4331 if (pte1_is_dirty(pte1)) {
4332 for (mt = m; mt < &m[PTE1_SIZE / PAGE_SIZE]; mt++)
4336 pmap->pm_stats.resident_count -= PTE1_SIZE / PAGE_SIZE;
4337 pvh = pa_to_pvh(pa);
4338 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4339 if (TAILQ_EMPTY(&pvh->pv_list)) {
4340 for (mt = m; mt < &m[PTE1_SIZE / PAGE_SIZE]; mt++)
4341 if (TAILQ_EMPTY(&mt->md.pv_list))
4342 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4344 mpt2pg = pmap_pt2_page(pmap, pv->pv_va);
4346 pmap_unwire_pt2_all(pmap, pv->pv_va, mpt2pg, free);
4350 * Just subroutine for pmap_remove_pages() to reasonably satisfy
4351 * good coding style, a.k.a. 80 character line width limit hell.
4353 static __inline void
4354 pmap_remove_pte2_quick(pmap_t pmap, pt2_entry_t pte2, pv_entry_t pv,
4355 struct spglist *free)
4359 struct md_page *pvh;
4362 m = PHYS_TO_VM_PAGE(pa);
4364 KASSERT(m->phys_addr == pa, ("%s: vm_page_t %p addr mismatch %#x %#x",
4365 __func__, m, m->phys_addr, pa));
4366 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4367 m < &vm_page_array[vm_page_array_size],
4368 ("%s: bad pte2 %#x", __func__, pte2));
4370 if (pte2_is_dirty(pte2))
4373 pmap->pm_stats.resident_count--;
4374 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4375 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
4376 pvh = pa_to_pvh(pa);
4377 if (TAILQ_EMPTY(&pvh->pv_list))
4378 vm_page_aflag_clear(m, PGA_WRITEABLE);
4380 pmap_unuse_pt2(pmap, pv->pv_va, free);
4384 * Remove all pages from specified address space this aids process
4385 * exit speeds. Also, this code is special cased for current process
4386 * only, but can have the more generic (and slightly slower) mode enabled.
4387 * This is much faster than pmap_remove in the case of running down
4388 * an entire address space.
4391 pmap_remove_pages(pmap_t pmap)
4393 pt1_entry_t *pte1p, pte1;
4394 pt2_entry_t *pte2p, pte2;
4396 struct pv_chunk *pc, *npc;
4397 struct spglist free;
4400 uint32_t inuse, bitmask;
4404 * Assert that the given pmap is only active on the current
4405 * CPU. Unfortunately, we cannot block another CPU from
4406 * activating the pmap while this function is executing.
4408 KASSERT(pmap == vmspace_pmap(curthread->td_proc->p_vmspace),
4409 ("%s: non-current pmap %p", __func__, pmap));
4410 #if defined(SMP) && defined(INVARIANTS)
4412 cpuset_t other_cpus;
4415 other_cpus = pmap->pm_active;
4416 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
4418 KASSERT(CPU_EMPTY(&other_cpus),
4419 ("%s: pmap %p active on other cpus", __func__, pmap));
4423 rw_wlock(&pvh_global_lock);
4426 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4427 KASSERT(pc->pc_pmap == pmap, ("%s: wrong pmap %p %p",
4428 __func__, pmap, pc->pc_pmap));
4430 for (field = 0; field < _NPCM; field++) {
4431 inuse = (~(pc->pc_map[field])) & pc_freemask[field];
4432 while (inuse != 0) {
4433 bit = ffs(inuse) - 1;
4434 bitmask = 1UL << bit;
4435 idx = field * 32 + bit;
4436 pv = &pc->pc_pventry[idx];
4440 * Note that we cannot remove wired pages
4441 * from a process' mapping at this time
4443 pte1p = pmap_pte1(pmap, pv->pv_va);
4444 pte1 = pte1_load(pte1p);
4445 if (pte1_is_section(pte1)) {
4446 if (pte1_is_wired(pte1)) {
4451 pmap_remove_pte1_quick(pmap, pte1, pv,
4454 else if (pte1_is_link(pte1)) {
4455 pte2p = pt2map_entry(pv->pv_va);
4456 pte2 = pte2_load(pte2p);
4458 if (!pte2_is_valid(pte2)) {
4459 printf("%s: pmap %p va %#x "
4460 "pte2 %#x\n", __func__,
4461 pmap, pv->pv_va, pte2);
4465 if (pte2_is_wired(pte2)) {
4470 pmap_remove_pte2_quick(pmap, pte2, pv,
4473 printf("%s: pmap %p va %#x pte1 %#x\n",
4474 __func__, pmap, pv->pv_va, pte1);
4479 PV_STAT(pv_entry_frees++);
4480 PV_STAT(pv_entry_spare++);
4482 pc->pc_map[field] |= bitmask;
4486 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4490 tlb_flush_all_ng_local();
4492 rw_wunlock(&pvh_global_lock);
4494 pmap_free_zero_pages(&free);
4498 * This code makes some *MAJOR* assumptions:
4499 * 1. Current pmap & pmap exists.
4502 * 4. No L2 page table pages.
4503 * but is *MUCH* faster than pmap_enter...
4506 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4507 vm_prot_t prot, vm_page_t mpt2pg)
4509 pt2_entry_t *pte2p, pte2;
4511 struct spglist free;
4514 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
4515 (m->oflags & VPO_UNMANAGED) != 0,
4516 ("%s: managed mapping within the clean submap", __func__));
4517 rw_assert(&pvh_global_lock, RA_WLOCKED);
4518 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4521 * In the case that a L2 page table page is not
4522 * resident, we are creating it here.
4524 if (va < VM_MAXUSER_ADDRESS) {
4526 pt1_entry_t pte1, *pte1p;
4530 * Get L1 page table things.
4532 pte1_idx = pte1_index(va);
4533 pte1p = pmap_pte1(pmap, va);
4534 pte1 = pte1_load(pte1p);
4536 if (mpt2pg && (mpt2pg->pindex == (pte1_idx & ~PT2PG_MASK))) {
4538 * Each of NPT2_IN_PG L2 page tables on the page can
4539 * come here. Make sure that associated L1 page table
4540 * link is established.
4542 * QQQ: It comes that we don't establish all links to
4543 * L2 page tables for newly allocated L2 page
4546 KASSERT(!pte1_is_section(pte1),
4547 ("%s: pte1 %#x is section", __func__, pte1));
4548 if (!pte1_is_link(pte1)) {
4549 pt2_pa = page_pt2pa(VM_PAGE_TO_PHYS(mpt2pg),
4551 pte1_store(pte1p, PTE1_LINK(pt2_pa));
4553 pt2_wirecount_inc(mpt2pg, pte1_idx);
4556 * If the L2 page table page is mapped, we just
4557 * increment the hold count, and activate it.
4559 if (pte1_is_section(pte1)) {
4561 } else if (pte1_is_link(pte1)) {
4562 mpt2pg = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
4563 pt2_wirecount_inc(mpt2pg, pte1_idx);
4565 mpt2pg = _pmap_allocpte2(pmap, va,
4566 PMAP_ENTER_NOSLEEP);
4576 * This call to pt2map_entry() makes the assumption that we are
4577 * entering the page into the current pmap. In order to support
4578 * quick entry into any pmap, one would likely use pmap_pte2_quick().
4579 * But that isn't as quick as pt2map_entry().
4581 pte2p = pt2map_entry(va);
4582 pte2 = pte2_load(pte2p);
4583 if (pte2_is_valid(pte2)) {
4584 if (mpt2pg != NULL) {
4586 * Remove extra pte2 reference
4588 pt2_wirecount_dec(mpt2pg, pte1_index(va));
4595 * Enter on the PV list if part of our managed memory.
4597 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4598 !pmap_try_insert_pv_entry(pmap, va, m)) {
4599 if (mpt2pg != NULL) {
4601 if (pmap_unwire_pt2(pmap, va, mpt2pg, &free)) {
4602 pmap_tlb_flush(pmap, va);
4603 pmap_free_zero_pages(&free);
4612 * Increment counters
4614 pmap->pm_stats.resident_count++;
4617 * Now validate mapping with RO protection
4619 pa = VM_PAGE_TO_PHYS(m);
4620 l2prot = PTE2_RO | PTE2_NM;
4621 if (va < VM_MAXUSER_ADDRESS)
4622 l2prot |= PTE2_U | PTE2_NG;
4623 if ((prot & VM_PROT_EXECUTE) == 0)
4625 else if (m->md.pat_mode == VM_MEMATTR_WB_WA && pmap != kernel_pmap) {
4627 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4628 * is set. QQQ: For more info, see comments in pmap_enter().
4630 cache_icache_sync_fresh(va, pa, PAGE_SIZE);
4632 pte2_store(pte2p, PTE2(pa, l2prot, vm_page_pte2_attr(m)));
4638 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4641 rw_wlock(&pvh_global_lock);
4643 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
4644 rw_wunlock(&pvh_global_lock);
4649 * Tries to create 1MB page mapping. Returns TRUE if successful and
4650 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
4651 * blocking, (2) a mapping already exists at the specified virtual address, or
4652 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
4655 pmap_enter_pte1(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4661 rw_assert(&pvh_global_lock, RA_WLOCKED);
4662 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4663 pte1p = pmap_pte1(pmap, va);
4664 if (pte1_is_valid(pte1_load(pte1p))) {
4665 CTR3(KTR_PMAP, "%s: failure for va %#lx in pmap %p", __func__,
4669 if ((m->oflags & VPO_UNMANAGED) == 0) {
4671 * Abort this mapping if its PV entry could not be created.
4673 if (!pmap_pv_insert_pte1(pmap, va, VM_PAGE_TO_PHYS(m))) {
4674 CTR3(KTR_PMAP, "%s: failure for va %#lx in pmap %p",
4675 __func__, va, pmap);
4680 * Increment counters.
4682 pmap->pm_stats.resident_count += PTE1_SIZE / PAGE_SIZE;
4687 * QQQ: Why VM_PROT_WRITE is not evaluated and the mapping is
4690 pa = VM_PAGE_TO_PHYS(m);
4691 l1prot = PTE1_RO | PTE1_NM;
4692 if (va < VM_MAXUSER_ADDRESS)
4693 l1prot |= PTE1_U | PTE1_NG;
4694 if ((prot & VM_PROT_EXECUTE) == 0)
4696 else if (m->md.pat_mode == VM_MEMATTR_WB_WA && pmap != kernel_pmap) {
4698 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4699 * is set. QQQ: For more info, see comments in pmap_enter().
4701 cache_icache_sync_fresh(va, pa, PTE1_SIZE);
4703 pte1_store(pte1p, PTE1(pa, l1prot, ATTR_TO_L1(vm_page_pte2_attr(m))));
4705 pmap_pte1_mappings++;
4706 CTR3(KTR_PMAP, "%s: success for va %#lx in pmap %p", __func__, va,
4712 * Maps a sequence of resident pages belonging to the same object.
4713 * The sequence begins with the given page m_start. This page is
4714 * mapped at the given virtual address start. Each subsequent page is
4715 * mapped at a virtual address that is offset from start by the same
4716 * amount as the page is offset from m_start within the object. The
4717 * last page in the sequence is the page with the largest offset from
4718 * m_start that can be mapped at a virtual address less than the given
4719 * virtual address end. Not every virtual page between start and end
4720 * is mapped; only those for which a resident page exists with the
4721 * corresponding offset from m_start are mapped.
4724 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4725 vm_page_t m_start, vm_prot_t prot)
4728 vm_page_t m, mpt2pg;
4729 vm_pindex_t diff, psize;
4731 PDEBUG(6, printf("%s: pmap %p start %#x end %#x m %p prot %#x\n",
4732 __func__, pmap, start, end, m_start, prot));
4734 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4735 psize = atop(end - start);
4738 rw_wlock(&pvh_global_lock);
4740 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4741 va = start + ptoa(diff);
4742 if ((va & PTE1_OFFSET) == 0 && va + PTE1_SIZE <= end &&
4743 m->psind == 1 && sp_enabled &&
4744 pmap_enter_pte1(pmap, va, m, prot))
4745 m = &m[PTE1_SIZE / PAGE_SIZE - 1];
4747 mpt2pg = pmap_enter_quick_locked(pmap, va, m, prot,
4749 m = TAILQ_NEXT(m, listq);
4751 rw_wunlock(&pvh_global_lock);
4756 * This code maps large physical mmap regions into the
4757 * processor address space. Note that some shortcuts
4758 * are taken, but the code works.
4761 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4762 vm_pindex_t pindex, vm_size_t size)
4765 vm_paddr_t pa, pte2_pa;
4767 vm_memattr_t pat_mode;
4768 u_int l1attr, l1prot;
4770 VM_OBJECT_ASSERT_WLOCKED(object);
4771 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4772 ("%s: non-device object", __func__));
4773 if ((addr & PTE1_OFFSET) == 0 && (size & PTE1_OFFSET) == 0) {
4774 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4776 p = vm_page_lookup(object, pindex);
4777 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4778 ("%s: invalid page %p", __func__, p));
4779 pat_mode = p->md.pat_mode;
4782 * Abort the mapping if the first page is not physically
4783 * aligned to a 1MB page boundary.
4785 pte2_pa = VM_PAGE_TO_PHYS(p);
4786 if (pte2_pa & PTE1_OFFSET)
4790 * Skip the first page. Abort the mapping if the rest of
4791 * the pages are not physically contiguous or have differing
4792 * memory attributes.
4794 p = TAILQ_NEXT(p, listq);
4795 for (pa = pte2_pa + PAGE_SIZE; pa < pte2_pa + size;
4797 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4798 ("%s: invalid page %p", __func__, p));
4799 if (pa != VM_PAGE_TO_PHYS(p) ||
4800 pat_mode != p->md.pat_mode)
4802 p = TAILQ_NEXT(p, listq);
4806 * Map using 1MB pages.
4808 * QQQ: Well, we are mapping a section, so same condition must
4809 * be hold like during promotion. It looks that only RW mapping
4810 * is done here, so readonly mapping must be done elsewhere.
4812 l1prot = PTE1_U | PTE1_NG | PTE1_RW | PTE1_M | PTE1_A;
4813 l1attr = ATTR_TO_L1(vm_memattr_to_pte2(pat_mode));
4815 for (pa = pte2_pa; pa < pte2_pa + size; pa += PTE1_SIZE) {
4816 pte1p = pmap_pte1(pmap, addr);
4817 if (!pte1_is_valid(pte1_load(pte1p))) {
4818 pte1_store(pte1p, PTE1(pa, l1prot, l1attr));
4819 pmap->pm_stats.resident_count += PTE1_SIZE /
4821 pmap_pte1_mappings++;
4823 /* Else continue on if the PTE1 is already valid. */
4831 * Do the things to protect a 1mpage in a process.
4834 pmap_protect_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t sva,
4837 pt1_entry_t npte1, opte1;
4838 vm_offset_t eva, va;
4841 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4842 KASSERT((sva & PTE1_OFFSET) == 0,
4843 ("%s: sva is not 1mpage aligned", __func__));
4845 opte1 = npte1 = pte1_load(pte1p);
4846 if (pte1_is_managed(opte1) && pte1_is_dirty(opte1)) {
4847 eva = sva + PTE1_SIZE;
4848 for (va = sva, m = PHYS_TO_VM_PAGE(pte1_pa(opte1));
4849 va < eva; va += PAGE_SIZE, m++)
4852 if ((prot & VM_PROT_WRITE) == 0)
4853 npte1 |= PTE1_RO | PTE1_NM;
4854 if ((prot & VM_PROT_EXECUTE) == 0)
4858 * QQQ: Herein, execute permission is never set.
4859 * It only can be cleared. So, no icache
4860 * syncing is needed.
4863 if (npte1 != opte1) {
4864 pte1_store(pte1p, npte1);
4865 pmap_tlb_flush(pmap, sva);
4870 * Set the physical protection on the
4871 * specified range of this map as requested.
4874 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
4876 boolean_t pv_lists_locked;
4878 pt1_entry_t *pte1p, pte1;
4879 pt2_entry_t *pte2p, opte2, npte2;
4881 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
4882 if (prot == VM_PROT_NONE) {
4883 pmap_remove(pmap, sva, eva);
4887 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
4888 (VM_PROT_WRITE | VM_PROT_EXECUTE))
4891 if (pmap_is_current(pmap))
4892 pv_lists_locked = FALSE;
4894 pv_lists_locked = TRUE;
4896 rw_wlock(&pvh_global_lock);
4901 for (; sva < eva; sva = nextva) {
4903 * Calculate address for next L2 page table.
4905 nextva = pte1_trunc(sva + PTE1_SIZE);
4909 pte1p = pmap_pte1(pmap, sva);
4910 pte1 = pte1_load(pte1p);
4913 * Weed out invalid mappings. Note: we assume that L1 page
4914 * page table is always allocated, and in kernel virtual.
4919 if (pte1_is_section(pte1)) {
4921 * Are we protecting the entire large page? If not,
4922 * demote the mapping and fall through.
4924 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
4925 pmap_protect_pte1(pmap, pte1p, sva, prot);
4928 if (!pv_lists_locked) {
4929 pv_lists_locked = TRUE;
4930 if (!rw_try_wlock(&pvh_global_lock)) {
4936 if (!pmap_demote_pte1(pmap, pte1p, sva)) {
4938 * The large page mapping
4945 /* Update pte1 after demotion */
4946 pte1 = pte1_load(pte1p);
4952 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
4953 " is not link", __func__, pmap, sva, pte1, pte1p));
4956 * Limit our scan to either the end of the va represented
4957 * by the current L2 page table page, or to the end of the
4958 * range being protected.
4963 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva; pte2p++,
4967 opte2 = npte2 = pte2_load(pte2p);
4968 if (!pte2_is_valid(opte2))
4971 if ((prot & VM_PROT_WRITE) == 0) {
4972 if (pte2_is_managed(opte2) &&
4973 pte2_is_dirty(opte2)) {
4974 m = PHYS_TO_VM_PAGE(pte2_pa(opte2));
4977 npte2 |= PTE2_RO | PTE2_NM;
4980 if ((prot & VM_PROT_EXECUTE) == 0)
4984 * QQQ: Herein, execute permission is never set.
4985 * It only can be cleared. So, no icache
4986 * syncing is needed.
4989 if (npte2 != opte2) {
4990 pte2_store(pte2p, npte2);
4991 pmap_tlb_flush(pmap, sva);
4995 if (pv_lists_locked) {
4997 rw_wunlock(&pvh_global_lock);
5003 * pmap_pvh_wired_mappings:
5005 * Return the updated number "count" of managed mappings that are wired.
5008 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
5015 rw_assert(&pvh_global_lock, RA_WLOCKED);
5017 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5020 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5021 if (pte1_is_section(pte1)) {
5022 if (pte1_is_wired(pte1))
5025 KASSERT(pte1_is_link(pte1),
5026 ("%s: pte1 %#x is not link", __func__, pte1));
5027 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5028 if (pte2_is_wired(pte2))
5038 * pmap_page_wired_mappings:
5040 * Return the number of managed mappings to the given physical page
5044 pmap_page_wired_mappings(vm_page_t m)
5049 if ((m->oflags & VPO_UNMANAGED) != 0)
5051 rw_wlock(&pvh_global_lock);
5052 count = pmap_pvh_wired_mappings(&m->md, count);
5053 if ((m->flags & PG_FICTITIOUS) == 0) {
5054 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
5057 rw_wunlock(&pvh_global_lock);
5062 * Returns TRUE if any of the given mappings were used to modify
5063 * physical memory. Otherwise, returns FALSE. Both page and 1mpage
5064 * mappings are supported.
5067 pmap_is_modified_pvh(struct md_page *pvh)
5075 rw_assert(&pvh_global_lock, RA_WLOCKED);
5078 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5081 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5082 if (pte1_is_section(pte1)) {
5083 rv = pte1_is_dirty(pte1);
5085 KASSERT(pte1_is_link(pte1),
5086 ("%s: pte1 %#x is not link", __func__, pte1));
5087 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5088 rv = pte2_is_dirty(pte2);
5101 * Return whether or not the specified physical page was modified
5102 * in any physical maps.
5105 pmap_is_modified(vm_page_t m)
5109 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5110 ("%s: page %p is not managed", __func__, m));
5113 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5114 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
5115 * is clear, no PTE2s can have PG_M set.
5117 VM_OBJECT_ASSERT_WLOCKED(m->object);
5118 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5120 rw_wlock(&pvh_global_lock);
5121 rv = pmap_is_modified_pvh(&m->md) ||
5122 ((m->flags & PG_FICTITIOUS) == 0 &&
5123 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
5124 rw_wunlock(&pvh_global_lock);
5129 * pmap_is_prefaultable:
5131 * Return whether or not the specified virtual address is eligible
5135 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
5143 pte1 = pte1_load(pmap_pte1(pmap, addr));
5144 if (pte1_is_link(pte1)) {
5145 pte2 = pte2_load(pt2map_entry(addr));
5146 rv = !pte2_is_valid(pte2) ;
5153 * Returns TRUE if any of the given mappings were referenced and FALSE
5154 * otherwise. Both page and 1mpage mappings are supported.
5157 pmap_is_referenced_pvh(struct md_page *pvh)
5166 rw_assert(&pvh_global_lock, RA_WLOCKED);
5169 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5172 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5173 if (pte1_is_section(pte1)) {
5174 rv = (pte1 & (PTE1_A | PTE1_V)) == (PTE1_A | PTE1_V);
5176 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5177 rv = (pte2 & (PTE2_A | PTE2_V)) == (PTE2_A | PTE2_V);
5188 * pmap_is_referenced:
5190 * Return whether or not the specified physical page was referenced
5191 * in any physical maps.
5194 pmap_is_referenced(vm_page_t m)
5198 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5199 ("%s: page %p is not managed", __func__, m));
5200 rw_wlock(&pvh_global_lock);
5201 rv = pmap_is_referenced_pvh(&m->md) ||
5202 ((m->flags & PG_FICTITIOUS) == 0 &&
5203 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
5204 rw_wunlock(&pvh_global_lock);
5209 * pmap_ts_referenced:
5211 * Return a count of reference bits for a page, clearing those bits.
5212 * It is not necessary for every reference bit to be cleared, but it
5213 * is necessary that 0 only be returned when there are truly no
5214 * reference bits set.
5216 * As an optimization, update the page's dirty field if a modified bit is
5217 * found while counting reference bits. This opportunistic update can be
5218 * performed at low cost and can eliminate the need for some future calls
5219 * to pmap_is_modified(). However, since this function stops after
5220 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5221 * dirty pages. Those dirty pages will only be detected by a future call
5222 * to pmap_is_modified().
5225 pmap_ts_referenced(vm_page_t m)
5227 struct md_page *pvh;
5230 pt1_entry_t *pte1p, opte1;
5231 pt2_entry_t *pte2p, opte2;
5235 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5236 ("%s: page %p is not managed", __func__, m));
5237 pa = VM_PAGE_TO_PHYS(m);
5238 pvh = pa_to_pvh(pa);
5239 rw_wlock(&pvh_global_lock);
5241 if ((m->flags & PG_FICTITIOUS) != 0 ||
5242 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5243 goto small_mappings;
5248 pte1p = pmap_pte1(pmap, pv->pv_va);
5249 opte1 = pte1_load(pte1p);
5250 if (pte1_is_dirty(opte1)) {
5252 * Although "opte1" is mapping a 1MB page, because
5253 * this function is called at a 4KB page granularity,
5254 * we only update the 4KB page under test.
5258 if ((opte1 & PTE1_A) != 0) {
5260 * Since this reference bit is shared by 256 4KB pages,
5261 * it should not be cleared every time it is tested.
5262 * Apply a simple "hash" function on the physical page
5263 * number, the virtual section number, and the pmap
5264 * address to select one 4KB page out of the 256
5265 * on which testing the reference bit will result
5266 * in clearing that bit. This function is designed
5267 * to avoid the selection of the same 4KB page
5268 * for every 1MB page mapping.
5270 * On demotion, a mapping that hasn't been referenced
5271 * is simply destroyed. To avoid the possibility of a
5272 * subsequent page fault on a demoted wired mapping,
5273 * always leave its reference bit set. Moreover,
5274 * since the section is wired, the current state of
5275 * its reference bit won't affect page replacement.
5277 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PTE1_SHIFT) ^
5278 (uintptr_t)pmap) & (NPTE2_IN_PG - 1)) == 0 &&
5279 !pte1_is_wired(opte1)) {
5280 pte1_clear_bit(pte1p, PTE1_A);
5281 pmap_tlb_flush(pmap, pv->pv_va);
5286 /* Rotate the PV list if it has more than one entry. */
5287 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5288 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5289 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5291 if (rtval >= PMAP_TS_REFERENCED_MAX)
5293 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5295 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5301 pte1p = pmap_pte1(pmap, pv->pv_va);
5302 KASSERT(pte1_is_link(pte1_load(pte1p)),
5303 ("%s: not found a link in page %p's pv list", __func__, m));
5305 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5306 opte2 = pte2_load(pte2p);
5307 if (pte2_is_dirty(opte2))
5309 if ((opte2 & PTE2_A) != 0) {
5310 pte2_clear_bit(pte2p, PTE2_A);
5311 pmap_tlb_flush(pmap, pv->pv_va);
5315 /* Rotate the PV list if it has more than one entry. */
5316 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5317 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5318 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5320 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
5321 PMAP_TS_REFERENCED_MAX);
5324 rw_wunlock(&pvh_global_lock);
5329 * Clear the wired attribute from the mappings for the specified range of
5330 * addresses in the given pmap. Every valid mapping within that range
5331 * must have the wired attribute set. In contrast, invalid mappings
5332 * cannot have the wired attribute set, so they are ignored.
5334 * The wired attribute of the page table entry is not a hardware feature,
5335 * so there is no need to invalidate any TLB entries.
5338 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5341 pt1_entry_t *pte1p, pte1;
5342 pt2_entry_t *pte2p, pte2;
5343 boolean_t pv_lists_locked;
5345 if (pmap_is_current(pmap))
5346 pv_lists_locked = FALSE;
5348 pv_lists_locked = TRUE;
5350 rw_wlock(&pvh_global_lock);
5354 for (; sva < eva; sva = nextva) {
5355 nextva = pte1_trunc(sva + PTE1_SIZE);
5359 pte1p = pmap_pte1(pmap, sva);
5360 pte1 = pte1_load(pte1p);
5363 * Weed out invalid mappings. Note: we assume that L1 page
5364 * page table is always allocated, and in kernel virtual.
5369 if (pte1_is_section(pte1)) {
5370 if (!pte1_is_wired(pte1))
5371 panic("%s: pte1 %#x not wired", __func__, pte1);
5374 * Are we unwiring the entire large page? If not,
5375 * demote the mapping and fall through.
5377 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
5378 pte1_clear_bit(pte1p, PTE1_W);
5379 pmap->pm_stats.wired_count -= PTE1_SIZE /
5383 if (!pv_lists_locked) {
5384 pv_lists_locked = TRUE;
5385 if (!rw_try_wlock(&pvh_global_lock)) {
5392 if (!pmap_demote_pte1(pmap, pte1p, sva))
5393 panic("%s: demotion failed", __func__);
5396 /* Update pte1 after demotion */
5397 pte1 = pte1_load(pte1p);
5403 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
5404 " is not link", __func__, pmap, sva, pte1, pte1p));
5407 * Limit our scan to either the end of the va represented
5408 * by the current L2 page table page, or to the end of the
5409 * range being protected.
5414 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva; pte2p++,
5416 pte2 = pte2_load(pte2p);
5417 if (!pte2_is_valid(pte2))
5419 if (!pte2_is_wired(pte2))
5420 panic("%s: pte2 %#x is missing PTE2_W",
5424 * PTE2_W must be cleared atomically. Although the pmap
5425 * lock synchronizes access to PTE2_W, another processor
5426 * could be changing PTE2_NM and/or PTE2_A concurrently.
5428 pte2_clear_bit(pte2p, PTE2_W);
5429 pmap->pm_stats.wired_count--;
5432 if (pv_lists_locked) {
5434 rw_wunlock(&pvh_global_lock);
5440 * Clear the write and modified bits in each of the given page's mappings.
5443 pmap_remove_write(vm_page_t m)
5445 struct md_page *pvh;
5446 pv_entry_t next_pv, pv;
5449 pt2_entry_t *pte2p, opte2;
5452 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5453 ("%s: page %p is not managed", __func__, m));
5456 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5457 * set by another thread while the object is locked. Thus,
5458 * if PGA_WRITEABLE is clear, no page table entries need updating.
5460 VM_OBJECT_ASSERT_WLOCKED(m->object);
5461 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5463 rw_wlock(&pvh_global_lock);
5465 if ((m->flags & PG_FICTITIOUS) != 0)
5466 goto small_mappings;
5467 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5468 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5472 pte1p = pmap_pte1(pmap, va);
5473 if (!(pte1_load(pte1p) & PTE1_RO))
5474 (void)pmap_demote_pte1(pmap, pte1p, va);
5478 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5481 pte1p = pmap_pte1(pmap, pv->pv_va);
5482 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found"
5483 " a section in page %p's pv list", __func__, m));
5484 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5485 opte2 = pte2_load(pte2p);
5486 if (!(opte2 & PTE2_RO)) {
5487 pte2_store(pte2p, opte2 | PTE2_RO | PTE2_NM);
5488 if (pte2_is_dirty(opte2))
5490 pmap_tlb_flush(pmap, pv->pv_va);
5494 vm_page_aflag_clear(m, PGA_WRITEABLE);
5496 rw_wunlock(&pvh_global_lock);
5500 * Apply the given advice to the specified range of addresses within the
5501 * given pmap. Depending on the advice, clear the referenced and/or
5502 * modified flags in each mapping and set the mapped page's dirty field.
5505 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5507 pt1_entry_t *pte1p, opte1;
5508 pt2_entry_t *pte2p, pte2;
5511 boolean_t pv_lists_locked;
5513 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5515 if (pmap_is_current(pmap))
5516 pv_lists_locked = FALSE;
5518 pv_lists_locked = TRUE;
5520 rw_wlock(&pvh_global_lock);
5524 for (; sva < eva; sva = pdnxt) {
5525 pdnxt = pte1_trunc(sva + PTE1_SIZE);
5528 pte1p = pmap_pte1(pmap, sva);
5529 opte1 = pte1_load(pte1p);
5530 if (!pte1_is_valid(opte1)) /* XXX */
5532 else if (pte1_is_section(opte1)) {
5533 if (!pte1_is_managed(opte1))
5535 if (!pv_lists_locked) {
5536 pv_lists_locked = TRUE;
5537 if (!rw_try_wlock(&pvh_global_lock)) {
5543 if (!pmap_demote_pte1(pmap, pte1p, sva)) {
5545 * The large page mapping was destroyed.
5551 * Unless the page mappings are wired, remove the
5552 * mapping to a single page so that a subsequent
5553 * access may repromote. Since the underlying L2 page
5554 * table is fully populated, this removal never
5555 * frees a L2 page table page.
5557 if (!pte1_is_wired(opte1)) {
5558 pte2p = pmap_pte2_quick(pmap, sva);
5559 KASSERT(pte2_is_valid(pte2_load(pte2p)),
5560 ("%s: invalid PTE2", __func__));
5561 pmap_remove_pte2(pmap, pte2p, sva, NULL);
5566 for (pte2p = pmap_pte2_quick(pmap, sva); sva != pdnxt; pte2p++,
5568 pte2 = pte2_load(pte2p);
5569 if (!pte2_is_valid(pte2) || !pte2_is_managed(pte2))
5571 else if (pte2_is_dirty(pte2)) {
5572 if (advice == MADV_DONTNEED) {
5574 * Future calls to pmap_is_modified()
5575 * can be avoided by making the page
5578 m = PHYS_TO_VM_PAGE(pte2_pa(pte2));
5581 pte2_set_bit(pte2p, PTE2_NM);
5582 pte2_clear_bit(pte2p, PTE2_A);
5583 } else if ((pte2 & PTE2_A) != 0)
5584 pte2_clear_bit(pte2p, PTE2_A);
5587 pmap_tlb_flush(pmap, sva);
5590 if (pv_lists_locked) {
5592 rw_wunlock(&pvh_global_lock);
5598 * Clear the modify bits on the specified physical page.
5601 pmap_clear_modify(vm_page_t m)
5603 struct md_page *pvh;
5604 pv_entry_t next_pv, pv;
5606 pt1_entry_t *pte1p, opte1;
5607 pt2_entry_t *pte2p, opte2;
5610 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5611 ("%s: page %p is not managed", __func__, m));
5612 VM_OBJECT_ASSERT_WLOCKED(m->object);
5613 KASSERT(!vm_page_xbusied(m),
5614 ("%s: page %p is exclusive busy", __func__, m));
5617 * If the page is not PGA_WRITEABLE, then no PTE2s can have PTE2_NM
5618 * cleared. If the object containing the page is locked and the page
5619 * is not exclusive busied, then PGA_WRITEABLE cannot be concurrently
5622 if ((m->flags & PGA_WRITEABLE) == 0)
5624 rw_wlock(&pvh_global_lock);
5626 if ((m->flags & PG_FICTITIOUS) != 0)
5627 goto small_mappings;
5628 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5629 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5633 pte1p = pmap_pte1(pmap, va);
5634 opte1 = pte1_load(pte1p);
5635 if (!(opte1 & PTE1_RO)) {
5636 if (pmap_demote_pte1(pmap, pte1p, va) &&
5637 !pte1_is_wired(opte1)) {
5639 * Write protect the mapping to a
5640 * single page so that a subsequent
5641 * write access may repromote.
5643 va += VM_PAGE_TO_PHYS(m) - pte1_pa(opte1);
5644 pte2p = pmap_pte2_quick(pmap, va);
5645 opte2 = pte2_load(pte2p);
5646 if ((opte2 & PTE2_V)) {
5647 pte2_set_bit(pte2p, PTE2_NM | PTE2_RO);
5649 pmap_tlb_flush(pmap, va);
5656 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5659 pte1p = pmap_pte1(pmap, pv->pv_va);
5660 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found"
5661 " a section in page %p's pv list", __func__, m));
5662 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5663 if (pte2_is_dirty(pte2_load(pte2p))) {
5664 pte2_set_bit(pte2p, PTE2_NM);
5665 pmap_tlb_flush(pmap, pv->pv_va);
5670 rw_wunlock(&pvh_global_lock);
5675 * Sets the memory attribute for the specified page.
5678 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5680 pt2_entry_t *cmap2_pte2p;
5685 oma = m->md.pat_mode;
5686 m->md.pat_mode = ma;
5688 CTR5(KTR_PMAP, "%s: page %p - 0x%08X oma: %d, ma: %d", __func__, m,
5689 VM_PAGE_TO_PHYS(m), oma, ma);
5690 if ((m->flags & PG_FICTITIOUS) != 0)
5694 * If "m" is a normal page, flush it from the cache.
5696 * First, try to find an existing mapping of the page by sf
5697 * buffer. sf_buf_invalidate_cache() modifies mapping and
5698 * flushes the cache.
5700 if (sf_buf_invalidate_cache(m, oma))
5704 * If page is not mapped by sf buffer, map the page
5705 * transient and do invalidation.
5708 pa = VM_PAGE_TO_PHYS(m);
5711 cmap2_pte2p = pc->pc_cmap2_pte2p;
5712 mtx_lock(&pc->pc_cmap_lock);
5713 if (pte2_load(cmap2_pte2p) != 0)
5714 panic("%s: CMAP2 busy", __func__);
5715 pte2_store(cmap2_pte2p, PTE2_KERN_NG(pa, PTE2_AP_KRW,
5716 vm_memattr_to_pte2(ma)));
5717 dcache_wbinv_poc((vm_offset_t)pc->pc_cmap2_addr, pa, PAGE_SIZE);
5718 pte2_clear(cmap2_pte2p);
5719 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5721 mtx_unlock(&pc->pc_cmap_lock);
5726 * Miscellaneous support routines follow
5730 * Returns TRUE if the given page is mapped individually or as part of
5731 * a 1mpage. Otherwise, returns FALSE.
5734 pmap_page_is_mapped(vm_page_t m)
5738 if ((m->oflags & VPO_UNMANAGED) != 0)
5740 rw_wlock(&pvh_global_lock);
5741 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5742 ((m->flags & PG_FICTITIOUS) == 0 &&
5743 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
5744 rw_wunlock(&pvh_global_lock);
5749 * Returns true if the pmap's pv is one of the first
5750 * 16 pvs linked to from this page. This count may
5751 * be changed upwards or downwards in the future; it
5752 * is only necessary that true be returned for a small
5753 * subset of pmaps for proper page aging.
5756 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5758 struct md_page *pvh;
5763 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5764 ("%s: page %p is not managed", __func__, m));
5766 rw_wlock(&pvh_global_lock);
5767 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5768 if (PV_PMAP(pv) == pmap) {
5776 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5777 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5778 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5779 if (PV_PMAP(pv) == pmap) {
5788 rw_wunlock(&pvh_global_lock);
5793 * pmap_zero_page zeros the specified hardware page by mapping
5794 * the page into KVM and using bzero to clear its contents.
5797 pmap_zero_page(vm_page_t m)
5799 pt2_entry_t *cmap2_pte2p;
5804 cmap2_pte2p = pc->pc_cmap2_pte2p;
5805 mtx_lock(&pc->pc_cmap_lock);
5806 if (pte2_load(cmap2_pte2p) != 0)
5807 panic("%s: CMAP2 busy", __func__);
5808 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5809 vm_page_pte2_attr(m)));
5810 pagezero(pc->pc_cmap2_addr);
5811 pte2_clear(cmap2_pte2p);
5812 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5814 mtx_unlock(&pc->pc_cmap_lock);
5818 * pmap_zero_page_area zeros the specified hardware page by mapping
5819 * the page into KVM and using bzero to clear its contents.
5821 * off and size may not cover an area beyond a single hardware page.
5824 pmap_zero_page_area(vm_page_t m, int off, int size)
5826 pt2_entry_t *cmap2_pte2p;
5831 cmap2_pte2p = pc->pc_cmap2_pte2p;
5832 mtx_lock(&pc->pc_cmap_lock);
5833 if (pte2_load(cmap2_pte2p) != 0)
5834 panic("%s: CMAP2 busy", __func__);
5835 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5836 vm_page_pte2_attr(m)));
5837 if (off == 0 && size == PAGE_SIZE)
5838 pagezero(pc->pc_cmap2_addr);
5840 bzero(pc->pc_cmap2_addr + off, size);
5841 pte2_clear(cmap2_pte2p);
5842 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5844 mtx_unlock(&pc->pc_cmap_lock);
5848 * pmap_copy_page copies the specified (machine independent)
5849 * page by mapping the page into virtual memory and using
5850 * bcopy to copy the page, one machine dependent page at a
5854 pmap_copy_page(vm_page_t src, vm_page_t dst)
5856 pt2_entry_t *cmap1_pte2p, *cmap2_pte2p;
5861 cmap1_pte2p = pc->pc_cmap1_pte2p;
5862 cmap2_pte2p = pc->pc_cmap2_pte2p;
5863 mtx_lock(&pc->pc_cmap_lock);
5864 if (pte2_load(cmap1_pte2p) != 0)
5865 panic("%s: CMAP1 busy", __func__);
5866 if (pte2_load(cmap2_pte2p) != 0)
5867 panic("%s: CMAP2 busy", __func__);
5868 pte2_store(cmap1_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(src),
5869 PTE2_AP_KR | PTE2_NM, vm_page_pte2_attr(src)));
5870 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(dst),
5871 PTE2_AP_KRW, vm_page_pte2_attr(dst)));
5872 bcopy(pc->pc_cmap1_addr, pc->pc_cmap2_addr, PAGE_SIZE);
5873 pte2_clear(cmap1_pte2p);
5874 tlb_flush((vm_offset_t)pc->pc_cmap1_addr);
5875 pte2_clear(cmap2_pte2p);
5876 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5878 mtx_unlock(&pc->pc_cmap_lock);
5881 int unmapped_buf_allowed = 1;
5884 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5885 vm_offset_t b_offset, int xfersize)
5887 pt2_entry_t *cmap1_pte2p, *cmap2_pte2p;
5888 vm_page_t a_pg, b_pg;
5890 vm_offset_t a_pg_offset, b_pg_offset;
5896 cmap1_pte2p = pc->pc_cmap1_pte2p;
5897 cmap2_pte2p = pc->pc_cmap2_pte2p;
5898 mtx_lock(&pc->pc_cmap_lock);
5899 if (pte2_load(cmap1_pte2p) != 0)
5900 panic("pmap_copy_pages: CMAP1 busy");
5901 if (pte2_load(cmap2_pte2p) != 0)
5902 panic("pmap_copy_pages: CMAP2 busy");
5903 while (xfersize > 0) {
5904 a_pg = ma[a_offset >> PAGE_SHIFT];
5905 a_pg_offset = a_offset & PAGE_MASK;
5906 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5907 b_pg = mb[b_offset >> PAGE_SHIFT];
5908 b_pg_offset = b_offset & PAGE_MASK;
5909 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5910 pte2_store(cmap1_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(a_pg),
5911 PTE2_AP_KR | PTE2_NM, vm_page_pte2_attr(a_pg)));
5912 tlb_flush_local((vm_offset_t)pc->pc_cmap1_addr);
5913 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(b_pg),
5914 PTE2_AP_KRW, vm_page_pte2_attr(b_pg)));
5915 tlb_flush_local((vm_offset_t)pc->pc_cmap2_addr);
5916 a_cp = pc->pc_cmap1_addr + a_pg_offset;
5917 b_cp = pc->pc_cmap2_addr + b_pg_offset;
5918 bcopy(a_cp, b_cp, cnt);
5923 pte2_clear(cmap1_pte2p);
5924 tlb_flush((vm_offset_t)pc->pc_cmap1_addr);
5925 pte2_clear(cmap2_pte2p);
5926 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5928 mtx_unlock(&pc->pc_cmap_lock);
5932 pmap_quick_enter_page(vm_page_t m)
5939 pte2p = pc->pc_qmap_pte2p;
5941 KASSERT(pte2_load(pte2p) == 0, ("%s: PTE2 busy", __func__));
5943 pte2_store(pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5944 vm_page_pte2_attr(m)));
5945 return (pc->pc_qmap_addr);
5949 pmap_quick_remove_page(vm_offset_t addr)
5955 pte2p = pc->pc_qmap_pte2p;
5957 KASSERT(addr == pc->pc_qmap_addr, ("%s: invalid address", __func__));
5958 KASSERT(pte2_load(pte2p) != 0, ("%s: PTE2 not in use", __func__));
5961 tlb_flush(pc->pc_qmap_addr);
5966 * Copy the range specified by src_addr/len
5967 * from the source map to the range dst_addr/len
5968 * in the destination map.
5970 * This routine is only advisory and need not do anything.
5973 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
5974 vm_offset_t src_addr)
5976 struct spglist free;
5978 vm_offset_t end_addr = src_addr + len;
5981 if (dst_addr != src_addr)
5984 if (!pmap_is_current(src_pmap))
5987 rw_wlock(&pvh_global_lock);
5988 if (dst_pmap < src_pmap) {
5989 PMAP_LOCK(dst_pmap);
5990 PMAP_LOCK(src_pmap);
5992 PMAP_LOCK(src_pmap);
5993 PMAP_LOCK(dst_pmap);
5996 for (addr = src_addr; addr < end_addr; addr = nextva) {
5997 pt2_entry_t *src_pte2p, *dst_pte2p;
5998 vm_page_t dst_mpt2pg, src_mpt2pg;
5999 pt1_entry_t src_pte1;
6002 KASSERT(addr < VM_MAXUSER_ADDRESS,
6003 ("%s: invalid to pmap_copy page tables", __func__));
6005 nextva = pte1_trunc(addr + PTE1_SIZE);
6009 pte1_idx = pte1_index(addr);
6010 src_pte1 = src_pmap->pm_pt1[pte1_idx];
6011 if (pte1_is_section(src_pte1)) {
6012 if ((addr & PTE1_OFFSET) != 0 ||
6013 (addr + PTE1_SIZE) > end_addr)
6015 if (dst_pmap->pm_pt1[pte1_idx] == 0 &&
6016 (!pte1_is_managed(src_pte1) ||
6017 pmap_pv_insert_pte1(dst_pmap, addr,
6018 pte1_pa(src_pte1)))) {
6019 dst_pmap->pm_pt1[pte1_idx] = src_pte1 &
6021 dst_pmap->pm_stats.resident_count +=
6022 PTE1_SIZE / PAGE_SIZE;
6023 pmap_pte1_mappings++;
6026 } else if (!pte1_is_link(src_pte1))
6029 src_mpt2pg = PHYS_TO_VM_PAGE(pte1_link_pa(src_pte1));
6032 * We leave PT2s to be linked from PT1 even if they are not
6033 * referenced until all PT2s in a page are without reference.
6035 * QQQ: It could be changed ...
6037 #if 0 /* single_pt2_link_is_cleared */
6038 KASSERT(pt2_wirecount_get(src_mpt2pg, pte1_idx) > 0,
6039 ("%s: source page table page is unused", __func__));
6041 if (pt2_wirecount_get(src_mpt2pg, pte1_idx) == 0)
6044 if (nextva > end_addr)
6047 src_pte2p = pt2map_entry(addr);
6048 while (addr < nextva) {
6049 pt2_entry_t temp_pte2;
6050 temp_pte2 = pte2_load(src_pte2p);
6052 * we only virtual copy managed pages
6054 if (pte2_is_managed(temp_pte2)) {
6055 dst_mpt2pg = pmap_allocpte2(dst_pmap, addr,
6056 PMAP_ENTER_NOSLEEP);
6057 if (dst_mpt2pg == NULL)
6059 dst_pte2p = pmap_pte2_quick(dst_pmap, addr);
6060 if (!pte2_is_valid(pte2_load(dst_pte2p)) &&
6061 pmap_try_insert_pv_entry(dst_pmap, addr,
6062 PHYS_TO_VM_PAGE(pte2_pa(temp_pte2)))) {
6064 * Clear the wired, modified, and
6065 * accessed (referenced) bits
6068 temp_pte2 &= ~(PTE2_W | PTE2_A);
6069 temp_pte2 |= PTE2_NM;
6070 pte2_store(dst_pte2p, temp_pte2);
6071 dst_pmap->pm_stats.resident_count++;
6074 if (pmap_unwire_pt2(dst_pmap, addr,
6075 dst_mpt2pg, &free)) {
6076 pmap_tlb_flush(dst_pmap, addr);
6077 pmap_free_zero_pages(&free);
6081 if (pt2_wirecount_get(dst_mpt2pg, pte1_idx) >=
6082 pt2_wirecount_get(src_mpt2pg, pte1_idx))
6091 rw_wunlock(&pvh_global_lock);
6092 PMAP_UNLOCK(src_pmap);
6093 PMAP_UNLOCK(dst_pmap);
6097 * Increase the starting virtual address of the given mapping if a
6098 * different alignment might result in more section mappings.
6101 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6102 vm_offset_t *addr, vm_size_t size)
6104 vm_offset_t pte1_offset;
6106 if (size < PTE1_SIZE)
6108 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6109 offset += ptoa(object->pg_color);
6110 pte1_offset = offset & PTE1_OFFSET;
6111 if (size - ((PTE1_SIZE - pte1_offset) & PTE1_OFFSET) < PTE1_SIZE ||
6112 (*addr & PTE1_OFFSET) == pte1_offset)
6114 if ((*addr & PTE1_OFFSET) < pte1_offset)
6115 *addr = pte1_trunc(*addr) + pte1_offset;
6117 *addr = pte1_roundup(*addr) + pte1_offset;
6121 pmap_activate(struct thread *td)
6123 pmap_t pmap, oldpmap;
6126 PDEBUG(9, printf("%s: td = %08x\n", __func__, (uint32_t)td));
6129 pmap = vmspace_pmap(td->td_proc->p_vmspace);
6130 oldpmap = PCPU_GET(curpmap);
6131 cpuid = PCPU_GET(cpuid);
6134 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
6135 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
6137 CPU_CLR(cpuid, &oldpmap->pm_active);
6138 CPU_SET(cpuid, &pmap->pm_active);
6141 ttb = pmap_ttb_get(pmap);
6144 * pmap_activate is for the current thread on the current cpu
6146 td->td_pcb->pcb_pagedir = ttb;
6148 PCPU_SET(curpmap, pmap);
6153 * Perform the pmap work for mincore.
6156 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
6158 pt1_entry_t *pte1p, pte1;
6159 pt2_entry_t *pte2p, pte2;
6166 pte1p = pmap_pte1(pmap, addr);
6167 pte1 = pte1_load(pte1p);
6168 if (pte1_is_section(pte1)) {
6169 pa = trunc_page(pte1_pa(pte1) | (addr & PTE1_OFFSET));
6170 managed = pte1_is_managed(pte1);
6171 val = MINCORE_SUPER | MINCORE_INCORE;
6172 if (pte1_is_dirty(pte1))
6173 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6175 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6176 } else if (pte1_is_link(pte1)) {
6177 pte2p = pmap_pte2(pmap, addr);
6178 pte2 = pte2_load(pte2p);
6179 pmap_pte2_release(pte2p);
6181 managed = pte2_is_managed(pte2);
6182 val = MINCORE_INCORE;
6183 if (pte2_is_dirty(pte2))
6184 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6186 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6191 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
6192 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
6193 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
6194 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
6197 PA_UNLOCK_COND(*locked_pa);
6203 pmap_kenter_device(vm_offset_t va, vm_size_t size, vm_paddr_t pa)
6208 KASSERT((size & PAGE_MASK) == 0,
6209 ("%s: device mapping not page-sized", __func__));
6212 l2attr = vm_memattr_to_pte2(VM_MEMATTR_DEVICE);
6214 pmap_kenter_prot_attr(va, pa, PTE2_AP_KRW, l2attr);
6219 tlb_flush_range(sva, va - sva);
6223 pmap_kremove_device(vm_offset_t va, vm_size_t size)
6227 KASSERT((size & PAGE_MASK) == 0,
6228 ("%s: device mapping not page-sized", __func__));
6236 tlb_flush_range(sva, va - sva);
6240 pmap_set_pcb_pagedir(pmap_t pmap, struct pcb *pcb)
6243 pcb->pcb_pagedir = pmap_ttb_get(pmap);
6248 * Clean L1 data cache range by physical address.
6249 * The range must be within a single page.
6252 pmap_dcache_wb_pou(vm_paddr_t pa, vm_size_t size, uint32_t attr)
6254 pt2_entry_t *cmap2_pte2p;
6257 KASSERT(((pa & PAGE_MASK) + size) <= PAGE_SIZE,
6258 ("%s: not on single page", __func__));
6262 cmap2_pte2p = pc->pc_cmap2_pte2p;
6263 mtx_lock(&pc->pc_cmap_lock);
6264 if (pte2_load(cmap2_pte2p) != 0)
6265 panic("%s: CMAP2 busy", __func__);
6266 pte2_store(cmap2_pte2p, PTE2_KERN_NG(pa, PTE2_AP_KRW, attr));
6267 dcache_wb_pou((vm_offset_t)pc->pc_cmap2_addr + (pa & PAGE_MASK), size);
6268 pte2_clear(cmap2_pte2p);
6269 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
6271 mtx_unlock(&pc->pc_cmap_lock);
6275 * Sync instruction cache range which is not mapped yet.
6278 cache_icache_sync_fresh(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
6280 uint32_t len, offset;
6283 /* Write back d-cache on given address range. */
6284 offset = pa & PAGE_MASK;
6285 for ( ; size != 0; size -= len, pa += len, offset = 0) {
6286 len = min(PAGE_SIZE - offset, size);
6287 m = PHYS_TO_VM_PAGE(pa);
6288 KASSERT(m != NULL, ("%s: vm_page_t is null for %#x",
6290 pmap_dcache_wb_pou(pa, len, vm_page_pte2_attr(m));
6293 * I-cache is VIPT. Only way how to flush all virtual mappings
6294 * on given physical address is to invalidate all i-cache.
6300 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t size)
6303 /* Write back d-cache on given address range. */
6304 if (va >= VM_MIN_KERNEL_ADDRESS) {
6305 dcache_wb_pou(va, size);
6307 uint32_t len, offset;
6311 offset = va & PAGE_MASK;
6312 for ( ; size != 0; size -= len, va += len, offset = 0) {
6313 pa = pmap_extract(pmap, va); /* offset is preserved */
6314 len = min(PAGE_SIZE - offset, size);
6315 m = PHYS_TO_VM_PAGE(pa);
6316 KASSERT(m != NULL, ("%s: vm_page_t is null for %#x",
6318 pmap_dcache_wb_pou(pa, len, vm_page_pte2_attr(m));
6322 * I-cache is VIPT. Only way how to flush all virtual mappings
6323 * on given physical address is to invalidate all i-cache.
6329 * The implementation of pmap_fault() uses IN_RANGE2() macro which
6330 * depends on the fact that given range size is a power of 2.
6332 CTASSERT(powerof2(NB_IN_PT1));
6333 CTASSERT(powerof2(PT2MAP_SIZE));
6335 #define IN_RANGE2(addr, start, size) \
6336 ((vm_offset_t)(start) == ((vm_offset_t)(addr) & ~((size) - 1)))
6339 * Handle access and R/W emulation faults.
6342 pmap_fault(pmap_t pmap, vm_offset_t far, uint32_t fsr, int idx, bool usermode)
6344 pt1_entry_t *pte1p, pte1;
6345 pt2_entry_t *pte2p, pte2;
6351 * In kernel, we should never get abort with FAR which is in range of
6352 * pmap->pm_pt1 or PT2MAP address spaces. If it happens, stop here
6353 * and print out a useful abort message and even get to the debugger
6354 * otherwise it likely ends with never ending loop of aborts.
6356 if (__predict_false(IN_RANGE2(far, pmap->pm_pt1, NB_IN_PT1))) {
6358 * All L1 tables should always be mapped and present.
6359 * However, we check only current one herein. For user mode,
6360 * only permission abort from malicious user is not fatal.
6361 * And alignment abort as it may have higher priority.
6363 if (!usermode || (idx != FAULT_ALIGN && idx != FAULT_PERM_L2)) {
6364 CTR4(KTR_PMAP, "%s: pmap %#x pm_pt1 %#x far %#x",
6365 __func__, pmap, pmap->pm_pt1, far);
6366 panic("%s: pm_pt1 abort", __func__);
6368 return (KERN_INVALID_ADDRESS);
6370 if (__predict_false(IN_RANGE2(far, PT2MAP, PT2MAP_SIZE))) {
6372 * PT2MAP should be always mapped and present in current
6373 * L1 table. However, only existing L2 tables are mapped
6374 * in PT2MAP. For user mode, only L2 translation abort and
6375 * permission abort from malicious user is not fatal.
6376 * And alignment abort as it may have higher priority.
6378 if (!usermode || (idx != FAULT_ALIGN &&
6379 idx != FAULT_TRAN_L2 && idx != FAULT_PERM_L2)) {
6380 CTR4(KTR_PMAP, "%s: pmap %#x PT2MAP %#x far %#x",
6381 __func__, pmap, PT2MAP, far);
6382 panic("%s: PT2MAP abort", __func__);
6384 return (KERN_INVALID_ADDRESS);
6388 * A pmap lock is used below for handling of access and R/W emulation
6389 * aborts. They were handled by atomic operations before so some
6390 * analysis of new situation is needed to answer the following question:
6391 * Is it safe to use the lock even for these aborts?
6393 * There may happen two cases in general:
6395 * (1) Aborts while the pmap lock is locked already - this should not
6396 * happen as pmap lock is not recursive. However, under pmap lock only
6397 * internal kernel data should be accessed and such data should be
6398 * mapped with A bit set and NM bit cleared. If double abort happens,
6399 * then a mapping of data which has caused it must be fixed. Further,
6400 * all new mappings are always made with A bit set and the bit can be
6401 * cleared only on managed mappings.
6403 * (2) Aborts while another lock(s) is/are locked - this already can
6404 * happen. However, there is no difference here if it's either access or
6405 * R/W emulation abort, or if it's some other abort.
6410 pte1 = pte1_load(pmap_pte1(pmap, far));
6411 if (pte1_is_link(pte1)) {
6413 * Check in advance that associated L2 page table is mapped into
6414 * PT2MAP space. Note that faulty access to not mapped L2 page
6415 * table is caught in more general check above where "far" is
6416 * checked that it does not lay in PT2MAP space. Note also that
6417 * L1 page table and PT2TAB always exist and are mapped.
6419 pte2 = pt2tab_load(pmap_pt2tab_entry(pmap, far));
6420 if (!pte2_is_valid(pte2))
6421 panic("%s: missing L2 page table (%p, %#x)",
6422 __func__, pmap, far);
6427 * Special treatment is due to break-before-make approach done when
6428 * pte1 is updated for userland mapping during section promotion or
6429 * demotion. If not caught here, pmap_enter() can find a section
6430 * mapping on faulting address. That is not allowed.
6432 if (idx == FAULT_TRAN_L1 && usermode && cp15_ats1cur_check(far) == 0) {
6434 return (KERN_SUCCESS);
6438 * Accesss bits for page and section. Note that the entry
6439 * is not in TLB yet, so TLB flush is not necessary.
6441 * QQQ: This is hardware emulation, we do not call userret()
6442 * for aborts from user mode.
6444 if (idx == FAULT_ACCESS_L2) {
6445 pte1 = pte1_load(pmap_pte1(pmap, far));
6446 if (pte1_is_link(pte1)) {
6447 /* L2 page table should exist and be mapped. */
6448 pte2p = pt2map_entry(far);
6449 pte2 = pte2_load(pte2p);
6450 if (pte2_is_valid(pte2)) {
6451 pte2_store(pte2p, pte2 | PTE2_A);
6453 return (KERN_SUCCESS);
6457 * We got L2 access fault but PTE1 is not a link.
6458 * Probably some race happened, do nothing.
6460 CTR3(KTR_PMAP, "%s: FAULT_ACCESS_L2 - pmap %#x far %#x",
6461 __func__, pmap, far);
6463 return (KERN_SUCCESS);
6466 if (idx == FAULT_ACCESS_L1) {
6467 pte1p = pmap_pte1(pmap, far);
6468 pte1 = pte1_load(pte1p);
6469 if (pte1_is_section(pte1)) {
6470 pte1_store(pte1p, pte1 | PTE1_A);
6472 return (KERN_SUCCESS);
6475 * We got L1 access fault but PTE1 is not section
6476 * mapping. Probably some race happened, do nothing.
6478 CTR3(KTR_PMAP, "%s: FAULT_ACCESS_L1 - pmap %#x far %#x",
6479 __func__, pmap, far);
6481 return (KERN_SUCCESS);
6486 * Handle modify bits for page and section. Note that the modify
6487 * bit is emulated by software. So PTEx_RO is software read only
6488 * bit and PTEx_NM flag is real hardware read only bit.
6490 * QQQ: This is hardware emulation, we do not call userret()
6491 * for aborts from user mode.
6493 if ((fsr & FSR_WNR) && (idx == FAULT_PERM_L2)) {
6494 pte1 = pte1_load(pmap_pte1(pmap, far));
6495 if (pte1_is_link(pte1)) {
6496 /* L2 page table should exist and be mapped. */
6497 pte2p = pt2map_entry(far);
6498 pte2 = pte2_load(pte2p);
6499 if (pte2_is_valid(pte2) && !(pte2 & PTE2_RO) &&
6501 pte2_store(pte2p, pte2 & ~PTE2_NM);
6502 tlb_flush(trunc_page(far));
6504 return (KERN_SUCCESS);
6508 * We got L2 permission fault but PTE1 is not a link.
6509 * Probably some race happened, do nothing.
6511 CTR3(KTR_PMAP, "%s: FAULT_PERM_L2 - pmap %#x far %#x",
6512 __func__, pmap, far);
6514 return (KERN_SUCCESS);
6517 if ((fsr & FSR_WNR) && (idx == FAULT_PERM_L1)) {
6518 pte1p = pmap_pte1(pmap, far);
6519 pte1 = pte1_load(pte1p);
6520 if (pte1_is_section(pte1)) {
6521 if (!(pte1 & PTE1_RO) && (pte1 & PTE1_NM)) {
6522 pte1_store(pte1p, pte1 & ~PTE1_NM);
6523 tlb_flush(pte1_trunc(far));
6525 return (KERN_SUCCESS);
6529 * We got L1 permission fault but PTE1 is not section
6530 * mapping. Probably some race happened, do nothing.
6532 CTR3(KTR_PMAP, "%s: FAULT_PERM_L1 - pmap %#x far %#x",
6533 __func__, pmap, far);
6535 return (KERN_SUCCESS);
6540 * QQQ: The previous code, mainly fast handling of access and
6541 * modify bits aborts, could be moved to ASM. Now we are
6542 * starting to deal with not fast aborts.
6545 return (KERN_FAILURE);
6548 #if defined(PMAP_DEBUG)
6550 * Reusing of KVA used in pmap_zero_page function !!!
6553 pmap_zero_page_check(vm_page_t m)
6555 pt2_entry_t *cmap2_pte2p;
6561 cmap2_pte2p = pc->pc_cmap2_pte2p;
6562 mtx_lock(&pc->pc_cmap_lock);
6563 if (pte2_load(cmap2_pte2p) != 0)
6564 panic("%s: CMAP2 busy", __func__);
6565 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
6566 vm_page_pte2_attr(m)));
6567 end = (uint32_t*)(pc->pc_cmap2_addr + PAGE_SIZE);
6568 for (p = (uint32_t*)pc->pc_cmap2_addr; p < end; p++)
6570 panic("%s: page %p not zero, va: %p", __func__, m,
6572 pte2_clear(cmap2_pte2p);
6573 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
6575 mtx_unlock(&pc->pc_cmap_lock);
6579 pmap_pid_dump(int pid)
6586 sx_slock(&allproc_lock);
6587 FOREACH_PROC_IN_SYSTEM(p) {
6588 if (p->p_pid != pid || p->p_vmspace == NULL)
6591 pmap = vmspace_pmap(p->p_vmspace);
6592 for (i = 0; i < NPTE1_IN_PT1; i++) {
6594 pt2_entry_t *pte2p, pte2;
6595 vm_offset_t base, va;
6599 base = i << PTE1_SHIFT;
6600 pte1 = pte1_load(&pmap->pm_pt1[i]);
6602 if (pte1_is_section(pte1)) {
6604 * QQQ: Do something here!
6606 } else if (pte1_is_link(pte1)) {
6607 for (j = 0; j < NPTE2_IN_PT2; j++) {
6608 va = base + (j << PAGE_SHIFT);
6609 if (va >= VM_MIN_KERNEL_ADDRESS) {
6614 sx_sunlock(&allproc_lock);
6617 pte2p = pmap_pte2(pmap, va);
6618 pte2 = pte2_load(pte2p);
6619 pmap_pte2_release(pte2p);
6620 if (!pte2_is_valid(pte2))
6624 m = PHYS_TO_VM_PAGE(pa);
6625 printf("va: 0x%x, pa: 0x%x, h: %d, w:"
6626 " %d, f: 0x%x", va, pa,
6627 m->hold_count, m->wire_count,
6641 sx_sunlock(&allproc_lock);
6648 static pt2_entry_t *
6649 pmap_pte2_ddb(pmap_t pmap, vm_offset_t va)
6652 vm_paddr_t pt2pg_pa;
6654 pte1 = pte1_load(pmap_pte1(pmap, va));
6655 if (!pte1_is_link(pte1))
6658 if (pmap_is_current(pmap))
6659 return (pt2map_entry(va));
6661 /* Note that L2 page table size is not equal to PAGE_SIZE. */
6662 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
6663 if (pte2_pa(pte2_load(PMAP3)) != pt2pg_pa) {
6664 pte2_store(PMAP3, PTE2_KPT(pt2pg_pa));
6666 PMAP3cpu = PCPU_GET(cpuid);
6668 tlb_flush_local((vm_offset_t)PADDR3);
6671 else if (PMAP3cpu != PCPU_GET(cpuid)) {
6672 PMAP3cpu = PCPU_GET(cpuid);
6673 tlb_flush_local((vm_offset_t)PADDR3);
6676 return (PADDR3 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
6680 dump_pmap(pmap_t pmap)
6683 printf("pmap %p\n", pmap);
6684 printf(" pm_pt1: %p\n", pmap->pm_pt1);
6685 printf(" pm_pt2tab: %p\n", pmap->pm_pt2tab);
6686 printf(" pm_active: 0x%08lX\n", pmap->pm_active.__bits[0]);
6689 DB_SHOW_COMMAND(pmaps, pmap_list_pmaps)
6693 LIST_FOREACH(pmap, &allpmaps, pm_list) {
6699 pte2_class(pt2_entry_t pte2)
6703 cls = (pte2 >> 2) & 0x03;
6704 cls |= (pte2 >> 4) & 0x04;
6709 dump_section(pmap_t pmap, uint32_t pte1_idx)
6714 dump_link(pmap_t pmap, uint32_t pte1_idx, boolean_t invalid_ok)
6718 pt2_entry_t *pte2p, pte2;
6721 va = pte1_idx << PTE1_SHIFT;
6722 pte2p = pmap_pte2_ddb(pmap, va);
6723 for (i = 0; i < NPTE2_IN_PT2; i++, pte2p++, va += PAGE_SIZE) {
6724 pte2 = pte2_load(pte2p);
6727 if (!pte2_is_valid(pte2)) {
6728 printf(" 0x%08X: 0x%08X", va, pte2);
6730 printf(" - not valid !!!");
6734 m = PHYS_TO_VM_PAGE(pte2_pa(pte2));
6735 printf(" 0x%08X: 0x%08X, TEX%d, s:%d, g:%d, m:%p", va , pte2,
6736 pte2_class(pte2), !!(pte2 & PTE2_S), !(pte2 & PTE2_NG), m);
6738 printf(" v:%d h:%d w:%d f:0x%04X\n", m->valid,
6739 m->hold_count, m->wire_count, m->flags);
6746 static __inline boolean_t
6747 is_pv_chunk_space(vm_offset_t va)
6750 if ((((vm_offset_t)pv_chunkbase) <= va) &&
6751 (va < ((vm_offset_t)pv_chunkbase + PAGE_SIZE * pv_maxchunks)))
6756 DB_SHOW_COMMAND(pmap, pmap_pmap_print)
6758 /* XXX convert args. */
6759 pmap_t pmap = (pmap_t)addr;
6762 vm_offset_t va, eva;
6765 boolean_t invalid_ok, dump_link_ok, dump_pv_chunk;
6770 LIST_FOREACH(pm, &allpmaps, pm_list)
6771 if (pm == pmap) break;
6773 printf("given pmap %p is not in allpmaps list\n", pmap);
6777 pmap = PCPU_GET(curpmap);
6779 eva = (modif[0] == 'u') ? VM_MAXUSER_ADDRESS : 0xFFFFFFFF;
6780 dump_pv_chunk = FALSE; /* XXX evaluate from modif[] */
6782 printf("pmap: 0x%08X\n", (uint32_t)pmap);
6783 printf("PT2MAP: 0x%08X\n", (uint32_t)PT2MAP);
6784 printf("pt2tab: 0x%08X\n", (uint32_t)pmap->pm_pt2tab);
6786 for(i = 0; i < NPTE1_IN_PT1; i++) {
6787 pte1 = pte1_load(&pmap->pm_pt1[i]);
6790 va = i << PTE1_SHIFT;
6794 if (pte1_is_section(pte1)) {
6795 printf("0x%08X: Section 0x%08X, s:%d g:%d\n", va, pte1,
6796 !!(pte1 & PTE1_S), !(pte1 & PTE1_NG));
6797 dump_section(pmap, i);
6798 } else if (pte1_is_link(pte1)) {
6799 dump_link_ok = TRUE;
6801 pte2 = pte2_load(pmap_pt2tab_entry(pmap, va));
6802 m = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
6803 printf("0x%08X: Link 0x%08X, pt2tab: 0x%08X m: %p",
6805 if (is_pv_chunk_space(va)) {
6806 printf(" - pv_chunk space");
6810 dump_link_ok = FALSE;
6813 printf(" w:%d w2:%u", m->wire_count,
6814 pt2_wirecount_get(m, pte1_index(va)));
6816 printf(" !!! pt2tab entry is ZERO");
6817 else if (pte2_pa(pte1) != pte2_pa(pte2))
6818 printf(" !!! pt2tab entry is DIFFERENT - m: %p",
6819 PHYS_TO_VM_PAGE(pte2_pa(pte2)));
6822 dump_link(pmap, i, invalid_ok);
6824 printf("0x%08X: Invalid entry 0x%08X\n", va, pte1);
6829 dump_pt2tab(pmap_t pmap)
6837 printf("PT2TAB:\n");
6838 for (i = 0; i < PT2TAB_ENTRIES; i++) {
6839 pte2 = pte2_load(&pmap->pm_pt2tab[i]);
6840 if (!pte2_is_valid(pte2))
6842 va = i << PT2TAB_SHIFT;
6844 m = PHYS_TO_VM_PAGE(pa);
6845 printf(" 0x%08X: 0x%08X, TEX%d, s:%d, m:%p", va, pte2,
6846 pte2_class(pte2), !!(pte2 & PTE2_S), m);
6848 printf(" , h: %d, w: %d, f: 0x%04X pidx: %lld",
6849 m->hold_count, m->wire_count, m->flags, m->pindex);
6854 DB_SHOW_COMMAND(pmap_pt2tab, pmap_pt2tab_print)
6856 /* XXX convert args. */
6857 pmap_t pmap = (pmap_t)addr;
6864 printf("supported only on current pmap\n");
6868 pmap = PCPU_GET(curpmap);
6869 printf("curpmap: 0x%08X\n", (uint32_t)pmap);
6870 printf("PT2MAP: 0x%08X\n", (uint32_t)PT2MAP);
6871 printf("pt2tab: 0x%08X\n", (uint32_t)pmap->pm_pt2tab);
6873 start = pte1_index((vm_offset_t)PT2MAP);
6874 for (i = start; i < (start + NPT2_IN_PT2TAB); i++) {
6875 pte1 = pte1_load(&pmap->pm_pt1[i]);
6878 va = i << PTE1_SHIFT;
6879 if (pte1_is_section(pte1)) {
6880 printf("0x%08X: Section 0x%08X, s:%d\n", va, pte1,
6882 dump_section(pmap, i);
6883 } else if (pte1_is_link(pte1)) {
6884 pte2 = pte2_load(pmap_pt2tab_entry(pmap, va));
6885 printf("0x%08X: Link 0x%08X, pt2tab: 0x%08X\n", va,
6888 printf(" !!! pt2tab entry is ZERO\n");
6890 printf("0x%08X: Invalid entry 0x%08X\n", va, pte1);