2 * SPDX-License-Identifier: BSD-3-Clause AND BSD-2-Clause-FreeBSD
4 * Copyright (c) 1991 Regents of the University of California.
5 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
7 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
8 * Copyright (c) 2014-2016 Svatopluk Kraus <skra@FreeBSD.org>
9 * Copyright (c) 2014-2016 Michal Meloun <mmel@FreeBSD.org>
10 * All rights reserved.
12 * This code is derived from software contributed to Berkeley by
13 * the Systems Programming Group of the University of Utah Computer
14 * Science Department and William Jolitz of UUNET Technologies Inc.
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions
19 * 1. Redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution.
24 * 3. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
43 * Copyright (c) 2003 Networks Associates Technology, Inc.
44 * All rights reserved.
46 * This software was developed for the FreeBSD Project by Jake Burkholder,
47 * Safeport Network Services, and Network Associates Laboratories, the
48 * Security Research Division of Network Associates, Inc. under
49 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
50 * CHATS research program.
52 * Redistribution and use in source and binary forms, with or without
53 * modification, are permitted provided that the following conditions
55 * 1. Redistributions of source code must retain the above copyright
56 * notice, this list of conditions and the following disclaimer.
57 * 2. Redistributions in binary form must reproduce the above copyright
58 * notice, this list of conditions and the following disclaimer in the
59 * documentation and/or other materials provided with the distribution.
61 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
62 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
64 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
74 #include <sys/cdefs.h>
75 __FBSDID("$FreeBSD$");
78 * Manages physical address maps.
80 * Since the information managed by this module is
81 * also stored by the logical address mapping module,
82 * this module may throw away valid virtual-to-physical
83 * mappings at almost any time. However, invalidations
84 * of virtual-to-physical mappings must be done as
87 * In order to cope with hardware architectures which
88 * make virtual-to-physical map invalidates expensive,
89 * this module may delay invalidate or reduced protection
90 * operations until such time as they are actually
91 * necessary. This module is given full information as
92 * to which processors are currently using which maps,
93 * and to when physical maps must be made correct.
100 #include <sys/param.h>
101 #include <sys/systm.h>
102 #include <sys/kernel.h>
104 #include <sys/lock.h>
105 #include <sys/proc.h>
106 #include <sys/rwlock.h>
107 #include <sys/malloc.h>
108 #include <sys/vmmeter.h>
109 #include <sys/malloc.h>
110 #include <sys/mman.h>
111 #include <sys/sf_buf.h>
113 #include <sys/sched.h>
114 #include <sys/sysctl.h>
120 #include <machine/physmem.h>
125 #include <vm/vm_param.h>
126 #include <vm/vm_kern.h>
127 #include <vm/vm_object.h>
128 #include <vm/vm_map.h>
129 #include <vm/vm_page.h>
130 #include <vm/vm_pageout.h>
131 #include <vm/vm_phys.h>
132 #include <vm/vm_extern.h>
133 #include <vm/vm_reserv.h>
134 #include <sys/lock.h>
135 #include <sys/mutex.h>
137 #include <machine/md_var.h>
138 #include <machine/pmap_var.h>
139 #include <machine/cpu.h>
140 #include <machine/pcb.h>
141 #include <machine/sf_buf.h>
143 #include <machine/smp.h>
145 #ifndef PMAP_SHPGPERPROC
146 #define PMAP_SHPGPERPROC 200
150 #define PMAP_INLINE __inline
156 static void pmap_zero_page_check(vm_page_t m);
157 void pmap_debug(int level);
158 int pmap_pid_dump(int pid);
160 #define PDEBUG(_lev_,_stat_) \
161 if (pmap_debug_level >= (_lev_)) \
163 #define dprintf printf
164 int pmap_debug_level = 1;
165 #else /* PMAP_DEBUG */
166 #define PDEBUG(_lev_,_stat_) /* Nothing */
167 #define dprintf(x, arg...)
168 #endif /* PMAP_DEBUG */
171 * Level 2 page tables map definion ('max' is excluded).
174 #define PT2V_MIN_ADDRESS ((vm_offset_t)PT2MAP)
175 #define PT2V_MAX_ADDRESS ((vm_offset_t)PT2MAP + PT2MAP_SIZE)
177 #define UPT2V_MIN_ADDRESS ((vm_offset_t)PT2MAP)
178 #define UPT2V_MAX_ADDRESS \
179 ((vm_offset_t)(PT2MAP + (KERNBASE >> PT2MAP_SHIFT)))
182 * Promotion to a 1MB (PTE1) page mapping requires that the corresponding
183 * 4KB (PTE2) page mappings have identical settings for the following fields:
185 #define PTE2_PROMOTE (PTE2_V | PTE2_A | PTE2_NM | PTE2_S | PTE2_NG | \
186 PTE2_NX | PTE2_RO | PTE2_U | PTE2_W | \
189 #define PTE1_PROMOTE (PTE1_V | PTE1_A | PTE1_NM | PTE1_S | PTE1_NG | \
190 PTE1_NX | PTE1_RO | PTE1_U | PTE1_W | \
193 #define ATTR_TO_L1(l2_attr) ((((l2_attr) & L2_TEX0) ? L1_S_TEX0 : 0) | \
194 (((l2_attr) & L2_C) ? L1_S_C : 0) | \
195 (((l2_attr) & L2_B) ? L1_S_B : 0) | \
196 (((l2_attr) & PTE2_A) ? PTE1_A : 0) | \
197 (((l2_attr) & PTE2_NM) ? PTE1_NM : 0) | \
198 (((l2_attr) & PTE2_S) ? PTE1_S : 0) | \
199 (((l2_attr) & PTE2_NG) ? PTE1_NG : 0) | \
200 (((l2_attr) & PTE2_NX) ? PTE1_NX : 0) | \
201 (((l2_attr) & PTE2_RO) ? PTE1_RO : 0) | \
202 (((l2_attr) & PTE2_U) ? PTE1_U : 0) | \
203 (((l2_attr) & PTE2_W) ? PTE1_W : 0))
205 #define ATTR_TO_L2(l1_attr) ((((l1_attr) & L1_S_TEX0) ? L2_TEX0 : 0) | \
206 (((l1_attr) & L1_S_C) ? L2_C : 0) | \
207 (((l1_attr) & L1_S_B) ? L2_B : 0) | \
208 (((l1_attr) & PTE1_A) ? PTE2_A : 0) | \
209 (((l1_attr) & PTE1_NM) ? PTE2_NM : 0) | \
210 (((l1_attr) & PTE1_S) ? PTE2_S : 0) | \
211 (((l1_attr) & PTE1_NG) ? PTE2_NG : 0) | \
212 (((l1_attr) & PTE1_NX) ? PTE2_NX : 0) | \
213 (((l1_attr) & PTE1_RO) ? PTE2_RO : 0) | \
214 (((l1_attr) & PTE1_U) ? PTE2_U : 0) | \
215 (((l1_attr) & PTE1_W) ? PTE2_W : 0))
218 * PTE2 descriptors creation macros.
220 #define PTE2_ATTR_DEFAULT vm_memattr_to_pte2(VM_MEMATTR_DEFAULT)
221 #define PTE2_ATTR_PT vm_memattr_to_pte2(pt_memattr)
223 #define PTE2_KPT(pa) PTE2_KERN(pa, PTE2_AP_KRW, PTE2_ATTR_PT)
224 #define PTE2_KPT_NG(pa) PTE2_KERN_NG(pa, PTE2_AP_KRW, PTE2_ATTR_PT)
226 #define PTE2_KRW(pa) PTE2_KERN(pa, PTE2_AP_KRW, PTE2_ATTR_DEFAULT)
227 #define PTE2_KRO(pa) PTE2_KERN(pa, PTE2_AP_KR, PTE2_ATTR_DEFAULT)
231 #define PV_STAT(x) do { x ; } while (0)
233 #define PV_STAT(x) do { } while (0)
237 * The boot_pt1 is used temporary in very early boot stage as L1 page table.
238 * We can init many things with no memory allocation thanks to its static
239 * allocation and this brings two main advantages:
240 * (1) other cores can be started very simply,
241 * (2) various boot loaders can be supported as its arguments can be processed
242 * in virtual address space and can be moved to safe location before
243 * first allocation happened.
244 * Only disadvantage is that boot_pt1 is used only in very early boot stage.
245 * However, the table is uninitialized and so lays in bss. Therefore kernel
246 * image size is not influenced.
248 * QQQ: In the future, maybe, boot_pt1 can be used for soft reset and
249 * CPU suspend/resume game.
251 extern pt1_entry_t boot_pt1[];
254 pt1_entry_t *kern_pt1;
255 pt2_entry_t *kern_pt2tab;
258 static uint32_t ttb_flags;
259 static vm_memattr_t pt_memattr;
260 ttb_entry_t pmap_kern_ttb;
262 struct pmap kernel_pmap_store;
263 LIST_HEAD(pmaplist, pmap);
264 static struct pmaplist allpmaps;
265 static struct mtx allpmaps_lock;
267 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
268 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
270 static vm_offset_t kernel_vm_end_new;
271 vm_offset_t kernel_vm_end = KERNBASE + NKPT2PG * NPT2_IN_PG * PTE1_SIZE;
272 vm_offset_t vm_max_kernel_address;
273 vm_paddr_t kernel_l1pa;
275 static struct rwlock __aligned(CACHE_LINE_SIZE) pvh_global_lock;
278 * Data for the pv entry allocation mechanism
280 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
281 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
282 static struct md_page *pv_table; /* XXX: Is it used only the list in md_page? */
283 static int shpgperproc = PMAP_SHPGPERPROC;
285 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
286 int pv_maxchunks; /* How many chunks we have KVA for */
287 vm_offset_t pv_vafree; /* freelist stored in the PTE */
289 vm_paddr_t first_managed_pa;
290 #define pa_to_pvh(pa) (&pv_table[pte1_index(pa - first_managed_pa)])
293 * All those kernel PT submaps that BSD is so fond of
300 static caddr_t crashdumpmap;
302 static pt2_entry_t *PMAP1 = NULL, *PMAP2;
303 static pt2_entry_t *PADDR1 = NULL, *PADDR2;
305 static pt2_entry_t *PMAP3;
306 static pt2_entry_t *PADDR3;
307 static int PMAP3cpu __unused; /* for SMP only */
311 static int PMAP1changedcpu;
312 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
314 "Number of times pmap_pte2_quick changed CPU with same PMAP1");
316 static int PMAP1changed;
317 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
319 "Number of times pmap_pte2_quick changed PMAP1");
320 static int PMAP1unchanged;
321 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
323 "Number of times pmap_pte2_quick didn't change PMAP1");
324 static struct mtx PMAP2mutex;
326 static __inline void pt2_wirecount_init(vm_page_t m);
327 static boolean_t pmap_demote_pte1(pmap_t pmap, pt1_entry_t *pte1p,
329 void cache_icache_sync_fresh(vm_offset_t va, vm_paddr_t pa, vm_size_t size);
332 * Function to set the debug level of the pmap code.
336 pmap_debug(int level)
339 pmap_debug_level = level;
340 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
342 #endif /* PMAP_DEBUG */
345 * This table must corespond with memory attribute configuration in vm.h.
346 * First entry is used for normal system mapping.
348 * Device memory is always marked as shared.
349 * Normal memory is shared only in SMP .
350 * Not outer shareable bits are not used yet.
351 * Class 6 cannot be used on ARM11.
353 #define TEXDEF_TYPE_SHIFT 0
354 #define TEXDEF_TYPE_MASK 0x3
355 #define TEXDEF_INNER_SHIFT 2
356 #define TEXDEF_INNER_MASK 0x3
357 #define TEXDEF_OUTER_SHIFT 4
358 #define TEXDEF_OUTER_MASK 0x3
359 #define TEXDEF_NOS_SHIFT 6
360 #define TEXDEF_NOS_MASK 0x1
362 #define TEX(t, i, o, s) \
363 ((t) << TEXDEF_TYPE_SHIFT) | \
364 ((i) << TEXDEF_INNER_SHIFT) | \
365 ((o) << TEXDEF_OUTER_SHIFT | \
366 ((s) << TEXDEF_NOS_SHIFT))
368 static uint32_t tex_class[8] = {
369 /* type inner cache outer cache */
370 TEX(PRRR_MEM, NMRR_WB_WA, NMRR_WB_WA, 0), /* 0 - ATTR_WB_WA */
371 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 1 - ATTR_NOCACHE */
372 TEX(PRRR_DEV, NMRR_NC, NMRR_NC, 0), /* 2 - ATTR_DEVICE */
373 TEX(PRRR_SO, NMRR_NC, NMRR_NC, 0), /* 3 - ATTR_SO */
374 TEX(PRRR_MEM, NMRR_WT, NMRR_WT, 0), /* 4 - ATTR_WT */
375 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 5 - NOT USED YET */
376 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 6 - NOT USED YET */
377 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 7 - NOT USED YET */
381 static uint32_t pte2_attr_tab[8] = {
382 PTE2_ATTR_WB_WA, /* 0 - VM_MEMATTR_WB_WA */
383 PTE2_ATTR_NOCACHE, /* 1 - VM_MEMATTR_NOCACHE */
384 PTE2_ATTR_DEVICE, /* 2 - VM_MEMATTR_DEVICE */
385 PTE2_ATTR_SO, /* 3 - VM_MEMATTR_SO */
386 PTE2_ATTR_WT, /* 4 - VM_MEMATTR_WRITE_THROUGH */
387 0, /* 5 - NOT USED YET */
388 0, /* 6 - NOT USED YET */
389 0 /* 7 - NOT USED YET */
391 CTASSERT(VM_MEMATTR_WB_WA == 0);
392 CTASSERT(VM_MEMATTR_NOCACHE == 1);
393 CTASSERT(VM_MEMATTR_DEVICE == 2);
394 CTASSERT(VM_MEMATTR_SO == 3);
395 CTASSERT(VM_MEMATTR_WRITE_THROUGH == 4);
397 static inline uint32_t
398 vm_memattr_to_pte2(vm_memattr_t ma)
401 KASSERT((u_int)ma < 5, ("%s: bad vm_memattr_t %d", __func__, ma));
402 return (pte2_attr_tab[(u_int)ma]);
405 static inline uint32_t
406 vm_page_pte2_attr(vm_page_t m)
409 return (vm_memattr_to_pte2(m->md.pat_mode));
413 * Convert TEX definition entry to TTB flags.
416 encode_ttb_flags(int idx)
418 uint32_t inner, outer, nos, reg;
420 inner = (tex_class[idx] >> TEXDEF_INNER_SHIFT) &
422 outer = (tex_class[idx] >> TEXDEF_OUTER_SHIFT) &
424 nos = (tex_class[idx] >> TEXDEF_NOS_SHIFT) &
429 if (cpuinfo.coherent_walk)
430 reg |= (inner & 0x1) << 6;
431 reg |= (inner & 0x2) >> 1;
441 * Set TEX remapping registers in current CPU.
447 uint32_t type, inner, outer, nos;
450 #ifdef PMAP_PTE_NOCACHE
452 if (cpuinfo.coherent_walk) {
453 pt_memattr = VM_MEMATTR_WB_WA;
454 ttb_flags = encode_ttb_flags(0);
457 pt_memattr = VM_MEMATTR_NOCACHE;
458 ttb_flags = encode_ttb_flags(1);
461 pt_memattr = VM_MEMATTR_WB_WA;
462 ttb_flags = encode_ttb_flags(0);
468 /* Build remapping register from TEX classes. */
469 for (i = 0; i < 8; i++) {
470 type = (tex_class[i] >> TEXDEF_TYPE_SHIFT) &
472 inner = (tex_class[i] >> TEXDEF_INNER_SHIFT) &
474 outer = (tex_class[i] >> TEXDEF_OUTER_SHIFT) &
476 nos = (tex_class[i] >> TEXDEF_NOS_SHIFT) &
479 prrr |= type << (i * 2);
480 prrr |= nos << (i + 24);
481 nmrr |= inner << (i * 2);
482 nmrr |= outer << (i * 2 + 16);
484 /* Add shareable bits for device memory. */
485 prrr |= PRRR_DS0 | PRRR_DS1;
487 /* Add shareable bits for normal memory in SMP case. */
496 /* Caches are disabled, so full TLB flush should be enough. */
497 tlb_flush_all_local();
501 * Remap one vm_meattr class to another one. This can be useful as
502 * workaround for SOC errata, e.g. if devices must be accessed using
505 * !!! Please note that this function is absolutely last resort thing.
506 * It should not be used under normal circumstances. !!!
509 * - it shall be called after pmap_bootstrap_prepare() and before
510 * cpu_mp_start() (thus only on boot CPU). In practice, it's expected
511 * to be called from platform_attach() or platform_late_init().
513 * - if remapping doesn't change caching mode, or until uncached class
514 * is remapped to any kind of cached one, then no other restriction exists.
516 * - if pmap_remap_vm_attr() changes caching mode, but both (original and
517 * remapped) remain cached, then caller is resposible for calling
518 * of dcache_wbinv_poc_all().
520 * - remapping of any kind of cached class to uncached is not permitted.
523 pmap_remap_vm_attr(vm_memattr_t old_attr, vm_memattr_t new_attr)
525 int old_idx, new_idx;
527 /* Map VM memattrs to indexes to tex_class table. */
528 old_idx = PTE2_ATTR2IDX(pte2_attr_tab[(int)old_attr]);
529 new_idx = PTE2_ATTR2IDX(pte2_attr_tab[(int)new_attr]);
531 /* Replace TEX attribute and apply it. */
532 tex_class[old_idx] = tex_class[new_idx];
537 * KERNBASE must be multiple of NPT2_IN_PG * PTE1_SIZE. In other words,
538 * KERNBASE is mapped by first L2 page table in L2 page table page. It
539 * meets same constrain due to PT2MAP being placed just under KERNBASE.
541 CTASSERT((KERNBASE & (NPT2_IN_PG * PTE1_SIZE - 1)) == 0);
542 CTASSERT((KERNBASE - VM_MAXUSER_ADDRESS) >= PT2MAP_SIZE);
545 * In crazy dreams, PAGE_SIZE could be a multiple of PTE2_SIZE in general.
546 * For now, anyhow, the following check must be fulfilled.
548 CTASSERT(PAGE_SIZE == PTE2_SIZE);
550 * We don't want to mess up MI code with all MMU and PMAP definitions,
551 * so some things, which depend on other ones, are defined independently.
552 * Now, it is time to check that we don't screw up something.
554 CTASSERT(PDRSHIFT == PTE1_SHIFT);
556 * Check L1 and L2 page table entries definitions consistency.
558 CTASSERT(NB_IN_PT1 == (sizeof(pt1_entry_t) * NPTE1_IN_PT1));
559 CTASSERT(NB_IN_PT2 == (sizeof(pt2_entry_t) * NPTE2_IN_PT2));
561 * Check L2 page tables page consistency.
563 CTASSERT(PAGE_SIZE == (NPT2_IN_PG * NB_IN_PT2));
564 CTASSERT((1 << PT2PG_SHIFT) == NPT2_IN_PG);
566 * Check PT2TAB consistency.
567 * PT2TAB_ENTRIES is defined as a division of NPTE1_IN_PT1 by NPT2_IN_PG.
568 * This should be done without remainder.
570 CTASSERT(NPTE1_IN_PT1 == (PT2TAB_ENTRIES * NPT2_IN_PG));
575 * All level 2 page tables (PT2s) are mapped continuously and accordingly
576 * into PT2MAP address space. As PT2 size is less than PAGE_SIZE, this can
577 * be done only if PAGE_SIZE is a multiple of PT2 size. All PT2s in one page
578 * must be used together, but not necessary at once. The first PT2 in a page
579 * must map things on correctly aligned address and the others must follow
582 #define NB_IN_PT2TAB (PT2TAB_ENTRIES * sizeof(pt2_entry_t))
583 #define NPT2_IN_PT2TAB (NB_IN_PT2TAB / NB_IN_PT2)
584 #define NPG_IN_PT2TAB (NB_IN_PT2TAB / PAGE_SIZE)
587 * Check PT2TAB consistency.
588 * NPT2_IN_PT2TAB is defined as a division of NB_IN_PT2TAB by NB_IN_PT2.
589 * NPG_IN_PT2TAB is defined as a division of NB_IN_PT2TAB by PAGE_SIZE.
590 * The both should be done without remainder.
592 CTASSERT(NB_IN_PT2TAB == (NPT2_IN_PT2TAB * NB_IN_PT2));
593 CTASSERT(NB_IN_PT2TAB == (NPG_IN_PT2TAB * PAGE_SIZE));
595 * The implementation was made general, however, with the assumption
596 * bellow in mind. In case of another value of NPG_IN_PT2TAB,
597 * the code should be once more rechecked.
599 CTASSERT(NPG_IN_PT2TAB == 1);
602 * Get offset of PT2 in a page
603 * associated with given PT1 index.
605 static __inline u_int
606 page_pt2off(u_int pt1_idx)
609 return ((pt1_idx & PT2PG_MASK) * NB_IN_PT2);
613 * Get physical address of PT2
614 * associated with given PT2s page and PT1 index.
616 static __inline vm_paddr_t
617 page_pt2pa(vm_paddr_t pgpa, u_int pt1_idx)
620 return (pgpa + page_pt2off(pt1_idx));
624 * Get first entry of PT2
625 * associated with given PT2s page and PT1 index.
627 static __inline pt2_entry_t *
628 page_pt2(vm_offset_t pgva, u_int pt1_idx)
631 return ((pt2_entry_t *)(pgva + page_pt2off(pt1_idx)));
635 * Get virtual address of PT2s page (mapped in PT2MAP)
636 * which holds PT2 which holds entry which maps given virtual address.
638 static __inline vm_offset_t
639 pt2map_pt2pg(vm_offset_t va)
642 va &= ~(NPT2_IN_PG * PTE1_SIZE - 1);
643 return ((vm_offset_t)pt2map_entry(va));
646 /*****************************************************************************
648 * THREE pmap initialization milestones exist:
651 * -> fundamental init (including MMU) in ASM
654 * -> fundamental init continues in C
655 * -> first available physical address is known
657 * pmap_bootstrap_prepare() -> FIRST PMAP MILESTONE (first epoch begins)
658 * -> basic (safe) interface for physical address allocation is made
659 * -> basic (safe) interface for virtual mapping is made
660 * -> limited not SMP coherent work is possible
662 * -> more fundamental init continues in C
663 * -> locks and some more things are available
664 * -> all fundamental allocations and mappings are done
666 * pmap_bootstrap() -> SECOND PMAP MILESTONE (second epoch begins)
667 * -> phys_avail[] and virtual_avail is set
668 * -> control is passed to vm subsystem
669 * -> physical and virtual address allocation are off limit
670 * -> low level mapping functions, some SMP coherent,
671 * are available, which cannot be used before vm subsystem
675 * -> vm subsystem is being inited
677 * pmap_init() -> THIRD PMAP MILESTONE (third epoch begins)
678 * -> pmap is fully inited
680 *****************************************************************************/
682 /*****************************************************************************
684 * PMAP first stage initialization and utility functions
685 * for pre-bootstrap epoch.
687 * After pmap_bootstrap_prepare() is called, the following functions
690 * (1) strictly only for this stage functions for physical page allocations,
691 * virtual space allocations, and mappings:
693 * vm_paddr_t pmap_preboot_get_pages(u_int num);
694 * void pmap_preboot_map_pages(vm_paddr_t pa, vm_offset_t va, u_int num);
695 * vm_offset_t pmap_preboot_reserve_pages(u_int num);
696 * vm_offset_t pmap_preboot_get_vpages(u_int num);
697 * void pmap_preboot_map_attr(vm_paddr_t pa, vm_offset_t va, vm_size_t size,
698 * vm_prot_t prot, vm_memattr_t attr);
700 * (2) for all stages:
702 * vm_paddr_t pmap_kextract(vm_offset_t va);
704 * NOTE: This is not SMP coherent stage.
706 *****************************************************************************/
708 #define KERNEL_P2V(pa) \
709 ((vm_offset_t)((pa) - arm_physmem_kernaddr + KERNVIRTADDR))
710 #define KERNEL_V2P(va) \
711 ((vm_paddr_t)((va) - KERNVIRTADDR + arm_physmem_kernaddr))
713 static vm_paddr_t last_paddr;
716 * Pre-bootstrap epoch page allocator.
719 pmap_preboot_get_pages(u_int num)
724 last_paddr += num * PAGE_SIZE;
730 * The fundamental initialization of PMAP stuff.
732 * Some things already happened in locore.S and some things could happen
733 * before pmap_bootstrap_prepare() is called, so let's recall what is done:
734 * 1. Caches are disabled.
735 * 2. We are running on virtual addresses already with 'boot_pt1'
737 * 3. So far, all virtual addresses can be converted to physical ones and
738 * vice versa by the following macros:
739 * KERNEL_P2V(pa) .... physical to virtual ones,
740 * KERNEL_V2P(va) .... virtual to physical ones.
742 * What is done herein:
743 * 1. The 'boot_pt1' is replaced by real kernel L1 page table 'kern_pt1'.
744 * 2. PT2MAP magic is brought to live.
745 * 3. Basic preboot functions for page allocations and mappings can be used.
746 * 4. Everything is prepared for L1 cache enabling.
749 * 1. To use second TTB register, so kernel and users page tables will be
750 * separated. This way process forking - pmap_pinit() - could be faster,
751 * it saves physical pages and KVA per a process, and it's simple change.
752 * However, it will lead, due to hardware matter, to the following:
753 * (a) 2G space for kernel and 2G space for users.
754 * (b) 1G space for kernel in low addresses and 3G for users above it.
755 * A question is: Is the case (b) really an option? Note that case (b)
756 * does save neither physical memory and KVA.
759 pmap_bootstrap_prepare(vm_paddr_t last)
761 vm_paddr_t pt2pg_pa, pt2tab_pa, pa, size;
762 vm_offset_t pt2pg_va;
769 * Now, we are going to make real kernel mapping. Note that we are
770 * already running on some mapping made in locore.S and we expect
771 * that it's large enough to ensure nofault access to physical memory
772 * allocated herein before switch.
774 * As kernel image and everything needed before are and will be mapped
775 * by section mappings, we align last physical address to PTE1_SIZE.
777 last_paddr = pte1_roundup(last);
780 * Allocate and zero page(s) for kernel L1 page table.
782 * Note that it's first allocation on space which was PTE1_SIZE
783 * aligned and as such base_pt1 is aligned to NB_IN_PT1 too.
785 base_pt1 = pmap_preboot_get_pages(NPG_IN_PT1);
786 kern_pt1 = (pt1_entry_t *)KERNEL_P2V(base_pt1);
787 bzero((void*)kern_pt1, NB_IN_PT1);
788 pte1_sync_range(kern_pt1, NB_IN_PT1);
790 /* Allocate and zero page(s) for kernel PT2TAB. */
791 pt2tab_pa = pmap_preboot_get_pages(NPG_IN_PT2TAB);
792 kern_pt2tab = (pt2_entry_t *)KERNEL_P2V(pt2tab_pa);
793 bzero(kern_pt2tab, NB_IN_PT2TAB);
794 pte2_sync_range(kern_pt2tab, NB_IN_PT2TAB);
796 /* Allocate and zero page(s) for kernel L2 page tables. */
797 pt2pg_pa = pmap_preboot_get_pages(NKPT2PG);
798 pt2pg_va = KERNEL_P2V(pt2pg_pa);
799 size = NKPT2PG * PAGE_SIZE;
800 bzero((void*)pt2pg_va, size);
801 pte2_sync_range((pt2_entry_t *)pt2pg_va, size);
804 * Add a physical memory segment (vm_phys_seg) corresponding to the
805 * preallocated pages for kernel L2 page tables so that vm_page
806 * structures representing these pages will be created. The vm_page
807 * structures are required for promotion of the corresponding kernel
808 * virtual addresses to section mappings.
810 vm_phys_add_seg(pt2tab_pa, pmap_preboot_get_pages(0));
813 * Insert allocated L2 page table pages to PT2TAB and make
814 * link to all PT2s in L1 page table. See how kernel_vm_end
817 * We play simple and safe. So every KVA will have underlaying
818 * L2 page table, even kernel image mapped by sections.
820 pte2p = kern_pt2tab_entry(KERNBASE);
821 for (pa = pt2pg_pa; pa < pt2pg_pa + size; pa += PTE2_SIZE)
822 pt2tab_store(pte2p++, PTE2_KPT(pa));
824 pte1p = kern_pte1(KERNBASE);
825 for (pa = pt2pg_pa; pa < pt2pg_pa + size; pa += NB_IN_PT2)
826 pte1_store(pte1p++, PTE1_LINK(pa));
828 /* Make section mappings for kernel. */
829 l1_attr = ATTR_TO_L1(PTE2_ATTR_DEFAULT);
830 pte1p = kern_pte1(KERNBASE);
831 for (pa = KERNEL_V2P(KERNBASE); pa < last; pa += PTE1_SIZE)
832 pte1_store(pte1p++, PTE1_KERN(pa, PTE1_AP_KRW, l1_attr));
835 * Get free and aligned space for PT2MAP and make L1 page table links
836 * to L2 page tables held in PT2TAB.
838 * Note that pages holding PT2s are stored in PT2TAB as pt2_entry_t
839 * descriptors and PT2TAB page(s) itself is(are) used as PT2s. Thus
840 * each entry in PT2TAB maps all PT2s in a page. This implies that
841 * virtual address of PT2MAP must be aligned to NPT2_IN_PG * PTE1_SIZE.
843 PT2MAP = (pt2_entry_t *)(KERNBASE - PT2MAP_SIZE);
844 pte1p = kern_pte1((vm_offset_t)PT2MAP);
845 for (pa = pt2tab_pa, i = 0; i < NPT2_IN_PT2TAB; i++, pa += NB_IN_PT2) {
846 pte1_store(pte1p++, PTE1_LINK(pa));
850 * Store PT2TAB in PT2TAB itself, i.e. self reference mapping.
851 * Each pmap will hold own PT2TAB, so the mapping should be not global.
853 pte2p = kern_pt2tab_entry((vm_offset_t)PT2MAP);
854 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE) {
855 pt2tab_store(pte2p++, PTE2_KPT_NG(pa));
859 * Choose correct L2 page table and make mappings for allocations
860 * made herein which replaces temporary locore.S mappings after a while.
861 * Note that PT2MAP cannot be used until we switch to kern_pt1.
863 * Note, that these allocations started aligned on 1M section and
864 * kernel PT1 was allocated first. Making of mappings must follow
865 * order of physical allocations as we've used KERNEL_P2V() macro
866 * for virtual addresses resolution.
868 pte2p = kern_pt2tab_entry((vm_offset_t)kern_pt1);
869 pt2pg_va = KERNEL_P2V(pte2_pa(pte2_load(pte2p)));
871 pte2p = page_pt2(pt2pg_va, pte1_index((vm_offset_t)kern_pt1));
873 /* Make mapping for kernel L1 page table. */
874 for (pa = base_pt1, i = 0; i < NPG_IN_PT1; i++, pa += PTE2_SIZE)
875 pte2_store(pte2p++, PTE2_KPT(pa));
877 /* Make mapping for kernel PT2TAB. */
878 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE)
879 pte2_store(pte2p++, PTE2_KPT(pa));
881 /* Finally, switch from 'boot_pt1' to 'kern_pt1'. */
882 pmap_kern_ttb = base_pt1 | ttb_flags;
883 cpuinfo_reinit_mmu(pmap_kern_ttb);
885 * Initialize the first available KVA. As kernel image is mapped by
886 * sections, we are leaving some gap behind.
888 virtual_avail = (vm_offset_t)kern_pt2tab + NPG_IN_PT2TAB * PAGE_SIZE;
892 * Setup L2 page table page for given KVA.
893 * Used in pre-bootstrap epoch.
895 * Note that we have allocated NKPT2PG pages for L2 page tables in advance
896 * and used them for mapping KVA starting from KERNBASE. However, this is not
897 * enough. Vectors and devices need L2 page tables too. Note that they are
898 * even above VM_MAX_KERNEL_ADDRESS.
900 static __inline vm_paddr_t
901 pmap_preboot_pt2pg_setup(vm_offset_t va)
903 pt2_entry_t *pte2p, pte2;
906 /* Get associated entry in PT2TAB. */
907 pte2p = kern_pt2tab_entry(va);
909 /* Just return, if PT2s page exists already. */
910 pte2 = pt2tab_load(pte2p);
911 if (pte2_is_valid(pte2))
912 return (pte2_pa(pte2));
914 KASSERT(va >= VM_MAX_KERNEL_ADDRESS,
915 ("%s: NKPT2PG too small", __func__));
918 * Allocate page for PT2s and insert it to PT2TAB.
919 * In other words, map it into PT2MAP space.
921 pt2pg_pa = pmap_preboot_get_pages(1);
922 pt2tab_store(pte2p, PTE2_KPT(pt2pg_pa));
924 /* Zero all PT2s in allocated page. */
925 bzero((void*)pt2map_pt2pg(va), PAGE_SIZE);
926 pte2_sync_range((pt2_entry_t *)pt2map_pt2pg(va), PAGE_SIZE);
932 * Setup L2 page table for given KVA.
933 * Used in pre-bootstrap epoch.
936 pmap_preboot_pt2_setup(vm_offset_t va)
939 vm_paddr_t pt2pg_pa, pt2_pa;
941 /* Setup PT2's page. */
942 pt2pg_pa = pmap_preboot_pt2pg_setup(va);
943 pt2_pa = page_pt2pa(pt2pg_pa, pte1_index(va));
945 /* Insert PT2 to PT1. */
946 pte1p = kern_pte1(va);
947 pte1_store(pte1p, PTE1_LINK(pt2_pa));
951 * Get L2 page entry associated with given KVA.
952 * Used in pre-bootstrap epoch.
954 static __inline pt2_entry_t*
955 pmap_preboot_vtopte2(vm_offset_t va)
959 /* Setup PT2 if needed. */
960 pte1p = kern_pte1(va);
961 if (!pte1_is_valid(pte1_load(pte1p))) /* XXX - sections ?! */
962 pmap_preboot_pt2_setup(va);
964 return (pt2map_entry(va));
968 * Pre-bootstrap epoch page(s) mapping(s).
971 pmap_preboot_map_pages(vm_paddr_t pa, vm_offset_t va, u_int num)
976 /* Map all the pages. */
977 for (i = 0; i < num; i++) {
978 pte2p = pmap_preboot_vtopte2(va);
979 pte2_store(pte2p, PTE2_KRW(pa));
986 * Pre-bootstrap epoch virtual space alocator.
989 pmap_preboot_reserve_pages(u_int num)
992 vm_offset_t start, va;
995 /* Allocate virtual space. */
996 start = va = virtual_avail;
997 virtual_avail += num * PAGE_SIZE;
999 /* Zero the mapping. */
1000 for (i = 0; i < num; i++) {
1001 pte2p = pmap_preboot_vtopte2(va);
1002 pte2_store(pte2p, 0);
1010 * Pre-bootstrap epoch page(s) allocation and mapping(s).
1013 pmap_preboot_get_vpages(u_int num)
1018 /* Allocate physical page(s). */
1019 pa = pmap_preboot_get_pages(num);
1021 /* Allocate virtual space. */
1023 virtual_avail += num * PAGE_SIZE;
1025 /* Map and zero all. */
1026 pmap_preboot_map_pages(pa, va, num);
1027 bzero((void *)va, num * PAGE_SIZE);
1033 * Pre-bootstrap epoch page mapping(s) with attributes.
1036 pmap_preboot_map_attr(vm_paddr_t pa, vm_offset_t va, vm_size_t size,
1037 vm_prot_t prot, vm_memattr_t attr)
1040 u_int l1_attr, l1_prot, l2_prot, l2_attr;
1044 l2_prot = prot & VM_PROT_WRITE ? PTE2_AP_KRW : PTE2_AP_KR;
1045 l2_prot |= (prot & VM_PROT_EXECUTE) ? PTE2_X : PTE2_NX;
1046 l2_attr = vm_memattr_to_pte2(attr);
1047 l1_prot = ATTR_TO_L1(l2_prot);
1048 l1_attr = ATTR_TO_L1(l2_attr);
1050 /* Map all the pages. */
1051 num = round_page(size);
1053 if ((((va | pa) & PTE1_OFFSET) == 0) && (num >= PTE1_SIZE)) {
1054 pte1p = kern_pte1(va);
1055 pte1_store(pte1p, PTE1_KERN(pa, l1_prot, l1_attr));
1060 pte2p = pmap_preboot_vtopte2(va);
1061 pte2_store(pte2p, PTE2_KERN(pa, l2_prot, l2_attr));
1070 * Extract from the kernel page table the physical address
1071 * that is mapped by the given virtual address "va".
1074 pmap_kextract(vm_offset_t va)
1080 pte1 = pte1_load(kern_pte1(va));
1081 if (pte1_is_section(pte1)) {
1082 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1083 } else if (pte1_is_link(pte1)) {
1085 * We should beware of concurrent promotion that changes
1086 * pte1 at this point. However, it's not a problem as PT2
1087 * page is preserved by promotion in PT2TAB. So even if
1088 * it happens, using of PT2MAP is still safe.
1090 * QQQ: However, concurrent removing is a problem which
1091 * ends in abort on PT2MAP space. Locking must be used
1092 * to deal with this.
1094 pte2 = pte2_load(pt2map_entry(va));
1095 pa = pte2_pa(pte2) | (va & PTE2_OFFSET);
1098 panic("%s: va %#x pte1 %#x", __func__, va, pte1);
1104 * Extract from the kernel page table the physical address
1105 * that is mapped by the given virtual address "va". Also
1106 * return L2 page table entry which maps the address.
1108 * This is only intended to be used for panic dumps.
1111 pmap_dump_kextract(vm_offset_t va, pt2_entry_t *pte2p)
1117 pte1 = pte1_load(kern_pte1(va));
1118 if (pte1_is_section(pte1)) {
1119 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1120 pte2 = pa | ATTR_TO_L2(pte1) | PTE2_V;
1121 } else if (pte1_is_link(pte1)) {
1122 pte2 = pte2_load(pt2map_entry(va));
1133 /*****************************************************************************
1135 * PMAP second stage initialization and utility functions
1136 * for bootstrap epoch.
1138 * After pmap_bootstrap() is called, the following functions for
1139 * mappings can be used:
1141 * void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
1142 * void pmap_kremove(vm_offset_t va);
1143 * vm_offset_t pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end,
1146 * NOTE: This is not SMP coherent stage. And physical page allocation is not
1147 * allowed during this stage.
1149 *****************************************************************************/
1152 * Initialize kernel PMAP locks and lists, kernel_pmap itself, and
1153 * reserve various virtual spaces for temporary mappings.
1156 pmap_bootstrap(vm_offset_t firstaddr)
1158 pt2_entry_t *unused __unused;
1162 * Initialize the kernel pmap (which is statically allocated).
1164 PMAP_LOCK_INIT(kernel_pmap);
1165 kernel_l1pa = (vm_paddr_t)kern_pt1; /* for libkvm */
1166 kernel_pmap->pm_pt1 = kern_pt1;
1167 kernel_pmap->pm_pt2tab = kern_pt2tab;
1168 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1169 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1172 * Initialize the global pv list lock.
1174 rw_init(&pvh_global_lock, "pmap pv global");
1176 LIST_INIT(&allpmaps);
1179 * Request a spin mutex so that changes to allpmaps cannot be
1180 * preempted by smp_rendezvous_cpus().
1182 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
1183 mtx_lock_spin(&allpmaps_lock);
1184 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
1185 mtx_unlock_spin(&allpmaps_lock);
1188 * Reserve some special page table entries/VA space for temporary
1191 #define SYSMAP(c, p, v, n) do { \
1192 v = (c)pmap_preboot_reserve_pages(n); \
1193 p = pt2map_entry((vm_offset_t)v); \
1197 * Local CMAP1/CMAP2 are used for zeroing and copying pages.
1198 * Local CMAP2 is also used for data cache cleaning.
1201 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
1202 SYSMAP(caddr_t, pc->pc_cmap1_pte2p, pc->pc_cmap1_addr, 1);
1203 SYSMAP(caddr_t, pc->pc_cmap2_pte2p, pc->pc_cmap2_addr, 1);
1204 SYSMAP(vm_offset_t, pc->pc_qmap_pte2p, pc->pc_qmap_addr, 1);
1209 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS);
1212 * _tmppt is used for reading arbitrary physical pages via /dev/mem.
1214 SYSMAP(caddr_t, unused, _tmppt, 1);
1217 * PADDR1 and PADDR2 are used by pmap_pte2_quick() and pmap_pte2(),
1218 * respectively. PADDR3 is used by pmap_pte2_ddb().
1220 SYSMAP(pt2_entry_t *, PMAP1, PADDR1, 1);
1221 SYSMAP(pt2_entry_t *, PMAP2, PADDR2, 1);
1223 SYSMAP(pt2_entry_t *, PMAP3, PADDR3, 1);
1225 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
1228 * Note that in very short time in initarm(), we are going to
1229 * initialize phys_avail[] array and no further page allocation
1230 * can happen after that until vm subsystem will be initialized.
1232 kernel_vm_end_new = kernel_vm_end;
1233 virtual_end = vm_max_kernel_address;
1237 pmap_init_reserved_pages(void)
1246 * Skip if the mapping has already been initialized,
1247 * i.e. this is the BSP.
1249 if (pc->pc_cmap1_addr != 0)
1251 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
1252 pages = kva_alloc(PAGE_SIZE * 3);
1254 panic("%s: unable to allocate KVA", __func__);
1255 pc->pc_cmap1_pte2p = pt2map_entry(pages);
1256 pc->pc_cmap2_pte2p = pt2map_entry(pages + PAGE_SIZE);
1257 pc->pc_qmap_pte2p = pt2map_entry(pages + (PAGE_SIZE * 2));
1258 pc->pc_cmap1_addr = (caddr_t)pages;
1259 pc->pc_cmap2_addr = (caddr_t)(pages + PAGE_SIZE);
1260 pc->pc_qmap_addr = pages + (PAGE_SIZE * 2);
1263 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
1266 * The function can already be use in second initialization stage.
1267 * As such, the function DOES NOT call pmap_growkernel() where PT2
1268 * allocation can happen. So if used, be sure that PT2 for given
1269 * virtual address is allocated already!
1271 * Add a wired page to the kva.
1272 * Note: not SMP coherent.
1274 static __inline void
1275 pmap_kenter_prot_attr(vm_offset_t va, vm_paddr_t pa, uint32_t prot,
1281 pte1p = kern_pte1(va);
1282 if (!pte1_is_valid(pte1_load(pte1p))) { /* XXX - sections ?! */
1284 * This is a very low level function, so PT2 and particularly
1285 * PT2PG associated with given virtual address must be already
1286 * allocated. It's a pain mainly during pmap initialization
1287 * stage. However, called after pmap initialization with
1288 * virtual address not under kernel_vm_end will lead to
1291 if (!pte2_is_valid(pte2_load(kern_pt2tab_entry(va))))
1292 panic("%s: kernel PT2 not allocated!", __func__);
1295 pte2p = pt2map_entry(va);
1296 pte2_store(pte2p, PTE2_KERN(pa, prot, attr));
1300 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1303 pmap_kenter_prot_attr(va, pa, PTE2_AP_KRW, PTE2_ATTR_DEFAULT);
1307 * Remove a page from the kernel pagetables.
1308 * Note: not SMP coherent.
1311 pmap_kremove(vm_offset_t va)
1316 pte1p = kern_pte1(va);
1317 if (pte1_is_section(pte1_load(pte1p))) {
1320 pte2p = pt2map_entry(va);
1326 * Share new kernel PT2PG with all pmaps.
1327 * The caller is responsible for maintaining TLB consistency.
1330 pmap_kenter_pt2tab(vm_offset_t va, pt2_entry_t npte2)
1335 mtx_lock_spin(&allpmaps_lock);
1336 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1337 pte2p = pmap_pt2tab_entry(pmap, va);
1338 pt2tab_store(pte2p, npte2);
1340 mtx_unlock_spin(&allpmaps_lock);
1344 * Share new kernel PTE1 with all pmaps.
1345 * The caller is responsible for maintaining TLB consistency.
1348 pmap_kenter_pte1(vm_offset_t va, pt1_entry_t npte1)
1353 mtx_lock_spin(&allpmaps_lock);
1354 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1355 pte1p = pmap_pte1(pmap, va);
1356 pte1_store(pte1p, npte1);
1358 mtx_unlock_spin(&allpmaps_lock);
1362 * Used to map a range of physical addresses into kernel
1363 * virtual address space.
1365 * The value passed in '*virt' is a suggested virtual address for
1366 * the mapping. Architectures which can support a direct-mapped
1367 * physical to virtual region can return the appropriate address
1368 * within that region, leaving '*virt' unchanged. Other
1369 * architectures should map the pages starting at '*virt' and
1370 * update '*virt' with the first usable address after the mapped
1373 * NOTE: Read the comments above pmap_kenter_prot_attr() as
1374 * the function is used herein!
1377 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1379 vm_offset_t va, sva;
1380 vm_paddr_t pte1_offset;
1382 uint32_t l1prot, l2prot;
1383 uint32_t l1attr, l2attr;
1385 PDEBUG(1, printf("%s: virt = %#x, start = %#x, end = %#x (size = %#x),"
1386 " prot = %d\n", __func__, *virt, start, end, end - start, prot));
1388 l2prot = (prot & VM_PROT_WRITE) ? PTE2_AP_KRW : PTE2_AP_KR;
1389 l2prot |= (prot & VM_PROT_EXECUTE) ? PTE2_X : PTE2_NX;
1390 l1prot = ATTR_TO_L1(l2prot);
1392 l2attr = PTE2_ATTR_DEFAULT;
1393 l1attr = ATTR_TO_L1(l2attr);
1397 * Does the physical address range's size and alignment permit at
1398 * least one section mapping to be created?
1400 pte1_offset = start & PTE1_OFFSET;
1401 if ((end - start) - ((PTE1_SIZE - pte1_offset) & PTE1_OFFSET) >=
1404 * Increase the starting virtual address so that its alignment
1405 * does not preclude the use of section mappings.
1407 if ((va & PTE1_OFFSET) < pte1_offset)
1408 va = pte1_trunc(va) + pte1_offset;
1409 else if ((va & PTE1_OFFSET) > pte1_offset)
1410 va = pte1_roundup(va) + pte1_offset;
1413 while (start < end) {
1414 if ((start & PTE1_OFFSET) == 0 && end - start >= PTE1_SIZE) {
1415 KASSERT((va & PTE1_OFFSET) == 0,
1416 ("%s: misaligned va %#x", __func__, va));
1417 npte1 = PTE1_KERN(start, l1prot, l1attr);
1418 pmap_kenter_pte1(va, npte1);
1422 pmap_kenter_prot_attr(va, start, l2prot, l2attr);
1427 tlb_flush_range(sva, va - sva);
1433 * Make a temporary mapping for a physical address.
1434 * This is only intended to be used for panic dumps.
1437 pmap_kenter_temporary(vm_paddr_t pa, int i)
1441 /* QQQ: 'i' should be less or equal to MAXDUMPPGS. */
1443 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
1444 pmap_kenter(va, pa);
1445 tlb_flush_local(va);
1446 return ((void *)crashdumpmap);
1450 /*************************************
1452 * TLB & cache maintenance routines.
1454 *************************************/
1457 * We inline these within pmap.c for speed.
1460 pmap_tlb_flush(pmap_t pmap, vm_offset_t va)
1463 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1468 pmap_tlb_flush_range(pmap_t pmap, vm_offset_t sva, vm_size_t size)
1471 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1472 tlb_flush_range(sva, size);
1476 * Abuse the pte2 nodes for unmapped kva to thread a kva freelist through.
1478 * - Must deal with pages in order to ensure that none of the PTE2_* bits
1479 * are ever set, PTE2_V in particular.
1480 * - Assumes we can write to pte2s without pte2_store() atomic ops.
1481 * - Assumes nothing will ever test these addresses for 0 to indicate
1482 * no mapping instead of correctly checking PTE2_V.
1483 * - Assumes a vm_offset_t will fit in a pte2 (true for arm).
1484 * Because PTE2_V is never set, there can be no mappings to invalidate.
1487 pmap_pte2list_alloc(vm_offset_t *head)
1494 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
1495 pte2p = pt2map_entry(va);
1498 panic("%s: va with PTE2_V set!", __func__);
1504 pmap_pte2list_free(vm_offset_t *head, vm_offset_t va)
1509 panic("%s: freeing va with PTE2_V set!", __func__);
1510 pte2p = pt2map_entry(va);
1511 *pte2p = *head; /* virtual! PTE2_V is 0 though */
1516 pmap_pte2list_init(vm_offset_t *head, void *base, int npages)
1522 for (i = npages - 1; i >= 0; i--) {
1523 va = (vm_offset_t)base + i * PAGE_SIZE;
1524 pmap_pte2list_free(head, va);
1528 /*****************************************************************************
1530 * PMAP third and final stage initialization.
1532 * After pmap_init() is called, PMAP subsystem is fully initialized.
1534 *****************************************************************************/
1536 SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
1538 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
1539 "Max number of PV entries");
1540 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
1541 "Page share factor per proc");
1543 static u_long nkpt2pg = NKPT2PG;
1544 SYSCTL_ULONG(_vm_pmap, OID_AUTO, nkpt2pg, CTLFLAG_RD,
1545 &nkpt2pg, 0, "Pre-allocated pages for kernel PT2s");
1547 static int sp_enabled = 1;
1548 SYSCTL_INT(_vm_pmap, OID_AUTO, sp_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
1549 &sp_enabled, 0, "Are large page mappings enabled?");
1551 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pte1, CTLFLAG_RD, 0,
1552 "1MB page mapping counters");
1554 static u_long pmap_pte1_demotions;
1555 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, demotions, CTLFLAG_RD,
1556 &pmap_pte1_demotions, 0, "1MB page demotions");
1558 static u_long pmap_pte1_mappings;
1559 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, mappings, CTLFLAG_RD,
1560 &pmap_pte1_mappings, 0, "1MB page mappings");
1562 static u_long pmap_pte1_p_failures;
1563 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, p_failures, CTLFLAG_RD,
1564 &pmap_pte1_p_failures, 0, "1MB page promotion failures");
1566 static u_long pmap_pte1_promotions;
1567 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, promotions, CTLFLAG_RD,
1568 &pmap_pte1_promotions, 0, "1MB page promotions");
1570 static u_long pmap_pte1_kern_demotions;
1571 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, kern_demotions, CTLFLAG_RD,
1572 &pmap_pte1_kern_demotions, 0, "1MB page kernel demotions");
1574 static u_long pmap_pte1_kern_promotions;
1575 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, kern_promotions, CTLFLAG_RD,
1576 &pmap_pte1_kern_promotions, 0, "1MB page kernel promotions");
1578 static __inline ttb_entry_t
1579 pmap_ttb_get(pmap_t pmap)
1582 return (vtophys(pmap->pm_pt1) | ttb_flags);
1586 * Initialize a vm_page's machine-dependent fields.
1589 * 1. Pages for L2 page tables are always not managed. So, pv_list and
1590 * pt2_wirecount can share same physical space. However, proper
1591 * initialization on a page alloc for page tables and reinitialization
1592 * on the page free must be ensured.
1595 pmap_page_init(vm_page_t m)
1598 TAILQ_INIT(&m->md.pv_list);
1599 pt2_wirecount_init(m);
1600 m->md.pat_mode = VM_MEMATTR_DEFAULT;
1604 * Virtualization for faster way how to zero whole page.
1606 static __inline void
1607 pagezero(void *page)
1610 bzero(page, PAGE_SIZE);
1614 * Zero L2 page table page.
1615 * Use same KVA as in pmap_zero_page().
1617 static __inline vm_paddr_t
1618 pmap_pt2pg_zero(vm_page_t m)
1620 pt2_entry_t *cmap2_pte2p;
1624 pa = VM_PAGE_TO_PHYS(m);
1627 * XXX: For now, we map whole page even if it's already zero,
1628 * to sync it even if the sync is only DSB.
1632 cmap2_pte2p = pc->pc_cmap2_pte2p;
1633 mtx_lock(&pc->pc_cmap_lock);
1634 if (pte2_load(cmap2_pte2p) != 0)
1635 panic("%s: CMAP2 busy", __func__);
1636 pte2_store(cmap2_pte2p, PTE2_KERN_NG(pa, PTE2_AP_KRW,
1637 vm_page_pte2_attr(m)));
1638 /* Even VM_ALLOC_ZERO request is only advisory. */
1639 if ((m->flags & PG_ZERO) == 0)
1640 pagezero(pc->pc_cmap2_addr);
1641 pte2_sync_range((pt2_entry_t *)pc->pc_cmap2_addr, PAGE_SIZE);
1642 pte2_clear(cmap2_pte2p);
1643 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
1646 * Unpin the thread before releasing the lock. Otherwise the thread
1647 * could be rescheduled while still bound to the current CPU, only
1648 * to unpin itself immediately upon resuming execution.
1651 mtx_unlock(&pc->pc_cmap_lock);
1657 * Init just allocated page as L2 page table(s) holder
1658 * and return its physical address.
1660 static __inline vm_paddr_t
1661 pmap_pt2pg_init(pmap_t pmap, vm_offset_t va, vm_page_t m)
1666 /* Check page attributes. */
1667 if (m->md.pat_mode != pt_memattr)
1668 pmap_page_set_memattr(m, pt_memattr);
1670 /* Zero page and init wire counts. */
1671 pa = pmap_pt2pg_zero(m);
1672 pt2_wirecount_init(m);
1675 * Map page to PT2MAP address space for given pmap.
1676 * Note that PT2MAP space is shared with all pmaps.
1678 if (pmap == kernel_pmap)
1679 pmap_kenter_pt2tab(va, PTE2_KPT(pa));
1681 pte2p = pmap_pt2tab_entry(pmap, va);
1682 pt2tab_store(pte2p, PTE2_KPT_NG(pa));
1689 * Initialize the pmap module.
1690 * Called by vm_init, to initialize any structures that the pmap
1691 * system needs to map virtual memory.
1697 pt2_entry_t *pte2p, pte2;
1698 u_int i, pte1_idx, pv_npg;
1700 PDEBUG(1, printf("%s: phys_start = %#x\n", __func__, PHYSADDR));
1703 * Initialize the vm page array entries for kernel pmap's
1704 * L2 page table pages allocated in advance.
1706 pte1_idx = pte1_index(KERNBASE - PT2MAP_SIZE);
1707 pte2p = kern_pt2tab_entry(KERNBASE - PT2MAP_SIZE);
1708 for (i = 0; i < nkpt2pg + NPG_IN_PT2TAB; i++, pte2p++) {
1712 pte2 = pte2_load(pte2p);
1713 KASSERT(pte2_is_valid(pte2), ("%s: no valid entry", __func__));
1716 m = PHYS_TO_VM_PAGE(pa);
1717 KASSERT(m >= vm_page_array &&
1718 m < &vm_page_array[vm_page_array_size],
1719 ("%s: L2 page table page is out of range", __func__));
1721 m->pindex = pte1_idx;
1723 pte1_idx += NPT2_IN_PG;
1727 * Initialize the address space (zone) for the pv entries. Set a
1728 * high water mark so that the system can recover from excessive
1729 * numbers of pv entries.
1731 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1732 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1733 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1734 pv_entry_max = roundup(pv_entry_max, _NPCPV);
1735 pv_entry_high_water = 9 * (pv_entry_max / 10);
1738 * Are large page mappings enabled?
1740 TUNABLE_INT_FETCH("vm.pmap.sp_enabled", &sp_enabled);
1742 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1743 ("%s: can't assign to pagesizes[1]", __func__));
1744 pagesizes[1] = PTE1_SIZE;
1748 * Calculate the size of the pv head table for sections.
1749 * Handle the possibility that "vm_phys_segs[...].end" is zero.
1750 * Note that the table is only for sections which could be promoted.
1752 first_managed_pa = pte1_trunc(vm_phys_segs[0].start);
1753 pv_npg = (pte1_trunc(vm_phys_segs[vm_phys_nsegs - 1].end - PAGE_SIZE)
1754 - first_managed_pa) / PTE1_SIZE + 1;
1757 * Allocate memory for the pv head table for sections.
1759 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1761 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
1763 for (i = 0; i < pv_npg; i++)
1764 TAILQ_INIT(&pv_table[i].pv_list);
1766 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
1767 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
1768 if (pv_chunkbase == NULL)
1769 panic("%s: not enough kvm for pv chunks", __func__);
1770 pmap_pte2list_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
1774 * Add a list of wired pages to the kva
1775 * this routine is only used for temporary
1776 * kernel mappings that do not need to have
1777 * page modification or references recorded.
1778 * Note that old mappings are simply written
1779 * over. The page *must* be wired.
1780 * Note: SMP coherent. Uses a ranged shootdown IPI.
1783 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1786 pt2_entry_t *epte2p, *pte2p, pte2;
1791 pte2p = pt2map_entry(sva);
1792 epte2p = pte2p + count;
1793 while (pte2p < epte2p) {
1795 pa = VM_PAGE_TO_PHYS(m);
1796 pte2 = pte2_load(pte2p);
1797 if ((pte2_pa(pte2) != pa) ||
1798 (pte2_attr(pte2) != vm_page_pte2_attr(m))) {
1800 pte2_store(pte2p, PTE2_KERN(pa, PTE2_AP_KRW,
1801 vm_page_pte2_attr(m)));
1805 if (__predict_false(anychanged))
1806 tlb_flush_range(sva, count * PAGE_SIZE);
1810 * This routine tears out page mappings from the
1811 * kernel -- it is meant only for temporary mappings.
1812 * Note: SMP coherent. Uses a ranged shootdown IPI.
1815 pmap_qremove(vm_offset_t sva, int count)
1820 while (count-- > 0) {
1824 tlb_flush_range(sva, va - sva);
1828 * Are we current address space or kernel?
1831 pmap_is_current(pmap_t pmap)
1834 return (pmap == kernel_pmap ||
1835 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace)));
1839 * If the given pmap is not the current or kernel pmap, the returned
1840 * pte2 must be released by passing it to pmap_pte2_release().
1842 static pt2_entry_t *
1843 pmap_pte2(pmap_t pmap, vm_offset_t va)
1846 vm_paddr_t pt2pg_pa;
1848 pte1 = pte1_load(pmap_pte1(pmap, va));
1849 if (pte1_is_section(pte1))
1850 panic("%s: attempt to map PTE1", __func__);
1851 if (pte1_is_link(pte1)) {
1852 /* Are we current address space or kernel? */
1853 if (pmap_is_current(pmap))
1854 return (pt2map_entry(va));
1855 /* Note that L2 page table size is not equal to PAGE_SIZE. */
1856 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
1857 mtx_lock(&PMAP2mutex);
1858 if (pte2_pa(pte2_load(PMAP2)) != pt2pg_pa) {
1859 pte2_store(PMAP2, PTE2_KPT(pt2pg_pa));
1860 tlb_flush((vm_offset_t)PADDR2);
1862 return (PADDR2 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
1868 * Releases a pte2 that was obtained from pmap_pte2().
1869 * Be prepared for the pte2p being NULL.
1871 static __inline void
1872 pmap_pte2_release(pt2_entry_t *pte2p)
1875 if ((pt2_entry_t *)(trunc_page((vm_offset_t)pte2p)) == PADDR2) {
1876 mtx_unlock(&PMAP2mutex);
1881 * Super fast pmap_pte2 routine best used when scanning
1882 * the pv lists. This eliminates many coarse-grained
1883 * invltlb calls. Note that many of the pv list
1884 * scans are across different pmaps. It is very wasteful
1885 * to do an entire tlb flush for checking a single mapping.
1887 * If the given pmap is not the current pmap, pvh_global_lock
1888 * must be held and curthread pinned to a CPU.
1890 static pt2_entry_t *
1891 pmap_pte2_quick(pmap_t pmap, vm_offset_t va)
1894 vm_paddr_t pt2pg_pa;
1896 pte1 = pte1_load(pmap_pte1(pmap, va));
1897 if (pte1_is_section(pte1))
1898 panic("%s: attempt to map PTE1", __func__);
1899 if (pte1_is_link(pte1)) {
1900 /* Are we current address space or kernel? */
1901 if (pmap_is_current(pmap))
1902 return (pt2map_entry(va));
1903 rw_assert(&pvh_global_lock, RA_WLOCKED);
1904 KASSERT(curthread->td_pinned > 0,
1905 ("%s: curthread not pinned", __func__));
1906 /* Note that L2 page table size is not equal to PAGE_SIZE. */
1907 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
1908 if (pte2_pa(pte2_load(PMAP1)) != pt2pg_pa) {
1909 pte2_store(PMAP1, PTE2_KPT(pt2pg_pa));
1911 PMAP1cpu = PCPU_GET(cpuid);
1913 tlb_flush_local((vm_offset_t)PADDR1);
1917 if (PMAP1cpu != PCPU_GET(cpuid)) {
1918 PMAP1cpu = PCPU_GET(cpuid);
1919 tlb_flush_local((vm_offset_t)PADDR1);
1924 return (PADDR1 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
1930 * Routine: pmap_extract
1932 * Extract the physical page address associated
1933 * with the given map/virtual_address pair.
1936 pmap_extract(pmap_t pmap, vm_offset_t va)
1943 pte1 = pte1_load(pmap_pte1(pmap, va));
1944 if (pte1_is_section(pte1))
1945 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1946 else if (pte1_is_link(pte1)) {
1947 pte2p = pmap_pte2(pmap, va);
1948 pa = pte2_pa(pte2_load(pte2p)) | (va & PTE2_OFFSET);
1949 pmap_pte2_release(pte2p);
1957 * Routine: pmap_extract_and_hold
1959 * Atomically extract and hold the physical page
1960 * with the given pmap and virtual address pair
1961 * if that mapping permits the given protection.
1964 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1966 vm_paddr_t pa, lockpa;
1968 pt2_entry_t pte2, *pte2p;
1975 pte1 = pte1_load(pmap_pte1(pmap, va));
1976 if (pte1_is_section(pte1)) {
1977 if (!(pte1 & PTE1_RO) || !(prot & VM_PROT_WRITE)) {
1978 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1979 if (vm_page_pa_tryrelock(pmap, pa, &lockpa))
1981 m = PHYS_TO_VM_PAGE(pa);
1984 } else if (pte1_is_link(pte1)) {
1985 pte2p = pmap_pte2(pmap, va);
1986 pte2 = pte2_load(pte2p);
1987 pmap_pte2_release(pte2p);
1988 if (pte2_is_valid(pte2) &&
1989 (!(pte2 & PTE2_RO) || !(prot & VM_PROT_WRITE))) {
1991 if (vm_page_pa_tryrelock(pmap, pa, &lockpa))
1993 m = PHYS_TO_VM_PAGE(pa);
1997 PA_UNLOCK_COND(lockpa);
2003 * Grow the number of kernel L2 page table entries, if needed.
2006 pmap_growkernel(vm_offset_t addr)
2009 vm_paddr_t pt2pg_pa, pt2_pa;
2013 PDEBUG(1, printf("%s: addr = %#x\n", __func__, addr));
2015 * All the time kernel_vm_end is first KVA for which underlying
2016 * L2 page table is either not allocated or linked from L1 page table
2017 * (not considering sections). Except for two possible cases:
2019 * (1) in the very beginning as long as pmap_growkernel() was
2020 * not called, it could be first unused KVA (which is not
2021 * rounded up to PTE1_SIZE),
2023 * (2) when all KVA space is mapped and kernel_map->max_offset
2024 * address is not rounded up to PTE1_SIZE. (For example,
2025 * it could be 0xFFFFFFFF.)
2027 kernel_vm_end = pte1_roundup(kernel_vm_end);
2028 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2029 addr = roundup2(addr, PTE1_SIZE);
2030 if (addr - 1 >= kernel_map->max_offset)
2031 addr = kernel_map->max_offset;
2032 while (kernel_vm_end < addr) {
2033 pte1 = pte1_load(kern_pte1(kernel_vm_end));
2034 if (pte1_is_valid(pte1)) {
2035 kernel_vm_end += PTE1_SIZE;
2036 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2037 kernel_vm_end = kernel_map->max_offset;
2044 * kernel_vm_end_new is used in pmap_pinit() when kernel
2045 * mappings are entered to new pmap all at once to avoid race
2046 * between pmap_kenter_pte1() and kernel_vm_end increase.
2047 * The same aplies to pmap_kenter_pt2tab().
2049 kernel_vm_end_new = kernel_vm_end + PTE1_SIZE;
2051 pte2 = pt2tab_load(kern_pt2tab_entry(kernel_vm_end));
2052 if (!pte2_is_valid(pte2)) {
2054 * Install new PT2s page into kernel PT2TAB.
2056 m = vm_page_alloc(NULL,
2057 pte1_index(kernel_vm_end) & ~PT2PG_MASK,
2058 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2059 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2061 panic("%s: no memory to grow kernel", __func__);
2063 * QQQ: To link all new L2 page tables from L1 page
2064 * table now and so pmap_kenter_pte1() them
2065 * at once together with pmap_kenter_pt2tab()
2066 * could be nice speed up. However,
2067 * pmap_growkernel() does not happen so often...
2068 * QQQ: The other TTBR is another option.
2070 pt2pg_pa = pmap_pt2pg_init(kernel_pmap, kernel_vm_end,
2073 pt2pg_pa = pte2_pa(pte2);
2075 pt2_pa = page_pt2pa(pt2pg_pa, pte1_index(kernel_vm_end));
2076 pmap_kenter_pte1(kernel_vm_end, PTE1_LINK(pt2_pa));
2078 kernel_vm_end = kernel_vm_end_new;
2079 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2080 kernel_vm_end = kernel_map->max_offset;
2087 kvm_size(SYSCTL_HANDLER_ARGS)
2089 unsigned long ksize = vm_max_kernel_address - KERNBASE;
2091 return (sysctl_handle_long(oidp, &ksize, 0, req));
2093 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2094 0, 0, kvm_size, "IU", "Size of KVM");
2097 kvm_free(SYSCTL_HANDLER_ARGS)
2099 unsigned long kfree = vm_max_kernel_address - kernel_vm_end;
2101 return (sysctl_handle_long(oidp, &kfree, 0, req));
2103 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2104 0, 0, kvm_free, "IU", "Amount of KVM free");
2106 /***********************************************
2108 * Pmap allocation/deallocation routines.
2110 ***********************************************/
2113 * Initialize the pmap for the swapper process.
2116 pmap_pinit0(pmap_t pmap)
2118 PDEBUG(1, printf("%s: pmap = %p\n", __func__, pmap));
2120 PMAP_LOCK_INIT(pmap);
2123 * Kernel page table directory and pmap stuff around is already
2124 * initialized, we are using it right now and here. So, finish
2125 * only PMAP structures initialization for process0 ...
2127 * Since the L1 page table and PT2TAB is shared with the kernel pmap,
2128 * which is already included in the list "allpmaps", this pmap does
2129 * not need to be inserted into that list.
2131 pmap->pm_pt1 = kern_pt1;
2132 pmap->pm_pt2tab = kern_pt2tab;
2133 CPU_ZERO(&pmap->pm_active);
2134 PCPU_SET(curpmap, pmap);
2135 TAILQ_INIT(&pmap->pm_pvchunk);
2136 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2137 CPU_SET(0, &pmap->pm_active);
2140 static __inline void
2141 pte1_copy_nosync(pt1_entry_t *spte1p, pt1_entry_t *dpte1p, vm_offset_t sva,
2146 idx = pte1_index(sva);
2147 count = (pte1_index(eva) - idx + 1) * sizeof(pt1_entry_t);
2148 bcopy(spte1p + idx, dpte1p + idx, count);
2151 static __inline void
2152 pt2tab_copy_nosync(pt2_entry_t *spte2p, pt2_entry_t *dpte2p, vm_offset_t sva,
2157 idx = pt2tab_index(sva);
2158 count = (pt2tab_index(eva) - idx + 1) * sizeof(pt2_entry_t);
2159 bcopy(spte2p + idx, dpte2p + idx, count);
2163 * Initialize a preallocated and zeroed pmap structure,
2164 * such as one in a vmspace structure.
2167 pmap_pinit(pmap_t pmap)
2171 vm_paddr_t pa, pt2tab_pa;
2174 PDEBUG(6, printf("%s: pmap = %p, pm_pt1 = %p\n", __func__, pmap,
2178 * No need to allocate L2 page table space yet but we do need
2179 * a valid L1 page table and PT2TAB table.
2181 * Install shared kernel mappings to these tables. It's a little
2182 * tricky as some parts of KVA are reserved for vectors, devices,
2183 * and whatever else. These parts are supposed to be above
2184 * vm_max_kernel_address. Thus two regions should be installed:
2186 * (1) <KERNBASE, kernel_vm_end),
2187 * (2) <vm_max_kernel_address, 0xFFFFFFFF>.
2189 * QQQ: The second region should be stable enough to be installed
2190 * only once in time when the tables are allocated.
2191 * QQQ: Maybe copy of both regions at once could be faster ...
2192 * QQQ: Maybe the other TTBR is an option.
2194 * Finally, install own PT2TAB table to these tables.
2197 if (pmap->pm_pt1 == NULL) {
2198 pmap->pm_pt1 = (pt1_entry_t *)kmem_alloc_contig(kernel_arena,
2199 NB_IN_PT1, M_NOWAIT | M_ZERO, 0, -1UL, NB_IN_PT1, 0,
2201 if (pmap->pm_pt1 == NULL)
2204 if (pmap->pm_pt2tab == NULL) {
2206 * QQQ: (1) PT2TAB must be contiguous. If PT2TAB is one page
2207 * only, what should be the only size for 32 bit systems,
2208 * then we could allocate it with vm_page_alloc() and all
2209 * the stuff needed as other L2 page table pages.
2210 * (2) Note that a process PT2TAB is special L2 page table
2211 * page. Its mapping in kernel_arena is permanent and can
2212 * be used no matter which process is current. Its mapping
2213 * in PT2MAP can be used only for current process.
2215 pmap->pm_pt2tab = (pt2_entry_t *)kmem_alloc_attr(kernel_arena,
2216 NB_IN_PT2TAB, M_NOWAIT | M_ZERO, 0, -1UL, pt_memattr);
2217 if (pmap->pm_pt2tab == NULL) {
2219 * QQQ: As struct pmap is allocated from UMA with
2220 * UMA_ZONE_NOFREE flag, it's important to leave
2221 * no allocation in pmap if initialization failed.
2223 kmem_free(kernel_arena, (vm_offset_t)pmap->pm_pt1,
2225 pmap->pm_pt1 = NULL;
2229 * QQQ: Each L2 page table page vm_page_t has pindex set to
2230 * pte1 index of virtual address mapped by this page.
2231 * It's not valid for non kernel PT2TABs themselves.
2232 * The pindex of these pages can not be altered because
2233 * of the way how they are allocated now. However, it
2234 * should not be a problem.
2238 mtx_lock_spin(&allpmaps_lock);
2240 * To avoid race with pmap_kenter_pte1() and pmap_kenter_pt2tab(),
2241 * kernel_vm_end_new is used here instead of kernel_vm_end.
2243 pte1_copy_nosync(kern_pt1, pmap->pm_pt1, KERNBASE,
2244 kernel_vm_end_new - 1);
2245 pte1_copy_nosync(kern_pt1, pmap->pm_pt1, vm_max_kernel_address,
2247 pt2tab_copy_nosync(kern_pt2tab, pmap->pm_pt2tab, KERNBASE,
2248 kernel_vm_end_new - 1);
2249 pt2tab_copy_nosync(kern_pt2tab, pmap->pm_pt2tab, vm_max_kernel_address,
2251 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
2252 mtx_unlock_spin(&allpmaps_lock);
2255 * Store PT2MAP PT2 pages (a.k.a. PT2TAB) in PT2TAB itself.
2256 * I.e. self reference mapping. The PT2TAB is private, however mapped
2257 * into shared PT2MAP space, so the mapping should be not global.
2259 pt2tab_pa = vtophys(pmap->pm_pt2tab);
2260 pte2p = pmap_pt2tab_entry(pmap, (vm_offset_t)PT2MAP);
2261 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE) {
2262 pt2tab_store(pte2p++, PTE2_KPT_NG(pa));
2265 /* Insert PT2MAP PT2s into pmap PT1. */
2266 pte1p = pmap_pte1(pmap, (vm_offset_t)PT2MAP);
2267 for (pa = pt2tab_pa, i = 0; i < NPT2_IN_PT2TAB; i++, pa += NB_IN_PT2) {
2268 pte1_store(pte1p++, PTE1_LINK(pa));
2272 * Now synchronize new mapping which was made above.
2274 pte1_sync_range(pmap->pm_pt1, NB_IN_PT1);
2275 pte2_sync_range(pmap->pm_pt2tab, NB_IN_PT2TAB);
2277 CPU_ZERO(&pmap->pm_active);
2278 TAILQ_INIT(&pmap->pm_pvchunk);
2279 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2286 pt2tab_user_is_empty(pt2_entry_t *tab)
2290 end = pt2tab_index(VM_MAXUSER_ADDRESS);
2291 for (i = 0; i < end; i++)
2292 if (tab[i] != 0) return (FALSE);
2297 * Release any resources held by the given physical map.
2298 * Called when a pmap initialized by pmap_pinit is being released.
2299 * Should only be called if the map contains no valid mappings.
2302 pmap_release(pmap_t pmap)
2305 vm_offset_t start, end;
2307 KASSERT(pmap->pm_stats.resident_count == 0,
2308 ("%s: pmap resident count %ld != 0", __func__,
2309 pmap->pm_stats.resident_count));
2310 KASSERT(pt2tab_user_is_empty(pmap->pm_pt2tab),
2311 ("%s: has allocated user PT2(s)", __func__));
2312 KASSERT(CPU_EMPTY(&pmap->pm_active),
2313 ("%s: pmap %p is active on some CPU(s)", __func__, pmap));
2315 mtx_lock_spin(&allpmaps_lock);
2316 LIST_REMOVE(pmap, pm_list);
2317 mtx_unlock_spin(&allpmaps_lock);
2320 start = pte1_index(KERNBASE) * sizeof(pt1_entry_t);
2321 end = (pte1_index(0xFFFFFFFF) + 1) * sizeof(pt1_entry_t);
2322 bzero((char *)pmap->pm_pt1 + start, end - start);
2324 start = pt2tab_index(KERNBASE) * sizeof(pt2_entry_t);
2325 end = (pt2tab_index(0xFFFFFFFF) + 1) * sizeof(pt2_entry_t);
2326 bzero((char *)pmap->pm_pt2tab + start, end - start);
2329 * We are leaving PT1 and PT2TAB allocated on released pmap,
2330 * so hopefully UMA vmspace_zone will always be inited with
2331 * UMA_ZONE_NOFREE flag.
2335 /*********************************************************
2337 * L2 table pages and their pages management routines.
2339 *********************************************************/
2342 * Virtual interface for L2 page table wire counting.
2344 * Each L2 page table in a page has own counter which counts a number of
2345 * valid mappings in a table. Global page counter counts mappings in all
2346 * tables in a page plus a single itself mapping in PT2TAB.
2348 * During a promotion we leave the associated L2 page table counter
2349 * untouched, so the table (strictly speaking a page which holds it)
2350 * is never freed if promoted.
2352 * If a page m->wire_count == 1 then no valid mappings exist in any L2 page
2353 * table in the page and the page itself is only mapped in PT2TAB.
2356 static __inline void
2357 pt2_wirecount_init(vm_page_t m)
2362 * Note: A page m is allocated with VM_ALLOC_WIRED flag and
2363 * m->wire_count should be already set correctly.
2364 * So, there is no need to set it again herein.
2366 for (i = 0; i < NPT2_IN_PG; i++)
2367 m->md.pt2_wirecount[i] = 0;
2370 static __inline void
2371 pt2_wirecount_inc(vm_page_t m, uint32_t pte1_idx)
2375 * Note: A just modificated pte2 (i.e. already allocated)
2376 * is acquiring one extra reference which must be
2377 * explicitly cleared. It influences the KASSERTs herein.
2378 * All L2 page tables in a page always belong to the same
2379 * pmap, so we allow only one extra reference for the page.
2381 KASSERT(m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] < (NPTE2_IN_PT2 + 1),
2382 ("%s: PT2 is overflowing ...", __func__));
2383 KASSERT(m->wire_count <= (NPTE2_IN_PG + 1),
2384 ("%s: PT2PG is overflowing ...", __func__));
2387 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]++;
2390 static __inline void
2391 pt2_wirecount_dec(vm_page_t m, uint32_t pte1_idx)
2394 KASSERT(m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] != 0,
2395 ("%s: PT2 is underflowing ...", __func__));
2396 KASSERT(m->wire_count > 1,
2397 ("%s: PT2PG is underflowing ...", __func__));
2400 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]--;
2403 static __inline void
2404 pt2_wirecount_set(vm_page_t m, uint32_t pte1_idx, uint16_t count)
2407 KASSERT(count <= NPTE2_IN_PT2,
2408 ("%s: invalid count %u", __func__, count));
2409 KASSERT(m->wire_count > m->md.pt2_wirecount[pte1_idx & PT2PG_MASK],
2410 ("%s: PT2PG corrupting (%u, %u) ...", __func__, m->wire_count,
2411 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]));
2413 m->wire_count -= m->md.pt2_wirecount[pte1_idx & PT2PG_MASK];
2414 m->wire_count += count;
2415 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] = count;
2417 KASSERT(m->wire_count <= (NPTE2_IN_PG + 1),
2418 ("%s: PT2PG is overflowed (%u) ...", __func__, m->wire_count));
2421 static __inline uint32_t
2422 pt2_wirecount_get(vm_page_t m, uint32_t pte1_idx)
2425 return (m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]);
2428 static __inline boolean_t
2429 pt2_is_empty(vm_page_t m, vm_offset_t va)
2432 return (m->md.pt2_wirecount[pte1_index(va) & PT2PG_MASK] == 0);
2435 static __inline boolean_t
2436 pt2_is_full(vm_page_t m, vm_offset_t va)
2439 return (m->md.pt2_wirecount[pte1_index(va) & PT2PG_MASK] ==
2443 static __inline boolean_t
2444 pt2pg_is_empty(vm_page_t m)
2447 return (m->wire_count == 1);
2451 * This routine is called if the L2 page table
2452 * is not mapped correctly.
2455 _pmap_allocpte2(pmap_t pmap, vm_offset_t va, u_int flags)
2461 vm_paddr_t pt2pg_pa, pt2_pa;
2463 pte1_idx = pte1_index(va);
2464 pte1p = pmap->pm_pt1 + pte1_idx;
2466 KASSERT(pte1_load(pte1p) == 0,
2467 ("%s: pm_pt1[%#x] is not zero: %#x", __func__, pte1_idx,
2470 pte2 = pt2tab_load(pmap_pt2tab_entry(pmap, va));
2471 if (!pte2_is_valid(pte2)) {
2473 * Install new PT2s page into pmap PT2TAB.
2475 m = vm_page_alloc(NULL, pte1_idx & ~PT2PG_MASK,
2476 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2478 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2480 rw_wunlock(&pvh_global_lock);
2482 rw_wlock(&pvh_global_lock);
2487 * Indicate the need to retry. While waiting,
2488 * the L2 page table page may have been allocated.
2492 pmap->pm_stats.resident_count++;
2493 pt2pg_pa = pmap_pt2pg_init(pmap, va, m);
2495 pt2pg_pa = pte2_pa(pte2);
2496 m = PHYS_TO_VM_PAGE(pt2pg_pa);
2499 pt2_wirecount_inc(m, pte1_idx);
2500 pt2_pa = page_pt2pa(pt2pg_pa, pte1_idx);
2501 pte1_store(pte1p, PTE1_LINK(pt2_pa));
2507 pmap_allocpte2(pmap_t pmap, vm_offset_t va, u_int flags)
2510 pt1_entry_t *pte1p, pte1;
2513 pte1_idx = pte1_index(va);
2515 pte1p = pmap->pm_pt1 + pte1_idx;
2516 pte1 = pte1_load(pte1p);
2519 * This supports switching from a 1MB page to a
2522 if (pte1_is_section(pte1)) {
2523 (void)pmap_demote_pte1(pmap, pte1p, va);
2525 * Reload pte1 after demotion.
2527 * Note: Demotion can even fail as either PT2 is not find for
2528 * the virtual address or PT2PG can not be allocated.
2530 pte1 = pte1_load(pte1p);
2534 * If the L2 page table page is mapped, we just increment the
2535 * hold count, and activate it.
2537 if (pte1_is_link(pte1)) {
2538 m = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
2539 pt2_wirecount_inc(m, pte1_idx);
2542 * Here if the PT2 isn't mapped, or if it has
2545 m = _pmap_allocpte2(pmap, va, flags);
2546 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2553 static __inline void
2554 pmap_free_zero_pages(struct spglist *free)
2558 while ((m = SLIST_FIRST(free)) != NULL) {
2559 SLIST_REMOVE_HEAD(free, plinks.s.ss);
2560 /* Preserve the page's PG_ZERO setting. */
2561 vm_page_free_toq(m);
2566 * Schedule the specified unused L2 page table page to be freed. Specifically,
2567 * add the page to the specified list of pages that will be released to the
2568 * physical memory manager after the TLB has been updated.
2570 static __inline void
2571 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free)
2575 * Put page on a list so that it is released after
2576 * *ALL* TLB shootdown is done
2579 pmap_zero_page_check(m);
2581 m->flags |= PG_ZERO;
2582 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2586 * Unwire L2 page tables page.
2589 pmap_unwire_pt2pg(pmap_t pmap, vm_offset_t va, vm_page_t m)
2591 pt1_entry_t *pte1p, opte1 __unused;
2595 KASSERT(pt2pg_is_empty(m),
2596 ("%s: pmap %p PT2PG %p wired", __func__, pmap, m));
2599 * Unmap all L2 page tables in the page from L1 page table.
2601 * QQQ: Individual L2 page tables (except the last one) can be unmapped
2602 * earlier. However, we are doing that this way.
2604 KASSERT(m->pindex == (pte1_index(va) & ~PT2PG_MASK),
2605 ("%s: pmap %p va %#x PT2PG %p bad index", __func__, pmap, va, m));
2606 pte1p = pmap->pm_pt1 + m->pindex;
2607 for (i = 0; i < NPT2_IN_PG; i++, pte1p++) {
2608 KASSERT(m->md.pt2_wirecount[i] == 0,
2609 ("%s: pmap %p PT2 %u (PG %p) wired", __func__, pmap, i, m));
2610 opte1 = pte1_load(pte1p);
2611 if (pte1_is_link(opte1)) {
2614 * Flush intermediate TLB cache.
2616 pmap_tlb_flush(pmap, (m->pindex + i) << PTE1_SHIFT);
2620 KASSERT((opte1 == 0) || pte1_is_section(opte1),
2621 ("%s: pmap %p va %#x bad pte1 %x at %u", __func__,
2622 pmap, va, opte1, i));
2627 * Unmap the page from PT2TAB.
2629 pte2p = pmap_pt2tab_entry(pmap, va);
2630 (void)pt2tab_load_clear(pte2p);
2631 pmap_tlb_flush(pmap, pt2map_pt2pg(va));
2634 pmap->pm_stats.resident_count--;
2637 * This barrier is so that the ordinary store unmapping
2638 * the L2 page table page is globally performed before TLB shoot-
2646 * Decrements a L2 page table page's wire count, which is used to record the
2647 * number of valid page table entries within the page. If the wire count
2648 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2649 * page table page was unmapped and FALSE otherwise.
2651 static __inline boolean_t
2652 pmap_unwire_pt2(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2654 pt2_wirecount_dec(m, pte1_index(va));
2655 if (pt2pg_is_empty(m)) {
2657 * QQQ: Wire count is zero, so whole page should be zero and
2658 * we can set PG_ZERO flag to it.
2659 * Note that when promotion is enabled, it takes some
2660 * more efforts. See pmap_unwire_pt2_all() below.
2662 pmap_unwire_pt2pg(pmap, va, m);
2663 pmap_add_delayed_free_list(m, free);
2670 * Drop a L2 page table page's wire count at once, which is used to record
2671 * the number of valid L2 page table entries within the page. If the wire
2672 * count drops to zero, then the L2 page table page is unmapped.
2674 static __inline void
2675 pmap_unwire_pt2_all(pmap_t pmap, vm_offset_t va, vm_page_t m,
2676 struct spglist *free)
2678 u_int pte1_idx = pte1_index(va);
2680 KASSERT(m->pindex == (pte1_idx & ~PT2PG_MASK),
2681 ("%s: PT2 page's pindex is wrong", __func__));
2682 KASSERT(m->wire_count > pt2_wirecount_get(m, pte1_idx),
2683 ("%s: bad pt2 wire count %u > %u", __func__, m->wire_count,
2684 pt2_wirecount_get(m, pte1_idx)));
2687 * It's possible that the L2 page table was never used.
2688 * It happened in case that a section was created without promotion.
2690 if (pt2_is_full(m, va)) {
2691 pt2_wirecount_set(m, pte1_idx, 0);
2694 * QQQ: We clear L2 page table now, so when L2 page table page
2695 * is going to be freed, we can set it PG_ZERO flag ...
2696 * This function is called only on section mappings, so
2697 * hopefully it's not to big overload.
2699 * XXX: If pmap is current, existing PT2MAP mapping could be
2702 pmap_zero_page_area(m, page_pt2off(pte1_idx), NB_IN_PT2);
2706 KASSERT(pt2_is_empty(m, va), ("%s: PT2 is not empty (%u)",
2707 __func__, pt2_wirecount_get(m, pte1_idx)));
2709 if (pt2pg_is_empty(m)) {
2710 pmap_unwire_pt2pg(pmap, va, m);
2711 pmap_add_delayed_free_list(m, free);
2716 * After removing a L2 page table entry, this routine is used to
2717 * conditionally free the page, and manage the hold/wire counts.
2720 pmap_unuse_pt2(pmap_t pmap, vm_offset_t va, struct spglist *free)
2725 if (va >= VM_MAXUSER_ADDRESS)
2727 pte1 = pte1_load(pmap_pte1(pmap, va));
2728 mpte = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
2729 return (pmap_unwire_pt2(pmap, va, mpte, free));
2732 /*************************************
2734 * Page management routines.
2736 *************************************/
2738 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2739 CTASSERT(_NPCM == 11);
2740 CTASSERT(_NPCPV == 336);
2742 static __inline struct pv_chunk *
2743 pv_to_chunk(pv_entry_t pv)
2746 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2749 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2751 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2752 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2754 static const uint32_t pc_freemask[_NPCM] = {
2755 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2756 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2757 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2758 PC_FREE0_9, PC_FREE10
2761 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2762 "Current number of pv entries");
2765 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2767 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2768 "Current number of pv entry chunks");
2769 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2770 "Current number of pv entry chunks allocated");
2771 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2772 "Current number of pv entry chunks frees");
2773 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail,
2774 0, "Number of times tried to get a chunk page but failed.");
2776 static long pv_entry_frees, pv_entry_allocs;
2777 static int pv_entry_spare;
2779 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2780 "Current number of pv entry frees");
2781 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs,
2782 0, "Current number of pv entry allocs");
2783 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2784 "Current number of spare pv entries");
2788 * Is given page managed?
2790 static __inline bool
2791 is_managed(vm_paddr_t pa)
2795 m = PHYS_TO_VM_PAGE(pa);
2798 return ((m->oflags & VPO_UNMANAGED) == 0);
2801 static __inline bool
2802 pte1_is_managed(pt1_entry_t pte1)
2805 return (is_managed(pte1_pa(pte1)));
2808 static __inline bool
2809 pte2_is_managed(pt2_entry_t pte2)
2812 return (is_managed(pte2_pa(pte2)));
2816 * We are in a serious low memory condition. Resort to
2817 * drastic measures to free some pages so we can allocate
2818 * another pv entry chunk.
2821 pmap_pv_reclaim(pmap_t locked_pmap)
2824 struct pv_chunk *pc;
2825 struct md_page *pvh;
2828 pt2_entry_t *pte2p, tpte2;
2832 struct spglist free;
2834 int bit, field, freed;
2836 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2840 TAILQ_INIT(&newtail);
2841 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2842 SLIST_EMPTY(&free))) {
2843 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2844 if (pmap != pc->pc_pmap) {
2846 if (pmap != locked_pmap)
2850 /* Avoid deadlock and lock recursion. */
2851 if (pmap > locked_pmap)
2853 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2855 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2861 * Destroy every non-wired, 4 KB page mapping in the chunk.
2864 for (field = 0; field < _NPCM; field++) {
2865 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2866 inuse != 0; inuse &= ~(1UL << bit)) {
2867 bit = ffs(inuse) - 1;
2868 pv = &pc->pc_pventry[field * 32 + bit];
2870 pte1p = pmap_pte1(pmap, va);
2871 if (pte1_is_section(pte1_load(pte1p)))
2873 pte2p = pmap_pte2(pmap, va);
2874 tpte2 = pte2_load(pte2p);
2875 if ((tpte2 & PTE2_W) == 0)
2876 tpte2 = pte2_load_clear(pte2p);
2877 pmap_pte2_release(pte2p);
2878 if ((tpte2 & PTE2_W) != 0)
2881 ("pmap_pv_reclaim: pmap %p va %#x zero pte",
2883 pmap_tlb_flush(pmap, va);
2884 m = PHYS_TO_VM_PAGE(pte2_pa(tpte2));
2885 if (pte2_is_dirty(tpte2))
2887 if ((tpte2 & PTE2_A) != 0)
2888 vm_page_aflag_set(m, PGA_REFERENCED);
2889 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2890 if (TAILQ_EMPTY(&m->md.pv_list) &&
2891 (m->flags & PG_FICTITIOUS) == 0) {
2892 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2893 if (TAILQ_EMPTY(&pvh->pv_list)) {
2894 vm_page_aflag_clear(m,
2898 pc->pc_map[field] |= 1UL << bit;
2899 pmap_unuse_pt2(pmap, va, &free);
2904 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2907 /* Every freed mapping is for a 4 KB page. */
2908 pmap->pm_stats.resident_count -= freed;
2909 PV_STAT(pv_entry_frees += freed);
2910 PV_STAT(pv_entry_spare += freed);
2911 pv_entry_count -= freed;
2912 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2913 for (field = 0; field < _NPCM; field++)
2914 if (pc->pc_map[field] != pc_freemask[field]) {
2915 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2917 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2920 * One freed pv entry in locked_pmap is
2923 if (pmap == locked_pmap)
2927 if (field == _NPCM) {
2928 PV_STAT(pv_entry_spare -= _NPCPV);
2929 PV_STAT(pc_chunk_count--);
2930 PV_STAT(pc_chunk_frees++);
2931 /* Entire chunk is free; return it. */
2932 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2933 pmap_qremove((vm_offset_t)pc, 1);
2934 pmap_pte2list_free(&pv_vafree, (vm_offset_t)pc);
2939 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2941 if (pmap != locked_pmap)
2944 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2945 m_pc = SLIST_FIRST(&free);
2946 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2947 /* Recycle a freed page table page. */
2948 m_pc->wire_count = 1;
2951 pmap_free_zero_pages(&free);
2956 free_pv_chunk(struct pv_chunk *pc)
2960 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2961 PV_STAT(pv_entry_spare -= _NPCPV);
2962 PV_STAT(pc_chunk_count--);
2963 PV_STAT(pc_chunk_frees++);
2964 /* entire chunk is free, return it */
2965 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2966 pmap_qremove((vm_offset_t)pc, 1);
2967 vm_page_unwire(m, PQ_NONE);
2969 pmap_pte2list_free(&pv_vafree, (vm_offset_t)pc);
2973 * Free the pv_entry back to the free list.
2976 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2978 struct pv_chunk *pc;
2979 int idx, field, bit;
2981 rw_assert(&pvh_global_lock, RA_WLOCKED);
2982 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2983 PV_STAT(pv_entry_frees++);
2984 PV_STAT(pv_entry_spare++);
2986 pc = pv_to_chunk(pv);
2987 idx = pv - &pc->pc_pventry[0];
2990 pc->pc_map[field] |= 1ul << bit;
2991 for (idx = 0; idx < _NPCM; idx++)
2992 if (pc->pc_map[idx] != pc_freemask[idx]) {
2994 * 98% of the time, pc is already at the head of the
2995 * list. If it isn't already, move it to the head.
2997 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2999 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3000 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
3005 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3010 * Get a new pv_entry, allocating a block from the system
3014 get_pv_entry(pmap_t pmap, boolean_t try)
3016 static const struct timeval printinterval = { 60, 0 };
3017 static struct timeval lastprint;
3020 struct pv_chunk *pc;
3023 rw_assert(&pvh_global_lock, RA_WLOCKED);
3024 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3025 PV_STAT(pv_entry_allocs++);
3027 if (pv_entry_count > pv_entry_high_water)
3028 if (ratecheck(&lastprint, &printinterval))
3029 printf("Approaching the limit on PV entries, consider "
3030 "increasing either the vm.pmap.shpgperproc or the "
3031 "vm.pmap.pv_entry_max tunable.\n");
3033 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3035 for (field = 0; field < _NPCM; field++) {
3036 if (pc->pc_map[field]) {
3037 bit = ffs(pc->pc_map[field]) - 1;
3041 if (field < _NPCM) {
3042 pv = &pc->pc_pventry[field * 32 + bit];
3043 pc->pc_map[field] &= ~(1ul << bit);
3044 /* If this was the last item, move it to tail */
3045 for (field = 0; field < _NPCM; field++)
3046 if (pc->pc_map[field] != 0) {
3047 PV_STAT(pv_entry_spare--);
3048 return (pv); /* not full, return */
3050 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3051 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3052 PV_STAT(pv_entry_spare--);
3057 * Access to the pte2list "pv_vafree" is synchronized by the pvh
3058 * global lock. If "pv_vafree" is currently non-empty, it will
3059 * remain non-empty until pmap_pte2list_alloc() completes.
3061 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3062 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
3065 PV_STAT(pc_chunk_tryfail++);
3068 m = pmap_pv_reclaim(pmap);
3072 PV_STAT(pc_chunk_count++);
3073 PV_STAT(pc_chunk_allocs++);
3074 pc = (struct pv_chunk *)pmap_pte2list_alloc(&pv_vafree);
3075 pmap_qenter((vm_offset_t)pc, &m, 1);
3077 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
3078 for (field = 1; field < _NPCM; field++)
3079 pc->pc_map[field] = pc_freemask[field];
3080 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
3081 pv = &pc->pc_pventry[0];
3082 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3083 PV_STAT(pv_entry_spare += _NPCPV - 1);
3088 * Create a pv entry for page at pa for
3092 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
3096 rw_assert(&pvh_global_lock, RA_WLOCKED);
3097 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3098 pv = get_pv_entry(pmap, FALSE);
3100 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3103 static __inline pv_entry_t
3104 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3108 rw_assert(&pvh_global_lock, RA_WLOCKED);
3109 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3110 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3111 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3119 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3123 pv = pmap_pvh_remove(pvh, pmap, va);
3124 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3125 free_pv_entry(pmap, pv);
3129 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
3131 struct md_page *pvh;
3133 rw_assert(&pvh_global_lock, RA_WLOCKED);
3134 pmap_pvh_free(&m->md, pmap, va);
3135 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
3136 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3137 if (TAILQ_EMPTY(&pvh->pv_list))
3138 vm_page_aflag_clear(m, PGA_WRITEABLE);
3143 pmap_pv_demote_pte1(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3145 struct md_page *pvh;
3147 vm_offset_t va_last;
3150 rw_assert(&pvh_global_lock, RA_WLOCKED);
3151 KASSERT((pa & PTE1_OFFSET) == 0,
3152 ("pmap_pv_demote_pte1: pa is not 1mpage aligned"));
3155 * Transfer the 1mpage's pv entry for this mapping to the first
3158 pvh = pa_to_pvh(pa);
3159 va = pte1_trunc(va);
3160 pv = pmap_pvh_remove(pvh, pmap, va);
3161 KASSERT(pv != NULL, ("pmap_pv_demote_pte1: pv not found"));
3162 m = PHYS_TO_VM_PAGE(pa);
3163 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3164 /* Instantiate the remaining NPTE2_IN_PT2 - 1 pv entries. */
3165 va_last = va + PTE1_SIZE - PAGE_SIZE;
3168 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3169 ("pmap_pv_demote_pte1: page %p is not managed", m));
3171 pmap_insert_entry(pmap, va, m);
3172 } while (va < va_last);
3175 #if VM_NRESERVLEVEL > 0
3177 pmap_pv_promote_pte1(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3179 struct md_page *pvh;
3181 vm_offset_t va_last;
3184 rw_assert(&pvh_global_lock, RA_WLOCKED);
3185 KASSERT((pa & PTE1_OFFSET) == 0,
3186 ("pmap_pv_promote_pte1: pa is not 1mpage aligned"));
3189 * Transfer the first page's pv entry for this mapping to the
3190 * 1mpage's pv list. Aside from avoiding the cost of a call
3191 * to get_pv_entry(), a transfer avoids the possibility that
3192 * get_pv_entry() calls pmap_pv_reclaim() and that pmap_pv_reclaim()
3193 * removes one of the mappings that is being promoted.
3195 m = PHYS_TO_VM_PAGE(pa);
3196 va = pte1_trunc(va);
3197 pv = pmap_pvh_remove(&m->md, pmap, va);
3198 KASSERT(pv != NULL, ("pmap_pv_promote_pte1: pv not found"));
3199 pvh = pa_to_pvh(pa);
3200 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3201 /* Free the remaining NPTE2_IN_PT2 - 1 pv entries. */
3202 va_last = va + PTE1_SIZE - PAGE_SIZE;
3206 pmap_pvh_free(&m->md, pmap, va);
3207 } while (va < va_last);
3212 * Conditionally create a pv entry.
3215 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
3219 rw_assert(&pvh_global_lock, RA_WLOCKED);
3220 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3221 if (pv_entry_count < pv_entry_high_water &&
3222 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
3224 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3231 * Create the pv entries for each of the pages within a section.
3234 pmap_pv_insert_pte1(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3236 struct md_page *pvh;
3239 rw_assert(&pvh_global_lock, RA_WLOCKED);
3240 if (pv_entry_count < pv_entry_high_water &&
3241 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
3243 pvh = pa_to_pvh(pa);
3244 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3251 pmap_tlb_flush_pte1(pmap_t pmap, vm_offset_t va, pt1_entry_t npte1)
3254 /* Kill all the small mappings or the big one only. */
3255 if (pte1_is_section(npte1))
3256 pmap_tlb_flush_range(pmap, pte1_trunc(va), PTE1_SIZE);
3258 pmap_tlb_flush(pmap, pte1_trunc(va));
3262 * Update kernel pte1 on all pmaps.
3264 * The following function is called only on one cpu with disabled interrupts.
3265 * In SMP case, smp_rendezvous_cpus() is used to stop other cpus. This way
3266 * nobody can invoke explicit hardware table walk during the update of pte1.
3267 * Unsolicited hardware table walk can still happen, invoked by speculative
3268 * data or instruction prefetch or even by speculative hardware table walk.
3270 * The break-before-make approach should be implemented here. However, it's
3271 * not so easy to do that for kernel mappings as it would be unhappy to unmap
3272 * itself unexpectedly but voluntarily.
3275 pmap_update_pte1_kernel(vm_offset_t va, pt1_entry_t npte1)
3281 * Get current pmap. Interrupts should be disabled here
3282 * so PCPU_GET() is done atomically.
3284 pmap = PCPU_GET(curpmap);
3289 * (1) Change pte1 on current pmap.
3290 * (2) Flush all obsolete TLB entries on current CPU.
3291 * (3) Change pte1 on all pmaps.
3292 * (4) Flush all obsolete TLB entries on all CPUs in SMP case.
3295 pte1p = pmap_pte1(pmap, va);
3296 pte1_store(pte1p, npte1);
3298 /* Kill all the small mappings or the big one only. */
3299 if (pte1_is_section(npte1)) {
3300 pmap_pte1_kern_promotions++;
3301 tlb_flush_range_local(pte1_trunc(va), PTE1_SIZE);
3303 pmap_pte1_kern_demotions++;
3304 tlb_flush_local(pte1_trunc(va));
3308 * In SMP case, this function is called when all cpus are at smp
3309 * rendezvous, so there is no need to use 'allpmaps_lock' lock here.
3310 * In UP case, the function is called with this lock locked.
3312 LIST_FOREACH(pmap, &allpmaps, pm_list) {
3313 pte1p = pmap_pte1(pmap, va);
3314 pte1_store(pte1p, npte1);
3318 /* Kill all the small mappings or the big one only. */
3319 if (pte1_is_section(npte1))
3320 tlb_flush_range(pte1_trunc(va), PTE1_SIZE);
3322 tlb_flush(pte1_trunc(va));
3327 struct pte1_action {
3330 u_int update; /* CPU that updates the PTE1 */
3334 pmap_update_pte1_action(void *arg)
3336 struct pte1_action *act = arg;
3338 if (act->update == PCPU_GET(cpuid))
3339 pmap_update_pte1_kernel(act->va, act->npte1);
3343 * Change pte1 on current pmap.
3344 * Note that kernel pte1 must be changed on all pmaps.
3346 * According to the architecture reference manual published by ARM,
3347 * the behaviour is UNPREDICTABLE when two or more TLB entries map the same VA.
3348 * According to this manual, UNPREDICTABLE behaviours must never happen in
3349 * a viable system. In contrast, on x86 processors, it is not specified which
3350 * TLB entry mapping the virtual address will be used, but the MMU doesn't
3351 * generate a bogus translation the way it does on Cortex-A8 rev 2 (Beaglebone
3354 * It's a problem when either promotion or demotion is being done. The pte1
3355 * update and appropriate TLB flush must be done atomically in general.
3358 pmap_change_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va,
3362 if (pmap == kernel_pmap) {
3363 struct pte1_action act;
3368 act.update = PCPU_GET(cpuid);
3369 smp_rendezvous_cpus(all_cpus, smp_no_rendezvous_barrier,
3370 pmap_update_pte1_action, NULL, &act);
3376 * Use break-before-make approach for changing userland
3377 * mappings. It can cause L1 translation aborts on other
3378 * cores in SMP case. So, special treatment is implemented
3379 * in pmap_fault(). To reduce the likelihood that another core
3380 * will be affected by the broken mapping, disable interrupts
3381 * until the mapping change is completed.
3383 cspr = disable_interrupts(PSR_I | PSR_F);
3385 pmap_tlb_flush_pte1(pmap, va, npte1);
3386 pte1_store(pte1p, npte1);
3387 restore_interrupts(cspr);
3392 pmap_change_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va,
3396 if (pmap == kernel_pmap) {
3397 mtx_lock_spin(&allpmaps_lock);
3398 pmap_update_pte1_kernel(va, npte1);
3399 mtx_unlock_spin(&allpmaps_lock);
3404 * Use break-before-make approach for changing userland
3405 * mappings. It's absolutely safe in UP case when interrupts
3408 cspr = disable_interrupts(PSR_I | PSR_F);
3410 pmap_tlb_flush_pte1(pmap, va, npte1);
3411 pte1_store(pte1p, npte1);
3412 restore_interrupts(cspr);
3417 #if VM_NRESERVLEVEL > 0
3419 * Tries to promote the NPTE2_IN_PT2, contiguous 4KB page mappings that are
3420 * within a single page table page (PT2) to a single 1MB page mapping.
3421 * For promotion to occur, two conditions must be met: (1) the 4KB page
3422 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3423 * mappings must have identical characteristics.
3425 * Managed (PG_MANAGED) mappings within the kernel address space are not
3426 * promoted. The reason is that kernel PTE1s are replicated in each pmap but
3427 * pmap_remove_write(), pmap_clear_modify(), and pmap_clear_reference() only
3428 * read the PTE1 from the kernel pmap.
3431 pmap_promote_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3434 pt2_entry_t *fpte2p, fpte2, fpte2_fav;
3435 pt2_entry_t *pte2p, pte2;
3436 vm_offset_t pteva __unused;
3437 vm_page_t m __unused;
3439 PDEBUG(6, printf("%s(%p): try for va %#x pte1 %#x at %p\n", __func__,
3440 pmap, va, pte1_load(pte1p), pte1p));
3442 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3445 * Examine the first PTE2 in the specified PT2. Abort if this PTE2 is
3446 * either invalid, unused, or does not map the first 4KB physical page
3447 * within a 1MB page.
3449 fpte2p = pmap_pte2_quick(pmap, pte1_trunc(va));
3450 fpte2 = pte2_load(fpte2p);
3451 if ((fpte2 & ((PTE2_FRAME & PTE1_OFFSET) | PTE2_A | PTE2_V)) !=
3452 (PTE2_A | PTE2_V)) {
3453 pmap_pte1_p_failures++;
3454 CTR3(KTR_PMAP, "%s: failure(1) for va %#x in pmap %p",
3455 __func__, va, pmap);
3458 if (pte2_is_managed(fpte2) && pmap == kernel_pmap) {
3459 pmap_pte1_p_failures++;
3460 CTR3(KTR_PMAP, "%s: failure(2) for va %#x in pmap %p",
3461 __func__, va, pmap);
3464 if ((fpte2 & (PTE2_NM | PTE2_RO)) == PTE2_NM) {
3466 * When page is not modified, PTE2_RO can be set without
3467 * a TLB invalidation.
3470 pte2_store(fpte2p, fpte2);
3474 * Examine each of the other PTE2s in the specified PT2. Abort if this
3475 * PTE2 maps an unexpected 4KB physical page or does not have identical
3476 * characteristics to the first PTE2.
3478 fpte2_fav = (fpte2 & (PTE2_FRAME | PTE2_A | PTE2_V));
3479 fpte2_fav += PTE1_SIZE - PTE2_SIZE; /* examine from the end */
3480 for (pte2p = fpte2p + NPTE2_IN_PT2 - 1; pte2p > fpte2p; pte2p--) {
3481 pte2 = pte2_load(pte2p);
3482 if ((pte2 & (PTE2_FRAME | PTE2_A | PTE2_V)) != fpte2_fav) {
3483 pmap_pte1_p_failures++;
3484 CTR3(KTR_PMAP, "%s: failure(3) for va %#x in pmap %p",
3485 __func__, va, pmap);
3488 if ((pte2 & (PTE2_NM | PTE2_RO)) == PTE2_NM) {
3490 * When page is not modified, PTE2_RO can be set
3491 * without a TLB invalidation. See note above.
3494 pte2_store(pte2p, pte2);
3495 pteva = pte1_trunc(va) | (pte2 & PTE1_OFFSET &
3497 CTR3(KTR_PMAP, "%s: protect for va %#x in pmap %p",
3498 __func__, pteva, pmap);
3500 if ((pte2 & PTE2_PROMOTE) != (fpte2 & PTE2_PROMOTE)) {
3501 pmap_pte1_p_failures++;
3502 CTR3(KTR_PMAP, "%s: failure(4) for va %#x in pmap %p",
3503 __func__, va, pmap);
3507 fpte2_fav -= PTE2_SIZE;
3510 * The page table page in its current state will stay in PT2TAB
3511 * until the PTE1 mapping the section is demoted by pmap_demote_pte1()
3512 * or destroyed by pmap_remove_pte1().
3514 * Note that L2 page table size is not equal to PAGE_SIZE.
3516 m = PHYS_TO_VM_PAGE(trunc_page(pte1_link_pa(pte1_load(pte1p))));
3517 KASSERT(m >= vm_page_array && m < &vm_page_array[vm_page_array_size],
3518 ("%s: PT2 page is out of range", __func__));
3519 KASSERT(m->pindex == (pte1_index(va) & ~PT2PG_MASK),
3520 ("%s: PT2 page's pindex is wrong", __func__));
3523 * Get pte1 from pte2 format.
3525 npte1 = (fpte2 & PTE1_FRAME) | ATTR_TO_L1(fpte2) | PTE1_V;
3528 * Promote the pv entries.
3530 if (pte2_is_managed(fpte2))
3531 pmap_pv_promote_pte1(pmap, va, pte1_pa(npte1));
3534 * Promote the mappings.
3536 pmap_change_pte1(pmap, pte1p, va, npte1);
3538 pmap_pte1_promotions++;
3539 CTR3(KTR_PMAP, "%s: success for va %#x in pmap %p",
3540 __func__, va, pmap);
3542 PDEBUG(6, printf("%s(%p): success for va %#x pte1 %#x(%#x) at %p\n",
3543 __func__, pmap, va, npte1, pte1_load(pte1p), pte1p));
3545 #endif /* VM_NRESERVLEVEL > 0 */
3548 * Zero L2 page table page.
3550 static __inline void
3551 pmap_clear_pt2(pt2_entry_t *fpte2p)
3555 for (pte2p = fpte2p; pte2p < fpte2p + NPTE2_IN_PT2; pte2p++)
3561 * Removes a 1MB page mapping from the kernel pmap.
3564 pmap_remove_kernel_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3568 pt2_entry_t *fpte2p;
3571 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3572 m = pmap_pt2_page(pmap, va);
3575 * QQQ: Is this function called only on promoted pte1?
3576 * We certainly do section mappings directly
3577 * (without promotion) in kernel !!!
3579 panic("%s: missing pt2 page", __func__);
3581 pte1_idx = pte1_index(va);
3584 * Initialize the L2 page table.
3586 fpte2p = page_pt2(pt2map_pt2pg(va), pte1_idx);
3587 pmap_clear_pt2(fpte2p);
3590 * Remove the mapping.
3592 pt2_pa = page_pt2pa(VM_PAGE_TO_PHYS(m), pte1_idx);
3593 pmap_kenter_pte1(va, PTE1_LINK(pt2_pa));
3596 * QQQ: We do not need to invalidate PT2MAP mapping
3597 * as we did not change it. I.e. the L2 page table page
3598 * was and still is mapped the same way.
3603 * Do the things to unmap a section in a process
3606 pmap_remove_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t sva,
3607 struct spglist *free)
3610 struct md_page *pvh;
3611 vm_offset_t eva, va;
3614 PDEBUG(6, printf("%s(%p): va %#x pte1 %#x at %p\n", __func__, pmap, sva,
3615 pte1_load(pte1p), pte1p));
3617 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3618 KASSERT((sva & PTE1_OFFSET) == 0,
3619 ("%s: sva is not 1mpage aligned", __func__));
3622 * Clear and invalidate the mapping. It should occupy one and only TLB
3623 * entry. So, pmap_tlb_flush() called with aligned address should be
3626 opte1 = pte1_load_clear(pte1p);
3627 pmap_tlb_flush(pmap, sva);
3629 if (pte1_is_wired(opte1))
3630 pmap->pm_stats.wired_count -= PTE1_SIZE / PAGE_SIZE;
3631 pmap->pm_stats.resident_count -= PTE1_SIZE / PAGE_SIZE;
3632 if (pte1_is_managed(opte1)) {
3633 pvh = pa_to_pvh(pte1_pa(opte1));
3634 pmap_pvh_free(pvh, pmap, sva);
3635 eva = sva + PTE1_SIZE;
3636 for (va = sva, m = PHYS_TO_VM_PAGE(pte1_pa(opte1));
3637 va < eva; va += PAGE_SIZE, m++) {
3638 if (pte1_is_dirty(opte1))
3641 vm_page_aflag_set(m, PGA_REFERENCED);
3642 if (TAILQ_EMPTY(&m->md.pv_list) &&
3643 TAILQ_EMPTY(&pvh->pv_list))
3644 vm_page_aflag_clear(m, PGA_WRITEABLE);
3647 if (pmap == kernel_pmap) {
3649 * L2 page table(s) can't be removed from kernel map as
3650 * kernel counts on it (stuff around pmap_growkernel()).
3652 pmap_remove_kernel_pte1(pmap, pte1p, sva);
3655 * Get associated L2 page table page.
3656 * It's possible that the page was never allocated.
3658 m = pmap_pt2_page(pmap, sva);
3660 pmap_unwire_pt2_all(pmap, sva, m, free);
3665 * Fills L2 page table page with mappings to consecutive physical pages.
3667 static __inline void
3668 pmap_fill_pt2(pt2_entry_t *fpte2p, pt2_entry_t npte2)
3672 for (pte2p = fpte2p; pte2p < fpte2p + NPTE2_IN_PT2; pte2p++) {
3673 pte2_store(pte2p, npte2);
3679 * Tries to demote a 1MB page mapping. If demotion fails, the
3680 * 1MB page mapping is invalidated.
3683 pmap_demote_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3685 pt1_entry_t opte1, npte1;
3686 pt2_entry_t *fpte2p, npte2;
3687 vm_paddr_t pt2pg_pa, pt2_pa;
3689 struct spglist free;
3690 uint32_t pte1_idx, isnew = 0;
3692 PDEBUG(6, printf("%s(%p): try for va %#x pte1 %#x at %p\n", __func__,
3693 pmap, va, pte1_load(pte1p), pte1p));
3695 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3697 opte1 = pte1_load(pte1p);
3698 KASSERT(pte1_is_section(opte1), ("%s: opte1 not a section", __func__));
3700 if ((opte1 & PTE1_A) == 0 || (m = pmap_pt2_page(pmap, va)) == NULL) {
3701 KASSERT(!pte1_is_wired(opte1),
3702 ("%s: PT2 page for a wired mapping is missing", __func__));
3705 * Invalidate the 1MB page mapping and return
3706 * "failure" if the mapping was never accessed or the
3707 * allocation of the new page table page fails.
3709 if ((opte1 & PTE1_A) == 0 || (m = vm_page_alloc(NULL,
3710 pte1_index(va) & ~PT2PG_MASK, VM_ALLOC_NOOBJ |
3711 VM_ALLOC_NORMAL | VM_ALLOC_WIRED)) == NULL) {
3713 pmap_remove_pte1(pmap, pte1p, pte1_trunc(va), &free);
3714 pmap_free_zero_pages(&free);
3715 CTR3(KTR_PMAP, "%s: failure for va %#x in pmap %p",
3716 __func__, va, pmap);
3719 if (va < VM_MAXUSER_ADDRESS)
3720 pmap->pm_stats.resident_count++;
3725 * We init all L2 page tables in the page even if
3726 * we are going to change everything for one L2 page
3729 pt2pg_pa = pmap_pt2pg_init(pmap, va, m);
3731 if (va < VM_MAXUSER_ADDRESS) {
3732 if (pt2_is_empty(m, va))
3733 isnew = 1; /* Demoting section w/o promotion. */
3736 KASSERT(pt2_is_full(m, va), ("%s: bad PT2 wire"
3737 " count %u", __func__,
3738 pt2_wirecount_get(m, pte1_index(va))));
3743 pt2pg_pa = VM_PAGE_TO_PHYS(m);
3744 pte1_idx = pte1_index(va);
3746 * If the pmap is current, then the PT2MAP can provide access to
3747 * the page table page (promoted L2 page tables are not unmapped).
3748 * Otherwise, temporarily map the L2 page table page (m) into
3749 * the kernel's address space at either PADDR1 or PADDR2.
3751 * Note that L2 page table size is not equal to PAGE_SIZE.
3753 if (pmap_is_current(pmap))
3754 fpte2p = page_pt2(pt2map_pt2pg(va), pte1_idx);
3755 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
3756 if (pte2_pa(pte2_load(PMAP1)) != pt2pg_pa) {
3757 pte2_store(PMAP1, PTE2_KPT(pt2pg_pa));
3759 PMAP1cpu = PCPU_GET(cpuid);
3761 tlb_flush_local((vm_offset_t)PADDR1);
3765 if (PMAP1cpu != PCPU_GET(cpuid)) {
3766 PMAP1cpu = PCPU_GET(cpuid);
3767 tlb_flush_local((vm_offset_t)PADDR1);
3772 fpte2p = page_pt2((vm_offset_t)PADDR1, pte1_idx);
3774 mtx_lock(&PMAP2mutex);
3775 if (pte2_pa(pte2_load(PMAP2)) != pt2pg_pa) {
3776 pte2_store(PMAP2, PTE2_KPT(pt2pg_pa));
3777 tlb_flush((vm_offset_t)PADDR2);
3779 fpte2p = page_pt2((vm_offset_t)PADDR2, pte1_idx);
3781 pt2_pa = page_pt2pa(pt2pg_pa, pte1_idx);
3782 npte1 = PTE1_LINK(pt2_pa);
3784 KASSERT((opte1 & PTE1_A) != 0,
3785 ("%s: opte1 is missing PTE1_A", __func__));
3786 KASSERT((opte1 & (PTE1_NM | PTE1_RO)) != PTE1_NM,
3787 ("%s: opte1 has PTE1_NM", __func__));
3790 * Get pte2 from pte1 format.
3792 npte2 = pte1_pa(opte1) | ATTR_TO_L2(opte1) | PTE2_V;
3795 * If the L2 page table page is new, initialize it. If the mapping
3796 * has changed attributes, update the page table entries.
3799 pt2_wirecount_set(m, pte1_idx, NPTE2_IN_PT2);
3800 pmap_fill_pt2(fpte2p, npte2);
3801 } else if ((pte2_load(fpte2p) & PTE2_PROMOTE) !=
3802 (npte2 & PTE2_PROMOTE))
3803 pmap_fill_pt2(fpte2p, npte2);
3805 KASSERT(pte2_pa(pte2_load(fpte2p)) == pte2_pa(npte2),
3806 ("%s: fpte2p and npte2 map different physical addresses",
3809 if (fpte2p == PADDR2)
3810 mtx_unlock(&PMAP2mutex);
3813 * Demote the mapping. This pmap is locked. The old PTE1 has
3814 * PTE1_A set. If the old PTE1 has not PTE1_RO set, it also
3815 * has not PTE1_NM set. Thus, there is no danger of a race with
3816 * another processor changing the setting of PTE1_A and/or PTE1_NM
3817 * between the read above and the store below.
3819 pmap_change_pte1(pmap, pte1p, va, npte1);
3822 * Demote the pv entry. This depends on the earlier demotion
3823 * of the mapping. Specifically, the (re)creation of a per-
3824 * page pv entry might trigger the execution of pmap_pv_reclaim(),
3825 * which might reclaim a newly (re)created per-page pv entry
3826 * and destroy the associated mapping. In order to destroy
3827 * the mapping, the PTE1 must have already changed from mapping
3828 * the 1mpage to referencing the page table page.
3830 if (pte1_is_managed(opte1))
3831 pmap_pv_demote_pte1(pmap, va, pte1_pa(opte1));
3833 pmap_pte1_demotions++;
3834 CTR3(KTR_PMAP, "%s: success for va %#x in pmap %p",
3835 __func__, va, pmap);
3837 PDEBUG(6, printf("%s(%p): success for va %#x pte1 %#x(%#x) at %p\n",
3838 __func__, pmap, va, npte1, pte1_load(pte1p), pte1p));
3843 * Insert the given physical page (p) at
3844 * the specified virtual address (v) in the
3845 * target physical map with the protection requested.
3847 * If specified, the page will be wired down, meaning
3848 * that the related pte can not be reclaimed.
3850 * NB: This is the only routine which MAY NOT lazy-evaluate
3851 * or lose information. That is, this routine must actually
3852 * insert this page into the given map NOW.
3855 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3856 u_int flags, int8_t psind)
3860 pt2_entry_t npte2, opte2;
3863 vm_page_t mpte2, om;
3866 va = trunc_page(va);
3868 wired = (flags & PMAP_ENTER_WIRED) != 0;
3870 KASSERT(va <= vm_max_kernel_address, ("%s: toobig", __func__));
3871 KASSERT(va < UPT2V_MIN_ADDRESS || va >= UPT2V_MAX_ADDRESS,
3872 ("%s: invalid to pmap_enter page table pages (va: 0x%x)", __func__,
3874 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3875 VM_OBJECT_ASSERT_LOCKED(m->object);
3877 rw_wlock(&pvh_global_lock);
3882 * In the case that a page table page is not
3883 * resident, we are creating it here.
3885 if (va < VM_MAXUSER_ADDRESS) {
3886 mpte2 = pmap_allocpte2(pmap, va, flags);
3887 if (mpte2 == NULL) {
3888 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3889 ("pmap_allocpte2 failed with sleep allowed"));
3891 rw_wunlock(&pvh_global_lock);
3893 return (KERN_RESOURCE_SHORTAGE);
3896 pte1p = pmap_pte1(pmap, va);
3897 if (pte1_is_section(pte1_load(pte1p)))
3898 panic("%s: attempted on 1MB page", __func__);
3899 pte2p = pmap_pte2_quick(pmap, va);
3901 panic("%s: invalid L1 page table entry va=%#x", __func__, va);
3904 pa = VM_PAGE_TO_PHYS(m);
3905 opte2 = pte2_load(pte2p);
3906 opa = pte2_pa(opte2);
3908 * Mapping has not changed, must be protection or wiring change.
3910 if (pte2_is_valid(opte2) && (opa == pa)) {
3912 * Wiring change, just update stats. We don't worry about
3913 * wiring PT2 pages as they remain resident as long as there
3914 * are valid mappings in them. Hence, if a user page is wired,
3915 * the PT2 page will be also.
3917 if (wired && !pte2_is_wired(opte2))
3918 pmap->pm_stats.wired_count++;
3919 else if (!wired && pte2_is_wired(opte2))
3920 pmap->pm_stats.wired_count--;
3923 * Remove extra pte2 reference
3926 pt2_wirecount_dec(mpte2, pte1_index(va));
3927 if (pte2_is_managed(opte2))
3933 * QQQ: We think that changing physical address on writeable mapping
3934 * is not safe. Well, maybe on kernel address space with correct
3935 * locking, it can make a sense. However, we have no idea why
3936 * anyone should do that on user address space. Are we wrong?
3938 KASSERT((opa == 0) || (opa == pa) ||
3939 !pte2_is_valid(opte2) || ((opte2 & PTE2_RO) != 0),
3940 ("%s: pmap %p va %#x(%#x) opa %#x pa %#x - gotcha %#x %#x!",
3941 __func__, pmap, va, opte2, opa, pa, flags, prot));
3946 * Mapping has changed, invalidate old range and fall through to
3947 * handle validating new mapping.
3950 if (pte2_is_wired(opte2))
3951 pmap->pm_stats.wired_count--;
3952 if (pte2_is_managed(opte2)) {
3953 om = PHYS_TO_VM_PAGE(opa);
3954 pv = pmap_pvh_remove(&om->md, pmap, va);
3957 * Remove extra pte2 reference
3960 pt2_wirecount_dec(mpte2, va >> PTE1_SHIFT);
3962 pmap->pm_stats.resident_count++;
3965 * Enter on the PV list if part of our managed memory.
3967 if ((m->oflags & VPO_UNMANAGED) == 0) {
3968 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3969 ("%s: managed mapping within the clean submap", __func__));
3971 pv = get_pv_entry(pmap, FALSE);
3973 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3974 } else if (pv != NULL)
3975 free_pv_entry(pmap, pv);
3978 * Increment counters
3981 pmap->pm_stats.wired_count++;
3985 * Now validate mapping with desired protection/wiring.
3987 npte2 = PTE2(pa, PTE2_NM, vm_page_pte2_attr(m));
3988 if (prot & VM_PROT_WRITE) {
3989 if (pte2_is_managed(npte2))
3990 vm_page_aflag_set(m, PGA_WRITEABLE);
3994 if ((prot & VM_PROT_EXECUTE) == 0)
3998 if (va < VM_MAXUSER_ADDRESS)
4000 if (pmap != kernel_pmap)
4004 * If the mapping or permission bits are different, we need
4005 * to update the pte2.
4007 * QQQ: Think again and again what to do
4008 * if the mapping is going to be changed!
4010 if ((opte2 & ~(PTE2_NM | PTE2_A)) != (npte2 & ~(PTE2_NM | PTE2_A))) {
4012 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4013 * is set. Do it now, before the mapping is stored and made
4014 * valid for hardware table walk. If done later, there is a race
4015 * for other threads of current process in lazy loading case.
4016 * Don't do it for kernel memory which is mapped with exec
4017 * permission even if the memory isn't going to hold executable
4018 * code. The only time when icache sync is needed is after
4019 * kernel module is loaded and the relocation info is processed.
4020 * And it's done in elf_cpu_load_file().
4022 * QQQ: (1) Does it exist any better way where
4023 * or how to sync icache?
4024 * (2) Now, we do it on a page basis.
4026 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
4027 m->md.pat_mode == VM_MEMATTR_WB_WA &&
4028 (opa != pa || (opte2 & PTE2_NX)))
4029 cache_icache_sync_fresh(va, pa, PAGE_SIZE);
4032 if (flags & VM_PROT_WRITE)
4034 if (opte2 & PTE2_V) {
4035 /* Change mapping with break-before-make approach. */
4036 opte2 = pte2_load_clear(pte2p);
4037 pmap_tlb_flush(pmap, va);
4038 pte2_store(pte2p, npte2);
4039 if (opte2 & PTE2_A) {
4040 if (pte2_is_managed(opte2))
4041 vm_page_aflag_set(om, PGA_REFERENCED);
4043 if (pte2_is_dirty(opte2)) {
4044 if (pte2_is_managed(opte2))
4047 if (pte2_is_managed(opte2) &&
4048 TAILQ_EMPTY(&om->md.pv_list) &&
4049 ((om->flags & PG_FICTITIOUS) != 0 ||
4050 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
4051 vm_page_aflag_clear(om, PGA_WRITEABLE);
4053 pte2_store(pte2p, npte2);
4058 * QQQ: In time when both access and not mofified bits are
4059 * emulated by software, this should not happen. Some
4060 * analysis is need, if this really happen. Missing
4061 * tlb flush somewhere could be the reason.
4063 panic("%s: pmap %p va %#x opte2 %x npte2 %x !!", __func__, pmap,
4068 #if VM_NRESERVLEVEL > 0
4070 * If both the L2 page table page and the reservation are fully
4071 * populated, then attempt promotion.
4073 if ((mpte2 == NULL || pt2_is_full(mpte2, va)) &&
4074 sp_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
4075 vm_reserv_level_iffullpop(m) == 0)
4076 pmap_promote_pte1(pmap, pte1p, va);
4079 rw_wunlock(&pvh_global_lock);
4081 return (KERN_SUCCESS);
4085 * Do the things to unmap a page in a process.
4088 pmap_remove_pte2(pmap_t pmap, pt2_entry_t *pte2p, vm_offset_t va,
4089 struct spglist *free)
4094 rw_assert(&pvh_global_lock, RA_WLOCKED);
4095 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4097 /* Clear and invalidate the mapping. */
4098 opte2 = pte2_load_clear(pte2p);
4099 pmap_tlb_flush(pmap, va);
4101 KASSERT(pte2_is_valid(opte2), ("%s: pmap %p va %#x not link pte2 %#x",
4102 __func__, pmap, va, opte2));
4105 pmap->pm_stats.wired_count -= 1;
4106 pmap->pm_stats.resident_count -= 1;
4107 if (pte2_is_managed(opte2)) {
4108 m = PHYS_TO_VM_PAGE(pte2_pa(opte2));
4109 if (pte2_is_dirty(opte2))
4112 vm_page_aflag_set(m, PGA_REFERENCED);
4113 pmap_remove_entry(pmap, m, va);
4115 return (pmap_unuse_pt2(pmap, va, free));
4119 * Remove a single page from a process address space.
4122 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
4126 rw_assert(&pvh_global_lock, RA_WLOCKED);
4127 KASSERT(curthread->td_pinned > 0,
4128 ("%s: curthread not pinned", __func__));
4129 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4130 if ((pte2p = pmap_pte2_quick(pmap, va)) == NULL ||
4131 !pte2_is_valid(pte2_load(pte2p)))
4133 pmap_remove_pte2(pmap, pte2p, va, free);
4137 * Remove the given range of addresses from the specified map.
4139 * It is assumed that the start and end are properly
4140 * rounded to the page size.
4143 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4146 pt1_entry_t *pte1p, pte1;
4147 pt2_entry_t *pte2p, pte2;
4148 struct spglist free;
4151 * Perform an unsynchronized read. This is, however, safe.
4153 if (pmap->pm_stats.resident_count == 0)
4158 rw_wlock(&pvh_global_lock);
4163 * Special handling of removing one page. A very common
4164 * operation and easy to short circuit some code.
4166 if (sva + PAGE_SIZE == eva) {
4167 pte1 = pte1_load(pmap_pte1(pmap, sva));
4168 if (pte1_is_link(pte1)) {
4169 pmap_remove_page(pmap, sva, &free);
4174 for (; sva < eva; sva = nextva) {
4176 * Calculate address for next L2 page table.
4178 nextva = pte1_trunc(sva + PTE1_SIZE);
4181 if (pmap->pm_stats.resident_count == 0)
4184 pte1p = pmap_pte1(pmap, sva);
4185 pte1 = pte1_load(pte1p);
4188 * Weed out invalid mappings. Note: we assume that the L1 page
4189 * table is always allocated, and in kernel virtual.
4194 if (pte1_is_section(pte1)) {
4196 * Are we removing the entire large page? If not,
4197 * demote the mapping and fall through.
4199 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
4200 pmap_remove_pte1(pmap, pte1p, sva, &free);
4202 } else if (!pmap_demote_pte1(pmap, pte1p, sva)) {
4203 /* The large page mapping was destroyed. */
4208 /* Update pte1 after demotion. */
4209 pte1 = pte1_load(pte1p);
4214 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
4215 " is not link", __func__, pmap, sva, pte1, pte1p));
4218 * Limit our scan to either the end of the va represented
4219 * by the current L2 page table page, or to the end of the
4220 * range being removed.
4225 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva;
4226 pte2p++, sva += PAGE_SIZE) {
4227 pte2 = pte2_load(pte2p);
4228 if (!pte2_is_valid(pte2))
4230 if (pmap_remove_pte2(pmap, pte2p, sva, &free))
4236 rw_wunlock(&pvh_global_lock);
4238 pmap_free_zero_pages(&free);
4242 * Routine: pmap_remove_all
4244 * Removes this physical page from
4245 * all physical maps in which it resides.
4246 * Reflects back modify bits to the pager.
4249 * Original versions of this routine were very
4250 * inefficient because they iteratively called
4251 * pmap_remove (slow...)
4255 pmap_remove_all(vm_page_t m)
4257 struct md_page *pvh;
4260 pt2_entry_t *pte2p, opte2;
4263 struct spglist free;
4265 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4266 ("%s: page %p is not managed", __func__, m));
4268 rw_wlock(&pvh_global_lock);
4270 if ((m->flags & PG_FICTITIOUS) != 0)
4271 goto small_mappings;
4272 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4273 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
4277 pte1p = pmap_pte1(pmap, va);
4278 (void)pmap_demote_pte1(pmap, pte1p, va);
4282 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4285 pmap->pm_stats.resident_count--;
4286 pte1p = pmap_pte1(pmap, pv->pv_va);
4287 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found "
4288 "a 1mpage in page %p's pv list", __func__, m));
4289 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
4290 opte2 = pte2_load_clear(pte2p);
4291 pmap_tlb_flush(pmap, pv->pv_va);
4292 KASSERT(pte2_is_valid(opte2), ("%s: pmap %p va %x zero pte2",
4293 __func__, pmap, pv->pv_va));
4294 if (pte2_is_wired(opte2))
4295 pmap->pm_stats.wired_count--;
4297 vm_page_aflag_set(m, PGA_REFERENCED);
4300 * Update the vm_page_t clean and reference bits.
4302 if (pte2_is_dirty(opte2))
4304 pmap_unuse_pt2(pmap, pv->pv_va, &free);
4305 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4306 free_pv_entry(pmap, pv);
4309 vm_page_aflag_clear(m, PGA_WRITEABLE);
4311 rw_wunlock(&pvh_global_lock);
4312 pmap_free_zero_pages(&free);
4316 * Just subroutine for pmap_remove_pages() to reasonably satisfy
4317 * good coding style, a.k.a. 80 character line width limit hell.
4319 static __inline void
4320 pmap_remove_pte1_quick(pmap_t pmap, pt1_entry_t pte1, pv_entry_t pv,
4321 struct spglist *free)
4324 vm_page_t m, mt, mpt2pg;
4325 struct md_page *pvh;
4328 m = PHYS_TO_VM_PAGE(pa);
4330 KASSERT(m->phys_addr == pa, ("%s: vm_page_t %p addr mismatch %#x %#x",
4331 __func__, m, m->phys_addr, pa));
4332 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4333 m < &vm_page_array[vm_page_array_size],
4334 ("%s: bad pte1 %#x", __func__, pte1));
4336 if (pte1_is_dirty(pte1)) {
4337 for (mt = m; mt < &m[PTE1_SIZE / PAGE_SIZE]; mt++)
4341 pmap->pm_stats.resident_count -= PTE1_SIZE / PAGE_SIZE;
4342 pvh = pa_to_pvh(pa);
4343 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4344 if (TAILQ_EMPTY(&pvh->pv_list)) {
4345 for (mt = m; mt < &m[PTE1_SIZE / PAGE_SIZE]; mt++)
4346 if (TAILQ_EMPTY(&mt->md.pv_list))
4347 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4349 mpt2pg = pmap_pt2_page(pmap, pv->pv_va);
4351 pmap_unwire_pt2_all(pmap, pv->pv_va, mpt2pg, free);
4355 * Just subroutine for pmap_remove_pages() to reasonably satisfy
4356 * good coding style, a.k.a. 80 character line width limit hell.
4358 static __inline void
4359 pmap_remove_pte2_quick(pmap_t pmap, pt2_entry_t pte2, pv_entry_t pv,
4360 struct spglist *free)
4364 struct md_page *pvh;
4367 m = PHYS_TO_VM_PAGE(pa);
4369 KASSERT(m->phys_addr == pa, ("%s: vm_page_t %p addr mismatch %#x %#x",
4370 __func__, m, m->phys_addr, pa));
4371 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4372 m < &vm_page_array[vm_page_array_size],
4373 ("%s: bad pte2 %#x", __func__, pte2));
4375 if (pte2_is_dirty(pte2))
4378 pmap->pm_stats.resident_count--;
4379 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4380 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
4381 pvh = pa_to_pvh(pa);
4382 if (TAILQ_EMPTY(&pvh->pv_list))
4383 vm_page_aflag_clear(m, PGA_WRITEABLE);
4385 pmap_unuse_pt2(pmap, pv->pv_va, free);
4389 * Remove all pages from specified address space this aids process
4390 * exit speeds. Also, this code is special cased for current process
4391 * only, but can have the more generic (and slightly slower) mode enabled.
4392 * This is much faster than pmap_remove in the case of running down
4393 * an entire address space.
4396 pmap_remove_pages(pmap_t pmap)
4398 pt1_entry_t *pte1p, pte1;
4399 pt2_entry_t *pte2p, pte2;
4401 struct pv_chunk *pc, *npc;
4402 struct spglist free;
4405 uint32_t inuse, bitmask;
4409 * Assert that the given pmap is only active on the current
4410 * CPU. Unfortunately, we cannot block another CPU from
4411 * activating the pmap while this function is executing.
4413 KASSERT(pmap == vmspace_pmap(curthread->td_proc->p_vmspace),
4414 ("%s: non-current pmap %p", __func__, pmap));
4415 #if defined(SMP) && defined(INVARIANTS)
4417 cpuset_t other_cpus;
4420 other_cpus = pmap->pm_active;
4421 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
4423 KASSERT(CPU_EMPTY(&other_cpus),
4424 ("%s: pmap %p active on other cpus", __func__, pmap));
4428 rw_wlock(&pvh_global_lock);
4431 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4432 KASSERT(pc->pc_pmap == pmap, ("%s: wrong pmap %p %p",
4433 __func__, pmap, pc->pc_pmap));
4435 for (field = 0; field < _NPCM; field++) {
4436 inuse = (~(pc->pc_map[field])) & pc_freemask[field];
4437 while (inuse != 0) {
4438 bit = ffs(inuse) - 1;
4439 bitmask = 1UL << bit;
4440 idx = field * 32 + bit;
4441 pv = &pc->pc_pventry[idx];
4445 * Note that we cannot remove wired pages
4446 * from a process' mapping at this time
4448 pte1p = pmap_pte1(pmap, pv->pv_va);
4449 pte1 = pte1_load(pte1p);
4450 if (pte1_is_section(pte1)) {
4451 if (pte1_is_wired(pte1)) {
4456 pmap_remove_pte1_quick(pmap, pte1, pv,
4459 else if (pte1_is_link(pte1)) {
4460 pte2p = pt2map_entry(pv->pv_va);
4461 pte2 = pte2_load(pte2p);
4463 if (!pte2_is_valid(pte2)) {
4464 printf("%s: pmap %p va %#x "
4465 "pte2 %#x\n", __func__,
4466 pmap, pv->pv_va, pte2);
4470 if (pte2_is_wired(pte2)) {
4475 pmap_remove_pte2_quick(pmap, pte2, pv,
4478 printf("%s: pmap %p va %#x pte1 %#x\n",
4479 __func__, pmap, pv->pv_va, pte1);
4484 PV_STAT(pv_entry_frees++);
4485 PV_STAT(pv_entry_spare++);
4487 pc->pc_map[field] |= bitmask;
4491 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4495 tlb_flush_all_ng_local();
4497 rw_wunlock(&pvh_global_lock);
4499 pmap_free_zero_pages(&free);
4503 * This code makes some *MAJOR* assumptions:
4504 * 1. Current pmap & pmap exists.
4507 * 4. No L2 page table pages.
4508 * but is *MUCH* faster than pmap_enter...
4511 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4512 vm_prot_t prot, vm_page_t mpt2pg)
4514 pt2_entry_t *pte2p, pte2;
4516 struct spglist free;
4519 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
4520 (m->oflags & VPO_UNMANAGED) != 0,
4521 ("%s: managed mapping within the clean submap", __func__));
4522 rw_assert(&pvh_global_lock, RA_WLOCKED);
4523 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4526 * In the case that a L2 page table page is not
4527 * resident, we are creating it here.
4529 if (va < VM_MAXUSER_ADDRESS) {
4531 pt1_entry_t pte1, *pte1p;
4535 * Get L1 page table things.
4537 pte1_idx = pte1_index(va);
4538 pte1p = pmap_pte1(pmap, va);
4539 pte1 = pte1_load(pte1p);
4541 if (mpt2pg && (mpt2pg->pindex == (pte1_idx & ~PT2PG_MASK))) {
4543 * Each of NPT2_IN_PG L2 page tables on the page can
4544 * come here. Make sure that associated L1 page table
4545 * link is established.
4547 * QQQ: It comes that we don't establish all links to
4548 * L2 page tables for newly allocated L2 page
4551 KASSERT(!pte1_is_section(pte1),
4552 ("%s: pte1 %#x is section", __func__, pte1));
4553 if (!pte1_is_link(pte1)) {
4554 pt2_pa = page_pt2pa(VM_PAGE_TO_PHYS(mpt2pg),
4556 pte1_store(pte1p, PTE1_LINK(pt2_pa));
4558 pt2_wirecount_inc(mpt2pg, pte1_idx);
4561 * If the L2 page table page is mapped, we just
4562 * increment the hold count, and activate it.
4564 if (pte1_is_section(pte1)) {
4566 } else if (pte1_is_link(pte1)) {
4567 mpt2pg = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
4568 pt2_wirecount_inc(mpt2pg, pte1_idx);
4570 mpt2pg = _pmap_allocpte2(pmap, va,
4571 PMAP_ENTER_NOSLEEP);
4581 * This call to pt2map_entry() makes the assumption that we are
4582 * entering the page into the current pmap. In order to support
4583 * quick entry into any pmap, one would likely use pmap_pte2_quick().
4584 * But that isn't as quick as pt2map_entry().
4586 pte2p = pt2map_entry(va);
4587 pte2 = pte2_load(pte2p);
4588 if (pte2_is_valid(pte2)) {
4589 if (mpt2pg != NULL) {
4591 * Remove extra pte2 reference
4593 pt2_wirecount_dec(mpt2pg, pte1_index(va));
4600 * Enter on the PV list if part of our managed memory.
4602 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4603 !pmap_try_insert_pv_entry(pmap, va, m)) {
4604 if (mpt2pg != NULL) {
4606 if (pmap_unwire_pt2(pmap, va, mpt2pg, &free)) {
4607 pmap_tlb_flush(pmap, va);
4608 pmap_free_zero_pages(&free);
4617 * Increment counters
4619 pmap->pm_stats.resident_count++;
4622 * Now validate mapping with RO protection
4624 pa = VM_PAGE_TO_PHYS(m);
4625 l2prot = PTE2_RO | PTE2_NM;
4626 if (va < VM_MAXUSER_ADDRESS)
4627 l2prot |= PTE2_U | PTE2_NG;
4628 if ((prot & VM_PROT_EXECUTE) == 0)
4630 else if (m->md.pat_mode == VM_MEMATTR_WB_WA && pmap != kernel_pmap) {
4632 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4633 * is set. QQQ: For more info, see comments in pmap_enter().
4635 cache_icache_sync_fresh(va, pa, PAGE_SIZE);
4637 pte2_store(pte2p, PTE2(pa, l2prot, vm_page_pte2_attr(m)));
4643 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4646 rw_wlock(&pvh_global_lock);
4648 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
4649 rw_wunlock(&pvh_global_lock);
4654 * Tries to create 1MB page mapping. Returns TRUE if successful and
4655 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
4656 * blocking, (2) a mapping already exists at the specified virtual address, or
4657 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
4660 pmap_enter_pte1(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4666 rw_assert(&pvh_global_lock, RA_WLOCKED);
4667 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4668 pte1p = pmap_pte1(pmap, va);
4669 if (pte1_is_valid(pte1_load(pte1p))) {
4670 CTR3(KTR_PMAP, "%s: failure for va %#lx in pmap %p", __func__,
4674 if ((m->oflags & VPO_UNMANAGED) == 0) {
4676 * Abort this mapping if its PV entry could not be created.
4678 if (!pmap_pv_insert_pte1(pmap, va, VM_PAGE_TO_PHYS(m))) {
4679 CTR3(KTR_PMAP, "%s: failure for va %#lx in pmap %p",
4680 __func__, va, pmap);
4685 * Increment counters.
4687 pmap->pm_stats.resident_count += PTE1_SIZE / PAGE_SIZE;
4692 * QQQ: Why VM_PROT_WRITE is not evaluated and the mapping is
4695 pa = VM_PAGE_TO_PHYS(m);
4696 l1prot = PTE1_RO | PTE1_NM;
4697 if (va < VM_MAXUSER_ADDRESS)
4698 l1prot |= PTE1_U | PTE1_NG;
4699 if ((prot & VM_PROT_EXECUTE) == 0)
4701 else if (m->md.pat_mode == VM_MEMATTR_WB_WA && pmap != kernel_pmap) {
4703 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4704 * is set. QQQ: For more info, see comments in pmap_enter().
4706 cache_icache_sync_fresh(va, pa, PTE1_SIZE);
4708 pte1_store(pte1p, PTE1(pa, l1prot, ATTR_TO_L1(vm_page_pte2_attr(m))));
4710 pmap_pte1_mappings++;
4711 CTR3(KTR_PMAP, "%s: success for va %#lx in pmap %p", __func__, va,
4717 * Maps a sequence of resident pages belonging to the same object.
4718 * The sequence begins with the given page m_start. This page is
4719 * mapped at the given virtual address start. Each subsequent page is
4720 * mapped at a virtual address that is offset from start by the same
4721 * amount as the page is offset from m_start within the object. The
4722 * last page in the sequence is the page with the largest offset from
4723 * m_start that can be mapped at a virtual address less than the given
4724 * virtual address end. Not every virtual page between start and end
4725 * is mapped; only those for which a resident page exists with the
4726 * corresponding offset from m_start are mapped.
4729 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4730 vm_page_t m_start, vm_prot_t prot)
4733 vm_page_t m, mpt2pg;
4734 vm_pindex_t diff, psize;
4736 PDEBUG(6, printf("%s: pmap %p start %#x end %#x m %p prot %#x\n",
4737 __func__, pmap, start, end, m_start, prot));
4739 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4740 psize = atop(end - start);
4743 rw_wlock(&pvh_global_lock);
4745 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4746 va = start + ptoa(diff);
4747 if ((va & PTE1_OFFSET) == 0 && va + PTE1_SIZE <= end &&
4748 m->psind == 1 && sp_enabled &&
4749 pmap_enter_pte1(pmap, va, m, prot))
4750 m = &m[PTE1_SIZE / PAGE_SIZE - 1];
4752 mpt2pg = pmap_enter_quick_locked(pmap, va, m, prot,
4754 m = TAILQ_NEXT(m, listq);
4756 rw_wunlock(&pvh_global_lock);
4761 * This code maps large physical mmap regions into the
4762 * processor address space. Note that some shortcuts
4763 * are taken, but the code works.
4766 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4767 vm_pindex_t pindex, vm_size_t size)
4770 vm_paddr_t pa, pte2_pa;
4772 vm_memattr_t pat_mode;
4773 u_int l1attr, l1prot;
4775 VM_OBJECT_ASSERT_WLOCKED(object);
4776 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4777 ("%s: non-device object", __func__));
4778 if ((addr & PTE1_OFFSET) == 0 && (size & PTE1_OFFSET) == 0) {
4779 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4781 p = vm_page_lookup(object, pindex);
4782 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4783 ("%s: invalid page %p", __func__, p));
4784 pat_mode = p->md.pat_mode;
4787 * Abort the mapping if the first page is not physically
4788 * aligned to a 1MB page boundary.
4790 pte2_pa = VM_PAGE_TO_PHYS(p);
4791 if (pte2_pa & PTE1_OFFSET)
4795 * Skip the first page. Abort the mapping if the rest of
4796 * the pages are not physically contiguous or have differing
4797 * memory attributes.
4799 p = TAILQ_NEXT(p, listq);
4800 for (pa = pte2_pa + PAGE_SIZE; pa < pte2_pa + size;
4802 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4803 ("%s: invalid page %p", __func__, p));
4804 if (pa != VM_PAGE_TO_PHYS(p) ||
4805 pat_mode != p->md.pat_mode)
4807 p = TAILQ_NEXT(p, listq);
4811 * Map using 1MB pages.
4813 * QQQ: Well, we are mapping a section, so same condition must
4814 * be hold like during promotion. It looks that only RW mapping
4815 * is done here, so readonly mapping must be done elsewhere.
4817 l1prot = PTE1_U | PTE1_NG | PTE1_RW | PTE1_M | PTE1_A;
4818 l1attr = ATTR_TO_L1(vm_memattr_to_pte2(pat_mode));
4820 for (pa = pte2_pa; pa < pte2_pa + size; pa += PTE1_SIZE) {
4821 pte1p = pmap_pte1(pmap, addr);
4822 if (!pte1_is_valid(pte1_load(pte1p))) {
4823 pte1_store(pte1p, PTE1(pa, l1prot, l1attr));
4824 pmap->pm_stats.resident_count += PTE1_SIZE /
4826 pmap_pte1_mappings++;
4828 /* Else continue on if the PTE1 is already valid. */
4836 * Do the things to protect a 1mpage in a process.
4839 pmap_protect_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t sva,
4842 pt1_entry_t npte1, opte1;
4843 vm_offset_t eva, va;
4846 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4847 KASSERT((sva & PTE1_OFFSET) == 0,
4848 ("%s: sva is not 1mpage aligned", __func__));
4850 opte1 = npte1 = pte1_load(pte1p);
4851 if (pte1_is_managed(opte1) && pte1_is_dirty(opte1)) {
4852 eva = sva + PTE1_SIZE;
4853 for (va = sva, m = PHYS_TO_VM_PAGE(pte1_pa(opte1));
4854 va < eva; va += PAGE_SIZE, m++)
4857 if ((prot & VM_PROT_WRITE) == 0)
4858 npte1 |= PTE1_RO | PTE1_NM;
4859 if ((prot & VM_PROT_EXECUTE) == 0)
4863 * QQQ: Herein, execute permission is never set.
4864 * It only can be cleared. So, no icache
4865 * syncing is needed.
4868 if (npte1 != opte1) {
4869 pte1_store(pte1p, npte1);
4870 pmap_tlb_flush(pmap, sva);
4875 * Set the physical protection on the
4876 * specified range of this map as requested.
4879 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
4881 boolean_t pv_lists_locked;
4883 pt1_entry_t *pte1p, pte1;
4884 pt2_entry_t *pte2p, opte2, npte2;
4886 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
4887 if (prot == VM_PROT_NONE) {
4888 pmap_remove(pmap, sva, eva);
4892 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
4893 (VM_PROT_WRITE | VM_PROT_EXECUTE))
4896 if (pmap_is_current(pmap))
4897 pv_lists_locked = FALSE;
4899 pv_lists_locked = TRUE;
4901 rw_wlock(&pvh_global_lock);
4906 for (; sva < eva; sva = nextva) {
4908 * Calculate address for next L2 page table.
4910 nextva = pte1_trunc(sva + PTE1_SIZE);
4914 pte1p = pmap_pte1(pmap, sva);
4915 pte1 = pte1_load(pte1p);
4918 * Weed out invalid mappings. Note: we assume that L1 page
4919 * page table is always allocated, and in kernel virtual.
4924 if (pte1_is_section(pte1)) {
4926 * Are we protecting the entire large page? If not,
4927 * demote the mapping and fall through.
4929 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
4930 pmap_protect_pte1(pmap, pte1p, sva, prot);
4933 if (!pv_lists_locked) {
4934 pv_lists_locked = TRUE;
4935 if (!rw_try_wlock(&pvh_global_lock)) {
4941 if (!pmap_demote_pte1(pmap, pte1p, sva)) {
4943 * The large page mapping
4950 /* Update pte1 after demotion */
4951 pte1 = pte1_load(pte1p);
4957 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
4958 " is not link", __func__, pmap, sva, pte1, pte1p));
4961 * Limit our scan to either the end of the va represented
4962 * by the current L2 page table page, or to the end of the
4963 * range being protected.
4968 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva; pte2p++,
4972 opte2 = npte2 = pte2_load(pte2p);
4973 if (!pte2_is_valid(opte2))
4976 if ((prot & VM_PROT_WRITE) == 0) {
4977 if (pte2_is_managed(opte2) &&
4978 pte2_is_dirty(opte2)) {
4979 m = PHYS_TO_VM_PAGE(pte2_pa(opte2));
4982 npte2 |= PTE2_RO | PTE2_NM;
4985 if ((prot & VM_PROT_EXECUTE) == 0)
4989 * QQQ: Herein, execute permission is never set.
4990 * It only can be cleared. So, no icache
4991 * syncing is needed.
4994 if (npte2 != opte2) {
4995 pte2_store(pte2p, npte2);
4996 pmap_tlb_flush(pmap, sva);
5000 if (pv_lists_locked) {
5002 rw_wunlock(&pvh_global_lock);
5008 * pmap_pvh_wired_mappings:
5010 * Return the updated number "count" of managed mappings that are wired.
5013 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
5020 rw_assert(&pvh_global_lock, RA_WLOCKED);
5022 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5025 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5026 if (pte1_is_section(pte1)) {
5027 if (pte1_is_wired(pte1))
5030 KASSERT(pte1_is_link(pte1),
5031 ("%s: pte1 %#x is not link", __func__, pte1));
5032 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5033 if (pte2_is_wired(pte2))
5043 * pmap_page_wired_mappings:
5045 * Return the number of managed mappings to the given physical page
5049 pmap_page_wired_mappings(vm_page_t m)
5054 if ((m->oflags & VPO_UNMANAGED) != 0)
5056 rw_wlock(&pvh_global_lock);
5057 count = pmap_pvh_wired_mappings(&m->md, count);
5058 if ((m->flags & PG_FICTITIOUS) == 0) {
5059 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
5062 rw_wunlock(&pvh_global_lock);
5067 * Returns TRUE if any of the given mappings were used to modify
5068 * physical memory. Otherwise, returns FALSE. Both page and 1mpage
5069 * mappings are supported.
5072 pmap_is_modified_pvh(struct md_page *pvh)
5080 rw_assert(&pvh_global_lock, RA_WLOCKED);
5083 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5086 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5087 if (pte1_is_section(pte1)) {
5088 rv = pte1_is_dirty(pte1);
5090 KASSERT(pte1_is_link(pte1),
5091 ("%s: pte1 %#x is not link", __func__, pte1));
5092 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5093 rv = pte2_is_dirty(pte2);
5106 * Return whether or not the specified physical page was modified
5107 * in any physical maps.
5110 pmap_is_modified(vm_page_t m)
5114 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5115 ("%s: page %p is not managed", __func__, m));
5118 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5119 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
5120 * is clear, no PTE2s can have PG_M set.
5122 VM_OBJECT_ASSERT_WLOCKED(m->object);
5123 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5125 rw_wlock(&pvh_global_lock);
5126 rv = pmap_is_modified_pvh(&m->md) ||
5127 ((m->flags & PG_FICTITIOUS) == 0 &&
5128 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
5129 rw_wunlock(&pvh_global_lock);
5134 * pmap_is_prefaultable:
5136 * Return whether or not the specified virtual address is eligible
5140 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
5148 pte1 = pte1_load(pmap_pte1(pmap, addr));
5149 if (pte1_is_link(pte1)) {
5150 pte2 = pte2_load(pt2map_entry(addr));
5151 rv = !pte2_is_valid(pte2) ;
5158 * Returns TRUE if any of the given mappings were referenced and FALSE
5159 * otherwise. Both page and 1mpage mappings are supported.
5162 pmap_is_referenced_pvh(struct md_page *pvh)
5171 rw_assert(&pvh_global_lock, RA_WLOCKED);
5174 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5177 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5178 if (pte1_is_section(pte1)) {
5179 rv = (pte1 & (PTE1_A | PTE1_V)) == (PTE1_A | PTE1_V);
5181 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5182 rv = (pte2 & (PTE2_A | PTE2_V)) == (PTE2_A | PTE2_V);
5193 * pmap_is_referenced:
5195 * Return whether or not the specified physical page was referenced
5196 * in any physical maps.
5199 pmap_is_referenced(vm_page_t m)
5203 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5204 ("%s: page %p is not managed", __func__, m));
5205 rw_wlock(&pvh_global_lock);
5206 rv = pmap_is_referenced_pvh(&m->md) ||
5207 ((m->flags & PG_FICTITIOUS) == 0 &&
5208 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
5209 rw_wunlock(&pvh_global_lock);
5214 * pmap_ts_referenced:
5216 * Return a count of reference bits for a page, clearing those bits.
5217 * It is not necessary for every reference bit to be cleared, but it
5218 * is necessary that 0 only be returned when there are truly no
5219 * reference bits set.
5221 * As an optimization, update the page's dirty field if a modified bit is
5222 * found while counting reference bits. This opportunistic update can be
5223 * performed at low cost and can eliminate the need for some future calls
5224 * to pmap_is_modified(). However, since this function stops after
5225 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5226 * dirty pages. Those dirty pages will only be detected by a future call
5227 * to pmap_is_modified().
5230 pmap_ts_referenced(vm_page_t m)
5232 struct md_page *pvh;
5235 pt1_entry_t *pte1p, opte1;
5236 pt2_entry_t *pte2p, opte2;
5240 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5241 ("%s: page %p is not managed", __func__, m));
5242 pa = VM_PAGE_TO_PHYS(m);
5243 pvh = pa_to_pvh(pa);
5244 rw_wlock(&pvh_global_lock);
5246 if ((m->flags & PG_FICTITIOUS) != 0 ||
5247 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5248 goto small_mappings;
5253 pte1p = pmap_pte1(pmap, pv->pv_va);
5254 opte1 = pte1_load(pte1p);
5255 if (pte1_is_dirty(opte1)) {
5257 * Although "opte1" is mapping a 1MB page, because
5258 * this function is called at a 4KB page granularity,
5259 * we only update the 4KB page under test.
5263 if ((opte1 & PTE1_A) != 0) {
5265 * Since this reference bit is shared by 256 4KB pages,
5266 * it should not be cleared every time it is tested.
5267 * Apply a simple "hash" function on the physical page
5268 * number, the virtual section number, and the pmap
5269 * address to select one 4KB page out of the 256
5270 * on which testing the reference bit will result
5271 * in clearing that bit. This function is designed
5272 * to avoid the selection of the same 4KB page
5273 * for every 1MB page mapping.
5275 * On demotion, a mapping that hasn't been referenced
5276 * is simply destroyed. To avoid the possibility of a
5277 * subsequent page fault on a demoted wired mapping,
5278 * always leave its reference bit set. Moreover,
5279 * since the section is wired, the current state of
5280 * its reference bit won't affect page replacement.
5282 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PTE1_SHIFT) ^
5283 (uintptr_t)pmap) & (NPTE2_IN_PG - 1)) == 0 &&
5284 !pte1_is_wired(opte1)) {
5285 pte1_clear_bit(pte1p, PTE1_A);
5286 pmap_tlb_flush(pmap, pv->pv_va);
5291 /* Rotate the PV list if it has more than one entry. */
5292 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5293 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5294 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5296 if (rtval >= PMAP_TS_REFERENCED_MAX)
5298 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5300 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5306 pte1p = pmap_pte1(pmap, pv->pv_va);
5307 KASSERT(pte1_is_link(pte1_load(pte1p)),
5308 ("%s: not found a link in page %p's pv list", __func__, m));
5310 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5311 opte2 = pte2_load(pte2p);
5312 if (pte2_is_dirty(opte2))
5314 if ((opte2 & PTE2_A) != 0) {
5315 pte2_clear_bit(pte2p, PTE2_A);
5316 pmap_tlb_flush(pmap, pv->pv_va);
5320 /* Rotate the PV list if it has more than one entry. */
5321 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5322 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5323 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5325 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
5326 PMAP_TS_REFERENCED_MAX);
5329 rw_wunlock(&pvh_global_lock);
5334 * Clear the wired attribute from the mappings for the specified range of
5335 * addresses in the given pmap. Every valid mapping within that range
5336 * must have the wired attribute set. In contrast, invalid mappings
5337 * cannot have the wired attribute set, so they are ignored.
5339 * The wired attribute of the page table entry is not a hardware feature,
5340 * so there is no need to invalidate any TLB entries.
5343 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5346 pt1_entry_t *pte1p, pte1;
5347 pt2_entry_t *pte2p, pte2;
5348 boolean_t pv_lists_locked;
5350 if (pmap_is_current(pmap))
5351 pv_lists_locked = FALSE;
5353 pv_lists_locked = TRUE;
5355 rw_wlock(&pvh_global_lock);
5359 for (; sva < eva; sva = nextva) {
5360 nextva = pte1_trunc(sva + PTE1_SIZE);
5364 pte1p = pmap_pte1(pmap, sva);
5365 pte1 = pte1_load(pte1p);
5368 * Weed out invalid mappings. Note: we assume that L1 page
5369 * page table is always allocated, and in kernel virtual.
5374 if (pte1_is_section(pte1)) {
5375 if (!pte1_is_wired(pte1))
5376 panic("%s: pte1 %#x not wired", __func__, pte1);
5379 * Are we unwiring the entire large page? If not,
5380 * demote the mapping and fall through.
5382 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
5383 pte1_clear_bit(pte1p, PTE1_W);
5384 pmap->pm_stats.wired_count -= PTE1_SIZE /
5388 if (!pv_lists_locked) {
5389 pv_lists_locked = TRUE;
5390 if (!rw_try_wlock(&pvh_global_lock)) {
5397 if (!pmap_demote_pte1(pmap, pte1p, sva))
5398 panic("%s: demotion failed", __func__);
5401 /* Update pte1 after demotion */
5402 pte1 = pte1_load(pte1p);
5408 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
5409 " is not link", __func__, pmap, sva, pte1, pte1p));
5412 * Limit our scan to either the end of the va represented
5413 * by the current L2 page table page, or to the end of the
5414 * range being protected.
5419 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva; pte2p++,
5421 pte2 = pte2_load(pte2p);
5422 if (!pte2_is_valid(pte2))
5424 if (!pte2_is_wired(pte2))
5425 panic("%s: pte2 %#x is missing PTE2_W",
5429 * PTE2_W must be cleared atomically. Although the pmap
5430 * lock synchronizes access to PTE2_W, another processor
5431 * could be changing PTE2_NM and/or PTE2_A concurrently.
5433 pte2_clear_bit(pte2p, PTE2_W);
5434 pmap->pm_stats.wired_count--;
5437 if (pv_lists_locked) {
5439 rw_wunlock(&pvh_global_lock);
5445 * Clear the write and modified bits in each of the given page's mappings.
5448 pmap_remove_write(vm_page_t m)
5450 struct md_page *pvh;
5451 pv_entry_t next_pv, pv;
5454 pt2_entry_t *pte2p, opte2;
5457 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5458 ("%s: page %p is not managed", __func__, m));
5461 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5462 * set by another thread while the object is locked. Thus,
5463 * if PGA_WRITEABLE is clear, no page table entries need updating.
5465 VM_OBJECT_ASSERT_WLOCKED(m->object);
5466 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5468 rw_wlock(&pvh_global_lock);
5470 if ((m->flags & PG_FICTITIOUS) != 0)
5471 goto small_mappings;
5472 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5473 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5477 pte1p = pmap_pte1(pmap, va);
5478 if (!(pte1_load(pte1p) & PTE1_RO))
5479 (void)pmap_demote_pte1(pmap, pte1p, va);
5483 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5486 pte1p = pmap_pte1(pmap, pv->pv_va);
5487 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found"
5488 " a section in page %p's pv list", __func__, m));
5489 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5490 opte2 = pte2_load(pte2p);
5491 if (!(opte2 & PTE2_RO)) {
5492 pte2_store(pte2p, opte2 | PTE2_RO | PTE2_NM);
5493 if (pte2_is_dirty(opte2))
5495 pmap_tlb_flush(pmap, pv->pv_va);
5499 vm_page_aflag_clear(m, PGA_WRITEABLE);
5501 rw_wunlock(&pvh_global_lock);
5505 * Apply the given advice to the specified range of addresses within the
5506 * given pmap. Depending on the advice, clear the referenced and/or
5507 * modified flags in each mapping and set the mapped page's dirty field.
5510 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5512 pt1_entry_t *pte1p, opte1;
5513 pt2_entry_t *pte2p, pte2;
5516 boolean_t pv_lists_locked;
5518 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5520 if (pmap_is_current(pmap))
5521 pv_lists_locked = FALSE;
5523 pv_lists_locked = TRUE;
5525 rw_wlock(&pvh_global_lock);
5529 for (; sva < eva; sva = pdnxt) {
5530 pdnxt = pte1_trunc(sva + PTE1_SIZE);
5533 pte1p = pmap_pte1(pmap, sva);
5534 opte1 = pte1_load(pte1p);
5535 if (!pte1_is_valid(opte1)) /* XXX */
5537 else if (pte1_is_section(opte1)) {
5538 if (!pte1_is_managed(opte1))
5540 if (!pv_lists_locked) {
5541 pv_lists_locked = TRUE;
5542 if (!rw_try_wlock(&pvh_global_lock)) {
5548 if (!pmap_demote_pte1(pmap, pte1p, sva)) {
5550 * The large page mapping was destroyed.
5556 * Unless the page mappings are wired, remove the
5557 * mapping to a single page so that a subsequent
5558 * access may repromote. Since the underlying L2 page
5559 * table is fully populated, this removal never
5560 * frees a L2 page table page.
5562 if (!pte1_is_wired(opte1)) {
5563 pte2p = pmap_pte2_quick(pmap, sva);
5564 KASSERT(pte2_is_valid(pte2_load(pte2p)),
5565 ("%s: invalid PTE2", __func__));
5566 pmap_remove_pte2(pmap, pte2p, sva, NULL);
5571 for (pte2p = pmap_pte2_quick(pmap, sva); sva != pdnxt; pte2p++,
5573 pte2 = pte2_load(pte2p);
5574 if (!pte2_is_valid(pte2) || !pte2_is_managed(pte2))
5576 else if (pte2_is_dirty(pte2)) {
5577 if (advice == MADV_DONTNEED) {
5579 * Future calls to pmap_is_modified()
5580 * can be avoided by making the page
5583 m = PHYS_TO_VM_PAGE(pte2_pa(pte2));
5586 pte2_set_bit(pte2p, PTE2_NM);
5587 pte2_clear_bit(pte2p, PTE2_A);
5588 } else if ((pte2 & PTE2_A) != 0)
5589 pte2_clear_bit(pte2p, PTE2_A);
5592 pmap_tlb_flush(pmap, sva);
5595 if (pv_lists_locked) {
5597 rw_wunlock(&pvh_global_lock);
5603 * Clear the modify bits on the specified physical page.
5606 pmap_clear_modify(vm_page_t m)
5608 struct md_page *pvh;
5609 pv_entry_t next_pv, pv;
5611 pt1_entry_t *pte1p, opte1;
5612 pt2_entry_t *pte2p, opte2;
5615 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5616 ("%s: page %p is not managed", __func__, m));
5617 VM_OBJECT_ASSERT_WLOCKED(m->object);
5618 KASSERT(!vm_page_xbusied(m),
5619 ("%s: page %p is exclusive busy", __func__, m));
5622 * If the page is not PGA_WRITEABLE, then no PTE2s can have PTE2_NM
5623 * cleared. If the object containing the page is locked and the page
5624 * is not exclusive busied, then PGA_WRITEABLE cannot be concurrently
5627 if ((m->flags & PGA_WRITEABLE) == 0)
5629 rw_wlock(&pvh_global_lock);
5631 if ((m->flags & PG_FICTITIOUS) != 0)
5632 goto small_mappings;
5633 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5634 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5638 pte1p = pmap_pte1(pmap, va);
5639 opte1 = pte1_load(pte1p);
5640 if (!(opte1 & PTE1_RO)) {
5641 if (pmap_demote_pte1(pmap, pte1p, va) &&
5642 !pte1_is_wired(opte1)) {
5644 * Write protect the mapping to a
5645 * single page so that a subsequent
5646 * write access may repromote.
5648 va += VM_PAGE_TO_PHYS(m) - pte1_pa(opte1);
5649 pte2p = pmap_pte2_quick(pmap, va);
5650 opte2 = pte2_load(pte2p);
5651 if ((opte2 & PTE2_V)) {
5652 pte2_set_bit(pte2p, PTE2_NM | PTE2_RO);
5654 pmap_tlb_flush(pmap, va);
5661 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5664 pte1p = pmap_pte1(pmap, pv->pv_va);
5665 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found"
5666 " a section in page %p's pv list", __func__, m));
5667 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5668 if (pte2_is_dirty(pte2_load(pte2p))) {
5669 pte2_set_bit(pte2p, PTE2_NM);
5670 pmap_tlb_flush(pmap, pv->pv_va);
5675 rw_wunlock(&pvh_global_lock);
5680 * Sets the memory attribute for the specified page.
5683 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5685 pt2_entry_t *cmap2_pte2p;
5690 oma = m->md.pat_mode;
5691 m->md.pat_mode = ma;
5693 CTR5(KTR_PMAP, "%s: page %p - 0x%08X oma: %d, ma: %d", __func__, m,
5694 VM_PAGE_TO_PHYS(m), oma, ma);
5695 if ((m->flags & PG_FICTITIOUS) != 0)
5699 * If "m" is a normal page, flush it from the cache.
5701 * First, try to find an existing mapping of the page by sf
5702 * buffer. sf_buf_invalidate_cache() modifies mapping and
5703 * flushes the cache.
5705 if (sf_buf_invalidate_cache(m, oma))
5709 * If page is not mapped by sf buffer, map the page
5710 * transient and do invalidation.
5713 pa = VM_PAGE_TO_PHYS(m);
5716 cmap2_pte2p = pc->pc_cmap2_pte2p;
5717 mtx_lock(&pc->pc_cmap_lock);
5718 if (pte2_load(cmap2_pte2p) != 0)
5719 panic("%s: CMAP2 busy", __func__);
5720 pte2_store(cmap2_pte2p, PTE2_KERN_NG(pa, PTE2_AP_KRW,
5721 vm_memattr_to_pte2(ma)));
5722 dcache_wbinv_poc((vm_offset_t)pc->pc_cmap2_addr, pa, PAGE_SIZE);
5723 pte2_clear(cmap2_pte2p);
5724 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5726 mtx_unlock(&pc->pc_cmap_lock);
5731 * Miscellaneous support routines follow
5735 * Returns TRUE if the given page is mapped individually or as part of
5736 * a 1mpage. Otherwise, returns FALSE.
5739 pmap_page_is_mapped(vm_page_t m)
5743 if ((m->oflags & VPO_UNMANAGED) != 0)
5745 rw_wlock(&pvh_global_lock);
5746 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5747 ((m->flags & PG_FICTITIOUS) == 0 &&
5748 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
5749 rw_wunlock(&pvh_global_lock);
5754 * Returns true if the pmap's pv is one of the first
5755 * 16 pvs linked to from this page. This count may
5756 * be changed upwards or downwards in the future; it
5757 * is only necessary that true be returned for a small
5758 * subset of pmaps for proper page aging.
5761 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5763 struct md_page *pvh;
5768 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5769 ("%s: page %p is not managed", __func__, m));
5771 rw_wlock(&pvh_global_lock);
5772 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5773 if (PV_PMAP(pv) == pmap) {
5781 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5782 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5783 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5784 if (PV_PMAP(pv) == pmap) {
5793 rw_wunlock(&pvh_global_lock);
5798 * pmap_zero_page zeros the specified hardware page by mapping
5799 * the page into KVM and using bzero to clear its contents.
5802 pmap_zero_page(vm_page_t m)
5804 pt2_entry_t *cmap2_pte2p;
5809 cmap2_pte2p = pc->pc_cmap2_pte2p;
5810 mtx_lock(&pc->pc_cmap_lock);
5811 if (pte2_load(cmap2_pte2p) != 0)
5812 panic("%s: CMAP2 busy", __func__);
5813 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5814 vm_page_pte2_attr(m)));
5815 pagezero(pc->pc_cmap2_addr);
5816 pte2_clear(cmap2_pte2p);
5817 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5819 mtx_unlock(&pc->pc_cmap_lock);
5823 * pmap_zero_page_area zeros the specified hardware page by mapping
5824 * the page into KVM and using bzero to clear its contents.
5826 * off and size may not cover an area beyond a single hardware page.
5829 pmap_zero_page_area(vm_page_t m, int off, int size)
5831 pt2_entry_t *cmap2_pte2p;
5836 cmap2_pte2p = pc->pc_cmap2_pte2p;
5837 mtx_lock(&pc->pc_cmap_lock);
5838 if (pte2_load(cmap2_pte2p) != 0)
5839 panic("%s: CMAP2 busy", __func__);
5840 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5841 vm_page_pte2_attr(m)));
5842 if (off == 0 && size == PAGE_SIZE)
5843 pagezero(pc->pc_cmap2_addr);
5845 bzero(pc->pc_cmap2_addr + off, size);
5846 pte2_clear(cmap2_pte2p);
5847 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5849 mtx_unlock(&pc->pc_cmap_lock);
5853 * pmap_copy_page copies the specified (machine independent)
5854 * page by mapping the page into virtual memory and using
5855 * bcopy to copy the page, one machine dependent page at a
5859 pmap_copy_page(vm_page_t src, vm_page_t dst)
5861 pt2_entry_t *cmap1_pte2p, *cmap2_pte2p;
5866 cmap1_pte2p = pc->pc_cmap1_pte2p;
5867 cmap2_pte2p = pc->pc_cmap2_pte2p;
5868 mtx_lock(&pc->pc_cmap_lock);
5869 if (pte2_load(cmap1_pte2p) != 0)
5870 panic("%s: CMAP1 busy", __func__);
5871 if (pte2_load(cmap2_pte2p) != 0)
5872 panic("%s: CMAP2 busy", __func__);
5873 pte2_store(cmap1_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(src),
5874 PTE2_AP_KR | PTE2_NM, vm_page_pte2_attr(src)));
5875 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(dst),
5876 PTE2_AP_KRW, vm_page_pte2_attr(dst)));
5877 bcopy(pc->pc_cmap1_addr, pc->pc_cmap2_addr, PAGE_SIZE);
5878 pte2_clear(cmap1_pte2p);
5879 tlb_flush((vm_offset_t)pc->pc_cmap1_addr);
5880 pte2_clear(cmap2_pte2p);
5881 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5883 mtx_unlock(&pc->pc_cmap_lock);
5886 int unmapped_buf_allowed = 1;
5889 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5890 vm_offset_t b_offset, int xfersize)
5892 pt2_entry_t *cmap1_pte2p, *cmap2_pte2p;
5893 vm_page_t a_pg, b_pg;
5895 vm_offset_t a_pg_offset, b_pg_offset;
5901 cmap1_pte2p = pc->pc_cmap1_pte2p;
5902 cmap2_pte2p = pc->pc_cmap2_pte2p;
5903 mtx_lock(&pc->pc_cmap_lock);
5904 if (pte2_load(cmap1_pte2p) != 0)
5905 panic("pmap_copy_pages: CMAP1 busy");
5906 if (pte2_load(cmap2_pte2p) != 0)
5907 panic("pmap_copy_pages: CMAP2 busy");
5908 while (xfersize > 0) {
5909 a_pg = ma[a_offset >> PAGE_SHIFT];
5910 a_pg_offset = a_offset & PAGE_MASK;
5911 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5912 b_pg = mb[b_offset >> PAGE_SHIFT];
5913 b_pg_offset = b_offset & PAGE_MASK;
5914 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5915 pte2_store(cmap1_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(a_pg),
5916 PTE2_AP_KR | PTE2_NM, vm_page_pte2_attr(a_pg)));
5917 tlb_flush_local((vm_offset_t)pc->pc_cmap1_addr);
5918 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(b_pg),
5919 PTE2_AP_KRW, vm_page_pte2_attr(b_pg)));
5920 tlb_flush_local((vm_offset_t)pc->pc_cmap2_addr);
5921 a_cp = pc->pc_cmap1_addr + a_pg_offset;
5922 b_cp = pc->pc_cmap2_addr + b_pg_offset;
5923 bcopy(a_cp, b_cp, cnt);
5928 pte2_clear(cmap1_pte2p);
5929 tlb_flush((vm_offset_t)pc->pc_cmap1_addr);
5930 pte2_clear(cmap2_pte2p);
5931 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5933 mtx_unlock(&pc->pc_cmap_lock);
5937 pmap_quick_enter_page(vm_page_t m)
5944 pte2p = pc->pc_qmap_pte2p;
5946 KASSERT(pte2_load(pte2p) == 0, ("%s: PTE2 busy", __func__));
5948 pte2_store(pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5949 vm_page_pte2_attr(m)));
5950 return (pc->pc_qmap_addr);
5954 pmap_quick_remove_page(vm_offset_t addr)
5960 pte2p = pc->pc_qmap_pte2p;
5962 KASSERT(addr == pc->pc_qmap_addr, ("%s: invalid address", __func__));
5963 KASSERT(pte2_load(pte2p) != 0, ("%s: PTE2 not in use", __func__));
5966 tlb_flush(pc->pc_qmap_addr);
5971 * Copy the range specified by src_addr/len
5972 * from the source map to the range dst_addr/len
5973 * in the destination map.
5975 * This routine is only advisory and need not do anything.
5978 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
5979 vm_offset_t src_addr)
5981 struct spglist free;
5983 vm_offset_t end_addr = src_addr + len;
5986 if (dst_addr != src_addr)
5989 if (!pmap_is_current(src_pmap))
5992 rw_wlock(&pvh_global_lock);
5993 if (dst_pmap < src_pmap) {
5994 PMAP_LOCK(dst_pmap);
5995 PMAP_LOCK(src_pmap);
5997 PMAP_LOCK(src_pmap);
5998 PMAP_LOCK(dst_pmap);
6001 for (addr = src_addr; addr < end_addr; addr = nextva) {
6002 pt2_entry_t *src_pte2p, *dst_pte2p;
6003 vm_page_t dst_mpt2pg, src_mpt2pg;
6004 pt1_entry_t src_pte1;
6007 KASSERT(addr < VM_MAXUSER_ADDRESS,
6008 ("%s: invalid to pmap_copy page tables", __func__));
6010 nextva = pte1_trunc(addr + PTE1_SIZE);
6014 pte1_idx = pte1_index(addr);
6015 src_pte1 = src_pmap->pm_pt1[pte1_idx];
6016 if (pte1_is_section(src_pte1)) {
6017 if ((addr & PTE1_OFFSET) != 0 ||
6018 (addr + PTE1_SIZE) > end_addr)
6020 if (dst_pmap->pm_pt1[pte1_idx] == 0 &&
6021 (!pte1_is_managed(src_pte1) ||
6022 pmap_pv_insert_pte1(dst_pmap, addr,
6023 pte1_pa(src_pte1)))) {
6024 dst_pmap->pm_pt1[pte1_idx] = src_pte1 &
6026 dst_pmap->pm_stats.resident_count +=
6027 PTE1_SIZE / PAGE_SIZE;
6028 pmap_pte1_mappings++;
6031 } else if (!pte1_is_link(src_pte1))
6034 src_mpt2pg = PHYS_TO_VM_PAGE(pte1_link_pa(src_pte1));
6037 * We leave PT2s to be linked from PT1 even if they are not
6038 * referenced until all PT2s in a page are without reference.
6040 * QQQ: It could be changed ...
6042 #if 0 /* single_pt2_link_is_cleared */
6043 KASSERT(pt2_wirecount_get(src_mpt2pg, pte1_idx) > 0,
6044 ("%s: source page table page is unused", __func__));
6046 if (pt2_wirecount_get(src_mpt2pg, pte1_idx) == 0)
6049 if (nextva > end_addr)
6052 src_pte2p = pt2map_entry(addr);
6053 while (addr < nextva) {
6054 pt2_entry_t temp_pte2;
6055 temp_pte2 = pte2_load(src_pte2p);
6057 * we only virtual copy managed pages
6059 if (pte2_is_managed(temp_pte2)) {
6060 dst_mpt2pg = pmap_allocpte2(dst_pmap, addr,
6061 PMAP_ENTER_NOSLEEP);
6062 if (dst_mpt2pg == NULL)
6064 dst_pte2p = pmap_pte2_quick(dst_pmap, addr);
6065 if (!pte2_is_valid(pte2_load(dst_pte2p)) &&
6066 pmap_try_insert_pv_entry(dst_pmap, addr,
6067 PHYS_TO_VM_PAGE(pte2_pa(temp_pte2)))) {
6069 * Clear the wired, modified, and
6070 * accessed (referenced) bits
6073 temp_pte2 &= ~(PTE2_W | PTE2_A);
6074 temp_pte2 |= PTE2_NM;
6075 pte2_store(dst_pte2p, temp_pte2);
6076 dst_pmap->pm_stats.resident_count++;
6079 if (pmap_unwire_pt2(dst_pmap, addr,
6080 dst_mpt2pg, &free)) {
6081 pmap_tlb_flush(dst_pmap, addr);
6082 pmap_free_zero_pages(&free);
6086 if (pt2_wirecount_get(dst_mpt2pg, pte1_idx) >=
6087 pt2_wirecount_get(src_mpt2pg, pte1_idx))
6096 rw_wunlock(&pvh_global_lock);
6097 PMAP_UNLOCK(src_pmap);
6098 PMAP_UNLOCK(dst_pmap);
6102 * Increase the starting virtual address of the given mapping if a
6103 * different alignment might result in more section mappings.
6106 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6107 vm_offset_t *addr, vm_size_t size)
6109 vm_offset_t pte1_offset;
6111 if (size < PTE1_SIZE)
6113 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6114 offset += ptoa(object->pg_color);
6115 pte1_offset = offset & PTE1_OFFSET;
6116 if (size - ((PTE1_SIZE - pte1_offset) & PTE1_OFFSET) < PTE1_SIZE ||
6117 (*addr & PTE1_OFFSET) == pte1_offset)
6119 if ((*addr & PTE1_OFFSET) < pte1_offset)
6120 *addr = pte1_trunc(*addr) + pte1_offset;
6122 *addr = pte1_roundup(*addr) + pte1_offset;
6126 pmap_activate(struct thread *td)
6128 pmap_t pmap, oldpmap;
6131 PDEBUG(9, printf("%s: td = %08x\n", __func__, (uint32_t)td));
6134 pmap = vmspace_pmap(td->td_proc->p_vmspace);
6135 oldpmap = PCPU_GET(curpmap);
6136 cpuid = PCPU_GET(cpuid);
6139 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
6140 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
6142 CPU_CLR(cpuid, &oldpmap->pm_active);
6143 CPU_SET(cpuid, &pmap->pm_active);
6146 ttb = pmap_ttb_get(pmap);
6149 * pmap_activate is for the current thread on the current cpu
6151 td->td_pcb->pcb_pagedir = ttb;
6153 PCPU_SET(curpmap, pmap);
6158 * Perform the pmap work for mincore.
6161 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
6163 pt1_entry_t *pte1p, pte1;
6164 pt2_entry_t *pte2p, pte2;
6171 pte1p = pmap_pte1(pmap, addr);
6172 pte1 = pte1_load(pte1p);
6173 if (pte1_is_section(pte1)) {
6174 pa = trunc_page(pte1_pa(pte1) | (addr & PTE1_OFFSET));
6175 managed = pte1_is_managed(pte1);
6176 val = MINCORE_SUPER | MINCORE_INCORE;
6177 if (pte1_is_dirty(pte1))
6178 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6180 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6181 } else if (pte1_is_link(pte1)) {
6182 pte2p = pmap_pte2(pmap, addr);
6183 pte2 = pte2_load(pte2p);
6184 pmap_pte2_release(pte2p);
6186 managed = pte2_is_managed(pte2);
6187 val = MINCORE_INCORE;
6188 if (pte2_is_dirty(pte2))
6189 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6191 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6196 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
6197 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
6198 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
6199 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
6202 PA_UNLOCK_COND(*locked_pa);
6208 pmap_kenter_device(vm_offset_t va, vm_size_t size, vm_paddr_t pa)
6213 KASSERT((size & PAGE_MASK) == 0,
6214 ("%s: device mapping not page-sized", __func__));
6217 l2attr = vm_memattr_to_pte2(VM_MEMATTR_DEVICE);
6219 pmap_kenter_prot_attr(va, pa, PTE2_AP_KRW, l2attr);
6224 tlb_flush_range(sva, va - sva);
6228 pmap_kremove_device(vm_offset_t va, vm_size_t size)
6232 KASSERT((size & PAGE_MASK) == 0,
6233 ("%s: device mapping not page-sized", __func__));
6241 tlb_flush_range(sva, va - sva);
6245 pmap_set_pcb_pagedir(pmap_t pmap, struct pcb *pcb)
6248 pcb->pcb_pagedir = pmap_ttb_get(pmap);
6253 * Clean L1 data cache range by physical address.
6254 * The range must be within a single page.
6257 pmap_dcache_wb_pou(vm_paddr_t pa, vm_size_t size, uint32_t attr)
6259 pt2_entry_t *cmap2_pte2p;
6262 KASSERT(((pa & PAGE_MASK) + size) <= PAGE_SIZE,
6263 ("%s: not on single page", __func__));
6267 cmap2_pte2p = pc->pc_cmap2_pte2p;
6268 mtx_lock(&pc->pc_cmap_lock);
6269 if (pte2_load(cmap2_pte2p) != 0)
6270 panic("%s: CMAP2 busy", __func__);
6271 pte2_store(cmap2_pte2p, PTE2_KERN_NG(pa, PTE2_AP_KRW, attr));
6272 dcache_wb_pou((vm_offset_t)pc->pc_cmap2_addr + (pa & PAGE_MASK), size);
6273 pte2_clear(cmap2_pte2p);
6274 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
6276 mtx_unlock(&pc->pc_cmap_lock);
6280 * Sync instruction cache range which is not mapped yet.
6283 cache_icache_sync_fresh(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
6285 uint32_t len, offset;
6288 /* Write back d-cache on given address range. */
6289 offset = pa & PAGE_MASK;
6290 for ( ; size != 0; size -= len, pa += len, offset = 0) {
6291 len = min(PAGE_SIZE - offset, size);
6292 m = PHYS_TO_VM_PAGE(pa);
6293 KASSERT(m != NULL, ("%s: vm_page_t is null for %#x",
6295 pmap_dcache_wb_pou(pa, len, vm_page_pte2_attr(m));
6298 * I-cache is VIPT. Only way how to flush all virtual mappings
6299 * on given physical address is to invalidate all i-cache.
6305 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t size)
6308 /* Write back d-cache on given address range. */
6309 if (va >= VM_MIN_KERNEL_ADDRESS) {
6310 dcache_wb_pou(va, size);
6312 uint32_t len, offset;
6316 offset = va & PAGE_MASK;
6317 for ( ; size != 0; size -= len, va += len, offset = 0) {
6318 pa = pmap_extract(pmap, va); /* offset is preserved */
6319 len = min(PAGE_SIZE - offset, size);
6320 m = PHYS_TO_VM_PAGE(pa);
6321 KASSERT(m != NULL, ("%s: vm_page_t is null for %#x",
6323 pmap_dcache_wb_pou(pa, len, vm_page_pte2_attr(m));
6327 * I-cache is VIPT. Only way how to flush all virtual mappings
6328 * on given physical address is to invalidate all i-cache.
6334 * The implementation of pmap_fault() uses IN_RANGE2() macro which
6335 * depends on the fact that given range size is a power of 2.
6337 CTASSERT(powerof2(NB_IN_PT1));
6338 CTASSERT(powerof2(PT2MAP_SIZE));
6340 #define IN_RANGE2(addr, start, size) \
6341 ((vm_offset_t)(start) == ((vm_offset_t)(addr) & ~((size) - 1)))
6344 * Handle access and R/W emulation faults.
6347 pmap_fault(pmap_t pmap, vm_offset_t far, uint32_t fsr, int idx, bool usermode)
6349 pt1_entry_t *pte1p, pte1;
6350 pt2_entry_t *pte2p, pte2;
6356 * In kernel, we should never get abort with FAR which is in range of
6357 * pmap->pm_pt1 or PT2MAP address spaces. If it happens, stop here
6358 * and print out a useful abort message and even get to the debugger
6359 * otherwise it likely ends with never ending loop of aborts.
6361 if (__predict_false(IN_RANGE2(far, pmap->pm_pt1, NB_IN_PT1))) {
6363 * All L1 tables should always be mapped and present.
6364 * However, we check only current one herein. For user mode,
6365 * only permission abort from malicious user is not fatal.
6366 * And alignment abort as it may have higher priority.
6368 if (!usermode || (idx != FAULT_ALIGN && idx != FAULT_PERM_L2)) {
6369 CTR4(KTR_PMAP, "%s: pmap %#x pm_pt1 %#x far %#x",
6370 __func__, pmap, pmap->pm_pt1, far);
6371 panic("%s: pm_pt1 abort", __func__);
6373 return (KERN_INVALID_ADDRESS);
6375 if (__predict_false(IN_RANGE2(far, PT2MAP, PT2MAP_SIZE))) {
6377 * PT2MAP should be always mapped and present in current
6378 * L1 table. However, only existing L2 tables are mapped
6379 * in PT2MAP. For user mode, only L2 translation abort and
6380 * permission abort from malicious user is not fatal.
6381 * And alignment abort as it may have higher priority.
6383 if (!usermode || (idx != FAULT_ALIGN &&
6384 idx != FAULT_TRAN_L2 && idx != FAULT_PERM_L2)) {
6385 CTR4(KTR_PMAP, "%s: pmap %#x PT2MAP %#x far %#x",
6386 __func__, pmap, PT2MAP, far);
6387 panic("%s: PT2MAP abort", __func__);
6389 return (KERN_INVALID_ADDRESS);
6393 * A pmap lock is used below for handling of access and R/W emulation
6394 * aborts. They were handled by atomic operations before so some
6395 * analysis of new situation is needed to answer the following question:
6396 * Is it safe to use the lock even for these aborts?
6398 * There may happen two cases in general:
6400 * (1) Aborts while the pmap lock is locked already - this should not
6401 * happen as pmap lock is not recursive. However, under pmap lock only
6402 * internal kernel data should be accessed and such data should be
6403 * mapped with A bit set and NM bit cleared. If double abort happens,
6404 * then a mapping of data which has caused it must be fixed. Further,
6405 * all new mappings are always made with A bit set and the bit can be
6406 * cleared only on managed mappings.
6408 * (2) Aborts while another lock(s) is/are locked - this already can
6409 * happen. However, there is no difference here if it's either access or
6410 * R/W emulation abort, or if it's some other abort.
6415 pte1 = pte1_load(pmap_pte1(pmap, far));
6416 if (pte1_is_link(pte1)) {
6418 * Check in advance that associated L2 page table is mapped into
6419 * PT2MAP space. Note that faulty access to not mapped L2 page
6420 * table is caught in more general check above where "far" is
6421 * checked that it does not lay in PT2MAP space. Note also that
6422 * L1 page table and PT2TAB always exist and are mapped.
6424 pte2 = pt2tab_load(pmap_pt2tab_entry(pmap, far));
6425 if (!pte2_is_valid(pte2))
6426 panic("%s: missing L2 page table (%p, %#x)",
6427 __func__, pmap, far);
6432 * Special treatment is due to break-before-make approach done when
6433 * pte1 is updated for userland mapping during section promotion or
6434 * demotion. If not caught here, pmap_enter() can find a section
6435 * mapping on faulting address. That is not allowed.
6437 if (idx == FAULT_TRAN_L1 && usermode && cp15_ats1cur_check(far) == 0) {
6439 return (KERN_SUCCESS);
6443 * Accesss bits for page and section. Note that the entry
6444 * is not in TLB yet, so TLB flush is not necessary.
6446 * QQQ: This is hardware emulation, we do not call userret()
6447 * for aborts from user mode.
6449 if (idx == FAULT_ACCESS_L2) {
6450 pte1 = pte1_load(pmap_pte1(pmap, far));
6451 if (pte1_is_link(pte1)) {
6452 /* L2 page table should exist and be mapped. */
6453 pte2p = pt2map_entry(far);
6454 pte2 = pte2_load(pte2p);
6455 if (pte2_is_valid(pte2)) {
6456 pte2_store(pte2p, pte2 | PTE2_A);
6458 return (KERN_SUCCESS);
6462 * We got L2 access fault but PTE1 is not a link.
6463 * Probably some race happened, do nothing.
6465 CTR3(KTR_PMAP, "%s: FAULT_ACCESS_L2 - pmap %#x far %#x",
6466 __func__, pmap, far);
6468 return (KERN_SUCCESS);
6471 if (idx == FAULT_ACCESS_L1) {
6472 pte1p = pmap_pte1(pmap, far);
6473 pte1 = pte1_load(pte1p);
6474 if (pte1_is_section(pte1)) {
6475 pte1_store(pte1p, pte1 | PTE1_A);
6477 return (KERN_SUCCESS);
6480 * We got L1 access fault but PTE1 is not section
6481 * mapping. Probably some race happened, do nothing.
6483 CTR3(KTR_PMAP, "%s: FAULT_ACCESS_L1 - pmap %#x far %#x",
6484 __func__, pmap, far);
6486 return (KERN_SUCCESS);
6491 * Handle modify bits for page and section. Note that the modify
6492 * bit is emulated by software. So PTEx_RO is software read only
6493 * bit and PTEx_NM flag is real hardware read only bit.
6495 * QQQ: This is hardware emulation, we do not call userret()
6496 * for aborts from user mode.
6498 if ((fsr & FSR_WNR) && (idx == FAULT_PERM_L2)) {
6499 pte1 = pte1_load(pmap_pte1(pmap, far));
6500 if (pte1_is_link(pte1)) {
6501 /* L2 page table should exist and be mapped. */
6502 pte2p = pt2map_entry(far);
6503 pte2 = pte2_load(pte2p);
6504 if (pte2_is_valid(pte2) && !(pte2 & PTE2_RO) &&
6506 pte2_store(pte2p, pte2 & ~PTE2_NM);
6507 tlb_flush(trunc_page(far));
6509 return (KERN_SUCCESS);
6513 * We got L2 permission fault but PTE1 is not a link.
6514 * Probably some race happened, do nothing.
6516 CTR3(KTR_PMAP, "%s: FAULT_PERM_L2 - pmap %#x far %#x",
6517 __func__, pmap, far);
6519 return (KERN_SUCCESS);
6522 if ((fsr & FSR_WNR) && (idx == FAULT_PERM_L1)) {
6523 pte1p = pmap_pte1(pmap, far);
6524 pte1 = pte1_load(pte1p);
6525 if (pte1_is_section(pte1)) {
6526 if (!(pte1 & PTE1_RO) && (pte1 & PTE1_NM)) {
6527 pte1_store(pte1p, pte1 & ~PTE1_NM);
6528 tlb_flush(pte1_trunc(far));
6530 return (KERN_SUCCESS);
6534 * We got L1 permission fault but PTE1 is not section
6535 * mapping. Probably some race happened, do nothing.
6537 CTR3(KTR_PMAP, "%s: FAULT_PERM_L1 - pmap %#x far %#x",
6538 __func__, pmap, far);
6540 return (KERN_SUCCESS);
6545 * QQQ: The previous code, mainly fast handling of access and
6546 * modify bits aborts, could be moved to ASM. Now we are
6547 * starting to deal with not fast aborts.
6550 return (KERN_FAILURE);
6553 #if defined(PMAP_DEBUG)
6555 * Reusing of KVA used in pmap_zero_page function !!!
6558 pmap_zero_page_check(vm_page_t m)
6560 pt2_entry_t *cmap2_pte2p;
6566 cmap2_pte2p = pc->pc_cmap2_pte2p;
6567 mtx_lock(&pc->pc_cmap_lock);
6568 if (pte2_load(cmap2_pte2p) != 0)
6569 panic("%s: CMAP2 busy", __func__);
6570 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
6571 vm_page_pte2_attr(m)));
6572 end = (uint32_t*)(pc->pc_cmap2_addr + PAGE_SIZE);
6573 for (p = (uint32_t*)pc->pc_cmap2_addr; p < end; p++)
6575 panic("%s: page %p not zero, va: %p", __func__, m,
6577 pte2_clear(cmap2_pte2p);
6578 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
6580 mtx_unlock(&pc->pc_cmap_lock);
6584 pmap_pid_dump(int pid)
6591 sx_slock(&allproc_lock);
6592 FOREACH_PROC_IN_SYSTEM(p) {
6593 if (p->p_pid != pid || p->p_vmspace == NULL)
6596 pmap = vmspace_pmap(p->p_vmspace);
6597 for (i = 0; i < NPTE1_IN_PT1; i++) {
6599 pt2_entry_t *pte2p, pte2;
6600 vm_offset_t base, va;
6604 base = i << PTE1_SHIFT;
6605 pte1 = pte1_load(&pmap->pm_pt1[i]);
6607 if (pte1_is_section(pte1)) {
6609 * QQQ: Do something here!
6611 } else if (pte1_is_link(pte1)) {
6612 for (j = 0; j < NPTE2_IN_PT2; j++) {
6613 va = base + (j << PAGE_SHIFT);
6614 if (va >= VM_MIN_KERNEL_ADDRESS) {
6619 sx_sunlock(&allproc_lock);
6622 pte2p = pmap_pte2(pmap, va);
6623 pte2 = pte2_load(pte2p);
6624 pmap_pte2_release(pte2p);
6625 if (!pte2_is_valid(pte2))
6629 m = PHYS_TO_VM_PAGE(pa);
6630 printf("va: 0x%x, pa: 0x%x, h: %d, w:"
6631 " %d, f: 0x%x", va, pa,
6632 m->hold_count, m->wire_count,
6646 sx_sunlock(&allproc_lock);
6653 static pt2_entry_t *
6654 pmap_pte2_ddb(pmap_t pmap, vm_offset_t va)
6657 vm_paddr_t pt2pg_pa;
6659 pte1 = pte1_load(pmap_pte1(pmap, va));
6660 if (!pte1_is_link(pte1))
6663 if (pmap_is_current(pmap))
6664 return (pt2map_entry(va));
6666 /* Note that L2 page table size is not equal to PAGE_SIZE. */
6667 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
6668 if (pte2_pa(pte2_load(PMAP3)) != pt2pg_pa) {
6669 pte2_store(PMAP3, PTE2_KPT(pt2pg_pa));
6671 PMAP3cpu = PCPU_GET(cpuid);
6673 tlb_flush_local((vm_offset_t)PADDR3);
6676 else if (PMAP3cpu != PCPU_GET(cpuid)) {
6677 PMAP3cpu = PCPU_GET(cpuid);
6678 tlb_flush_local((vm_offset_t)PADDR3);
6681 return (PADDR3 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
6685 dump_pmap(pmap_t pmap)
6688 printf("pmap %p\n", pmap);
6689 printf(" pm_pt1: %p\n", pmap->pm_pt1);
6690 printf(" pm_pt2tab: %p\n", pmap->pm_pt2tab);
6691 printf(" pm_active: 0x%08lX\n", pmap->pm_active.__bits[0]);
6694 DB_SHOW_COMMAND(pmaps, pmap_list_pmaps)
6698 LIST_FOREACH(pmap, &allpmaps, pm_list) {
6704 pte2_class(pt2_entry_t pte2)
6708 cls = (pte2 >> 2) & 0x03;
6709 cls |= (pte2 >> 4) & 0x04;
6714 dump_section(pmap_t pmap, uint32_t pte1_idx)
6719 dump_link(pmap_t pmap, uint32_t pte1_idx, boolean_t invalid_ok)
6723 pt2_entry_t *pte2p, pte2;
6726 va = pte1_idx << PTE1_SHIFT;
6727 pte2p = pmap_pte2_ddb(pmap, va);
6728 for (i = 0; i < NPTE2_IN_PT2; i++, pte2p++, va += PAGE_SIZE) {
6729 pte2 = pte2_load(pte2p);
6732 if (!pte2_is_valid(pte2)) {
6733 printf(" 0x%08X: 0x%08X", va, pte2);
6735 printf(" - not valid !!!");
6739 m = PHYS_TO_VM_PAGE(pte2_pa(pte2));
6740 printf(" 0x%08X: 0x%08X, TEX%d, s:%d, g:%d, m:%p", va , pte2,
6741 pte2_class(pte2), !!(pte2 & PTE2_S), !(pte2 & PTE2_NG), m);
6743 printf(" v:%d h:%d w:%d f:0x%04X\n", m->valid,
6744 m->hold_count, m->wire_count, m->flags);
6751 static __inline boolean_t
6752 is_pv_chunk_space(vm_offset_t va)
6755 if ((((vm_offset_t)pv_chunkbase) <= va) &&
6756 (va < ((vm_offset_t)pv_chunkbase + PAGE_SIZE * pv_maxchunks)))
6761 DB_SHOW_COMMAND(pmap, pmap_pmap_print)
6763 /* XXX convert args. */
6764 pmap_t pmap = (pmap_t)addr;
6767 vm_offset_t va, eva;
6770 boolean_t invalid_ok, dump_link_ok, dump_pv_chunk;
6775 LIST_FOREACH(pm, &allpmaps, pm_list)
6776 if (pm == pmap) break;
6778 printf("given pmap %p is not in allpmaps list\n", pmap);
6782 pmap = PCPU_GET(curpmap);
6784 eva = (modif[0] == 'u') ? VM_MAXUSER_ADDRESS : 0xFFFFFFFF;
6785 dump_pv_chunk = FALSE; /* XXX evaluate from modif[] */
6787 printf("pmap: 0x%08X\n", (uint32_t)pmap);
6788 printf("PT2MAP: 0x%08X\n", (uint32_t)PT2MAP);
6789 printf("pt2tab: 0x%08X\n", (uint32_t)pmap->pm_pt2tab);
6791 for(i = 0; i < NPTE1_IN_PT1; i++) {
6792 pte1 = pte1_load(&pmap->pm_pt1[i]);
6795 va = i << PTE1_SHIFT;
6799 if (pte1_is_section(pte1)) {
6800 printf("0x%08X: Section 0x%08X, s:%d g:%d\n", va, pte1,
6801 !!(pte1 & PTE1_S), !(pte1 & PTE1_NG));
6802 dump_section(pmap, i);
6803 } else if (pte1_is_link(pte1)) {
6804 dump_link_ok = TRUE;
6806 pte2 = pte2_load(pmap_pt2tab_entry(pmap, va));
6807 m = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
6808 printf("0x%08X: Link 0x%08X, pt2tab: 0x%08X m: %p",
6810 if (is_pv_chunk_space(va)) {
6811 printf(" - pv_chunk space");
6815 dump_link_ok = FALSE;
6818 printf(" w:%d w2:%u", m->wire_count,
6819 pt2_wirecount_get(m, pte1_index(va)));
6821 printf(" !!! pt2tab entry is ZERO");
6822 else if (pte2_pa(pte1) != pte2_pa(pte2))
6823 printf(" !!! pt2tab entry is DIFFERENT - m: %p",
6824 PHYS_TO_VM_PAGE(pte2_pa(pte2)));
6827 dump_link(pmap, i, invalid_ok);
6829 printf("0x%08X: Invalid entry 0x%08X\n", va, pte1);
6834 dump_pt2tab(pmap_t pmap)
6842 printf("PT2TAB:\n");
6843 for (i = 0; i < PT2TAB_ENTRIES; i++) {
6844 pte2 = pte2_load(&pmap->pm_pt2tab[i]);
6845 if (!pte2_is_valid(pte2))
6847 va = i << PT2TAB_SHIFT;
6849 m = PHYS_TO_VM_PAGE(pa);
6850 printf(" 0x%08X: 0x%08X, TEX%d, s:%d, m:%p", va, pte2,
6851 pte2_class(pte2), !!(pte2 & PTE2_S), m);
6853 printf(" , h: %d, w: %d, f: 0x%04X pidx: %lld",
6854 m->hold_count, m->wire_count, m->flags, m->pindex);
6859 DB_SHOW_COMMAND(pmap_pt2tab, pmap_pt2tab_print)
6861 /* XXX convert args. */
6862 pmap_t pmap = (pmap_t)addr;
6869 printf("supported only on current pmap\n");
6873 pmap = PCPU_GET(curpmap);
6874 printf("curpmap: 0x%08X\n", (uint32_t)pmap);
6875 printf("PT2MAP: 0x%08X\n", (uint32_t)PT2MAP);
6876 printf("pt2tab: 0x%08X\n", (uint32_t)pmap->pm_pt2tab);
6878 start = pte1_index((vm_offset_t)PT2MAP);
6879 for (i = start; i < (start + NPT2_IN_PT2TAB); i++) {
6880 pte1 = pte1_load(&pmap->pm_pt1[i]);
6883 va = i << PTE1_SHIFT;
6884 if (pte1_is_section(pte1)) {
6885 printf("0x%08X: Section 0x%08X, s:%d\n", va, pte1,
6887 dump_section(pmap, i);
6888 } else if (pte1_is_link(pte1)) {
6889 pte2 = pte2_load(pmap_pt2tab_entry(pmap, va));
6890 printf("0x%08X: Link 0x%08X, pt2tab: 0x%08X\n", va,
6893 printf(" !!! pt2tab entry is ZERO\n");
6895 printf("0x%08X: Invalid entry 0x%08X\n", va, pte1);