2 * SPDX-License-Identifier: BSD-3-Clause AND BSD-2-Clause-FreeBSD
4 * Copyright (c) 1991 Regents of the University of California.
5 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
7 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
8 * Copyright (c) 2014-2016 Svatopluk Kraus <skra@FreeBSD.org>
9 * Copyright (c) 2014-2016 Michal Meloun <mmel@FreeBSD.org>
10 * All rights reserved.
12 * This code is derived from software contributed to Berkeley by
13 * the Systems Programming Group of the University of Utah Computer
14 * Science Department and William Jolitz of UUNET Technologies Inc.
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions
19 * 1. Redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution.
24 * 3. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
43 * Copyright (c) 2003 Networks Associates Technology, Inc.
44 * All rights reserved.
46 * This software was developed for the FreeBSD Project by Jake Burkholder,
47 * Safeport Network Services, and Network Associates Laboratories, the
48 * Security Research Division of Network Associates, Inc. under
49 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
50 * CHATS research program.
52 * Redistribution and use in source and binary forms, with or without
53 * modification, are permitted provided that the following conditions
55 * 1. Redistributions of source code must retain the above copyright
56 * notice, this list of conditions and the following disclaimer.
57 * 2. Redistributions in binary form must reproduce the above copyright
58 * notice, this list of conditions and the following disclaimer in the
59 * documentation and/or other materials provided with the distribution.
61 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
62 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
64 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
74 #include <sys/cdefs.h>
75 __FBSDID("$FreeBSD$");
78 * Manages physical address maps.
80 * Since the information managed by this module is
81 * also stored by the logical address mapping module,
82 * this module may throw away valid virtual-to-physical
83 * mappings at almost any time. However, invalidations
84 * of virtual-to-physical mappings must be done as
87 * In order to cope with hardware architectures which
88 * make virtual-to-physical map invalidates expensive,
89 * this module may delay invalidate or reduced protection
90 * operations until such time as they are actually
91 * necessary. This module is given full information as
92 * to which processors are currently using which maps,
93 * and to when physical maps must be made correct.
100 #include <sys/param.h>
101 #include <sys/systm.h>
102 #include <sys/kernel.h>
104 #include <sys/lock.h>
105 #include <sys/proc.h>
106 #include <sys/rwlock.h>
107 #include <sys/malloc.h>
108 #include <sys/vmmeter.h>
109 #include <sys/malloc.h>
110 #include <sys/mman.h>
111 #include <sys/sf_buf.h>
113 #include <sys/sched.h>
114 #include <sys/sysctl.h>
120 #include <machine/physmem.h>
125 #include <vm/vm_param.h>
126 #include <vm/vm_kern.h>
127 #include <vm/vm_object.h>
128 #include <vm/vm_map.h>
129 #include <vm/vm_page.h>
130 #include <vm/vm_pageout.h>
131 #include <vm/vm_phys.h>
132 #include <vm/vm_extern.h>
133 #include <vm/vm_reserv.h>
134 #include <sys/lock.h>
135 #include <sys/mutex.h>
137 #include <machine/md_var.h>
138 #include <machine/pmap_var.h>
139 #include <machine/cpu.h>
140 #include <machine/pcb.h>
141 #include <machine/sf_buf.h>
143 #include <machine/smp.h>
145 #ifndef PMAP_SHPGPERPROC
146 #define PMAP_SHPGPERPROC 200
150 #define PMAP_INLINE __inline
156 static void pmap_zero_page_check(vm_page_t m);
157 void pmap_debug(int level);
158 int pmap_pid_dump(int pid);
160 #define PDEBUG(_lev_,_stat_) \
161 if (pmap_debug_level >= (_lev_)) \
163 #define dprintf printf
164 int pmap_debug_level = 1;
165 #else /* PMAP_DEBUG */
166 #define PDEBUG(_lev_,_stat_) /* Nothing */
167 #define dprintf(x, arg...)
168 #endif /* PMAP_DEBUG */
171 * Level 2 page tables map definion ('max' is excluded).
174 #define PT2V_MIN_ADDRESS ((vm_offset_t)PT2MAP)
175 #define PT2V_MAX_ADDRESS ((vm_offset_t)PT2MAP + PT2MAP_SIZE)
177 #define UPT2V_MIN_ADDRESS ((vm_offset_t)PT2MAP)
178 #define UPT2V_MAX_ADDRESS \
179 ((vm_offset_t)(PT2MAP + (KERNBASE >> PT2MAP_SHIFT)))
182 * Promotion to a 1MB (PTE1) page mapping requires that the corresponding
183 * 4KB (PTE2) page mappings have identical settings for the following fields:
185 #define PTE2_PROMOTE (PTE2_V | PTE2_A | PTE2_NM | PTE2_S | PTE2_NG | \
186 PTE2_NX | PTE2_RO | PTE2_U | PTE2_W | \
189 #define PTE1_PROMOTE (PTE1_V | PTE1_A | PTE1_NM | PTE1_S | PTE1_NG | \
190 PTE1_NX | PTE1_RO | PTE1_U | PTE1_W | \
193 #define ATTR_TO_L1(l2_attr) ((((l2_attr) & L2_TEX0) ? L1_S_TEX0 : 0) | \
194 (((l2_attr) & L2_C) ? L1_S_C : 0) | \
195 (((l2_attr) & L2_B) ? L1_S_B : 0) | \
196 (((l2_attr) & PTE2_A) ? PTE1_A : 0) | \
197 (((l2_attr) & PTE2_NM) ? PTE1_NM : 0) | \
198 (((l2_attr) & PTE2_S) ? PTE1_S : 0) | \
199 (((l2_attr) & PTE2_NG) ? PTE1_NG : 0) | \
200 (((l2_attr) & PTE2_NX) ? PTE1_NX : 0) | \
201 (((l2_attr) & PTE2_RO) ? PTE1_RO : 0) | \
202 (((l2_attr) & PTE2_U) ? PTE1_U : 0) | \
203 (((l2_attr) & PTE2_W) ? PTE1_W : 0))
205 #define ATTR_TO_L2(l1_attr) ((((l1_attr) & L1_S_TEX0) ? L2_TEX0 : 0) | \
206 (((l1_attr) & L1_S_C) ? L2_C : 0) | \
207 (((l1_attr) & L1_S_B) ? L2_B : 0) | \
208 (((l1_attr) & PTE1_A) ? PTE2_A : 0) | \
209 (((l1_attr) & PTE1_NM) ? PTE2_NM : 0) | \
210 (((l1_attr) & PTE1_S) ? PTE2_S : 0) | \
211 (((l1_attr) & PTE1_NG) ? PTE2_NG : 0) | \
212 (((l1_attr) & PTE1_NX) ? PTE2_NX : 0) | \
213 (((l1_attr) & PTE1_RO) ? PTE2_RO : 0) | \
214 (((l1_attr) & PTE1_U) ? PTE2_U : 0) | \
215 (((l1_attr) & PTE1_W) ? PTE2_W : 0))
218 * PTE2 descriptors creation macros.
220 #define PTE2_ATTR_DEFAULT vm_memattr_to_pte2(VM_MEMATTR_DEFAULT)
221 #define PTE2_ATTR_PT vm_memattr_to_pte2(pt_memattr)
223 #define PTE2_KPT(pa) PTE2_KERN(pa, PTE2_AP_KRW, PTE2_ATTR_PT)
224 #define PTE2_KPT_NG(pa) PTE2_KERN_NG(pa, PTE2_AP_KRW, PTE2_ATTR_PT)
226 #define PTE2_KRW(pa) PTE2_KERN(pa, PTE2_AP_KRW, PTE2_ATTR_DEFAULT)
227 #define PTE2_KRO(pa) PTE2_KERN(pa, PTE2_AP_KR, PTE2_ATTR_DEFAULT)
231 #define PV_STAT(x) do { x ; } while (0)
233 #define PV_STAT(x) do { } while (0)
237 * The boot_pt1 is used temporary in very early boot stage as L1 page table.
238 * We can init many things with no memory allocation thanks to its static
239 * allocation and this brings two main advantages:
240 * (1) other cores can be started very simply,
241 * (2) various boot loaders can be supported as its arguments can be processed
242 * in virtual address space and can be moved to safe location before
243 * first allocation happened.
244 * Only disadvantage is that boot_pt1 is used only in very early boot stage.
245 * However, the table is uninitialized and so lays in bss. Therefore kernel
246 * image size is not influenced.
248 * QQQ: In the future, maybe, boot_pt1 can be used for soft reset and
249 * CPU suspend/resume game.
251 extern pt1_entry_t boot_pt1[];
254 pt1_entry_t *kern_pt1;
255 pt2_entry_t *kern_pt2tab;
258 static uint32_t ttb_flags;
259 static vm_memattr_t pt_memattr;
260 ttb_entry_t pmap_kern_ttb;
262 struct pmap kernel_pmap_store;
263 LIST_HEAD(pmaplist, pmap);
264 static struct pmaplist allpmaps;
265 static struct mtx allpmaps_lock;
267 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
268 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
270 static vm_offset_t kernel_vm_end_new;
271 vm_offset_t kernel_vm_end = KERNBASE + NKPT2PG * NPT2_IN_PG * PTE1_SIZE;
272 vm_offset_t vm_max_kernel_address;
273 vm_paddr_t kernel_l1pa;
275 static struct rwlock __aligned(CACHE_LINE_SIZE) pvh_global_lock;
278 * Data for the pv entry allocation mechanism
280 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
281 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
282 static struct md_page *pv_table; /* XXX: Is it used only the list in md_page? */
283 static int shpgperproc = PMAP_SHPGPERPROC;
285 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
286 int pv_maxchunks; /* How many chunks we have KVA for */
287 vm_offset_t pv_vafree; /* freelist stored in the PTE */
289 vm_paddr_t first_managed_pa;
290 #define pa_to_pvh(pa) (&pv_table[pte1_index(pa - first_managed_pa)])
293 * All those kernel PT submaps that BSD is so fond of
300 static caddr_t crashdumpmap;
302 static pt2_entry_t *PMAP1 = NULL, *PMAP2;
303 static pt2_entry_t *PADDR1 = NULL, *PADDR2;
305 static pt2_entry_t *PMAP3;
306 static pt2_entry_t *PADDR3;
307 static int PMAP3cpu __unused; /* for SMP only */
311 static int PMAP1changedcpu;
312 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
314 "Number of times pmap_pte2_quick changed CPU with same PMAP1");
316 static int PMAP1changed;
317 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
319 "Number of times pmap_pte2_quick changed PMAP1");
320 static int PMAP1unchanged;
321 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
323 "Number of times pmap_pte2_quick didn't change PMAP1");
324 static struct mtx PMAP2mutex;
327 * Internal flags for pmap_enter()'s helper functions.
329 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
330 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
332 static __inline void pt2_wirecount_init(vm_page_t m);
333 static boolean_t pmap_demote_pte1(pmap_t pmap, pt1_entry_t *pte1p,
335 static int pmap_enter_pte1(pmap_t pmap, vm_offset_t va, pt1_entry_t pte1,
336 u_int flags, vm_page_t m);
337 void cache_icache_sync_fresh(vm_offset_t va, vm_paddr_t pa, vm_size_t size);
340 * Function to set the debug level of the pmap code.
344 pmap_debug(int level)
347 pmap_debug_level = level;
348 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
350 #endif /* PMAP_DEBUG */
353 * This table must corespond with memory attribute configuration in vm.h.
354 * First entry is used for normal system mapping.
356 * Device memory is always marked as shared.
357 * Normal memory is shared only in SMP .
358 * Not outer shareable bits are not used yet.
359 * Class 6 cannot be used on ARM11.
361 #define TEXDEF_TYPE_SHIFT 0
362 #define TEXDEF_TYPE_MASK 0x3
363 #define TEXDEF_INNER_SHIFT 2
364 #define TEXDEF_INNER_MASK 0x3
365 #define TEXDEF_OUTER_SHIFT 4
366 #define TEXDEF_OUTER_MASK 0x3
367 #define TEXDEF_NOS_SHIFT 6
368 #define TEXDEF_NOS_MASK 0x1
370 #define TEX(t, i, o, s) \
371 ((t) << TEXDEF_TYPE_SHIFT) | \
372 ((i) << TEXDEF_INNER_SHIFT) | \
373 ((o) << TEXDEF_OUTER_SHIFT | \
374 ((s) << TEXDEF_NOS_SHIFT))
376 static uint32_t tex_class[8] = {
377 /* type inner cache outer cache */
378 TEX(PRRR_MEM, NMRR_WB_WA, NMRR_WB_WA, 0), /* 0 - ATTR_WB_WA */
379 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 1 - ATTR_NOCACHE */
380 TEX(PRRR_DEV, NMRR_NC, NMRR_NC, 0), /* 2 - ATTR_DEVICE */
381 TEX(PRRR_SO, NMRR_NC, NMRR_NC, 0), /* 3 - ATTR_SO */
382 TEX(PRRR_MEM, NMRR_WT, NMRR_WT, 0), /* 4 - ATTR_WT */
383 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 5 - NOT USED YET */
384 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 6 - NOT USED YET */
385 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 7 - NOT USED YET */
389 static uint32_t pte2_attr_tab[8] = {
390 PTE2_ATTR_WB_WA, /* 0 - VM_MEMATTR_WB_WA */
391 PTE2_ATTR_NOCACHE, /* 1 - VM_MEMATTR_NOCACHE */
392 PTE2_ATTR_DEVICE, /* 2 - VM_MEMATTR_DEVICE */
393 PTE2_ATTR_SO, /* 3 - VM_MEMATTR_SO */
394 PTE2_ATTR_WT, /* 4 - VM_MEMATTR_WRITE_THROUGH */
395 0, /* 5 - NOT USED YET */
396 0, /* 6 - NOT USED YET */
397 0 /* 7 - NOT USED YET */
399 CTASSERT(VM_MEMATTR_WB_WA == 0);
400 CTASSERT(VM_MEMATTR_NOCACHE == 1);
401 CTASSERT(VM_MEMATTR_DEVICE == 2);
402 CTASSERT(VM_MEMATTR_SO == 3);
403 CTASSERT(VM_MEMATTR_WRITE_THROUGH == 4);
404 #define VM_MEMATTR_END (VM_MEMATTR_WRITE_THROUGH + 1)
407 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
410 return (mode >= 0 && mode < VM_MEMATTR_END);
413 static inline uint32_t
414 vm_memattr_to_pte2(vm_memattr_t ma)
417 KASSERT((u_int)ma < VM_MEMATTR_END,
418 ("%s: bad vm_memattr_t %d", __func__, ma));
419 return (pte2_attr_tab[(u_int)ma]);
422 static inline uint32_t
423 vm_page_pte2_attr(vm_page_t m)
426 return (vm_memattr_to_pte2(m->md.pat_mode));
430 * Convert TEX definition entry to TTB flags.
433 encode_ttb_flags(int idx)
435 uint32_t inner, outer, nos, reg;
437 inner = (tex_class[idx] >> TEXDEF_INNER_SHIFT) &
439 outer = (tex_class[idx] >> TEXDEF_OUTER_SHIFT) &
441 nos = (tex_class[idx] >> TEXDEF_NOS_SHIFT) &
446 if (cpuinfo.coherent_walk)
447 reg |= (inner & 0x1) << 6;
448 reg |= (inner & 0x2) >> 1;
458 * Set TEX remapping registers in current CPU.
464 uint32_t type, inner, outer, nos;
467 #ifdef PMAP_PTE_NOCACHE
469 if (cpuinfo.coherent_walk) {
470 pt_memattr = VM_MEMATTR_WB_WA;
471 ttb_flags = encode_ttb_flags(0);
474 pt_memattr = VM_MEMATTR_NOCACHE;
475 ttb_flags = encode_ttb_flags(1);
478 pt_memattr = VM_MEMATTR_WB_WA;
479 ttb_flags = encode_ttb_flags(0);
485 /* Build remapping register from TEX classes. */
486 for (i = 0; i < 8; i++) {
487 type = (tex_class[i] >> TEXDEF_TYPE_SHIFT) &
489 inner = (tex_class[i] >> TEXDEF_INNER_SHIFT) &
491 outer = (tex_class[i] >> TEXDEF_OUTER_SHIFT) &
493 nos = (tex_class[i] >> TEXDEF_NOS_SHIFT) &
496 prrr |= type << (i * 2);
497 prrr |= nos << (i + 24);
498 nmrr |= inner << (i * 2);
499 nmrr |= outer << (i * 2 + 16);
501 /* Add shareable bits for device memory. */
502 prrr |= PRRR_DS0 | PRRR_DS1;
504 /* Add shareable bits for normal memory in SMP case. */
513 /* Caches are disabled, so full TLB flush should be enough. */
514 tlb_flush_all_local();
518 * Remap one vm_meattr class to another one. This can be useful as
519 * workaround for SOC errata, e.g. if devices must be accessed using
522 * !!! Please note that this function is absolutely last resort thing.
523 * It should not be used under normal circumstances. !!!
526 * - it shall be called after pmap_bootstrap_prepare() and before
527 * cpu_mp_start() (thus only on boot CPU). In practice, it's expected
528 * to be called from platform_attach() or platform_late_init().
530 * - if remapping doesn't change caching mode, or until uncached class
531 * is remapped to any kind of cached one, then no other restriction exists.
533 * - if pmap_remap_vm_attr() changes caching mode, but both (original and
534 * remapped) remain cached, then caller is resposible for calling
535 * of dcache_wbinv_poc_all().
537 * - remapping of any kind of cached class to uncached is not permitted.
540 pmap_remap_vm_attr(vm_memattr_t old_attr, vm_memattr_t new_attr)
542 int old_idx, new_idx;
544 /* Map VM memattrs to indexes to tex_class table. */
545 old_idx = PTE2_ATTR2IDX(pte2_attr_tab[(int)old_attr]);
546 new_idx = PTE2_ATTR2IDX(pte2_attr_tab[(int)new_attr]);
548 /* Replace TEX attribute and apply it. */
549 tex_class[old_idx] = tex_class[new_idx];
554 * KERNBASE must be multiple of NPT2_IN_PG * PTE1_SIZE. In other words,
555 * KERNBASE is mapped by first L2 page table in L2 page table page. It
556 * meets same constrain due to PT2MAP being placed just under KERNBASE.
558 CTASSERT((KERNBASE & (NPT2_IN_PG * PTE1_SIZE - 1)) == 0);
559 CTASSERT((KERNBASE - VM_MAXUSER_ADDRESS) >= PT2MAP_SIZE);
562 * In crazy dreams, PAGE_SIZE could be a multiple of PTE2_SIZE in general.
563 * For now, anyhow, the following check must be fulfilled.
565 CTASSERT(PAGE_SIZE == PTE2_SIZE);
567 * We don't want to mess up MI code with all MMU and PMAP definitions,
568 * so some things, which depend on other ones, are defined independently.
569 * Now, it is time to check that we don't screw up something.
571 CTASSERT(PDRSHIFT == PTE1_SHIFT);
573 * Check L1 and L2 page table entries definitions consistency.
575 CTASSERT(NB_IN_PT1 == (sizeof(pt1_entry_t) * NPTE1_IN_PT1));
576 CTASSERT(NB_IN_PT2 == (sizeof(pt2_entry_t) * NPTE2_IN_PT2));
578 * Check L2 page tables page consistency.
580 CTASSERT(PAGE_SIZE == (NPT2_IN_PG * NB_IN_PT2));
581 CTASSERT((1 << PT2PG_SHIFT) == NPT2_IN_PG);
583 * Check PT2TAB consistency.
584 * PT2TAB_ENTRIES is defined as a division of NPTE1_IN_PT1 by NPT2_IN_PG.
585 * This should be done without remainder.
587 CTASSERT(NPTE1_IN_PT1 == (PT2TAB_ENTRIES * NPT2_IN_PG));
592 * All level 2 page tables (PT2s) are mapped continuously and accordingly
593 * into PT2MAP address space. As PT2 size is less than PAGE_SIZE, this can
594 * be done only if PAGE_SIZE is a multiple of PT2 size. All PT2s in one page
595 * must be used together, but not necessary at once. The first PT2 in a page
596 * must map things on correctly aligned address and the others must follow
599 #define NB_IN_PT2TAB (PT2TAB_ENTRIES * sizeof(pt2_entry_t))
600 #define NPT2_IN_PT2TAB (NB_IN_PT2TAB / NB_IN_PT2)
601 #define NPG_IN_PT2TAB (NB_IN_PT2TAB / PAGE_SIZE)
604 * Check PT2TAB consistency.
605 * NPT2_IN_PT2TAB is defined as a division of NB_IN_PT2TAB by NB_IN_PT2.
606 * NPG_IN_PT2TAB is defined as a division of NB_IN_PT2TAB by PAGE_SIZE.
607 * The both should be done without remainder.
609 CTASSERT(NB_IN_PT2TAB == (NPT2_IN_PT2TAB * NB_IN_PT2));
610 CTASSERT(NB_IN_PT2TAB == (NPG_IN_PT2TAB * PAGE_SIZE));
612 * The implementation was made general, however, with the assumption
613 * bellow in mind. In case of another value of NPG_IN_PT2TAB,
614 * the code should be once more rechecked.
616 CTASSERT(NPG_IN_PT2TAB == 1);
619 * Get offset of PT2 in a page
620 * associated with given PT1 index.
622 static __inline u_int
623 page_pt2off(u_int pt1_idx)
626 return ((pt1_idx & PT2PG_MASK) * NB_IN_PT2);
630 * Get physical address of PT2
631 * associated with given PT2s page and PT1 index.
633 static __inline vm_paddr_t
634 page_pt2pa(vm_paddr_t pgpa, u_int pt1_idx)
637 return (pgpa + page_pt2off(pt1_idx));
641 * Get first entry of PT2
642 * associated with given PT2s page and PT1 index.
644 static __inline pt2_entry_t *
645 page_pt2(vm_offset_t pgva, u_int pt1_idx)
648 return ((pt2_entry_t *)(pgva + page_pt2off(pt1_idx)));
652 * Get virtual address of PT2s page (mapped in PT2MAP)
653 * which holds PT2 which holds entry which maps given virtual address.
655 static __inline vm_offset_t
656 pt2map_pt2pg(vm_offset_t va)
659 va &= ~(NPT2_IN_PG * PTE1_SIZE - 1);
660 return ((vm_offset_t)pt2map_entry(va));
663 /*****************************************************************************
665 * THREE pmap initialization milestones exist:
668 * -> fundamental init (including MMU) in ASM
671 * -> fundamental init continues in C
672 * -> first available physical address is known
674 * pmap_bootstrap_prepare() -> FIRST PMAP MILESTONE (first epoch begins)
675 * -> basic (safe) interface for physical address allocation is made
676 * -> basic (safe) interface for virtual mapping is made
677 * -> limited not SMP coherent work is possible
679 * -> more fundamental init continues in C
680 * -> locks and some more things are available
681 * -> all fundamental allocations and mappings are done
683 * pmap_bootstrap() -> SECOND PMAP MILESTONE (second epoch begins)
684 * -> phys_avail[] and virtual_avail is set
685 * -> control is passed to vm subsystem
686 * -> physical and virtual address allocation are off limit
687 * -> low level mapping functions, some SMP coherent,
688 * are available, which cannot be used before vm subsystem
692 * -> vm subsystem is being inited
694 * pmap_init() -> THIRD PMAP MILESTONE (third epoch begins)
695 * -> pmap is fully inited
697 *****************************************************************************/
699 /*****************************************************************************
701 * PMAP first stage initialization and utility functions
702 * for pre-bootstrap epoch.
704 * After pmap_bootstrap_prepare() is called, the following functions
707 * (1) strictly only for this stage functions for physical page allocations,
708 * virtual space allocations, and mappings:
710 * vm_paddr_t pmap_preboot_get_pages(u_int num);
711 * void pmap_preboot_map_pages(vm_paddr_t pa, vm_offset_t va, u_int num);
712 * vm_offset_t pmap_preboot_reserve_pages(u_int num);
713 * vm_offset_t pmap_preboot_get_vpages(u_int num);
714 * void pmap_preboot_map_attr(vm_paddr_t pa, vm_offset_t va, vm_size_t size,
715 * vm_prot_t prot, vm_memattr_t attr);
717 * (2) for all stages:
719 * vm_paddr_t pmap_kextract(vm_offset_t va);
721 * NOTE: This is not SMP coherent stage.
723 *****************************************************************************/
725 #define KERNEL_P2V(pa) \
726 ((vm_offset_t)((pa) - arm_physmem_kernaddr + KERNVIRTADDR))
727 #define KERNEL_V2P(va) \
728 ((vm_paddr_t)((va) - KERNVIRTADDR + arm_physmem_kernaddr))
730 static vm_paddr_t last_paddr;
733 * Pre-bootstrap epoch page allocator.
736 pmap_preboot_get_pages(u_int num)
741 last_paddr += num * PAGE_SIZE;
747 * The fundamental initialization of PMAP stuff.
749 * Some things already happened in locore.S and some things could happen
750 * before pmap_bootstrap_prepare() is called, so let's recall what is done:
751 * 1. Caches are disabled.
752 * 2. We are running on virtual addresses already with 'boot_pt1'
754 * 3. So far, all virtual addresses can be converted to physical ones and
755 * vice versa by the following macros:
756 * KERNEL_P2V(pa) .... physical to virtual ones,
757 * KERNEL_V2P(va) .... virtual to physical ones.
759 * What is done herein:
760 * 1. The 'boot_pt1' is replaced by real kernel L1 page table 'kern_pt1'.
761 * 2. PT2MAP magic is brought to live.
762 * 3. Basic preboot functions for page allocations and mappings can be used.
763 * 4. Everything is prepared for L1 cache enabling.
766 * 1. To use second TTB register, so kernel and users page tables will be
767 * separated. This way process forking - pmap_pinit() - could be faster,
768 * it saves physical pages and KVA per a process, and it's simple change.
769 * However, it will lead, due to hardware matter, to the following:
770 * (a) 2G space for kernel and 2G space for users.
771 * (b) 1G space for kernel in low addresses and 3G for users above it.
772 * A question is: Is the case (b) really an option? Note that case (b)
773 * does save neither physical memory and KVA.
776 pmap_bootstrap_prepare(vm_paddr_t last)
778 vm_paddr_t pt2pg_pa, pt2tab_pa, pa, size;
779 vm_offset_t pt2pg_va;
786 * Now, we are going to make real kernel mapping. Note that we are
787 * already running on some mapping made in locore.S and we expect
788 * that it's large enough to ensure nofault access to physical memory
789 * allocated herein before switch.
791 * As kernel image and everything needed before are and will be mapped
792 * by section mappings, we align last physical address to PTE1_SIZE.
794 last_paddr = pte1_roundup(last);
797 * Allocate and zero page(s) for kernel L1 page table.
799 * Note that it's first allocation on space which was PTE1_SIZE
800 * aligned and as such base_pt1 is aligned to NB_IN_PT1 too.
802 base_pt1 = pmap_preboot_get_pages(NPG_IN_PT1);
803 kern_pt1 = (pt1_entry_t *)KERNEL_P2V(base_pt1);
804 bzero((void*)kern_pt1, NB_IN_PT1);
805 pte1_sync_range(kern_pt1, NB_IN_PT1);
807 /* Allocate and zero page(s) for kernel PT2TAB. */
808 pt2tab_pa = pmap_preboot_get_pages(NPG_IN_PT2TAB);
809 kern_pt2tab = (pt2_entry_t *)KERNEL_P2V(pt2tab_pa);
810 bzero(kern_pt2tab, NB_IN_PT2TAB);
811 pte2_sync_range(kern_pt2tab, NB_IN_PT2TAB);
813 /* Allocate and zero page(s) for kernel L2 page tables. */
814 pt2pg_pa = pmap_preboot_get_pages(NKPT2PG);
815 pt2pg_va = KERNEL_P2V(pt2pg_pa);
816 size = NKPT2PG * PAGE_SIZE;
817 bzero((void*)pt2pg_va, size);
818 pte2_sync_range((pt2_entry_t *)pt2pg_va, size);
821 * Add a physical memory segment (vm_phys_seg) corresponding to the
822 * preallocated pages for kernel L2 page tables so that vm_page
823 * structures representing these pages will be created. The vm_page
824 * structures are required for promotion of the corresponding kernel
825 * virtual addresses to section mappings.
827 vm_phys_add_seg(pt2tab_pa, pmap_preboot_get_pages(0));
830 * Insert allocated L2 page table pages to PT2TAB and make
831 * link to all PT2s in L1 page table. See how kernel_vm_end
834 * We play simple and safe. So every KVA will have underlaying
835 * L2 page table, even kernel image mapped by sections.
837 pte2p = kern_pt2tab_entry(KERNBASE);
838 for (pa = pt2pg_pa; pa < pt2pg_pa + size; pa += PTE2_SIZE)
839 pt2tab_store(pte2p++, PTE2_KPT(pa));
841 pte1p = kern_pte1(KERNBASE);
842 for (pa = pt2pg_pa; pa < pt2pg_pa + size; pa += NB_IN_PT2)
843 pte1_store(pte1p++, PTE1_LINK(pa));
845 /* Make section mappings for kernel. */
846 l1_attr = ATTR_TO_L1(PTE2_ATTR_DEFAULT);
847 pte1p = kern_pte1(KERNBASE);
848 for (pa = KERNEL_V2P(KERNBASE); pa < last; pa += PTE1_SIZE)
849 pte1_store(pte1p++, PTE1_KERN(pa, PTE1_AP_KRW, l1_attr));
852 * Get free and aligned space for PT2MAP and make L1 page table links
853 * to L2 page tables held in PT2TAB.
855 * Note that pages holding PT2s are stored in PT2TAB as pt2_entry_t
856 * descriptors and PT2TAB page(s) itself is(are) used as PT2s. Thus
857 * each entry in PT2TAB maps all PT2s in a page. This implies that
858 * virtual address of PT2MAP must be aligned to NPT2_IN_PG * PTE1_SIZE.
860 PT2MAP = (pt2_entry_t *)(KERNBASE - PT2MAP_SIZE);
861 pte1p = kern_pte1((vm_offset_t)PT2MAP);
862 for (pa = pt2tab_pa, i = 0; i < NPT2_IN_PT2TAB; i++, pa += NB_IN_PT2) {
863 pte1_store(pte1p++, PTE1_LINK(pa));
867 * Store PT2TAB in PT2TAB itself, i.e. self reference mapping.
868 * Each pmap will hold own PT2TAB, so the mapping should be not global.
870 pte2p = kern_pt2tab_entry((vm_offset_t)PT2MAP);
871 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE) {
872 pt2tab_store(pte2p++, PTE2_KPT_NG(pa));
876 * Choose correct L2 page table and make mappings for allocations
877 * made herein which replaces temporary locore.S mappings after a while.
878 * Note that PT2MAP cannot be used until we switch to kern_pt1.
880 * Note, that these allocations started aligned on 1M section and
881 * kernel PT1 was allocated first. Making of mappings must follow
882 * order of physical allocations as we've used KERNEL_P2V() macro
883 * for virtual addresses resolution.
885 pte2p = kern_pt2tab_entry((vm_offset_t)kern_pt1);
886 pt2pg_va = KERNEL_P2V(pte2_pa(pte2_load(pte2p)));
888 pte2p = page_pt2(pt2pg_va, pte1_index((vm_offset_t)kern_pt1));
890 /* Make mapping for kernel L1 page table. */
891 for (pa = base_pt1, i = 0; i < NPG_IN_PT1; i++, pa += PTE2_SIZE)
892 pte2_store(pte2p++, PTE2_KPT(pa));
894 /* Make mapping for kernel PT2TAB. */
895 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE)
896 pte2_store(pte2p++, PTE2_KPT(pa));
898 /* Finally, switch from 'boot_pt1' to 'kern_pt1'. */
899 pmap_kern_ttb = base_pt1 | ttb_flags;
900 cpuinfo_reinit_mmu(pmap_kern_ttb);
902 * Initialize the first available KVA. As kernel image is mapped by
903 * sections, we are leaving some gap behind.
905 virtual_avail = (vm_offset_t)kern_pt2tab + NPG_IN_PT2TAB * PAGE_SIZE;
909 * Setup L2 page table page for given KVA.
910 * Used in pre-bootstrap epoch.
912 * Note that we have allocated NKPT2PG pages for L2 page tables in advance
913 * and used them for mapping KVA starting from KERNBASE. However, this is not
914 * enough. Vectors and devices need L2 page tables too. Note that they are
915 * even above VM_MAX_KERNEL_ADDRESS.
917 static __inline vm_paddr_t
918 pmap_preboot_pt2pg_setup(vm_offset_t va)
920 pt2_entry_t *pte2p, pte2;
923 /* Get associated entry in PT2TAB. */
924 pte2p = kern_pt2tab_entry(va);
926 /* Just return, if PT2s page exists already. */
927 pte2 = pt2tab_load(pte2p);
928 if (pte2_is_valid(pte2))
929 return (pte2_pa(pte2));
931 KASSERT(va >= VM_MAX_KERNEL_ADDRESS,
932 ("%s: NKPT2PG too small", __func__));
935 * Allocate page for PT2s and insert it to PT2TAB.
936 * In other words, map it into PT2MAP space.
938 pt2pg_pa = pmap_preboot_get_pages(1);
939 pt2tab_store(pte2p, PTE2_KPT(pt2pg_pa));
941 /* Zero all PT2s in allocated page. */
942 bzero((void*)pt2map_pt2pg(va), PAGE_SIZE);
943 pte2_sync_range((pt2_entry_t *)pt2map_pt2pg(va), PAGE_SIZE);
949 * Setup L2 page table for given KVA.
950 * Used in pre-bootstrap epoch.
953 pmap_preboot_pt2_setup(vm_offset_t va)
956 vm_paddr_t pt2pg_pa, pt2_pa;
958 /* Setup PT2's page. */
959 pt2pg_pa = pmap_preboot_pt2pg_setup(va);
960 pt2_pa = page_pt2pa(pt2pg_pa, pte1_index(va));
962 /* Insert PT2 to PT1. */
963 pte1p = kern_pte1(va);
964 pte1_store(pte1p, PTE1_LINK(pt2_pa));
968 * Get L2 page entry associated with given KVA.
969 * Used in pre-bootstrap epoch.
971 static __inline pt2_entry_t*
972 pmap_preboot_vtopte2(vm_offset_t va)
976 /* Setup PT2 if needed. */
977 pte1p = kern_pte1(va);
978 if (!pte1_is_valid(pte1_load(pte1p))) /* XXX - sections ?! */
979 pmap_preboot_pt2_setup(va);
981 return (pt2map_entry(va));
985 * Pre-bootstrap epoch page(s) mapping(s).
988 pmap_preboot_map_pages(vm_paddr_t pa, vm_offset_t va, u_int num)
993 /* Map all the pages. */
994 for (i = 0; i < num; i++) {
995 pte2p = pmap_preboot_vtopte2(va);
996 pte2_store(pte2p, PTE2_KRW(pa));
1003 * Pre-bootstrap epoch virtual space alocator.
1006 pmap_preboot_reserve_pages(u_int num)
1009 vm_offset_t start, va;
1012 /* Allocate virtual space. */
1013 start = va = virtual_avail;
1014 virtual_avail += num * PAGE_SIZE;
1016 /* Zero the mapping. */
1017 for (i = 0; i < num; i++) {
1018 pte2p = pmap_preboot_vtopte2(va);
1019 pte2_store(pte2p, 0);
1027 * Pre-bootstrap epoch page(s) allocation and mapping(s).
1030 pmap_preboot_get_vpages(u_int num)
1035 /* Allocate physical page(s). */
1036 pa = pmap_preboot_get_pages(num);
1038 /* Allocate virtual space. */
1040 virtual_avail += num * PAGE_SIZE;
1042 /* Map and zero all. */
1043 pmap_preboot_map_pages(pa, va, num);
1044 bzero((void *)va, num * PAGE_SIZE);
1050 * Pre-bootstrap epoch page mapping(s) with attributes.
1053 pmap_preboot_map_attr(vm_paddr_t pa, vm_offset_t va, vm_size_t size,
1054 vm_prot_t prot, vm_memattr_t attr)
1057 u_int l1_attr, l1_prot, l2_prot, l2_attr;
1061 l2_prot = prot & VM_PROT_WRITE ? PTE2_AP_KRW : PTE2_AP_KR;
1062 l2_prot |= (prot & VM_PROT_EXECUTE) ? PTE2_X : PTE2_NX;
1063 l2_attr = vm_memattr_to_pte2(attr);
1064 l1_prot = ATTR_TO_L1(l2_prot);
1065 l1_attr = ATTR_TO_L1(l2_attr);
1067 /* Map all the pages. */
1068 num = round_page(size);
1070 if ((((va | pa) & PTE1_OFFSET) == 0) && (num >= PTE1_SIZE)) {
1071 pte1p = kern_pte1(va);
1072 pte1_store(pte1p, PTE1_KERN(pa, l1_prot, l1_attr));
1077 pte2p = pmap_preboot_vtopte2(va);
1078 pte2_store(pte2p, PTE2_KERN(pa, l2_prot, l2_attr));
1087 * Extract from the kernel page table the physical address
1088 * that is mapped by the given virtual address "va".
1091 pmap_kextract(vm_offset_t va)
1097 pte1 = pte1_load(kern_pte1(va));
1098 if (pte1_is_section(pte1)) {
1099 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1100 } else if (pte1_is_link(pte1)) {
1102 * We should beware of concurrent promotion that changes
1103 * pte1 at this point. However, it's not a problem as PT2
1104 * page is preserved by promotion in PT2TAB. So even if
1105 * it happens, using of PT2MAP is still safe.
1107 * QQQ: However, concurrent removing is a problem which
1108 * ends in abort on PT2MAP space. Locking must be used
1109 * to deal with this.
1111 pte2 = pte2_load(pt2map_entry(va));
1112 pa = pte2_pa(pte2) | (va & PTE2_OFFSET);
1115 panic("%s: va %#x pte1 %#x", __func__, va, pte1);
1121 * Extract from the kernel page table the physical address
1122 * that is mapped by the given virtual address "va". Also
1123 * return L2 page table entry which maps the address.
1125 * This is only intended to be used for panic dumps.
1128 pmap_dump_kextract(vm_offset_t va, pt2_entry_t *pte2p)
1134 pte1 = pte1_load(kern_pte1(va));
1135 if (pte1_is_section(pte1)) {
1136 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1137 pte2 = pa | ATTR_TO_L2(pte1) | PTE2_V;
1138 } else if (pte1_is_link(pte1)) {
1139 pte2 = pte2_load(pt2map_entry(va));
1150 /*****************************************************************************
1152 * PMAP second stage initialization and utility functions
1153 * for bootstrap epoch.
1155 * After pmap_bootstrap() is called, the following functions for
1156 * mappings can be used:
1158 * void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
1159 * void pmap_kremove(vm_offset_t va);
1160 * vm_offset_t pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end,
1163 * NOTE: This is not SMP coherent stage. And physical page allocation is not
1164 * allowed during this stage.
1166 *****************************************************************************/
1169 * Initialize kernel PMAP locks and lists, kernel_pmap itself, and
1170 * reserve various virtual spaces for temporary mappings.
1173 pmap_bootstrap(vm_offset_t firstaddr)
1175 pt2_entry_t *unused __unused;
1179 * Initialize the kernel pmap (which is statically allocated).
1181 PMAP_LOCK_INIT(kernel_pmap);
1182 kernel_l1pa = (vm_paddr_t)kern_pt1; /* for libkvm */
1183 kernel_pmap->pm_pt1 = kern_pt1;
1184 kernel_pmap->pm_pt2tab = kern_pt2tab;
1185 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1186 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1189 * Initialize the global pv list lock.
1191 rw_init(&pvh_global_lock, "pmap pv global");
1193 LIST_INIT(&allpmaps);
1196 * Request a spin mutex so that changes to allpmaps cannot be
1197 * preempted by smp_rendezvous_cpus().
1199 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
1200 mtx_lock_spin(&allpmaps_lock);
1201 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
1202 mtx_unlock_spin(&allpmaps_lock);
1205 * Reserve some special page table entries/VA space for temporary
1208 #define SYSMAP(c, p, v, n) do { \
1209 v = (c)pmap_preboot_reserve_pages(n); \
1210 p = pt2map_entry((vm_offset_t)v); \
1214 * Local CMAP1/CMAP2 are used for zeroing and copying pages.
1215 * Local CMAP2 is also used for data cache cleaning.
1218 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
1219 SYSMAP(caddr_t, pc->pc_cmap1_pte2p, pc->pc_cmap1_addr, 1);
1220 SYSMAP(caddr_t, pc->pc_cmap2_pte2p, pc->pc_cmap2_addr, 1);
1221 SYSMAP(vm_offset_t, pc->pc_qmap_pte2p, pc->pc_qmap_addr, 1);
1226 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS);
1229 * _tmppt is used for reading arbitrary physical pages via /dev/mem.
1231 SYSMAP(caddr_t, unused, _tmppt, 1);
1234 * PADDR1 and PADDR2 are used by pmap_pte2_quick() and pmap_pte2(),
1235 * respectively. PADDR3 is used by pmap_pte2_ddb().
1237 SYSMAP(pt2_entry_t *, PMAP1, PADDR1, 1);
1238 SYSMAP(pt2_entry_t *, PMAP2, PADDR2, 1);
1240 SYSMAP(pt2_entry_t *, PMAP3, PADDR3, 1);
1242 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
1245 * Note that in very short time in initarm(), we are going to
1246 * initialize phys_avail[] array and no further page allocation
1247 * can happen after that until vm subsystem will be initialized.
1249 kernel_vm_end_new = kernel_vm_end;
1250 virtual_end = vm_max_kernel_address;
1254 pmap_init_reserved_pages(void)
1263 * Skip if the mapping has already been initialized,
1264 * i.e. this is the BSP.
1266 if (pc->pc_cmap1_addr != 0)
1268 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
1269 pages = kva_alloc(PAGE_SIZE * 3);
1271 panic("%s: unable to allocate KVA", __func__);
1272 pc->pc_cmap1_pte2p = pt2map_entry(pages);
1273 pc->pc_cmap2_pte2p = pt2map_entry(pages + PAGE_SIZE);
1274 pc->pc_qmap_pte2p = pt2map_entry(pages + (PAGE_SIZE * 2));
1275 pc->pc_cmap1_addr = (caddr_t)pages;
1276 pc->pc_cmap2_addr = (caddr_t)(pages + PAGE_SIZE);
1277 pc->pc_qmap_addr = pages + (PAGE_SIZE * 2);
1280 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
1283 * The function can already be use in second initialization stage.
1284 * As such, the function DOES NOT call pmap_growkernel() where PT2
1285 * allocation can happen. So if used, be sure that PT2 for given
1286 * virtual address is allocated already!
1288 * Add a wired page to the kva.
1289 * Note: not SMP coherent.
1291 static __inline void
1292 pmap_kenter_prot_attr(vm_offset_t va, vm_paddr_t pa, uint32_t prot,
1298 pte1p = kern_pte1(va);
1299 if (!pte1_is_valid(pte1_load(pte1p))) { /* XXX - sections ?! */
1301 * This is a very low level function, so PT2 and particularly
1302 * PT2PG associated with given virtual address must be already
1303 * allocated. It's a pain mainly during pmap initialization
1304 * stage. However, called after pmap initialization with
1305 * virtual address not under kernel_vm_end will lead to
1308 if (!pte2_is_valid(pte2_load(kern_pt2tab_entry(va))))
1309 panic("%s: kernel PT2 not allocated!", __func__);
1312 pte2p = pt2map_entry(va);
1313 pte2_store(pte2p, PTE2_KERN(pa, prot, attr));
1317 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1320 pmap_kenter_prot_attr(va, pa, PTE2_AP_KRW, PTE2_ATTR_DEFAULT);
1324 * Remove a page from the kernel pagetables.
1325 * Note: not SMP coherent.
1328 pmap_kremove(vm_offset_t va)
1333 pte1p = kern_pte1(va);
1334 if (pte1_is_section(pte1_load(pte1p))) {
1337 pte2p = pt2map_entry(va);
1343 * Share new kernel PT2PG with all pmaps.
1344 * The caller is responsible for maintaining TLB consistency.
1347 pmap_kenter_pt2tab(vm_offset_t va, pt2_entry_t npte2)
1352 mtx_lock_spin(&allpmaps_lock);
1353 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1354 pte2p = pmap_pt2tab_entry(pmap, va);
1355 pt2tab_store(pte2p, npte2);
1357 mtx_unlock_spin(&allpmaps_lock);
1361 * Share new kernel PTE1 with all pmaps.
1362 * The caller is responsible for maintaining TLB consistency.
1365 pmap_kenter_pte1(vm_offset_t va, pt1_entry_t npte1)
1370 mtx_lock_spin(&allpmaps_lock);
1371 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1372 pte1p = pmap_pte1(pmap, va);
1373 pte1_store(pte1p, npte1);
1375 mtx_unlock_spin(&allpmaps_lock);
1379 * Used to map a range of physical addresses into kernel
1380 * virtual address space.
1382 * The value passed in '*virt' is a suggested virtual address for
1383 * the mapping. Architectures which can support a direct-mapped
1384 * physical to virtual region can return the appropriate address
1385 * within that region, leaving '*virt' unchanged. Other
1386 * architectures should map the pages starting at '*virt' and
1387 * update '*virt' with the first usable address after the mapped
1390 * NOTE: Read the comments above pmap_kenter_prot_attr() as
1391 * the function is used herein!
1394 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1396 vm_offset_t va, sva;
1397 vm_paddr_t pte1_offset;
1399 uint32_t l1prot, l2prot;
1400 uint32_t l1attr, l2attr;
1402 PDEBUG(1, printf("%s: virt = %#x, start = %#x, end = %#x (size = %#x),"
1403 " prot = %d\n", __func__, *virt, start, end, end - start, prot));
1405 l2prot = (prot & VM_PROT_WRITE) ? PTE2_AP_KRW : PTE2_AP_KR;
1406 l2prot |= (prot & VM_PROT_EXECUTE) ? PTE2_X : PTE2_NX;
1407 l1prot = ATTR_TO_L1(l2prot);
1409 l2attr = PTE2_ATTR_DEFAULT;
1410 l1attr = ATTR_TO_L1(l2attr);
1414 * Does the physical address range's size and alignment permit at
1415 * least one section mapping to be created?
1417 pte1_offset = start & PTE1_OFFSET;
1418 if ((end - start) - ((PTE1_SIZE - pte1_offset) & PTE1_OFFSET) >=
1421 * Increase the starting virtual address so that its alignment
1422 * does not preclude the use of section mappings.
1424 if ((va & PTE1_OFFSET) < pte1_offset)
1425 va = pte1_trunc(va) + pte1_offset;
1426 else if ((va & PTE1_OFFSET) > pte1_offset)
1427 va = pte1_roundup(va) + pte1_offset;
1430 while (start < end) {
1431 if ((start & PTE1_OFFSET) == 0 && end - start >= PTE1_SIZE) {
1432 KASSERT((va & PTE1_OFFSET) == 0,
1433 ("%s: misaligned va %#x", __func__, va));
1434 npte1 = PTE1_KERN(start, l1prot, l1attr);
1435 pmap_kenter_pte1(va, npte1);
1439 pmap_kenter_prot_attr(va, start, l2prot, l2attr);
1444 tlb_flush_range(sva, va - sva);
1450 * Make a temporary mapping for a physical address.
1451 * This is only intended to be used for panic dumps.
1454 pmap_kenter_temporary(vm_paddr_t pa, int i)
1458 /* QQQ: 'i' should be less or equal to MAXDUMPPGS. */
1460 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
1461 pmap_kenter(va, pa);
1462 tlb_flush_local(va);
1463 return ((void *)crashdumpmap);
1467 /*************************************
1469 * TLB & cache maintenance routines.
1471 *************************************/
1474 * We inline these within pmap.c for speed.
1477 pmap_tlb_flush(pmap_t pmap, vm_offset_t va)
1480 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1485 pmap_tlb_flush_range(pmap_t pmap, vm_offset_t sva, vm_size_t size)
1488 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1489 tlb_flush_range(sva, size);
1493 * Abuse the pte2 nodes for unmapped kva to thread a kva freelist through.
1495 * - Must deal with pages in order to ensure that none of the PTE2_* bits
1496 * are ever set, PTE2_V in particular.
1497 * - Assumes we can write to pte2s without pte2_store() atomic ops.
1498 * - Assumes nothing will ever test these addresses for 0 to indicate
1499 * no mapping instead of correctly checking PTE2_V.
1500 * - Assumes a vm_offset_t will fit in a pte2 (true for arm).
1501 * Because PTE2_V is never set, there can be no mappings to invalidate.
1504 pmap_pte2list_alloc(vm_offset_t *head)
1511 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
1512 pte2p = pt2map_entry(va);
1515 panic("%s: va with PTE2_V set!", __func__);
1521 pmap_pte2list_free(vm_offset_t *head, vm_offset_t va)
1526 panic("%s: freeing va with PTE2_V set!", __func__);
1527 pte2p = pt2map_entry(va);
1528 *pte2p = *head; /* virtual! PTE2_V is 0 though */
1533 pmap_pte2list_init(vm_offset_t *head, void *base, int npages)
1539 for (i = npages - 1; i >= 0; i--) {
1540 va = (vm_offset_t)base + i * PAGE_SIZE;
1541 pmap_pte2list_free(head, va);
1545 /*****************************************************************************
1547 * PMAP third and final stage initialization.
1549 * After pmap_init() is called, PMAP subsystem is fully initialized.
1551 *****************************************************************************/
1553 SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
1555 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
1556 "Max number of PV entries");
1557 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
1558 "Page share factor per proc");
1560 static u_long nkpt2pg = NKPT2PG;
1561 SYSCTL_ULONG(_vm_pmap, OID_AUTO, nkpt2pg, CTLFLAG_RD,
1562 &nkpt2pg, 0, "Pre-allocated pages for kernel PT2s");
1564 static int sp_enabled = 1;
1565 SYSCTL_INT(_vm_pmap, OID_AUTO, sp_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
1566 &sp_enabled, 0, "Are large page mappings enabled?");
1569 pmap_ps_enabled(pmap_t pmap __unused)
1572 return (sp_enabled != 0);
1575 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pte1, CTLFLAG_RD, 0,
1576 "1MB page mapping counters");
1578 static u_long pmap_pte1_demotions;
1579 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, demotions, CTLFLAG_RD,
1580 &pmap_pte1_demotions, 0, "1MB page demotions");
1582 static u_long pmap_pte1_mappings;
1583 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, mappings, CTLFLAG_RD,
1584 &pmap_pte1_mappings, 0, "1MB page mappings");
1586 static u_long pmap_pte1_p_failures;
1587 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, p_failures, CTLFLAG_RD,
1588 &pmap_pte1_p_failures, 0, "1MB page promotion failures");
1590 static u_long pmap_pte1_promotions;
1591 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, promotions, CTLFLAG_RD,
1592 &pmap_pte1_promotions, 0, "1MB page promotions");
1594 static u_long pmap_pte1_kern_demotions;
1595 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, kern_demotions, CTLFLAG_RD,
1596 &pmap_pte1_kern_demotions, 0, "1MB page kernel demotions");
1598 static u_long pmap_pte1_kern_promotions;
1599 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, kern_promotions, CTLFLAG_RD,
1600 &pmap_pte1_kern_promotions, 0, "1MB page kernel promotions");
1602 static __inline ttb_entry_t
1603 pmap_ttb_get(pmap_t pmap)
1606 return (vtophys(pmap->pm_pt1) | ttb_flags);
1610 * Initialize a vm_page's machine-dependent fields.
1613 * 1. Pages for L2 page tables are always not managed. So, pv_list and
1614 * pt2_wirecount can share same physical space. However, proper
1615 * initialization on a page alloc for page tables and reinitialization
1616 * on the page free must be ensured.
1619 pmap_page_init(vm_page_t m)
1622 TAILQ_INIT(&m->md.pv_list);
1623 pt2_wirecount_init(m);
1624 m->md.pat_mode = VM_MEMATTR_DEFAULT;
1628 * Virtualization for faster way how to zero whole page.
1630 static __inline void
1631 pagezero(void *page)
1634 bzero(page, PAGE_SIZE);
1638 * Zero L2 page table page.
1639 * Use same KVA as in pmap_zero_page().
1641 static __inline vm_paddr_t
1642 pmap_pt2pg_zero(vm_page_t m)
1644 pt2_entry_t *cmap2_pte2p;
1648 pa = VM_PAGE_TO_PHYS(m);
1651 * XXX: For now, we map whole page even if it's already zero,
1652 * to sync it even if the sync is only DSB.
1656 cmap2_pte2p = pc->pc_cmap2_pte2p;
1657 mtx_lock(&pc->pc_cmap_lock);
1658 if (pte2_load(cmap2_pte2p) != 0)
1659 panic("%s: CMAP2 busy", __func__);
1660 pte2_store(cmap2_pte2p, PTE2_KERN_NG(pa, PTE2_AP_KRW,
1661 vm_page_pte2_attr(m)));
1662 /* Even VM_ALLOC_ZERO request is only advisory. */
1663 if ((m->flags & PG_ZERO) == 0)
1664 pagezero(pc->pc_cmap2_addr);
1665 pte2_sync_range((pt2_entry_t *)pc->pc_cmap2_addr, PAGE_SIZE);
1666 pte2_clear(cmap2_pte2p);
1667 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
1670 * Unpin the thread before releasing the lock. Otherwise the thread
1671 * could be rescheduled while still bound to the current CPU, only
1672 * to unpin itself immediately upon resuming execution.
1675 mtx_unlock(&pc->pc_cmap_lock);
1681 * Init just allocated page as L2 page table(s) holder
1682 * and return its physical address.
1684 static __inline vm_paddr_t
1685 pmap_pt2pg_init(pmap_t pmap, vm_offset_t va, vm_page_t m)
1690 /* Check page attributes. */
1691 if (m->md.pat_mode != pt_memattr)
1692 pmap_page_set_memattr(m, pt_memattr);
1694 /* Zero page and init wire counts. */
1695 pa = pmap_pt2pg_zero(m);
1696 pt2_wirecount_init(m);
1699 * Map page to PT2MAP address space for given pmap.
1700 * Note that PT2MAP space is shared with all pmaps.
1702 if (pmap == kernel_pmap)
1703 pmap_kenter_pt2tab(va, PTE2_KPT(pa));
1705 pte2p = pmap_pt2tab_entry(pmap, va);
1706 pt2tab_store(pte2p, PTE2_KPT_NG(pa));
1713 * Initialize the pmap module.
1714 * Called by vm_init, to initialize any structures that the pmap
1715 * system needs to map virtual memory.
1721 pt2_entry_t *pte2p, pte2;
1722 u_int i, pte1_idx, pv_npg;
1724 PDEBUG(1, printf("%s: phys_start = %#x\n", __func__, PHYSADDR));
1727 * Initialize the vm page array entries for kernel pmap's
1728 * L2 page table pages allocated in advance.
1730 pte1_idx = pte1_index(KERNBASE - PT2MAP_SIZE);
1731 pte2p = kern_pt2tab_entry(KERNBASE - PT2MAP_SIZE);
1732 for (i = 0; i < nkpt2pg + NPG_IN_PT2TAB; i++, pte2p++) {
1736 pte2 = pte2_load(pte2p);
1737 KASSERT(pte2_is_valid(pte2), ("%s: no valid entry", __func__));
1740 m = PHYS_TO_VM_PAGE(pa);
1741 KASSERT(m >= vm_page_array &&
1742 m < &vm_page_array[vm_page_array_size],
1743 ("%s: L2 page table page is out of range", __func__));
1745 m->pindex = pte1_idx;
1747 pte1_idx += NPT2_IN_PG;
1751 * Initialize the address space (zone) for the pv entries. Set a
1752 * high water mark so that the system can recover from excessive
1753 * numbers of pv entries.
1755 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1756 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1757 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1758 pv_entry_max = roundup(pv_entry_max, _NPCPV);
1759 pv_entry_high_water = 9 * (pv_entry_max / 10);
1762 * Are large page mappings enabled?
1764 TUNABLE_INT_FETCH("vm.pmap.sp_enabled", &sp_enabled);
1766 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1767 ("%s: can't assign to pagesizes[1]", __func__));
1768 pagesizes[1] = PTE1_SIZE;
1772 * Calculate the size of the pv head table for sections.
1773 * Handle the possibility that "vm_phys_segs[...].end" is zero.
1774 * Note that the table is only for sections which could be promoted.
1776 first_managed_pa = pte1_trunc(vm_phys_segs[0].start);
1777 pv_npg = (pte1_trunc(vm_phys_segs[vm_phys_nsegs - 1].end - PAGE_SIZE)
1778 - first_managed_pa) / PTE1_SIZE + 1;
1781 * Allocate memory for the pv head table for sections.
1783 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1785 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1786 for (i = 0; i < pv_npg; i++)
1787 TAILQ_INIT(&pv_table[i].pv_list);
1789 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
1790 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
1791 if (pv_chunkbase == NULL)
1792 panic("%s: not enough kvm for pv chunks", __func__);
1793 pmap_pte2list_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
1797 * Add a list of wired pages to the kva
1798 * this routine is only used for temporary
1799 * kernel mappings that do not need to have
1800 * page modification or references recorded.
1801 * Note that old mappings are simply written
1802 * over. The page *must* be wired.
1803 * Note: SMP coherent. Uses a ranged shootdown IPI.
1806 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1809 pt2_entry_t *epte2p, *pte2p, pte2;
1814 pte2p = pt2map_entry(sva);
1815 epte2p = pte2p + count;
1816 while (pte2p < epte2p) {
1818 pa = VM_PAGE_TO_PHYS(m);
1819 pte2 = pte2_load(pte2p);
1820 if ((pte2_pa(pte2) != pa) ||
1821 (pte2_attr(pte2) != vm_page_pte2_attr(m))) {
1823 pte2_store(pte2p, PTE2_KERN(pa, PTE2_AP_KRW,
1824 vm_page_pte2_attr(m)));
1828 if (__predict_false(anychanged))
1829 tlb_flush_range(sva, count * PAGE_SIZE);
1833 * This routine tears out page mappings from the
1834 * kernel -- it is meant only for temporary mappings.
1835 * Note: SMP coherent. Uses a ranged shootdown IPI.
1838 pmap_qremove(vm_offset_t sva, int count)
1843 while (count-- > 0) {
1847 tlb_flush_range(sva, va - sva);
1851 * Are we current address space or kernel?
1854 pmap_is_current(pmap_t pmap)
1857 return (pmap == kernel_pmap ||
1858 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace)));
1862 * If the given pmap is not the current or kernel pmap, the returned
1863 * pte2 must be released by passing it to pmap_pte2_release().
1865 static pt2_entry_t *
1866 pmap_pte2(pmap_t pmap, vm_offset_t va)
1869 vm_paddr_t pt2pg_pa;
1871 pte1 = pte1_load(pmap_pte1(pmap, va));
1872 if (pte1_is_section(pte1))
1873 panic("%s: attempt to map PTE1", __func__);
1874 if (pte1_is_link(pte1)) {
1875 /* Are we current address space or kernel? */
1876 if (pmap_is_current(pmap))
1877 return (pt2map_entry(va));
1878 /* Note that L2 page table size is not equal to PAGE_SIZE. */
1879 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
1880 mtx_lock(&PMAP2mutex);
1881 if (pte2_pa(pte2_load(PMAP2)) != pt2pg_pa) {
1882 pte2_store(PMAP2, PTE2_KPT(pt2pg_pa));
1883 tlb_flush((vm_offset_t)PADDR2);
1885 return (PADDR2 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
1891 * Releases a pte2 that was obtained from pmap_pte2().
1892 * Be prepared for the pte2p being NULL.
1894 static __inline void
1895 pmap_pte2_release(pt2_entry_t *pte2p)
1898 if ((pt2_entry_t *)(trunc_page((vm_offset_t)pte2p)) == PADDR2) {
1899 mtx_unlock(&PMAP2mutex);
1904 * Super fast pmap_pte2 routine best used when scanning
1905 * the pv lists. This eliminates many coarse-grained
1906 * invltlb calls. Note that many of the pv list
1907 * scans are across different pmaps. It is very wasteful
1908 * to do an entire tlb flush for checking a single mapping.
1910 * If the given pmap is not the current pmap, pvh_global_lock
1911 * must be held and curthread pinned to a CPU.
1913 static pt2_entry_t *
1914 pmap_pte2_quick(pmap_t pmap, vm_offset_t va)
1917 vm_paddr_t pt2pg_pa;
1919 pte1 = pte1_load(pmap_pte1(pmap, va));
1920 if (pte1_is_section(pte1))
1921 panic("%s: attempt to map PTE1", __func__);
1922 if (pte1_is_link(pte1)) {
1923 /* Are we current address space or kernel? */
1924 if (pmap_is_current(pmap))
1925 return (pt2map_entry(va));
1926 rw_assert(&pvh_global_lock, RA_WLOCKED);
1927 KASSERT(curthread->td_pinned > 0,
1928 ("%s: curthread not pinned", __func__));
1929 /* Note that L2 page table size is not equal to PAGE_SIZE. */
1930 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
1931 if (pte2_pa(pte2_load(PMAP1)) != pt2pg_pa) {
1932 pte2_store(PMAP1, PTE2_KPT(pt2pg_pa));
1934 PMAP1cpu = PCPU_GET(cpuid);
1936 tlb_flush_local((vm_offset_t)PADDR1);
1940 if (PMAP1cpu != PCPU_GET(cpuid)) {
1941 PMAP1cpu = PCPU_GET(cpuid);
1942 tlb_flush_local((vm_offset_t)PADDR1);
1947 return (PADDR1 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
1953 * Routine: pmap_extract
1955 * Extract the physical page address associated
1956 * with the given map/virtual_address pair.
1959 pmap_extract(pmap_t pmap, vm_offset_t va)
1966 pte1 = pte1_load(pmap_pte1(pmap, va));
1967 if (pte1_is_section(pte1))
1968 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1969 else if (pte1_is_link(pte1)) {
1970 pte2p = pmap_pte2(pmap, va);
1971 pa = pte2_pa(pte2_load(pte2p)) | (va & PTE2_OFFSET);
1972 pmap_pte2_release(pte2p);
1980 * Routine: pmap_extract_and_hold
1982 * Atomically extract and hold the physical page
1983 * with the given pmap and virtual address pair
1984 * if that mapping permits the given protection.
1987 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1989 vm_paddr_t pa, lockpa;
1991 pt2_entry_t pte2, *pte2p;
1998 pte1 = pte1_load(pmap_pte1(pmap, va));
1999 if (pte1_is_section(pte1)) {
2000 if (!(pte1 & PTE1_RO) || !(prot & VM_PROT_WRITE)) {
2001 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
2002 if (vm_page_pa_tryrelock(pmap, pa, &lockpa))
2004 m = PHYS_TO_VM_PAGE(pa);
2007 } else if (pte1_is_link(pte1)) {
2008 pte2p = pmap_pte2(pmap, va);
2009 pte2 = pte2_load(pte2p);
2010 pmap_pte2_release(pte2p);
2011 if (pte2_is_valid(pte2) &&
2012 (!(pte2 & PTE2_RO) || !(prot & VM_PROT_WRITE))) {
2014 if (vm_page_pa_tryrelock(pmap, pa, &lockpa))
2016 m = PHYS_TO_VM_PAGE(pa);
2020 PA_UNLOCK_COND(lockpa);
2026 * Grow the number of kernel L2 page table entries, if needed.
2029 pmap_growkernel(vm_offset_t addr)
2032 vm_paddr_t pt2pg_pa, pt2_pa;
2036 PDEBUG(1, printf("%s: addr = %#x\n", __func__, addr));
2038 * All the time kernel_vm_end is first KVA for which underlying
2039 * L2 page table is either not allocated or linked from L1 page table
2040 * (not considering sections). Except for two possible cases:
2042 * (1) in the very beginning as long as pmap_growkernel() was
2043 * not called, it could be first unused KVA (which is not
2044 * rounded up to PTE1_SIZE),
2046 * (2) when all KVA space is mapped and vm_map_max(kernel_map)
2047 * address is not rounded up to PTE1_SIZE. (For example,
2048 * it could be 0xFFFFFFFF.)
2050 kernel_vm_end = pte1_roundup(kernel_vm_end);
2051 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2052 addr = roundup2(addr, PTE1_SIZE);
2053 if (addr - 1 >= vm_map_max(kernel_map))
2054 addr = vm_map_max(kernel_map);
2055 while (kernel_vm_end < addr) {
2056 pte1 = pte1_load(kern_pte1(kernel_vm_end));
2057 if (pte1_is_valid(pte1)) {
2058 kernel_vm_end += PTE1_SIZE;
2059 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2060 kernel_vm_end = vm_map_max(kernel_map);
2067 * kernel_vm_end_new is used in pmap_pinit() when kernel
2068 * mappings are entered to new pmap all at once to avoid race
2069 * between pmap_kenter_pte1() and kernel_vm_end increase.
2070 * The same aplies to pmap_kenter_pt2tab().
2072 kernel_vm_end_new = kernel_vm_end + PTE1_SIZE;
2074 pte2 = pt2tab_load(kern_pt2tab_entry(kernel_vm_end));
2075 if (!pte2_is_valid(pte2)) {
2077 * Install new PT2s page into kernel PT2TAB.
2079 m = vm_page_alloc(NULL,
2080 pte1_index(kernel_vm_end) & ~PT2PG_MASK,
2081 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2082 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2084 panic("%s: no memory to grow kernel", __func__);
2086 * QQQ: To link all new L2 page tables from L1 page
2087 * table now and so pmap_kenter_pte1() them
2088 * at once together with pmap_kenter_pt2tab()
2089 * could be nice speed up. However,
2090 * pmap_growkernel() does not happen so often...
2091 * QQQ: The other TTBR is another option.
2093 pt2pg_pa = pmap_pt2pg_init(kernel_pmap, kernel_vm_end,
2096 pt2pg_pa = pte2_pa(pte2);
2098 pt2_pa = page_pt2pa(pt2pg_pa, pte1_index(kernel_vm_end));
2099 pmap_kenter_pte1(kernel_vm_end, PTE1_LINK(pt2_pa));
2101 kernel_vm_end = kernel_vm_end_new;
2102 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2103 kernel_vm_end = vm_map_max(kernel_map);
2110 kvm_size(SYSCTL_HANDLER_ARGS)
2112 unsigned long ksize = vm_max_kernel_address - KERNBASE;
2114 return (sysctl_handle_long(oidp, &ksize, 0, req));
2116 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2117 0, 0, kvm_size, "IU", "Size of KVM");
2120 kvm_free(SYSCTL_HANDLER_ARGS)
2122 unsigned long kfree = vm_max_kernel_address - kernel_vm_end;
2124 return (sysctl_handle_long(oidp, &kfree, 0, req));
2126 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2127 0, 0, kvm_free, "IU", "Amount of KVM free");
2129 /***********************************************
2131 * Pmap allocation/deallocation routines.
2133 ***********************************************/
2136 * Initialize the pmap for the swapper process.
2139 pmap_pinit0(pmap_t pmap)
2141 PDEBUG(1, printf("%s: pmap = %p\n", __func__, pmap));
2143 PMAP_LOCK_INIT(pmap);
2146 * Kernel page table directory and pmap stuff around is already
2147 * initialized, we are using it right now and here. So, finish
2148 * only PMAP structures initialization for process0 ...
2150 * Since the L1 page table and PT2TAB is shared with the kernel pmap,
2151 * which is already included in the list "allpmaps", this pmap does
2152 * not need to be inserted into that list.
2154 pmap->pm_pt1 = kern_pt1;
2155 pmap->pm_pt2tab = kern_pt2tab;
2156 CPU_ZERO(&pmap->pm_active);
2157 PCPU_SET(curpmap, pmap);
2158 TAILQ_INIT(&pmap->pm_pvchunk);
2159 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2160 CPU_SET(0, &pmap->pm_active);
2163 static __inline void
2164 pte1_copy_nosync(pt1_entry_t *spte1p, pt1_entry_t *dpte1p, vm_offset_t sva,
2169 idx = pte1_index(sva);
2170 count = (pte1_index(eva) - idx + 1) * sizeof(pt1_entry_t);
2171 bcopy(spte1p + idx, dpte1p + idx, count);
2174 static __inline void
2175 pt2tab_copy_nosync(pt2_entry_t *spte2p, pt2_entry_t *dpte2p, vm_offset_t sva,
2180 idx = pt2tab_index(sva);
2181 count = (pt2tab_index(eva) - idx + 1) * sizeof(pt2_entry_t);
2182 bcopy(spte2p + idx, dpte2p + idx, count);
2186 * Initialize a preallocated and zeroed pmap structure,
2187 * such as one in a vmspace structure.
2190 pmap_pinit(pmap_t pmap)
2194 vm_paddr_t pa, pt2tab_pa;
2197 PDEBUG(6, printf("%s: pmap = %p, pm_pt1 = %p\n", __func__, pmap,
2201 * No need to allocate L2 page table space yet but we do need
2202 * a valid L1 page table and PT2TAB table.
2204 * Install shared kernel mappings to these tables. It's a little
2205 * tricky as some parts of KVA are reserved for vectors, devices,
2206 * and whatever else. These parts are supposed to be above
2207 * vm_max_kernel_address. Thus two regions should be installed:
2209 * (1) <KERNBASE, kernel_vm_end),
2210 * (2) <vm_max_kernel_address, 0xFFFFFFFF>.
2212 * QQQ: The second region should be stable enough to be installed
2213 * only once in time when the tables are allocated.
2214 * QQQ: Maybe copy of both regions at once could be faster ...
2215 * QQQ: Maybe the other TTBR is an option.
2217 * Finally, install own PT2TAB table to these tables.
2220 if (pmap->pm_pt1 == NULL) {
2221 pmap->pm_pt1 = (pt1_entry_t *)kmem_alloc_contig(NB_IN_PT1,
2222 M_NOWAIT | M_ZERO, 0, -1UL, NB_IN_PT1, 0, pt_memattr);
2223 if (pmap->pm_pt1 == NULL)
2226 if (pmap->pm_pt2tab == NULL) {
2228 * QQQ: (1) PT2TAB must be contiguous. If PT2TAB is one page
2229 * only, what should be the only size for 32 bit systems,
2230 * then we could allocate it with vm_page_alloc() and all
2231 * the stuff needed as other L2 page table pages.
2232 * (2) Note that a process PT2TAB is special L2 page table
2233 * page. Its mapping in kernel_arena is permanent and can
2234 * be used no matter which process is current. Its mapping
2235 * in PT2MAP can be used only for current process.
2237 pmap->pm_pt2tab = (pt2_entry_t *)kmem_alloc_attr(NB_IN_PT2TAB,
2238 M_NOWAIT | M_ZERO, 0, -1UL, pt_memattr);
2239 if (pmap->pm_pt2tab == NULL) {
2241 * QQQ: As struct pmap is allocated from UMA with
2242 * UMA_ZONE_NOFREE flag, it's important to leave
2243 * no allocation in pmap if initialization failed.
2245 kmem_free((vm_offset_t)pmap->pm_pt1, NB_IN_PT1);
2246 pmap->pm_pt1 = NULL;
2250 * QQQ: Each L2 page table page vm_page_t has pindex set to
2251 * pte1 index of virtual address mapped by this page.
2252 * It's not valid for non kernel PT2TABs themselves.
2253 * The pindex of these pages can not be altered because
2254 * of the way how they are allocated now. However, it
2255 * should not be a problem.
2259 mtx_lock_spin(&allpmaps_lock);
2261 * To avoid race with pmap_kenter_pte1() and pmap_kenter_pt2tab(),
2262 * kernel_vm_end_new is used here instead of kernel_vm_end.
2264 pte1_copy_nosync(kern_pt1, pmap->pm_pt1, KERNBASE,
2265 kernel_vm_end_new - 1);
2266 pte1_copy_nosync(kern_pt1, pmap->pm_pt1, vm_max_kernel_address,
2268 pt2tab_copy_nosync(kern_pt2tab, pmap->pm_pt2tab, KERNBASE,
2269 kernel_vm_end_new - 1);
2270 pt2tab_copy_nosync(kern_pt2tab, pmap->pm_pt2tab, vm_max_kernel_address,
2272 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
2273 mtx_unlock_spin(&allpmaps_lock);
2276 * Store PT2MAP PT2 pages (a.k.a. PT2TAB) in PT2TAB itself.
2277 * I.e. self reference mapping. The PT2TAB is private, however mapped
2278 * into shared PT2MAP space, so the mapping should be not global.
2280 pt2tab_pa = vtophys(pmap->pm_pt2tab);
2281 pte2p = pmap_pt2tab_entry(pmap, (vm_offset_t)PT2MAP);
2282 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE) {
2283 pt2tab_store(pte2p++, PTE2_KPT_NG(pa));
2286 /* Insert PT2MAP PT2s into pmap PT1. */
2287 pte1p = pmap_pte1(pmap, (vm_offset_t)PT2MAP);
2288 for (pa = pt2tab_pa, i = 0; i < NPT2_IN_PT2TAB; i++, pa += NB_IN_PT2) {
2289 pte1_store(pte1p++, PTE1_LINK(pa));
2293 * Now synchronize new mapping which was made above.
2295 pte1_sync_range(pmap->pm_pt1, NB_IN_PT1);
2296 pte2_sync_range(pmap->pm_pt2tab, NB_IN_PT2TAB);
2298 CPU_ZERO(&pmap->pm_active);
2299 TAILQ_INIT(&pmap->pm_pvchunk);
2300 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2307 pt2tab_user_is_empty(pt2_entry_t *tab)
2311 end = pt2tab_index(VM_MAXUSER_ADDRESS);
2312 for (i = 0; i < end; i++)
2313 if (tab[i] != 0) return (FALSE);
2318 * Release any resources held by the given physical map.
2319 * Called when a pmap initialized by pmap_pinit is being released.
2320 * Should only be called if the map contains no valid mappings.
2323 pmap_release(pmap_t pmap)
2326 vm_offset_t start, end;
2328 KASSERT(pmap->pm_stats.resident_count == 0,
2329 ("%s: pmap resident count %ld != 0", __func__,
2330 pmap->pm_stats.resident_count));
2331 KASSERT(pt2tab_user_is_empty(pmap->pm_pt2tab),
2332 ("%s: has allocated user PT2(s)", __func__));
2333 KASSERT(CPU_EMPTY(&pmap->pm_active),
2334 ("%s: pmap %p is active on some CPU(s)", __func__, pmap));
2336 mtx_lock_spin(&allpmaps_lock);
2337 LIST_REMOVE(pmap, pm_list);
2338 mtx_unlock_spin(&allpmaps_lock);
2341 start = pte1_index(KERNBASE) * sizeof(pt1_entry_t);
2342 end = (pte1_index(0xFFFFFFFF) + 1) * sizeof(pt1_entry_t);
2343 bzero((char *)pmap->pm_pt1 + start, end - start);
2345 start = pt2tab_index(KERNBASE) * sizeof(pt2_entry_t);
2346 end = (pt2tab_index(0xFFFFFFFF) + 1) * sizeof(pt2_entry_t);
2347 bzero((char *)pmap->pm_pt2tab + start, end - start);
2350 * We are leaving PT1 and PT2TAB allocated on released pmap,
2351 * so hopefully UMA vmspace_zone will always be inited with
2352 * UMA_ZONE_NOFREE flag.
2356 /*********************************************************
2358 * L2 table pages and their pages management routines.
2360 *********************************************************/
2363 * Virtual interface for L2 page table wire counting.
2365 * Each L2 page table in a page has own counter which counts a number of
2366 * valid mappings in a table. Global page counter counts mappings in all
2367 * tables in a page plus a single itself mapping in PT2TAB.
2369 * During a promotion we leave the associated L2 page table counter
2370 * untouched, so the table (strictly speaking a page which holds it)
2371 * is never freed if promoted.
2373 * If a page m->wire_count == 1 then no valid mappings exist in any L2 page
2374 * table in the page and the page itself is only mapped in PT2TAB.
2377 static __inline void
2378 pt2_wirecount_init(vm_page_t m)
2383 * Note: A page m is allocated with VM_ALLOC_WIRED flag and
2384 * m->wire_count should be already set correctly.
2385 * So, there is no need to set it again herein.
2387 for (i = 0; i < NPT2_IN_PG; i++)
2388 m->md.pt2_wirecount[i] = 0;
2391 static __inline void
2392 pt2_wirecount_inc(vm_page_t m, uint32_t pte1_idx)
2396 * Note: A just modificated pte2 (i.e. already allocated)
2397 * is acquiring one extra reference which must be
2398 * explicitly cleared. It influences the KASSERTs herein.
2399 * All L2 page tables in a page always belong to the same
2400 * pmap, so we allow only one extra reference for the page.
2402 KASSERT(m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] < (NPTE2_IN_PT2 + 1),
2403 ("%s: PT2 is overflowing ...", __func__));
2404 KASSERT(m->wire_count <= (NPTE2_IN_PG + 1),
2405 ("%s: PT2PG is overflowing ...", __func__));
2408 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]++;
2411 static __inline void
2412 pt2_wirecount_dec(vm_page_t m, uint32_t pte1_idx)
2415 KASSERT(m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] != 0,
2416 ("%s: PT2 is underflowing ...", __func__));
2417 KASSERT(m->wire_count > 1,
2418 ("%s: PT2PG is underflowing ...", __func__));
2421 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]--;
2424 static __inline void
2425 pt2_wirecount_set(vm_page_t m, uint32_t pte1_idx, uint16_t count)
2428 KASSERT(count <= NPTE2_IN_PT2,
2429 ("%s: invalid count %u", __func__, count));
2430 KASSERT(m->wire_count > m->md.pt2_wirecount[pte1_idx & PT2PG_MASK],
2431 ("%s: PT2PG corrupting (%u, %u) ...", __func__, m->wire_count,
2432 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]));
2434 m->wire_count -= m->md.pt2_wirecount[pte1_idx & PT2PG_MASK];
2435 m->wire_count += count;
2436 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] = count;
2438 KASSERT(m->wire_count <= (NPTE2_IN_PG + 1),
2439 ("%s: PT2PG is overflowed (%u) ...", __func__, m->wire_count));
2442 static __inline uint32_t
2443 pt2_wirecount_get(vm_page_t m, uint32_t pte1_idx)
2446 return (m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]);
2449 static __inline boolean_t
2450 pt2_is_empty(vm_page_t m, vm_offset_t va)
2453 return (m->md.pt2_wirecount[pte1_index(va) & PT2PG_MASK] == 0);
2456 static __inline boolean_t
2457 pt2_is_full(vm_page_t m, vm_offset_t va)
2460 return (m->md.pt2_wirecount[pte1_index(va) & PT2PG_MASK] ==
2464 static __inline boolean_t
2465 pt2pg_is_empty(vm_page_t m)
2468 return (m->wire_count == 1);
2472 * This routine is called if the L2 page table
2473 * is not mapped correctly.
2476 _pmap_allocpte2(pmap_t pmap, vm_offset_t va, u_int flags)
2482 vm_paddr_t pt2pg_pa, pt2_pa;
2484 pte1_idx = pte1_index(va);
2485 pte1p = pmap->pm_pt1 + pte1_idx;
2487 KASSERT(pte1_load(pte1p) == 0,
2488 ("%s: pm_pt1[%#x] is not zero: %#x", __func__, pte1_idx,
2491 pte2 = pt2tab_load(pmap_pt2tab_entry(pmap, va));
2492 if (!pte2_is_valid(pte2)) {
2494 * Install new PT2s page into pmap PT2TAB.
2496 m = vm_page_alloc(NULL, pte1_idx & ~PT2PG_MASK,
2497 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2499 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2501 rw_wunlock(&pvh_global_lock);
2503 rw_wlock(&pvh_global_lock);
2508 * Indicate the need to retry. While waiting,
2509 * the L2 page table page may have been allocated.
2513 pmap->pm_stats.resident_count++;
2514 pt2pg_pa = pmap_pt2pg_init(pmap, va, m);
2516 pt2pg_pa = pte2_pa(pte2);
2517 m = PHYS_TO_VM_PAGE(pt2pg_pa);
2520 pt2_wirecount_inc(m, pte1_idx);
2521 pt2_pa = page_pt2pa(pt2pg_pa, pte1_idx);
2522 pte1_store(pte1p, PTE1_LINK(pt2_pa));
2528 pmap_allocpte2(pmap_t pmap, vm_offset_t va, u_int flags)
2531 pt1_entry_t *pte1p, pte1;
2534 pte1_idx = pte1_index(va);
2536 pte1p = pmap->pm_pt1 + pte1_idx;
2537 pte1 = pte1_load(pte1p);
2540 * This supports switching from a 1MB page to a
2543 if (pte1_is_section(pte1)) {
2544 (void)pmap_demote_pte1(pmap, pte1p, va);
2546 * Reload pte1 after demotion.
2548 * Note: Demotion can even fail as either PT2 is not find for
2549 * the virtual address or PT2PG can not be allocated.
2551 pte1 = pte1_load(pte1p);
2555 * If the L2 page table page is mapped, we just increment the
2556 * hold count, and activate it.
2558 if (pte1_is_link(pte1)) {
2559 m = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
2560 pt2_wirecount_inc(m, pte1_idx);
2563 * Here if the PT2 isn't mapped, or if it has
2566 m = _pmap_allocpte2(pmap, va, flags);
2567 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2575 * Schedule the specified unused L2 page table page to be freed. Specifically,
2576 * add the page to the specified list of pages that will be released to the
2577 * physical memory manager after the TLB has been updated.
2579 static __inline void
2580 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free)
2584 * Put page on a list so that it is released after
2585 * *ALL* TLB shootdown is done
2588 pmap_zero_page_check(m);
2590 m->flags |= PG_ZERO;
2591 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2595 * Unwire L2 page tables page.
2598 pmap_unwire_pt2pg(pmap_t pmap, vm_offset_t va, vm_page_t m)
2600 pt1_entry_t *pte1p, opte1 __unused;
2604 KASSERT(pt2pg_is_empty(m),
2605 ("%s: pmap %p PT2PG %p wired", __func__, pmap, m));
2608 * Unmap all L2 page tables in the page from L1 page table.
2610 * QQQ: Individual L2 page tables (except the last one) can be unmapped
2611 * earlier. However, we are doing that this way.
2613 KASSERT(m->pindex == (pte1_index(va) & ~PT2PG_MASK),
2614 ("%s: pmap %p va %#x PT2PG %p bad index", __func__, pmap, va, m));
2615 pte1p = pmap->pm_pt1 + m->pindex;
2616 for (i = 0; i < NPT2_IN_PG; i++, pte1p++) {
2617 KASSERT(m->md.pt2_wirecount[i] == 0,
2618 ("%s: pmap %p PT2 %u (PG %p) wired", __func__, pmap, i, m));
2619 opte1 = pte1_load(pte1p);
2620 if (pte1_is_link(opte1)) {
2623 * Flush intermediate TLB cache.
2625 pmap_tlb_flush(pmap, (m->pindex + i) << PTE1_SHIFT);
2629 KASSERT((opte1 == 0) || pte1_is_section(opte1),
2630 ("%s: pmap %p va %#x bad pte1 %x at %u", __func__,
2631 pmap, va, opte1, i));
2636 * Unmap the page from PT2TAB.
2638 pte2p = pmap_pt2tab_entry(pmap, va);
2639 (void)pt2tab_load_clear(pte2p);
2640 pmap_tlb_flush(pmap, pt2map_pt2pg(va));
2643 pmap->pm_stats.resident_count--;
2646 * This barrier is so that the ordinary store unmapping
2647 * the L2 page table page is globally performed before TLB shoot-
2655 * Decrements a L2 page table page's wire count, which is used to record the
2656 * number of valid page table entries within the page. If the wire count
2657 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2658 * page table page was unmapped and FALSE otherwise.
2660 static __inline boolean_t
2661 pmap_unwire_pt2(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2663 pt2_wirecount_dec(m, pte1_index(va));
2664 if (pt2pg_is_empty(m)) {
2666 * QQQ: Wire count is zero, so whole page should be zero and
2667 * we can set PG_ZERO flag to it.
2668 * Note that when promotion is enabled, it takes some
2669 * more efforts. See pmap_unwire_pt2_all() below.
2671 pmap_unwire_pt2pg(pmap, va, m);
2672 pmap_add_delayed_free_list(m, free);
2679 * Drop a L2 page table page's wire count at once, which is used to record
2680 * the number of valid L2 page table entries within the page. If the wire
2681 * count drops to zero, then the L2 page table page is unmapped.
2683 static __inline void
2684 pmap_unwire_pt2_all(pmap_t pmap, vm_offset_t va, vm_page_t m,
2685 struct spglist *free)
2687 u_int pte1_idx = pte1_index(va);
2689 KASSERT(m->pindex == (pte1_idx & ~PT2PG_MASK),
2690 ("%s: PT2 page's pindex is wrong", __func__));
2691 KASSERT(m->wire_count > pt2_wirecount_get(m, pte1_idx),
2692 ("%s: bad pt2 wire count %u > %u", __func__, m->wire_count,
2693 pt2_wirecount_get(m, pte1_idx)));
2696 * It's possible that the L2 page table was never used.
2697 * It happened in case that a section was created without promotion.
2699 if (pt2_is_full(m, va)) {
2700 pt2_wirecount_set(m, pte1_idx, 0);
2703 * QQQ: We clear L2 page table now, so when L2 page table page
2704 * is going to be freed, we can set it PG_ZERO flag ...
2705 * This function is called only on section mappings, so
2706 * hopefully it's not to big overload.
2708 * XXX: If pmap is current, existing PT2MAP mapping could be
2711 pmap_zero_page_area(m, page_pt2off(pte1_idx), NB_IN_PT2);
2715 KASSERT(pt2_is_empty(m, va), ("%s: PT2 is not empty (%u)",
2716 __func__, pt2_wirecount_get(m, pte1_idx)));
2718 if (pt2pg_is_empty(m)) {
2719 pmap_unwire_pt2pg(pmap, va, m);
2720 pmap_add_delayed_free_list(m, free);
2725 * After removing a L2 page table entry, this routine is used to
2726 * conditionally free the page, and manage the hold/wire counts.
2729 pmap_unuse_pt2(pmap_t pmap, vm_offset_t va, struct spglist *free)
2734 if (va >= VM_MAXUSER_ADDRESS)
2736 pte1 = pte1_load(pmap_pte1(pmap, va));
2737 mpte = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
2738 return (pmap_unwire_pt2(pmap, va, mpte, free));
2741 /*************************************
2743 * Page management routines.
2745 *************************************/
2747 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2748 CTASSERT(_NPCM == 11);
2749 CTASSERT(_NPCPV == 336);
2751 static __inline struct pv_chunk *
2752 pv_to_chunk(pv_entry_t pv)
2755 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2758 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2760 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2761 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2763 static const uint32_t pc_freemask[_NPCM] = {
2764 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2765 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2766 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2767 PC_FREE0_9, PC_FREE10
2770 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2771 "Current number of pv entries");
2774 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2776 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2777 "Current number of pv entry chunks");
2778 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2779 "Current number of pv entry chunks allocated");
2780 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2781 "Current number of pv entry chunks frees");
2782 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail,
2783 0, "Number of times tried to get a chunk page but failed.");
2785 static long pv_entry_frees, pv_entry_allocs;
2786 static int pv_entry_spare;
2788 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2789 "Current number of pv entry frees");
2790 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs,
2791 0, "Current number of pv entry allocs");
2792 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2793 "Current number of spare pv entries");
2797 * Is given page managed?
2799 static __inline bool
2800 is_managed(vm_paddr_t pa)
2804 m = PHYS_TO_VM_PAGE(pa);
2807 return ((m->oflags & VPO_UNMANAGED) == 0);
2810 static __inline bool
2811 pte1_is_managed(pt1_entry_t pte1)
2814 return (is_managed(pte1_pa(pte1)));
2817 static __inline bool
2818 pte2_is_managed(pt2_entry_t pte2)
2821 return (is_managed(pte2_pa(pte2)));
2825 * We are in a serious low memory condition. Resort to
2826 * drastic measures to free some pages so we can allocate
2827 * another pv entry chunk.
2830 pmap_pv_reclaim(pmap_t locked_pmap)
2833 struct pv_chunk *pc;
2834 struct md_page *pvh;
2837 pt2_entry_t *pte2p, tpte2;
2841 struct spglist free;
2843 int bit, field, freed;
2845 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2849 TAILQ_INIT(&newtail);
2850 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2851 SLIST_EMPTY(&free))) {
2852 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2853 if (pmap != pc->pc_pmap) {
2855 if (pmap != locked_pmap)
2859 /* Avoid deadlock and lock recursion. */
2860 if (pmap > locked_pmap)
2862 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2864 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2870 * Destroy every non-wired, 4 KB page mapping in the chunk.
2873 for (field = 0; field < _NPCM; field++) {
2874 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2875 inuse != 0; inuse &= ~(1UL << bit)) {
2876 bit = ffs(inuse) - 1;
2877 pv = &pc->pc_pventry[field * 32 + bit];
2879 pte1p = pmap_pte1(pmap, va);
2880 if (pte1_is_section(pte1_load(pte1p)))
2882 pte2p = pmap_pte2(pmap, va);
2883 tpte2 = pte2_load(pte2p);
2884 if ((tpte2 & PTE2_W) == 0)
2885 tpte2 = pte2_load_clear(pte2p);
2886 pmap_pte2_release(pte2p);
2887 if ((tpte2 & PTE2_W) != 0)
2890 ("pmap_pv_reclaim: pmap %p va %#x zero pte",
2892 pmap_tlb_flush(pmap, va);
2893 m = PHYS_TO_VM_PAGE(pte2_pa(tpte2));
2894 if (pte2_is_dirty(tpte2))
2896 if ((tpte2 & PTE2_A) != 0)
2897 vm_page_aflag_set(m, PGA_REFERENCED);
2898 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2899 if (TAILQ_EMPTY(&m->md.pv_list) &&
2900 (m->flags & PG_FICTITIOUS) == 0) {
2901 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2902 if (TAILQ_EMPTY(&pvh->pv_list)) {
2903 vm_page_aflag_clear(m,
2907 pc->pc_map[field] |= 1UL << bit;
2908 pmap_unuse_pt2(pmap, va, &free);
2913 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2916 /* Every freed mapping is for a 4 KB page. */
2917 pmap->pm_stats.resident_count -= freed;
2918 PV_STAT(pv_entry_frees += freed);
2919 PV_STAT(pv_entry_spare += freed);
2920 pv_entry_count -= freed;
2921 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2922 for (field = 0; field < _NPCM; field++)
2923 if (pc->pc_map[field] != pc_freemask[field]) {
2924 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2926 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2929 * One freed pv entry in locked_pmap is
2932 if (pmap == locked_pmap)
2936 if (field == _NPCM) {
2937 PV_STAT(pv_entry_spare -= _NPCPV);
2938 PV_STAT(pc_chunk_count--);
2939 PV_STAT(pc_chunk_frees++);
2940 /* Entire chunk is free; return it. */
2941 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2942 pmap_qremove((vm_offset_t)pc, 1);
2943 pmap_pte2list_free(&pv_vafree, (vm_offset_t)pc);
2948 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2950 if (pmap != locked_pmap)
2953 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2954 m_pc = SLIST_FIRST(&free);
2955 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2956 /* Recycle a freed page table page. */
2957 m_pc->wire_count = 1;
2960 vm_page_free_pages_toq(&free, false);
2965 free_pv_chunk(struct pv_chunk *pc)
2969 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2970 PV_STAT(pv_entry_spare -= _NPCPV);
2971 PV_STAT(pc_chunk_count--);
2972 PV_STAT(pc_chunk_frees++);
2973 /* entire chunk is free, return it */
2974 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2975 pmap_qremove((vm_offset_t)pc, 1);
2976 vm_page_unwire_noq(m);
2978 pmap_pte2list_free(&pv_vafree, (vm_offset_t)pc);
2982 * Free the pv_entry back to the free list.
2985 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2987 struct pv_chunk *pc;
2988 int idx, field, bit;
2990 rw_assert(&pvh_global_lock, RA_WLOCKED);
2991 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2992 PV_STAT(pv_entry_frees++);
2993 PV_STAT(pv_entry_spare++);
2995 pc = pv_to_chunk(pv);
2996 idx = pv - &pc->pc_pventry[0];
2999 pc->pc_map[field] |= 1ul << bit;
3000 for (idx = 0; idx < _NPCM; idx++)
3001 if (pc->pc_map[idx] != pc_freemask[idx]) {
3003 * 98% of the time, pc is already at the head of the
3004 * list. If it isn't already, move it to the head.
3006 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
3008 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3009 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
3014 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3019 * Get a new pv_entry, allocating a block from the system
3023 get_pv_entry(pmap_t pmap, boolean_t try)
3025 static const struct timeval printinterval = { 60, 0 };
3026 static struct timeval lastprint;
3029 struct pv_chunk *pc;
3032 rw_assert(&pvh_global_lock, RA_WLOCKED);
3033 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3034 PV_STAT(pv_entry_allocs++);
3036 if (pv_entry_count > pv_entry_high_water)
3037 if (ratecheck(&lastprint, &printinterval))
3038 printf("Approaching the limit on PV entries, consider "
3039 "increasing either the vm.pmap.shpgperproc or the "
3040 "vm.pmap.pv_entries tunable.\n");
3042 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3044 for (field = 0; field < _NPCM; field++) {
3045 if (pc->pc_map[field]) {
3046 bit = ffs(pc->pc_map[field]) - 1;
3050 if (field < _NPCM) {
3051 pv = &pc->pc_pventry[field * 32 + bit];
3052 pc->pc_map[field] &= ~(1ul << bit);
3053 /* If this was the last item, move it to tail */
3054 for (field = 0; field < _NPCM; field++)
3055 if (pc->pc_map[field] != 0) {
3056 PV_STAT(pv_entry_spare--);
3057 return (pv); /* not full, return */
3059 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3060 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3061 PV_STAT(pv_entry_spare--);
3066 * Access to the pte2list "pv_vafree" is synchronized by the pvh
3067 * global lock. If "pv_vafree" is currently non-empty, it will
3068 * remain non-empty until pmap_pte2list_alloc() completes.
3070 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3071 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
3074 PV_STAT(pc_chunk_tryfail++);
3077 m = pmap_pv_reclaim(pmap);
3081 PV_STAT(pc_chunk_count++);
3082 PV_STAT(pc_chunk_allocs++);
3083 pc = (struct pv_chunk *)pmap_pte2list_alloc(&pv_vafree);
3084 pmap_qenter((vm_offset_t)pc, &m, 1);
3086 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
3087 for (field = 1; field < _NPCM; field++)
3088 pc->pc_map[field] = pc_freemask[field];
3089 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
3090 pv = &pc->pc_pventry[0];
3091 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3092 PV_STAT(pv_entry_spare += _NPCPV - 1);
3097 * Create a pv entry for page at pa for
3101 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
3105 rw_assert(&pvh_global_lock, RA_WLOCKED);
3106 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3107 pv = get_pv_entry(pmap, FALSE);
3109 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3112 static __inline pv_entry_t
3113 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3117 rw_assert(&pvh_global_lock, RA_WLOCKED);
3118 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3119 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3120 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3128 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3132 pv = pmap_pvh_remove(pvh, pmap, va);
3133 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3134 free_pv_entry(pmap, pv);
3138 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
3140 struct md_page *pvh;
3142 rw_assert(&pvh_global_lock, RA_WLOCKED);
3143 pmap_pvh_free(&m->md, pmap, va);
3144 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
3145 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3146 if (TAILQ_EMPTY(&pvh->pv_list))
3147 vm_page_aflag_clear(m, PGA_WRITEABLE);
3152 pmap_pv_demote_pte1(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3154 struct md_page *pvh;
3156 vm_offset_t va_last;
3159 rw_assert(&pvh_global_lock, RA_WLOCKED);
3160 KASSERT((pa & PTE1_OFFSET) == 0,
3161 ("pmap_pv_demote_pte1: pa is not 1mpage aligned"));
3164 * Transfer the 1mpage's pv entry for this mapping to the first
3167 pvh = pa_to_pvh(pa);
3168 va = pte1_trunc(va);
3169 pv = pmap_pvh_remove(pvh, pmap, va);
3170 KASSERT(pv != NULL, ("pmap_pv_demote_pte1: pv not found"));
3171 m = PHYS_TO_VM_PAGE(pa);
3172 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3173 /* Instantiate the remaining NPTE2_IN_PT2 - 1 pv entries. */
3174 va_last = va + PTE1_SIZE - PAGE_SIZE;
3177 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3178 ("pmap_pv_demote_pte1: page %p is not managed", m));
3180 pmap_insert_entry(pmap, va, m);
3181 } while (va < va_last);
3184 #if VM_NRESERVLEVEL > 0
3186 pmap_pv_promote_pte1(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3188 struct md_page *pvh;
3190 vm_offset_t va_last;
3193 rw_assert(&pvh_global_lock, RA_WLOCKED);
3194 KASSERT((pa & PTE1_OFFSET) == 0,
3195 ("pmap_pv_promote_pte1: pa is not 1mpage aligned"));
3198 * Transfer the first page's pv entry for this mapping to the
3199 * 1mpage's pv list. Aside from avoiding the cost of a call
3200 * to get_pv_entry(), a transfer avoids the possibility that
3201 * get_pv_entry() calls pmap_pv_reclaim() and that pmap_pv_reclaim()
3202 * removes one of the mappings that is being promoted.
3204 m = PHYS_TO_VM_PAGE(pa);
3205 va = pte1_trunc(va);
3206 pv = pmap_pvh_remove(&m->md, pmap, va);
3207 KASSERT(pv != NULL, ("pmap_pv_promote_pte1: pv not found"));
3208 pvh = pa_to_pvh(pa);
3209 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3210 /* Free the remaining NPTE2_IN_PT2 - 1 pv entries. */
3211 va_last = va + PTE1_SIZE - PAGE_SIZE;
3215 pmap_pvh_free(&m->md, pmap, va);
3216 } while (va < va_last);
3221 * Conditionally create a pv entry.
3224 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
3228 rw_assert(&pvh_global_lock, RA_WLOCKED);
3229 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3230 if (pv_entry_count < pv_entry_high_water &&
3231 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
3233 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3240 * Create the pv entries for each of the pages within a section.
3243 pmap_pv_insert_pte1(pmap_t pmap, vm_offset_t va, pt1_entry_t pte1, u_int flags)
3245 struct md_page *pvh;
3249 rw_assert(&pvh_global_lock, RA_WLOCKED);
3250 noreclaim = (flags & PMAP_ENTER_NORECLAIM) != 0;
3251 if ((noreclaim && pv_entry_count >= pv_entry_high_water) ||
3252 (pv = get_pv_entry(pmap, noreclaim)) == NULL)
3255 pvh = pa_to_pvh(pte1_pa(pte1));
3256 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3261 pmap_tlb_flush_pte1(pmap_t pmap, vm_offset_t va, pt1_entry_t npte1)
3264 /* Kill all the small mappings or the big one only. */
3265 if (pte1_is_section(npte1))
3266 pmap_tlb_flush_range(pmap, pte1_trunc(va), PTE1_SIZE);
3268 pmap_tlb_flush(pmap, pte1_trunc(va));
3272 * Update kernel pte1 on all pmaps.
3274 * The following function is called only on one cpu with disabled interrupts.
3275 * In SMP case, smp_rendezvous_cpus() is used to stop other cpus. This way
3276 * nobody can invoke explicit hardware table walk during the update of pte1.
3277 * Unsolicited hardware table walk can still happen, invoked by speculative
3278 * data or instruction prefetch or even by speculative hardware table walk.
3280 * The break-before-make approach should be implemented here. However, it's
3281 * not so easy to do that for kernel mappings as it would be unhappy to unmap
3282 * itself unexpectedly but voluntarily.
3285 pmap_update_pte1_kernel(vm_offset_t va, pt1_entry_t npte1)
3291 * Get current pmap. Interrupts should be disabled here
3292 * so PCPU_GET() is done atomically.
3294 pmap = PCPU_GET(curpmap);
3299 * (1) Change pte1 on current pmap.
3300 * (2) Flush all obsolete TLB entries on current CPU.
3301 * (3) Change pte1 on all pmaps.
3302 * (4) Flush all obsolete TLB entries on all CPUs in SMP case.
3305 pte1p = pmap_pte1(pmap, va);
3306 pte1_store(pte1p, npte1);
3308 /* Kill all the small mappings or the big one only. */
3309 if (pte1_is_section(npte1)) {
3310 pmap_pte1_kern_promotions++;
3311 tlb_flush_range_local(pte1_trunc(va), PTE1_SIZE);
3313 pmap_pte1_kern_demotions++;
3314 tlb_flush_local(pte1_trunc(va));
3318 * In SMP case, this function is called when all cpus are at smp
3319 * rendezvous, so there is no need to use 'allpmaps_lock' lock here.
3320 * In UP case, the function is called with this lock locked.
3322 LIST_FOREACH(pmap, &allpmaps, pm_list) {
3323 pte1p = pmap_pte1(pmap, va);
3324 pte1_store(pte1p, npte1);
3328 /* Kill all the small mappings or the big one only. */
3329 if (pte1_is_section(npte1))
3330 tlb_flush_range(pte1_trunc(va), PTE1_SIZE);
3332 tlb_flush(pte1_trunc(va));
3337 struct pte1_action {
3340 u_int update; /* CPU that updates the PTE1 */
3344 pmap_update_pte1_action(void *arg)
3346 struct pte1_action *act = arg;
3348 if (act->update == PCPU_GET(cpuid))
3349 pmap_update_pte1_kernel(act->va, act->npte1);
3353 * Change pte1 on current pmap.
3354 * Note that kernel pte1 must be changed on all pmaps.
3356 * According to the architecture reference manual published by ARM,
3357 * the behaviour is UNPREDICTABLE when two or more TLB entries map the same VA.
3358 * According to this manual, UNPREDICTABLE behaviours must never happen in
3359 * a viable system. In contrast, on x86 processors, it is not specified which
3360 * TLB entry mapping the virtual address will be used, but the MMU doesn't
3361 * generate a bogus translation the way it does on Cortex-A8 rev 2 (Beaglebone
3364 * It's a problem when either promotion or demotion is being done. The pte1
3365 * update and appropriate TLB flush must be done atomically in general.
3368 pmap_change_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va,
3372 if (pmap == kernel_pmap) {
3373 struct pte1_action act;
3378 act.update = PCPU_GET(cpuid);
3379 smp_rendezvous_cpus(all_cpus, smp_no_rendezvous_barrier,
3380 pmap_update_pte1_action, NULL, &act);
3386 * Use break-before-make approach for changing userland
3387 * mappings. It can cause L1 translation aborts on other
3388 * cores in SMP case. So, special treatment is implemented
3389 * in pmap_fault(). To reduce the likelihood that another core
3390 * will be affected by the broken mapping, disable interrupts
3391 * until the mapping change is completed.
3393 cspr = disable_interrupts(PSR_I | PSR_F);
3395 pmap_tlb_flush_pte1(pmap, va, npte1);
3396 pte1_store(pte1p, npte1);
3397 restore_interrupts(cspr);
3402 pmap_change_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va,
3406 if (pmap == kernel_pmap) {
3407 mtx_lock_spin(&allpmaps_lock);
3408 pmap_update_pte1_kernel(va, npte1);
3409 mtx_unlock_spin(&allpmaps_lock);
3414 * Use break-before-make approach for changing userland
3415 * mappings. It's absolutely safe in UP case when interrupts
3418 cspr = disable_interrupts(PSR_I | PSR_F);
3420 pmap_tlb_flush_pte1(pmap, va, npte1);
3421 pte1_store(pte1p, npte1);
3422 restore_interrupts(cspr);
3427 #if VM_NRESERVLEVEL > 0
3429 * Tries to promote the NPTE2_IN_PT2, contiguous 4KB page mappings that are
3430 * within a single page table page (PT2) to a single 1MB page mapping.
3431 * For promotion to occur, two conditions must be met: (1) the 4KB page
3432 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3433 * mappings must have identical characteristics.
3435 * Managed (PG_MANAGED) mappings within the kernel address space are not
3436 * promoted. The reason is that kernel PTE1s are replicated in each pmap but
3437 * pmap_remove_write(), pmap_clear_modify(), and pmap_clear_reference() only
3438 * read the PTE1 from the kernel pmap.
3441 pmap_promote_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3444 pt2_entry_t *fpte2p, fpte2, fpte2_fav;
3445 pt2_entry_t *pte2p, pte2;
3446 vm_offset_t pteva __unused;
3447 vm_page_t m __unused;
3449 PDEBUG(6, printf("%s(%p): try for va %#x pte1 %#x at %p\n", __func__,
3450 pmap, va, pte1_load(pte1p), pte1p));
3452 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3455 * Examine the first PTE2 in the specified PT2. Abort if this PTE2 is
3456 * either invalid, unused, or does not map the first 4KB physical page
3457 * within a 1MB page.
3459 fpte2p = pmap_pte2_quick(pmap, pte1_trunc(va));
3460 fpte2 = pte2_load(fpte2p);
3461 if ((fpte2 & ((PTE2_FRAME & PTE1_OFFSET) | PTE2_A | PTE2_V)) !=
3462 (PTE2_A | PTE2_V)) {
3463 pmap_pte1_p_failures++;
3464 CTR3(KTR_PMAP, "%s: failure(1) for va %#x in pmap %p",
3465 __func__, va, pmap);
3468 if (pte2_is_managed(fpte2) && pmap == kernel_pmap) {
3469 pmap_pte1_p_failures++;
3470 CTR3(KTR_PMAP, "%s: failure(2) for va %#x in pmap %p",
3471 __func__, va, pmap);
3474 if ((fpte2 & (PTE2_NM | PTE2_RO)) == PTE2_NM) {
3476 * When page is not modified, PTE2_RO can be set without
3477 * a TLB invalidation.
3480 pte2_store(fpte2p, fpte2);
3484 * Examine each of the other PTE2s in the specified PT2. Abort if this
3485 * PTE2 maps an unexpected 4KB physical page or does not have identical
3486 * characteristics to the first PTE2.
3488 fpte2_fav = (fpte2 & (PTE2_FRAME | PTE2_A | PTE2_V));
3489 fpte2_fav += PTE1_SIZE - PTE2_SIZE; /* examine from the end */
3490 for (pte2p = fpte2p + NPTE2_IN_PT2 - 1; pte2p > fpte2p; pte2p--) {
3491 pte2 = pte2_load(pte2p);
3492 if ((pte2 & (PTE2_FRAME | PTE2_A | PTE2_V)) != fpte2_fav) {
3493 pmap_pte1_p_failures++;
3494 CTR3(KTR_PMAP, "%s: failure(3) for va %#x in pmap %p",
3495 __func__, va, pmap);
3498 if ((pte2 & (PTE2_NM | PTE2_RO)) == PTE2_NM) {
3500 * When page is not modified, PTE2_RO can be set
3501 * without a TLB invalidation. See note above.
3504 pte2_store(pte2p, pte2);
3505 pteva = pte1_trunc(va) | (pte2 & PTE1_OFFSET &
3507 CTR3(KTR_PMAP, "%s: protect for va %#x in pmap %p",
3508 __func__, pteva, pmap);
3510 if ((pte2 & PTE2_PROMOTE) != (fpte2 & PTE2_PROMOTE)) {
3511 pmap_pte1_p_failures++;
3512 CTR3(KTR_PMAP, "%s: failure(4) for va %#x in pmap %p",
3513 __func__, va, pmap);
3517 fpte2_fav -= PTE2_SIZE;
3520 * The page table page in its current state will stay in PT2TAB
3521 * until the PTE1 mapping the section is demoted by pmap_demote_pte1()
3522 * or destroyed by pmap_remove_pte1().
3524 * Note that L2 page table size is not equal to PAGE_SIZE.
3526 m = PHYS_TO_VM_PAGE(trunc_page(pte1_link_pa(pte1_load(pte1p))));
3527 KASSERT(m >= vm_page_array && m < &vm_page_array[vm_page_array_size],
3528 ("%s: PT2 page is out of range", __func__));
3529 KASSERT(m->pindex == (pte1_index(va) & ~PT2PG_MASK),
3530 ("%s: PT2 page's pindex is wrong", __func__));
3533 * Get pte1 from pte2 format.
3535 npte1 = (fpte2 & PTE1_FRAME) | ATTR_TO_L1(fpte2) | PTE1_V;
3538 * Promote the pv entries.
3540 if (pte2_is_managed(fpte2))
3541 pmap_pv_promote_pte1(pmap, va, pte1_pa(npte1));
3544 * Promote the mappings.
3546 pmap_change_pte1(pmap, pte1p, va, npte1);
3548 pmap_pte1_promotions++;
3549 CTR3(KTR_PMAP, "%s: success for va %#x in pmap %p",
3550 __func__, va, pmap);
3552 PDEBUG(6, printf("%s(%p): success for va %#x pte1 %#x(%#x) at %p\n",
3553 __func__, pmap, va, npte1, pte1_load(pte1p), pte1p));
3555 #endif /* VM_NRESERVLEVEL > 0 */
3558 * Zero L2 page table page.
3560 static __inline void
3561 pmap_clear_pt2(pt2_entry_t *fpte2p)
3565 for (pte2p = fpte2p; pte2p < fpte2p + NPTE2_IN_PT2; pte2p++)
3571 * Removes a 1MB page mapping from the kernel pmap.
3574 pmap_remove_kernel_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3578 pt2_entry_t *fpte2p;
3581 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3582 m = pmap_pt2_page(pmap, va);
3585 * QQQ: Is this function called only on promoted pte1?
3586 * We certainly do section mappings directly
3587 * (without promotion) in kernel !!!
3589 panic("%s: missing pt2 page", __func__);
3591 pte1_idx = pte1_index(va);
3594 * Initialize the L2 page table.
3596 fpte2p = page_pt2(pt2map_pt2pg(va), pte1_idx);
3597 pmap_clear_pt2(fpte2p);
3600 * Remove the mapping.
3602 pt2_pa = page_pt2pa(VM_PAGE_TO_PHYS(m), pte1_idx);
3603 pmap_kenter_pte1(va, PTE1_LINK(pt2_pa));
3606 * QQQ: We do not need to invalidate PT2MAP mapping
3607 * as we did not change it. I.e. the L2 page table page
3608 * was and still is mapped the same way.
3613 * Do the things to unmap a section in a process
3616 pmap_remove_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t sva,
3617 struct spglist *free)
3620 struct md_page *pvh;
3621 vm_offset_t eva, va;
3624 PDEBUG(6, printf("%s(%p): va %#x pte1 %#x at %p\n", __func__, pmap, sva,
3625 pte1_load(pte1p), pte1p));
3627 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3628 KASSERT((sva & PTE1_OFFSET) == 0,
3629 ("%s: sva is not 1mpage aligned", __func__));
3632 * Clear and invalidate the mapping. It should occupy one and only TLB
3633 * entry. So, pmap_tlb_flush() called with aligned address should be
3636 opte1 = pte1_load_clear(pte1p);
3637 pmap_tlb_flush(pmap, sva);
3639 if (pte1_is_wired(opte1))
3640 pmap->pm_stats.wired_count -= PTE1_SIZE / PAGE_SIZE;
3641 pmap->pm_stats.resident_count -= PTE1_SIZE / PAGE_SIZE;
3642 if (pte1_is_managed(opte1)) {
3643 pvh = pa_to_pvh(pte1_pa(opte1));
3644 pmap_pvh_free(pvh, pmap, sva);
3645 eva = sva + PTE1_SIZE;
3646 for (va = sva, m = PHYS_TO_VM_PAGE(pte1_pa(opte1));
3647 va < eva; va += PAGE_SIZE, m++) {
3648 if (pte1_is_dirty(opte1))
3651 vm_page_aflag_set(m, PGA_REFERENCED);
3652 if (TAILQ_EMPTY(&m->md.pv_list) &&
3653 TAILQ_EMPTY(&pvh->pv_list))
3654 vm_page_aflag_clear(m, PGA_WRITEABLE);
3657 if (pmap == kernel_pmap) {
3659 * L2 page table(s) can't be removed from kernel map as
3660 * kernel counts on it (stuff around pmap_growkernel()).
3662 pmap_remove_kernel_pte1(pmap, pte1p, sva);
3665 * Get associated L2 page table page.
3666 * It's possible that the page was never allocated.
3668 m = pmap_pt2_page(pmap, sva);
3670 pmap_unwire_pt2_all(pmap, sva, m, free);
3675 * Fills L2 page table page with mappings to consecutive physical pages.
3677 static __inline void
3678 pmap_fill_pt2(pt2_entry_t *fpte2p, pt2_entry_t npte2)
3682 for (pte2p = fpte2p; pte2p < fpte2p + NPTE2_IN_PT2; pte2p++) {
3683 pte2_store(pte2p, npte2);
3689 * Tries to demote a 1MB page mapping. If demotion fails, the
3690 * 1MB page mapping is invalidated.
3693 pmap_demote_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3695 pt1_entry_t opte1, npte1;
3696 pt2_entry_t *fpte2p, npte2;
3697 vm_paddr_t pt2pg_pa, pt2_pa;
3699 struct spglist free;
3700 uint32_t pte1_idx, isnew = 0;
3702 PDEBUG(6, printf("%s(%p): try for va %#x pte1 %#x at %p\n", __func__,
3703 pmap, va, pte1_load(pte1p), pte1p));
3705 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3707 opte1 = pte1_load(pte1p);
3708 KASSERT(pte1_is_section(opte1), ("%s: opte1 not a section", __func__));
3710 if ((opte1 & PTE1_A) == 0 || (m = pmap_pt2_page(pmap, va)) == NULL) {
3711 KASSERT(!pte1_is_wired(opte1),
3712 ("%s: PT2 page for a wired mapping is missing", __func__));
3715 * Invalidate the 1MB page mapping and return
3716 * "failure" if the mapping was never accessed or the
3717 * allocation of the new page table page fails.
3719 if ((opte1 & PTE1_A) == 0 || (m = vm_page_alloc(NULL,
3720 pte1_index(va) & ~PT2PG_MASK, VM_ALLOC_NOOBJ |
3721 VM_ALLOC_NORMAL | VM_ALLOC_WIRED)) == NULL) {
3723 pmap_remove_pte1(pmap, pte1p, pte1_trunc(va), &free);
3724 vm_page_free_pages_toq(&free, false);
3725 CTR3(KTR_PMAP, "%s: failure for va %#x in pmap %p",
3726 __func__, va, pmap);
3729 if (va < VM_MAXUSER_ADDRESS)
3730 pmap->pm_stats.resident_count++;
3735 * We init all L2 page tables in the page even if
3736 * we are going to change everything for one L2 page
3739 pt2pg_pa = pmap_pt2pg_init(pmap, va, m);
3741 if (va < VM_MAXUSER_ADDRESS) {
3742 if (pt2_is_empty(m, va))
3743 isnew = 1; /* Demoting section w/o promotion. */
3746 KASSERT(pt2_is_full(m, va), ("%s: bad PT2 wire"
3747 " count %u", __func__,
3748 pt2_wirecount_get(m, pte1_index(va))));
3753 pt2pg_pa = VM_PAGE_TO_PHYS(m);
3754 pte1_idx = pte1_index(va);
3756 * If the pmap is current, then the PT2MAP can provide access to
3757 * the page table page (promoted L2 page tables are not unmapped).
3758 * Otherwise, temporarily map the L2 page table page (m) into
3759 * the kernel's address space at either PADDR1 or PADDR2.
3761 * Note that L2 page table size is not equal to PAGE_SIZE.
3763 if (pmap_is_current(pmap))
3764 fpte2p = page_pt2(pt2map_pt2pg(va), pte1_idx);
3765 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
3766 if (pte2_pa(pte2_load(PMAP1)) != pt2pg_pa) {
3767 pte2_store(PMAP1, PTE2_KPT(pt2pg_pa));
3769 PMAP1cpu = PCPU_GET(cpuid);
3771 tlb_flush_local((vm_offset_t)PADDR1);
3775 if (PMAP1cpu != PCPU_GET(cpuid)) {
3776 PMAP1cpu = PCPU_GET(cpuid);
3777 tlb_flush_local((vm_offset_t)PADDR1);
3782 fpte2p = page_pt2((vm_offset_t)PADDR1, pte1_idx);
3784 mtx_lock(&PMAP2mutex);
3785 if (pte2_pa(pte2_load(PMAP2)) != pt2pg_pa) {
3786 pte2_store(PMAP2, PTE2_KPT(pt2pg_pa));
3787 tlb_flush((vm_offset_t)PADDR2);
3789 fpte2p = page_pt2((vm_offset_t)PADDR2, pte1_idx);
3791 pt2_pa = page_pt2pa(pt2pg_pa, pte1_idx);
3792 npte1 = PTE1_LINK(pt2_pa);
3794 KASSERT((opte1 & PTE1_A) != 0,
3795 ("%s: opte1 is missing PTE1_A", __func__));
3796 KASSERT((opte1 & (PTE1_NM | PTE1_RO)) != PTE1_NM,
3797 ("%s: opte1 has PTE1_NM", __func__));
3800 * Get pte2 from pte1 format.
3802 npte2 = pte1_pa(opte1) | ATTR_TO_L2(opte1) | PTE2_V;
3805 * If the L2 page table page is new, initialize it. If the mapping
3806 * has changed attributes, update the page table entries.
3809 pt2_wirecount_set(m, pte1_idx, NPTE2_IN_PT2);
3810 pmap_fill_pt2(fpte2p, npte2);
3811 } else if ((pte2_load(fpte2p) & PTE2_PROMOTE) !=
3812 (npte2 & PTE2_PROMOTE))
3813 pmap_fill_pt2(fpte2p, npte2);
3815 KASSERT(pte2_pa(pte2_load(fpte2p)) == pte2_pa(npte2),
3816 ("%s: fpte2p and npte2 map different physical addresses",
3819 if (fpte2p == PADDR2)
3820 mtx_unlock(&PMAP2mutex);
3823 * Demote the mapping. This pmap is locked. The old PTE1 has
3824 * PTE1_A set. If the old PTE1 has not PTE1_RO set, it also
3825 * has not PTE1_NM set. Thus, there is no danger of a race with
3826 * another processor changing the setting of PTE1_A and/or PTE1_NM
3827 * between the read above and the store below.
3829 pmap_change_pte1(pmap, pte1p, va, npte1);
3832 * Demote the pv entry. This depends on the earlier demotion
3833 * of the mapping. Specifically, the (re)creation of a per-
3834 * page pv entry might trigger the execution of pmap_pv_reclaim(),
3835 * which might reclaim a newly (re)created per-page pv entry
3836 * and destroy the associated mapping. In order to destroy
3837 * the mapping, the PTE1 must have already changed from mapping
3838 * the 1mpage to referencing the page table page.
3840 if (pte1_is_managed(opte1))
3841 pmap_pv_demote_pte1(pmap, va, pte1_pa(opte1));
3843 pmap_pte1_demotions++;
3844 CTR3(KTR_PMAP, "%s: success for va %#x in pmap %p",
3845 __func__, va, pmap);
3847 PDEBUG(6, printf("%s(%p): success for va %#x pte1 %#x(%#x) at %p\n",
3848 __func__, pmap, va, npte1, pte1_load(pte1p), pte1p));
3853 * Insert the given physical page (p) at
3854 * the specified virtual address (v) in the
3855 * target physical map with the protection requested.
3857 * If specified, the page will be wired down, meaning
3858 * that the related pte can not be reclaimed.
3860 * NB: This is the only routine which MAY NOT lazy-evaluate
3861 * or lose information. That is, this routine must actually
3862 * insert this page into the given map NOW.
3865 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3866 u_int flags, int8_t psind)
3870 pt2_entry_t npte2, opte2;
3873 vm_page_t mpte2, om;
3876 va = trunc_page(va);
3877 KASSERT(va <= vm_max_kernel_address, ("%s: toobig", __func__));
3878 KASSERT(va < UPT2V_MIN_ADDRESS || va >= UPT2V_MAX_ADDRESS,
3879 ("%s: invalid to pmap_enter page table pages (va: 0x%x)", __func__,
3881 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
3882 va >= kmi.clean_eva,
3883 ("%s: managed mapping within the clean submap", __func__));
3884 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3885 VM_OBJECT_ASSERT_LOCKED(m->object);
3886 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
3887 ("%s: flags %u has reserved bits set", __func__, flags));
3888 pa = VM_PAGE_TO_PHYS(m);
3889 npte2 = PTE2(pa, PTE2_A, vm_page_pte2_attr(m));
3890 if ((flags & VM_PROT_WRITE) == 0)
3892 if ((prot & VM_PROT_WRITE) == 0)
3894 KASSERT((npte2 & (PTE2_NM | PTE2_RO)) != PTE2_RO,
3895 ("%s: flags includes VM_PROT_WRITE but prot doesn't", __func__));
3896 if ((prot & VM_PROT_EXECUTE) == 0)
3898 if ((flags & PMAP_ENTER_WIRED) != 0)
3900 if (va < VM_MAXUSER_ADDRESS)
3902 if (pmap != kernel_pmap)
3905 rw_wlock(&pvh_global_lock);
3909 /* Assert the required virtual and physical alignment. */
3910 KASSERT((va & PTE1_OFFSET) == 0,
3911 ("%s: va unaligned", __func__));
3912 KASSERT(m->psind > 0, ("%s: m->psind < psind", __func__));
3913 rv = pmap_enter_pte1(pmap, va, PTE1_PA(pa) | ATTR_TO_L1(npte2) |
3919 * In the case that a page table page is not
3920 * resident, we are creating it here.
3922 if (va < VM_MAXUSER_ADDRESS) {
3923 mpte2 = pmap_allocpte2(pmap, va, flags);
3924 if (mpte2 == NULL) {
3925 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3926 ("pmap_allocpte2 failed with sleep allowed"));
3927 rv = KERN_RESOURCE_SHORTAGE;
3932 pte1p = pmap_pte1(pmap, va);
3933 if (pte1_is_section(pte1_load(pte1p)))
3934 panic("%s: attempted on 1MB page", __func__);
3935 pte2p = pmap_pte2_quick(pmap, va);
3937 panic("%s: invalid L1 page table entry va=%#x", __func__, va);
3940 opte2 = pte2_load(pte2p);
3941 opa = pte2_pa(opte2);
3943 * Mapping has not changed, must be protection or wiring change.
3945 if (pte2_is_valid(opte2) && (opa == pa)) {
3947 * Wiring change, just update stats. We don't worry about
3948 * wiring PT2 pages as they remain resident as long as there
3949 * are valid mappings in them. Hence, if a user page is wired,
3950 * the PT2 page will be also.
3952 if (pte2_is_wired(npte2) && !pte2_is_wired(opte2))
3953 pmap->pm_stats.wired_count++;
3954 else if (!pte2_is_wired(npte2) && pte2_is_wired(opte2))
3955 pmap->pm_stats.wired_count--;
3958 * Remove extra pte2 reference
3961 pt2_wirecount_dec(mpte2, pte1_index(va));
3962 if ((m->oflags & VPO_UNMANAGED) == 0)
3968 * QQQ: We think that changing physical address on writeable mapping
3969 * is not safe. Well, maybe on kernel address space with correct
3970 * locking, it can make a sense. However, we have no idea why
3971 * anyone should do that on user address space. Are we wrong?
3973 KASSERT((opa == 0) || (opa == pa) ||
3974 !pte2_is_valid(opte2) || ((opte2 & PTE2_RO) != 0),
3975 ("%s: pmap %p va %#x(%#x) opa %#x pa %#x - gotcha %#x %#x!",
3976 __func__, pmap, va, opte2, opa, pa, flags, prot));
3981 * Mapping has changed, invalidate old range and fall through to
3982 * handle validating new mapping.
3985 if (pte2_is_wired(opte2))
3986 pmap->pm_stats.wired_count--;
3987 om = PHYS_TO_VM_PAGE(opa);
3988 if (om != NULL && (om->oflags & VPO_UNMANAGED) != 0)
3991 pv = pmap_pvh_remove(&om->md, pmap, va);
3994 * Remove extra pte2 reference
3997 pt2_wirecount_dec(mpte2, va >> PTE1_SHIFT);
3999 pmap->pm_stats.resident_count++;
4002 * Enter on the PV list if part of our managed memory.
4004 if ((m->oflags & VPO_UNMANAGED) == 0) {
4006 pv = get_pv_entry(pmap, FALSE);
4009 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4010 } else if (pv != NULL)
4011 free_pv_entry(pmap, pv);
4014 * Increment counters
4016 if (pte2_is_wired(npte2))
4017 pmap->pm_stats.wired_count++;
4021 * Now validate mapping with desired protection/wiring.
4023 if (prot & VM_PROT_WRITE) {
4024 if ((m->oflags & VPO_UNMANAGED) == 0)
4025 vm_page_aflag_set(m, PGA_WRITEABLE);
4029 * If the mapping or permission bits are different, we need
4030 * to update the pte2.
4032 * QQQ: Think again and again what to do
4033 * if the mapping is going to be changed!
4035 if ((opte2 & ~(PTE2_NM | PTE2_A)) != (npte2 & ~(PTE2_NM | PTE2_A))) {
4037 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4038 * is set. Do it now, before the mapping is stored and made
4039 * valid for hardware table walk. If done later, there is a race
4040 * for other threads of current process in lazy loading case.
4041 * Don't do it for kernel memory which is mapped with exec
4042 * permission even if the memory isn't going to hold executable
4043 * code. The only time when icache sync is needed is after
4044 * kernel module is loaded and the relocation info is processed.
4045 * And it's done in elf_cpu_load_file().
4047 * QQQ: (1) Does it exist any better way where
4048 * or how to sync icache?
4049 * (2) Now, we do it on a page basis.
4051 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
4052 m->md.pat_mode == VM_MEMATTR_WB_WA &&
4053 (opa != pa || (opte2 & PTE2_NX)))
4054 cache_icache_sync_fresh(va, pa, PAGE_SIZE);
4056 if (opte2 & PTE2_V) {
4057 /* Change mapping with break-before-make approach. */
4058 opte2 = pte2_load_clear(pte2p);
4059 pmap_tlb_flush(pmap, va);
4060 pte2_store(pte2p, npte2);
4062 KASSERT((om->oflags & VPO_UNMANAGED) == 0,
4063 ("%s: om %p unmanaged", __func__, om));
4064 if ((opte2 & PTE2_A) != 0)
4065 vm_page_aflag_set(om, PGA_REFERENCED);
4066 if (pte2_is_dirty(opte2))
4068 if (TAILQ_EMPTY(&om->md.pv_list) &&
4069 ((om->flags & PG_FICTITIOUS) != 0 ||
4070 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
4071 vm_page_aflag_clear(om, PGA_WRITEABLE);
4074 pte2_store(pte2p, npte2);
4079 * QQQ: In time when both access and not mofified bits are
4080 * emulated by software, this should not happen. Some
4081 * analysis is need, if this really happen. Missing
4082 * tlb flush somewhere could be the reason.
4084 panic("%s: pmap %p va %#x opte2 %x npte2 %x !!", __func__, pmap,
4089 #if VM_NRESERVLEVEL > 0
4091 * If both the L2 page table page and the reservation are fully
4092 * populated, then attempt promotion.
4094 if ((mpte2 == NULL || pt2_is_full(mpte2, va)) &&
4095 sp_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
4096 vm_reserv_level_iffullpop(m) == 0)
4097 pmap_promote_pte1(pmap, pte1p, va);
4103 rw_wunlock(&pvh_global_lock);
4109 * Do the things to unmap a page in a process.
4112 pmap_remove_pte2(pmap_t pmap, pt2_entry_t *pte2p, vm_offset_t va,
4113 struct spglist *free)
4118 rw_assert(&pvh_global_lock, RA_WLOCKED);
4119 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4121 /* Clear and invalidate the mapping. */
4122 opte2 = pte2_load_clear(pte2p);
4123 pmap_tlb_flush(pmap, va);
4125 KASSERT(pte2_is_valid(opte2), ("%s: pmap %p va %#x not link pte2 %#x",
4126 __func__, pmap, va, opte2));
4129 pmap->pm_stats.wired_count -= 1;
4130 pmap->pm_stats.resident_count -= 1;
4131 if (pte2_is_managed(opte2)) {
4132 m = PHYS_TO_VM_PAGE(pte2_pa(opte2));
4133 if (pte2_is_dirty(opte2))
4136 vm_page_aflag_set(m, PGA_REFERENCED);
4137 pmap_remove_entry(pmap, m, va);
4139 return (pmap_unuse_pt2(pmap, va, free));
4143 * Remove a single page from a process address space.
4146 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
4150 rw_assert(&pvh_global_lock, RA_WLOCKED);
4151 KASSERT(curthread->td_pinned > 0,
4152 ("%s: curthread not pinned", __func__));
4153 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4154 if ((pte2p = pmap_pte2_quick(pmap, va)) == NULL ||
4155 !pte2_is_valid(pte2_load(pte2p)))
4157 pmap_remove_pte2(pmap, pte2p, va, free);
4161 * Remove the given range of addresses from the specified map.
4163 * It is assumed that the start and end are properly
4164 * rounded to the page size.
4167 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4170 pt1_entry_t *pte1p, pte1;
4171 pt2_entry_t *pte2p, pte2;
4172 struct spglist free;
4175 * Perform an unsynchronized read. This is, however, safe.
4177 if (pmap->pm_stats.resident_count == 0)
4182 rw_wlock(&pvh_global_lock);
4187 * Special handling of removing one page. A very common
4188 * operation and easy to short circuit some code.
4190 if (sva + PAGE_SIZE == eva) {
4191 pte1 = pte1_load(pmap_pte1(pmap, sva));
4192 if (pte1_is_link(pte1)) {
4193 pmap_remove_page(pmap, sva, &free);
4198 for (; sva < eva; sva = nextva) {
4200 * Calculate address for next L2 page table.
4202 nextva = pte1_trunc(sva + PTE1_SIZE);
4205 if (pmap->pm_stats.resident_count == 0)
4208 pte1p = pmap_pte1(pmap, sva);
4209 pte1 = pte1_load(pte1p);
4212 * Weed out invalid mappings. Note: we assume that the L1 page
4213 * table is always allocated, and in kernel virtual.
4218 if (pte1_is_section(pte1)) {
4220 * Are we removing the entire large page? If not,
4221 * demote the mapping and fall through.
4223 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
4224 pmap_remove_pte1(pmap, pte1p, sva, &free);
4226 } else if (!pmap_demote_pte1(pmap, pte1p, sva)) {
4227 /* The large page mapping was destroyed. */
4232 /* Update pte1 after demotion. */
4233 pte1 = pte1_load(pte1p);
4238 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
4239 " is not link", __func__, pmap, sva, pte1, pte1p));
4242 * Limit our scan to either the end of the va represented
4243 * by the current L2 page table page, or to the end of the
4244 * range being removed.
4249 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva;
4250 pte2p++, sva += PAGE_SIZE) {
4251 pte2 = pte2_load(pte2p);
4252 if (!pte2_is_valid(pte2))
4254 if (pmap_remove_pte2(pmap, pte2p, sva, &free))
4260 rw_wunlock(&pvh_global_lock);
4262 vm_page_free_pages_toq(&free, false);
4266 * Routine: pmap_remove_all
4268 * Removes this physical page from
4269 * all physical maps in which it resides.
4270 * Reflects back modify bits to the pager.
4273 * Original versions of this routine were very
4274 * inefficient because they iteratively called
4275 * pmap_remove (slow...)
4279 pmap_remove_all(vm_page_t m)
4281 struct md_page *pvh;
4284 pt2_entry_t *pte2p, opte2;
4287 struct spglist free;
4289 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4290 ("%s: page %p is not managed", __func__, m));
4292 rw_wlock(&pvh_global_lock);
4294 if ((m->flags & PG_FICTITIOUS) != 0)
4295 goto small_mappings;
4296 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4297 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
4301 pte1p = pmap_pte1(pmap, va);
4302 (void)pmap_demote_pte1(pmap, pte1p, va);
4306 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4309 pmap->pm_stats.resident_count--;
4310 pte1p = pmap_pte1(pmap, pv->pv_va);
4311 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found "
4312 "a 1mpage in page %p's pv list", __func__, m));
4313 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
4314 opte2 = pte2_load_clear(pte2p);
4315 pmap_tlb_flush(pmap, pv->pv_va);
4316 KASSERT(pte2_is_valid(opte2), ("%s: pmap %p va %x zero pte2",
4317 __func__, pmap, pv->pv_va));
4318 if (pte2_is_wired(opte2))
4319 pmap->pm_stats.wired_count--;
4321 vm_page_aflag_set(m, PGA_REFERENCED);
4324 * Update the vm_page_t clean and reference bits.
4326 if (pte2_is_dirty(opte2))
4328 pmap_unuse_pt2(pmap, pv->pv_va, &free);
4329 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4330 free_pv_entry(pmap, pv);
4333 vm_page_aflag_clear(m, PGA_WRITEABLE);
4335 rw_wunlock(&pvh_global_lock);
4336 vm_page_free_pages_toq(&free, false);
4340 * Just subroutine for pmap_remove_pages() to reasonably satisfy
4341 * good coding style, a.k.a. 80 character line width limit hell.
4343 static __inline void
4344 pmap_remove_pte1_quick(pmap_t pmap, pt1_entry_t pte1, pv_entry_t pv,
4345 struct spglist *free)
4348 vm_page_t m, mt, mpt2pg;
4349 struct md_page *pvh;
4352 m = PHYS_TO_VM_PAGE(pa);
4354 KASSERT(m->phys_addr == pa, ("%s: vm_page_t %p addr mismatch %#x %#x",
4355 __func__, m, m->phys_addr, pa));
4356 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4357 m < &vm_page_array[vm_page_array_size],
4358 ("%s: bad pte1 %#x", __func__, pte1));
4360 if (pte1_is_dirty(pte1)) {
4361 for (mt = m; mt < &m[PTE1_SIZE / PAGE_SIZE]; mt++)
4365 pmap->pm_stats.resident_count -= PTE1_SIZE / PAGE_SIZE;
4366 pvh = pa_to_pvh(pa);
4367 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4368 if (TAILQ_EMPTY(&pvh->pv_list)) {
4369 for (mt = m; mt < &m[PTE1_SIZE / PAGE_SIZE]; mt++)
4370 if (TAILQ_EMPTY(&mt->md.pv_list))
4371 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4373 mpt2pg = pmap_pt2_page(pmap, pv->pv_va);
4375 pmap_unwire_pt2_all(pmap, pv->pv_va, mpt2pg, free);
4379 * Just subroutine for pmap_remove_pages() to reasonably satisfy
4380 * good coding style, a.k.a. 80 character line width limit hell.
4382 static __inline void
4383 pmap_remove_pte2_quick(pmap_t pmap, pt2_entry_t pte2, pv_entry_t pv,
4384 struct spglist *free)
4388 struct md_page *pvh;
4391 m = PHYS_TO_VM_PAGE(pa);
4393 KASSERT(m->phys_addr == pa, ("%s: vm_page_t %p addr mismatch %#x %#x",
4394 __func__, m, m->phys_addr, pa));
4395 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4396 m < &vm_page_array[vm_page_array_size],
4397 ("%s: bad pte2 %#x", __func__, pte2));
4399 if (pte2_is_dirty(pte2))
4402 pmap->pm_stats.resident_count--;
4403 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4404 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
4405 pvh = pa_to_pvh(pa);
4406 if (TAILQ_EMPTY(&pvh->pv_list))
4407 vm_page_aflag_clear(m, PGA_WRITEABLE);
4409 pmap_unuse_pt2(pmap, pv->pv_va, free);
4413 * Remove all pages from specified address space this aids process
4414 * exit speeds. Also, this code is special cased for current process
4415 * only, but can have the more generic (and slightly slower) mode enabled.
4416 * This is much faster than pmap_remove in the case of running down
4417 * an entire address space.
4420 pmap_remove_pages(pmap_t pmap)
4422 pt1_entry_t *pte1p, pte1;
4423 pt2_entry_t *pte2p, pte2;
4425 struct pv_chunk *pc, *npc;
4426 struct spglist free;
4429 uint32_t inuse, bitmask;
4433 * Assert that the given pmap is only active on the current
4434 * CPU. Unfortunately, we cannot block another CPU from
4435 * activating the pmap while this function is executing.
4437 KASSERT(pmap == vmspace_pmap(curthread->td_proc->p_vmspace),
4438 ("%s: non-current pmap %p", __func__, pmap));
4439 #if defined(SMP) && defined(INVARIANTS)
4441 cpuset_t other_cpus;
4444 other_cpus = pmap->pm_active;
4445 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
4447 KASSERT(CPU_EMPTY(&other_cpus),
4448 ("%s: pmap %p active on other cpus", __func__, pmap));
4452 rw_wlock(&pvh_global_lock);
4455 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4456 KASSERT(pc->pc_pmap == pmap, ("%s: wrong pmap %p %p",
4457 __func__, pmap, pc->pc_pmap));
4459 for (field = 0; field < _NPCM; field++) {
4460 inuse = (~(pc->pc_map[field])) & pc_freemask[field];
4461 while (inuse != 0) {
4462 bit = ffs(inuse) - 1;
4463 bitmask = 1UL << bit;
4464 idx = field * 32 + bit;
4465 pv = &pc->pc_pventry[idx];
4469 * Note that we cannot remove wired pages
4470 * from a process' mapping at this time
4472 pte1p = pmap_pte1(pmap, pv->pv_va);
4473 pte1 = pte1_load(pte1p);
4474 if (pte1_is_section(pte1)) {
4475 if (pte1_is_wired(pte1)) {
4480 pmap_remove_pte1_quick(pmap, pte1, pv,
4483 else if (pte1_is_link(pte1)) {
4484 pte2p = pt2map_entry(pv->pv_va);
4485 pte2 = pte2_load(pte2p);
4487 if (!pte2_is_valid(pte2)) {
4488 printf("%s: pmap %p va %#x "
4489 "pte2 %#x\n", __func__,
4490 pmap, pv->pv_va, pte2);
4494 if (pte2_is_wired(pte2)) {
4499 pmap_remove_pte2_quick(pmap, pte2, pv,
4502 printf("%s: pmap %p va %#x pte1 %#x\n",
4503 __func__, pmap, pv->pv_va, pte1);
4508 PV_STAT(pv_entry_frees++);
4509 PV_STAT(pv_entry_spare++);
4511 pc->pc_map[field] |= bitmask;
4515 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4519 tlb_flush_all_ng_local();
4521 rw_wunlock(&pvh_global_lock);
4523 vm_page_free_pages_toq(&free, false);
4527 * This code makes some *MAJOR* assumptions:
4528 * 1. Current pmap & pmap exists.
4531 * 4. No L2 page table pages.
4532 * but is *MUCH* faster than pmap_enter...
4535 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4536 vm_prot_t prot, vm_page_t mpt2pg)
4538 pt2_entry_t *pte2p, pte2;
4540 struct spglist free;
4543 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
4544 (m->oflags & VPO_UNMANAGED) != 0,
4545 ("%s: managed mapping within the clean submap", __func__));
4546 rw_assert(&pvh_global_lock, RA_WLOCKED);
4547 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4550 * In the case that a L2 page table page is not
4551 * resident, we are creating it here.
4553 if (va < VM_MAXUSER_ADDRESS) {
4555 pt1_entry_t pte1, *pte1p;
4559 * Get L1 page table things.
4561 pte1_idx = pte1_index(va);
4562 pte1p = pmap_pte1(pmap, va);
4563 pte1 = pte1_load(pte1p);
4565 if (mpt2pg && (mpt2pg->pindex == (pte1_idx & ~PT2PG_MASK))) {
4567 * Each of NPT2_IN_PG L2 page tables on the page can
4568 * come here. Make sure that associated L1 page table
4569 * link is established.
4571 * QQQ: It comes that we don't establish all links to
4572 * L2 page tables for newly allocated L2 page
4575 KASSERT(!pte1_is_section(pte1),
4576 ("%s: pte1 %#x is section", __func__, pte1));
4577 if (!pte1_is_link(pte1)) {
4578 pt2_pa = page_pt2pa(VM_PAGE_TO_PHYS(mpt2pg),
4580 pte1_store(pte1p, PTE1_LINK(pt2_pa));
4582 pt2_wirecount_inc(mpt2pg, pte1_idx);
4585 * If the L2 page table page is mapped, we just
4586 * increment the hold count, and activate it.
4588 if (pte1_is_section(pte1)) {
4590 } else if (pte1_is_link(pte1)) {
4591 mpt2pg = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
4592 pt2_wirecount_inc(mpt2pg, pte1_idx);
4594 mpt2pg = _pmap_allocpte2(pmap, va,
4595 PMAP_ENTER_NOSLEEP);
4605 * This call to pt2map_entry() makes the assumption that we are
4606 * entering the page into the current pmap. In order to support
4607 * quick entry into any pmap, one would likely use pmap_pte2_quick().
4608 * But that isn't as quick as pt2map_entry().
4610 pte2p = pt2map_entry(va);
4611 pte2 = pte2_load(pte2p);
4612 if (pte2_is_valid(pte2)) {
4613 if (mpt2pg != NULL) {
4615 * Remove extra pte2 reference
4617 pt2_wirecount_dec(mpt2pg, pte1_index(va));
4624 * Enter on the PV list if part of our managed memory.
4626 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4627 !pmap_try_insert_pv_entry(pmap, va, m)) {
4628 if (mpt2pg != NULL) {
4630 if (pmap_unwire_pt2(pmap, va, mpt2pg, &free)) {
4631 pmap_tlb_flush(pmap, va);
4632 vm_page_free_pages_toq(&free, false);
4641 * Increment counters
4643 pmap->pm_stats.resident_count++;
4646 * Now validate mapping with RO protection
4648 pa = VM_PAGE_TO_PHYS(m);
4649 l2prot = PTE2_RO | PTE2_NM;
4650 if (va < VM_MAXUSER_ADDRESS)
4651 l2prot |= PTE2_U | PTE2_NG;
4652 if ((prot & VM_PROT_EXECUTE) == 0)
4654 else if (m->md.pat_mode == VM_MEMATTR_WB_WA && pmap != kernel_pmap) {
4656 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4657 * is set. QQQ: For more info, see comments in pmap_enter().
4659 cache_icache_sync_fresh(va, pa, PAGE_SIZE);
4661 pte2_store(pte2p, PTE2(pa, l2prot, vm_page_pte2_attr(m)));
4667 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4670 rw_wlock(&pvh_global_lock);
4672 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
4673 rw_wunlock(&pvh_global_lock);
4678 * Tries to create a read- and/or execute-only 1 MB page mapping. Returns
4679 * true if successful. Returns false if (1) a mapping already exists at the
4680 * specified virtual address or (2) a PV entry cannot be allocated without
4681 * reclaiming another PV entry.
4684 pmap_enter_1mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4689 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4690 pa = VM_PAGE_TO_PHYS(m);
4691 pte1 = PTE1(pa, PTE1_NM | PTE1_RO, ATTR_TO_L1(vm_page_pte2_attr(m)));
4692 if ((prot & VM_PROT_EXECUTE) == 0)
4694 if (va < VM_MAXUSER_ADDRESS)
4696 if (pmap != kernel_pmap)
4698 return (pmap_enter_pte1(pmap, va, pte1, PMAP_ENTER_NOSLEEP |
4699 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, m) == KERN_SUCCESS);
4703 * Tries to create the specified 1 MB page mapping. Returns KERN_SUCCESS if
4704 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
4705 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
4706 * a mapping already exists at the specified virtual address. Returns
4707 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NORECLAIM was specified and PV entry
4708 * allocation failed.
4711 pmap_enter_pte1(pmap_t pmap, vm_offset_t va, pt1_entry_t pte1, u_int flags,
4714 struct spglist free;
4715 pt1_entry_t opte1, *pte1p;
4716 pt2_entry_t pte2, *pte2p;
4717 vm_offset_t cur, end;
4720 rw_assert(&pvh_global_lock, RA_WLOCKED);
4721 KASSERT((pte1 & (PTE1_NM | PTE1_RO)) == 0 ||
4722 (pte1 & (PTE1_NM | PTE1_RO)) == (PTE1_NM | PTE1_RO),
4723 ("%s: pte1 has inconsistent NM and RO attributes", __func__));
4724 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4725 pte1p = pmap_pte1(pmap, va);
4726 opte1 = pte1_load(pte1p);
4727 if (pte1_is_valid(opte1)) {
4728 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
4729 CTR3(KTR_PMAP, "%s: failure for va %#lx in pmap %p",
4730 __func__, va, pmap);
4731 return (KERN_FAILURE);
4733 /* Break the existing mapping(s). */
4735 if (pte1_is_section(opte1)) {
4737 * If the section resulted from a promotion, then a
4738 * reserved PT page could be freed.
4740 pmap_remove_pte1(pmap, pte1p, va, &free);
4743 end = va + PTE1_SIZE;
4744 for (cur = va, pte2p = pmap_pte2_quick(pmap, va);
4745 cur != end; cur += PAGE_SIZE, pte2p++) {
4746 pte2 = pte2_load(pte2p);
4747 if (!pte2_is_valid(pte2))
4749 if (pmap_remove_pte2(pmap, pte2p, cur, &free))
4754 vm_page_free_pages_toq(&free, false);
4756 if ((m->oflags & VPO_UNMANAGED) == 0) {
4758 * Abort this mapping if its PV entry could not be created.
4760 if (!pmap_pv_insert_pte1(pmap, va, pte1, flags)) {
4761 CTR3(KTR_PMAP, "%s: failure for va %#lx in pmap %p",
4762 __func__, va, pmap);
4763 return (KERN_RESOURCE_SHORTAGE);
4765 if ((pte1 & PTE1_RO) == 0) {
4766 for (mt = m; mt < &m[PTE1_SIZE / PAGE_SIZE]; mt++)
4767 vm_page_aflag_set(mt, PGA_WRITEABLE);
4772 * Increment counters.
4774 if (pte1_is_wired(pte1))
4775 pmap->pm_stats.wired_count += PTE1_SIZE / PAGE_SIZE;
4776 pmap->pm_stats.resident_count += PTE1_SIZE / PAGE_SIZE;
4779 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4780 * is set. QQQ: For more info, see comments in pmap_enter().
4782 if ((pte1 & PTE1_NX) == 0 && m->md.pat_mode == VM_MEMATTR_WB_WA &&
4783 pmap != kernel_pmap && (!pte1_is_section(opte1) ||
4784 pte1_pa(opte1) != VM_PAGE_TO_PHYS(m) || (opte1 & PTE2_NX) != 0))
4785 cache_icache_sync_fresh(va, VM_PAGE_TO_PHYS(m), PTE1_SIZE);
4790 pte1_store(pte1p, pte1);
4792 pmap_pte1_mappings++;
4793 CTR3(KTR_PMAP, "%s: success for va %#lx in pmap %p", __func__, va,
4795 return (KERN_SUCCESS);
4799 * Maps a sequence of resident pages belonging to the same object.
4800 * The sequence begins with the given page m_start. This page is
4801 * mapped at the given virtual address start. Each subsequent page is
4802 * mapped at a virtual address that is offset from start by the same
4803 * amount as the page is offset from m_start within the object. The
4804 * last page in the sequence is the page with the largest offset from
4805 * m_start that can be mapped at a virtual address less than the given
4806 * virtual address end. Not every virtual page between start and end
4807 * is mapped; only those for which a resident page exists with the
4808 * corresponding offset from m_start are mapped.
4811 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4812 vm_page_t m_start, vm_prot_t prot)
4815 vm_page_t m, mpt2pg;
4816 vm_pindex_t diff, psize;
4818 PDEBUG(6, printf("%s: pmap %p start %#x end %#x m %p prot %#x\n",
4819 __func__, pmap, start, end, m_start, prot));
4821 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4822 psize = atop(end - start);
4825 rw_wlock(&pvh_global_lock);
4827 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4828 va = start + ptoa(diff);
4829 if ((va & PTE1_OFFSET) == 0 && va + PTE1_SIZE <= end &&
4830 m->psind == 1 && sp_enabled &&
4831 pmap_enter_1mpage(pmap, va, m, prot))
4832 m = &m[PTE1_SIZE / PAGE_SIZE - 1];
4834 mpt2pg = pmap_enter_quick_locked(pmap, va, m, prot,
4836 m = TAILQ_NEXT(m, listq);
4838 rw_wunlock(&pvh_global_lock);
4843 * This code maps large physical mmap regions into the
4844 * processor address space. Note that some shortcuts
4845 * are taken, but the code works.
4848 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4849 vm_pindex_t pindex, vm_size_t size)
4852 vm_paddr_t pa, pte2_pa;
4854 vm_memattr_t pat_mode;
4855 u_int l1attr, l1prot;
4857 VM_OBJECT_ASSERT_WLOCKED(object);
4858 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4859 ("%s: non-device object", __func__));
4860 if ((addr & PTE1_OFFSET) == 0 && (size & PTE1_OFFSET) == 0) {
4861 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4863 p = vm_page_lookup(object, pindex);
4864 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4865 ("%s: invalid page %p", __func__, p));
4866 pat_mode = p->md.pat_mode;
4869 * Abort the mapping if the first page is not physically
4870 * aligned to a 1MB page boundary.
4872 pte2_pa = VM_PAGE_TO_PHYS(p);
4873 if (pte2_pa & PTE1_OFFSET)
4877 * Skip the first page. Abort the mapping if the rest of
4878 * the pages are not physically contiguous or have differing
4879 * memory attributes.
4881 p = TAILQ_NEXT(p, listq);
4882 for (pa = pte2_pa + PAGE_SIZE; pa < pte2_pa + size;
4884 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4885 ("%s: invalid page %p", __func__, p));
4886 if (pa != VM_PAGE_TO_PHYS(p) ||
4887 pat_mode != p->md.pat_mode)
4889 p = TAILQ_NEXT(p, listq);
4893 * Map using 1MB pages.
4895 * QQQ: Well, we are mapping a section, so same condition must
4896 * be hold like during promotion. It looks that only RW mapping
4897 * is done here, so readonly mapping must be done elsewhere.
4899 l1prot = PTE1_U | PTE1_NG | PTE1_RW | PTE1_M | PTE1_A;
4900 l1attr = ATTR_TO_L1(vm_memattr_to_pte2(pat_mode));
4902 for (pa = pte2_pa; pa < pte2_pa + size; pa += PTE1_SIZE) {
4903 pte1p = pmap_pte1(pmap, addr);
4904 if (!pte1_is_valid(pte1_load(pte1p))) {
4905 pte1_store(pte1p, PTE1(pa, l1prot, l1attr));
4906 pmap->pm_stats.resident_count += PTE1_SIZE /
4908 pmap_pte1_mappings++;
4910 /* Else continue on if the PTE1 is already valid. */
4918 * Do the things to protect a 1mpage in a process.
4921 pmap_protect_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t sva,
4924 pt1_entry_t npte1, opte1;
4925 vm_offset_t eva, va;
4928 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4929 KASSERT((sva & PTE1_OFFSET) == 0,
4930 ("%s: sva is not 1mpage aligned", __func__));
4932 opte1 = npte1 = pte1_load(pte1p);
4933 if (pte1_is_managed(opte1) && pte1_is_dirty(opte1)) {
4934 eva = sva + PTE1_SIZE;
4935 for (va = sva, m = PHYS_TO_VM_PAGE(pte1_pa(opte1));
4936 va < eva; va += PAGE_SIZE, m++)
4939 if ((prot & VM_PROT_WRITE) == 0)
4940 npte1 |= PTE1_RO | PTE1_NM;
4941 if ((prot & VM_PROT_EXECUTE) == 0)
4945 * QQQ: Herein, execute permission is never set.
4946 * It only can be cleared. So, no icache
4947 * syncing is needed.
4950 if (npte1 != opte1) {
4951 pte1_store(pte1p, npte1);
4952 pmap_tlb_flush(pmap, sva);
4957 * Set the physical protection on the
4958 * specified range of this map as requested.
4961 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
4963 boolean_t pv_lists_locked;
4965 pt1_entry_t *pte1p, pte1;
4966 pt2_entry_t *pte2p, opte2, npte2;
4968 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
4969 if (prot == VM_PROT_NONE) {
4970 pmap_remove(pmap, sva, eva);
4974 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
4975 (VM_PROT_WRITE | VM_PROT_EXECUTE))
4978 if (pmap_is_current(pmap))
4979 pv_lists_locked = FALSE;
4981 pv_lists_locked = TRUE;
4983 rw_wlock(&pvh_global_lock);
4988 for (; sva < eva; sva = nextva) {
4990 * Calculate address for next L2 page table.
4992 nextva = pte1_trunc(sva + PTE1_SIZE);
4996 pte1p = pmap_pte1(pmap, sva);
4997 pte1 = pte1_load(pte1p);
5000 * Weed out invalid mappings. Note: we assume that L1 page
5001 * page table is always allocated, and in kernel virtual.
5006 if (pte1_is_section(pte1)) {
5008 * Are we protecting the entire large page? If not,
5009 * demote the mapping and fall through.
5011 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
5012 pmap_protect_pte1(pmap, pte1p, sva, prot);
5015 if (!pv_lists_locked) {
5016 pv_lists_locked = TRUE;
5017 if (!rw_try_wlock(&pvh_global_lock)) {
5023 if (!pmap_demote_pte1(pmap, pte1p, sva)) {
5025 * The large page mapping
5032 /* Update pte1 after demotion */
5033 pte1 = pte1_load(pte1p);
5039 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
5040 " is not link", __func__, pmap, sva, pte1, pte1p));
5043 * Limit our scan to either the end of the va represented
5044 * by the current L2 page table page, or to the end of the
5045 * range being protected.
5050 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva; pte2p++,
5054 opte2 = npte2 = pte2_load(pte2p);
5055 if (!pte2_is_valid(opte2))
5058 if ((prot & VM_PROT_WRITE) == 0) {
5059 if (pte2_is_managed(opte2) &&
5060 pte2_is_dirty(opte2)) {
5061 m = PHYS_TO_VM_PAGE(pte2_pa(opte2));
5064 npte2 |= PTE2_RO | PTE2_NM;
5067 if ((prot & VM_PROT_EXECUTE) == 0)
5071 * QQQ: Herein, execute permission is never set.
5072 * It only can be cleared. So, no icache
5073 * syncing is needed.
5076 if (npte2 != opte2) {
5077 pte2_store(pte2p, npte2);
5078 pmap_tlb_flush(pmap, sva);
5082 if (pv_lists_locked) {
5084 rw_wunlock(&pvh_global_lock);
5090 * pmap_pvh_wired_mappings:
5092 * Return the updated number "count" of managed mappings that are wired.
5095 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
5102 rw_assert(&pvh_global_lock, RA_WLOCKED);
5104 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5107 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5108 if (pte1_is_section(pte1)) {
5109 if (pte1_is_wired(pte1))
5112 KASSERT(pte1_is_link(pte1),
5113 ("%s: pte1 %#x is not link", __func__, pte1));
5114 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5115 if (pte2_is_wired(pte2))
5125 * pmap_page_wired_mappings:
5127 * Return the number of managed mappings to the given physical page
5131 pmap_page_wired_mappings(vm_page_t m)
5136 if ((m->oflags & VPO_UNMANAGED) != 0)
5138 rw_wlock(&pvh_global_lock);
5139 count = pmap_pvh_wired_mappings(&m->md, count);
5140 if ((m->flags & PG_FICTITIOUS) == 0) {
5141 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
5144 rw_wunlock(&pvh_global_lock);
5149 * Returns TRUE if any of the given mappings were used to modify
5150 * physical memory. Otherwise, returns FALSE. Both page and 1mpage
5151 * mappings are supported.
5154 pmap_is_modified_pvh(struct md_page *pvh)
5162 rw_assert(&pvh_global_lock, RA_WLOCKED);
5165 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5168 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5169 if (pte1_is_section(pte1)) {
5170 rv = pte1_is_dirty(pte1);
5172 KASSERT(pte1_is_link(pte1),
5173 ("%s: pte1 %#x is not link", __func__, pte1));
5174 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5175 rv = pte2_is_dirty(pte2);
5188 * Return whether or not the specified physical page was modified
5189 * in any physical maps.
5192 pmap_is_modified(vm_page_t m)
5196 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5197 ("%s: page %p is not managed", __func__, m));
5200 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5201 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
5202 * is clear, no PTE2s can have PG_M set.
5204 VM_OBJECT_ASSERT_WLOCKED(m->object);
5205 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5207 rw_wlock(&pvh_global_lock);
5208 rv = pmap_is_modified_pvh(&m->md) ||
5209 ((m->flags & PG_FICTITIOUS) == 0 &&
5210 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
5211 rw_wunlock(&pvh_global_lock);
5216 * pmap_is_prefaultable:
5218 * Return whether or not the specified virtual address is eligible
5222 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
5230 pte1 = pte1_load(pmap_pte1(pmap, addr));
5231 if (pte1_is_link(pte1)) {
5232 pte2 = pte2_load(pt2map_entry(addr));
5233 rv = !pte2_is_valid(pte2) ;
5240 * Returns TRUE if any of the given mappings were referenced and FALSE
5241 * otherwise. Both page and 1mpage mappings are supported.
5244 pmap_is_referenced_pvh(struct md_page *pvh)
5253 rw_assert(&pvh_global_lock, RA_WLOCKED);
5256 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5259 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5260 if (pte1_is_section(pte1)) {
5261 rv = (pte1 & (PTE1_A | PTE1_V)) == (PTE1_A | PTE1_V);
5263 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5264 rv = (pte2 & (PTE2_A | PTE2_V)) == (PTE2_A | PTE2_V);
5275 * pmap_is_referenced:
5277 * Return whether or not the specified physical page was referenced
5278 * in any physical maps.
5281 pmap_is_referenced(vm_page_t m)
5285 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5286 ("%s: page %p is not managed", __func__, m));
5287 rw_wlock(&pvh_global_lock);
5288 rv = pmap_is_referenced_pvh(&m->md) ||
5289 ((m->flags & PG_FICTITIOUS) == 0 &&
5290 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
5291 rw_wunlock(&pvh_global_lock);
5296 * pmap_ts_referenced:
5298 * Return a count of reference bits for a page, clearing those bits.
5299 * It is not necessary for every reference bit to be cleared, but it
5300 * is necessary that 0 only be returned when there are truly no
5301 * reference bits set.
5303 * As an optimization, update the page's dirty field if a modified bit is
5304 * found while counting reference bits. This opportunistic update can be
5305 * performed at low cost and can eliminate the need for some future calls
5306 * to pmap_is_modified(). However, since this function stops after
5307 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5308 * dirty pages. Those dirty pages will only be detected by a future call
5309 * to pmap_is_modified().
5312 pmap_ts_referenced(vm_page_t m)
5314 struct md_page *pvh;
5317 pt1_entry_t *pte1p, opte1;
5318 pt2_entry_t *pte2p, opte2;
5322 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5323 ("%s: page %p is not managed", __func__, m));
5324 pa = VM_PAGE_TO_PHYS(m);
5325 pvh = pa_to_pvh(pa);
5326 rw_wlock(&pvh_global_lock);
5328 if ((m->flags & PG_FICTITIOUS) != 0 ||
5329 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5330 goto small_mappings;
5335 pte1p = pmap_pte1(pmap, pv->pv_va);
5336 opte1 = pte1_load(pte1p);
5337 if (pte1_is_dirty(opte1)) {
5339 * Although "opte1" is mapping a 1MB page, because
5340 * this function is called at a 4KB page granularity,
5341 * we only update the 4KB page under test.
5345 if ((opte1 & PTE1_A) != 0) {
5347 * Since this reference bit is shared by 256 4KB pages,
5348 * it should not be cleared every time it is tested.
5349 * Apply a simple "hash" function on the physical page
5350 * number, the virtual section number, and the pmap
5351 * address to select one 4KB page out of the 256
5352 * on which testing the reference bit will result
5353 * in clearing that bit. This function is designed
5354 * to avoid the selection of the same 4KB page
5355 * for every 1MB page mapping.
5357 * On demotion, a mapping that hasn't been referenced
5358 * is simply destroyed. To avoid the possibility of a
5359 * subsequent page fault on a demoted wired mapping,
5360 * always leave its reference bit set. Moreover,
5361 * since the section is wired, the current state of
5362 * its reference bit won't affect page replacement.
5364 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PTE1_SHIFT) ^
5365 (uintptr_t)pmap) & (NPTE2_IN_PG - 1)) == 0 &&
5366 !pte1_is_wired(opte1)) {
5367 pte1_clear_bit(pte1p, PTE1_A);
5368 pmap_tlb_flush(pmap, pv->pv_va);
5373 /* Rotate the PV list if it has more than one entry. */
5374 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5375 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5376 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5378 if (rtval >= PMAP_TS_REFERENCED_MAX)
5380 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5382 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5388 pte1p = pmap_pte1(pmap, pv->pv_va);
5389 KASSERT(pte1_is_link(pte1_load(pte1p)),
5390 ("%s: not found a link in page %p's pv list", __func__, m));
5392 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5393 opte2 = pte2_load(pte2p);
5394 if (pte2_is_dirty(opte2))
5396 if ((opte2 & PTE2_A) != 0) {
5397 pte2_clear_bit(pte2p, PTE2_A);
5398 pmap_tlb_flush(pmap, pv->pv_va);
5402 /* Rotate the PV list if it has more than one entry. */
5403 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5404 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5405 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5407 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
5408 PMAP_TS_REFERENCED_MAX);
5411 rw_wunlock(&pvh_global_lock);
5416 * Clear the wired attribute from the mappings for the specified range of
5417 * addresses in the given pmap. Every valid mapping within that range
5418 * must have the wired attribute set. In contrast, invalid mappings
5419 * cannot have the wired attribute set, so they are ignored.
5421 * The wired attribute of the page table entry is not a hardware feature,
5422 * so there is no need to invalidate any TLB entries.
5425 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5428 pt1_entry_t *pte1p, pte1;
5429 pt2_entry_t *pte2p, pte2;
5430 boolean_t pv_lists_locked;
5432 if (pmap_is_current(pmap))
5433 pv_lists_locked = FALSE;
5435 pv_lists_locked = TRUE;
5437 rw_wlock(&pvh_global_lock);
5441 for (; sva < eva; sva = nextva) {
5442 nextva = pte1_trunc(sva + PTE1_SIZE);
5446 pte1p = pmap_pte1(pmap, sva);
5447 pte1 = pte1_load(pte1p);
5450 * Weed out invalid mappings. Note: we assume that L1 page
5451 * page table is always allocated, and in kernel virtual.
5456 if (pte1_is_section(pte1)) {
5457 if (!pte1_is_wired(pte1))
5458 panic("%s: pte1 %#x not wired", __func__, pte1);
5461 * Are we unwiring the entire large page? If not,
5462 * demote the mapping and fall through.
5464 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
5465 pte1_clear_bit(pte1p, PTE1_W);
5466 pmap->pm_stats.wired_count -= PTE1_SIZE /
5470 if (!pv_lists_locked) {
5471 pv_lists_locked = TRUE;
5472 if (!rw_try_wlock(&pvh_global_lock)) {
5479 if (!pmap_demote_pte1(pmap, pte1p, sva))
5480 panic("%s: demotion failed", __func__);
5483 /* Update pte1 after demotion */
5484 pte1 = pte1_load(pte1p);
5490 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
5491 " is not link", __func__, pmap, sva, pte1, pte1p));
5494 * Limit our scan to either the end of the va represented
5495 * by the current L2 page table page, or to the end of the
5496 * range being protected.
5501 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva; pte2p++,
5503 pte2 = pte2_load(pte2p);
5504 if (!pte2_is_valid(pte2))
5506 if (!pte2_is_wired(pte2))
5507 panic("%s: pte2 %#x is missing PTE2_W",
5511 * PTE2_W must be cleared atomically. Although the pmap
5512 * lock synchronizes access to PTE2_W, another processor
5513 * could be changing PTE2_NM and/or PTE2_A concurrently.
5515 pte2_clear_bit(pte2p, PTE2_W);
5516 pmap->pm_stats.wired_count--;
5519 if (pv_lists_locked) {
5521 rw_wunlock(&pvh_global_lock);
5527 * Clear the write and modified bits in each of the given page's mappings.
5530 pmap_remove_write(vm_page_t m)
5532 struct md_page *pvh;
5533 pv_entry_t next_pv, pv;
5536 pt2_entry_t *pte2p, opte2;
5539 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5540 ("%s: page %p is not managed", __func__, m));
5543 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5544 * set by another thread while the object is locked. Thus,
5545 * if PGA_WRITEABLE is clear, no page table entries need updating.
5547 VM_OBJECT_ASSERT_WLOCKED(m->object);
5548 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5550 rw_wlock(&pvh_global_lock);
5552 if ((m->flags & PG_FICTITIOUS) != 0)
5553 goto small_mappings;
5554 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5555 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5559 pte1p = pmap_pte1(pmap, va);
5560 if (!(pte1_load(pte1p) & PTE1_RO))
5561 (void)pmap_demote_pte1(pmap, pte1p, va);
5565 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5568 pte1p = pmap_pte1(pmap, pv->pv_va);
5569 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found"
5570 " a section in page %p's pv list", __func__, m));
5571 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5572 opte2 = pte2_load(pte2p);
5573 if (!(opte2 & PTE2_RO)) {
5574 pte2_store(pte2p, opte2 | PTE2_RO | PTE2_NM);
5575 if (pte2_is_dirty(opte2))
5577 pmap_tlb_flush(pmap, pv->pv_va);
5581 vm_page_aflag_clear(m, PGA_WRITEABLE);
5583 rw_wunlock(&pvh_global_lock);
5587 * Apply the given advice to the specified range of addresses within the
5588 * given pmap. Depending on the advice, clear the referenced and/or
5589 * modified flags in each mapping and set the mapped page's dirty field.
5592 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5594 pt1_entry_t *pte1p, opte1;
5595 pt2_entry_t *pte2p, pte2;
5598 boolean_t pv_lists_locked;
5600 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5602 if (pmap_is_current(pmap))
5603 pv_lists_locked = FALSE;
5605 pv_lists_locked = TRUE;
5607 rw_wlock(&pvh_global_lock);
5611 for (; sva < eva; sva = pdnxt) {
5612 pdnxt = pte1_trunc(sva + PTE1_SIZE);
5615 pte1p = pmap_pte1(pmap, sva);
5616 opte1 = pte1_load(pte1p);
5617 if (!pte1_is_valid(opte1)) /* XXX */
5619 else if (pte1_is_section(opte1)) {
5620 if (!pte1_is_managed(opte1))
5622 if (!pv_lists_locked) {
5623 pv_lists_locked = TRUE;
5624 if (!rw_try_wlock(&pvh_global_lock)) {
5630 if (!pmap_demote_pte1(pmap, pte1p, sva)) {
5632 * The large page mapping was destroyed.
5638 * Unless the page mappings are wired, remove the
5639 * mapping to a single page so that a subsequent
5640 * access may repromote. Since the underlying L2 page
5641 * table is fully populated, this removal never
5642 * frees a L2 page table page.
5644 if (!pte1_is_wired(opte1)) {
5645 pte2p = pmap_pte2_quick(pmap, sva);
5646 KASSERT(pte2_is_valid(pte2_load(pte2p)),
5647 ("%s: invalid PTE2", __func__));
5648 pmap_remove_pte2(pmap, pte2p, sva, NULL);
5653 for (pte2p = pmap_pte2_quick(pmap, sva); sva != pdnxt; pte2p++,
5655 pte2 = pte2_load(pte2p);
5656 if (!pte2_is_valid(pte2) || !pte2_is_managed(pte2))
5658 else if (pte2_is_dirty(pte2)) {
5659 if (advice == MADV_DONTNEED) {
5661 * Future calls to pmap_is_modified()
5662 * can be avoided by making the page
5665 m = PHYS_TO_VM_PAGE(pte2_pa(pte2));
5668 pte2_set_bit(pte2p, PTE2_NM);
5669 pte2_clear_bit(pte2p, PTE2_A);
5670 } else if ((pte2 & PTE2_A) != 0)
5671 pte2_clear_bit(pte2p, PTE2_A);
5674 pmap_tlb_flush(pmap, sva);
5677 if (pv_lists_locked) {
5679 rw_wunlock(&pvh_global_lock);
5685 * Clear the modify bits on the specified physical page.
5688 pmap_clear_modify(vm_page_t m)
5690 struct md_page *pvh;
5691 pv_entry_t next_pv, pv;
5693 pt1_entry_t *pte1p, opte1;
5694 pt2_entry_t *pte2p, opte2;
5697 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5698 ("%s: page %p is not managed", __func__, m));
5699 VM_OBJECT_ASSERT_WLOCKED(m->object);
5700 KASSERT(!vm_page_xbusied(m),
5701 ("%s: page %p is exclusive busy", __func__, m));
5704 * If the page is not PGA_WRITEABLE, then no PTE2s can have PTE2_NM
5705 * cleared. If the object containing the page is locked and the page
5706 * is not exclusive busied, then PGA_WRITEABLE cannot be concurrently
5709 if ((m->flags & PGA_WRITEABLE) == 0)
5711 rw_wlock(&pvh_global_lock);
5713 if ((m->flags & PG_FICTITIOUS) != 0)
5714 goto small_mappings;
5715 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5716 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5720 pte1p = pmap_pte1(pmap, va);
5721 opte1 = pte1_load(pte1p);
5722 if (!(opte1 & PTE1_RO)) {
5723 if (pmap_demote_pte1(pmap, pte1p, va) &&
5724 !pte1_is_wired(opte1)) {
5726 * Write protect the mapping to a
5727 * single page so that a subsequent
5728 * write access may repromote.
5730 va += VM_PAGE_TO_PHYS(m) - pte1_pa(opte1);
5731 pte2p = pmap_pte2_quick(pmap, va);
5732 opte2 = pte2_load(pte2p);
5733 if ((opte2 & PTE2_V)) {
5734 pte2_set_bit(pte2p, PTE2_NM | PTE2_RO);
5736 pmap_tlb_flush(pmap, va);
5743 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5746 pte1p = pmap_pte1(pmap, pv->pv_va);
5747 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found"
5748 " a section in page %p's pv list", __func__, m));
5749 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5750 if (pte2_is_dirty(pte2_load(pte2p))) {
5751 pte2_set_bit(pte2p, PTE2_NM);
5752 pmap_tlb_flush(pmap, pv->pv_va);
5757 rw_wunlock(&pvh_global_lock);
5762 * Sets the memory attribute for the specified page.
5765 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5767 pt2_entry_t *cmap2_pte2p;
5772 oma = m->md.pat_mode;
5773 m->md.pat_mode = ma;
5775 CTR5(KTR_PMAP, "%s: page %p - 0x%08X oma: %d, ma: %d", __func__, m,
5776 VM_PAGE_TO_PHYS(m), oma, ma);
5777 if ((m->flags & PG_FICTITIOUS) != 0)
5781 * If "m" is a normal page, flush it from the cache.
5783 * First, try to find an existing mapping of the page by sf
5784 * buffer. sf_buf_invalidate_cache() modifies mapping and
5785 * flushes the cache.
5787 if (sf_buf_invalidate_cache(m, oma))
5791 * If page is not mapped by sf buffer, map the page
5792 * transient and do invalidation.
5795 pa = VM_PAGE_TO_PHYS(m);
5798 cmap2_pte2p = pc->pc_cmap2_pte2p;
5799 mtx_lock(&pc->pc_cmap_lock);
5800 if (pte2_load(cmap2_pte2p) != 0)
5801 panic("%s: CMAP2 busy", __func__);
5802 pte2_store(cmap2_pte2p, PTE2_KERN_NG(pa, PTE2_AP_KRW,
5803 vm_memattr_to_pte2(ma)));
5804 dcache_wbinv_poc((vm_offset_t)pc->pc_cmap2_addr, pa, PAGE_SIZE);
5805 pte2_clear(cmap2_pte2p);
5806 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5808 mtx_unlock(&pc->pc_cmap_lock);
5813 * Miscellaneous support routines follow
5817 * Returns TRUE if the given page is mapped individually or as part of
5818 * a 1mpage. Otherwise, returns FALSE.
5821 pmap_page_is_mapped(vm_page_t m)
5825 if ((m->oflags & VPO_UNMANAGED) != 0)
5827 rw_wlock(&pvh_global_lock);
5828 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5829 ((m->flags & PG_FICTITIOUS) == 0 &&
5830 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
5831 rw_wunlock(&pvh_global_lock);
5836 * Returns true if the pmap's pv is one of the first
5837 * 16 pvs linked to from this page. This count may
5838 * be changed upwards or downwards in the future; it
5839 * is only necessary that true be returned for a small
5840 * subset of pmaps for proper page aging.
5843 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5845 struct md_page *pvh;
5850 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5851 ("%s: page %p is not managed", __func__, m));
5853 rw_wlock(&pvh_global_lock);
5854 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5855 if (PV_PMAP(pv) == pmap) {
5863 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5864 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5865 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5866 if (PV_PMAP(pv) == pmap) {
5875 rw_wunlock(&pvh_global_lock);
5880 * pmap_zero_page zeros the specified hardware page by mapping
5881 * the page into KVM and using bzero to clear its contents.
5884 pmap_zero_page(vm_page_t m)
5886 pt2_entry_t *cmap2_pte2p;
5891 cmap2_pte2p = pc->pc_cmap2_pte2p;
5892 mtx_lock(&pc->pc_cmap_lock);
5893 if (pte2_load(cmap2_pte2p) != 0)
5894 panic("%s: CMAP2 busy", __func__);
5895 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5896 vm_page_pte2_attr(m)));
5897 pagezero(pc->pc_cmap2_addr);
5898 pte2_clear(cmap2_pte2p);
5899 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5901 mtx_unlock(&pc->pc_cmap_lock);
5905 * pmap_zero_page_area zeros the specified hardware page by mapping
5906 * the page into KVM and using bzero to clear its contents.
5908 * off and size may not cover an area beyond a single hardware page.
5911 pmap_zero_page_area(vm_page_t m, int off, int size)
5913 pt2_entry_t *cmap2_pte2p;
5918 cmap2_pte2p = pc->pc_cmap2_pte2p;
5919 mtx_lock(&pc->pc_cmap_lock);
5920 if (pte2_load(cmap2_pte2p) != 0)
5921 panic("%s: CMAP2 busy", __func__);
5922 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5923 vm_page_pte2_attr(m)));
5924 if (off == 0 && size == PAGE_SIZE)
5925 pagezero(pc->pc_cmap2_addr);
5927 bzero(pc->pc_cmap2_addr + off, size);
5928 pte2_clear(cmap2_pte2p);
5929 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5931 mtx_unlock(&pc->pc_cmap_lock);
5935 * pmap_copy_page copies the specified (machine independent)
5936 * page by mapping the page into virtual memory and using
5937 * bcopy to copy the page, one machine dependent page at a
5941 pmap_copy_page(vm_page_t src, vm_page_t dst)
5943 pt2_entry_t *cmap1_pte2p, *cmap2_pte2p;
5948 cmap1_pte2p = pc->pc_cmap1_pte2p;
5949 cmap2_pte2p = pc->pc_cmap2_pte2p;
5950 mtx_lock(&pc->pc_cmap_lock);
5951 if (pte2_load(cmap1_pte2p) != 0)
5952 panic("%s: CMAP1 busy", __func__);
5953 if (pte2_load(cmap2_pte2p) != 0)
5954 panic("%s: CMAP2 busy", __func__);
5955 pte2_store(cmap1_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(src),
5956 PTE2_AP_KR | PTE2_NM, vm_page_pte2_attr(src)));
5957 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(dst),
5958 PTE2_AP_KRW, vm_page_pte2_attr(dst)));
5959 bcopy(pc->pc_cmap1_addr, pc->pc_cmap2_addr, PAGE_SIZE);
5960 pte2_clear(cmap1_pte2p);
5961 tlb_flush((vm_offset_t)pc->pc_cmap1_addr);
5962 pte2_clear(cmap2_pte2p);
5963 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5965 mtx_unlock(&pc->pc_cmap_lock);
5968 int unmapped_buf_allowed = 1;
5971 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5972 vm_offset_t b_offset, int xfersize)
5974 pt2_entry_t *cmap1_pte2p, *cmap2_pte2p;
5975 vm_page_t a_pg, b_pg;
5977 vm_offset_t a_pg_offset, b_pg_offset;
5983 cmap1_pte2p = pc->pc_cmap1_pte2p;
5984 cmap2_pte2p = pc->pc_cmap2_pte2p;
5985 mtx_lock(&pc->pc_cmap_lock);
5986 if (pte2_load(cmap1_pte2p) != 0)
5987 panic("pmap_copy_pages: CMAP1 busy");
5988 if (pte2_load(cmap2_pte2p) != 0)
5989 panic("pmap_copy_pages: CMAP2 busy");
5990 while (xfersize > 0) {
5991 a_pg = ma[a_offset >> PAGE_SHIFT];
5992 a_pg_offset = a_offset & PAGE_MASK;
5993 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5994 b_pg = mb[b_offset >> PAGE_SHIFT];
5995 b_pg_offset = b_offset & PAGE_MASK;
5996 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5997 pte2_store(cmap1_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(a_pg),
5998 PTE2_AP_KR | PTE2_NM, vm_page_pte2_attr(a_pg)));
5999 tlb_flush_local((vm_offset_t)pc->pc_cmap1_addr);
6000 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(b_pg),
6001 PTE2_AP_KRW, vm_page_pte2_attr(b_pg)));
6002 tlb_flush_local((vm_offset_t)pc->pc_cmap2_addr);
6003 a_cp = pc->pc_cmap1_addr + a_pg_offset;
6004 b_cp = pc->pc_cmap2_addr + b_pg_offset;
6005 bcopy(a_cp, b_cp, cnt);
6010 pte2_clear(cmap1_pte2p);
6011 tlb_flush((vm_offset_t)pc->pc_cmap1_addr);
6012 pte2_clear(cmap2_pte2p);
6013 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
6015 mtx_unlock(&pc->pc_cmap_lock);
6019 pmap_quick_enter_page(vm_page_t m)
6026 pte2p = pc->pc_qmap_pte2p;
6028 KASSERT(pte2_load(pte2p) == 0, ("%s: PTE2 busy", __func__));
6030 pte2_store(pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
6031 vm_page_pte2_attr(m)));
6032 return (pc->pc_qmap_addr);
6036 pmap_quick_remove_page(vm_offset_t addr)
6042 pte2p = pc->pc_qmap_pte2p;
6044 KASSERT(addr == pc->pc_qmap_addr, ("%s: invalid address", __func__));
6045 KASSERT(pte2_load(pte2p) != 0, ("%s: PTE2 not in use", __func__));
6048 tlb_flush(pc->pc_qmap_addr);
6053 * Copy the range specified by src_addr/len
6054 * from the source map to the range dst_addr/len
6055 * in the destination map.
6057 * This routine is only advisory and need not do anything.
6060 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
6061 vm_offset_t src_addr)
6063 struct spglist free;
6065 vm_offset_t end_addr = src_addr + len;
6068 if (dst_addr != src_addr)
6071 if (!pmap_is_current(src_pmap))
6074 rw_wlock(&pvh_global_lock);
6075 if (dst_pmap < src_pmap) {
6076 PMAP_LOCK(dst_pmap);
6077 PMAP_LOCK(src_pmap);
6079 PMAP_LOCK(src_pmap);
6080 PMAP_LOCK(dst_pmap);
6083 for (addr = src_addr; addr < end_addr; addr = nextva) {
6084 pt2_entry_t *src_pte2p, *dst_pte2p;
6085 vm_page_t dst_mpt2pg, src_mpt2pg;
6086 pt1_entry_t src_pte1;
6089 KASSERT(addr < VM_MAXUSER_ADDRESS,
6090 ("%s: invalid to pmap_copy page tables", __func__));
6092 nextva = pte1_trunc(addr + PTE1_SIZE);
6096 pte1_idx = pte1_index(addr);
6097 src_pte1 = src_pmap->pm_pt1[pte1_idx];
6098 if (pte1_is_section(src_pte1)) {
6099 if ((addr & PTE1_OFFSET) != 0 ||
6100 (addr + PTE1_SIZE) > end_addr)
6102 if (dst_pmap->pm_pt1[pte1_idx] == 0 &&
6103 (!pte1_is_managed(src_pte1) ||
6104 pmap_pv_insert_pte1(dst_pmap, addr, src_pte1,
6105 PMAP_ENTER_NORECLAIM))) {
6106 dst_pmap->pm_pt1[pte1_idx] = src_pte1 &
6108 dst_pmap->pm_stats.resident_count +=
6109 PTE1_SIZE / PAGE_SIZE;
6110 pmap_pte1_mappings++;
6113 } else if (!pte1_is_link(src_pte1))
6116 src_mpt2pg = PHYS_TO_VM_PAGE(pte1_link_pa(src_pte1));
6119 * We leave PT2s to be linked from PT1 even if they are not
6120 * referenced until all PT2s in a page are without reference.
6122 * QQQ: It could be changed ...
6124 #if 0 /* single_pt2_link_is_cleared */
6125 KASSERT(pt2_wirecount_get(src_mpt2pg, pte1_idx) > 0,
6126 ("%s: source page table page is unused", __func__));
6128 if (pt2_wirecount_get(src_mpt2pg, pte1_idx) == 0)
6131 if (nextva > end_addr)
6134 src_pte2p = pt2map_entry(addr);
6135 while (addr < nextva) {
6136 pt2_entry_t temp_pte2;
6137 temp_pte2 = pte2_load(src_pte2p);
6139 * we only virtual copy managed pages
6141 if (pte2_is_managed(temp_pte2)) {
6142 dst_mpt2pg = pmap_allocpte2(dst_pmap, addr,
6143 PMAP_ENTER_NOSLEEP);
6144 if (dst_mpt2pg == NULL)
6146 dst_pte2p = pmap_pte2_quick(dst_pmap, addr);
6147 if (!pte2_is_valid(pte2_load(dst_pte2p)) &&
6148 pmap_try_insert_pv_entry(dst_pmap, addr,
6149 PHYS_TO_VM_PAGE(pte2_pa(temp_pte2)))) {
6151 * Clear the wired, modified, and
6152 * accessed (referenced) bits
6155 temp_pte2 &= ~(PTE2_W | PTE2_A);
6156 temp_pte2 |= PTE2_NM;
6157 pte2_store(dst_pte2p, temp_pte2);
6158 dst_pmap->pm_stats.resident_count++;
6161 if (pmap_unwire_pt2(dst_pmap, addr,
6162 dst_mpt2pg, &free)) {
6163 pmap_tlb_flush(dst_pmap, addr);
6164 vm_page_free_pages_toq(&free,
6169 if (pt2_wirecount_get(dst_mpt2pg, pte1_idx) >=
6170 pt2_wirecount_get(src_mpt2pg, pte1_idx))
6179 rw_wunlock(&pvh_global_lock);
6180 PMAP_UNLOCK(src_pmap);
6181 PMAP_UNLOCK(dst_pmap);
6185 * Increase the starting virtual address of the given mapping if a
6186 * different alignment might result in more section mappings.
6189 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6190 vm_offset_t *addr, vm_size_t size)
6192 vm_offset_t pte1_offset;
6194 if (size < PTE1_SIZE)
6196 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6197 offset += ptoa(object->pg_color);
6198 pte1_offset = offset & PTE1_OFFSET;
6199 if (size - ((PTE1_SIZE - pte1_offset) & PTE1_OFFSET) < PTE1_SIZE ||
6200 (*addr & PTE1_OFFSET) == pte1_offset)
6202 if ((*addr & PTE1_OFFSET) < pte1_offset)
6203 *addr = pte1_trunc(*addr) + pte1_offset;
6205 *addr = pte1_roundup(*addr) + pte1_offset;
6209 pmap_activate(struct thread *td)
6211 pmap_t pmap, oldpmap;
6214 PDEBUG(9, printf("%s: td = %08x\n", __func__, (uint32_t)td));
6217 pmap = vmspace_pmap(td->td_proc->p_vmspace);
6218 oldpmap = PCPU_GET(curpmap);
6219 cpuid = PCPU_GET(cpuid);
6222 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
6223 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
6225 CPU_CLR(cpuid, &oldpmap->pm_active);
6226 CPU_SET(cpuid, &pmap->pm_active);
6229 ttb = pmap_ttb_get(pmap);
6232 * pmap_activate is for the current thread on the current cpu
6234 td->td_pcb->pcb_pagedir = ttb;
6236 PCPU_SET(curpmap, pmap);
6241 * Perform the pmap work for mincore.
6244 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
6246 pt1_entry_t *pte1p, pte1;
6247 pt2_entry_t *pte2p, pte2;
6254 pte1p = pmap_pte1(pmap, addr);
6255 pte1 = pte1_load(pte1p);
6256 if (pte1_is_section(pte1)) {
6257 pa = trunc_page(pte1_pa(pte1) | (addr & PTE1_OFFSET));
6258 managed = pte1_is_managed(pte1);
6259 val = MINCORE_SUPER | MINCORE_INCORE;
6260 if (pte1_is_dirty(pte1))
6261 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6263 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6264 } else if (pte1_is_link(pte1)) {
6265 pte2p = pmap_pte2(pmap, addr);
6266 pte2 = pte2_load(pte2p);
6267 pmap_pte2_release(pte2p);
6269 managed = pte2_is_managed(pte2);
6270 val = MINCORE_INCORE;
6271 if (pte2_is_dirty(pte2))
6272 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6274 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6279 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
6280 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
6281 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
6282 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
6285 PA_UNLOCK_COND(*locked_pa);
6291 pmap_kenter_device(vm_offset_t va, vm_size_t size, vm_paddr_t pa)
6296 KASSERT((size & PAGE_MASK) == 0,
6297 ("%s: device mapping not page-sized", __func__));
6300 l2attr = vm_memattr_to_pte2(VM_MEMATTR_DEVICE);
6302 pmap_kenter_prot_attr(va, pa, PTE2_AP_KRW, l2attr);
6307 tlb_flush_range(sva, va - sva);
6311 pmap_kremove_device(vm_offset_t va, vm_size_t size)
6315 KASSERT((size & PAGE_MASK) == 0,
6316 ("%s: device mapping not page-sized", __func__));
6324 tlb_flush_range(sva, va - sva);
6328 pmap_set_pcb_pagedir(pmap_t pmap, struct pcb *pcb)
6331 pcb->pcb_pagedir = pmap_ttb_get(pmap);
6336 * Clean L1 data cache range by physical address.
6337 * The range must be within a single page.
6340 pmap_dcache_wb_pou(vm_paddr_t pa, vm_size_t size, uint32_t attr)
6342 pt2_entry_t *cmap2_pte2p;
6345 KASSERT(((pa & PAGE_MASK) + size) <= PAGE_SIZE,
6346 ("%s: not on single page", __func__));
6350 cmap2_pte2p = pc->pc_cmap2_pte2p;
6351 mtx_lock(&pc->pc_cmap_lock);
6352 if (pte2_load(cmap2_pte2p) != 0)
6353 panic("%s: CMAP2 busy", __func__);
6354 pte2_store(cmap2_pte2p, PTE2_KERN_NG(pa, PTE2_AP_KRW, attr));
6355 dcache_wb_pou((vm_offset_t)pc->pc_cmap2_addr + (pa & PAGE_MASK), size);
6356 pte2_clear(cmap2_pte2p);
6357 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
6359 mtx_unlock(&pc->pc_cmap_lock);
6363 * Sync instruction cache range which is not mapped yet.
6366 cache_icache_sync_fresh(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
6368 uint32_t len, offset;
6371 /* Write back d-cache on given address range. */
6372 offset = pa & PAGE_MASK;
6373 for ( ; size != 0; size -= len, pa += len, offset = 0) {
6374 len = min(PAGE_SIZE - offset, size);
6375 m = PHYS_TO_VM_PAGE(pa);
6376 KASSERT(m != NULL, ("%s: vm_page_t is null for %#x",
6378 pmap_dcache_wb_pou(pa, len, vm_page_pte2_attr(m));
6381 * I-cache is VIPT. Only way how to flush all virtual mappings
6382 * on given physical address is to invalidate all i-cache.
6388 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t size)
6391 /* Write back d-cache on given address range. */
6392 if (va >= VM_MIN_KERNEL_ADDRESS) {
6393 dcache_wb_pou(va, size);
6395 uint32_t len, offset;
6399 offset = va & PAGE_MASK;
6400 for ( ; size != 0; size -= len, va += len, offset = 0) {
6401 pa = pmap_extract(pmap, va); /* offset is preserved */
6402 len = min(PAGE_SIZE - offset, size);
6403 m = PHYS_TO_VM_PAGE(pa);
6404 KASSERT(m != NULL, ("%s: vm_page_t is null for %#x",
6406 pmap_dcache_wb_pou(pa, len, vm_page_pte2_attr(m));
6410 * I-cache is VIPT. Only way how to flush all virtual mappings
6411 * on given physical address is to invalidate all i-cache.
6417 * The implementation of pmap_fault() uses IN_RANGE2() macro which
6418 * depends on the fact that given range size is a power of 2.
6420 CTASSERT(powerof2(NB_IN_PT1));
6421 CTASSERT(powerof2(PT2MAP_SIZE));
6423 #define IN_RANGE2(addr, start, size) \
6424 ((vm_offset_t)(start) == ((vm_offset_t)(addr) & ~((size) - 1)))
6427 * Handle access and R/W emulation faults.
6430 pmap_fault(pmap_t pmap, vm_offset_t far, uint32_t fsr, int idx, bool usermode)
6432 pt1_entry_t *pte1p, pte1;
6433 pt2_entry_t *pte2p, pte2;
6439 * In kernel, we should never get abort with FAR which is in range of
6440 * pmap->pm_pt1 or PT2MAP address spaces. If it happens, stop here
6441 * and print out a useful abort message and even get to the debugger
6442 * otherwise it likely ends with never ending loop of aborts.
6444 if (__predict_false(IN_RANGE2(far, pmap->pm_pt1, NB_IN_PT1))) {
6446 * All L1 tables should always be mapped and present.
6447 * However, we check only current one herein. For user mode,
6448 * only permission abort from malicious user is not fatal.
6449 * And alignment abort as it may have higher priority.
6451 if (!usermode || (idx != FAULT_ALIGN && idx != FAULT_PERM_L2)) {
6452 CTR4(KTR_PMAP, "%s: pmap %#x pm_pt1 %#x far %#x",
6453 __func__, pmap, pmap->pm_pt1, far);
6454 panic("%s: pm_pt1 abort", __func__);
6456 return (KERN_INVALID_ADDRESS);
6458 if (__predict_false(IN_RANGE2(far, PT2MAP, PT2MAP_SIZE))) {
6460 * PT2MAP should be always mapped and present in current
6461 * L1 table. However, only existing L2 tables are mapped
6462 * in PT2MAP. For user mode, only L2 translation abort and
6463 * permission abort from malicious user is not fatal.
6464 * And alignment abort as it may have higher priority.
6466 if (!usermode || (idx != FAULT_ALIGN &&
6467 idx != FAULT_TRAN_L2 && idx != FAULT_PERM_L2)) {
6468 CTR4(KTR_PMAP, "%s: pmap %#x PT2MAP %#x far %#x",
6469 __func__, pmap, PT2MAP, far);
6470 panic("%s: PT2MAP abort", __func__);
6472 return (KERN_INVALID_ADDRESS);
6476 * A pmap lock is used below for handling of access and R/W emulation
6477 * aborts. They were handled by atomic operations before so some
6478 * analysis of new situation is needed to answer the following question:
6479 * Is it safe to use the lock even for these aborts?
6481 * There may happen two cases in general:
6483 * (1) Aborts while the pmap lock is locked already - this should not
6484 * happen as pmap lock is not recursive. However, under pmap lock only
6485 * internal kernel data should be accessed and such data should be
6486 * mapped with A bit set and NM bit cleared. If double abort happens,
6487 * then a mapping of data which has caused it must be fixed. Further,
6488 * all new mappings are always made with A bit set and the bit can be
6489 * cleared only on managed mappings.
6491 * (2) Aborts while another lock(s) is/are locked - this already can
6492 * happen. However, there is no difference here if it's either access or
6493 * R/W emulation abort, or if it's some other abort.
6498 pte1 = pte1_load(pmap_pte1(pmap, far));
6499 if (pte1_is_link(pte1)) {
6501 * Check in advance that associated L2 page table is mapped into
6502 * PT2MAP space. Note that faulty access to not mapped L2 page
6503 * table is caught in more general check above where "far" is
6504 * checked that it does not lay in PT2MAP space. Note also that
6505 * L1 page table and PT2TAB always exist and are mapped.
6507 pte2 = pt2tab_load(pmap_pt2tab_entry(pmap, far));
6508 if (!pte2_is_valid(pte2))
6509 panic("%s: missing L2 page table (%p, %#x)",
6510 __func__, pmap, far);
6515 * Special treatment is due to break-before-make approach done when
6516 * pte1 is updated for userland mapping during section promotion or
6517 * demotion. If not caught here, pmap_enter() can find a section
6518 * mapping on faulting address. That is not allowed.
6520 if (idx == FAULT_TRAN_L1 && usermode && cp15_ats1cur_check(far) == 0) {
6522 return (KERN_SUCCESS);
6526 * Accesss bits for page and section. Note that the entry
6527 * is not in TLB yet, so TLB flush is not necessary.
6529 * QQQ: This is hardware emulation, we do not call userret()
6530 * for aborts from user mode.
6532 if (idx == FAULT_ACCESS_L2) {
6533 pte1 = pte1_load(pmap_pte1(pmap, far));
6534 if (pte1_is_link(pte1)) {
6535 /* L2 page table should exist and be mapped. */
6536 pte2p = pt2map_entry(far);
6537 pte2 = pte2_load(pte2p);
6538 if (pte2_is_valid(pte2)) {
6539 pte2_store(pte2p, pte2 | PTE2_A);
6541 return (KERN_SUCCESS);
6545 * We got L2 access fault but PTE1 is not a link.
6546 * Probably some race happened, do nothing.
6548 CTR3(KTR_PMAP, "%s: FAULT_ACCESS_L2 - pmap %#x far %#x",
6549 __func__, pmap, far);
6551 return (KERN_SUCCESS);
6554 if (idx == FAULT_ACCESS_L1) {
6555 pte1p = pmap_pte1(pmap, far);
6556 pte1 = pte1_load(pte1p);
6557 if (pte1_is_section(pte1)) {
6558 pte1_store(pte1p, pte1 | PTE1_A);
6560 return (KERN_SUCCESS);
6563 * We got L1 access fault but PTE1 is not section
6564 * mapping. Probably some race happened, do nothing.
6566 CTR3(KTR_PMAP, "%s: FAULT_ACCESS_L1 - pmap %#x far %#x",
6567 __func__, pmap, far);
6569 return (KERN_SUCCESS);
6574 * Handle modify bits for page and section. Note that the modify
6575 * bit is emulated by software. So PTEx_RO is software read only
6576 * bit and PTEx_NM flag is real hardware read only bit.
6578 * QQQ: This is hardware emulation, we do not call userret()
6579 * for aborts from user mode.
6581 if ((fsr & FSR_WNR) && (idx == FAULT_PERM_L2)) {
6582 pte1 = pte1_load(pmap_pte1(pmap, far));
6583 if (pte1_is_link(pte1)) {
6584 /* L2 page table should exist and be mapped. */
6585 pte2p = pt2map_entry(far);
6586 pte2 = pte2_load(pte2p);
6587 if (pte2_is_valid(pte2) && !(pte2 & PTE2_RO) &&
6589 pte2_store(pte2p, pte2 & ~PTE2_NM);
6590 tlb_flush(trunc_page(far));
6592 return (KERN_SUCCESS);
6596 * We got L2 permission fault but PTE1 is not a link.
6597 * Probably some race happened, do nothing.
6599 CTR3(KTR_PMAP, "%s: FAULT_PERM_L2 - pmap %#x far %#x",
6600 __func__, pmap, far);
6602 return (KERN_SUCCESS);
6605 if ((fsr & FSR_WNR) && (idx == FAULT_PERM_L1)) {
6606 pte1p = pmap_pte1(pmap, far);
6607 pte1 = pte1_load(pte1p);
6608 if (pte1_is_section(pte1)) {
6609 if (!(pte1 & PTE1_RO) && (pte1 & PTE1_NM)) {
6610 pte1_store(pte1p, pte1 & ~PTE1_NM);
6611 tlb_flush(pte1_trunc(far));
6613 return (KERN_SUCCESS);
6617 * We got L1 permission fault but PTE1 is not section
6618 * mapping. Probably some race happened, do nothing.
6620 CTR3(KTR_PMAP, "%s: FAULT_PERM_L1 - pmap %#x far %#x",
6621 __func__, pmap, far);
6623 return (KERN_SUCCESS);
6628 * QQQ: The previous code, mainly fast handling of access and
6629 * modify bits aborts, could be moved to ASM. Now we are
6630 * starting to deal with not fast aborts.
6633 return (KERN_FAILURE);
6636 #if defined(PMAP_DEBUG)
6638 * Reusing of KVA used in pmap_zero_page function !!!
6641 pmap_zero_page_check(vm_page_t m)
6643 pt2_entry_t *cmap2_pte2p;
6649 cmap2_pte2p = pc->pc_cmap2_pte2p;
6650 mtx_lock(&pc->pc_cmap_lock);
6651 if (pte2_load(cmap2_pte2p) != 0)
6652 panic("%s: CMAP2 busy", __func__);
6653 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
6654 vm_page_pte2_attr(m)));
6655 end = (uint32_t*)(pc->pc_cmap2_addr + PAGE_SIZE);
6656 for (p = (uint32_t*)pc->pc_cmap2_addr; p < end; p++)
6658 panic("%s: page %p not zero, va: %p", __func__, m,
6660 pte2_clear(cmap2_pte2p);
6661 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
6663 mtx_unlock(&pc->pc_cmap_lock);
6667 pmap_pid_dump(int pid)
6674 sx_slock(&allproc_lock);
6675 FOREACH_PROC_IN_SYSTEM(p) {
6676 if (p->p_pid != pid || p->p_vmspace == NULL)
6679 pmap = vmspace_pmap(p->p_vmspace);
6680 for (i = 0; i < NPTE1_IN_PT1; i++) {
6682 pt2_entry_t *pte2p, pte2;
6683 vm_offset_t base, va;
6687 base = i << PTE1_SHIFT;
6688 pte1 = pte1_load(&pmap->pm_pt1[i]);
6690 if (pte1_is_section(pte1)) {
6692 * QQQ: Do something here!
6694 } else if (pte1_is_link(pte1)) {
6695 for (j = 0; j < NPTE2_IN_PT2; j++) {
6696 va = base + (j << PAGE_SHIFT);
6697 if (va >= VM_MIN_KERNEL_ADDRESS) {
6702 sx_sunlock(&allproc_lock);
6705 pte2p = pmap_pte2(pmap, va);
6706 pte2 = pte2_load(pte2p);
6707 pmap_pte2_release(pte2p);
6708 if (!pte2_is_valid(pte2))
6712 m = PHYS_TO_VM_PAGE(pa);
6713 printf("va: 0x%x, pa: 0x%x, w: %d, "
6715 m->wire_count, m->flags);
6728 sx_sunlock(&allproc_lock);
6735 static pt2_entry_t *
6736 pmap_pte2_ddb(pmap_t pmap, vm_offset_t va)
6739 vm_paddr_t pt2pg_pa;
6741 pte1 = pte1_load(pmap_pte1(pmap, va));
6742 if (!pte1_is_link(pte1))
6745 if (pmap_is_current(pmap))
6746 return (pt2map_entry(va));
6748 /* Note that L2 page table size is not equal to PAGE_SIZE. */
6749 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
6750 if (pte2_pa(pte2_load(PMAP3)) != pt2pg_pa) {
6751 pte2_store(PMAP3, PTE2_KPT(pt2pg_pa));
6753 PMAP3cpu = PCPU_GET(cpuid);
6755 tlb_flush_local((vm_offset_t)PADDR3);
6758 else if (PMAP3cpu != PCPU_GET(cpuid)) {
6759 PMAP3cpu = PCPU_GET(cpuid);
6760 tlb_flush_local((vm_offset_t)PADDR3);
6763 return (PADDR3 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
6767 dump_pmap(pmap_t pmap)
6770 printf("pmap %p\n", pmap);
6771 printf(" pm_pt1: %p\n", pmap->pm_pt1);
6772 printf(" pm_pt2tab: %p\n", pmap->pm_pt2tab);
6773 printf(" pm_active: 0x%08lX\n", pmap->pm_active.__bits[0]);
6776 DB_SHOW_COMMAND(pmaps, pmap_list_pmaps)
6780 LIST_FOREACH(pmap, &allpmaps, pm_list) {
6786 pte2_class(pt2_entry_t pte2)
6790 cls = (pte2 >> 2) & 0x03;
6791 cls |= (pte2 >> 4) & 0x04;
6796 dump_section(pmap_t pmap, uint32_t pte1_idx)
6801 dump_link(pmap_t pmap, uint32_t pte1_idx, boolean_t invalid_ok)
6805 pt2_entry_t *pte2p, pte2;
6808 va = pte1_idx << PTE1_SHIFT;
6809 pte2p = pmap_pte2_ddb(pmap, va);
6810 for (i = 0; i < NPTE2_IN_PT2; i++, pte2p++, va += PAGE_SIZE) {
6811 pte2 = pte2_load(pte2p);
6814 if (!pte2_is_valid(pte2)) {
6815 printf(" 0x%08X: 0x%08X", va, pte2);
6817 printf(" - not valid !!!");
6821 m = PHYS_TO_VM_PAGE(pte2_pa(pte2));
6822 printf(" 0x%08X: 0x%08X, TEX%d, s:%d, g:%d, m:%p", va , pte2,
6823 pte2_class(pte2), !!(pte2 & PTE2_S), !(pte2 & PTE2_NG), m);
6825 printf(" v:%d w:%d f:0x%04X\n", m->valid,
6826 m->wire_count, m->flags);
6833 static __inline boolean_t
6834 is_pv_chunk_space(vm_offset_t va)
6837 if ((((vm_offset_t)pv_chunkbase) <= va) &&
6838 (va < ((vm_offset_t)pv_chunkbase + PAGE_SIZE * pv_maxchunks)))
6843 DB_SHOW_COMMAND(pmap, pmap_pmap_print)
6845 /* XXX convert args. */
6846 pmap_t pmap = (pmap_t)addr;
6849 vm_offset_t va, eva;
6852 boolean_t invalid_ok, dump_link_ok, dump_pv_chunk;
6857 LIST_FOREACH(pm, &allpmaps, pm_list)
6858 if (pm == pmap) break;
6860 printf("given pmap %p is not in allpmaps list\n", pmap);
6864 pmap = PCPU_GET(curpmap);
6866 eva = (modif[0] == 'u') ? VM_MAXUSER_ADDRESS : 0xFFFFFFFF;
6867 dump_pv_chunk = FALSE; /* XXX evaluate from modif[] */
6869 printf("pmap: 0x%08X\n", (uint32_t)pmap);
6870 printf("PT2MAP: 0x%08X\n", (uint32_t)PT2MAP);
6871 printf("pt2tab: 0x%08X\n", (uint32_t)pmap->pm_pt2tab);
6873 for(i = 0; i < NPTE1_IN_PT1; i++) {
6874 pte1 = pte1_load(&pmap->pm_pt1[i]);
6877 va = i << PTE1_SHIFT;
6881 if (pte1_is_section(pte1)) {
6882 printf("0x%08X: Section 0x%08X, s:%d g:%d\n", va, pte1,
6883 !!(pte1 & PTE1_S), !(pte1 & PTE1_NG));
6884 dump_section(pmap, i);
6885 } else if (pte1_is_link(pte1)) {
6886 dump_link_ok = TRUE;
6888 pte2 = pte2_load(pmap_pt2tab_entry(pmap, va));
6889 m = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
6890 printf("0x%08X: Link 0x%08X, pt2tab: 0x%08X m: %p",
6892 if (is_pv_chunk_space(va)) {
6893 printf(" - pv_chunk space");
6897 dump_link_ok = FALSE;
6900 printf(" w:%d w2:%u", m->wire_count,
6901 pt2_wirecount_get(m, pte1_index(va)));
6903 printf(" !!! pt2tab entry is ZERO");
6904 else if (pte2_pa(pte1) != pte2_pa(pte2))
6905 printf(" !!! pt2tab entry is DIFFERENT - m: %p",
6906 PHYS_TO_VM_PAGE(pte2_pa(pte2)));
6909 dump_link(pmap, i, invalid_ok);
6911 printf("0x%08X: Invalid entry 0x%08X\n", va, pte1);
6916 dump_pt2tab(pmap_t pmap)
6924 printf("PT2TAB:\n");
6925 for (i = 0; i < PT2TAB_ENTRIES; i++) {
6926 pte2 = pte2_load(&pmap->pm_pt2tab[i]);
6927 if (!pte2_is_valid(pte2))
6929 va = i << PT2TAB_SHIFT;
6931 m = PHYS_TO_VM_PAGE(pa);
6932 printf(" 0x%08X: 0x%08X, TEX%d, s:%d, m:%p", va, pte2,
6933 pte2_class(pte2), !!(pte2 & PTE2_S), m);
6935 printf(" , w: %d, f: 0x%04X pidx: %lld",
6936 m->wire_count, m->flags, m->pindex);
6941 DB_SHOW_COMMAND(pmap_pt2tab, pmap_pt2tab_print)
6943 /* XXX convert args. */
6944 pmap_t pmap = (pmap_t)addr;
6951 printf("supported only on current pmap\n");
6955 pmap = PCPU_GET(curpmap);
6956 printf("curpmap: 0x%08X\n", (uint32_t)pmap);
6957 printf("PT2MAP: 0x%08X\n", (uint32_t)PT2MAP);
6958 printf("pt2tab: 0x%08X\n", (uint32_t)pmap->pm_pt2tab);
6960 start = pte1_index((vm_offset_t)PT2MAP);
6961 for (i = start; i < (start + NPT2_IN_PT2TAB); i++) {
6962 pte1 = pte1_load(&pmap->pm_pt1[i]);
6965 va = i << PTE1_SHIFT;
6966 if (pte1_is_section(pte1)) {
6967 printf("0x%08X: Section 0x%08X, s:%d\n", va, pte1,
6969 dump_section(pmap, i);
6970 } else if (pte1_is_link(pte1)) {
6971 pte2 = pte2_load(pmap_pt2tab_entry(pmap, va));
6972 printf("0x%08X: Link 0x%08X, pt2tab: 0x%08X\n", va,
6975 printf(" !!! pt2tab entry is ZERO\n");
6977 printf("0x%08X: Invalid entry 0x%08X\n", va, pte1);