1 /* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */
3 * Copyright 2004 Olivier Houchard.
4 * Copyright 2003 Wasabi Systems, Inc.
7 * Written by Steve C. Woodford for Wasabi Systems, Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
39 * Copyright (c) 2002-2003 Wasabi Systems, Inc.
40 * Copyright (c) 2001 Richard Earnshaw
41 * Copyright (c) 2001-2002 Christopher Gilbert
42 * All rights reserved.
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. The name of the company nor the name of the author may be used to
50 * endorse or promote products derived from this software without specific
51 * prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
66 * Copyright (c) 1999 The NetBSD Foundation, Inc.
67 * All rights reserved.
69 * This code is derived from software contributed to The NetBSD Foundation
70 * by Charles M. Hannum.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
81 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
82 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
83 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
84 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
85 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
86 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
87 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
88 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
89 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
90 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
91 * POSSIBILITY OF SUCH DAMAGE.
95 * Copyright (c) 1994-1998 Mark Brinicombe.
96 * Copyright (c) 1994 Brini.
97 * All rights reserved.
99 * This code is derived from software written for Brini by Mark Brinicombe
101 * Redistribution and use in source and binary forms, with or without
102 * modification, are permitted provided that the following conditions
104 * 1. Redistributions of source code must retain the above copyright
105 * notice, this list of conditions and the following disclaimer.
106 * 2. Redistributions in binary form must reproduce the above copyright
107 * notice, this list of conditions and the following disclaimer in the
108 * documentation and/or other materials provided with the distribution.
109 * 3. All advertising materials mentioning features or use of this software
110 * must display the following acknowledgement:
111 * This product includes software developed by Mark Brinicombe.
112 * 4. The name of the author may not be used to endorse or promote products
113 * derived from this software without specific prior written permission.
115 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
116 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
117 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
118 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
119 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
120 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
121 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
122 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
123 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
125 * RiscBSD kernel project
129 * Machine dependant vm stuff
135 * Special compilation symbols
136 * PMAP_DEBUG - Build in pmap_debug_level code
138 * Note that pmap_mapdev() and pmap_unmapdev() are implemented in arm/devmap.c
140 /* Include header files */
144 #include <sys/cdefs.h>
145 __FBSDID("$FreeBSD$");
146 #include <sys/param.h>
147 #include <sys/systm.h>
148 #include <sys/kernel.h>
150 #include <sys/lock.h>
151 #include <sys/proc.h>
152 #include <sys/malloc.h>
153 #include <sys/msgbuf.h>
154 #include <sys/mutex.h>
155 #include <sys/vmmeter.h>
156 #include <sys/mman.h>
157 #include <sys/rwlock.h>
159 #include <sys/sched.h>
162 #include <vm/vm_param.h>
165 #include <vm/vm_kern.h>
166 #include <vm/vm_object.h>
167 #include <vm/vm_map.h>
168 #include <vm/vm_page.h>
169 #include <vm/vm_pageout.h>
170 #include <vm/vm_phys.h>
171 #include <vm/vm_extern.h>
173 #include <machine/md_var.h>
174 #include <machine/cpu.h>
175 #include <machine/cpufunc.h>
176 #include <machine/pcb.h>
179 #define PDEBUG(_lev_,_stat_) \
180 if (pmap_debug_level >= (_lev_)) \
182 #define dprintf printf
184 int pmap_debug_level = 0;
186 #else /* PMAP_DEBUG */
187 #define PDEBUG(_lev_,_stat_) /* Nothing */
188 #define dprintf(x, arg...)
189 #define PMAP_INLINE __inline
190 #endif /* PMAP_DEBUG */
192 extern struct pv_addr systempage;
194 extern int last_fault_code;
197 * Internal function prototypes
199 static void pmap_free_pv_entry (pv_entry_t);
200 static pv_entry_t pmap_get_pv_entry(void);
202 static int pmap_enter_locked(pmap_t, vm_offset_t, vm_page_t,
204 static vm_paddr_t pmap_extract_locked(pmap_t pmap, vm_offset_t va);
205 static void pmap_fix_cache(struct vm_page *, pmap_t, vm_offset_t);
206 static void pmap_alloc_l1(pmap_t);
207 static void pmap_free_l1(pmap_t);
209 static int pmap_clearbit(struct vm_page *, u_int);
211 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t);
212 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t);
213 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int);
214 static vm_offset_t kernel_pt_lookup(vm_paddr_t);
216 static MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1");
218 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
219 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
220 vm_offset_t pmap_curmaxkvaddr;
221 vm_paddr_t kernel_l1pa;
223 vm_offset_t kernel_vm_end = 0;
225 vm_offset_t vm_max_kernel_address;
227 struct pmap kernel_pmap_store;
229 static pt_entry_t *csrc_pte, *cdst_pte;
230 static vm_offset_t csrcp, cdstp;
231 static struct mtx cmtx;
233 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *);
235 * These routines are called when the CPU type is identified to set up
236 * the PTE prototypes, cache modes, etc.
238 * The variables are always here, just in case LKMs need to reference
239 * them (though, they shouldn't).
242 pt_entry_t pte_l1_s_cache_mode;
243 pt_entry_t pte_l1_s_cache_mode_pt;
244 pt_entry_t pte_l1_s_cache_mask;
246 pt_entry_t pte_l2_l_cache_mode;
247 pt_entry_t pte_l2_l_cache_mode_pt;
248 pt_entry_t pte_l2_l_cache_mask;
250 pt_entry_t pte_l2_s_cache_mode;
251 pt_entry_t pte_l2_s_cache_mode_pt;
252 pt_entry_t pte_l2_s_cache_mask;
254 pt_entry_t pte_l2_s_prot_u;
255 pt_entry_t pte_l2_s_prot_w;
256 pt_entry_t pte_l2_s_prot_mask;
258 pt_entry_t pte_l1_s_proto;
259 pt_entry_t pte_l1_c_proto;
260 pt_entry_t pte_l2_s_proto;
262 void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t);
263 void (*pmap_copy_page_offs_func)(vm_paddr_t a_phys,
264 vm_offset_t a_offs, vm_paddr_t b_phys, vm_offset_t b_offs,
266 void (*pmap_zero_page_func)(vm_paddr_t, int, int);
268 struct msgbuf *msgbufp = 0;
273 static caddr_t crashdumpmap;
275 extern void bcopy_page(vm_offset_t, vm_offset_t);
276 extern void bzero_page(vm_offset_t);
278 extern vm_offset_t alloc_firstaddr;
283 * Metadata for L1 translation tables.
286 /* Entry on the L1 Table list */
287 SLIST_ENTRY(l1_ttable) l1_link;
289 /* Entry on the L1 Least Recently Used list */
290 TAILQ_ENTRY(l1_ttable) l1_lru;
292 /* Track how many domains are allocated from this L1 */
293 volatile u_int l1_domain_use_count;
296 * A free-list of domain numbers for this L1.
297 * We avoid using ffs() and a bitmap to track domains since ffs()
300 u_int8_t l1_domain_first;
301 u_int8_t l1_domain_free[PMAP_DOMAINS];
303 /* Physical address of this L1 page table */
304 vm_paddr_t l1_physaddr;
306 /* KVA of this L1 page table */
311 * Convert a virtual address into its L1 table index. That is, the
312 * index used to locate the L2 descriptor table pointer in an L1 table.
313 * This is basically used to index l1->l1_kva[].
315 * Each L2 descriptor table represents 1MB of VA space.
317 #define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT)
320 * L1 Page Tables are tracked using a Least Recently Used list.
321 * - New L1s are allocated from the HEAD.
322 * - Freed L1s are added to the TAIl.
323 * - Recently accessed L1s (where an 'access' is some change to one of
324 * the userland pmaps which owns this L1) are moved to the TAIL.
326 static TAILQ_HEAD(, l1_ttable) l1_lru_list;
328 * A list of all L1 tables
330 static SLIST_HEAD(, l1_ttable) l1_list;
331 static struct mtx l1_lru_lock;
334 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots.
336 * This is normally 16MB worth L2 page descriptors for any given pmap.
337 * Reference counts are maintained for L2 descriptors so they can be
341 /* The number of L2 page descriptors allocated to this l2_dtable */
344 /* List of L2 page descriptors */
346 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */
347 vm_paddr_t l2b_phys; /* Physical address of same */
348 u_short l2b_l1idx; /* This L2 table's L1 index */
349 u_short l2b_occupancy; /* How many active descriptors */
350 } l2_bucket[L2_BUCKET_SIZE];
353 /* pmap_kenter_internal flags */
354 #define KENTER_CACHE 0x1
355 #define KENTER_USER 0x2
358 * Given an L1 table index, calculate the corresponding l2_dtable index
359 * and bucket index within the l2_dtable.
361 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \
363 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1))
366 * Given a virtual address, this macro returns the
367 * virtual address required to drop into the next L2 bucket.
369 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE)
372 * We try to map the page tables write-through, if possible. However, not
373 * all CPUs have a write-through cache mode, so on those we have to sync
374 * the cache when we frob page tables.
376 * We try to evaluate this at compile time, if possible. However, it's
377 * not always possible to do that, hence this run-time var.
379 int pmap_needs_pte_sync;
382 * Macro to determine if a mapping might be resident in the
383 * instruction cache and/or TLB
385 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC))
388 * Macro to determine if a mapping might be resident in the
389 * data cache and/or TLB
391 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0)
393 #ifndef PMAP_SHPGPERPROC
394 #define PMAP_SHPGPERPROC 200
397 #define pmap_is_current(pm) ((pm) == pmap_kernel() || \
398 curproc->p_vmspace->vm_map.pmap == (pm))
399 static uma_zone_t pvzone = NULL;
401 static uma_zone_t l2table_zone;
402 static vm_offset_t pmap_kernel_l2dtable_kva;
403 static vm_offset_t pmap_kernel_l2ptp_kva;
404 static vm_paddr_t pmap_kernel_l2ptp_phys;
405 static int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0;
406 static struct rwlock pvh_global_lock;
408 void pmap_copy_page_offs_generic(vm_paddr_t a_phys, vm_offset_t a_offs,
409 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt);
410 #if ARM_MMU_XSCALE == 1
411 void pmap_copy_page_offs_xscale(vm_paddr_t a_phys, vm_offset_t a_offs,
412 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt);
416 * This list exists for the benefit of pmap_map_chunk(). It keeps track
417 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can
418 * find them as necessary.
420 * Note that the data on this list MUST remain valid after initarm() returns,
421 * as pmap_bootstrap() uses it to contruct L2 table metadata.
423 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list);
426 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt)
431 l1->l1_domain_use_count = 0;
432 l1->l1_domain_first = 0;
434 for (i = 0; i < PMAP_DOMAINS; i++)
435 l1->l1_domain_free[i] = i + 1;
438 * Copy the kernel's L1 entries to each new L1.
440 if (l1pt != pmap_kernel()->pm_l1->l1_kva)
441 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE);
443 if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0)
444 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt);
445 SLIST_INSERT_HEAD(&l1_list, l1, l1_link);
446 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
450 kernel_pt_lookup(vm_paddr_t pa)
454 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) {
461 #if ARM_MMU_GENERIC != 0
463 pmap_pte_init_generic(void)
466 pte_l1_s_cache_mode = L1_S_B|L1_S_C;
467 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic;
469 pte_l2_l_cache_mode = L2_B|L2_C;
470 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic;
472 pte_l2_s_cache_mode = L2_B|L2_C;
473 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic;
476 * If we have a write-through cache, set B and C. If
477 * we have a write-back cache, then we assume setting
478 * only C will make those pages write-through.
480 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) {
481 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
482 pte_l2_l_cache_mode_pt = L2_B|L2_C;
483 pte_l2_s_cache_mode_pt = L2_B|L2_C;
485 pte_l1_s_cache_mode_pt = L1_S_C;
486 pte_l2_l_cache_mode_pt = L2_C;
487 pte_l2_s_cache_mode_pt = L2_C;
490 pte_l2_s_prot_u = L2_S_PROT_U_generic;
491 pte_l2_s_prot_w = L2_S_PROT_W_generic;
492 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic;
494 pte_l1_s_proto = L1_S_PROTO_generic;
495 pte_l1_c_proto = L1_C_PROTO_generic;
496 pte_l2_s_proto = L2_S_PROTO_generic;
498 pmap_copy_page_func = pmap_copy_page_generic;
499 pmap_copy_page_offs_func = pmap_copy_page_offs_generic;
500 pmap_zero_page_func = pmap_zero_page_generic;
503 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH)
505 pmap_pte_init_arm9(void)
509 * ARM9 is compatible with generic, but we want to use
510 * write-through caching for now.
512 pmap_pte_init_generic();
514 pte_l1_s_cache_mode = L1_S_C;
515 pte_l2_l_cache_mode = L2_C;
516 pte_l2_s_cache_mode = L2_C;
518 pte_l1_s_cache_mode_pt = L1_S_C;
519 pte_l2_l_cache_mode_pt = L2_C;
520 pte_l2_s_cache_mode_pt = L2_C;
522 #endif /* CPU_ARM9 */
523 #endif /* ARM_MMU_GENERIC != 0 */
525 #if defined(CPU_ARM10)
527 pmap_pte_init_arm10(void)
531 * ARM10 is compatible with generic, but we want to use
532 * write-through caching for now.
534 pmap_pte_init_generic();
536 pte_l1_s_cache_mode = L1_S_B | L1_S_C;
537 pte_l2_l_cache_mode = L2_B | L2_C;
538 pte_l2_s_cache_mode = L2_B | L2_C;
540 pte_l1_s_cache_mode_pt = L1_S_C;
541 pte_l2_l_cache_mode_pt = L2_C;
542 pte_l2_s_cache_mode_pt = L2_C;
545 #endif /* CPU_ARM10 */
547 #if ARM_MMU_XSCALE == 1
548 #if (ARM_NMMUS > 1) || defined (CPU_XSCALE_CORE3)
549 static u_int xscale_use_minidata;
553 pmap_pte_init_xscale(void)
556 int write_through = 0;
558 pte_l1_s_cache_mode = L1_S_B|L1_S_C|L1_S_XSCALE_P;
559 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale;
561 pte_l2_l_cache_mode = L2_B|L2_C;
562 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale;
564 pte_l2_s_cache_mode = L2_B|L2_C;
565 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale;
567 pte_l1_s_cache_mode_pt = L1_S_C;
568 pte_l2_l_cache_mode_pt = L2_C;
569 pte_l2_s_cache_mode_pt = L2_C;
570 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE
572 * The XScale core has an enhanced mode where writes that
573 * miss the cache cause a cache line to be allocated. This
574 * is significantly faster than the traditional, write-through
575 * behavior of this case.
577 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X);
578 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X);
579 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X);
580 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */
581 #ifdef XSCALE_CACHE_WRITE_THROUGH
583 * Some versions of the XScale core have various bugs in
584 * their cache units, the work-around for which is to run
585 * the cache in write-through mode. Unfortunately, this
586 * has a major (negative) impact on performance. So, we
587 * go ahead and run fast-and-loose, in the hopes that we
588 * don't line up the planets in a way that will trip the
591 * However, we give you the option to be slow-but-correct.
594 #elif defined(XSCALE_CACHE_WRITE_BACK)
595 /* force write back cache mode */
597 #elif defined(CPU_XSCALE_PXA2X0)
599 * Intel PXA2[15]0 processors are known to have a bug in
600 * write-back cache on revision 4 and earlier (stepping
601 * A[01] and B[012]). Fixed for C0 and later.
607 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK);
609 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) {
610 if ((id & CPU_ID_REVISION_MASK) < 5) {
611 /* write through for stepping A0-1 and B0-2 */
616 #endif /* XSCALE_CACHE_WRITE_THROUGH */
619 pte_l1_s_cache_mode = L1_S_C;
620 pte_l2_l_cache_mode = L2_C;
621 pte_l2_s_cache_mode = L2_C;
625 xscale_use_minidata = 1;
628 pte_l2_s_prot_u = L2_S_PROT_U_xscale;
629 pte_l2_s_prot_w = L2_S_PROT_W_xscale;
630 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale;
632 pte_l1_s_proto = L1_S_PROTO_xscale;
633 pte_l1_c_proto = L1_C_PROTO_xscale;
634 pte_l2_s_proto = L2_S_PROTO_xscale;
636 #ifdef CPU_XSCALE_CORE3
637 pmap_copy_page_func = pmap_copy_page_generic;
638 pmap_copy_page_offs_func = pmap_copy_page_offs_generic;
639 pmap_zero_page_func = pmap_zero_page_generic;
640 xscale_use_minidata = 0;
641 /* Make sure it is L2-cachable */
642 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_T);
643 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode &~ L1_S_XSCALE_P;
644 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_T) ;
645 pte_l2_l_cache_mode_pt = pte_l1_s_cache_mode;
646 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_T);
647 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode;
650 pmap_copy_page_func = pmap_copy_page_xscale;
651 pmap_copy_page_offs_func = pmap_copy_page_offs_xscale;
652 pmap_zero_page_func = pmap_zero_page_xscale;
656 * Disable ECC protection of page table access, for now.
658 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
659 auxctl &= ~XSCALE_AUXCTL_P;
660 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
664 * xscale_setup_minidata:
666 * Set up the mini-data cache clean area. We require the
667 * caller to allocate the right amount of physically and
668 * virtually contiguous space.
670 extern vm_offset_t xscale_minidata_clean_addr;
671 extern vm_size_t xscale_minidata_clean_size; /* already initialized */
673 xscale_setup_minidata(vm_offset_t l1pt, vm_offset_t va, vm_paddr_t pa)
675 pd_entry_t *pde = (pd_entry_t *) l1pt;
680 xscale_minidata_clean_addr = va;
682 /* Round it to page size. */
683 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME;
686 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) {
687 pte = (pt_entry_t *) kernel_pt_lookup(
688 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
690 panic("xscale_setup_minidata: can't find L2 table for "
691 "VA 0x%08x", (u_int32_t) va);
692 pte[l2pte_index(va)] =
693 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
694 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X);
698 * Configure the mini-data cache for write-back with
699 * read/write-allocate.
701 * NOTE: In order to reconfigure the mini-data cache, we must
702 * make sure it contains no valid data! In order to do that,
703 * we must issue a global data cache invalidate command!
705 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED!
706 * THIS IS VERY IMPORTANT!
709 /* Invalidate data and mini-data. */
710 __asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
711 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
712 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA;
713 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
718 * Allocate an L1 translation table for the specified pmap.
719 * This is called at pmap creation time.
722 pmap_alloc_l1(pmap_t pm)
724 struct l1_ttable *l1;
728 * Remove the L1 at the head of the LRU list
730 mtx_lock(&l1_lru_lock);
731 l1 = TAILQ_FIRST(&l1_lru_list);
732 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
735 * Pick the first available domain number, and update
736 * the link to the next number.
738 domain = l1->l1_domain_first;
739 l1->l1_domain_first = l1->l1_domain_free[domain];
742 * If there are still free domain numbers in this L1,
743 * put it back on the TAIL of the LRU list.
745 if (++l1->l1_domain_use_count < PMAP_DOMAINS)
746 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
748 mtx_unlock(&l1_lru_lock);
751 * Fix up the relevant bits in the pmap structure
754 pm->pm_domain = domain + 1;
758 * Free an L1 translation table.
759 * This is called at pmap destruction time.
762 pmap_free_l1(pmap_t pm)
764 struct l1_ttable *l1 = pm->pm_l1;
766 mtx_lock(&l1_lru_lock);
769 * If this L1 is currently on the LRU list, remove it.
771 if (l1->l1_domain_use_count < PMAP_DOMAINS)
772 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
775 * Free up the domain number which was allocated to the pmap
777 l1->l1_domain_free[pm->pm_domain - 1] = l1->l1_domain_first;
778 l1->l1_domain_first = pm->pm_domain - 1;
779 l1->l1_domain_use_count--;
782 * The L1 now must have at least 1 free domain, so add
783 * it back to the LRU list. If the use count is zero,
784 * put it at the head of the list, otherwise it goes
787 if (l1->l1_domain_use_count == 0) {
788 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru);
790 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
792 mtx_unlock(&l1_lru_lock);
796 * Returns a pointer to the L2 bucket associated with the specified pmap
797 * and VA, or NULL if no L2 bucket exists for the address.
799 static PMAP_INLINE struct l2_bucket *
800 pmap_get_l2_bucket(pmap_t pm, vm_offset_t va)
802 struct l2_dtable *l2;
803 struct l2_bucket *l2b;
808 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL ||
809 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL)
816 * Returns a pointer to the L2 bucket associated with the specified pmap
819 * If no L2 bucket exists, perform the necessary allocations to put an L2
820 * bucket/page table in place.
822 * Note that if a new L2 bucket/page was allocated, the caller *must*
823 * increment the bucket occupancy counter appropriately *before*
824 * releasing the pmap's lock to ensure no other thread or cpu deallocates
825 * the bucket/page in the meantime.
827 static struct l2_bucket *
828 pmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va)
830 struct l2_dtable *l2;
831 struct l2_bucket *l2b;
836 PMAP_ASSERT_LOCKED(pm);
837 rw_assert(&pvh_global_lock, RA_WLOCKED);
838 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
840 * No mapping at this address, as there is
841 * no entry in the L1 table.
842 * Need to allocate a new l2_dtable.
845 rw_wunlock(&pvh_global_lock);
846 if ((l2 = uma_zalloc(l2table_zone, M_NOWAIT)) == NULL) {
847 rw_wlock(&pvh_global_lock);
851 rw_wlock(&pvh_global_lock);
853 if (pm->pm_l2[L2_IDX(l1idx)] != NULL) {
855 * Someone already allocated the l2_dtable while
856 * we were doing the same.
858 uma_zfree(l2table_zone, l2);
859 l2 = pm->pm_l2[L2_IDX(l1idx)];
861 bzero(l2, sizeof(*l2));
863 * Link it into the parent pmap
865 pm->pm_l2[L2_IDX(l1idx)] = l2;
869 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
872 * Fetch pointer to the L2 page table associated with the address.
874 if (l2b->l2b_kva == NULL) {
878 * No L2 page table has been allocated. Chances are, this
879 * is because we just allocated the l2_dtable, above.
882 rw_wunlock(&pvh_global_lock);
883 ptep = uma_zalloc(l2zone, M_NOWAIT);
884 rw_wlock(&pvh_global_lock);
886 if (l2b->l2b_kva != 0) {
887 /* We lost the race. */
888 uma_zfree(l2zone, ptep);
891 l2b->l2b_phys = vtophys(ptep);
894 * Oops, no more L2 page tables available at this
895 * time. We may need to deallocate the l2_dtable
896 * if we allocated a new one above.
898 if (l2->l2_occupancy == 0) {
899 pm->pm_l2[L2_IDX(l1idx)] = NULL;
900 uma_zfree(l2table_zone, l2);
907 l2b->l2b_l1idx = l1idx;
913 static PMAP_INLINE void
914 #ifndef PMAP_INCLUDE_PTE_SYNC
915 pmap_free_l2_ptp(pt_entry_t *l2)
917 pmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2)
920 #ifdef PMAP_INCLUDE_PTE_SYNC
922 * Note: With a write-back cache, we may need to sync this
923 * L2 table before re-using it.
924 * This is because it may have belonged to a non-current
925 * pmap, in which case the cache syncs would have been
926 * skipped when the pages were being unmapped. If the
927 * L2 table were then to be immediately re-allocated to
928 * the *current* pmap, it may well contain stale mappings
929 * which have not yet been cleared by a cache write-back
930 * and so would still be visible to the mmu.
933 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
935 uma_zfree(l2zone, l2);
938 * One or more mappings in the specified L2 descriptor table have just been
941 * Garbage collect the metadata and descriptor table itself if necessary.
943 * The pmap lock must be acquired when this is called (not necessary
944 * for the kernel pmap).
947 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count)
949 struct l2_dtable *l2;
950 pd_entry_t *pl1pd, l1pd;
956 * Update the bucket's reference count according to how many
957 * PTEs the caller has just invalidated.
959 l2b->l2b_occupancy -= count;
964 * Level 2 page tables allocated to the kernel pmap are never freed
965 * as that would require checking all Level 1 page tables and
966 * removing any references to the Level 2 page table. See also the
967 * comment elsewhere about never freeing bootstrap L2 descriptors.
969 * We make do with just invalidating the mapping in the L2 table.
971 * This isn't really a big deal in practice and, in fact, leads
972 * to a performance win over time as we don't need to continually
975 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel())
979 * There are no more valid mappings in this level 2 page table.
980 * Go ahead and NULL-out the pointer in the bucket, then
981 * free the page table.
983 l1idx = l2b->l2b_l1idx;
987 pl1pd = &pm->pm_l1->l1_kva[l1idx];
990 * If the L1 slot matches the pmap's domain
991 * number, then invalidate it.
993 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK);
994 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) {
1000 * Release the L2 descriptor table back to the pool cache.
1002 #ifndef PMAP_INCLUDE_PTE_SYNC
1003 pmap_free_l2_ptp(ptep);
1005 pmap_free_l2_ptp(!pmap_is_current(pm), ptep);
1009 * Update the reference count in the associated l2_dtable
1011 l2 = pm->pm_l2[L2_IDX(l1idx)];
1012 if (--l2->l2_occupancy > 0)
1016 * There are no more valid mappings in any of the Level 1
1017 * slots managed by this l2_dtable. Go ahead and NULL-out
1018 * the pointer in the parent pmap and free the l2_dtable.
1020 pm->pm_l2[L2_IDX(l1idx)] = NULL;
1021 uma_zfree(l2table_zone, l2);
1025 * Pool cache constructors for L2 descriptor tables, metadata and pmap
1029 pmap_l2ptp_ctor(void *mem, int size, void *arg, int flags)
1031 #ifndef PMAP_INCLUDE_PTE_SYNC
1032 struct l2_bucket *l2b;
1033 pt_entry_t *ptep, pte;
1035 vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK;
1038 * The mappings for these page tables were initially made using
1039 * pmap_kenter() by the pool subsystem. Therefore, the cache-
1040 * mode will not be right for page table mappings. To avoid
1041 * polluting the pmap_kenter() code with a special case for
1042 * page tables, we simply fix up the cache-mode here if it's not
1045 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
1046 ptep = &l2b->l2b_kva[l2pte_index(va)];
1049 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
1051 * Page tables must have the cache-mode set to
1054 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
1056 cpu_tlb_flushD_SE(va);
1060 memset(mem, 0, L2_TABLE_SIZE_REAL);
1061 PTE_SYNC_RANGE(mem, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
1066 * A bunch of routines to conditionally flush the caches/TLB depending
1067 * on whether the specified pmap actually needs to be flushed at any
1070 static PMAP_INLINE void
1071 pmap_tlb_flushID_SE(pmap_t pm, vm_offset_t va)
1074 if (pmap_is_current(pm))
1075 cpu_tlb_flushID_SE(va);
1078 static PMAP_INLINE void
1079 pmap_tlb_flushD_SE(pmap_t pm, vm_offset_t va)
1082 if (pmap_is_current(pm))
1083 cpu_tlb_flushD_SE(va);
1086 static PMAP_INLINE void
1087 pmap_tlb_flushID(pmap_t pm)
1090 if (pmap_is_current(pm))
1093 static PMAP_INLINE void
1094 pmap_tlb_flushD(pmap_t pm)
1097 if (pmap_is_current(pm))
1102 pmap_has_valid_mapping(pmap_t pm, vm_offset_t va)
1107 if (pmap_get_pde_pte(pm, va, &pde, &ptep) &&
1108 ptep && ((*ptep & L2_TYPE_MASK) != L2_TYPE_INV))
1114 static PMAP_INLINE void
1115 pmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len)
1119 CTR4(KTR_PMAP, "pmap_dcache_wbinv_range: pmap %p is_kernel %d va 0x%08x"
1120 " len 0x%x ", pm, pm == pmap_kernel(), va, len);
1122 if (pmap_is_current(pm) || pm == pmap_kernel()) {
1123 rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len);
1125 if (pmap_has_valid_mapping(pm, va)) {
1126 cpu_idcache_wbinv_range(va, rest);
1127 cpu_l2cache_wbinv_range(va, rest);
1131 rest = MIN(PAGE_SIZE, len);
1136 static PMAP_INLINE void
1137 pmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len, boolean_t do_inv,
1142 CTR4(KTR_PMAP, "pmap_dcache_wb_range: pmap %p is_kernel %d va 0x%08x "
1143 "len 0x%x ", pm, pm == pmap_kernel(), va, len);
1144 CTR2(KTR_PMAP, " do_inv %d rd_only %d", do_inv, rd_only);
1146 if (pmap_is_current(pm)) {
1147 rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len);
1149 if (pmap_has_valid_mapping(pm, va)) {
1150 if (do_inv && rd_only) {
1151 cpu_dcache_inv_range(va, rest);
1152 cpu_l2cache_inv_range(va, rest);
1153 } else if (do_inv) {
1154 cpu_dcache_wbinv_range(va, rest);
1155 cpu_l2cache_wbinv_range(va, rest);
1156 } else if (!rd_only) {
1157 cpu_dcache_wb_range(va, rest);
1158 cpu_l2cache_wb_range(va, rest);
1164 rest = MIN(PAGE_SIZE, len);
1169 static PMAP_INLINE void
1170 pmap_idcache_wbinv_all(pmap_t pm)
1173 if (pmap_is_current(pm)) {
1174 cpu_idcache_wbinv_all();
1175 cpu_l2cache_wbinv_all();
1180 static PMAP_INLINE void
1181 pmap_dcache_wbinv_all(pmap_t pm)
1184 if (pmap_is_current(pm)) {
1185 cpu_dcache_wbinv_all();
1186 cpu_l2cache_wbinv_all();
1194 * Make sure the pte is written out to RAM.
1195 * We need to do this for one of two cases:
1196 * - We're dealing with the kernel pmap
1197 * - There is no pmap active in the cache/tlb.
1198 * - The specified pmap is 'active' in the cache/tlb.
1200 #ifdef PMAP_INCLUDE_PTE_SYNC
1201 #define PTE_SYNC_CURRENT(pm, ptep) \
1203 if (PMAP_NEEDS_PTE_SYNC && \
1204 pmap_is_current(pm)) \
1206 } while (/*CONSTCOND*/0)
1208 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */
1212 * cacheable == -1 means we must make the entry uncacheable, 1 means
1215 static __inline void
1216 pmap_set_cache_entry(pv_entry_t pv, pmap_t pm, vm_offset_t va, int cacheable)
1218 struct l2_bucket *l2b;
1219 pt_entry_t *ptep, pte;
1221 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
1222 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
1224 if (cacheable == 1) {
1225 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode;
1226 if (l2pte_valid(pte)) {
1227 if (PV_BEEN_EXECD(pv->pv_flags)) {
1228 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va);
1229 } else if (PV_BEEN_REFD(pv->pv_flags)) {
1230 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va);
1234 pte = *ptep &~ L2_S_CACHE_MASK;
1235 if ((va != pv->pv_va || pm != pv->pv_pmap) &&
1237 if (PV_BEEN_EXECD(pv->pv_flags)) {
1238 pmap_idcache_wbinv_range(pv->pv_pmap,
1239 pv->pv_va, PAGE_SIZE);
1240 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va);
1241 } else if (PV_BEEN_REFD(pv->pv_flags)) {
1242 pmap_dcache_wb_range(pv->pv_pmap,
1243 pv->pv_va, PAGE_SIZE, TRUE,
1244 (pv->pv_flags & PVF_WRITE) == 0);
1245 pmap_tlb_flushD_SE(pv->pv_pmap,
1251 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
1255 pmap_fix_cache(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1258 int writable = 0, kwritable = 0, uwritable = 0;
1259 int entries = 0, kentries = 0, uentries = 0;
1260 struct pv_entry *pv;
1262 rw_assert(&pvh_global_lock, RA_WLOCKED);
1264 /* the cache gets written back/invalidated on context switch.
1265 * therefore, if a user page shares an entry in the same page or
1266 * with the kernel map and at least one is writable, then the
1267 * cache entry must be set write-through.
1270 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1271 /* generate a count of the pv_entry uses */
1272 if (pv->pv_flags & PVF_WRITE) {
1273 if (pv->pv_pmap == pmap_kernel())
1275 else if (pv->pv_pmap == pm)
1279 if (pv->pv_pmap == pmap_kernel())
1282 if (pv->pv_pmap == pm)
1288 * check if the user duplicate mapping has
1291 if ((pm != pmap_kernel()) && (((uentries > 1) && uwritable) ||
1295 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1296 /* check for user uncachable conditions - order is important */
1297 if (pm != pmap_kernel() &&
1298 (pv->pv_pmap == pm || pv->pv_pmap == pmap_kernel())) {
1300 if ((uentries > 1 && uwritable) || uwritable > 1) {
1302 /* user duplicate mapping */
1303 if (pv->pv_pmap != pmap_kernel())
1304 pv->pv_flags |= PVF_MWC;
1306 if (!(pv->pv_flags & PVF_NC)) {
1307 pv->pv_flags |= PVF_NC;
1308 pmap_set_cache_entry(pv, pm, va, -1);
1311 } else /* no longer a duplicate user */
1312 pv->pv_flags &= ~PVF_MWC;
1316 * check for kernel uncachable conditions
1317 * kernel writable or kernel readable with writable user entry
1319 if ((kwritable && (entries || kentries > 1)) ||
1321 ((kwritable != writable) && kentries &&
1322 (pv->pv_pmap == pmap_kernel() ||
1323 (pv->pv_flags & PVF_WRITE) ||
1324 (pv->pv_flags & PVF_MWC)))) {
1326 if (!(pv->pv_flags & PVF_NC)) {
1327 pv->pv_flags |= PVF_NC;
1328 pmap_set_cache_entry(pv, pm, va, -1);
1333 /* kernel and user are cachable */
1334 if ((pm == pmap_kernel()) && !(pv->pv_flags & PVF_MWC) &&
1335 (pv->pv_flags & PVF_NC)) {
1337 pv->pv_flags &= ~PVF_NC;
1338 if (pg->md.pv_memattr != VM_MEMATTR_UNCACHEABLE)
1339 pmap_set_cache_entry(pv, pm, va, 1);
1342 /* user is no longer sharable and writable */
1343 if (pm != pmap_kernel() &&
1344 (pv->pv_pmap == pm || pv->pv_pmap == pmap_kernel()) &&
1345 !pmwc && (pv->pv_flags & PVF_NC)) {
1347 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1348 if (pg->md.pv_memattr != VM_MEMATTR_UNCACHEABLE)
1349 pmap_set_cache_entry(pv, pm, va, 1);
1353 if ((kwritable == 0) && (writable == 0)) {
1354 pg->md.pvh_attrs &= ~PVF_MOD;
1355 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1361 * Modify pte bits for all ptes corresponding to the given physical address.
1362 * We use `maskbits' rather than `clearbits' because we're always passing
1363 * constants and the latter would require an extra inversion at run-time.
1366 pmap_clearbit(struct vm_page *pg, u_int maskbits)
1368 struct l2_bucket *l2b;
1369 struct pv_entry *pv;
1370 pt_entry_t *ptep, npte, opte;
1376 rw_wlock(&pvh_global_lock);
1378 if (maskbits & PVF_WRITE)
1379 maskbits |= PVF_MOD;
1381 * Clear saved attributes (modify, reference)
1383 pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF));
1385 if (TAILQ_EMPTY(&pg->md.pv_list)) {
1386 rw_wunlock(&pvh_global_lock);
1391 * Loop over all current mappings setting/clearing as appropos
1393 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1396 oflags = pv->pv_flags;
1398 if (!(oflags & maskbits)) {
1399 if ((maskbits & PVF_WRITE) && (pv->pv_flags & PVF_NC)) {
1400 if (pg->md.pv_memattr !=
1401 VM_MEMATTR_UNCACHEABLE) {
1403 l2b = pmap_get_l2_bucket(pm, va);
1404 ptep = &l2b->l2b_kva[l2pte_index(va)];
1405 *ptep |= pte_l2_s_cache_mode;
1409 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1413 pv->pv_flags &= ~maskbits;
1417 l2b = pmap_get_l2_bucket(pm, va);
1419 ptep = &l2b->l2b_kva[l2pte_index(va)];
1420 npte = opte = *ptep;
1422 if (maskbits & (PVF_WRITE|PVF_MOD)) {
1423 if ((pv->pv_flags & PVF_NC)) {
1425 * Entry is not cacheable:
1427 * Don't turn caching on again if this is a
1428 * modified emulation. This would be
1429 * inconsitent with the settings created by
1430 * pmap_fix_cache(). Otherwise, it's safe
1431 * to re-enable cacheing.
1433 * There's no need to call pmap_fix_cache()
1434 * here: all pages are losing their write
1437 if (maskbits & PVF_WRITE) {
1438 if (pg->md.pv_memattr !=
1439 VM_MEMATTR_UNCACHEABLE)
1440 npte |= pte_l2_s_cache_mode;
1441 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1444 if (opte & L2_S_PROT_W) {
1447 * Entry is writable/cacheable: check if pmap
1448 * is current if it is flush it, otherwise it
1449 * won't be in the cache
1451 if (PV_BEEN_EXECD(oflags))
1452 pmap_idcache_wbinv_range(pm, pv->pv_va,
1455 if (PV_BEEN_REFD(oflags))
1456 pmap_dcache_wb_range(pm, pv->pv_va,
1458 (maskbits & PVF_REF) ? TRUE : FALSE,
1462 /* make the pte read only */
1463 npte &= ~L2_S_PROT_W;
1466 if (maskbits & PVF_REF) {
1467 if ((pv->pv_flags & PVF_NC) == 0 &&
1468 (maskbits & (PVF_WRITE|PVF_MOD)) == 0) {
1470 * Check npte here; we may have already
1471 * done the wbinv above, and the validity
1472 * of the PTE is the same for opte and
1475 if (npte & L2_S_PROT_W) {
1476 if (PV_BEEN_EXECD(oflags))
1477 pmap_idcache_wbinv_range(pm,
1478 pv->pv_va, PAGE_SIZE);
1480 if (PV_BEEN_REFD(oflags))
1481 pmap_dcache_wb_range(pm,
1482 pv->pv_va, PAGE_SIZE,
1485 if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) {
1486 /* XXXJRT need idcache_inv_range */
1487 if (PV_BEEN_EXECD(oflags))
1488 pmap_idcache_wbinv_range(pm,
1489 pv->pv_va, PAGE_SIZE);
1491 if (PV_BEEN_REFD(oflags))
1492 pmap_dcache_wb_range(pm,
1493 pv->pv_va, PAGE_SIZE,
1499 * Make the PTE invalid so that we will take a
1500 * page fault the next time the mapping is
1503 npte &= ~L2_TYPE_MASK;
1504 npte |= L2_TYPE_INV;
1511 /* Flush the TLB entry if a current pmap. */
1512 if (PV_BEEN_EXECD(oflags))
1513 pmap_tlb_flushID_SE(pm, pv->pv_va);
1515 if (PV_BEEN_REFD(oflags))
1516 pmap_tlb_flushD_SE(pm, pv->pv_va);
1523 if (maskbits & PVF_WRITE)
1524 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1525 rw_wunlock(&pvh_global_lock);
1530 * main pv_entry manipulation functions:
1531 * pmap_enter_pv: enter a mapping onto a vm_page list
1532 * pmap_remove_pv: remove a mappiing from a vm_page list
1534 * NOTE: pmap_enter_pv expects to lock the pvh itself
1535 * pmap_remove_pv expects the caller to lock the pvh before calling
1539 * pmap_enter_pv: enter a mapping onto a vm_page's PV list
1541 * => caller should hold the proper lock on pvh_global_lock
1542 * => caller should have pmap locked
1543 * => we will (someday) gain the lock on the vm_page's PV list
1544 * => caller should adjust ptp's wire_count before calling
1545 * => caller should not adjust pmap's wire_count
1548 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm,
1549 vm_offset_t va, u_int flags)
1552 rw_assert(&pvh_global_lock, RA_WLOCKED);
1553 PMAP_ASSERT_LOCKED(pm);
1554 if (pg->md.pv_kva != 0) {
1555 pve->pv_pmap = kernel_pmap;
1556 pve->pv_va = pg->md.pv_kva;
1557 pve->pv_flags = PVF_WRITE | PVF_UNMAN;
1558 if (pm != kernel_pmap)
1559 PMAP_LOCK(kernel_pmap);
1560 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list);
1561 TAILQ_INSERT_HEAD(&kernel_pmap->pm_pvlist, pve, pv_plist);
1562 if (pm != kernel_pmap)
1563 PMAP_UNLOCK(kernel_pmap);
1565 if ((pve = pmap_get_pv_entry()) == NULL)
1566 panic("pmap_kenter_pv: no pv entries");
1570 pve->pv_flags = flags;
1571 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list);
1572 TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist);
1573 pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD);
1574 if (pve->pv_flags & PVF_WIRED)
1575 ++pm->pm_stats.wired_count;
1576 vm_page_aflag_set(pg, PGA_REFERENCED);
1581 * pmap_find_pv: Find a pv entry
1583 * => caller should hold lock on vm_page
1585 static PMAP_INLINE struct pv_entry *
1586 pmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1588 struct pv_entry *pv;
1590 rw_assert(&pvh_global_lock, RA_WLOCKED);
1591 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list)
1592 if (pm == pv->pv_pmap && va == pv->pv_va)
1598 * vector_page_setprot:
1600 * Manipulate the protection of the vector page.
1603 vector_page_setprot(int prot)
1605 struct l2_bucket *l2b;
1608 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page);
1610 ptep = &l2b->l2b_kva[l2pte_index(vector_page)];
1612 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot);
1614 cpu_tlb_flushD_SE(vector_page);
1619 * pmap_remove_pv: try to remove a mapping from a pv_list
1621 * => caller should hold proper lock on pmap_main_lock
1622 * => pmap should be locked
1623 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1624 * => caller should adjust ptp's wire_count and free PTP if needed
1625 * => caller should NOT adjust pmap's wire_count
1626 * => we return the removed pve
1630 pmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve)
1633 struct pv_entry *pv;
1634 rw_assert(&pvh_global_lock, RA_WLOCKED);
1635 PMAP_ASSERT_LOCKED(pm);
1636 TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list);
1637 TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist);
1638 if (pve->pv_flags & PVF_WIRED)
1639 --pm->pm_stats.wired_count;
1640 if (pg->md.pvh_attrs & PVF_MOD)
1642 if (TAILQ_FIRST(&pg->md.pv_list) == NULL)
1643 pg->md.pvh_attrs &= ~PVF_REF;
1645 vm_page_aflag_set(pg, PGA_REFERENCED);
1646 if ((pve->pv_flags & PVF_NC) && ((pm == pmap_kernel()) ||
1647 (pve->pv_flags & PVF_WRITE) || !(pve->pv_flags & PVF_MWC)))
1648 pmap_fix_cache(pg, pm, 0);
1649 else if (pve->pv_flags & PVF_WRITE) {
1650 TAILQ_FOREACH(pve, &pg->md.pv_list, pv_list)
1651 if (pve->pv_flags & PVF_WRITE)
1654 pg->md.pvh_attrs &= ~PVF_MOD;
1655 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1658 pv = TAILQ_FIRST(&pg->md.pv_list);
1659 if (pv != NULL && (pv->pv_flags & PVF_UNMAN) &&
1660 TAILQ_NEXT(pv, pv_list) == NULL) {
1662 pg->md.pv_kva = pv->pv_va;
1663 /* a recursive pmap_nuke_pv */
1664 TAILQ_REMOVE(&pg->md.pv_list, pv, pv_list);
1665 TAILQ_REMOVE(&pm->pm_pvlist, pv, pv_plist);
1666 if (pv->pv_flags & PVF_WIRED)
1667 --pm->pm_stats.wired_count;
1668 pg->md.pvh_attrs &= ~PVF_REF;
1669 pg->md.pvh_attrs &= ~PVF_MOD;
1670 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1671 pmap_free_pv_entry(pv);
1675 static struct pv_entry *
1676 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1678 struct pv_entry *pve;
1680 rw_assert(&pvh_global_lock, RA_WLOCKED);
1681 pve = TAILQ_FIRST(&pg->md.pv_list);
1684 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */
1685 pmap_nuke_pv(pg, pm, pve);
1688 pve = TAILQ_NEXT(pve, pv_list);
1691 if (pve == NULL && pg->md.pv_kva == va)
1694 return(pve); /* return removed pve */
1698 * pmap_modify_pv: Update pv flags
1700 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1701 * => caller should NOT adjust pmap's wire_count
1702 * => we return the old flags
1704 * Modify a physical-virtual mapping in the pv table
1707 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va,
1708 u_int clr_mask, u_int set_mask)
1710 struct pv_entry *npv;
1711 u_int flags, oflags;
1713 PMAP_ASSERT_LOCKED(pm);
1714 rw_assert(&pvh_global_lock, RA_WLOCKED);
1715 if ((npv = pmap_find_pv(pg, pm, va)) == NULL)
1719 * There is at least one VA mapping this page.
1722 if (clr_mask & (PVF_REF | PVF_MOD))
1723 pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD);
1725 oflags = npv->pv_flags;
1726 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask;
1728 if ((flags ^ oflags) & PVF_WIRED) {
1729 if (flags & PVF_WIRED)
1730 ++pm->pm_stats.wired_count;
1732 --pm->pm_stats.wired_count;
1735 if ((flags ^ oflags) & PVF_WRITE)
1736 pmap_fix_cache(pg, pm, 0);
1741 /* Function to set the debug level of the pmap code */
1744 pmap_debug(int level)
1746 pmap_debug_level = level;
1747 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
1749 #endif /* PMAP_DEBUG */
1752 pmap_pinit0(struct pmap *pmap)
1754 PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap));
1756 bcopy(kernel_pmap, pmap, sizeof(*pmap));
1757 bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx));
1758 PMAP_LOCK_INIT(pmap);
1762 * Initialize a vm_page's machine-dependent fields.
1765 pmap_page_init(vm_page_t m)
1768 TAILQ_INIT(&m->md.pv_list);
1769 m->md.pv_memattr = VM_MEMATTR_DEFAULT;
1773 * Initialize the pmap module.
1774 * Called by vm_init, to initialize any structures that the pmap
1775 * system needs to map virtual memory.
1780 int shpgperproc = PMAP_SHPGPERPROC;
1782 l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor,
1783 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1784 l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable), NULL,
1785 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1788 * Initialize the PV entry allocator.
1790 pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL,
1791 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1792 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1793 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1794 uma_zone_reserve_kva(pvzone, pv_entry_max);
1795 pv_entry_high_water = 9 * (pv_entry_max / 10);
1798 * Now it is safe to enable pv_table recording.
1800 PDEBUG(1, printf("pmap_init: done!\n"));
1804 pmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user)
1806 struct l2_dtable *l2;
1807 struct l2_bucket *l2b;
1808 pd_entry_t *pl1pd, l1pd;
1809 pt_entry_t *ptep, pte;
1815 rw_wlock(&pvh_global_lock);
1819 * If there is no l2_dtable for this address, then the process
1820 * has no business accessing it.
1822 * Note: This will catch userland processes trying to access
1825 l2 = pm->pm_l2[L2_IDX(l1idx)];
1830 * Likewise if there is no L2 descriptor table
1832 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
1833 if (l2b->l2b_kva == NULL)
1837 * Check the PTE itself.
1839 ptep = &l2b->l2b_kva[l2pte_index(va)];
1845 * Catch a userland access to the vector page mapped at 0x0
1847 if (user && (pte & L2_S_PROT_U) == 0)
1849 if (va == vector_page)
1854 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) {
1856 * This looks like a good candidate for "page modified"
1859 struct pv_entry *pv;
1862 /* Extract the physical address of the page */
1863 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) {
1866 /* Get the current flags for this page. */
1868 pv = pmap_find_pv(pg, pm, va);
1874 * Do the flags say this page is writable? If not then it
1875 * is a genuine write fault. If yes then the write fault is
1876 * our fault as we did not reflect the write access in the
1877 * PTE. Now we know a write has occurred we can correct this
1878 * and also set the modified bit
1880 if ((pv->pv_flags & PVF_WRITE) == 0) {
1884 pg->md.pvh_attrs |= PVF_REF | PVF_MOD;
1886 pv->pv_flags |= PVF_REF | PVF_MOD;
1889 * Re-enable write permissions for the page. No need to call
1890 * pmap_fix_cache(), since this is just a
1891 * modified-emulation fault, and the PVF_WRITE bit isn't
1892 * changing. We've already set the cacheable bits based on
1893 * the assumption that we can write to this page.
1895 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W;
1899 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) {
1901 * This looks like a good candidate for "page referenced"
1904 struct pv_entry *pv;
1907 /* Extract the physical address of the page */
1908 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL)
1910 /* Get the current flags for this page. */
1912 pv = pmap_find_pv(pg, pm, va);
1916 pg->md.pvh_attrs |= PVF_REF;
1917 pv->pv_flags |= PVF_REF;
1920 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO;
1926 * We know there is a valid mapping here, so simply
1927 * fix up the L1 if necessary.
1929 pl1pd = &pm->pm_l1->l1_kva[l1idx];
1930 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO;
1931 if (*pl1pd != l1pd) {
1939 * If 'rv == 0' at this point, it generally indicates that there is a
1940 * stale TLB entry for the faulting address. This happens when two or
1941 * more processes are sharing an L1. Since we don't flush the TLB on
1942 * a context switch between such processes, we can take domain faults
1943 * for mappings which exist at the same VA in both processes. EVEN IF
1944 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for
1947 * This is extremely likely to happen if pmap_enter() updated the L1
1948 * entry for a recently entered mapping. In this case, the TLB is
1949 * flushed for the new mapping, but there may still be TLB entries for
1950 * other mappings belonging to other processes in the 1MB range
1951 * covered by the L1 entry.
1953 * Since 'rv == 0', we know that the L1 already contains the correct
1954 * value, so the fault must be due to a stale TLB entry.
1956 * Since we always need to flush the TLB anyway in the case where we
1957 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with
1958 * stale TLB entries dynamically.
1960 * However, the above condition can ONLY happen if the current L1 is
1961 * being shared. If it happens when the L1 is unshared, it indicates
1962 * that other parts of the pmap are not doing their job WRT managing
1965 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) {
1966 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n",
1967 pm, (u_long)va, ftype);
1968 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n",
1969 l2, l2b, ptep, pl1pd);
1970 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n",
1971 pte, l1pd, last_fault_code);
1978 cpu_tlb_flushID_SE(va);
1984 rw_wunlock(&pvh_global_lock);
1992 struct l2_bucket *l2b;
1993 struct l1_ttable *l1;
1995 pt_entry_t *ptep, pte;
1996 vm_offset_t va, eva;
1999 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0);
2001 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK);
2003 for (loop = 0; loop < needed; loop++, l1++) {
2004 /* Allocate a L1 page table */
2005 va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0,
2006 0xffffffff, L1_TABLE_SIZE, 0);
2009 panic("Cannot allocate L1 KVM");
2011 eva = va + L1_TABLE_SIZE;
2012 pl1pt = (pd_entry_t *)va;
2015 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2016 ptep = &l2b->l2b_kva[l2pte_index(va)];
2018 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
2021 cpu_tlb_flushD_SE(va);
2025 pmap_init_l1(l1, pl1pt);
2030 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n",
2036 * This is used to stuff certain critical values into the PCB where they
2037 * can be accessed quickly from cpu_switch() et al.
2040 pmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb)
2042 struct l2_bucket *l2b;
2044 pcb->pcb_pagedir = pm->pm_l1->l1_physaddr;
2045 pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) |
2046 (DOMAIN_CLIENT << (pm->pm_domain * 2));
2048 if (vector_page < KERNBASE) {
2049 pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)];
2050 l2b = pmap_get_l2_bucket(pm, vector_page);
2051 pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO |
2052 L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL);
2054 pcb->pcb_pl1vec = NULL;
2058 pmap_activate(struct thread *td)
2063 pm = vmspace_pmap(td->td_proc->p_vmspace);
2067 pmap_set_pcb_pagedir(pm, pcb);
2069 if (td == curthread) {
2070 u_int cur_dacr, cur_ttb;
2072 __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb));
2073 __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr));
2075 cur_ttb &= ~(L1_TABLE_SIZE - 1);
2077 if (cur_ttb == (u_int)pcb->pcb_pagedir &&
2078 cur_dacr == pcb->pcb_dacr) {
2080 * No need to switch address spaces.
2088 * We MUST, I repeat, MUST fix up the L1 entry corresponding
2089 * to 'vector_page' in the incoming L1 table before switching
2090 * to it otherwise subsequent interrupts/exceptions (including
2091 * domain faults!) will jump into hyperspace.
2093 if (pcb->pcb_pl1vec) {
2095 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2097 * Don't need to PTE_SYNC() at this point since
2098 * cpu_setttb() is about to flush both the cache
2103 cpu_domains(pcb->pcb_dacr);
2104 cpu_setttb(pcb->pcb_pagedir);
2110 pmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va)
2112 pd_entry_t *pdep, pde;
2113 pt_entry_t *ptep, pte;
2118 * Make sure the descriptor itself has the correct cache mode
2120 pdep = &kl1[L1_IDX(va)];
2123 if (l1pte_section_p(pde)) {
2124 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) {
2125 *pdep = (pde & ~L1_S_CACHE_MASK) |
2126 pte_l1_s_cache_mode_pt;
2128 cpu_dcache_wbinv_range((vm_offset_t)pdep,
2130 cpu_l2cache_wbinv_range((vm_offset_t)pdep,
2135 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2136 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2138 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep);
2140 ptep = &ptep[l2pte_index(va)];
2142 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
2143 *ptep = (pte & ~L2_S_CACHE_MASK) |
2144 pte_l2_s_cache_mode_pt;
2146 cpu_dcache_wbinv_range((vm_offset_t)ptep,
2148 cpu_l2cache_wbinv_range((vm_offset_t)ptep,
2158 pmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap,
2161 vm_offset_t va = *availp;
2162 struct l2_bucket *l2b;
2165 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2167 panic("pmap_alloc_specials: no l2b for 0x%x", va);
2169 *ptep = &l2b->l2b_kva[l2pte_index(va)];
2173 *availp = va + (PAGE_SIZE * pages);
2177 * Bootstrap the system enough to run with virtual memory.
2179 * On the arm this is called after mapping has already been enabled
2180 * and just syncs the pmap module with what has already been done.
2181 * [We can't call it easily with mapping off since the kernel is not
2182 * mapped with PA == VA, hence we would have to relocate every address
2183 * from the linked base (virtual) address "KERNBASE" to the actual
2184 * (physical) address starting relative to 0]
2186 #define PMAP_STATIC_L2_SIZE 16
2188 pmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt)
2190 static struct l1_ttable static_l1;
2191 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE];
2192 struct l1_ttable *l1 = &static_l1;
2193 struct l2_dtable *l2;
2194 struct l2_bucket *l2b;
2196 pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va;
2201 int l1idx, l2idx, l2next = 0;
2203 PDEBUG(1, printf("firstaddr = %08x, lastaddr = %08x\n",
2204 firstaddr, vm_max_kernel_address));
2206 virtual_avail = firstaddr;
2207 kernel_pmap->pm_l1 = l1;
2208 kernel_l1pa = l1pt->pv_pa;
2211 * Scan the L1 translation table created by initarm() and create
2212 * the required metadata for all valid mappings found in it.
2214 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) {
2215 pde = kernel_l1pt[l1idx];
2218 * We're only interested in Coarse mappings.
2219 * pmap_extract() can deal with section mappings without
2220 * recourse to checking L2 metadata.
2222 if ((pde & L1_TYPE_MASK) != L1_TYPE_C)
2226 * Lookup the KVA of this L2 descriptor table
2228 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2229 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2232 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx",
2233 (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa);
2237 * Fetch the associated L2 metadata structure.
2238 * Allocate a new one if necessary.
2240 if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) {
2241 if (l2next == PMAP_STATIC_L2_SIZE)
2242 panic("pmap_bootstrap: out of static L2s");
2243 kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 =
2244 &static_l2[l2next++];
2248 * One more L1 slot tracked...
2253 * Fill in the details of the L2 descriptor in the
2254 * appropriate bucket.
2256 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2257 l2b->l2b_kva = ptep;
2259 l2b->l2b_l1idx = l1idx;
2262 * Establish an initial occupancy count for this descriptor
2265 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
2267 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) {
2268 l2b->l2b_occupancy++;
2273 * Make sure the descriptor itself has the correct cache mode.
2274 * If not, fix it, but whine about the problem. Port-meisters
2275 * should consider this a clue to fix up their initarm()
2278 if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) {
2279 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2280 "L2 pte @ %p\n", ptep);
2286 * Ensure the primary (kernel) L1 has the correct cache mode for
2287 * a page table. Bitch if it is not correctly set.
2289 for (va = (vm_offset_t)kernel_l1pt;
2290 va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) {
2291 if (pmap_set_pt_cache_mode(kernel_l1pt, va))
2292 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2293 "primary L1 @ 0x%x\n", va);
2296 cpu_dcache_wbinv_all();
2297 cpu_l2cache_wbinv_all();
2301 PMAP_LOCK_INIT(kernel_pmap);
2302 CPU_FILL(&kernel_pmap->pm_active);
2303 kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL;
2304 TAILQ_INIT(&kernel_pmap->pm_pvlist);
2307 * Initialize the global pv list lock.
2309 rw_init_flags(&pvh_global_lock, "pmap pv global", RW_RECURSE);
2312 * Reserve some special page table entries/VA space for temporary
2315 pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte);
2316 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte);
2317 pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte);
2318 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte);
2319 size = ((vm_max_kernel_address - pmap_curmaxkvaddr) + L1_S_OFFSET) /
2321 pmap_alloc_specials(&virtual_avail,
2322 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE,
2323 &pmap_kernel_l2ptp_kva, NULL);
2325 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE;
2326 pmap_alloc_specials(&virtual_avail,
2327 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE,
2328 &pmap_kernel_l2dtable_kva, NULL);
2330 pmap_alloc_specials(&virtual_avail,
2331 1, (vm_offset_t*)&_tmppt, NULL);
2332 pmap_alloc_specials(&virtual_avail,
2333 MAXDUMPPGS, (vm_offset_t *)&crashdumpmap, NULL);
2334 SLIST_INIT(&l1_list);
2335 TAILQ_INIT(&l1_lru_list);
2336 mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF);
2337 pmap_init_l1(l1, kernel_l1pt);
2338 cpu_dcache_wbinv_all();
2339 cpu_l2cache_wbinv_all();
2341 virtual_avail = round_page(virtual_avail);
2342 virtual_end = vm_max_kernel_address;
2343 kernel_vm_end = pmap_curmaxkvaddr;
2344 mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF);
2346 pmap_set_pcb_pagedir(kernel_pmap, thread0.td_pcb);
2349 /***************************************************
2350 * Pmap allocation/deallocation routines.
2351 ***************************************************/
2354 * Release any resources held by the given physical map.
2355 * Called when a pmap initialized by pmap_pinit is being released.
2356 * Should only be called if the map contains no valid mappings.
2359 pmap_release(pmap_t pmap)
2363 pmap_idcache_wbinv_all(pmap);
2364 cpu_l2cache_wbinv_all();
2365 pmap_tlb_flushID(pmap);
2367 if (vector_page < KERNBASE) {
2368 struct pcb *curpcb = PCPU_GET(curpcb);
2369 pcb = thread0.td_pcb;
2370 if (pmap_is_current(pmap)) {
2372 * Frob the L1 entry corresponding to the vector
2373 * page so that it contains the kernel pmap's domain
2374 * number. This will ensure pmap_remove() does not
2375 * pull the current vector page out from under us.
2378 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2379 cpu_domains(pcb->pcb_dacr);
2380 cpu_setttb(pcb->pcb_pagedir);
2383 pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE);
2385 * Make sure cpu_switch(), et al, DTRT. This is safe to do
2386 * since this process has no remaining mappings of its own.
2388 curpcb->pcb_pl1vec = pcb->pcb_pl1vec;
2389 curpcb->pcb_l1vec = pcb->pcb_l1vec;
2390 curpcb->pcb_dacr = pcb->pcb_dacr;
2391 curpcb->pcb_pagedir = pcb->pcb_pagedir;
2396 dprintf("pmap_release()\n");
2402 * Helper function for pmap_grow_l2_bucket()
2405 pmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap)
2407 struct l2_bucket *l2b;
2412 pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
2415 pa = VM_PAGE_TO_PHYS(pg);
2420 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2422 ptep = &l2b->l2b_kva[l2pte_index(va)];
2423 *ptep = L2_S_PROTO | pa | cache_mode |
2424 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE);
2430 * This is the same as pmap_alloc_l2_bucket(), except that it is only
2431 * used by pmap_growkernel().
2433 static __inline struct l2_bucket *
2434 pmap_grow_l2_bucket(pmap_t pm, vm_offset_t va)
2436 struct l2_dtable *l2;
2437 struct l2_bucket *l2b;
2438 struct l1_ttable *l1;
2445 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
2447 * No mapping at this address, as there is
2448 * no entry in the L1 table.
2449 * Need to allocate a new l2_dtable.
2451 nva = pmap_kernel_l2dtable_kva;
2452 if ((nva & PAGE_MASK) == 0) {
2454 * Need to allocate a backing page
2456 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2460 l2 = (struct l2_dtable *)nva;
2461 nva += sizeof(struct l2_dtable);
2463 if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva &
2466 * The new l2_dtable straddles a page boundary.
2467 * Map in another page to cover it.
2469 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2473 pmap_kernel_l2dtable_kva = nva;
2476 * Link it into the parent pmap
2478 pm->pm_l2[L2_IDX(l1idx)] = l2;
2479 memset(l2, 0, sizeof(*l2));
2482 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2485 * Fetch pointer to the L2 page table associated with the address.
2487 if (l2b->l2b_kva == NULL) {
2491 * No L2 page table has been allocated. Chances are, this
2492 * is because we just allocated the l2_dtable, above.
2494 nva = pmap_kernel_l2ptp_kva;
2495 ptep = (pt_entry_t *)nva;
2496 if ((nva & PAGE_MASK) == 0) {
2498 * Need to allocate a backing page
2500 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt,
2501 &pmap_kernel_l2ptp_phys))
2503 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t));
2505 memset(ptep, 0, L2_TABLE_SIZE_REAL);
2507 l2b->l2b_kva = ptep;
2508 l2b->l2b_l1idx = l1idx;
2509 l2b->l2b_phys = pmap_kernel_l2ptp_phys;
2511 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL;
2512 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL;
2515 /* Distribute new L1 entry to all other L1s */
2516 SLIST_FOREACH(l1, &l1_list, l1_link) {
2517 pl1pd = &l1->l1_kva[L1_IDX(va)];
2518 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) |
2528 * grow the number of kernel page table entries, if needed
2531 pmap_growkernel(vm_offset_t addr)
2533 pmap_t kpm = pmap_kernel();
2535 if (addr <= pmap_curmaxkvaddr)
2536 return; /* we are OK */
2539 * whoops! we need to add kernel PTPs
2542 /* Map 1MB at a time */
2543 for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE)
2544 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr);
2547 * flush out the cache, expensive but growkernel will happen so
2550 cpu_dcache_wbinv_all();
2551 cpu_l2cache_wbinv_all();
2554 kernel_vm_end = pmap_curmaxkvaddr;
2559 * Remove all pages from specified address space
2560 * this aids process exit speeds. Also, this code
2561 * is special cased for current process only, but
2562 * can have the more generic (and slightly slower)
2563 * mode enabled. This is much faster than pmap_remove
2564 * in the case of running down an entire address space.
2567 pmap_remove_pages(pmap_t pmap)
2569 struct pv_entry *pv, *npv;
2570 struct l2_bucket *l2b = NULL;
2574 rw_wlock(&pvh_global_lock);
2576 cpu_idcache_wbinv_all();
2577 cpu_l2cache_wbinv_all();
2578 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) {
2579 if (pv->pv_flags & PVF_WIRED || pv->pv_flags & PVF_UNMAN) {
2580 /* Cannot remove wired or unmanaged pages now. */
2581 npv = TAILQ_NEXT(pv, pv_plist);
2584 pmap->pm_stats.resident_count--;
2585 l2b = pmap_get_l2_bucket(pmap, pv->pv_va);
2586 KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages"));
2587 pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
2588 m = PHYS_TO_VM_PAGE(*pt & L2_ADDR_MASK);
2589 KASSERT((vm_offset_t)m >= KERNBASE, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt));
2592 npv = TAILQ_NEXT(pv, pv_plist);
2593 pmap_nuke_pv(m, pmap, pv);
2594 if (TAILQ_EMPTY(&m->md.pv_list))
2595 vm_page_aflag_clear(m, PGA_WRITEABLE);
2596 pmap_free_pv_entry(pv);
2597 pmap_free_l2_bucket(pmap, l2b, 1);
2599 rw_wunlock(&pvh_global_lock);
2606 /***************************************************
2607 * Low level mapping routines.....
2608 ***************************************************/
2610 #ifdef ARM_HAVE_SUPERSECTIONS
2611 /* Map a super section into the KVA. */
2614 pmap_kenter_supersection(vm_offset_t va, uint64_t pa, int flags)
2616 pd_entry_t pd = L1_S_PROTO | L1_S_SUPERSEC | (pa & L1_SUP_FRAME) |
2617 (((pa >> 32) & 0xf) << 20) | L1_S_PROT(PTE_KERNEL,
2618 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
2619 struct l1_ttable *l1;
2620 vm_offset_t va0, va_end;
2622 KASSERT(((va | pa) & L1_SUP_OFFSET) == 0,
2623 ("Not a valid super section mapping"));
2624 if (flags & SECTION_CACHE)
2625 pd |= pte_l1_s_cache_mode;
2626 else if (flags & SECTION_PT)
2627 pd |= pte_l1_s_cache_mode_pt;
2628 va0 = va & L1_SUP_FRAME;
2629 va_end = va + L1_SUP_SIZE;
2630 SLIST_FOREACH(l1, &l1_list, l1_link) {
2632 for (; va < va_end; va += L1_S_SIZE) {
2633 l1->l1_kva[L1_IDX(va)] = pd;
2634 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2640 /* Map a section into the KVA. */
2643 pmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags)
2645 pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL,
2646 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
2647 struct l1_ttable *l1;
2649 KASSERT(((va | pa) & L1_S_OFFSET) == 0,
2650 ("Not a valid section mapping"));
2651 if (flags & SECTION_CACHE)
2652 pd |= pte_l1_s_cache_mode;
2653 else if (flags & SECTION_PT)
2654 pd |= pte_l1_s_cache_mode_pt;
2655 SLIST_FOREACH(l1, &l1_list, l1_link) {
2656 l1->l1_kva[L1_IDX(va)] = pd;
2657 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2662 * Make a temporary mapping for a physical address. This is only intended
2663 * to be used for panic dumps.
2666 pmap_kenter_temporary(vm_paddr_t pa, int i)
2670 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
2671 pmap_kenter(va, pa);
2672 return ((void *)crashdumpmap);
2676 * add a wired page to the kva
2677 * note that in order for the mapping to take effect -- you
2678 * should do a invltlb after doing the pmap_kenter...
2680 static PMAP_INLINE void
2681 pmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags)
2683 struct l2_bucket *l2b;
2686 struct pv_entry *pve;
2689 PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n",
2690 (uint32_t) va, (uint32_t) pa));
2693 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2695 l2b = pmap_grow_l2_bucket(pmap_kernel(), va);
2696 KASSERT(l2b != NULL, ("No L2 Bucket"));
2697 pte = &l2b->l2b_kva[l2pte_index(va)];
2699 PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n",
2700 (uint32_t) pte, opte, *pte));
2701 if (l2pte_valid(opte)) {
2705 l2b->l2b_occupancy++;
2707 *pte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL,
2708 VM_PROT_READ | VM_PROT_WRITE);
2709 if (flags & KENTER_CACHE)
2710 *pte |= pte_l2_s_cache_mode;
2711 if (flags & KENTER_USER)
2712 *pte |= L2_S_PROT_U;
2716 * A kernel mapping may not be the page's only mapping, so create a PV
2717 * entry to ensure proper caching.
2719 * The existence test for the pvzone is used to delay the recording of
2720 * kernel mappings until the VM system is fully initialized.
2722 * This expects the physical memory to have a vm_page_array entry.
2724 if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa)) != NULL) {
2725 rw_wlock(&pvh_global_lock);
2726 if (!TAILQ_EMPTY(&m->md.pv_list) || m->md.pv_kva != 0) {
2727 if ((pve = pmap_get_pv_entry()) == NULL)
2728 panic("pmap_kenter_internal: no pv entries");
2729 PMAP_LOCK(pmap_kernel());
2730 pmap_enter_pv(m, pve, pmap_kernel(), va,
2731 PVF_WRITE | PVF_UNMAN);
2732 pmap_fix_cache(m, pmap_kernel(), va);
2733 PMAP_UNLOCK(pmap_kernel());
2737 rw_wunlock(&pvh_global_lock);
2742 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2744 pmap_kenter_internal(va, pa, KENTER_CACHE);
2748 pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa)
2751 pmap_kenter_internal(va, pa, 0);
2755 pmap_kenter_device(vm_offset_t va, vm_paddr_t pa)
2759 * XXX - Need a way for kenter_internal to handle PTE_DEVICE mapping as
2760 * a potentially different thing than PTE_NOCACHE.
2762 pmap_kenter_internal(va, pa, 0);
2766 pmap_kenter_user(vm_offset_t va, vm_paddr_t pa)
2769 pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER);
2771 * Call pmap_fault_fixup now, to make sure we'll have no exception
2772 * at the first use of the new address, or bad things will happen,
2773 * as we use one of these addresses in the exception handlers.
2775 pmap_fault_fixup(pmap_kernel(), va, VM_PROT_READ|VM_PROT_WRITE, 1);
2779 pmap_kextract(vm_offset_t va)
2782 return (pmap_extract_locked(kernel_pmap, va));
2786 * remove a page from the kernel pagetables
2789 pmap_kremove(vm_offset_t va)
2791 struct l2_bucket *l2b;
2792 pt_entry_t *pte, opte;
2793 struct pv_entry *pve;
2797 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2800 KASSERT(l2b != NULL, ("No L2 Bucket"));
2801 pte = &l2b->l2b_kva[l2pte_index(va)];
2803 if (l2pte_valid(opte)) {
2804 /* pa = vtophs(va) taken from pmap_extract() */
2805 switch (opte & L2_TYPE_MASK) {
2807 pa = (opte & L2_L_FRAME) | (va & L2_L_OFFSET);
2810 pa = (opte & L2_S_FRAME) | (va & L2_S_OFFSET);
2813 /* note: should never have to remove an allocation
2814 * before the pvzone is initialized.
2816 rw_wlock(&pvh_global_lock);
2817 PMAP_LOCK(pmap_kernel());
2818 if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa)) &&
2819 (pve = pmap_remove_pv(m, pmap_kernel(), va)))
2820 pmap_free_pv_entry(pve);
2821 PMAP_UNLOCK(pmap_kernel());
2822 rw_wunlock(&pvh_global_lock);
2823 va = va & ~PAGE_MASK;
2824 cpu_dcache_wbinv_range(va, PAGE_SIZE);
2825 cpu_l2cache_wbinv_range(va, PAGE_SIZE);
2826 cpu_tlb_flushD_SE(va);
2834 * Used to map a range of physical addresses into kernel
2835 * virtual address space.
2837 * The value passed in '*virt' is a suggested virtual address for
2838 * the mapping. Architectures which can support a direct-mapped
2839 * physical to virtual region can return the appropriate address
2840 * within that region, leaving '*virt' unchanged. Other
2841 * architectures should map the pages starting at '*virt' and
2842 * update '*virt' with the first usable address after the mapped
2846 pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot)
2848 vm_offset_t sva = *virt;
2849 vm_offset_t va = sva;
2851 PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, "
2852 "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end,
2855 while (start < end) {
2856 pmap_kenter(va, start);
2865 pmap_wb_page(vm_page_t m)
2867 struct pv_entry *pv;
2869 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
2870 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, FALSE,
2871 (pv->pv_flags & PVF_WRITE) == 0);
2875 pmap_inv_page(vm_page_t m)
2877 struct pv_entry *pv;
2879 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
2880 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, TRUE, TRUE);
2883 * Add a list of wired pages to the kva
2884 * this routine is only used for temporary
2885 * kernel mappings that do not need to have
2886 * page modification or references recorded.
2887 * Note that old mappings are simply written
2888 * over. The page *must* be wired.
2891 pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
2895 for (i = 0; i < count; i++) {
2897 pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]),
2905 * this routine jerks page mappings from the
2906 * kernel -- it is meant only for temporary mappings.
2909 pmap_qremove(vm_offset_t va, int count)
2914 for (i = 0; i < count; i++) {
2917 pmap_inv_page(PHYS_TO_VM_PAGE(pa));
2926 * pmap_object_init_pt preloads the ptes for a given object
2927 * into the specified pmap. This eliminates the blast of soft
2928 * faults on process startup and immediately after an mmap.
2931 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
2932 vm_pindex_t pindex, vm_size_t size)
2935 VM_OBJECT_ASSERT_WLOCKED(object);
2936 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2937 ("pmap_object_init_pt: non-device object"));
2942 * pmap_is_prefaultable:
2944 * Return whether or not the specified virtual address is elgible
2948 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
2953 if (!pmap_get_pde_pte(pmap, addr, &pde, &pte))
2955 KASSERT(pte != NULL, ("Valid mapping but no pte ?"));
2962 * Fetch pointers to the PDE/PTE for the given pmap/VA pair.
2963 * Returns TRUE if the mapping exists, else FALSE.
2965 * NOTE: This function is only used by a couple of arm-specific modules.
2966 * It is not safe to take any pmap locks here, since we could be right
2967 * in the middle of debugging the pmap anyway...
2969 * It is possible for this routine to return FALSE even though a valid
2970 * mapping does exist. This is because we don't lock, so the metadata
2971 * state may be inconsistent.
2973 * NOTE: We can return a NULL *ptp in the case where the L1 pde is
2974 * a "section" mapping.
2977 pmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp)
2979 struct l2_dtable *l2;
2980 pd_entry_t *pl1pd, l1pd;
2984 if (pm->pm_l1 == NULL)
2988 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx];
2991 if (l1pte_section_p(l1pd)) {
2996 if (pm->pm_l2 == NULL)
2999 l2 = pm->pm_l2[L2_IDX(l1idx)];
3002 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3006 *ptp = &ptep[l2pte_index(va)];
3011 * Routine: pmap_remove_all
3013 * Removes this physical page from
3014 * all physical maps in which it resides.
3015 * Reflects back modify bits to the pager.
3018 * Original versions of this routine were very
3019 * inefficient because they iteratively called
3020 * pmap_remove (slow...)
3023 pmap_remove_all(vm_page_t m)
3027 struct l2_bucket *l2b;
3028 boolean_t flush = FALSE;
3032 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3033 ("pmap_remove_all: page %p is not managed", m));
3034 if (TAILQ_EMPTY(&m->md.pv_list))
3036 rw_wlock(&pvh_global_lock);
3039 * XXX This call shouldn't exist. Iterating over the PV list twice,
3040 * once in pmap_clearbit() and again below, is both unnecessary and
3041 * inefficient. The below code should itself write back the cache
3042 * entry before it destroys the mapping.
3044 pmap_clearbit(m, PVF_WRITE);
3045 curpm = vmspace_pmap(curproc->p_vmspace);
3046 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3047 if (flush == FALSE && (pv->pv_pmap == curpm ||
3048 pv->pv_pmap == pmap_kernel()))
3051 PMAP_LOCK(pv->pv_pmap);
3053 * Cached contents were written-back in pmap_clearbit(),
3054 * but we still have to invalidate the cache entry to make
3055 * sure stale data are not retrieved when another page will be
3056 * mapped under this virtual address.
3058 if (pmap_is_current(pv->pv_pmap)) {
3059 cpu_dcache_inv_range(pv->pv_va, PAGE_SIZE);
3060 if (pmap_has_valid_mapping(pv->pv_pmap, pv->pv_va))
3061 cpu_l2cache_inv_range(pv->pv_va, PAGE_SIZE);
3064 if (pv->pv_flags & PVF_UNMAN) {
3065 /* remove the pv entry, but do not remove the mapping
3066 * and remember this is a kernel mapped page
3068 m->md.pv_kva = pv->pv_va;
3070 /* remove the mapping and pv entry */
3071 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
3072 KASSERT(l2b != NULL, ("No l2 bucket"));
3073 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
3075 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
3076 pmap_free_l2_bucket(pv->pv_pmap, l2b, 1);
3077 pv->pv_pmap->pm_stats.resident_count--;
3078 flags |= pv->pv_flags;
3080 pmap_nuke_pv(m, pv->pv_pmap, pv);
3081 PMAP_UNLOCK(pv->pv_pmap);
3082 pmap_free_pv_entry(pv);
3086 if (PV_BEEN_EXECD(flags))
3087 pmap_tlb_flushID(curpm);
3089 pmap_tlb_flushD(curpm);
3091 vm_page_aflag_clear(m, PGA_WRITEABLE);
3092 rw_wunlock(&pvh_global_lock);
3097 * Set the physical protection on the
3098 * specified range of this map as requested.
3101 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3103 struct l2_bucket *l2b;
3104 pt_entry_t *ptep, pte;
3105 vm_offset_t next_bucket;
3109 CTR4(KTR_PMAP, "pmap_protect: pmap %p sva 0x%08x eva 0x%08x prot %x",
3110 pm, sva, eva, prot);
3112 if ((prot & VM_PROT_READ) == 0) {
3113 pmap_remove(pm, sva, eva);
3117 if (prot & VM_PROT_WRITE) {
3119 * If this is a read->write transition, just ignore it and let
3120 * vm_fault() take care of it later.
3125 rw_wlock(&pvh_global_lock);
3129 * OK, at this point, we know we're doing write-protect operation.
3130 * If the pmap is active, write-back the range.
3132 pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE);
3134 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1;
3138 next_bucket = L2_NEXT_BUCKET(sva);
3139 if (next_bucket > eva)
3142 l2b = pmap_get_l2_bucket(pm, sva);
3148 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3150 while (sva < next_bucket) {
3151 if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) {
3155 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
3156 pte &= ~L2_S_PROT_W;
3160 if (!(pg->oflags & VPO_UNMANAGED)) {
3161 f = pmap_modify_pv(pg, pm, sva,
3172 if (PV_BEEN_EXECD(f))
3173 pmap_tlb_flushID_SE(pm, sva);
3175 if (PV_BEEN_REFD(f))
3176 pmap_tlb_flushD_SE(pm, sva);
3186 if (PV_BEEN_EXECD(flags))
3187 pmap_tlb_flushID(pm);
3189 if (PV_BEEN_REFD(flags))
3190 pmap_tlb_flushD(pm);
3192 rw_wunlock(&pvh_global_lock);
3199 * Insert the given physical page (p) at
3200 * the specified virtual address (v) in the
3201 * target physical map with the protection requested.
3203 * If specified, the page will be wired down, meaning
3204 * that the related pte can not be reclaimed.
3206 * NB: This is the only routine which MAY NOT lazy-evaluate
3207 * or lose information. That is, this routine must actually
3208 * insert this page into the given map NOW.
3212 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3213 u_int flags, int8_t psind __unused)
3217 rw_wlock(&pvh_global_lock);
3219 rv = pmap_enter_locked(pmap, va, m, prot, flags);
3220 rw_wunlock(&pvh_global_lock);
3226 * The pvh global and pmap locks must be held.
3229 pmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3232 struct l2_bucket *l2b = NULL;
3233 struct vm_page *opg;
3234 struct pv_entry *pve = NULL;
3235 pt_entry_t *ptep, npte, opte;
3240 PMAP_ASSERT_LOCKED(pmap);
3241 rw_assert(&pvh_global_lock, RA_WLOCKED);
3242 if (va == vector_page) {
3243 pa = systempage.pv_pa;
3246 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3247 VM_OBJECT_ASSERT_LOCKED(m->object);
3248 pa = VM_PAGE_TO_PHYS(m);
3251 if (prot & VM_PROT_WRITE)
3252 nflags |= PVF_WRITE;
3253 if (prot & VM_PROT_EXECUTE)
3255 if ((flags & PMAP_ENTER_WIRED) != 0)
3256 nflags |= PVF_WIRED;
3257 PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, "
3258 "flags = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, flags));
3260 if (pmap == pmap_kernel()) {
3261 l2b = pmap_get_l2_bucket(pmap, va);
3263 l2b = pmap_grow_l2_bucket(pmap, va);
3266 l2b = pmap_alloc_l2_bucket(pmap, va);
3268 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
3270 rw_wunlock(&pvh_global_lock);
3272 rw_wlock(&pvh_global_lock);
3276 return (KERN_RESOURCE_SHORTAGE);
3280 ptep = &l2b->l2b_kva[l2pte_index(va)];
3287 * There is already a mapping at this address.
3288 * If the physical address is different, lookup the
3291 if (l2pte_pa(opte) != pa)
3292 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte));
3298 if ((prot & (VM_PROT_ALL)) ||
3299 (!m || m->md.pvh_attrs & PVF_REF)) {
3301 * - The access type indicates that we don't need
3302 * to do referenced emulation.
3304 * - The physical page has already been referenced
3305 * so no need to re-do referenced emulation here.
3311 if (m && ((prot & VM_PROT_WRITE) != 0 ||
3312 (m->md.pvh_attrs & PVF_MOD))) {
3314 * This is a writable mapping, and the
3315 * page's mod state indicates it has
3316 * already been modified. Make it
3317 * writable from the outset.
3320 if (!(m->md.pvh_attrs & PVF_MOD))
3324 vm_page_aflag_set(m, PGA_REFERENCED);
3327 * Need to do page referenced emulation.
3329 npte |= L2_TYPE_INV;
3332 if (prot & VM_PROT_WRITE) {
3333 npte |= L2_S_PROT_W;
3335 (m->oflags & VPO_UNMANAGED) == 0)
3336 vm_page_aflag_set(m, PGA_WRITEABLE);
3338 if (m->md.pv_memattr != VM_MEMATTR_UNCACHEABLE)
3339 npte |= pte_l2_s_cache_mode;
3340 if (m && m == opg) {
3342 * We're changing the attrs of an existing mapping.
3344 oflags = pmap_modify_pv(m, pmap, va,
3345 PVF_WRITE | PVF_EXEC | PVF_WIRED |
3346 PVF_MOD | PVF_REF, nflags);
3349 * We may need to flush the cache if we're
3352 if (pmap_is_current(pmap) &&
3353 (oflags & PVF_NC) == 0 &&
3354 (opte & L2_S_PROT_W) != 0 &&
3355 (prot & VM_PROT_WRITE) == 0 &&
3356 (opte & L2_TYPE_MASK) != L2_TYPE_INV) {
3357 cpu_dcache_wb_range(va, PAGE_SIZE);
3358 cpu_l2cache_wb_range(va, PAGE_SIZE);
3362 * New mapping, or changing the backing page
3363 * of an existing mapping.
3367 * Replacing an existing mapping with a new one.
3368 * It is part of our managed memory so we
3369 * must remove it from the PV list
3371 if ((pve = pmap_remove_pv(opg, pmap, va))) {
3373 /* note for patch: the oflags/invalidation was moved
3374 * because PG_FICTITIOUS pages could free the pve
3376 oflags = pve->pv_flags;
3378 * If the old mapping was valid (ref/mod
3379 * emulation creates 'invalid' mappings
3380 * initially) then make sure to frob
3383 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) {
3384 if (PV_BEEN_EXECD(oflags)) {
3385 pmap_idcache_wbinv_range(pmap, va,
3388 if (PV_BEEN_REFD(oflags)) {
3389 pmap_dcache_wb_range(pmap, va,
3391 (oflags & PVF_WRITE) == 0);
3395 /* free/allocate a pv_entry for UNMANAGED pages if
3396 * this physical page is not/is already mapped.
3399 if (m && (m->oflags & VPO_UNMANAGED) &&
3401 TAILQ_EMPTY(&m->md.pv_list)) {
3402 pmap_free_pv_entry(pve);
3406 (!(m->oflags & VPO_UNMANAGED) || m->md.pv_kva ||
3407 !TAILQ_EMPTY(&m->md.pv_list)))
3408 pve = pmap_get_pv_entry();
3410 (!(m->oflags & VPO_UNMANAGED) || m->md.pv_kva ||
3411 !TAILQ_EMPTY(&m->md.pv_list)))
3412 pve = pmap_get_pv_entry();
3415 if ((m->oflags & VPO_UNMANAGED)) {
3416 if (!TAILQ_EMPTY(&m->md.pv_list) ||
3418 KASSERT(pve != NULL, ("No pv"));
3419 nflags |= PVF_UNMAN;
3420 pmap_enter_pv(m, pve, pmap, va, nflags);
3424 KASSERT(va < kmi.clean_sva ||
3425 va >= kmi.clean_eva,
3426 ("pmap_enter: managed mapping within the clean submap"));
3427 KASSERT(pve != NULL, ("No pv"));
3428 pmap_enter_pv(m, pve, pmap, va, nflags);
3433 * Make sure userland mappings get the right permissions
3435 if (pmap != pmap_kernel() && va != vector_page) {
3436 npte |= L2_S_PROT_U;
3440 * Keep the stats up to date
3443 l2b->l2b_occupancy++;
3444 pmap->pm_stats.resident_count++;
3448 * If this is just a wiring change, the two PTEs will be
3449 * identical, so there's no need to update the page table.
3452 boolean_t is_cached = pmap_is_current(pmap);
3457 * We only need to frob the cache/tlb if this pmap
3461 if (L1_IDX(va) != L1_IDX(vector_page) &&
3462 l2pte_valid(npte)) {
3464 * This mapping is likely to be accessed as
3465 * soon as we return to userland. Fix up the
3466 * L1 entry to avoid taking another
3467 * page/domain fault.
3469 pd_entry_t *pl1pd, l1pd;
3471 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
3472 l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) |
3474 if (*pl1pd != l1pd) {
3481 if (PV_BEEN_EXECD(oflags))
3482 pmap_tlb_flushID_SE(pmap, va);
3483 else if (PV_BEEN_REFD(oflags))
3484 pmap_tlb_flushD_SE(pmap, va);
3488 pmap_fix_cache(m, pmap, va);
3490 return (KERN_SUCCESS);
3494 * Maps a sequence of resident pages belonging to the same object.
3495 * The sequence begins with the given page m_start. This page is
3496 * mapped at the given virtual address start. Each subsequent page is
3497 * mapped at a virtual address that is offset from start by the same
3498 * amount as the page is offset from m_start within the object. The
3499 * last page in the sequence is the page with the largest offset from
3500 * m_start that can be mapped at a virtual address less than the given
3501 * virtual address end. Not every virtual page between start and end
3502 * is mapped; only those for which a resident page exists with the
3503 * corresponding offset from m_start are mapped.
3506 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3507 vm_page_t m_start, vm_prot_t prot)
3510 vm_pindex_t diff, psize;
3512 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3514 psize = atop(end - start);
3516 rw_wlock(&pvh_global_lock);
3518 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3519 pmap_enter_locked(pmap, start + ptoa(diff), m, prot &
3520 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP);
3521 m = TAILQ_NEXT(m, listq);
3523 rw_wunlock(&pvh_global_lock);
3528 * this code makes some *MAJOR* assumptions:
3529 * 1. Current pmap & pmap exists.
3532 * 4. No page table pages.
3533 * but is *MUCH* faster than pmap_enter...
3537 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3540 rw_wlock(&pvh_global_lock);
3542 pmap_enter_locked(pmap, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
3543 PMAP_ENTER_NOSLEEP);
3544 rw_wunlock(&pvh_global_lock);
3549 * Clear the wired attribute from the mappings for the specified range of
3550 * addresses in the given pmap. Every valid mapping within that range
3551 * must have the wired attribute set. In contrast, invalid mappings
3552 * cannot have the wired attribute set, so they are ignored.
3554 * XXX Wired mappings of unmanaged pages cannot be counted by this pmap
3558 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3560 struct l2_bucket *l2b;
3561 pt_entry_t *ptep, pte;
3563 vm_offset_t next_bucket;
3566 rw_wlock(&pvh_global_lock);
3569 next_bucket = L2_NEXT_BUCKET(sva);
3570 if (next_bucket > eva)
3572 l2b = pmap_get_l2_bucket(pmap, sva);
3577 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; sva < next_bucket;
3578 sva += PAGE_SIZE, ptep++) {
3579 if ((pte = *ptep) == 0 ||
3580 (m = PHYS_TO_VM_PAGE(l2pte_pa(pte))) == NULL ||
3581 (m->oflags & VPO_UNMANAGED) != 0)
3583 pv = pmap_find_pv(m, pmap, sva);
3584 if ((pv->pv_flags & PVF_WIRED) == 0)
3585 panic("pmap_unwire: pv %p isn't wired", pv);
3586 pv->pv_flags &= ~PVF_WIRED;
3587 pmap->pm_stats.wired_count--;
3590 rw_wunlock(&pvh_global_lock);
3596 * Copy the range specified by src_addr/len
3597 * from the source map to the range dst_addr/len
3598 * in the destination map.
3600 * This routine is only advisory and need not do anything.
3603 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
3604 vm_size_t len, vm_offset_t src_addr)
3610 * Routine: pmap_extract
3612 * Extract the physical page address associated
3613 * with the given map/virtual_address pair.
3616 pmap_extract(pmap_t pmap, vm_offset_t va)
3621 pa = pmap_extract_locked(pmap, va);
3627 pmap_extract_locked(pmap_t pmap, vm_offset_t va)
3629 struct l2_dtable *l2;
3631 pt_entry_t *ptep, pte;
3635 if (pmap != kernel_pmap)
3636 PMAP_ASSERT_LOCKED(pmap);
3638 l1pd = pmap->pm_l1->l1_kva[l1idx];
3639 if (l1pte_section_p(l1pd)) {
3641 * These should only happen for the kernel pmap.
3643 KASSERT(pmap == kernel_pmap, ("unexpected section"));
3644 /* XXX: what to do about the bits > 32 ? */
3645 if (l1pd & L1_S_SUPERSEC)
3646 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3648 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3651 * Note that we can't rely on the validity of the L1
3652 * descriptor as an indication that a mapping exists.
3653 * We have to look it up in the L2 dtable.
3655 l2 = pmap->pm_l2[L2_IDX(l1idx)];
3657 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL)
3659 pte = ptep[l2pte_index(va)];
3662 switch (pte & L2_TYPE_MASK) {
3664 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3667 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3675 * Atomically extract and hold the physical page with the given
3676 * pmap and virtual address pair if that mapping permits the given
3681 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3683 struct l2_dtable *l2;
3685 pt_entry_t *ptep, pte;
3686 vm_paddr_t pa, paddr;
3694 l1pd = pmap->pm_l1->l1_kva[l1idx];
3695 if (l1pte_section_p(l1pd)) {
3697 * These should only happen for pmap_kernel()
3699 KASSERT(pmap == pmap_kernel(), ("huh"));
3700 /* XXX: what to do about the bits > 32 ? */
3701 if (l1pd & L1_S_SUPERSEC)
3702 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3704 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3705 if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr))
3707 if (l1pd & L1_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3708 m = PHYS_TO_VM_PAGE(pa);
3714 * Note that we can't rely on the validity of the L1
3715 * descriptor as an indication that a mapping exists.
3716 * We have to look it up in the L2 dtable.
3718 l2 = pmap->pm_l2[L2_IDX(l1idx)];
3721 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3726 ptep = &ptep[l2pte_index(va)];
3733 if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3734 switch (pte & L2_TYPE_MASK) {
3736 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3740 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3743 if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr))
3745 m = PHYS_TO_VM_PAGE(pa);
3751 PA_UNLOCK_COND(paddr);
3756 * Initialize a preallocated and zeroed pmap structure,
3757 * such as one in a vmspace structure.
3761 pmap_pinit(pmap_t pmap)
3763 PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap));
3765 pmap_alloc_l1(pmap);
3766 bzero(pmap->pm_l2, sizeof(pmap->pm_l2));
3768 CPU_ZERO(&pmap->pm_active);
3770 TAILQ_INIT(&pmap->pm_pvlist);
3771 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3772 pmap->pm_stats.resident_count = 1;
3773 if (vector_page < KERNBASE) {
3774 pmap_enter(pmap, vector_page, PHYS_TO_VM_PAGE(systempage.pv_pa),
3775 VM_PROT_READ, PMAP_ENTER_WIRED | VM_PROT_READ, 0);
3781 /***************************************************
3782 * page management routines.
3783 ***************************************************/
3787 pmap_free_pv_entry(pv_entry_t pv)
3790 uma_zfree(pvzone, pv);
3795 * get a new pv_entry, allocating a block from the system
3797 * the memory allocation is performed bypassing the malloc code
3798 * because of the possibility of allocations at interrupt time.
3801 pmap_get_pv_entry(void)
3803 pv_entry_t ret_value;
3806 if (pv_entry_count > pv_entry_high_water)
3807 pagedaemon_wakeup();
3808 ret_value = uma_zalloc(pvzone, M_NOWAIT);
3813 * Remove the given range of addresses from the specified map.
3815 * It is assumed that the start and end are properly
3816 * rounded to the page size.
3818 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3
3820 pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva)
3822 struct l2_bucket *l2b;
3823 vm_offset_t next_bucket;
3826 u_int mappings, is_exec, is_refd;
3831 * we lock in the pmap => pv_head direction
3834 rw_wlock(&pvh_global_lock);
3839 * Do one L2 bucket's worth at a time.
3841 next_bucket = L2_NEXT_BUCKET(sva);
3842 if (next_bucket > eva)
3845 l2b = pmap_get_l2_bucket(pm, sva);
3851 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3854 while (sva < next_bucket) {
3863 * Nothing here, move along
3870 pm->pm_stats.resident_count--;
3876 * Update flags. In a number of circumstances,
3877 * we could cluster a lot of these and do a
3878 * number of sequential pages in one go.
3880 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) {
3881 struct pv_entry *pve;
3883 pve = pmap_remove_pv(pg, pm, sva);
3885 is_exec = PV_BEEN_EXECD(pve->pv_flags);
3886 is_refd = PV_BEEN_REFD(pve->pv_flags);
3887 pmap_free_pv_entry(pve);
3891 if (l2pte_valid(pte) && pmap_is_current(pm)) {
3892 if (total < PMAP_REMOVE_CLEAN_LIST_SIZE) {
3895 cpu_idcache_wbinv_range(sva,
3897 cpu_l2cache_wbinv_range(sva,
3899 cpu_tlb_flushID_SE(sva);
3900 } else if (is_refd) {
3901 cpu_dcache_wbinv_range(sva,
3903 cpu_l2cache_wbinv_range(sva,
3905 cpu_tlb_flushD_SE(sva);
3907 } else if (total == PMAP_REMOVE_CLEAN_LIST_SIZE) {
3908 /* flushall will also only get set for
3909 * for a current pmap
3911 cpu_idcache_wbinv_all();
3912 cpu_l2cache_wbinv_all();
3925 pmap_free_l2_bucket(pm, l2b, mappings);
3928 rw_wunlock(&pvh_global_lock);
3937 * Zero a given physical page by mapping it at a page hook point.
3938 * In doing the zero page op, the page we zero is mapped cachable, as with
3939 * StrongARM accesses to non-cached pages are non-burst making writing
3940 * _any_ bulk data very slow.
3942 #if ARM_MMU_GENERIC != 0 || defined(CPU_XSCALE_CORE3)
3944 pmap_zero_page_generic(vm_paddr_t phys, int off, int size)
3947 if (_arm_bzero && size >= _min_bzero_size &&
3948 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0)
3953 * Hook in the page, zero it, invalidate the TLB as needed.
3955 * Note the temporary zero-page mapping must be a non-cached page in
3956 * order to work without corruption when write-allocate is enabled.
3958 *cdst_pte = L2_S_PROTO | phys | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE);
3960 cpu_tlb_flushD_SE(cdstp);
3962 if (off || size != PAGE_SIZE)
3963 bzero((void *)(cdstp + off), size);
3969 #endif /* ARM_MMU_GENERIC != 0 */
3971 #if ARM_MMU_XSCALE == 1
3973 pmap_zero_page_xscale(vm_paddr_t phys, int off, int size)
3976 if (_arm_bzero && size >= _min_bzero_size &&
3977 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0)
3982 * Hook in the page, zero it, and purge the cache for that
3983 * zeroed page. Invalidate the TLB as needed.
3985 *cdst_pte = L2_S_PROTO | phys |
3986 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
3987 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
3989 cpu_tlb_flushD_SE(cdstp);
3991 if (off || size != PAGE_SIZE)
3992 bzero((void *)(cdstp + off), size);
3996 xscale_cache_clean_minidata();
4000 * Change the PTEs for the specified kernel mappings such that they
4001 * will use the mini data cache instead of the main data cache.
4004 pmap_use_minicache(vm_offset_t va, vm_size_t size)
4006 struct l2_bucket *l2b;
4007 pt_entry_t *ptep, *sptep, pte;
4008 vm_offset_t next_bucket, eva;
4010 #if (ARM_NMMUS > 1) || defined(CPU_XSCALE_CORE3)
4011 if (xscale_use_minidata == 0)
4018 next_bucket = L2_NEXT_BUCKET(va);
4019 if (next_bucket > eva)
4022 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
4024 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)];
4026 while (va < next_bucket) {
4028 if (!l2pte_minidata(pte)) {
4029 cpu_dcache_wbinv_range(va, PAGE_SIZE);
4030 cpu_tlb_flushD_SE(va);
4031 *ptep = pte & ~L2_B;
4036 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep));
4040 #endif /* ARM_MMU_XSCALE == 1 */
4043 * pmap_zero_page zeros the specified hardware page by mapping
4044 * the page into KVM and using bzero to clear its contents.
4047 pmap_zero_page(vm_page_t m)
4049 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), 0, PAGE_SIZE);
4054 * pmap_zero_page_area zeros the specified hardware page by mapping
4055 * the page into KVM and using bzero to clear its contents.
4057 * off and size may not cover an area beyond a single hardware page.
4060 pmap_zero_page_area(vm_page_t m, int off, int size)
4063 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), off, size);
4068 * pmap_zero_page_idle zeros the specified hardware page by mapping
4069 * the page into KVM and using bzero to clear its contents. This
4070 * is intended to be called from the vm_pagezero process only and
4074 pmap_zero_page_idle(vm_page_t m)
4084 * This is a local function used to work out the best strategy to clean
4085 * a single page referenced by its entry in the PV table. It should be used by
4086 * pmap_copy_page, pmap_zero page and maybe some others later on.
4088 * Its policy is effectively:
4089 * o If there are no mappings, we don't bother doing anything with the cache.
4090 * o If there is one mapping, we clean just that page.
4091 * o If there are multiple mappings, we clean the entire cache.
4093 * So that some functions can be further optimised, it returns 0 if it didn't
4094 * clean the entire cache, or 1 if it did.
4096 * XXX One bug in this routine is that if the pv_entry has a single page
4097 * mapped at 0x00000000 a whole cache clean will be performed rather than
4098 * just the 1 page. Since this should not occur in everyday use and if it does
4099 * it will just result in not the most efficient clean for the page.
4101 * We don't yet use this function but may want to.
4104 pmap_clean_page(struct pv_entry *pv, boolean_t is_src)
4106 pmap_t pm, pm_to_clean = NULL;
4107 struct pv_entry *npv;
4108 u_int cache_needs_cleaning = 0;
4110 vm_offset_t page_to_clean = 0;
4113 /* nothing mapped in so nothing to flush */
4118 * Since we flush the cache each time we change to a different
4119 * user vmspace, we only need to flush the page if it is in the
4123 pm = vmspace_pmap(curproc->p_vmspace);
4127 for (npv = pv; npv; npv = TAILQ_NEXT(npv, pv_list)) {
4128 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) {
4129 flags |= npv->pv_flags;
4131 * The page is mapped non-cacheable in
4132 * this map. No need to flush the cache.
4134 if (npv->pv_flags & PVF_NC) {
4136 if (cache_needs_cleaning)
4137 panic("pmap_clean_page: "
4138 "cache inconsistency");
4141 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0)
4143 if (cache_needs_cleaning) {
4147 page_to_clean = npv->pv_va;
4148 pm_to_clean = npv->pv_pmap;
4150 cache_needs_cleaning = 1;
4153 if (page_to_clean) {
4154 if (PV_BEEN_EXECD(flags))
4155 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean,
4158 pmap_dcache_wb_range(pm_to_clean, page_to_clean,
4159 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0);
4160 } else if (cache_needs_cleaning) {
4161 if (PV_BEEN_EXECD(flags))
4162 pmap_idcache_wbinv_all(pm);
4164 pmap_dcache_wbinv_all(pm);
4172 * pmap_copy_page copies the specified (machine independent)
4173 * page by mapping the page into virtual memory and using
4174 * bcopy to copy the page, one machine dependent page at a
4181 * Copy one physical page into another, by mapping the pages into
4182 * hook points. The same comment regarding cachability as in
4183 * pmap_zero_page also applies here.
4185 #if ARM_MMU_GENERIC != 0 || defined (CPU_XSCALE_CORE3)
4187 pmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst)
4190 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4194 * Clean the source page. Hold the source page's lock for
4195 * the duration of the copy so that no other mappings can
4196 * be created while we have a potentially aliased mapping.
4200 * XXX: Not needed while we call cpu_dcache_wbinv_all() in
4203 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4206 * Map the pages into the page hook points, copy them, and purge
4207 * the cache for the appropriate page. Invalidate the TLB
4211 *csrc_pte = L2_S_PROTO | src |
4212 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
4214 *cdst_pte = L2_S_PROTO | dst |
4215 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
4217 cpu_tlb_flushD_SE(csrcp);
4218 cpu_tlb_flushD_SE(cdstp);
4220 bcopy_page(csrcp, cdstp);
4222 cpu_dcache_inv_range(csrcp, PAGE_SIZE);
4223 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE);
4224 cpu_l2cache_inv_range(csrcp, PAGE_SIZE);
4225 cpu_l2cache_wbinv_range(cdstp, PAGE_SIZE);
4229 pmap_copy_page_offs_generic(vm_paddr_t a_phys, vm_offset_t a_offs,
4230 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt)
4234 *csrc_pte = L2_S_PROTO | a_phys |
4235 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
4237 *cdst_pte = L2_S_PROTO | b_phys |
4238 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
4240 cpu_tlb_flushD_SE(csrcp);
4241 cpu_tlb_flushD_SE(cdstp);
4243 bcopy((char *)csrcp + a_offs, (char *)cdstp + b_offs, cnt);
4245 cpu_dcache_inv_range(csrcp + a_offs, cnt);
4246 cpu_dcache_wbinv_range(cdstp + b_offs, cnt);
4247 cpu_l2cache_inv_range(csrcp + a_offs, cnt);
4248 cpu_l2cache_wbinv_range(cdstp + b_offs, cnt);
4250 #endif /* ARM_MMU_GENERIC != 0 */
4252 #if ARM_MMU_XSCALE == 1
4254 pmap_copy_page_xscale(vm_paddr_t src, vm_paddr_t dst)
4257 /* XXX: Only needed for pmap_clean_page(), which is commented out. */
4258 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4262 * Clean the source page. Hold the source page's lock for
4263 * the duration of the copy so that no other mappings can
4264 * be created while we have a potentially aliased mapping.
4268 * XXX: Not needed while we call cpu_dcache_wbinv_all() in
4271 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4274 * Map the pages into the page hook points, copy them, and purge
4275 * the cache for the appropriate page. Invalidate the TLB
4279 *csrc_pte = L2_S_PROTO | src |
4280 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
4281 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4283 *cdst_pte = L2_S_PROTO | dst |
4284 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4285 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4287 cpu_tlb_flushD_SE(csrcp);
4288 cpu_tlb_flushD_SE(cdstp);
4290 bcopy_page(csrcp, cdstp);
4292 xscale_cache_clean_minidata();
4296 pmap_copy_page_offs_xscale(vm_paddr_t a_phys, vm_offset_t a_offs,
4297 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt)
4301 *csrc_pte = L2_S_PROTO | a_phys |
4302 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
4303 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X);
4305 *cdst_pte = L2_S_PROTO | b_phys |
4306 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4307 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X);
4309 cpu_tlb_flushD_SE(csrcp);
4310 cpu_tlb_flushD_SE(cdstp);
4312 bcopy((char *)csrcp + a_offs, (char *)cdstp + b_offs, cnt);
4314 xscale_cache_clean_minidata();
4316 #endif /* ARM_MMU_XSCALE == 1 */
4319 pmap_copy_page(vm_page_t src, vm_page_t dst)
4322 cpu_dcache_wbinv_all();
4323 cpu_l2cache_wbinv_all();
4324 if (_arm_memcpy && PAGE_SIZE >= _min_memcpy_size &&
4325 _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst),
4326 (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0)
4328 pmap_copy_page_func(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst));
4331 int unmapped_buf_allowed = 1;
4334 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4335 vm_offset_t b_offset, int xfersize)
4337 vm_page_t a_pg, b_pg;
4338 vm_offset_t a_pg_offset, b_pg_offset;
4341 cpu_dcache_wbinv_all();
4342 cpu_l2cache_wbinv_all();
4343 while (xfersize > 0) {
4344 a_pg = ma[a_offset >> PAGE_SHIFT];
4345 a_pg_offset = a_offset & PAGE_MASK;
4346 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4347 b_pg = mb[b_offset >> PAGE_SHIFT];
4348 b_pg_offset = b_offset & PAGE_MASK;
4349 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4350 pmap_copy_page_offs_func(VM_PAGE_TO_PHYS(a_pg), a_pg_offset,
4351 VM_PAGE_TO_PHYS(b_pg), b_pg_offset, cnt);
4359 * this routine returns true if a physical page resides
4360 * in the given pmap.
4363 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4369 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4370 ("pmap_page_exists_quick: page %p is not managed", m));
4372 rw_wlock(&pvh_global_lock);
4373 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4374 if (pv->pv_pmap == pmap) {
4382 rw_wunlock(&pvh_global_lock);
4387 * pmap_page_wired_mappings:
4389 * Return the number of managed mappings to the given physical page
4393 pmap_page_wired_mappings(vm_page_t m)
4399 if ((m->oflags & VPO_UNMANAGED) != 0)
4401 rw_wlock(&pvh_global_lock);
4402 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
4403 if ((pv->pv_flags & PVF_WIRED) != 0)
4405 rw_wunlock(&pvh_global_lock);
4410 * This function is advisory.
4413 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4418 * pmap_ts_referenced:
4420 * Return the count of reference bits for a page, clearing all of them.
4423 pmap_ts_referenced(vm_page_t m)
4426 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4427 ("pmap_ts_referenced: page %p is not managed", m));
4428 return (pmap_clearbit(m, PVF_REF));
4433 pmap_is_modified(vm_page_t m)
4436 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4437 ("pmap_is_modified: page %p is not managed", m));
4438 if (m->md.pvh_attrs & PVF_MOD)
4446 * Clear the modify bits on the specified physical page.
4449 pmap_clear_modify(vm_page_t m)
4452 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4453 ("pmap_clear_modify: page %p is not managed", m));
4454 VM_OBJECT_ASSERT_WLOCKED(m->object);
4455 KASSERT(!vm_page_xbusied(m),
4456 ("pmap_clear_modify: page %p is exclusive busied", m));
4459 * If the page is not PGA_WRITEABLE, then no mappings can be modified.
4460 * If the object containing the page is locked and the page is not
4461 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
4463 if ((m->aflags & PGA_WRITEABLE) == 0)
4465 if (m->md.pvh_attrs & PVF_MOD)
4466 pmap_clearbit(m, PVF_MOD);
4471 * pmap_is_referenced:
4473 * Return whether or not the specified physical page was referenced
4474 * in any physical maps.
4477 pmap_is_referenced(vm_page_t m)
4480 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4481 ("pmap_is_referenced: page %p is not managed", m));
4482 return ((m->md.pvh_attrs & PVF_REF) != 0);
4487 * Clear the write and modified bits in each of the given page's mappings.
4490 pmap_remove_write(vm_page_t m)
4493 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4494 ("pmap_remove_write: page %p is not managed", m));
4497 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4498 * set by another thread while the object is locked. Thus,
4499 * if PGA_WRITEABLE is clear, no page table entries need updating.
4501 VM_OBJECT_ASSERT_WLOCKED(m->object);
4502 if (vm_page_xbusied(m) || (m->aflags & PGA_WRITEABLE) != 0)
4503 pmap_clearbit(m, PVF_WRITE);
4508 * perform the pmap work for mincore
4511 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
4513 struct l2_bucket *l2b;
4514 pt_entry_t *ptep, pte;
4522 l2b = pmap_get_l2_bucket(pmap, addr);
4527 ptep = &l2b->l2b_kva[l2pte_index(addr)];
4529 if (!l2pte_valid(pte)) {
4533 val = MINCORE_INCORE;
4534 if (pte & L2_S_PROT_W)
4535 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4538 m = PHYS_TO_VM_PAGE(pa);
4539 if (m != NULL && !(m->oflags & VPO_UNMANAGED))
4543 * The ARM pmap tries to maintain a per-mapping
4544 * reference bit. The trouble is that it's kept in
4545 * the PV entry, not the PTE, so it's costly to access
4546 * here. You would need to acquire the pvh global
4547 * lock, call pmap_find_pv(), and introduce a custom
4548 * version of vm_page_pa_tryrelock() that releases and
4549 * reacquires the pvh global lock. In the end, I
4550 * doubt it's worthwhile. This may falsely report
4551 * the given address as referenced.
4553 if ((m->md.pvh_attrs & PVF_REF) != 0)
4554 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4556 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
4557 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
4558 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
4559 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
4563 PA_UNLOCK_COND(*locked_pa);
4570 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
4576 * Increase the starting virtual address of the given mapping if a
4577 * different alignment might result in more superpage mappings.
4580 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
4581 vm_offset_t *addr, vm_size_t size)
4585 #define BOOTSTRAP_DEBUG
4590 * Create a single section mapping.
4593 pmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4594 int prot, int cache)
4596 pd_entry_t *pde = (pd_entry_t *) l1pt;
4599 KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2"));
4608 fl = pte_l1_s_cache_mode;
4612 fl = pte_l1_s_cache_mode_pt;
4616 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4617 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL);
4618 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4625 * Link the L2 page table specified by l2pv.pv_pa into the L1
4626 * page table at the slot for "va".
4629 pmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv)
4631 pd_entry_t *pde = (pd_entry_t *) l1pt, proto;
4632 u_int slot = va >> L1_S_SHIFT;
4634 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO;
4636 #ifdef VERBOSE_INIT_ARM
4637 printf("pmap_link_l2pt: pa=0x%x va=0x%x\n", l2pv->pv_pa, l2pv->pv_va);
4640 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000);
4642 PTE_SYNC(&pde[slot]);
4644 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list);
4652 * Create a single page mapping.
4655 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot,
4658 pd_entry_t *pde = (pd_entry_t *) l1pt;
4662 KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin"));
4671 fl = pte_l2_s_cache_mode;
4675 fl = pte_l2_s_cache_mode_pt;
4679 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4680 panic("pmap_map_entry: no L2 table for VA 0x%08x", va);
4682 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4685 panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va);
4687 pte[l2pte_index(va)] =
4688 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl;
4689 PTE_SYNC(&pte[l2pte_index(va)]);
4695 * Map a chunk of memory using the most efficient mappings
4696 * possible (section. large page, small page) into the
4697 * provided L1 and L2 tables at the specified virtual address.
4700 pmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4701 vm_size_t size, int prot, int cache)
4703 pd_entry_t *pde = (pd_entry_t *) l1pt;
4704 pt_entry_t *pte, f1, f2s, f2l;
4708 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
4711 panic("pmap_map_chunk: no L1 table provided");
4713 #ifdef VERBOSE_INIT_ARM
4714 printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x "
4715 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache);
4727 f1 = pte_l1_s_cache_mode;
4728 f2l = pte_l2_l_cache_mode;
4729 f2s = pte_l2_s_cache_mode;
4733 f1 = pte_l1_s_cache_mode_pt;
4734 f2l = pte_l2_l_cache_mode_pt;
4735 f2s = pte_l2_s_cache_mode_pt;
4742 /* See if we can use a section mapping. */
4743 if (L1_S_MAPPABLE_P(va, pa, resid)) {
4744 #ifdef VERBOSE_INIT_ARM
4747 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4748 L1_S_PROT(PTE_KERNEL, prot) | f1 |
4749 L1_S_DOM(PMAP_DOMAIN_KERNEL);
4750 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4758 * Ok, we're going to use an L2 table. Make sure
4759 * one is actually in the corresponding L1 slot
4760 * for the current VA.
4762 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4763 panic("pmap_map_chunk: no L2 table for VA 0x%08x", va);
4765 pte = (pt_entry_t *) kernel_pt_lookup(
4766 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4768 panic("pmap_map_chunk: can't find L2 table for VA"
4770 /* See if we can use a L2 large page mapping. */
4771 if (L2_L_MAPPABLE_P(va, pa, resid)) {
4772 #ifdef VERBOSE_INIT_ARM
4775 for (i = 0; i < 16; i++) {
4776 pte[l2pte_index(va) + i] =
4778 L2_L_PROT(PTE_KERNEL, prot) | f2l;
4779 PTE_SYNC(&pte[l2pte_index(va) + i]);
4787 /* Use a small page mapping. */
4788 #ifdef VERBOSE_INIT_ARM
4791 pte[l2pte_index(va)] =
4792 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s;
4793 PTE_SYNC(&pte[l2pte_index(va)]);
4798 #ifdef VERBOSE_INIT_ARM
4806 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
4809 * Remember the memattr in a field that gets used to set the appropriate
4810 * bits in the PTEs as mappings are established.
4812 m->md.pv_memattr = ma;
4815 * It appears that this function can only be called before any mappings
4816 * for the page are established on ARM. If this ever changes, this code
4817 * will need to walk the pv_list and make each of the existing mappings
4818 * uncacheable, being careful to sync caches and PTEs (and maybe
4819 * invalidate TLB?) for any current mapping it modifies.
4821 if (m->md.pv_kva != 0 || TAILQ_FIRST(&m->md.pv_list) != NULL)
4822 panic("Can't change memattr on page with existing mappings");