1 /* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */
3 * Copyright 2004 Olivier Houchard.
4 * Copyright 2003 Wasabi Systems, Inc.
7 * Written by Steve C. Woodford for Wasabi Systems, Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
39 * Copyright (c) 2002-2003 Wasabi Systems, Inc.
40 * Copyright (c) 2001 Richard Earnshaw
41 * Copyright (c) 2001-2002 Christopher Gilbert
42 * All rights reserved.
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. The name of the company nor the name of the author may be used to
50 * endorse or promote products derived from this software without specific
51 * prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
66 * Copyright (c) 1999 The NetBSD Foundation, Inc.
67 * All rights reserved.
69 * This code is derived from software contributed to The NetBSD Foundation
70 * by Charles M. Hannum.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
80 * 3. All advertising materials mentioning features or use of this software
81 * must display the following acknowledgement:
82 * This product includes software developed by the NetBSD
83 * Foundation, Inc. and its contributors.
84 * 4. Neither the name of The NetBSD Foundation nor the names of its
85 * contributors may be used to endorse or promote products derived
86 * from this software without specific prior written permission.
88 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
89 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
90 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
91 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
92 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
93 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
94 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
95 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
96 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
97 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
98 * POSSIBILITY OF SUCH DAMAGE.
102 * Copyright (c) 1994-1998 Mark Brinicombe.
103 * Copyright (c) 1994 Brini.
104 * All rights reserved.
106 * This code is derived from software written for Brini by Mark Brinicombe
108 * Redistribution and use in source and binary forms, with or without
109 * modification, are permitted provided that the following conditions
111 * 1. Redistributions of source code must retain the above copyright
112 * notice, this list of conditions and the following disclaimer.
113 * 2. Redistributions in binary form must reproduce the above copyright
114 * notice, this list of conditions and the following disclaimer in the
115 * documentation and/or other materials provided with the distribution.
116 * 3. All advertising materials mentioning features or use of this software
117 * must display the following acknowledgement:
118 * This product includes software developed by Mark Brinicombe.
119 * 4. The name of the author may not be used to endorse or promote products
120 * derived from this software without specific prior written permission.
122 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
123 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
124 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
125 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
126 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
127 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
128 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
129 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
130 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
132 * RiscBSD kernel project
136 * Machine dependant vm stuff
142 * Special compilation symbols
143 * PMAP_DEBUG - Build in pmap_debug_level code
145 /* Include header files */
149 #include <sys/cdefs.h>
150 __FBSDID("$FreeBSD$");
151 #include <sys/param.h>
152 #include <sys/systm.h>
153 #include <sys/kernel.h>
155 #include <sys/proc.h>
156 #include <sys/malloc.h>
157 #include <sys/msgbuf.h>
158 #include <sys/vmmeter.h>
159 #include <sys/mman.h>
161 #include <sys/sched.h>
166 #include <vm/vm_kern.h>
167 #include <vm/vm_object.h>
168 #include <vm/vm_map.h>
169 #include <vm/vm_page.h>
170 #include <vm/vm_pageout.h>
171 #include <vm/vm_extern.h>
172 #include <sys/lock.h>
173 #include <sys/mutex.h>
174 #include <machine/md_var.h>
175 #include <machine/vmparam.h>
176 #include <machine/cpu.h>
177 #include <machine/cpufunc.h>
178 #include <machine/pcb.h>
181 #define PDEBUG(_lev_,_stat_) \
182 if (pmap_debug_level >= (_lev_)) \
184 #define dprintf printf
186 int pmap_debug_level = 0;
188 #else /* PMAP_DEBUG */
189 #define PDEBUG(_lev_,_stat_) /* Nothing */
190 #define dprintf(x, arg...)
191 #define PMAP_INLINE __inline
192 #endif /* PMAP_DEBUG */
194 extern struct pv_addr systempage;
196 * Internal function prototypes
198 static void pmap_free_pv_entry (pv_entry_t);
199 static pv_entry_t pmap_get_pv_entry(void);
201 static void pmap_enter_locked(pmap_t, vm_offset_t, vm_page_t,
202 vm_prot_t, boolean_t, int);
203 static __inline void pmap_fix_cache(struct vm_page *, pmap_t,
205 static void pmap_alloc_l1(pmap_t);
206 static void pmap_free_l1(pmap_t);
207 static void pmap_use_l1(pmap_t);
209 static int pmap_clearbit(struct vm_page *, u_int);
211 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t);
212 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t);
213 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int);
214 static vm_offset_t kernel_pt_lookup(vm_paddr_t);
216 static MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1");
218 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
219 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
220 vm_offset_t pmap_curmaxkvaddr;
221 vm_paddr_t kernel_l1pa;
224 vm_offset_t kernel_vm_end = 0;
226 struct pmap kernel_pmap_store;
229 static pt_entry_t *csrc_pte, *cdst_pte;
230 static vm_offset_t csrcp, cdstp;
231 static struct mtx cmtx;
233 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *);
235 * These routines are called when the CPU type is identified to set up
236 * the PTE prototypes, cache modes, etc.
238 * The variables are always here, just in case LKMs need to reference
239 * them (though, they shouldn't).
242 pt_entry_t pte_l1_s_cache_mode;
243 pt_entry_t pte_l1_s_cache_mode_pt;
244 pt_entry_t pte_l1_s_cache_mask;
246 pt_entry_t pte_l2_l_cache_mode;
247 pt_entry_t pte_l2_l_cache_mode_pt;
248 pt_entry_t pte_l2_l_cache_mask;
250 pt_entry_t pte_l2_s_cache_mode;
251 pt_entry_t pte_l2_s_cache_mode_pt;
252 pt_entry_t pte_l2_s_cache_mask;
254 pt_entry_t pte_l2_s_prot_u;
255 pt_entry_t pte_l2_s_prot_w;
256 pt_entry_t pte_l2_s_prot_mask;
258 pt_entry_t pte_l1_s_proto;
259 pt_entry_t pte_l1_c_proto;
260 pt_entry_t pte_l2_s_proto;
262 void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t);
263 void (*pmap_zero_page_func)(vm_paddr_t, int, int);
265 * Which pmap is currently 'live' in the cache
267 * XXXSCW: Fix for SMP ...
269 union pmap_cache_state *pmap_cache_state;
271 struct msgbuf *msgbufp = 0;
273 extern void bcopy_page(vm_offset_t, vm_offset_t);
274 extern void bzero_page(vm_offset_t);
276 extern vm_offset_t alloc_firstaddr;
281 * Metadata for L1 translation tables.
284 /* Entry on the L1 Table list */
285 SLIST_ENTRY(l1_ttable) l1_link;
287 /* Entry on the L1 Least Recently Used list */
288 TAILQ_ENTRY(l1_ttable) l1_lru;
290 /* Track how many domains are allocated from this L1 */
291 volatile u_int l1_domain_use_count;
294 * A free-list of domain numbers for this L1.
295 * We avoid using ffs() and a bitmap to track domains since ffs()
298 u_int8_t l1_domain_first;
299 u_int8_t l1_domain_free[PMAP_DOMAINS];
301 /* Physical address of this L1 page table */
302 vm_paddr_t l1_physaddr;
304 /* KVA of this L1 page table */
309 * Convert a virtual address into its L1 table index. That is, the
310 * index used to locate the L2 descriptor table pointer in an L1 table.
311 * This is basically used to index l1->l1_kva[].
313 * Each L2 descriptor table represents 1MB of VA space.
315 #define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT)
318 * L1 Page Tables are tracked using a Least Recently Used list.
319 * - New L1s are allocated from the HEAD.
320 * - Freed L1s are added to the TAIl.
321 * - Recently accessed L1s (where an 'access' is some change to one of
322 * the userland pmaps which owns this L1) are moved to the TAIL.
324 static TAILQ_HEAD(, l1_ttable) l1_lru_list;
326 * A list of all L1 tables
328 static SLIST_HEAD(, l1_ttable) l1_list;
329 static struct mtx l1_lru_lock;
332 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots.
334 * This is normally 16MB worth L2 page descriptors for any given pmap.
335 * Reference counts are maintained for L2 descriptors so they can be
339 /* The number of L2 page descriptors allocated to this l2_dtable */
342 /* List of L2 page descriptors */
344 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */
345 vm_paddr_t l2b_phys; /* Physical address of same */
346 u_short l2b_l1idx; /* This L2 table's L1 index */
347 u_short l2b_occupancy; /* How many active descriptors */
348 } l2_bucket[L2_BUCKET_SIZE];
351 /* pmap_kenter_internal flags */
352 #define KENTER_CACHE 0x1
353 #define KENTER_USER 0x2
356 * Given an L1 table index, calculate the corresponding l2_dtable index
357 * and bucket index within the l2_dtable.
359 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \
361 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1))
364 * Given a virtual address, this macro returns the
365 * virtual address required to drop into the next L2 bucket.
367 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE)
372 #define pmap_alloc_l2_dtable() \
373 (void*)uma_zalloc(l2table_zone, M_NOWAIT|M_USE_RESERVE)
374 #define pmap_free_l2_dtable(l2) \
375 uma_zfree(l2table_zone, l2)
378 * We try to map the page tables write-through, if possible. However, not
379 * all CPUs have a write-through cache mode, so on those we have to sync
380 * the cache when we frob page tables.
382 * We try to evaluate this at compile time, if possible. However, it's
383 * not always possible to do that, hence this run-time var.
385 int pmap_needs_pte_sync;
388 * Macro to determine if a mapping might be resident in the
389 * instruction cache and/or TLB
391 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC))
394 * Macro to determine if a mapping might be resident in the
395 * data cache and/or TLB
397 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0)
399 #ifndef PMAP_SHPGPERPROC
400 #define PMAP_SHPGPERPROC 200
403 #define pmap_is_current(pm) ((pm) == pmap_kernel() || \
404 curproc->p_vmspace->vm_map.pmap == (pm))
405 static uma_zone_t pvzone;
407 static uma_zone_t l2table_zone;
408 static vm_offset_t pmap_kernel_l2dtable_kva;
409 static vm_offset_t pmap_kernel_l2ptp_kva;
410 static vm_paddr_t pmap_kernel_l2ptp_phys;
411 static struct vm_object pvzone_obj;
412 static int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0;
415 * This list exists for the benefit of pmap_map_chunk(). It keeps track
416 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can
417 * find them as necessary.
419 * Note that the data on this list MUST remain valid after initarm() returns,
420 * as pmap_bootstrap() uses it to contruct L2 table metadata.
422 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list);
425 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt)
430 l1->l1_domain_use_count = 0;
431 l1->l1_domain_first = 0;
433 for (i = 0; i < PMAP_DOMAINS; i++)
434 l1->l1_domain_free[i] = i + 1;
437 * Copy the kernel's L1 entries to each new L1.
439 if (l1pt != pmap_kernel()->pm_l1->l1_kva)
440 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE);
442 if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0)
443 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt);
444 SLIST_INSERT_HEAD(&l1_list, l1, l1_link);
445 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
449 kernel_pt_lookup(vm_paddr_t pa)
453 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) {
460 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
462 pmap_pte_init_generic(void)
465 pte_l1_s_cache_mode = L1_S_B|L1_S_C;
466 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic;
468 pte_l2_l_cache_mode = L2_B|L2_C;
469 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic;
471 pte_l2_s_cache_mode = L2_B|L2_C;
472 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic;
475 * If we have a write-through cache, set B and C. If
476 * we have a write-back cache, then we assume setting
477 * only C will make those pages write-through.
479 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) {
480 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
481 pte_l2_l_cache_mode_pt = L2_B|L2_C;
482 pte_l2_s_cache_mode_pt = L2_B|L2_C;
484 pte_l1_s_cache_mode_pt = L1_S_C;
485 pte_l2_l_cache_mode_pt = L2_C;
486 pte_l2_s_cache_mode_pt = L2_C;
489 pte_l2_s_prot_u = L2_S_PROT_U_generic;
490 pte_l2_s_prot_w = L2_S_PROT_W_generic;
491 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic;
493 pte_l1_s_proto = L1_S_PROTO_generic;
494 pte_l1_c_proto = L1_C_PROTO_generic;
495 pte_l2_s_proto = L2_S_PROTO_generic;
497 pmap_copy_page_func = pmap_copy_page_generic;
498 pmap_zero_page_func = pmap_zero_page_generic;
501 #if defined(CPU_ARM8)
503 pmap_pte_init_arm8(void)
507 * ARM8 is compatible with generic, but we need to use
508 * the page tables uncached.
510 pmap_pte_init_generic();
512 pte_l1_s_cache_mode_pt = 0;
513 pte_l2_l_cache_mode_pt = 0;
514 pte_l2_s_cache_mode_pt = 0;
516 #endif /* CPU_ARM8 */
518 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH)
520 pmap_pte_init_arm9(void)
524 * ARM9 is compatible with generic, but we want to use
525 * write-through caching for now.
527 pmap_pte_init_generic();
529 pte_l1_s_cache_mode = L1_S_C;
530 pte_l2_l_cache_mode = L2_C;
531 pte_l2_s_cache_mode = L2_C;
533 pte_l1_s_cache_mode_pt = L1_S_C;
534 pte_l2_l_cache_mode_pt = L2_C;
535 pte_l2_s_cache_mode_pt = L2_C;
537 #endif /* CPU_ARM9 */
538 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
540 #if defined(CPU_ARM10)
542 pmap_pte_init_arm10(void)
546 * ARM10 is compatible with generic, but we want to use
547 * write-through caching for now.
549 pmap_pte_init_generic();
551 pte_l1_s_cache_mode = L1_S_B | L1_S_C;
552 pte_l2_l_cache_mode = L2_B | L2_C;
553 pte_l2_s_cache_mode = L2_B | L2_C;
555 pte_l1_s_cache_mode_pt = L1_S_C;
556 pte_l2_l_cache_mode_pt = L2_C;
557 pte_l2_s_cache_mode_pt = L2_C;
560 #endif /* CPU_ARM10 */
564 pmap_pte_init_sa1(void)
568 * The StrongARM SA-1 cache does not have a write-through
569 * mode. So, do the generic initialization, then reset
570 * the page table cache mode to B=1,C=1, and note that
571 * the PTEs need to be sync'd.
573 pmap_pte_init_generic();
575 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
576 pte_l2_l_cache_mode_pt = L2_B|L2_C;
577 pte_l2_s_cache_mode_pt = L2_B|L2_C;
579 pmap_needs_pte_sync = 1;
581 #endif /* ARM_MMU_SA1 == 1*/
583 #if ARM_MMU_XSCALE == 1
584 #if (ARM_NMMUS > 1) || defined (CPU_XSCALE_CORE3)
585 static u_int xscale_use_minidata;
589 pmap_pte_init_xscale(void)
592 int write_through = 0;
594 pte_l1_s_cache_mode = L1_S_B|L1_S_C|L1_S_XSCALE_P;
595 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale;
597 pte_l2_l_cache_mode = L2_B|L2_C;
598 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale;
600 pte_l2_s_cache_mode = L2_B|L2_C;
601 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale;
603 pte_l1_s_cache_mode_pt = L1_S_C;
604 pte_l2_l_cache_mode_pt = L2_C;
605 pte_l2_s_cache_mode_pt = L2_C;
606 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE
608 * The XScale core has an enhanced mode where writes that
609 * miss the cache cause a cache line to be allocated. This
610 * is significantly faster than the traditional, write-through
611 * behavior of this case.
613 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X);
614 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X);
615 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X);
616 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */
617 #ifdef XSCALE_CACHE_WRITE_THROUGH
619 * Some versions of the XScale core have various bugs in
620 * their cache units, the work-around for which is to run
621 * the cache in write-through mode. Unfortunately, this
622 * has a major (negative) impact on performance. So, we
623 * go ahead and run fast-and-loose, in the hopes that we
624 * don't line up the planets in a way that will trip the
627 * However, we give you the option to be slow-but-correct.
630 #elif defined(XSCALE_CACHE_WRITE_BACK)
631 /* force write back cache mode */
633 #elif defined(CPU_XSCALE_PXA2X0)
635 * Intel PXA2[15]0 processors are known to have a bug in
636 * write-back cache on revision 4 and earlier (stepping
637 * A[01] and B[012]). Fixed for C0 and later.
643 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK);
645 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) {
646 if ((id & CPU_ID_REVISION_MASK) < 5) {
647 /* write through for stepping A0-1 and B0-2 */
652 #endif /* XSCALE_CACHE_WRITE_THROUGH */
655 pte_l1_s_cache_mode = L1_S_C;
656 pte_l2_l_cache_mode = L2_C;
657 pte_l2_s_cache_mode = L2_C;
661 xscale_use_minidata = 1;
664 pte_l2_s_prot_u = L2_S_PROT_U_xscale;
665 pte_l2_s_prot_w = L2_S_PROT_W_xscale;
666 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale;
668 pte_l1_s_proto = L1_S_PROTO_xscale;
669 pte_l1_c_proto = L1_C_PROTO_xscale;
670 pte_l2_s_proto = L2_S_PROTO_xscale;
672 #ifdef CPU_XSCALE_CORE3
673 pmap_copy_page_func = pmap_copy_page_generic;
674 pmap_zero_page_func = pmap_zero_page_generic;
675 xscale_use_minidata = 0;
676 /* Make sure it is L2-cachable */
677 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_T);
678 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode &~ L1_S_XSCALE_P;
679 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_T) ;
680 pte_l2_l_cache_mode_pt = pte_l1_s_cache_mode;
681 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_T);
682 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode;
685 pmap_copy_page_func = pmap_copy_page_xscale;
686 pmap_zero_page_func = pmap_zero_page_xscale;
690 * Disable ECC protection of page table access, for now.
692 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
693 auxctl &= ~XSCALE_AUXCTL_P;
694 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
698 * xscale_setup_minidata:
700 * Set up the mini-data cache clean area. We require the
701 * caller to allocate the right amount of physically and
702 * virtually contiguous space.
704 extern vm_offset_t xscale_minidata_clean_addr;
705 extern vm_size_t xscale_minidata_clean_size; /* already initialized */
707 xscale_setup_minidata(vm_offset_t l1pt, vm_offset_t va, vm_paddr_t pa)
709 pd_entry_t *pde = (pd_entry_t *) l1pt;
714 xscale_minidata_clean_addr = va;
716 /* Round it to page size. */
717 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME;
720 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) {
721 pte = (pt_entry_t *) kernel_pt_lookup(
722 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
724 panic("xscale_setup_minidata: can't find L2 table for "
725 "VA 0x%08x", (u_int32_t) va);
726 pte[l2pte_index(va)] =
727 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
728 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X);
732 * Configure the mini-data cache for write-back with
733 * read/write-allocate.
735 * NOTE: In order to reconfigure the mini-data cache, we must
736 * make sure it contains no valid data! In order to do that,
737 * we must issue a global data cache invalidate command!
739 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED!
740 * THIS IS VERY IMPORTANT!
743 /* Invalidate data and mini-data. */
744 __asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
745 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
746 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA;
747 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
752 * Allocate an L1 translation table for the specified pmap.
753 * This is called at pmap creation time.
756 pmap_alloc_l1(pmap_t pm)
758 struct l1_ttable *l1;
762 * Remove the L1 at the head of the LRU list
764 mtx_lock(&l1_lru_lock);
765 l1 = TAILQ_FIRST(&l1_lru_list);
766 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
769 * Pick the first available domain number, and update
770 * the link to the next number.
772 domain = l1->l1_domain_first;
773 l1->l1_domain_first = l1->l1_domain_free[domain];
776 * If there are still free domain numbers in this L1,
777 * put it back on the TAIL of the LRU list.
779 if (++l1->l1_domain_use_count < PMAP_DOMAINS)
780 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
782 mtx_unlock(&l1_lru_lock);
785 * Fix up the relevant bits in the pmap structure
788 pm->pm_domain = domain + 1;
792 * Free an L1 translation table.
793 * This is called at pmap destruction time.
796 pmap_free_l1(pmap_t pm)
798 struct l1_ttable *l1 = pm->pm_l1;
800 mtx_lock(&l1_lru_lock);
803 * If this L1 is currently on the LRU list, remove it.
805 if (l1->l1_domain_use_count < PMAP_DOMAINS)
806 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
809 * Free up the domain number which was allocated to the pmap
811 l1->l1_domain_free[pm->pm_domain - 1] = l1->l1_domain_first;
812 l1->l1_domain_first = pm->pm_domain - 1;
813 l1->l1_domain_use_count--;
816 * The L1 now must have at least 1 free domain, so add
817 * it back to the LRU list. If the use count is zero,
818 * put it at the head of the list, otherwise it goes
821 if (l1->l1_domain_use_count == 0) {
822 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru);
824 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
826 mtx_unlock(&l1_lru_lock);
829 static PMAP_INLINE void
830 pmap_use_l1(pmap_t pm)
832 struct l1_ttable *l1;
835 * Do nothing if we're in interrupt context.
836 * Access to an L1 by the kernel pmap must not affect
839 if (pm == pmap_kernel())
845 * If the L1 is not currently on the LRU list, just return
847 if (l1->l1_domain_use_count == PMAP_DOMAINS)
850 mtx_lock(&l1_lru_lock);
853 * Check the use count again, now that we've acquired the lock
855 if (l1->l1_domain_use_count == PMAP_DOMAINS) {
856 mtx_unlock(&l1_lru_lock);
861 * Move the L1 to the back of the LRU list
863 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
864 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
866 mtx_unlock(&l1_lru_lock);
871 * Returns a pointer to the L2 bucket associated with the specified pmap
872 * and VA, or NULL if no L2 bucket exists for the address.
874 static PMAP_INLINE struct l2_bucket *
875 pmap_get_l2_bucket(pmap_t pm, vm_offset_t va)
877 struct l2_dtable *l2;
878 struct l2_bucket *l2b;
883 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL ||
884 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL)
891 * Returns a pointer to the L2 bucket associated with the specified pmap
894 * If no L2 bucket exists, perform the necessary allocations to put an L2
895 * bucket/page table in place.
897 * Note that if a new L2 bucket/page was allocated, the caller *must*
898 * increment the bucket occupancy counter appropriately *before*
899 * releasing the pmap's lock to ensure no other thread or cpu deallocates
900 * the bucket/page in the meantime.
902 static struct l2_bucket *
903 pmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va)
905 struct l2_dtable *l2;
906 struct l2_bucket *l2b;
911 PMAP_ASSERT_LOCKED(pm);
912 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
913 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
915 * No mapping at this address, as there is
916 * no entry in the L1 table.
917 * Need to allocate a new l2_dtable.
921 vm_page_unlock_queues();
922 if ((l2 = pmap_alloc_l2_dtable()) == NULL) {
923 vm_page_lock_queues();
927 vm_page_lock_queues();
929 if (pm->pm_l2[L2_IDX(l1idx)] != NULL) {
931 vm_page_unlock_queues();
932 uma_zfree(l2table_zone, l2);
933 vm_page_lock_queues();
935 l2 = pm->pm_l2[L2_IDX(l1idx)];
939 * Someone already allocated the l2_dtable while
940 * we were doing the same.
943 bzero(l2, sizeof(*l2));
945 * Link it into the parent pmap
947 pm->pm_l2[L2_IDX(l1idx)] = l2;
951 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
954 * Fetch pointer to the L2 page table associated with the address.
956 if (l2b->l2b_kva == NULL) {
960 * No L2 page table has been allocated. Chances are, this
961 * is because we just allocated the l2_dtable, above.
965 vm_page_unlock_queues();
966 ptep = (void*)uma_zalloc(l2zone, M_NOWAIT|M_USE_RESERVE);
967 vm_page_lock_queues();
969 if (l2b->l2b_kva != 0) {
970 /* We lost the race. */
972 vm_page_unlock_queues();
973 uma_zfree(l2zone, ptep);
974 vm_page_lock_queues();
976 if (l2b->l2b_kva == 0)
980 l2b->l2b_phys = vtophys(ptep);
983 * Oops, no more L2 page tables available at this
984 * time. We may need to deallocate the l2_dtable
985 * if we allocated a new one above.
987 if (l2->l2_occupancy == 0) {
988 pm->pm_l2[L2_IDX(l1idx)] = NULL;
989 pmap_free_l2_dtable(l2);
996 l2b->l2b_l1idx = l1idx;
1002 static PMAP_INLINE void
1003 #ifndef PMAP_INCLUDE_PTE_SYNC
1004 pmap_free_l2_ptp(pt_entry_t *l2)
1006 pmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2)
1009 #ifdef PMAP_INCLUDE_PTE_SYNC
1011 * Note: With a write-back cache, we may need to sync this
1012 * L2 table before re-using it.
1013 * This is because it may have belonged to a non-current
1014 * pmap, in which case the cache syncs would have been
1015 * skipped when the pages were being unmapped. If the
1016 * L2 table were then to be immediately re-allocated to
1017 * the *current* pmap, it may well contain stale mappings
1018 * which have not yet been cleared by a cache write-back
1019 * and so would still be visible to the mmu.
1022 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
1024 uma_zfree(l2zone, l2);
1027 * One or more mappings in the specified L2 descriptor table have just been
1030 * Garbage collect the metadata and descriptor table itself if necessary.
1032 * The pmap lock must be acquired when this is called (not necessary
1033 * for the kernel pmap).
1036 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count)
1038 struct l2_dtable *l2;
1039 pd_entry_t *pl1pd, l1pd;
1045 * Update the bucket's reference count according to how many
1046 * PTEs the caller has just invalidated.
1048 l2b->l2b_occupancy -= count;
1053 * Level 2 page tables allocated to the kernel pmap are never freed
1054 * as that would require checking all Level 1 page tables and
1055 * removing any references to the Level 2 page table. See also the
1056 * comment elsewhere about never freeing bootstrap L2 descriptors.
1058 * We make do with just invalidating the mapping in the L2 table.
1060 * This isn't really a big deal in practice and, in fact, leads
1061 * to a performance win over time as we don't need to continually
1064 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel())
1068 * There are no more valid mappings in this level 2 page table.
1069 * Go ahead and NULL-out the pointer in the bucket, then
1070 * free the page table.
1072 l1idx = l2b->l2b_l1idx;
1073 ptep = l2b->l2b_kva;
1074 l2b->l2b_kva = NULL;
1076 pl1pd = &pm->pm_l1->l1_kva[l1idx];
1079 * If the L1 slot matches the pmap's domain
1080 * number, then invalidate it.
1082 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK);
1083 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) {
1089 * Release the L2 descriptor table back to the pool cache.
1091 #ifndef PMAP_INCLUDE_PTE_SYNC
1092 pmap_free_l2_ptp(ptep);
1094 pmap_free_l2_ptp(!pmap_is_current(pm), ptep);
1098 * Update the reference count in the associated l2_dtable
1100 l2 = pm->pm_l2[L2_IDX(l1idx)];
1101 if (--l2->l2_occupancy > 0)
1105 * There are no more valid mappings in any of the Level 1
1106 * slots managed by this l2_dtable. Go ahead and NULL-out
1107 * the pointer in the parent pmap and free the l2_dtable.
1109 pm->pm_l2[L2_IDX(l1idx)] = NULL;
1110 pmap_free_l2_dtable(l2);
1114 * Pool cache constructors for L2 descriptor tables, metadata and pmap
1118 pmap_l2ptp_ctor(void *mem, int size, void *arg, int flags)
1120 #ifndef PMAP_INCLUDE_PTE_SYNC
1121 struct l2_bucket *l2b;
1122 pt_entry_t *ptep, pte;
1123 #ifdef ARM_USE_SMALL_ALLOC
1126 vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK;
1129 * The mappings for these page tables were initially made using
1130 * pmap_kenter() by the pool subsystem. Therefore, the cache-
1131 * mode will not be right for page table mappings. To avoid
1132 * polluting the pmap_kenter() code with a special case for
1133 * page tables, we simply fix up the cache-mode here if it's not
1136 #ifdef ARM_USE_SMALL_ALLOC
1137 pde = &kernel_pmap->pm_l1->l1_kva[L1_IDX(va)];
1138 if (!l1pte_section_p(*pde)) {
1140 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
1141 ptep = &l2b->l2b_kva[l2pte_index(va)];
1144 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
1146 * Page tables must have the cache-mode set to
1149 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
1151 cpu_tlb_flushD_SE(va);
1154 #ifdef ARM_USE_SMALL_ALLOC
1158 memset(mem, 0, L2_TABLE_SIZE_REAL);
1159 PTE_SYNC_RANGE(mem, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
1164 * A bunch of routines to conditionally flush the caches/TLB depending
1165 * on whether the specified pmap actually needs to be flushed at any
1168 static PMAP_INLINE void
1169 pmap_tlb_flushID_SE(pmap_t pm, vm_offset_t va)
1172 if (pmap_is_current(pm))
1173 cpu_tlb_flushID_SE(va);
1176 static PMAP_INLINE void
1177 pmap_tlb_flushD_SE(pmap_t pm, vm_offset_t va)
1180 if (pmap_is_current(pm))
1181 cpu_tlb_flushD_SE(va);
1184 static PMAP_INLINE void
1185 pmap_tlb_flushID(pmap_t pm)
1188 if (pmap_is_current(pm))
1191 static PMAP_INLINE void
1192 pmap_tlb_flushD(pmap_t pm)
1195 if (pmap_is_current(pm))
1199 static PMAP_INLINE void
1200 pmap_l2cache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len)
1206 rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len);
1209 CTR4(KTR_PMAP, "pmap_l2cache_wbinv_range: pmap %p is_kernel %d "
1210 "va 0x%08x len 0x%x ", pm, pm == pmap_kernel(), va, rest);
1211 if (pmap_get_pde_pte(pm, va, &pde, &ptep) && l2pte_valid(*ptep))
1212 cpu_l2cache_wb_range(va, rest);
1217 rest = MIN(PAGE_SIZE, len);
1221 static PMAP_INLINE void
1222 pmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len)
1225 if (pmap_is_current(pm)) {
1226 cpu_idcache_wbinv_range(va, len);
1227 pmap_l2cache_wbinv_range(pm, va, len);
1231 static PMAP_INLINE void
1232 pmap_l2cache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len)
1238 rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len);
1241 CTR4(KTR_PMAP, "pmap_l2cache_wb_range: pmap %p is_kernel %d "
1242 "va 0x%08x len 0x%x ", pm, pm == pmap_kernel(), va, rest);
1243 if (pmap_get_pde_pte(pm, va, &pde, &ptep) && l2pte_valid(*ptep))
1244 cpu_l2cache_wb_range(va, rest);
1249 rest = MIN(PAGE_SIZE, len);
1253 static PMAP_INLINE void
1254 pmap_l2cache_inv_range(pmap_t pm, vm_offset_t va, vm_size_t len)
1260 rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len);
1263 CTR4(KTR_PMAP, "pmap_l2cache_wb_range: pmap %p is_kernel %d "
1264 "va 0x%08x len 0x%x ", pm, pm == pmap_kernel(), va, rest);
1265 if (pmap_get_pde_pte(pm, va, &pde, &ptep) && l2pte_valid(*ptep))
1266 cpu_l2cache_inv_range(va, rest);
1271 rest = MIN(PAGE_SIZE, len);
1275 static PMAP_INLINE void
1276 pmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len, boolean_t do_inv,
1279 CTR4(KTR_PMAP, "pmap_dcache_wb_range: pmap %p is_kernel %d va 0x%08x "
1280 "len 0x%x ", pm, pm == pmap_kernel(), va, len);
1281 CTR2(KTR_PMAP, " do_inv %d rd_only %d", do_inv, rd_only);
1283 if (pmap_is_current(pm)) {
1286 cpu_dcache_inv_range(va, len);
1287 pmap_l2cache_inv_range(pm, va, len);
1290 cpu_dcache_wbinv_range(va, len);
1291 pmap_l2cache_wbinv_range(pm, va, len);
1295 cpu_dcache_wb_range(va, len);
1296 pmap_l2cache_wb_range(pm, va, len);
1301 static PMAP_INLINE void
1302 pmap_idcache_wbinv_all(pmap_t pm)
1305 if (pmap_is_current(pm)) {
1306 cpu_idcache_wbinv_all();
1307 cpu_l2cache_wbinv_all();
1311 static PMAP_INLINE void
1312 pmap_dcache_wbinv_all(pmap_t pm)
1315 if (pmap_is_current(pm)) {
1316 cpu_dcache_wbinv_all();
1317 cpu_l2cache_wbinv_all();
1324 * Make sure the pte is written out to RAM.
1325 * We need to do this for one of two cases:
1326 * - We're dealing with the kernel pmap
1327 * - There is no pmap active in the cache/tlb.
1328 * - The specified pmap is 'active' in the cache/tlb.
1330 #ifdef PMAP_INCLUDE_PTE_SYNC
1331 #define PTE_SYNC_CURRENT(pm, ptep) \
1333 if (PMAP_NEEDS_PTE_SYNC && \
1334 pmap_is_current(pm)) \
1336 } while (/*CONSTCOND*/0)
1338 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */
1342 * cacheable == -1 means we must make the entry uncacheable, 1 means
1345 static __inline void
1346 pmap_set_cache_entry(pv_entry_t pv, pmap_t pm, vm_offset_t va, int cacheable)
1348 struct l2_bucket *l2b;
1349 pt_entry_t *ptep, pte;
1351 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
1352 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
1354 if (cacheable == 1) {
1355 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode;
1356 if (l2pte_valid(pte)) {
1357 if (PV_BEEN_EXECD(pv->pv_flags)) {
1358 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va);
1359 } else if (PV_BEEN_REFD(pv->pv_flags)) {
1360 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va);
1364 pte = *ptep &~ L2_S_CACHE_MASK;
1365 if ((va != pv->pv_va || pm != pv->pv_pmap) &&
1367 if (PV_BEEN_EXECD(pv->pv_flags)) {
1368 pmap_idcache_wbinv_range(pv->pv_pmap,
1369 pv->pv_va, PAGE_SIZE);
1370 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va);
1371 } else if (PV_BEEN_REFD(pv->pv_flags)) {
1372 pmap_dcache_wb_range(pv->pv_pmap,
1373 pv->pv_va, PAGE_SIZE, TRUE,
1374 (pv->pv_flags & PVF_WRITE) == 0);
1375 pmap_tlb_flushD_SE(pv->pv_pmap,
1381 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
1385 pmap_fix_cache(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1388 int writable = 0, kwritable = 0, uwritable = 0;
1389 int entries = 0, kentries = 0, uentries = 0;
1390 struct pv_entry *pv;
1392 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1394 /* the cache gets written back/invalidated on context switch.
1395 * therefore, if a user page shares an entry in the same page or
1396 * with the kernel map and at least one is writable, then the
1397 * cache entry must be set write-through.
1400 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1401 /* generate a count of the pv_entry uses */
1402 if (pv->pv_flags & PVF_WRITE) {
1403 if (pv->pv_pmap == pmap_kernel())
1405 else if (pv->pv_pmap == pm)
1409 if (pv->pv_pmap == pmap_kernel())
1412 if (pv->pv_pmap == pm)
1418 * check if the user duplicate mapping has
1421 if ((pm != pmap_kernel()) && (((uentries > 1) && uwritable) ||
1425 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1426 /* check for user uncachable conditions - order is important */
1427 if (pm != pmap_kernel() &&
1428 (pv->pv_pmap == pm || pv->pv_pmap == pmap_kernel())) {
1430 if ((uentries > 1 && uwritable) || uwritable > 1) {
1432 /* user duplicate mapping */
1433 if (pv->pv_pmap != pmap_kernel())
1434 pv->pv_flags |= PVF_MWC;
1436 if (!(pv->pv_flags & PVF_NC)) {
1437 pv->pv_flags |= PVF_NC;
1438 pmap_set_cache_entry(pv, pm, va, -1);
1441 } else /* no longer a duplicate user */
1442 pv->pv_flags &= ~PVF_MWC;
1446 * check for kernel uncachable conditions
1447 * kernel writable or kernel readable with writable user entry
1449 if ((kwritable && entries) ||
1450 ((kwritable != writable) && kentries &&
1451 (pv->pv_pmap == pmap_kernel() ||
1452 (pv->pv_flags & PVF_WRITE) ||
1453 (pv->pv_flags & PVF_MWC)))) {
1455 if (!(pv->pv_flags & PVF_NC)) {
1456 pv->pv_flags |= PVF_NC;
1457 pmap_set_cache_entry(pv, pm, va, -1);
1462 /* kernel and user are cachable */
1463 if ((pm == pmap_kernel()) && !(pv->pv_flags & PVF_MWC) &&
1464 (pv->pv_flags & PVF_NC)) {
1466 pv->pv_flags &= ~PVF_NC;
1467 pmap_set_cache_entry(pv, pm, va, 1);
1470 /* user is no longer sharable and writable */
1471 if (pm != pmap_kernel() && (pv->pv_pmap == pm) &&
1472 !pmwc && (pv->pv_flags & PVF_NC)) {
1474 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1475 pmap_set_cache_entry(pv, pm, va, 1);
1479 if ((kwritable == 0) && (writable == 0)) {
1480 pg->md.pvh_attrs &= ~PVF_MOD;
1481 vm_page_flag_clear(pg, PG_WRITEABLE);
1487 * Modify pte bits for all ptes corresponding to the given physical address.
1488 * We use `maskbits' rather than `clearbits' because we're always passing
1489 * constants and the latter would require an extra inversion at run-time.
1492 pmap_clearbit(struct vm_page *pg, u_int maskbits)
1494 struct l2_bucket *l2b;
1495 struct pv_entry *pv;
1496 pt_entry_t *ptep, npte, opte;
1502 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1504 if (maskbits & PVF_WRITE)
1505 maskbits |= PVF_MOD;
1507 * Clear saved attributes (modify, reference)
1509 pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF));
1511 if (TAILQ_EMPTY(&pg->md.pv_list)) {
1516 * Loop over all current mappings setting/clearing as appropos
1518 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1521 oflags = pv->pv_flags;
1523 if (!(oflags & maskbits)) {
1524 if ((maskbits & PVF_WRITE) && (pv->pv_flags & PVF_NC)) {
1525 /* It is safe to re-enable cacheing here. */
1527 l2b = pmap_get_l2_bucket(pm, va);
1528 ptep = &l2b->l2b_kva[l2pte_index(va)];
1529 *ptep |= pte_l2_s_cache_mode;
1532 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1537 pv->pv_flags &= ~maskbits;
1541 l2b = pmap_get_l2_bucket(pm, va);
1543 ptep = &l2b->l2b_kva[l2pte_index(va)];
1544 npte = opte = *ptep;
1546 if (maskbits & (PVF_WRITE|PVF_MOD)) {
1547 if ((pv->pv_flags & PVF_NC)) {
1549 * Entry is not cacheable:
1551 * Don't turn caching on again if this is a
1552 * modified emulation. This would be
1553 * inconsitent with the settings created by
1554 * pmap_fix_cache(). Otherwise, it's safe
1555 * to re-enable cacheing.
1557 * There's no need to call pmap_fix_cache()
1558 * here: all pages are losing their write
1561 if (maskbits & PVF_WRITE) {
1562 npte |= pte_l2_s_cache_mode;
1563 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1566 if (opte & L2_S_PROT_W) {
1569 * Entry is writable/cacheable: check if pmap
1570 * is current if it is flush it, otherwise it
1571 * won't be in the cache
1573 if (PV_BEEN_EXECD(oflags))
1574 pmap_idcache_wbinv_range(pm, pv->pv_va,
1577 if (PV_BEEN_REFD(oflags))
1578 pmap_dcache_wb_range(pm, pv->pv_va,
1580 (maskbits & PVF_REF) ? TRUE : FALSE,
1584 /* make the pte read only */
1585 npte &= ~L2_S_PROT_W;
1588 if (maskbits & PVF_REF) {
1589 if ((pv->pv_flags & PVF_NC) == 0 &&
1590 (maskbits & (PVF_WRITE|PVF_MOD)) == 0) {
1592 * Check npte here; we may have already
1593 * done the wbinv above, and the validity
1594 * of the PTE is the same for opte and
1597 if (npte & L2_S_PROT_W) {
1598 if (PV_BEEN_EXECD(oflags))
1599 pmap_idcache_wbinv_range(pm,
1600 pv->pv_va, PAGE_SIZE);
1602 if (PV_BEEN_REFD(oflags))
1603 pmap_dcache_wb_range(pm,
1604 pv->pv_va, PAGE_SIZE,
1607 if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) {
1608 /* XXXJRT need idcache_inv_range */
1609 if (PV_BEEN_EXECD(oflags))
1610 pmap_idcache_wbinv_range(pm,
1611 pv->pv_va, PAGE_SIZE);
1613 if (PV_BEEN_REFD(oflags))
1614 pmap_dcache_wb_range(pm,
1615 pv->pv_va, PAGE_SIZE,
1621 * Make the PTE invalid so that we will take a
1622 * page fault the next time the mapping is
1625 npte &= ~L2_TYPE_MASK;
1626 npte |= L2_TYPE_INV;
1633 /* Flush the TLB entry if a current pmap. */
1634 if (PV_BEEN_EXECD(oflags))
1635 pmap_tlb_flushID_SE(pm, pv->pv_va);
1637 if (PV_BEEN_REFD(oflags))
1638 pmap_tlb_flushD_SE(pm, pv->pv_va);
1645 if (maskbits & PVF_WRITE)
1646 vm_page_flag_clear(pg, PG_WRITEABLE);
1651 * main pv_entry manipulation functions:
1652 * pmap_enter_pv: enter a mapping onto a vm_page list
1653 * pmap_remove_pv: remove a mappiing from a vm_page list
1655 * NOTE: pmap_enter_pv expects to lock the pvh itself
1656 * pmap_remove_pv expects te caller to lock the pvh before calling
1660 * pmap_enter_pv: enter a mapping onto a vm_page lst
1662 * => caller should hold the proper lock on pmap_main_lock
1663 * => caller should have pmap locked
1664 * => we will gain the lock on the vm_page and allocate the new pv_entry
1665 * => caller should adjust ptp's wire_count before calling
1666 * => caller should not adjust pmap's wire_count
1669 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm,
1670 vm_offset_t va, u_int flags)
1673 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1674 PMAP_ASSERT_LOCKED(pm);
1677 pve->pv_flags = flags;
1679 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list);
1680 TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist);
1681 pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD);
1682 if (pve->pv_flags & PVF_WIRED)
1683 ++pm->pm_stats.wired_count;
1684 vm_page_flag_set(pg, PG_REFERENCED);
1689 * pmap_find_pv: Find a pv entry
1691 * => caller should hold lock on vm_page
1693 static PMAP_INLINE struct pv_entry *
1694 pmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1696 struct pv_entry *pv;
1698 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1699 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list)
1700 if (pm == pv->pv_pmap && va == pv->pv_va)
1706 * vector_page_setprot:
1708 * Manipulate the protection of the vector page.
1711 vector_page_setprot(int prot)
1713 struct l2_bucket *l2b;
1716 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page);
1718 ptep = &l2b->l2b_kva[l2pte_index(vector_page)];
1720 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot);
1722 cpu_tlb_flushD_SE(vector_page);
1727 * pmap_remove_pv: try to remove a mapping from a pv_list
1729 * => caller should hold proper lock on pmap_main_lock
1730 * => pmap should be locked
1731 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1732 * => caller should adjust ptp's wire_count and free PTP if needed
1733 * => caller should NOT adjust pmap's wire_count
1734 * => we return the removed pve
1738 pmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve)
1741 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1742 PMAP_ASSERT_LOCKED(pm);
1743 TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list);
1744 TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist);
1745 if (pve->pv_flags & PVF_WIRED)
1746 --pm->pm_stats.wired_count;
1747 if (pg->md.pvh_attrs & PVF_MOD)
1749 if (TAILQ_FIRST(&pg->md.pv_list) == NULL)
1750 pg->md.pvh_attrs &= ~PVF_REF;
1752 vm_page_flag_set(pg, PG_REFERENCED);
1753 if ((pve->pv_flags & PVF_NC) && ((pm == pmap_kernel()) ||
1754 (pve->pv_flags & PVF_WRITE) || !(pve->pv_flags & PVF_MWC)))
1755 pmap_fix_cache(pg, pm, 0);
1756 else if (pve->pv_flags & PVF_WRITE) {
1757 TAILQ_FOREACH(pve, &pg->md.pv_list, pv_list)
1758 if (pve->pv_flags & PVF_WRITE)
1761 pg->md.pvh_attrs &= ~PVF_MOD;
1762 vm_page_flag_clear(pg, PG_WRITEABLE);
1767 static struct pv_entry *
1768 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1770 struct pv_entry *pve;
1772 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1773 pve = TAILQ_FIRST(&pg->md.pv_list);
1776 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */
1777 pmap_nuke_pv(pg, pm, pve);
1780 pve = TAILQ_NEXT(pve, pv_list);
1783 return(pve); /* return removed pve */
1787 * pmap_modify_pv: Update pv flags
1789 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1790 * => caller should NOT adjust pmap's wire_count
1791 * => we return the old flags
1793 * Modify a physical-virtual mapping in the pv table
1796 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va,
1797 u_int clr_mask, u_int set_mask)
1799 struct pv_entry *npv;
1800 u_int flags, oflags;
1802 PMAP_ASSERT_LOCKED(pm);
1803 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1804 if ((npv = pmap_find_pv(pg, pm, va)) == NULL)
1808 * There is at least one VA mapping this page.
1811 if (clr_mask & (PVF_REF | PVF_MOD))
1812 pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD);
1814 oflags = npv->pv_flags;
1815 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask;
1817 if ((flags ^ oflags) & PVF_WIRED) {
1818 if (flags & PVF_WIRED)
1819 ++pm->pm_stats.wired_count;
1821 --pm->pm_stats.wired_count;
1824 if ((flags ^ oflags) & PVF_WRITE)
1825 pmap_fix_cache(pg, pm, 0);
1830 /* Function to set the debug level of the pmap code */
1833 pmap_debug(int level)
1835 pmap_debug_level = level;
1836 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
1838 #endif /* PMAP_DEBUG */
1841 pmap_pinit0(struct pmap *pmap)
1843 PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap));
1845 dprintf("pmap_pinit0: pmap = %08x, pm_pdir = %08x\n",
1846 (u_int32_t) pmap, (u_int32_t) pmap->pm_pdir);
1847 bcopy(kernel_pmap, pmap, sizeof(*pmap));
1848 bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx));
1849 PMAP_LOCK_INIT(pmap);
1853 * Initialize a vm_page's machine-dependent fields.
1856 pmap_page_init(vm_page_t m)
1859 TAILQ_INIT(&m->md.pv_list);
1863 * Initialize the pmap module.
1864 * Called by vm_init, to initialize any structures that the pmap
1865 * system needs to map virtual memory.
1870 int shpgperproc = PMAP_SHPGPERPROC;
1872 PDEBUG(1, printf("pmap_init: phys_start = %08x\n"));
1875 * init the pv free list
1877 pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL,
1878 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1880 * Now it is safe to enable pv_table recording.
1882 PDEBUG(1, printf("pmap_init: done!\n"));
1884 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1886 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
1887 pv_entry_high_water = 9 * (pv_entry_max / 10);
1888 l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor,
1889 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1890 l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable),
1891 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1892 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1894 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max);
1899 pmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user)
1901 struct l2_dtable *l2;
1902 struct l2_bucket *l2b;
1903 pd_entry_t *pl1pd, l1pd;
1904 pt_entry_t *ptep, pte;
1910 vm_page_lock_queues();
1914 * If there is no l2_dtable for this address, then the process
1915 * has no business accessing it.
1917 * Note: This will catch userland processes trying to access
1920 l2 = pm->pm_l2[L2_IDX(l1idx)];
1925 * Likewise if there is no L2 descriptor table
1927 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
1928 if (l2b->l2b_kva == NULL)
1932 * Check the PTE itself.
1934 ptep = &l2b->l2b_kva[l2pte_index(va)];
1940 * Catch a userland access to the vector page mapped at 0x0
1942 if (user && (pte & L2_S_PROT_U) == 0)
1944 if (va == vector_page)
1949 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) {
1951 * This looks like a good candidate for "page modified"
1954 struct pv_entry *pv;
1957 /* Extract the physical address of the page */
1958 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) {
1961 /* Get the current flags for this page. */
1963 pv = pmap_find_pv(pg, pm, va);
1969 * Do the flags say this page is writable? If not then it
1970 * is a genuine write fault. If yes then the write fault is
1971 * our fault as we did not reflect the write access in the
1972 * PTE. Now we know a write has occurred we can correct this
1973 * and also set the modified bit
1975 if ((pv->pv_flags & PVF_WRITE) == 0) {
1979 pg->md.pvh_attrs |= PVF_REF | PVF_MOD;
1981 pv->pv_flags |= PVF_REF | PVF_MOD;
1984 * Re-enable write permissions for the page. No need to call
1985 * pmap_fix_cache(), since this is just a
1986 * modified-emulation fault, and the PVF_WRITE bit isn't
1987 * changing. We've already set the cacheable bits based on
1988 * the assumption that we can write to this page.
1990 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W;
1994 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) {
1996 * This looks like a good candidate for "page referenced"
1999 struct pv_entry *pv;
2002 /* Extract the physical address of the page */
2003 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL)
2005 /* Get the current flags for this page. */
2007 pv = pmap_find_pv(pg, pm, va);
2011 pg->md.pvh_attrs |= PVF_REF;
2012 pv->pv_flags |= PVF_REF;
2015 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO;
2021 * We know there is a valid mapping here, so simply
2022 * fix up the L1 if necessary.
2024 pl1pd = &pm->pm_l1->l1_kva[l1idx];
2025 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO;
2026 if (*pl1pd != l1pd) {
2034 * There are bugs in the rev K SA110. This is a check for one
2037 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 &&
2038 curcpu()->ci_arm_cpurev < 3) {
2039 /* Always current pmap */
2040 if (l2pte_valid(pte)) {
2041 extern int kernel_debug;
2042 if (kernel_debug & 1) {
2043 struct proc *p = curlwp->l_proc;
2044 printf("prefetch_abort: page is already "
2045 "mapped - pte=%p *pte=%08x\n", ptep, pte);
2046 printf("prefetch_abort: pc=%08lx proc=%p "
2047 "process=%s\n", va, p, p->p_comm);
2048 printf("prefetch_abort: far=%08x fs=%x\n",
2049 cpu_faultaddress(), cpu_faultstatus());
2052 if (kernel_debug & 2)
2058 #endif /* CPU_SA110 */
2062 * If 'rv == 0' at this point, it generally indicates that there is a
2063 * stale TLB entry for the faulting address. This happens when two or
2064 * more processes are sharing an L1. Since we don't flush the TLB on
2065 * a context switch between such processes, we can take domain faults
2066 * for mappings which exist at the same VA in both processes. EVEN IF
2067 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for
2070 * This is extremely likely to happen if pmap_enter() updated the L1
2071 * entry for a recently entered mapping. In this case, the TLB is
2072 * flushed for the new mapping, but there may still be TLB entries for
2073 * other mappings belonging to other processes in the 1MB range
2074 * covered by the L1 entry.
2076 * Since 'rv == 0', we know that the L1 already contains the correct
2077 * value, so the fault must be due to a stale TLB entry.
2079 * Since we always need to flush the TLB anyway in the case where we
2080 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with
2081 * stale TLB entries dynamically.
2083 * However, the above condition can ONLY happen if the current L1 is
2084 * being shared. If it happens when the L1 is unshared, it indicates
2085 * that other parts of the pmap are not doing their job WRT managing
2088 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) {
2089 extern int last_fault_code;
2090 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n",
2092 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n",
2093 l2, l2b, ptep, pl1pd);
2094 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n",
2095 pte, l1pd, last_fault_code);
2102 cpu_tlb_flushID_SE(va);
2108 vm_page_unlock_queues();
2116 struct l2_bucket *l2b;
2117 struct l1_ttable *l1;
2119 pt_entry_t *ptep, pte;
2120 vm_offset_t va, eva;
2123 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0);
2125 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK);
2127 for (loop = 0; loop < needed; loop++, l1++) {
2128 /* Allocate a L1 page table */
2129 va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0,
2130 0xffffffff, L1_TABLE_SIZE, 0);
2133 panic("Cannot allocate L1 KVM");
2135 eva = va + L1_TABLE_SIZE;
2136 pl1pt = (pd_entry_t *)va;
2139 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2140 ptep = &l2b->l2b_kva[l2pte_index(va)];
2142 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
2145 cpu_tlb_flushD_SE(va);
2149 pmap_init_l1(l1, pl1pt);
2154 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n",
2160 * This is used to stuff certain critical values into the PCB where they
2161 * can be accessed quickly from cpu_switch() et al.
2164 pmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb)
2166 struct l2_bucket *l2b;
2168 pcb->pcb_pagedir = pm->pm_l1->l1_physaddr;
2169 pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) |
2170 (DOMAIN_CLIENT << (pm->pm_domain * 2));
2172 if (vector_page < KERNBASE) {
2173 pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)];
2174 l2b = pmap_get_l2_bucket(pm, vector_page);
2175 pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO |
2176 L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL);
2178 pcb->pcb_pl1vec = NULL;
2182 pmap_activate(struct thread *td)
2187 pm = vmspace_pmap(td->td_proc->p_vmspace);
2191 pmap_set_pcb_pagedir(pm, pcb);
2193 if (td == curthread) {
2194 u_int cur_dacr, cur_ttb;
2196 __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb));
2197 __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr));
2199 cur_ttb &= ~(L1_TABLE_SIZE - 1);
2201 if (cur_ttb == (u_int)pcb->pcb_pagedir &&
2202 cur_dacr == pcb->pcb_dacr) {
2204 * No need to switch address spaces.
2212 * We MUST, I repeat, MUST fix up the L1 entry corresponding
2213 * to 'vector_page' in the incoming L1 table before switching
2214 * to it otherwise subsequent interrupts/exceptions (including
2215 * domain faults!) will jump into hyperspace.
2217 if (pcb->pcb_pl1vec) {
2219 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2221 * Don't need to PTE_SYNC() at this point since
2222 * cpu_setttb() is about to flush both the cache
2227 cpu_domains(pcb->pcb_dacr);
2228 cpu_setttb(pcb->pcb_pagedir);
2234 pmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va)
2236 pd_entry_t *pdep, pde;
2237 pt_entry_t *ptep, pte;
2242 * Make sure the descriptor itself has the correct cache mode
2244 pdep = &kl1[L1_IDX(va)];
2247 if (l1pte_section_p(pde)) {
2248 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) {
2249 *pdep = (pde & ~L1_S_CACHE_MASK) |
2250 pte_l1_s_cache_mode_pt;
2252 cpu_dcache_wbinv_range((vm_offset_t)pdep,
2254 cpu_l2cache_wbinv_range((vm_offset_t)pdep,
2259 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2260 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2262 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep);
2264 ptep = &ptep[l2pte_index(va)];
2266 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
2267 *ptep = (pte & ~L2_S_CACHE_MASK) |
2268 pte_l2_s_cache_mode_pt;
2270 cpu_dcache_wbinv_range((vm_offset_t)ptep,
2272 cpu_l2cache_wbinv_range((vm_offset_t)ptep,
2282 pmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap,
2285 vm_offset_t va = *availp;
2286 struct l2_bucket *l2b;
2289 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2291 panic("pmap_alloc_specials: no l2b for 0x%x", va);
2293 *ptep = &l2b->l2b_kva[l2pte_index(va)];
2297 *availp = va + (PAGE_SIZE * pages);
2301 * Bootstrap the system enough to run with virtual memory.
2303 * On the arm this is called after mapping has already been enabled
2304 * and just syncs the pmap module with what has already been done.
2305 * [We can't call it easily with mapping off since the kernel is not
2306 * mapped with PA == VA, hence we would have to relocate every address
2307 * from the linked base (virtual) address "KERNBASE" to the actual
2308 * (physical) address starting relative to 0]
2310 #define PMAP_STATIC_L2_SIZE 16
2311 #ifdef ARM_USE_SMALL_ALLOC
2312 extern struct mtx smallalloc_mtx;
2316 pmap_bootstrap(vm_offset_t firstaddr, vm_offset_t lastaddr, struct pv_addr *l1pt)
2318 static struct l1_ttable static_l1;
2319 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE];
2320 struct l1_ttable *l1 = &static_l1;
2321 struct l2_dtable *l2;
2322 struct l2_bucket *l2b;
2324 pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va;
2329 int l1idx, l2idx, l2next = 0;
2331 PDEBUG(1, printf("firstaddr = %08x, loadaddr = %08x\n",
2332 firstaddr, loadaddr));
2334 virtual_avail = firstaddr;
2335 kernel_pmap = &kernel_pmap_store;
2336 kernel_pmap->pm_l1 = l1;
2337 kernel_l1pa = l1pt->pv_pa;
2340 * Scan the L1 translation table created by initarm() and create
2341 * the required metadata for all valid mappings found in it.
2343 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) {
2344 pde = kernel_l1pt[l1idx];
2347 * We're only interested in Coarse mappings.
2348 * pmap_extract() can deal with section mappings without
2349 * recourse to checking L2 metadata.
2351 if ((pde & L1_TYPE_MASK) != L1_TYPE_C)
2355 * Lookup the KVA of this L2 descriptor table
2357 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2358 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2361 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx",
2362 (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa);
2366 * Fetch the associated L2 metadata structure.
2367 * Allocate a new one if necessary.
2369 if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) {
2370 if (l2next == PMAP_STATIC_L2_SIZE)
2371 panic("pmap_bootstrap: out of static L2s");
2372 kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 =
2373 &static_l2[l2next++];
2377 * One more L1 slot tracked...
2382 * Fill in the details of the L2 descriptor in the
2383 * appropriate bucket.
2385 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2386 l2b->l2b_kva = ptep;
2388 l2b->l2b_l1idx = l1idx;
2391 * Establish an initial occupancy count for this descriptor
2394 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
2396 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) {
2397 l2b->l2b_occupancy++;
2402 * Make sure the descriptor itself has the correct cache mode.
2403 * If not, fix it, but whine about the problem. Port-meisters
2404 * should consider this a clue to fix up their initarm()
2407 if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) {
2408 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2409 "L2 pte @ %p\n", ptep);
2415 * Ensure the primary (kernel) L1 has the correct cache mode for
2416 * a page table. Bitch if it is not correctly set.
2418 for (va = (vm_offset_t)kernel_l1pt;
2419 va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) {
2420 if (pmap_set_pt_cache_mode(kernel_l1pt, va))
2421 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2422 "primary L1 @ 0x%x\n", va);
2425 cpu_dcache_wbinv_all();
2426 cpu_l2cache_wbinv_all();
2430 PMAP_LOCK_INIT(kernel_pmap);
2431 kernel_pmap->pm_active = -1;
2432 kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL;
2433 TAILQ_INIT(&kernel_pmap->pm_pvlist);
2436 * Reserve some special page table entries/VA space for temporary
2439 #define SYSMAP(c, p, v, n) \
2440 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
2442 pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte);
2443 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte);
2444 pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte);
2445 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte);
2446 size = ((lastaddr - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE;
2447 pmap_alloc_specials(&virtual_avail,
2448 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE,
2449 &pmap_kernel_l2ptp_kva, NULL);
2451 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE;
2452 pmap_alloc_specials(&virtual_avail,
2453 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE,
2454 &pmap_kernel_l2dtable_kva, NULL);
2456 pmap_alloc_specials(&virtual_avail,
2457 1, (vm_offset_t*)&_tmppt, NULL);
2458 SLIST_INIT(&l1_list);
2459 TAILQ_INIT(&l1_lru_list);
2460 mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF);
2461 pmap_init_l1(l1, kernel_l1pt);
2462 cpu_dcache_wbinv_all();
2463 cpu_l2cache_wbinv_all();
2465 virtual_avail = round_page(virtual_avail);
2466 virtual_end = lastaddr;
2467 kernel_vm_end = pmap_curmaxkvaddr;
2468 arm_nocache_startaddr = lastaddr;
2469 mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF);
2471 #ifdef ARM_USE_SMALL_ALLOC
2472 mtx_init(&smallalloc_mtx, "Small alloc page list", NULL, MTX_DEF);
2473 arm_init_smallalloc();
2475 pmap_set_pcb_pagedir(kernel_pmap, thread0.td_pcb);
2478 /***************************************************
2479 * Pmap allocation/deallocation routines.
2480 ***************************************************/
2483 * Release any resources held by the given physical map.
2484 * Called when a pmap initialized by pmap_pinit is being released.
2485 * Should only be called if the map contains no valid mappings.
2488 pmap_release(pmap_t pmap)
2492 pmap_idcache_wbinv_all(pmap);
2493 cpu_l2cache_wbinv_all();
2494 pmap_tlb_flushID(pmap);
2496 if (vector_page < KERNBASE) {
2497 struct pcb *curpcb = PCPU_GET(curpcb);
2498 pcb = thread0.td_pcb;
2499 if (pmap_is_current(pmap)) {
2501 * Frob the L1 entry corresponding to the vector
2502 * page so that it contains the kernel pmap's domain
2503 * number. This will ensure pmap_remove() does not
2504 * pull the current vector page out from under us.
2507 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2508 cpu_domains(pcb->pcb_dacr);
2509 cpu_setttb(pcb->pcb_pagedir);
2512 pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE);
2514 * Make sure cpu_switch(), et al, DTRT. This is safe to do
2515 * since this process has no remaining mappings of its own.
2517 curpcb->pcb_pl1vec = pcb->pcb_pl1vec;
2518 curpcb->pcb_l1vec = pcb->pcb_l1vec;
2519 curpcb->pcb_dacr = pcb->pcb_dacr;
2520 curpcb->pcb_pagedir = pcb->pcb_pagedir;
2524 PMAP_LOCK_DESTROY(pmap);
2526 dprintf("pmap_release()\n");
2532 * Helper function for pmap_grow_l2_bucket()
2535 pmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap)
2537 struct l2_bucket *l2b;
2542 pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
2545 pa = VM_PAGE_TO_PHYS(pg);
2550 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2552 ptep = &l2b->l2b_kva[l2pte_index(va)];
2553 *ptep = L2_S_PROTO | pa | cache_mode |
2554 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE);
2560 * This is the same as pmap_alloc_l2_bucket(), except that it is only
2561 * used by pmap_growkernel().
2563 static __inline struct l2_bucket *
2564 pmap_grow_l2_bucket(pmap_t pm, vm_offset_t va)
2566 struct l2_dtable *l2;
2567 struct l2_bucket *l2b;
2568 struct l1_ttable *l1;
2575 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
2577 * No mapping at this address, as there is
2578 * no entry in the L1 table.
2579 * Need to allocate a new l2_dtable.
2581 nva = pmap_kernel_l2dtable_kva;
2582 if ((nva & PAGE_MASK) == 0) {
2584 * Need to allocate a backing page
2586 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2590 l2 = (struct l2_dtable *)nva;
2591 nva += sizeof(struct l2_dtable);
2593 if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva &
2596 * The new l2_dtable straddles a page boundary.
2597 * Map in another page to cover it.
2599 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2603 pmap_kernel_l2dtable_kva = nva;
2606 * Link it into the parent pmap
2608 pm->pm_l2[L2_IDX(l1idx)] = l2;
2609 memset(l2, 0, sizeof(*l2));
2612 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2615 * Fetch pointer to the L2 page table associated with the address.
2617 if (l2b->l2b_kva == NULL) {
2621 * No L2 page table has been allocated. Chances are, this
2622 * is because we just allocated the l2_dtable, above.
2624 nva = pmap_kernel_l2ptp_kva;
2625 ptep = (pt_entry_t *)nva;
2626 if ((nva & PAGE_MASK) == 0) {
2628 * Need to allocate a backing page
2630 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt,
2631 &pmap_kernel_l2ptp_phys))
2633 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t));
2635 memset(ptep, 0, L2_TABLE_SIZE_REAL);
2637 l2b->l2b_kva = ptep;
2638 l2b->l2b_l1idx = l1idx;
2639 l2b->l2b_phys = pmap_kernel_l2ptp_phys;
2641 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL;
2642 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL;
2645 /* Distribute new L1 entry to all other L1s */
2646 SLIST_FOREACH(l1, &l1_list, l1_link) {
2647 pl1pd = &l1->l1_kva[L1_IDX(va)];
2648 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) |
2658 * grow the number of kernel page table entries, if needed
2661 pmap_growkernel(vm_offset_t addr)
2663 pmap_t kpm = pmap_kernel();
2665 if (addr <= pmap_curmaxkvaddr)
2666 return; /* we are OK */
2669 * whoops! we need to add kernel PTPs
2672 /* Map 1MB at a time */
2673 for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE)
2674 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr);
2677 * flush out the cache, expensive but growkernel will happen so
2680 cpu_dcache_wbinv_all();
2681 cpu_l2cache_wbinv_all();
2684 kernel_vm_end = pmap_curmaxkvaddr;
2689 * Remove all pages from specified address space
2690 * this aids process exit speeds. Also, this code
2691 * is special cased for current process only, but
2692 * can have the more generic (and slightly slower)
2693 * mode enabled. This is much faster than pmap_remove
2694 * in the case of running down an entire address space.
2697 pmap_remove_pages(pmap_t pmap)
2699 struct pv_entry *pv, *npv;
2700 struct l2_bucket *l2b = NULL;
2704 vm_page_lock_queues();
2706 cpu_idcache_wbinv_all();
2707 cpu_l2cache_wbinv_all();
2708 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) {
2709 if (pv->pv_flags & PVF_WIRED) {
2710 /* The page is wired, cannot remove it now. */
2711 npv = TAILQ_NEXT(pv, pv_plist);
2714 pmap->pm_stats.resident_count--;
2715 l2b = pmap_get_l2_bucket(pmap, pv->pv_va);
2716 KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages"));
2717 pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
2718 m = PHYS_TO_VM_PAGE(*pt & L2_ADDR_MASK);
2719 #ifdef ARM_USE_SMALL_ALLOC
2720 KASSERT((vm_offset_t)m >= alloc_firstaddr, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt));
2722 KASSERT((vm_offset_t)m >= KERNBASE, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt));
2726 npv = TAILQ_NEXT(pv, pv_plist);
2727 pmap_nuke_pv(m, pmap, pv);
2728 if (TAILQ_EMPTY(&m->md.pv_list))
2729 vm_page_flag_clear(m, PG_WRITEABLE);
2730 pmap_free_pv_entry(pv);
2731 pmap_free_l2_bucket(pmap, l2b, 1);
2733 vm_page_unlock_queues();
2740 /***************************************************
2741 * Low level mapping routines.....
2742 ***************************************************/
2744 #ifdef ARM_HAVE_SUPERSECTIONS
2745 /* Map a super section into the KVA. */
2748 pmap_kenter_supersection(vm_offset_t va, uint64_t pa, int flags)
2750 pd_entry_t pd = L1_S_PROTO | L1_S_SUPERSEC | (pa & L1_SUP_FRAME) |
2751 (((pa >> 32) & 0xf) << 20) | L1_S_PROT(PTE_KERNEL,
2752 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
2753 struct l1_ttable *l1;
2754 vm_offset_t va0, va_end;
2756 KASSERT(((va | pa) & L1_SUP_OFFSET) == 0,
2757 ("Not a valid super section mapping"));
2758 if (flags & SECTION_CACHE)
2759 pd |= pte_l1_s_cache_mode;
2760 else if (flags & SECTION_PT)
2761 pd |= pte_l1_s_cache_mode_pt;
2762 va0 = va & L1_SUP_FRAME;
2763 va_end = va + L1_SUP_SIZE;
2764 SLIST_FOREACH(l1, &l1_list, l1_link) {
2766 for (; va < va_end; va += L1_S_SIZE) {
2767 l1->l1_kva[L1_IDX(va)] = pd;
2768 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2774 /* Map a section into the KVA. */
2777 pmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags)
2779 pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL,
2780 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
2781 struct l1_ttable *l1;
2783 KASSERT(((va | pa) & L1_S_OFFSET) == 0,
2784 ("Not a valid section mapping"));
2785 if (flags & SECTION_CACHE)
2786 pd |= pte_l1_s_cache_mode;
2787 else if (flags & SECTION_PT)
2788 pd |= pte_l1_s_cache_mode_pt;
2789 SLIST_FOREACH(l1, &l1_list, l1_link) {
2790 l1->l1_kva[L1_IDX(va)] = pd;
2791 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2796 * add a wired page to the kva
2797 * note that in order for the mapping to take effect -- you
2798 * should do a invltlb after doing the pmap_kenter...
2800 static PMAP_INLINE void
2801 pmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags)
2803 struct l2_bucket *l2b;
2806 PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n",
2807 (uint32_t) va, (uint32_t) pa));
2810 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2812 l2b = pmap_grow_l2_bucket(pmap_kernel(), va);
2813 KASSERT(l2b != NULL, ("No L2 Bucket"));
2814 pte = &l2b->l2b_kva[l2pte_index(va)];
2816 PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n",
2817 (uint32_t) pte, opte, *pte));
2818 if (l2pte_valid(opte)) {
2819 cpu_dcache_wbinv_range(va, PAGE_SIZE);
2820 cpu_l2cache_wbinv_range(va, PAGE_SIZE);
2821 cpu_tlb_flushD_SE(va);
2825 l2b->l2b_occupancy++;
2827 *pte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL,
2828 VM_PROT_READ | VM_PROT_WRITE);
2829 if (flags & KENTER_CACHE)
2830 *pte |= pte_l2_s_cache_mode;
2831 if (flags & KENTER_USER)
2832 *pte |= L2_S_PROT_U;
2837 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2839 pmap_kenter_internal(va, pa, KENTER_CACHE);
2843 pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa)
2846 pmap_kenter_internal(va, pa, 0);
2850 pmap_kenter_user(vm_offset_t va, vm_paddr_t pa)
2853 pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER);
2855 * Call pmap_fault_fixup now, to make sure we'll have no exception
2856 * at the first use of the new address, or bad things will happen,
2857 * as we use one of these addresses in the exception handlers.
2859 pmap_fault_fixup(pmap_kernel(), va, VM_PROT_READ|VM_PROT_WRITE, 1);
2863 * remove a page rom the kernel pagetables
2866 pmap_kremove(vm_offset_t va)
2868 struct l2_bucket *l2b;
2869 pt_entry_t *pte, opte;
2871 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2874 KASSERT(l2b != NULL, ("No L2 Bucket"));
2875 pte = &l2b->l2b_kva[l2pte_index(va)];
2877 if (l2pte_valid(opte)) {
2878 cpu_dcache_wbinv_range(va, PAGE_SIZE);
2879 cpu_l2cache_wbinv_range(va, PAGE_SIZE);
2880 cpu_tlb_flushD_SE(va);
2888 * Used to map a range of physical addresses into kernel
2889 * virtual address space.
2891 * The value passed in '*virt' is a suggested virtual address for
2892 * the mapping. Architectures which can support a direct-mapped
2893 * physical to virtual region can return the appropriate address
2894 * within that region, leaving '*virt' unchanged. Other
2895 * architectures should map the pages starting at '*virt' and
2896 * update '*virt' with the first usable address after the mapped
2900 pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot)
2902 #ifdef ARM_USE_SMALL_ALLOC
2903 return (arm_ptovirt(start));
2905 vm_offset_t sva = *virt;
2906 vm_offset_t va = sva;
2908 PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, "
2909 "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end,
2912 while (start < end) {
2913 pmap_kenter(va, start);
2923 pmap_wb_page(vm_page_t m)
2925 struct pv_entry *pv;
2927 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
2928 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, FALSE,
2929 (pv->pv_flags & PVF_WRITE) == 0);
2933 pmap_inv_page(vm_page_t m)
2935 struct pv_entry *pv;
2937 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
2938 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, TRUE, TRUE);
2941 * Add a list of wired pages to the kva
2942 * this routine is only used for temporary
2943 * kernel mappings that do not need to have
2944 * page modification or references recorded.
2945 * Note that old mappings are simply written
2946 * over. The page *must* be wired.
2949 pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
2953 for (i = 0; i < count; i++) {
2955 pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]),
2963 * this routine jerks page mappings from the
2964 * kernel -- it is meant only for temporary mappings.
2967 pmap_qremove(vm_offset_t va, int count)
2972 for (i = 0; i < count; i++) {
2975 pmap_inv_page(PHYS_TO_VM_PAGE(pa));
2984 * pmap_object_init_pt preloads the ptes for a given object
2985 * into the specified pmap. This eliminates the blast of soft
2986 * faults on process startup and immediately after an mmap.
2989 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
2990 vm_pindex_t pindex, vm_size_t size)
2993 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
2994 KASSERT(object->type == OBJT_DEVICE,
2995 ("pmap_object_init_pt: non-device object"));
3000 * pmap_is_prefaultable:
3002 * Return whether or not the specified virtual address is elgible
3006 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3011 if (!pmap_get_pde_pte(pmap, addr, &pde, &pte))
3013 KASSERT(pte != NULL, ("Valid mapping but no pte ?"));
3020 * Fetch pointers to the PDE/PTE for the given pmap/VA pair.
3021 * Returns TRUE if the mapping exists, else FALSE.
3023 * NOTE: This function is only used by a couple of arm-specific modules.
3024 * It is not safe to take any pmap locks here, since we could be right
3025 * in the middle of debugging the pmap anyway...
3027 * It is possible for this routine to return FALSE even though a valid
3028 * mapping does exist. This is because we don't lock, so the metadata
3029 * state may be inconsistent.
3031 * NOTE: We can return a NULL *ptp in the case where the L1 pde is
3032 * a "section" mapping.
3035 pmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp)
3037 struct l2_dtable *l2;
3038 pd_entry_t *pl1pd, l1pd;
3042 if (pm->pm_l1 == NULL)
3046 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx];
3049 if (l1pte_section_p(l1pd)) {
3054 if (pm->pm_l2 == NULL)
3057 l2 = pm->pm_l2[L2_IDX(l1idx)];
3060 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3064 *ptp = &ptep[l2pte_index(va)];
3069 * Routine: pmap_remove_all
3071 * Removes this physical page from
3072 * all physical maps in which it resides.
3073 * Reflects back modify bits to the pager.
3076 * Original versions of this routine were very
3077 * inefficient because they iteratively called
3078 * pmap_remove (slow...)
3081 pmap_remove_all(vm_page_t m)
3084 pt_entry_t *ptep, pte;
3085 struct l2_bucket *l2b;
3086 boolean_t flush = FALSE;
3090 #if defined(PMAP_DEBUG)
3092 * XXX This makes pmap_remove_all() illegal for non-managed pages!
3094 if (m->flags & PG_FICTITIOUS) {
3095 panic("pmap_remove_all: illegal for unmanaged page, va: 0x%x", VM_PAGE_TO_PHYS(m));
3099 if (TAILQ_EMPTY(&m->md.pv_list))
3101 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3102 pmap_remove_write(m);
3103 curpm = vmspace_pmap(curproc->p_vmspace);
3104 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3105 if (flush == FALSE && (pv->pv_pmap == curpm ||
3106 pv->pv_pmap == pmap_kernel()))
3108 PMAP_LOCK(pv->pv_pmap);
3109 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
3110 KASSERT(l2b != NULL, ("No l2 bucket"));
3111 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
3114 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
3115 pmap_free_l2_bucket(pv->pv_pmap, l2b, 1);
3116 if (pv->pv_flags & PVF_WIRED)
3117 pv->pv_pmap->pm_stats.wired_count--;
3118 pv->pv_pmap->pm_stats.resident_count--;
3119 flags |= pv->pv_flags;
3120 pmap_nuke_pv(m, pv->pv_pmap, pv);
3121 PMAP_UNLOCK(pv->pv_pmap);
3122 pmap_free_pv_entry(pv);
3126 if (PV_BEEN_EXECD(flags))
3127 pmap_tlb_flushID(curpm);
3129 pmap_tlb_flushD(curpm);
3131 vm_page_flag_clear(m, PG_WRITEABLE);
3136 * Set the physical protection on the
3137 * specified range of this map as requested.
3140 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3142 struct l2_bucket *l2b;
3143 pt_entry_t *ptep, pte;
3144 vm_offset_t next_bucket;
3148 CTR4(KTR_PMAP, "pmap_protect: pmap %p sva 0x%08x eva 0x%08x prot %x",
3149 pm, sva, eva, prot);
3151 if ((prot & VM_PROT_READ) == 0) {
3152 pmap_remove(pm, sva, eva);
3156 if (prot & VM_PROT_WRITE) {
3158 * If this is a read->write transition, just ignore it and let
3159 * vm_fault() take care of it later.
3164 vm_page_lock_queues();
3168 * OK, at this point, we know we're doing write-protect operation.
3169 * If the pmap is active, write-back the range.
3171 pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE);
3173 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1;
3177 next_bucket = L2_NEXT_BUCKET(sva);
3178 if (next_bucket > eva)
3181 l2b = pmap_get_l2_bucket(pm, sva);
3187 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3189 while (sva < next_bucket) {
3190 if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) {
3194 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
3195 pte &= ~L2_S_PROT_W;
3200 f = pmap_modify_pv(pg, pm, sva,
3204 f = PVF_REF | PVF_EXEC;
3210 if (PV_BEEN_EXECD(f))
3211 pmap_tlb_flushID_SE(pm, sva);
3213 if (PV_BEEN_REFD(f))
3214 pmap_tlb_flushD_SE(pm, sva);
3224 if (PV_BEEN_EXECD(flags))
3225 pmap_tlb_flushID(pm);
3227 if (PV_BEEN_REFD(flags))
3228 pmap_tlb_flushD(pm);
3230 vm_page_unlock_queues();
3237 * Insert the given physical page (p) at
3238 * the specified virtual address (v) in the
3239 * target physical map with the protection requested.
3241 * If specified, the page will be wired down, meaning
3242 * that the related pte can not be reclaimed.
3244 * NB: This is the only routine which MAY NOT lazy-evaluate
3245 * or lose information. That is, this routine must actually
3246 * insert this page into the given map NOW.
3250 pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
3251 vm_prot_t prot, boolean_t wired)
3254 vm_page_lock_queues();
3256 pmap_enter_locked(pmap, va, m, prot, wired, M_WAITOK);
3257 vm_page_unlock_queues();
3262 * The page queues and pmap must be locked.
3265 pmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3266 boolean_t wired, int flags)
3268 struct l2_bucket *l2b = NULL;
3269 struct vm_page *opg;
3270 struct pv_entry *pve = NULL;
3271 pt_entry_t *ptep, npte, opte;
3276 PMAP_ASSERT_LOCKED(pmap);
3277 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3278 if (va == vector_page) {
3279 pa = systempage.pv_pa;
3282 pa = VM_PAGE_TO_PHYS(m);
3284 if (prot & VM_PROT_WRITE)
3285 nflags |= PVF_WRITE;
3286 if (prot & VM_PROT_EXECUTE)
3289 nflags |= PVF_WIRED;
3290 PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, "
3291 "wired = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, wired));
3293 if (pmap == pmap_kernel()) {
3294 l2b = pmap_get_l2_bucket(pmap, va);
3296 l2b = pmap_grow_l2_bucket(pmap, va);
3299 l2b = pmap_alloc_l2_bucket(pmap, va);
3301 if (flags & M_WAITOK) {
3303 vm_page_unlock_queues();
3305 vm_page_lock_queues();
3313 ptep = &l2b->l2b_kva[l2pte_index(va)];
3320 * There is already a mapping at this address.
3321 * If the physical address is different, lookup the
3324 if (l2pte_pa(opte) != pa)
3325 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte));
3331 if ((prot & (VM_PROT_ALL)) ||
3332 (!m || m->md.pvh_attrs & PVF_REF)) {
3334 * - The access type indicates that we don't need
3335 * to do referenced emulation.
3337 * - The physical page has already been referenced
3338 * so no need to re-do referenced emulation here.
3344 if (m && ((prot & VM_PROT_WRITE) != 0 ||
3345 (m->md.pvh_attrs & PVF_MOD))) {
3347 * This is a writable mapping, and the
3348 * page's mod state indicates it has
3349 * already been modified. Make it
3350 * writable from the outset.
3353 if (!(m->md.pvh_attrs & PVF_MOD))
3357 vm_page_flag_set(m, PG_REFERENCED);
3360 * Need to do page referenced emulation.
3362 npte |= L2_TYPE_INV;
3365 if (prot & VM_PROT_WRITE) {
3366 npte |= L2_S_PROT_W;
3368 vm_page_flag_set(m, PG_WRITEABLE);
3370 npte |= pte_l2_s_cache_mode;
3371 if (m && m == opg) {
3373 * We're changing the attrs of an existing mapping.
3375 oflags = pmap_modify_pv(m, pmap, va,
3376 PVF_WRITE | PVF_EXEC | PVF_WIRED |
3377 PVF_MOD | PVF_REF, nflags);
3380 * We may need to flush the cache if we're
3383 if (pmap_is_current(pmap) &&
3384 (oflags & PVF_NC) == 0 &&
3385 (opte & L2_S_PROT_W) != 0 &&
3386 (prot & VM_PROT_WRITE) == 0) {
3387 cpu_dcache_wb_range(va, PAGE_SIZE);
3388 pmap_l2cache_wb_range(pmap, va, PAGE_SIZE);
3392 * New mapping, or changing the backing page
3393 * of an existing mapping.
3397 * Replacing an existing mapping with a new one.
3398 * It is part of our managed memory so we
3399 * must remove it from the PV list
3401 pve = pmap_remove_pv(opg, pmap, va);
3402 if (m && (m->flags & (PG_UNMANAGED | PG_FICTITIOUS)) &&
3404 pmap_free_pv_entry(pve);
3406 !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS)))
3407 pve = pmap_get_pv_entry();
3408 KASSERT(pve != NULL || m->flags & (PG_UNMANAGED |
3409 PG_FICTITIOUS), ("No pv"));
3410 oflags = pve->pv_flags;
3413 * If the old mapping was valid (ref/mod
3414 * emulation creates 'invalid' mappings
3415 * initially) then make sure to frob
3418 if ((oflags & PVF_NC) == 0 &&
3419 l2pte_valid(opte)) {
3420 if (PV_BEEN_EXECD(oflags)) {
3421 pmap_idcache_wbinv_range(pmap, va,
3424 if (PV_BEEN_REFD(oflags)) {
3425 pmap_dcache_wb_range(pmap, va,
3427 (oflags & PVF_WRITE) == 0);
3430 } else if (m && !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS)))
3431 if ((pve = pmap_get_pv_entry()) == NULL) {
3432 panic("pmap_enter: no pv entries");
3434 if (m && !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS))) {
3435 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3436 ("pmap_enter: managed mapping within the clean submap"));
3437 pmap_enter_pv(m, pve, pmap, va, nflags);
3441 * Make sure userland mappings get the right permissions
3443 if (pmap != pmap_kernel() && va != vector_page) {
3444 npte |= L2_S_PROT_U;
3448 * Keep the stats up to date
3451 l2b->l2b_occupancy++;
3452 pmap->pm_stats.resident_count++;
3457 * If this is just a wiring change, the two PTEs will be
3458 * identical, so there's no need to update the page table.
3461 boolean_t is_cached = pmap_is_current(pmap);
3466 * We only need to frob the cache/tlb if this pmap
3470 if (L1_IDX(va) != L1_IDX(vector_page) &&
3471 l2pte_valid(npte)) {
3473 * This mapping is likely to be accessed as
3474 * soon as we return to userland. Fix up the
3475 * L1 entry to avoid taking another
3476 * page/domain fault.
3478 pd_entry_t *pl1pd, l1pd;
3480 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
3481 l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) |
3483 if (*pl1pd != l1pd) {
3490 if (PV_BEEN_EXECD(oflags))
3491 pmap_tlb_flushID_SE(pmap, va);
3492 else if (PV_BEEN_REFD(oflags))
3493 pmap_tlb_flushD_SE(pmap, va);
3497 pmap_fix_cache(m, pmap, va);
3502 * Maps a sequence of resident pages belonging to the same object.
3503 * The sequence begins with the given page m_start. This page is
3504 * mapped at the given virtual address start. Each subsequent page is
3505 * mapped at a virtual address that is offset from start by the same
3506 * amount as the page is offset from m_start within the object. The
3507 * last page in the sequence is the page with the largest offset from
3508 * m_start that can be mapped at a virtual address less than the given
3509 * virtual address end. Not every virtual page between start and end
3510 * is mapped; only those for which a resident page exists with the
3511 * corresponding offset from m_start are mapped.
3514 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3515 vm_page_t m_start, vm_prot_t prot)
3518 vm_pindex_t diff, psize;
3520 psize = atop(end - start);
3523 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3524 pmap_enter_locked(pmap, start + ptoa(diff), m, prot &
3525 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE, M_NOWAIT);
3526 m = TAILQ_NEXT(m, listq);
3532 * this code makes some *MAJOR* assumptions:
3533 * 1. Current pmap & pmap exists.
3536 * 4. No page table pages.
3537 * but is *MUCH* faster than pmap_enter...
3541 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3545 pmap_enter_locked(pmap, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
3551 * Routine: pmap_change_wiring
3552 * Function: Change the wiring attribute for a map/virtual-address
3554 * In/out conditions:
3555 * The mapping must already exist in the pmap.
3558 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
3560 struct l2_bucket *l2b;
3561 pt_entry_t *ptep, pte;
3564 vm_page_lock_queues();
3566 l2b = pmap_get_l2_bucket(pmap, va);
3567 KASSERT(l2b, ("No l2b bucket in pmap_change_wiring"));
3568 ptep = &l2b->l2b_kva[l2pte_index(va)];
3570 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
3572 pmap_modify_pv(pg, pmap, va, PVF_WIRED, wired);
3573 vm_page_unlock_queues();
3579 * Copy the range specified by src_addr/len
3580 * from the source map to the range dst_addr/len
3581 * in the destination map.
3583 * This routine is only advisory and need not do anything.
3586 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
3587 vm_size_t len, vm_offset_t src_addr)
3593 * Routine: pmap_extract
3595 * Extract the physical page address associated
3596 * with the given map/virtual_address pair.
3599 pmap_extract(pmap_t pm, vm_offset_t va)
3601 struct l2_dtable *l2;
3603 pt_entry_t *ptep, pte;
3609 l1pd = pm->pm_l1->l1_kva[l1idx];
3610 if (l1pte_section_p(l1pd)) {
3612 * These should only happen for pmap_kernel()
3614 KASSERT(pm == pmap_kernel(), ("huh"));
3615 /* XXX: what to do about the bits > 32 ? */
3616 if (l1pd & L1_S_SUPERSEC)
3617 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3619 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3622 * Note that we can't rely on the validity of the L1
3623 * descriptor as an indication that a mapping exists.
3624 * We have to look it up in the L2 dtable.
3626 l2 = pm->pm_l2[L2_IDX(l1idx)];
3629 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3634 ptep = &ptep[l2pte_index(va)];
3642 switch (pte & L2_TYPE_MASK) {
3644 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3648 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3658 * Atomically extract and hold the physical page with the given
3659 * pmap and virtual address pair if that mapping permits the given
3664 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3666 struct l2_dtable *l2;
3668 pt_entry_t *ptep, pte;
3674 vm_page_lock_queues();
3676 l1pd = pmap->pm_l1->l1_kva[l1idx];
3677 if (l1pte_section_p(l1pd)) {
3679 * These should only happen for pmap_kernel()
3681 KASSERT(pmap == pmap_kernel(), ("huh"));
3682 /* XXX: what to do about the bits > 32 ? */
3683 if (l1pd & L1_S_SUPERSEC)
3684 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3686 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3687 if (l1pd & L1_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3688 m = PHYS_TO_VM_PAGE(pa);
3694 * Note that we can't rely on the validity of the L1
3695 * descriptor as an indication that a mapping exists.
3696 * We have to look it up in the L2 dtable.
3698 l2 = pmap->pm_l2[L2_IDX(l1idx)];
3701 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3703 vm_page_unlock_queues();
3707 ptep = &ptep[l2pte_index(va)];
3712 vm_page_unlock_queues();
3715 if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3716 switch (pte & L2_TYPE_MASK) {
3718 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3722 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3725 m = PHYS_TO_VM_PAGE(pa);
3731 vm_page_unlock_queues();
3736 * Initialize a preallocated and zeroed pmap structure,
3737 * such as one in a vmspace structure.
3741 pmap_pinit(pmap_t pmap)
3743 PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap));
3745 PMAP_LOCK_INIT(pmap);
3746 pmap_alloc_l1(pmap);
3747 bzero(pmap->pm_l2, sizeof(pmap->pm_l2));
3749 pmap->pm_active = 0;
3751 TAILQ_INIT(&pmap->pm_pvlist);
3752 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3753 pmap->pm_stats.resident_count = 1;
3754 if (vector_page < KERNBASE) {
3755 pmap_enter(pmap, vector_page,
3756 VM_PROT_READ, PHYS_TO_VM_PAGE(systempage.pv_pa),
3763 /***************************************************
3764 * page management routines.
3765 ***************************************************/
3769 pmap_free_pv_entry(pv_entry_t pv)
3772 uma_zfree(pvzone, pv);
3777 * get a new pv_entry, allocating a block from the system
3779 * the memory allocation is performed bypassing the malloc code
3780 * because of the possibility of allocations at interrupt time.
3783 pmap_get_pv_entry(void)
3785 pv_entry_t ret_value;
3788 if (pv_entry_count > pv_entry_high_water)
3789 pagedaemon_wakeup();
3790 ret_value = uma_zalloc(pvzone, M_NOWAIT);
3795 * Remove the given range of addresses from the specified map.
3797 * It is assumed that the start and end are properly
3798 * rounded to the page size.
3800 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3
3802 pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva)
3804 struct l2_bucket *l2b;
3805 vm_offset_t next_bucket;
3808 u_int mappings, is_exec, is_refd;
3813 * we lock in the pmap => pv_head direction
3816 vm_page_lock_queues();
3821 * Do one L2 bucket's worth at a time.
3823 next_bucket = L2_NEXT_BUCKET(sva);
3824 if (next_bucket > eva)
3827 l2b = pmap_get_l2_bucket(pm, sva);
3833 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3836 while (sva < next_bucket) {
3845 * Nothing here, move along
3852 pm->pm_stats.resident_count--;
3858 * Update flags. In a number of circumstances,
3859 * we could cluster a lot of these and do a
3860 * number of sequential pages in one go.
3862 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) {
3863 struct pv_entry *pve;
3865 pve = pmap_remove_pv(pg, pm, sva);
3867 is_exec = PV_BEEN_EXECD(pve->pv_flags);
3868 is_refd = PV_BEEN_REFD(pve->pv_flags);
3869 pmap_free_pv_entry(pve);
3873 if (l2pte_valid(pte) && pmap_is_current(pm)) {
3874 if (total < PMAP_REMOVE_CLEAN_LIST_SIZE) {
3877 cpu_idcache_wbinv_range(sva,
3879 cpu_l2cache_wbinv_range(sva,
3881 cpu_tlb_flushID_SE(sva);
3882 } else if (is_refd) {
3883 cpu_dcache_wbinv_range(sva,
3885 cpu_l2cache_wbinv_range(sva,
3887 cpu_tlb_flushD_SE(sva);
3889 } else if (total == PMAP_REMOVE_CLEAN_LIST_SIZE) {
3890 /* flushall will also only get set for
3891 * for a current pmap
3893 cpu_idcache_wbinv_all();
3894 cpu_l2cache_wbinv_all();
3907 pmap_free_l2_bucket(pm, l2b, mappings);
3910 vm_page_unlock_queues();
3919 * Zero a given physical page by mapping it at a page hook point.
3920 * In doing the zero page op, the page we zero is mapped cachable, as with
3921 * StrongARM accesses to non-cached pages are non-burst making writing
3922 * _any_ bulk data very slow.
3924 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_CORE3)
3926 pmap_zero_page_generic(vm_paddr_t phys, int off, int size)
3928 #ifdef ARM_USE_SMALL_ALLOC
3933 struct vm_page *pg = PHYS_TO_VM_PAGE(phys);
3935 if (pg->md.pvh_list != NULL)
3936 panic("pmap_zero_page: page has mappings");
3939 if (_arm_bzero && size >= _min_bzero_size &&
3940 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0)
3943 #ifdef ARM_USE_SMALL_ALLOC
3944 dstpg = (char *)arm_ptovirt(phys);
3945 if (off || size != PAGE_SIZE) {
3946 bzero(dstpg + off, size);
3947 cpu_dcache_wbinv_range((vm_offset_t)(dstpg + off), size);
3948 cpu_l2cache_wbinv_range((vm_offset_t)(dstpg + off), size);
3950 bzero_page((vm_offset_t)dstpg);
3951 cpu_dcache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE);
3952 cpu_l2cache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE);
3958 * Hook in the page, zero it, invalidate the TLB as needed.
3960 * Note the temporary zero-page mapping must be a non-cached page in
3961 * ordert to work without corruption when write-allocate is enabled.
3963 *cdst_pte = L2_S_PROTO | phys | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE);
3964 cpu_tlb_flushD_SE(cdstp);
3966 if (off || size != PAGE_SIZE)
3967 bzero((void *)(cdstp + off), size);
3974 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
3976 #if ARM_MMU_XSCALE == 1
3978 pmap_zero_page_xscale(vm_paddr_t phys, int off, int size)
3980 #ifdef ARM_USE_SMALL_ALLOC
3984 if (_arm_bzero && size >= _min_bzero_size &&
3985 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0)
3987 #ifdef ARM_USE_SMALL_ALLOC
3988 dstpg = (char *)arm_ptovirt(phys);
3989 if (off || size != PAGE_SIZE) {
3990 bzero(dstpg + off, size);
3991 cpu_dcache_wbinv_range((vm_offset_t)(dstpg + off), size);
3993 bzero_page((vm_offset_t)dstpg);
3994 cpu_dcache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE);
3999 * Hook in the page, zero it, and purge the cache for that
4000 * zeroed page. Invalidate the TLB as needed.
4002 *cdst_pte = L2_S_PROTO | phys |
4003 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4004 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4006 cpu_tlb_flushD_SE(cdstp);
4008 if (off || size != PAGE_SIZE)
4009 bzero((void *)(cdstp + off), size);
4013 xscale_cache_clean_minidata();
4018 * Change the PTEs for the specified kernel mappings such that they
4019 * will use the mini data cache instead of the main data cache.
4022 pmap_use_minicache(vm_offset_t va, vm_size_t size)
4024 struct l2_bucket *l2b;
4025 pt_entry_t *ptep, *sptep, pte;
4026 vm_offset_t next_bucket, eva;
4028 #if (ARM_NMMUS > 1) || defined(CPU_XSCALE_CORE3)
4029 if (xscale_use_minidata == 0)
4036 next_bucket = L2_NEXT_BUCKET(va);
4037 if (next_bucket > eva)
4040 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
4042 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)];
4044 while (va < next_bucket) {
4046 if (!l2pte_minidata(pte)) {
4047 cpu_dcache_wbinv_range(va, PAGE_SIZE);
4048 cpu_tlb_flushD_SE(va);
4049 *ptep = pte & ~L2_B;
4054 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep));
4058 #endif /* ARM_MMU_XSCALE == 1 */
4061 * pmap_zero_page zeros the specified hardware page by mapping
4062 * the page into KVM and using bzero to clear its contents.
4065 pmap_zero_page(vm_page_t m)
4067 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), 0, PAGE_SIZE);
4072 * pmap_zero_page_area zeros the specified hardware page by mapping
4073 * the page into KVM and using bzero to clear its contents.
4075 * off and size may not cover an area beyond a single hardware page.
4078 pmap_zero_page_area(vm_page_t m, int off, int size)
4081 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), off, size);
4086 * pmap_zero_page_idle zeros the specified hardware page by mapping
4087 * the page into KVM and using bzero to clear its contents. This
4088 * is intended to be called from the vm_pagezero process only and
4092 pmap_zero_page_idle(vm_page_t m)
4102 * This is a local function used to work out the best strategy to clean
4103 * a single page referenced by its entry in the PV table. It's used by
4104 * pmap_copy_page, pmap_zero page and maybe some others later on.
4106 * Its policy is effectively:
4107 * o If there are no mappings, we don't bother doing anything with the cache.
4108 * o If there is one mapping, we clean just that page.
4109 * o If there are multiple mappings, we clean the entire cache.
4111 * So that some functions can be further optimised, it returns 0 if it didn't
4112 * clean the entire cache, or 1 if it did.
4114 * XXX One bug in this routine is that if the pv_entry has a single page
4115 * mapped at 0x00000000 a whole cache clean will be performed rather than
4116 * just the 1 page. Since this should not occur in everyday use and if it does
4117 * it will just result in not the most efficient clean for the page.
4120 pmap_clean_page(struct pv_entry *pv, boolean_t is_src)
4122 pmap_t pm, pm_to_clean = NULL;
4123 struct pv_entry *npv;
4124 u_int cache_needs_cleaning = 0;
4126 vm_offset_t page_to_clean = 0;
4129 /* nothing mapped in so nothing to flush */
4134 * Since we flush the cache each time we change to a different
4135 * user vmspace, we only need to flush the page if it is in the
4139 pm = vmspace_pmap(curproc->p_vmspace);
4143 for (npv = pv; npv; npv = TAILQ_NEXT(npv, pv_list)) {
4144 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) {
4145 flags |= npv->pv_flags;
4147 * The page is mapped non-cacheable in
4148 * this map. No need to flush the cache.
4150 if (npv->pv_flags & PVF_NC) {
4152 if (cache_needs_cleaning)
4153 panic("pmap_clean_page: "
4154 "cache inconsistency");
4157 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0)
4159 if (cache_needs_cleaning) {
4163 page_to_clean = npv->pv_va;
4164 pm_to_clean = npv->pv_pmap;
4166 cache_needs_cleaning = 1;
4169 if (page_to_clean) {
4170 if (PV_BEEN_EXECD(flags))
4171 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean,
4174 pmap_dcache_wb_range(pm_to_clean, page_to_clean,
4175 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0);
4176 } else if (cache_needs_cleaning) {
4177 if (PV_BEEN_EXECD(flags))
4178 pmap_idcache_wbinv_all(pm);
4180 pmap_dcache_wbinv_all(pm);
4188 * pmap_copy_page copies the specified (machine independent)
4189 * page by mapping the page into virtual memory and using
4190 * bcopy to copy the page, one machine dependent page at a
4197 * Copy one physical page into another, by mapping the pages into
4198 * hook points. The same comment regarding cachability as in
4199 * pmap_zero_page also applies here.
4201 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined (CPU_XSCALE_CORE3)
4203 pmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst)
4206 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4209 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst);
4211 if (dst_pg->md.pvh_list != NULL)
4212 panic("pmap_copy_page: dst page has mappings");
4217 * Clean the source page. Hold the source page's lock for
4218 * the duration of the copy so that no other mappings can
4219 * be created while we have a potentially aliased mapping.
4223 * XXX: Not needed while we call cpu_dcache_wbinv_all() in
4226 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4229 * Map the pages into the page hook points, copy them, and purge
4230 * the cache for the appropriate page. Invalidate the TLB
4234 *csrc_pte = L2_S_PROTO | src |
4235 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
4237 *cdst_pte = L2_S_PROTO | dst |
4238 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
4240 cpu_tlb_flushD_SE(csrcp);
4241 cpu_tlb_flushD_SE(cdstp);
4243 bcopy_page(csrcp, cdstp);
4245 cpu_dcache_inv_range(csrcp, PAGE_SIZE);
4246 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE);
4247 cpu_l2cache_inv_range(csrcp, PAGE_SIZE);
4248 cpu_l2cache_wbinv_range(cdstp, PAGE_SIZE);
4250 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
4252 #if ARM_MMU_XSCALE == 1
4254 pmap_copy_page_xscale(vm_paddr_t src, vm_paddr_t dst)
4257 /* XXX: Only needed for pmap_clean_page(), which is commented out. */
4258 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4261 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst);
4263 if (dst_pg->md.pvh_list != NULL)
4264 panic("pmap_copy_page: dst page has mappings");
4269 * Clean the source page. Hold the source page's lock for
4270 * the duration of the copy so that no other mappings can
4271 * be created while we have a potentially aliased mapping.
4275 * XXX: Not needed while we call cpu_dcache_wbinv_all() in
4278 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4281 * Map the pages into the page hook points, copy them, and purge
4282 * the cache for the appropriate page. Invalidate the TLB
4286 *csrc_pte = L2_S_PROTO | src |
4287 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
4288 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4290 *cdst_pte = L2_S_PROTO | dst |
4291 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4292 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4294 cpu_tlb_flushD_SE(csrcp);
4295 cpu_tlb_flushD_SE(cdstp);
4297 bcopy_page(csrcp, cdstp);
4299 xscale_cache_clean_minidata();
4301 #endif /* ARM_MMU_XSCALE == 1 */
4304 pmap_copy_page(vm_page_t src, vm_page_t dst)
4306 #ifdef ARM_USE_SMALL_ALLOC
4307 vm_offset_t srcpg, dstpg;
4310 cpu_dcache_wbinv_all();
4311 cpu_l2cache_wbinv_all();
4312 if (_arm_memcpy && PAGE_SIZE >= _min_memcpy_size &&
4313 _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst),
4314 (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0)
4316 #ifdef ARM_USE_SMALL_ALLOC
4317 srcpg = arm_ptovirt(VM_PAGE_TO_PHYS(src));
4318 dstpg = arm_ptovirt(VM_PAGE_TO_PHYS(dst));
4319 bcopy_page(srcpg, dstpg);
4320 cpu_dcache_wbinv_range(dstpg, PAGE_SIZE);
4321 cpu_l2cache_wbinv_range(dstpg, PAGE_SIZE);
4323 pmap_copy_page_func(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst));
4331 * this routine returns true if a physical page resides
4332 * in the given pmap.
4335 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4340 if (m->flags & PG_FICTITIOUS)
4344 * Not found, check current mappings returning immediately
4346 for (pv = TAILQ_FIRST(&m->md.pv_list);
4348 pv = TAILQ_NEXT(pv, pv_list)) {
4349 if (pv->pv_pmap == pmap) {
4360 * pmap_page_wired_mappings:
4362 * Return the number of managed mappings to the given physical page
4366 pmap_page_wired_mappings(vm_page_t m)
4372 if ((m->flags & PG_FICTITIOUS) != 0)
4374 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
4375 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
4376 if ((pv->pv_flags & PVF_WIRED) != 0)
4382 * pmap_ts_referenced:
4384 * Return the count of reference bits for a page, clearing all of them.
4387 pmap_ts_referenced(vm_page_t m)
4390 if (m->flags & PG_FICTITIOUS)
4392 return (pmap_clearbit(m, PVF_REF));
4397 pmap_is_modified(vm_page_t m)
4400 if (m->md.pvh_attrs & PVF_MOD)
4408 * Clear the modify bits on the specified physical page.
4411 pmap_clear_modify(vm_page_t m)
4414 if (m->md.pvh_attrs & PVF_MOD)
4415 pmap_clearbit(m, PVF_MOD);
4420 * pmap_clear_reference:
4422 * Clear the reference bit on the specified physical page.
4425 pmap_clear_reference(vm_page_t m)
4428 if (m->md.pvh_attrs & PVF_REF)
4429 pmap_clearbit(m, PVF_REF);
4434 * Clear the write and modified bits in each of the given page's mappings.
4437 pmap_remove_write(vm_page_t m)
4440 if (m->flags & PG_WRITEABLE)
4441 pmap_clearbit(m, PVF_WRITE);
4446 * perform the pmap work for mincore
4449 pmap_mincore(pmap_t pmap, vm_offset_t addr)
4451 printf("pmap_mincore()\n");
4458 * Increase the starting virtual address of the given mapping if a
4459 * different alignment might result in more superpage mappings.
4462 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
4463 vm_offset_t *addr, vm_size_t size)
4469 * Map a set of physical memory pages into the kernel virtual
4470 * address space. Return a pointer to where it is mapped. This
4471 * routine is intended to be used for mapping device memory,
4475 pmap_mapdev(vm_offset_t pa, vm_size_t size)
4477 vm_offset_t va, tmpva, offset;
4479 offset = pa & PAGE_MASK;
4480 size = roundup(size, PAGE_SIZE);
4484 va = kmem_alloc_nofault(kernel_map, size);
4486 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
4487 for (tmpva = va; size > 0;) {
4488 pmap_kenter_internal(tmpva, pa, 0);
4494 return ((void *)(va + offset));
4497 #define BOOTSTRAP_DEBUG
4502 * Create a single section mapping.
4505 pmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4506 int prot, int cache)
4508 pd_entry_t *pde = (pd_entry_t *) l1pt;
4511 KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2"));
4520 fl = pte_l1_s_cache_mode;
4524 fl = pte_l1_s_cache_mode_pt;
4528 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4529 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL);
4530 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4537 * Link the L2 page table specified by l2pv.pv_pa into the L1
4538 * page table at the slot for "va".
4541 pmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv)
4543 pd_entry_t *pde = (pd_entry_t *) l1pt, proto;
4544 u_int slot = va >> L1_S_SHIFT;
4546 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO;
4548 #ifdef VERBOSE_INIT_ARM
4549 printf("pmap_link_l2pt: pa=0x%x va=0x%x\n", l2pv->pv_pa, l2pv->pv_va);
4552 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000);
4554 PTE_SYNC(&pde[slot]);
4556 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list);
4564 * Create a single page mapping.
4567 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot,
4570 pd_entry_t *pde = (pd_entry_t *) l1pt;
4574 KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin"));
4583 fl = pte_l2_s_cache_mode;
4587 fl = pte_l2_s_cache_mode_pt;
4591 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4592 panic("pmap_map_entry: no L2 table for VA 0x%08x", va);
4594 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4597 panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va);
4599 pte[l2pte_index(va)] =
4600 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl;
4601 PTE_SYNC(&pte[l2pte_index(va)]);
4607 * Map a chunk of memory using the most efficient mappings
4608 * possible (section. large page, small page) into the
4609 * provided L1 and L2 tables at the specified virtual address.
4612 pmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4613 vm_size_t size, int prot, int cache)
4615 pd_entry_t *pde = (pd_entry_t *) l1pt;
4616 pt_entry_t *pte, f1, f2s, f2l;
4620 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
4623 panic("pmap_map_chunk: no L1 table provided");
4625 #ifdef VERBOSE_INIT_ARM
4626 printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x "
4627 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache);
4639 f1 = pte_l1_s_cache_mode;
4640 f2l = pte_l2_l_cache_mode;
4641 f2s = pte_l2_s_cache_mode;
4645 f1 = pte_l1_s_cache_mode_pt;
4646 f2l = pte_l2_l_cache_mode_pt;
4647 f2s = pte_l2_s_cache_mode_pt;
4654 /* See if we can use a section mapping. */
4655 if (L1_S_MAPPABLE_P(va, pa, resid)) {
4656 #ifdef VERBOSE_INIT_ARM
4659 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4660 L1_S_PROT(PTE_KERNEL, prot) | f1 |
4661 L1_S_DOM(PMAP_DOMAIN_KERNEL);
4662 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4670 * Ok, we're going to use an L2 table. Make sure
4671 * one is actually in the corresponding L1 slot
4672 * for the current VA.
4674 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4675 panic("pmap_map_chunk: no L2 table for VA 0x%08x", va);
4677 pte = (pt_entry_t *) kernel_pt_lookup(
4678 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4680 panic("pmap_map_chunk: can't find L2 table for VA"
4682 /* See if we can use a L2 large page mapping. */
4683 if (L2_L_MAPPABLE_P(va, pa, resid)) {
4684 #ifdef VERBOSE_INIT_ARM
4687 for (i = 0; i < 16; i++) {
4688 pte[l2pte_index(va) + i] =
4690 L2_L_PROT(PTE_KERNEL, prot) | f2l;
4691 PTE_SYNC(&pte[l2pte_index(va) + i]);
4699 /* Use a small page mapping. */
4700 #ifdef VERBOSE_INIT_ARM
4703 pte[l2pte_index(va)] =
4704 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s;
4705 PTE_SYNC(&pte[l2pte_index(va)]);
4710 #ifdef VERBOSE_INIT_ARM
4717 /********************** Static device map routines ***************************/
4719 static const struct pmap_devmap *pmap_devmap_table;
4722 * Register the devmap table. This is provided in case early console
4723 * initialization needs to register mappings created by bootstrap code
4724 * before pmap_devmap_bootstrap() is called.
4727 pmap_devmap_register(const struct pmap_devmap *table)
4730 pmap_devmap_table = table;
4734 * Map all of the static regions in the devmap table, and remember
4735 * the devmap table so other parts of the kernel can look up entries
4739 pmap_devmap_bootstrap(vm_offset_t l1pt, const struct pmap_devmap *table)
4743 pmap_devmap_table = table;
4745 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
4746 #ifdef VERBOSE_INIT_ARM
4747 printf("devmap: %08x -> %08x @ %08x\n",
4748 pmap_devmap_table[i].pd_pa,
4749 pmap_devmap_table[i].pd_pa +
4750 pmap_devmap_table[i].pd_size - 1,
4751 pmap_devmap_table[i].pd_va);
4753 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va,
4754 pmap_devmap_table[i].pd_pa,
4755 pmap_devmap_table[i].pd_size,
4756 pmap_devmap_table[i].pd_prot,
4757 pmap_devmap_table[i].pd_cache);
4761 const struct pmap_devmap *
4762 pmap_devmap_find_pa(vm_paddr_t pa, vm_size_t size)
4766 if (pmap_devmap_table == NULL)
4769 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
4770 if (pa >= pmap_devmap_table[i].pd_pa &&
4771 pa + size <= pmap_devmap_table[i].pd_pa +
4772 pmap_devmap_table[i].pd_size)
4773 return (&pmap_devmap_table[i]);
4779 const struct pmap_devmap *
4780 pmap_devmap_find_va(vm_offset_t va, vm_size_t size)
4784 if (pmap_devmap_table == NULL)
4787 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
4788 if (va >= pmap_devmap_table[i].pd_va &&
4789 va + size <= pmap_devmap_table[i].pd_va +
4790 pmap_devmap_table[i].pd_size)
4791 return (&pmap_devmap_table[i]);