1 /* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */
3 * Copyright 2004 Olivier Houchard.
4 * Copyright 2003 Wasabi Systems, Inc.
7 * Written by Steve C. Woodford for Wasabi Systems, Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
39 * Copyright (c) 2002-2003 Wasabi Systems, Inc.
40 * Copyright (c) 2001 Richard Earnshaw
41 * Copyright (c) 2001-2002 Christopher Gilbert
42 * All rights reserved.
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. The name of the company nor the name of the author may be used to
50 * endorse or promote products derived from this software without specific
51 * prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
66 * Copyright (c) 1999 The NetBSD Foundation, Inc.
67 * All rights reserved.
69 * This code is derived from software contributed to The NetBSD Foundation
70 * by Charles M. Hannum.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
80 * 3. All advertising materials mentioning features or use of this software
81 * must display the following acknowledgement:
82 * This product includes software developed by the NetBSD
83 * Foundation, Inc. and its contributors.
84 * 4. Neither the name of The NetBSD Foundation nor the names of its
85 * contributors may be used to endorse or promote products derived
86 * from this software without specific prior written permission.
88 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
89 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
90 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
91 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
92 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
93 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
94 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
95 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
96 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
97 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
98 * POSSIBILITY OF SUCH DAMAGE.
102 * Copyright (c) 1994-1998 Mark Brinicombe.
103 * Copyright (c) 1994 Brini.
104 * All rights reserved.
106 * This code is derived from software written for Brini by Mark Brinicombe
108 * Redistribution and use in source and binary forms, with or without
109 * modification, are permitted provided that the following conditions
111 * 1. Redistributions of source code must retain the above copyright
112 * notice, this list of conditions and the following disclaimer.
113 * 2. Redistributions in binary form must reproduce the above copyright
114 * notice, this list of conditions and the following disclaimer in the
115 * documentation and/or other materials provided with the distribution.
116 * 3. All advertising materials mentioning features or use of this software
117 * must display the following acknowledgement:
118 * This product includes software developed by Mark Brinicombe.
119 * 4. The name of the author may not be used to endorse or promote products
120 * derived from this software without specific prior written permission.
122 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
123 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
124 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
125 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
126 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
127 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
128 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
129 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
130 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
132 * RiscBSD kernel project
136 * Machine dependant vm stuff
142 * Special compilation symbols
143 * PMAP_DEBUG - Build in pmap_debug_level code
145 /* Include header files */
149 #include <sys/cdefs.h>
150 __FBSDID("$FreeBSD$");
151 #include <sys/param.h>
152 #include <sys/systm.h>
153 #include <sys/kernel.h>
154 #include <sys/proc.h>
155 #include <sys/malloc.h>
156 #include <sys/msgbuf.h>
157 #include <sys/vmmeter.h>
158 #include <sys/mman.h>
160 #include <sys/sched.h>
165 #include <vm/vm_kern.h>
166 #include <vm/vm_object.h>
167 #include <vm/vm_map.h>
168 #include <vm/vm_page.h>
169 #include <vm/vm_pageout.h>
170 #include <vm/vm_extern.h>
171 #include <sys/lock.h>
172 #include <sys/mutex.h>
173 #include <machine/md_var.h>
174 #include <machine/vmparam.h>
175 #include <machine/cpu.h>
176 #include <machine/cpufunc.h>
177 #include <machine/pcb.h>
180 #define PDEBUG(_lev_,_stat_) \
181 if (pmap_debug_level >= (_lev_)) \
183 #define dprintf printf
185 int pmap_debug_level = 0;
187 #else /* PMAP_DEBUG */
188 #define PDEBUG(_lev_,_stat_) /* Nothing */
189 #define dprintf(x, arg...)
190 #define PMAP_INLINE __inline
191 #endif /* PMAP_DEBUG */
193 extern struct pv_addr systempage;
195 * Internal function prototypes
197 static void pmap_free_pv_entry (pv_entry_t);
198 static pv_entry_t pmap_get_pv_entry(void);
200 static void pmap_enter_locked(pmap_t, vm_offset_t, vm_page_t,
201 vm_prot_t, boolean_t, int);
202 static void pmap_vac_me_harder(struct vm_page *, pmap_t,
204 static void pmap_vac_me_kpmap(struct vm_page *, pmap_t,
206 static void pmap_vac_me_user(struct vm_page *, pmap_t, vm_offset_t);
207 static void pmap_alloc_l1(pmap_t);
208 static void pmap_free_l1(pmap_t);
209 static void pmap_use_l1(pmap_t);
211 static int pmap_clearbit(struct vm_page *, u_int);
213 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t);
214 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t);
215 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int);
216 static vm_offset_t kernel_pt_lookup(vm_paddr_t);
218 static MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1");
220 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
221 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
222 vm_offset_t pmap_curmaxkvaddr;
223 vm_paddr_t kernel_l1pa;
226 vm_offset_t kernel_vm_end = 0;
228 struct pmap kernel_pmap_store;
231 static pt_entry_t *csrc_pte, *cdst_pte;
232 static vm_offset_t csrcp, cdstp;
233 static struct mtx cmtx;
235 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *);
237 * These routines are called when the CPU type is identified to set up
238 * the PTE prototypes, cache modes, etc.
240 * The variables are always here, just in case LKMs need to reference
241 * them (though, they shouldn't).
244 pt_entry_t pte_l1_s_cache_mode;
245 pt_entry_t pte_l1_s_cache_mode_pt;
246 pt_entry_t pte_l1_s_cache_mask;
248 pt_entry_t pte_l2_l_cache_mode;
249 pt_entry_t pte_l2_l_cache_mode_pt;
250 pt_entry_t pte_l2_l_cache_mask;
252 pt_entry_t pte_l2_s_cache_mode;
253 pt_entry_t pte_l2_s_cache_mode_pt;
254 pt_entry_t pte_l2_s_cache_mask;
256 pt_entry_t pte_l2_s_prot_u;
257 pt_entry_t pte_l2_s_prot_w;
258 pt_entry_t pte_l2_s_prot_mask;
260 pt_entry_t pte_l1_s_proto;
261 pt_entry_t pte_l1_c_proto;
262 pt_entry_t pte_l2_s_proto;
264 void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t);
265 void (*pmap_zero_page_func)(vm_paddr_t, int, int);
267 * Which pmap is currently 'live' in the cache
269 * XXXSCW: Fix for SMP ...
271 union pmap_cache_state *pmap_cache_state;
273 /* static pt_entry_t *msgbufmap;*/
274 struct msgbuf *msgbufp = 0;
276 extern void bcopy_page(vm_offset_t, vm_offset_t);
277 extern void bzero_page(vm_offset_t);
279 extern vm_offset_t alloc_firstaddr;
284 * Metadata for L1 translation tables.
287 /* Entry on the L1 Table list */
288 SLIST_ENTRY(l1_ttable) l1_link;
290 /* Entry on the L1 Least Recently Used list */
291 TAILQ_ENTRY(l1_ttable) l1_lru;
293 /* Track how many domains are allocated from this L1 */
294 volatile u_int l1_domain_use_count;
297 * A free-list of domain numbers for this L1.
298 * We avoid using ffs() and a bitmap to track domains since ffs()
301 u_int8_t l1_domain_first;
302 u_int8_t l1_domain_free[PMAP_DOMAINS];
304 /* Physical address of this L1 page table */
305 vm_paddr_t l1_physaddr;
307 /* KVA of this L1 page table */
312 * Convert a virtual address into its L1 table index. That is, the
313 * index used to locate the L2 descriptor table pointer in an L1 table.
314 * This is basically used to index l1->l1_kva[].
316 * Each L2 descriptor table represents 1MB of VA space.
318 #define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT)
321 * L1 Page Tables are tracked using a Least Recently Used list.
322 * - New L1s are allocated from the HEAD.
323 * - Freed L1s are added to the TAIl.
324 * - Recently accessed L1s (where an 'access' is some change to one of
325 * the userland pmaps which owns this L1) are moved to the TAIL.
327 static TAILQ_HEAD(, l1_ttable) l1_lru_list;
329 * A list of all L1 tables
331 static SLIST_HEAD(, l1_ttable) l1_list;
332 static struct mtx l1_lru_lock;
335 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots.
337 * This is normally 16MB worth L2 page descriptors for any given pmap.
338 * Reference counts are maintained for L2 descriptors so they can be
342 /* The number of L2 page descriptors allocated to this l2_dtable */
345 /* List of L2 page descriptors */
347 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */
348 vm_paddr_t l2b_phys; /* Physical address of same */
349 u_short l2b_l1idx; /* This L2 table's L1 index */
350 u_short l2b_occupancy; /* How many active descriptors */
351 } l2_bucket[L2_BUCKET_SIZE];
354 /* pmap_kenter_internal flags */
355 #define KENTER_CACHE 0x1
356 #define KENTER_USER 0x2
359 * Given an L1 table index, calculate the corresponding l2_dtable index
360 * and bucket index within the l2_dtable.
362 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \
364 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1))
367 * Given a virtual address, this macro returns the
368 * virtual address required to drop into the next L2 bucket.
370 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE)
375 #define pmap_alloc_l2_dtable() \
376 (void*)uma_zalloc(l2table_zone, M_NOWAIT|M_USE_RESERVE)
377 #define pmap_free_l2_dtable(l2) \
378 uma_zfree(l2table_zone, l2)
381 * We try to map the page tables write-through, if possible. However, not
382 * all CPUs have a write-through cache mode, so on those we have to sync
383 * the cache when we frob page tables.
385 * We try to evaluate this at compile time, if possible. However, it's
386 * not always possible to do that, hence this run-time var.
388 int pmap_needs_pte_sync;
391 * Macro to determine if a mapping might be resident in the
392 * instruction cache and/or TLB
394 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC))
397 * Macro to determine if a mapping might be resident in the
398 * data cache and/or TLB
400 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0)
402 #ifndef PMAP_SHPGPERPROC
403 #define PMAP_SHPGPERPROC 200
406 #define pmap_is_current(pm) ((pm) == pmap_kernel() || \
407 curproc->p_vmspace->vm_map.pmap == (pm))
408 static uma_zone_t pvzone;
410 static uma_zone_t l2table_zone;
411 static vm_offset_t pmap_kernel_l2dtable_kva;
412 static vm_offset_t pmap_kernel_l2ptp_kva;
413 static vm_paddr_t pmap_kernel_l2ptp_phys;
414 static struct vm_object pvzone_obj;
415 static int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0;
418 * This list exists for the benefit of pmap_map_chunk(). It keeps track
419 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can
420 * find them as necessary.
422 * Note that the data on this list MUST remain valid after initarm() returns,
423 * as pmap_bootstrap() uses it to contruct L2 table metadata.
425 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list);
428 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt)
433 l1->l1_domain_use_count = 0;
434 l1->l1_domain_first = 1;
436 for (i = 0; i < PMAP_DOMAINS; i++)
437 l1->l1_domain_free[i] = i + 2;
440 * Copy the kernel's L1 entries to each new L1.
442 if (l1pt != pmap_kernel()->pm_l1->l1_kva)
443 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE);
445 if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0)
446 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt);
447 SLIST_INSERT_HEAD(&l1_list, l1, l1_link);
448 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
452 kernel_pt_lookup(vm_paddr_t pa)
456 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) {
463 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
465 pmap_pte_init_generic(void)
468 pte_l1_s_cache_mode = L1_S_B|L1_S_C;
469 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic;
471 pte_l2_l_cache_mode = L2_B|L2_C;
472 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic;
474 pte_l2_s_cache_mode = L2_B|L2_C;
475 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic;
478 * If we have a write-through cache, set B and C. If
479 * we have a write-back cache, then we assume setting
480 * only C will make those pages write-through.
482 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) {
483 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
484 pte_l2_l_cache_mode_pt = L2_B|L2_C;
485 pte_l2_s_cache_mode_pt = L2_B|L2_C;
487 pte_l1_s_cache_mode_pt = L1_S_C;
488 pte_l2_l_cache_mode_pt = L2_C;
489 pte_l2_s_cache_mode_pt = L2_C;
492 pte_l2_s_prot_u = L2_S_PROT_U_generic;
493 pte_l2_s_prot_w = L2_S_PROT_W_generic;
494 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic;
496 pte_l1_s_proto = L1_S_PROTO_generic;
497 pte_l1_c_proto = L1_C_PROTO_generic;
498 pte_l2_s_proto = L2_S_PROTO_generic;
500 pmap_copy_page_func = pmap_copy_page_generic;
501 pmap_zero_page_func = pmap_zero_page_generic;
504 #if defined(CPU_ARM8)
506 pmap_pte_init_arm8(void)
510 * ARM8 is compatible with generic, but we need to use
511 * the page tables uncached.
513 pmap_pte_init_generic();
515 pte_l1_s_cache_mode_pt = 0;
516 pte_l2_l_cache_mode_pt = 0;
517 pte_l2_s_cache_mode_pt = 0;
519 #endif /* CPU_ARM8 */
521 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH)
523 pmap_pte_init_arm9(void)
527 * ARM9 is compatible with generic, but we want to use
528 * write-through caching for now.
530 pmap_pte_init_generic();
532 pte_l1_s_cache_mode = L1_S_C;
533 pte_l2_l_cache_mode = L2_C;
534 pte_l2_s_cache_mode = L2_C;
536 pte_l1_s_cache_mode_pt = L1_S_C;
537 pte_l2_l_cache_mode_pt = L2_C;
538 pte_l2_s_cache_mode_pt = L2_C;
540 #endif /* CPU_ARM9 */
541 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
543 #if defined(CPU_ARM10)
545 pmap_pte_init_arm10(void)
549 * ARM10 is compatible with generic, but we want to use
550 * write-through caching for now.
552 pmap_pte_init_generic();
554 pte_l1_s_cache_mode = L1_S_B | L1_S_C;
555 pte_l2_l_cache_mode = L2_B | L2_C;
556 pte_l2_s_cache_mode = L2_B | L2_C;
558 pte_l1_s_cache_mode_pt = L1_S_C;
559 pte_l2_l_cache_mode_pt = L2_C;
560 pte_l2_s_cache_mode_pt = L2_C;
563 #endif /* CPU_ARM10 */
567 pmap_pte_init_sa1(void)
571 * The StrongARM SA-1 cache does not have a write-through
572 * mode. So, do the generic initialization, then reset
573 * the page table cache mode to B=1,C=1, and note that
574 * the PTEs need to be sync'd.
576 pmap_pte_init_generic();
578 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
579 pte_l2_l_cache_mode_pt = L2_B|L2_C;
580 pte_l2_s_cache_mode_pt = L2_B|L2_C;
582 pmap_needs_pte_sync = 1;
584 #endif /* ARM_MMU_SA1 == 1*/
586 #if ARM_MMU_XSCALE == 1
587 #if (ARM_NMMUS > 1) || defined (CPU_XSCALE_CORE3)
588 static u_int xscale_use_minidata;
592 pmap_pte_init_xscale(void)
595 int write_through = 0;
597 pte_l1_s_cache_mode = L1_S_B|L1_S_C|L1_S_XSCALE_P;
598 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale;
600 pte_l2_l_cache_mode = L2_B|L2_C;
601 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale;
603 pte_l2_s_cache_mode = L2_B|L2_C;
604 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale;
606 pte_l1_s_cache_mode_pt = L1_S_C;
607 pte_l2_l_cache_mode_pt = L2_C;
608 pte_l2_s_cache_mode_pt = L2_C;
609 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE
611 * The XScale core has an enhanced mode where writes that
612 * miss the cache cause a cache line to be allocated. This
613 * is significantly faster than the traditional, write-through
614 * behavior of this case.
616 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X);
617 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X);
618 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X);
619 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */
620 #ifdef XSCALE_CACHE_WRITE_THROUGH
622 * Some versions of the XScale core have various bugs in
623 * their cache units, the work-around for which is to run
624 * the cache in write-through mode. Unfortunately, this
625 * has a major (negative) impact on performance. So, we
626 * go ahead and run fast-and-loose, in the hopes that we
627 * don't line up the planets in a way that will trip the
630 * However, we give you the option to be slow-but-correct.
633 #elif defined(XSCALE_CACHE_WRITE_BACK)
634 /* force write back cache mode */
636 #elif defined(CPU_XSCALE_PXA2X0)
638 * Intel PXA2[15]0 processors are known to have a bug in
639 * write-back cache on revision 4 and earlier (stepping
640 * A[01] and B[012]). Fixed for C0 and later.
646 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK);
648 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) {
649 if ((id & CPU_ID_REVISION_MASK) < 5) {
650 /* write through for stepping A0-1 and B0-2 */
655 #endif /* XSCALE_CACHE_WRITE_THROUGH */
658 pte_l1_s_cache_mode = L1_S_C;
659 pte_l2_l_cache_mode = L2_C;
660 pte_l2_s_cache_mode = L2_C;
664 xscale_use_minidata = 1;
667 pte_l2_s_prot_u = L2_S_PROT_U_xscale;
668 pte_l2_s_prot_w = L2_S_PROT_W_xscale;
669 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale;
671 pte_l1_s_proto = L1_S_PROTO_xscale;
672 pte_l1_c_proto = L1_C_PROTO_xscale;
673 pte_l2_s_proto = L2_S_PROTO_xscale;
675 #ifdef CPU_XSCALE_CORE3
676 pmap_copy_page_func = pmap_copy_page_generic;
677 pmap_zero_page_func = pmap_zero_page_generic;
678 xscale_use_minidata = 0;
679 pte_l1_s_cache_mode_pt = pte_l2_l_cache_mode_pt =
680 pte_l2_s_cache_mode_pt = 0;
682 pmap_copy_page_func = pmap_copy_page_xscale;
683 pmap_zero_page_func = pmap_zero_page_xscale;
687 * Disable ECC protection of page table access, for now.
689 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
690 auxctl &= ~XSCALE_AUXCTL_P;
691 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
695 * xscale_setup_minidata:
697 * Set up the mini-data cache clean area. We require the
698 * caller to allocate the right amount of physically and
699 * virtually contiguous space.
701 extern vm_offset_t xscale_minidata_clean_addr;
702 extern vm_size_t xscale_minidata_clean_size; /* already initialized */
704 xscale_setup_minidata(vm_offset_t l1pt, vm_offset_t va, vm_paddr_t pa)
706 pd_entry_t *pde = (pd_entry_t *) l1pt;
711 xscale_minidata_clean_addr = va;
713 /* Round it to page size. */
714 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME;
717 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) {
718 pte = (pt_entry_t *) kernel_pt_lookup(
719 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
721 panic("xscale_setup_minidata: can't find L2 table for "
722 "VA 0x%08x", (u_int32_t) va);
723 pte[l2pte_index(va)] =
724 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
725 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X);
729 * Configure the mini-data cache for write-back with
730 * read/write-allocate.
732 * NOTE: In order to reconfigure the mini-data cache, we must
733 * make sure it contains no valid data! In order to do that,
734 * we must issue a global data cache invalidate command!
736 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED!
737 * THIS IS VERY IMPORTANT!
740 /* Invalidate data and mini-data. */
741 __asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
742 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
743 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA;
744 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
749 * Allocate an L1 translation table for the specified pmap.
750 * This is called at pmap creation time.
753 pmap_alloc_l1(pmap_t pm)
755 struct l1_ttable *l1;
759 * Remove the L1 at the head of the LRU list
761 mtx_lock(&l1_lru_lock);
762 l1 = TAILQ_FIRST(&l1_lru_list);
763 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
766 * Pick the first available domain number, and update
767 * the link to the next number.
769 domain = l1->l1_domain_first;
770 l1->l1_domain_first = l1->l1_domain_free[domain];
773 * If there are still free domain numbers in this L1,
774 * put it back on the TAIL of the LRU list.
776 if (++l1->l1_domain_use_count < PMAP_DOMAINS)
777 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
779 mtx_unlock(&l1_lru_lock);
782 * Fix up the relevant bits in the pmap structure
785 pm->pm_domain = domain;
789 * Free an L1 translation table.
790 * This is called at pmap destruction time.
793 pmap_free_l1(pmap_t pm)
795 struct l1_ttable *l1 = pm->pm_l1;
797 mtx_lock(&l1_lru_lock);
800 * If this L1 is currently on the LRU list, remove it.
802 if (l1->l1_domain_use_count < PMAP_DOMAINS)
803 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
806 * Free up the domain number which was allocated to the pmap
808 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first;
809 l1->l1_domain_first = pm->pm_domain;
810 l1->l1_domain_use_count--;
813 * The L1 now must have at least 1 free domain, so add
814 * it back to the LRU list. If the use count is zero,
815 * put it at the head of the list, otherwise it goes
818 if (l1->l1_domain_use_count == 0) {
819 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru);
821 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
823 mtx_unlock(&l1_lru_lock);
826 static PMAP_INLINE void
827 pmap_use_l1(pmap_t pm)
829 struct l1_ttable *l1;
832 * Do nothing if we're in interrupt context.
833 * Access to an L1 by the kernel pmap must not affect
836 if (pm == pmap_kernel())
842 * If the L1 is not currently on the LRU list, just return
844 if (l1->l1_domain_use_count == PMAP_DOMAINS)
847 mtx_lock(&l1_lru_lock);
850 * Check the use count again, now that we've acquired the lock
852 if (l1->l1_domain_use_count == PMAP_DOMAINS) {
853 mtx_unlock(&l1_lru_lock);
858 * Move the L1 to the back of the LRU list
860 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
861 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
863 mtx_unlock(&l1_lru_lock);
868 * Returns a pointer to the L2 bucket associated with the specified pmap
869 * and VA, or NULL if no L2 bucket exists for the address.
871 static PMAP_INLINE struct l2_bucket *
872 pmap_get_l2_bucket(pmap_t pm, vm_offset_t va)
874 struct l2_dtable *l2;
875 struct l2_bucket *l2b;
880 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL ||
881 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL)
888 * Returns a pointer to the L2 bucket associated with the specified pmap
891 * If no L2 bucket exists, perform the necessary allocations to put an L2
892 * bucket/page table in place.
894 * Note that if a new L2 bucket/page was allocated, the caller *must*
895 * increment the bucket occupancy counter appropriately *before*
896 * releasing the pmap's lock to ensure no other thread or cpu deallocates
897 * the bucket/page in the meantime.
899 static struct l2_bucket *
900 pmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va)
902 struct l2_dtable *l2;
903 struct l2_bucket *l2b;
908 PMAP_ASSERT_LOCKED(pm);
909 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
910 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
912 * No mapping at this address, as there is
913 * no entry in the L1 table.
914 * Need to allocate a new l2_dtable.
918 vm_page_unlock_queues();
919 if ((l2 = pmap_alloc_l2_dtable()) == NULL) {
920 vm_page_lock_queues();
924 vm_page_lock_queues();
926 if (pm->pm_l2[L2_IDX(l1idx)] != NULL) {
928 vm_page_unlock_queues();
929 uma_zfree(l2table_zone, l2);
930 vm_page_lock_queues();
932 l2 = pm->pm_l2[L2_IDX(l1idx)];
936 * Someone already allocated the l2_dtable while
937 * we were doing the same.
940 bzero(l2, sizeof(*l2));
942 * Link it into the parent pmap
944 pm->pm_l2[L2_IDX(l1idx)] = l2;
948 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
951 * Fetch pointer to the L2 page table associated with the address.
953 if (l2b->l2b_kva == NULL) {
957 * No L2 page table has been allocated. Chances are, this
958 * is because we just allocated the l2_dtable, above.
962 vm_page_unlock_queues();
963 ptep = (void*)uma_zalloc(l2zone, M_NOWAIT|M_USE_RESERVE);
964 vm_page_lock_queues();
966 if (l2b->l2b_kva != 0) {
967 /* We lost the race. */
969 vm_page_unlock_queues();
970 uma_zfree(l2zone, ptep);
971 vm_page_lock_queues();
973 if (l2b->l2b_kva == 0)
977 l2b->l2b_phys = vtophys(ptep);
980 * Oops, no more L2 page tables available at this
981 * time. We may need to deallocate the l2_dtable
982 * if we allocated a new one above.
984 if (l2->l2_occupancy == 0) {
985 pm->pm_l2[L2_IDX(l1idx)] = NULL;
986 pmap_free_l2_dtable(l2);
993 l2b->l2b_l1idx = l1idx;
999 static PMAP_INLINE void
1000 #ifndef PMAP_INCLUDE_PTE_SYNC
1001 pmap_free_l2_ptp(pt_entry_t *l2)
1003 pmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2)
1006 #ifdef PMAP_INCLUDE_PTE_SYNC
1008 * Note: With a write-back cache, we may need to sync this
1009 * L2 table before re-using it.
1010 * This is because it may have belonged to a non-current
1011 * pmap, in which case the cache syncs would have been
1012 * skipped when the pages were being unmapped. If the
1013 * L2 table were then to be immediately re-allocated to
1014 * the *current* pmap, it may well contain stale mappings
1015 * which have not yet been cleared by a cache write-back
1016 * and so would still be visible to the mmu.
1019 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
1021 uma_zfree(l2zone, l2);
1024 * One or more mappings in the specified L2 descriptor table have just been
1027 * Garbage collect the metadata and descriptor table itself if necessary.
1029 * The pmap lock must be acquired when this is called (not necessary
1030 * for the kernel pmap).
1033 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count)
1035 struct l2_dtable *l2;
1036 pd_entry_t *pl1pd, l1pd;
1042 * Update the bucket's reference count according to how many
1043 * PTEs the caller has just invalidated.
1045 l2b->l2b_occupancy -= count;
1050 * Level 2 page tables allocated to the kernel pmap are never freed
1051 * as that would require checking all Level 1 page tables and
1052 * removing any references to the Level 2 page table. See also the
1053 * comment elsewhere about never freeing bootstrap L2 descriptors.
1055 * We make do with just invalidating the mapping in the L2 table.
1057 * This isn't really a big deal in practice and, in fact, leads
1058 * to a performance win over time as we don't need to continually
1061 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel())
1065 * There are no more valid mappings in this level 2 page table.
1066 * Go ahead and NULL-out the pointer in the bucket, then
1067 * free the page table.
1069 l1idx = l2b->l2b_l1idx;
1070 ptep = l2b->l2b_kva;
1071 l2b->l2b_kva = NULL;
1073 pl1pd = &pm->pm_l1->l1_kva[l1idx];
1076 * If the L1 slot matches the pmap's domain
1077 * number, then invalidate it.
1079 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK);
1080 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) {
1086 * Release the L2 descriptor table back to the pool cache.
1088 #ifndef PMAP_INCLUDE_PTE_SYNC
1089 pmap_free_l2_ptp(ptep);
1091 pmap_free_l2_ptp(!pmap_is_current(pm), ptep);
1095 * Update the reference count in the associated l2_dtable
1097 l2 = pm->pm_l2[L2_IDX(l1idx)];
1098 if (--l2->l2_occupancy > 0)
1102 * There are no more valid mappings in any of the Level 1
1103 * slots managed by this l2_dtable. Go ahead and NULL-out
1104 * the pointer in the parent pmap and free the l2_dtable.
1106 pm->pm_l2[L2_IDX(l1idx)] = NULL;
1107 pmap_free_l2_dtable(l2);
1111 * Pool cache constructors for L2 descriptor tables, metadata and pmap
1115 pmap_l2ptp_ctor(void *mem, int size, void *arg, int flags)
1117 #ifndef PMAP_INCLUDE_PTE_SYNC
1118 struct l2_bucket *l2b;
1119 pt_entry_t *ptep, pte;
1120 #ifdef ARM_USE_SMALL_ALLOC
1123 vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK;
1126 * The mappings for these page tables were initially made using
1127 * pmap_kenter() by the pool subsystem. Therefore, the cache-
1128 * mode will not be right for page table mappings. To avoid
1129 * polluting the pmap_kenter() code with a special case for
1130 * page tables, we simply fix up the cache-mode here if it's not
1133 #ifdef ARM_USE_SMALL_ALLOC
1134 pde = &kernel_pmap->pm_l1->l1_kva[L1_IDX(va)];
1135 if (!l1pte_section_p(*pde)) {
1137 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
1138 ptep = &l2b->l2b_kva[l2pte_index(va)];
1141 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
1143 * Page tables must have the cache-mode set to
1146 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
1148 cpu_tlb_flushD_SE(va);
1151 #ifdef ARM_USE_SMALL_ALLOC
1155 memset(mem, 0, L2_TABLE_SIZE_REAL);
1156 PTE_SYNC_RANGE(mem, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
1161 * A bunch of routines to conditionally flush the caches/TLB depending
1162 * on whether the specified pmap actually needs to be flushed at any
1165 static PMAP_INLINE void
1166 pmap_tlb_flushID_SE(pmap_t pm, vm_offset_t va)
1169 if (pmap_is_current(pm))
1170 cpu_tlb_flushID_SE(va);
1173 static PMAP_INLINE void
1174 pmap_tlb_flushD_SE(pmap_t pm, vm_offset_t va)
1177 if (pmap_is_current(pm))
1178 cpu_tlb_flushD_SE(va);
1181 static PMAP_INLINE void
1182 pmap_tlb_flushID(pmap_t pm)
1185 if (pmap_is_current(pm))
1188 static PMAP_INLINE void
1189 pmap_tlb_flushD(pmap_t pm)
1192 if (pmap_is_current(pm))
1196 static PMAP_INLINE void
1197 pmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len)
1200 if (pmap_is_current(pm))
1201 cpu_idcache_wbinv_range(va, len);
1204 static PMAP_INLINE void
1205 pmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len,
1206 boolean_t do_inv, boolean_t rd_only)
1209 if (pmap_is_current(pm)) {
1212 cpu_dcache_inv_range(va, len);
1214 cpu_dcache_wbinv_range(va, len);
1217 cpu_dcache_wb_range(va, len);
1221 static PMAP_INLINE void
1222 pmap_idcache_wbinv_all(pmap_t pm)
1225 if (pmap_is_current(pm))
1226 cpu_idcache_wbinv_all();
1229 static PMAP_INLINE void
1230 pmap_dcache_wbinv_all(pmap_t pm)
1233 if (pmap_is_current(pm))
1234 cpu_dcache_wbinv_all();
1240 * Make sure the pte is written out to RAM.
1241 * We need to do this for one of two cases:
1242 * - We're dealing with the kernel pmap
1243 * - There is no pmap active in the cache/tlb.
1244 * - The specified pmap is 'active' in the cache/tlb.
1246 #ifdef PMAP_INCLUDE_PTE_SYNC
1247 #define PTE_SYNC_CURRENT(pm, ptep) \
1249 if (PMAP_NEEDS_PTE_SYNC && \
1250 pmap_is_current(pm)) \
1252 } while (/*CONSTCOND*/0)
1254 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */
1258 * Since we have a virtually indexed cache, we may need to inhibit caching if
1259 * there is more than one mapping and at least one of them is writable.
1260 * Since we purge the cache on every context switch, we only need to check for
1261 * other mappings within the same pmap, or kernel_pmap.
1262 * This function is also called when a page is unmapped, to possibly reenable
1263 * caching on any remaining mappings.
1265 * The code implements the following logic, where:
1267 * KW = # of kernel read/write pages
1268 * KR = # of kernel read only pages
1269 * UW = # of user read/write pages
1270 * UR = # of user read only pages
1272 * KC = kernel mapping is cacheable
1273 * UC = user mapping is cacheable
1275 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0
1276 * +---------------------------------------------
1277 * UW=0,UR=0 | --- KC=1 KC=1 KC=0
1278 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0
1279 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0
1280 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0
1283 static const int pmap_vac_flags[4][4] = {
1284 {-1, 0, 0, PVF_KNC},
1285 {0, 0, PVF_NC, PVF_NC},
1286 {0, PVF_NC, PVF_NC, PVF_NC},
1287 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC}
1290 static PMAP_INLINE int
1291 pmap_get_vac_flags(const struct vm_page *pg)
1296 if (pg->md.kro_mappings || pg->md.krw_mappings > 1)
1298 if (pg->md.krw_mappings)
1302 if (pg->md.uro_mappings || pg->md.urw_mappings > 1)
1304 if (pg->md.urw_mappings)
1307 return (pmap_vac_flags[uidx][kidx]);
1310 static __inline void
1311 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1315 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1316 nattr = pmap_get_vac_flags(pg);
1319 pg->md.pvh_attrs &= ~PVF_NC;
1323 if (nattr == 0 && (pg->md.pvh_attrs & PVF_NC) == 0) {
1327 if (pm == pmap_kernel())
1328 pmap_vac_me_kpmap(pg, pm, va);
1330 pmap_vac_me_user(pg, pm, va);
1332 pg->md.pvh_attrs = (pg->md.pvh_attrs & ~PVF_NC) | nattr;
1336 pmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1338 u_int u_cacheable, u_entries;
1339 struct pv_entry *pv;
1340 pmap_t last_pmap = pm;
1343 * Pass one, see if there are both kernel and user pmaps for
1344 * this page. Calculate whether there are user-writable or
1345 * kernel-writable pages.
1348 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1349 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0)
1353 u_entries = pg->md.urw_mappings + pg->md.uro_mappings;
1356 * We know we have just been updating a kernel entry, so if
1357 * all user pages are already cacheable, then there is nothing
1360 if (pg->md.k_mappings == 0 && u_cacheable == u_entries)
1365 * Scan over the list again, for each entry, if it
1366 * might not be set correctly, call pmap_vac_me_user
1367 * to recalculate the settings.
1369 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1371 * We know kernel mappings will get set
1372 * correctly in other calls. We also know
1373 * that if the pmap is the same as last_pmap
1374 * then we've just handled this entry.
1376 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap)
1380 * If there are kernel entries and this page
1381 * is writable but non-cacheable, then we can
1382 * skip this entry also.
1384 if (pg->md.k_mappings &&
1385 (pv->pv_flags & (PVF_NC | PVF_WRITE)) ==
1386 (PVF_NC | PVF_WRITE))
1390 * Similarly if there are no kernel-writable
1391 * entries and the page is already
1392 * read-only/cacheable.
1394 if (pg->md.krw_mappings == 0 &&
1395 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0)
1399 * For some of the remaining cases, we know
1400 * that we must recalculate, but for others we
1401 * can't tell if they are correct or not, so
1402 * we recalculate anyway.
1404 pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0);
1407 if (pg->md.k_mappings == 0)
1411 pmap_vac_me_user(pg, pm, va);
1415 pmap_vac_me_user(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1417 pmap_t kpmap = pmap_kernel();
1418 struct pv_entry *pv, *npv;
1419 struct l2_bucket *l2b;
1420 pt_entry_t *ptep, pte;
1423 u_int cacheable_entries = 0;
1424 u_int kern_cacheable = 0;
1425 u_int other_writable = 0;
1428 * Count mappings and writable mappings in this pmap.
1429 * Include kernel mappings as part of our own.
1430 * Keep a pointer to the first one.
1432 npv = TAILQ_FIRST(&pg->md.pv_list);
1433 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1434 /* Count mappings in the same pmap */
1435 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) {
1439 /* Cacheable mappings */
1440 if ((pv->pv_flags & PVF_NC) == 0) {
1441 cacheable_entries++;
1442 if (kpmap == pv->pv_pmap)
1446 /* Writable mappings */
1447 if (pv->pv_flags & PVF_WRITE)
1450 if (pv->pv_flags & PVF_WRITE)
1455 * Enable or disable caching as necessary.
1456 * Note: the first entry might be part of the kernel pmap,
1457 * so we can't assume this is indicative of the state of the
1458 * other (maybe non-kpmap) entries.
1460 if ((entries > 1 && writable) ||
1461 (entries > 0 && pm == kpmap && other_writable)) {
1462 if (cacheable_entries == 0)
1465 for (pv = npv; pv; pv = TAILQ_NEXT(pv, pv_list)) {
1466 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) ||
1467 (pv->pv_flags & PVF_NC))
1470 pv->pv_flags |= PVF_NC;
1472 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
1473 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
1474 pte = *ptep & ~L2_S_CACHE_MASK;
1476 if ((va != pv->pv_va || pm != pv->pv_pmap) &&
1478 if (PV_BEEN_EXECD(pv->pv_flags)) {
1479 pmap_idcache_wbinv_range(pv->pv_pmap,
1480 pv->pv_va, PAGE_SIZE);
1481 pmap_tlb_flushID_SE(pv->pv_pmap,
1484 if (PV_BEEN_REFD(pv->pv_flags)) {
1485 pmap_dcache_wb_range(pv->pv_pmap,
1486 pv->pv_va, PAGE_SIZE, TRUE,
1487 (pv->pv_flags & PVF_WRITE) == 0);
1488 pmap_tlb_flushD_SE(pv->pv_pmap,
1494 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
1498 if (entries > cacheable_entries) {
1500 * Turn cacheing back on for some pages. If it is a kernel
1501 * page, only do so if there are no other writable pages.
1503 for (pv = npv; pv; pv = TAILQ_NEXT(pv, pv_list)) {
1504 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap &&
1505 (kpmap != pv->pv_pmap || other_writable)))
1508 pv->pv_flags &= ~PVF_NC;
1510 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
1511 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
1512 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode;
1514 if (l2pte_valid(pte)) {
1515 if (PV_BEEN_EXECD(pv->pv_flags)) {
1516 pmap_tlb_flushID_SE(pv->pv_pmap,
1519 if (PV_BEEN_REFD(pv->pv_flags)) {
1520 pmap_tlb_flushD_SE(pv->pv_pmap,
1526 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
1532 * Modify pte bits for all ptes corresponding to the given physical address.
1533 * We use `maskbits' rather than `clearbits' because we're always passing
1534 * constants and the latter would require an extra inversion at run-time.
1537 pmap_clearbit(struct vm_page *pg, u_int maskbits)
1539 struct l2_bucket *l2b;
1540 struct pv_entry *pv;
1541 pt_entry_t *ptep, npte, opte;
1547 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1550 * Clear saved attributes (modify, reference)
1552 pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF));
1554 if (TAILQ_EMPTY(&pg->md.pv_list)) {
1559 * Loop over all current mappings setting/clearing as appropos
1561 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1564 oflags = pv->pv_flags;
1565 pv->pv_flags &= ~maskbits;
1569 l2b = pmap_get_l2_bucket(pm, va);
1571 ptep = &l2b->l2b_kva[l2pte_index(va)];
1572 npte = opte = *ptep;
1574 if (maskbits & (PVF_WRITE|PVF_MOD)) {
1575 if ((pv->pv_flags & PVF_NC)) {
1577 * Entry is not cacheable:
1579 * Don't turn caching on again if this is a
1580 * modified emulation. This would be
1581 * inconsitent with the settings created by
1582 * pmap_vac_me_harder(). Otherwise, it's safe
1583 * to re-enable cacheing.
1585 * There's no need to call pmap_vac_me_harder()
1586 * here: all pages are losing their write
1589 if (maskbits & PVF_WRITE) {
1590 npte |= pte_l2_s_cache_mode;
1591 pv->pv_flags &= ~PVF_NC;
1594 if (opte & L2_S_PROT_W) {
1597 * Entry is writable/cacheable: check if pmap
1598 * is current if it is flush it, otherwise it
1599 * won't be in the cache
1601 if (PV_BEEN_EXECD(oflags))
1602 pmap_idcache_wbinv_range(pm, pv->pv_va,
1605 if (PV_BEEN_REFD(oflags))
1606 pmap_dcache_wb_range(pm, pv->pv_va,
1608 (maskbits & PVF_REF) ? TRUE : FALSE,
1612 /* make the pte read only */
1613 npte &= ~L2_S_PROT_W;
1615 if (maskbits & PVF_WRITE) {
1617 * Keep alias accounting up to date
1619 if (pv->pv_pmap == pmap_kernel()) {
1620 if (oflags & PVF_WRITE) {
1621 pg->md.krw_mappings--;
1622 pg->md.kro_mappings++;
1625 if (oflags & PVF_WRITE) {
1626 pg->md.urw_mappings--;
1627 pg->md.uro_mappings++;
1632 if (maskbits & PVF_REF) {
1633 if ((pv->pv_flags & PVF_NC) == 0 &&
1634 (maskbits & (PVF_WRITE|PVF_MOD)) == 0) {
1636 * Check npte here; we may have already
1637 * done the wbinv above, and the validity
1638 * of the PTE is the same for opte and
1641 if (npte & L2_S_PROT_W) {
1642 if (PV_BEEN_EXECD(oflags))
1643 pmap_idcache_wbinv_range(pm,
1644 pv->pv_va, PAGE_SIZE);
1646 if (PV_BEEN_REFD(oflags))
1647 pmap_dcache_wb_range(pm,
1648 pv->pv_va, PAGE_SIZE,
1651 if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) {
1652 /* XXXJRT need idcache_inv_range */
1653 if (PV_BEEN_EXECD(oflags))
1654 pmap_idcache_wbinv_range(pm,
1655 pv->pv_va, PAGE_SIZE);
1657 if (PV_BEEN_REFD(oflags))
1658 pmap_dcache_wb_range(pm,
1659 pv->pv_va, PAGE_SIZE,
1665 * Make the PTE invalid so that we will take a
1666 * page fault the next time the mapping is
1669 npte &= ~L2_TYPE_MASK;
1670 npte |= L2_TYPE_INV;
1677 /* Flush the TLB entry if a current pmap. */
1678 if (PV_BEEN_EXECD(oflags))
1679 pmap_tlb_flushID_SE(pm, pv->pv_va);
1681 if (PV_BEEN_REFD(oflags))
1682 pmap_tlb_flushD_SE(pm, pv->pv_va);
1689 if (maskbits & PVF_WRITE)
1690 vm_page_flag_clear(pg, PG_WRITEABLE);
1695 * main pv_entry manipulation functions:
1696 * pmap_enter_pv: enter a mapping onto a vm_page list
1697 * pmap_remove_pv: remove a mappiing from a vm_page list
1699 * NOTE: pmap_enter_pv expects to lock the pvh itself
1700 * pmap_remove_pv expects te caller to lock the pvh before calling
1704 * pmap_enter_pv: enter a mapping onto a vm_page lst
1706 * => caller should hold the proper lock on pmap_main_lock
1707 * => caller should have pmap locked
1708 * => we will gain the lock on the vm_page and allocate the new pv_entry
1709 * => caller should adjust ptp's wire_count before calling
1710 * => caller should not adjust pmap's wire_count
1713 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm,
1714 vm_offset_t va, u_int flags)
1717 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1718 PMAP_ASSERT_LOCKED(pm);
1721 pve->pv_flags = flags;
1723 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list);
1724 TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist);
1725 pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD);
1726 if (pm == pmap_kernel()) {
1727 if (flags & PVF_WRITE)
1728 pg->md.krw_mappings++;
1730 pg->md.kro_mappings++;
1732 if (flags & PVF_WRITE)
1733 pg->md.urw_mappings++;
1735 pg->md.uro_mappings++;
1736 pg->md.pv_list_count++;
1737 if (pve->pv_flags & PVF_WIRED)
1738 ++pm->pm_stats.wired_count;
1739 vm_page_flag_set(pg, PG_REFERENCED);
1744 * pmap_find_pv: Find a pv entry
1746 * => caller should hold lock on vm_page
1748 static PMAP_INLINE struct pv_entry *
1749 pmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1751 struct pv_entry *pv;
1753 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1754 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list)
1755 if (pm == pv->pv_pmap && va == pv->pv_va)
1761 * vector_page_setprot:
1763 * Manipulate the protection of the vector page.
1766 vector_page_setprot(int prot)
1768 struct l2_bucket *l2b;
1771 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page);
1773 ptep = &l2b->l2b_kva[l2pte_index(vector_page)];
1775 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot);
1777 cpu_tlb_flushD_SE(vector_page);
1782 * pmap_remove_pv: try to remove a mapping from a pv_list
1784 * => caller should hold proper lock on pmap_main_lock
1785 * => pmap should be locked
1786 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1787 * => caller should adjust ptp's wire_count and free PTP if needed
1788 * => caller should NOT adjust pmap's wire_count
1789 * => we return the removed pve
1793 pmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve)
1796 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1797 PMAP_ASSERT_LOCKED(pm);
1798 TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list);
1799 TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist);
1800 if (pve->pv_flags & PVF_WIRED)
1801 --pm->pm_stats.wired_count;
1802 pg->md.pv_list_count--;
1803 if (pg->md.pvh_attrs & PVF_MOD)
1805 if (pm == pmap_kernel()) {
1806 if (pve->pv_flags & PVF_WRITE)
1807 pg->md.krw_mappings--;
1809 pg->md.kro_mappings--;
1811 if (pve->pv_flags & PVF_WRITE)
1812 pg->md.urw_mappings--;
1814 pg->md.uro_mappings--;
1815 if (TAILQ_FIRST(&pg->md.pv_list) == NULL ||
1816 (pg->md.krw_mappings == 0 && pg->md.urw_mappings == 0)) {
1817 pg->md.pvh_attrs &= ~PVF_MOD;
1818 if (TAILQ_FIRST(&pg->md.pv_list) == NULL)
1819 pg->md.pvh_attrs &= ~PVF_REF;
1820 vm_page_flag_clear(pg, PG_WRITEABLE);
1822 if (TAILQ_FIRST(&pg->md.pv_list))
1823 vm_page_flag_set(pg, PG_REFERENCED);
1824 if (pve->pv_flags & PVF_WRITE)
1825 pmap_vac_me_harder(pg, pm, 0);
1828 static struct pv_entry *
1829 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1831 struct pv_entry *pve;
1833 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1834 pve = TAILQ_FIRST(&pg->md.pv_list);
1837 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */
1838 pmap_nuke_pv(pg, pm, pve);
1841 pve = TAILQ_NEXT(pve, pv_list);
1844 return(pve); /* return removed pve */
1848 * pmap_modify_pv: Update pv flags
1850 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1851 * => caller should NOT adjust pmap's wire_count
1852 * => caller must call pmap_vac_me_harder() if writable status of a page
1854 * => we return the old flags
1856 * Modify a physical-virtual mapping in the pv table
1859 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va,
1860 u_int clr_mask, u_int set_mask)
1862 struct pv_entry *npv;
1863 u_int flags, oflags;
1865 PMAP_ASSERT_LOCKED(pm);
1866 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1867 if ((npv = pmap_find_pv(pg, pm, va)) == NULL)
1871 * There is at least one VA mapping this page.
1874 if (clr_mask & (PVF_REF | PVF_MOD))
1875 pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD);
1877 oflags = npv->pv_flags;
1878 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask;
1880 if ((flags ^ oflags) & PVF_WIRED) {
1881 if (flags & PVF_WIRED)
1882 ++pm->pm_stats.wired_count;
1884 --pm->pm_stats.wired_count;
1887 if ((flags ^ oflags) & PVF_WRITE) {
1888 if (pm == pmap_kernel()) {
1889 if (flags & PVF_WRITE) {
1890 pg->md.krw_mappings++;
1891 pg->md.kro_mappings--;
1893 pg->md.kro_mappings++;
1894 pg->md.krw_mappings--;
1897 if (flags & PVF_WRITE) {
1898 pg->md.urw_mappings++;
1899 pg->md.uro_mappings--;
1901 pg->md.uro_mappings++;
1902 pg->md.urw_mappings--;
1904 if (pg->md.krw_mappings == 0 && pg->md.urw_mappings == 0) {
1905 pg->md.pvh_attrs &= ~PVF_MOD;
1906 vm_page_flag_clear(pg, PG_WRITEABLE);
1908 pmap_vac_me_harder(pg, pm, 0);
1914 /* Function to set the debug level of the pmap code */
1917 pmap_debug(int level)
1919 pmap_debug_level = level;
1920 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
1922 #endif /* PMAP_DEBUG */
1925 pmap_pinit0(struct pmap *pmap)
1927 PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap));
1929 dprintf("pmap_pinit0: pmap = %08x, pm_pdir = %08x\n",
1930 (u_int32_t) pmap, (u_int32_t) pmap->pm_pdir);
1931 bcopy(kernel_pmap, pmap, sizeof(*pmap));
1932 bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx));
1933 PMAP_LOCK_INIT(pmap);
1937 * Initialize a vm_page's machine-dependent fields.
1940 pmap_page_init(vm_page_t m)
1943 TAILQ_INIT(&m->md.pv_list);
1944 m->md.pv_list_count = 0;
1948 * Initialize the pmap module.
1949 * Called by vm_init, to initialize any structures that the pmap
1950 * system needs to map virtual memory.
1955 int shpgperproc = PMAP_SHPGPERPROC;
1957 PDEBUG(1, printf("pmap_init: phys_start = %08x\n"));
1960 * init the pv free list
1962 pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL,
1963 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1965 * Now it is safe to enable pv_table recording.
1967 PDEBUG(1, printf("pmap_init: done!\n"));
1969 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1971 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
1972 pv_entry_high_water = 9 * (pv_entry_max / 10);
1973 l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor,
1974 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1975 l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable),
1976 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1977 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1979 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max);
1984 pmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user)
1986 struct l2_dtable *l2;
1987 struct l2_bucket *l2b;
1988 pd_entry_t *pl1pd, l1pd;
1989 pt_entry_t *ptep, pte;
1995 vm_page_lock_queues();
1999 * If there is no l2_dtable for this address, then the process
2000 * has no business accessing it.
2002 * Note: This will catch userland processes trying to access
2005 l2 = pm->pm_l2[L2_IDX(l1idx)];
2010 * Likewise if there is no L2 descriptor table
2012 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2013 if (l2b->l2b_kva == NULL)
2017 * Check the PTE itself.
2019 ptep = &l2b->l2b_kva[l2pte_index(va)];
2025 * Catch a userland access to the vector page mapped at 0x0
2027 if (user && (pte & L2_S_PROT_U) == 0)
2029 if (va == vector_page)
2034 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) {
2036 * This looks like a good candidate for "page modified"
2039 struct pv_entry *pv;
2042 /* Extract the physical address of the page */
2043 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) {
2046 /* Get the current flags for this page. */
2048 pv = pmap_find_pv(pg, pm, va);
2054 * Do the flags say this page is writable? If not then it
2055 * is a genuine write fault. If yes then the write fault is
2056 * our fault as we did not reflect the write access in the
2057 * PTE. Now we know a write has occurred we can correct this
2058 * and also set the modified bit
2060 if ((pv->pv_flags & PVF_WRITE) == 0) {
2064 pg->md.pvh_attrs |= PVF_REF | PVF_MOD;
2066 pv->pv_flags |= PVF_REF | PVF_MOD;
2069 * Re-enable write permissions for the page. No need to call
2070 * pmap_vac_me_harder(), since this is just a
2071 * modified-emulation fault, and the PVF_WRITE bit isn't
2072 * changing. We've already set the cacheable bits based on
2073 * the assumption that we can write to this page.
2075 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W;
2079 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) {
2081 * This looks like a good candidate for "page referenced"
2084 struct pv_entry *pv;
2087 /* Extract the physical address of the page */
2088 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL)
2090 /* Get the current flags for this page. */
2092 pv = pmap_find_pv(pg, pm, va);
2096 pg->md.pvh_attrs |= PVF_REF;
2097 pv->pv_flags |= PVF_REF;
2100 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO;
2106 * We know there is a valid mapping here, so simply
2107 * fix up the L1 if necessary.
2109 pl1pd = &pm->pm_l1->l1_kva[l1idx];
2110 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO;
2111 if (*pl1pd != l1pd) {
2119 * There are bugs in the rev K SA110. This is a check for one
2122 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 &&
2123 curcpu()->ci_arm_cpurev < 3) {
2124 /* Always current pmap */
2125 if (l2pte_valid(pte)) {
2126 extern int kernel_debug;
2127 if (kernel_debug & 1) {
2128 struct proc *p = curlwp->l_proc;
2129 printf("prefetch_abort: page is already "
2130 "mapped - pte=%p *pte=%08x\n", ptep, pte);
2131 printf("prefetch_abort: pc=%08lx proc=%p "
2132 "process=%s\n", va, p, p->p_comm);
2133 printf("prefetch_abort: far=%08x fs=%x\n",
2134 cpu_faultaddress(), cpu_faultstatus());
2137 if (kernel_debug & 2)
2143 #endif /* CPU_SA110 */
2147 * If 'rv == 0' at this point, it generally indicates that there is a
2148 * stale TLB entry for the faulting address. This happens when two or
2149 * more processes are sharing an L1. Since we don't flush the TLB on
2150 * a context switch between such processes, we can take domain faults
2151 * for mappings which exist at the same VA in both processes. EVEN IF
2152 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for
2155 * This is extremely likely to happen if pmap_enter() updated the L1
2156 * entry for a recently entered mapping. In this case, the TLB is
2157 * flushed for the new mapping, but there may still be TLB entries for
2158 * other mappings belonging to other processes in the 1MB range
2159 * covered by the L1 entry.
2161 * Since 'rv == 0', we know that the L1 already contains the correct
2162 * value, so the fault must be due to a stale TLB entry.
2164 * Since we always need to flush the TLB anyway in the case where we
2165 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with
2166 * stale TLB entries dynamically.
2168 * However, the above condition can ONLY happen if the current L1 is
2169 * being shared. If it happens when the L1 is unshared, it indicates
2170 * that other parts of the pmap are not doing their job WRT managing
2173 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) {
2174 extern int last_fault_code;
2175 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n",
2177 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n",
2178 l2, l2b, ptep, pl1pd);
2179 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n",
2180 pte, l1pd, last_fault_code);
2187 cpu_tlb_flushID_SE(va);
2193 vm_page_unlock_queues();
2201 struct l2_bucket *l2b;
2202 struct l1_ttable *l1;
2204 pt_entry_t *ptep, pte;
2205 vm_offset_t va, eva;
2208 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0);
2210 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK);
2212 for (loop = 0; loop < needed; loop++, l1++) {
2213 /* Allocate a L1 page table */
2214 va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0,
2215 0xffffffff, L1_TABLE_SIZE, 0);
2218 panic("Cannot allocate L1 KVM");
2220 eva = va + L1_TABLE_SIZE;
2221 pl1pt = (pd_entry_t *)va;
2224 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2225 ptep = &l2b->l2b_kva[l2pte_index(va)];
2227 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
2230 cpu_tlb_flushD_SE(va);
2234 pmap_init_l1(l1, pl1pt);
2239 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n",
2245 * This is used to stuff certain critical values into the PCB where they
2246 * can be accessed quickly from cpu_switch() et al.
2249 pmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb)
2251 struct l2_bucket *l2b;
2253 pcb->pcb_pagedir = pm->pm_l1->l1_physaddr;
2254 pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) |
2255 (DOMAIN_CLIENT << (pm->pm_domain * 2));
2257 if (vector_page < KERNBASE) {
2258 pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)];
2259 l2b = pmap_get_l2_bucket(pm, vector_page);
2260 pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO |
2261 L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL);
2263 pcb->pcb_pl1vec = NULL;
2267 pmap_activate(struct thread *td)
2272 pm = vmspace_pmap(td->td_proc->p_vmspace);
2276 pmap_set_pcb_pagedir(pm, pcb);
2278 if (td == curthread) {
2279 u_int cur_dacr, cur_ttb;
2281 __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb));
2282 __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr));
2284 cur_ttb &= ~(L1_TABLE_SIZE - 1);
2286 if (cur_ttb == (u_int)pcb->pcb_pagedir &&
2287 cur_dacr == pcb->pcb_dacr) {
2289 * No need to switch address spaces.
2297 * We MUST, I repeat, MUST fix up the L1 entry corresponding
2298 * to 'vector_page' in the incoming L1 table before switching
2299 * to it otherwise subsequent interrupts/exceptions (including
2300 * domain faults!) will jump into hyperspace.
2302 if (pcb->pcb_pl1vec) {
2304 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2306 * Don't need to PTE_SYNC() at this point since
2307 * cpu_setttb() is about to flush both the cache
2312 cpu_domains(pcb->pcb_dacr);
2313 cpu_setttb(pcb->pcb_pagedir);
2319 pmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va)
2321 pd_entry_t *pdep, pde;
2322 pt_entry_t *ptep, pte;
2327 * Make sure the descriptor itself has the correct cache mode
2329 pdep = &kl1[L1_IDX(va)];
2332 if (l1pte_section_p(pde)) {
2333 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) {
2334 *pdep = (pde & ~L1_S_CACHE_MASK) |
2335 pte_l1_s_cache_mode_pt;
2337 cpu_dcache_wbinv_range((vm_offset_t)pdep,
2342 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2343 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2345 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep);
2347 ptep = &ptep[l2pte_index(va)];
2349 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
2350 *ptep = (pte & ~L2_S_CACHE_MASK) |
2351 pte_l2_s_cache_mode_pt;
2353 cpu_dcache_wbinv_range((vm_offset_t)ptep,
2363 pmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap,
2366 vm_offset_t va = *availp;
2367 struct l2_bucket *l2b;
2370 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2372 panic("pmap_alloc_specials: no l2b for 0x%x", va);
2374 *ptep = &l2b->l2b_kva[l2pte_index(va)];
2378 *availp = va + (PAGE_SIZE * pages);
2382 * Bootstrap the system enough to run with virtual memory.
2384 * On the arm this is called after mapping has already been enabled
2385 * and just syncs the pmap module with what has already been done.
2386 * [We can't call it easily with mapping off since the kernel is not
2387 * mapped with PA == VA, hence we would have to relocate every address
2388 * from the linked base (virtual) address "KERNBASE" to the actual
2389 * (physical) address starting relative to 0]
2391 #define PMAP_STATIC_L2_SIZE 16
2392 #ifdef ARM_USE_SMALL_ALLOC
2393 extern struct mtx smallalloc_mtx;
2397 pmap_bootstrap(vm_offset_t firstaddr, vm_offset_t lastaddr, struct pv_addr *l1pt)
2399 static struct l1_ttable static_l1;
2400 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE];
2401 struct l1_ttable *l1 = &static_l1;
2402 struct l2_dtable *l2;
2403 struct l2_bucket *l2b;
2405 pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va;
2410 int l1idx, l2idx, l2next = 0;
2412 PDEBUG(1, printf("firstaddr = %08x, loadaddr = %08x\n",
2413 firstaddr, loadaddr));
2415 virtual_avail = firstaddr;
2416 kernel_pmap = &kernel_pmap_store;
2417 kernel_pmap->pm_l1 = l1;
2418 kernel_l1pa = l1pt->pv_pa;
2421 * Scan the L1 translation table created by initarm() and create
2422 * the required metadata for all valid mappings found in it.
2424 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) {
2425 pde = kernel_l1pt[l1idx];
2428 * We're only interested in Coarse mappings.
2429 * pmap_extract() can deal with section mappings without
2430 * recourse to checking L2 metadata.
2432 if ((pde & L1_TYPE_MASK) != L1_TYPE_C)
2436 * Lookup the KVA of this L2 descriptor table
2438 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2439 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2442 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx",
2443 (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa);
2447 * Fetch the associated L2 metadata structure.
2448 * Allocate a new one if necessary.
2450 if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) {
2451 if (l2next == PMAP_STATIC_L2_SIZE)
2452 panic("pmap_bootstrap: out of static L2s");
2453 kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 =
2454 &static_l2[l2next++];
2458 * One more L1 slot tracked...
2463 * Fill in the details of the L2 descriptor in the
2464 * appropriate bucket.
2466 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2467 l2b->l2b_kva = ptep;
2469 l2b->l2b_l1idx = l1idx;
2472 * Establish an initial occupancy count for this descriptor
2475 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
2477 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) {
2478 l2b->l2b_occupancy++;
2483 * Make sure the descriptor itself has the correct cache mode.
2484 * If not, fix it, but whine about the problem. Port-meisters
2485 * should consider this a clue to fix up their initarm()
2488 if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) {
2489 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2490 "L2 pte @ %p\n", ptep);
2496 * Ensure the primary (kernel) L1 has the correct cache mode for
2497 * a page table. Bitch if it is not correctly set.
2499 for (va = (vm_offset_t)kernel_l1pt;
2500 va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) {
2501 if (pmap_set_pt_cache_mode(kernel_l1pt, va))
2502 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2503 "primary L1 @ 0x%x\n", va);
2506 cpu_dcache_wbinv_all();
2510 PMAP_LOCK_INIT(kernel_pmap);
2511 kernel_pmap->pm_active = -1;
2512 kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL;
2513 TAILQ_INIT(&kernel_pmap->pm_pvlist);
2516 * Reserve some special page table entries/VA space for temporary
2519 #define SYSMAP(c, p, v, n) \
2520 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
2522 pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte);
2523 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte);
2524 pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte);
2525 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte);
2526 size = ((lastaddr - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE;
2527 pmap_alloc_specials(&virtual_avail,
2528 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE,
2529 &pmap_kernel_l2ptp_kva, NULL);
2531 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE;
2532 pmap_alloc_specials(&virtual_avail,
2533 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE,
2534 &pmap_kernel_l2dtable_kva, NULL);
2536 pmap_alloc_specials(&virtual_avail,
2537 1, (vm_offset_t*)&_tmppt, NULL);
2538 SLIST_INIT(&l1_list);
2539 TAILQ_INIT(&l1_lru_list);
2540 mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF);
2541 pmap_init_l1(l1, kernel_l1pt);
2542 cpu_dcache_wbinv_all();
2544 virtual_avail = round_page(virtual_avail);
2545 virtual_end = lastaddr;
2546 kernel_vm_end = pmap_curmaxkvaddr;
2547 arm_nocache_startaddr = lastaddr;
2548 mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF);
2550 #ifdef ARM_USE_SMALL_ALLOC
2551 mtx_init(&smallalloc_mtx, "Small alloc page list", NULL, MTX_DEF);
2552 arm_init_smallalloc();
2554 pmap_set_pcb_pagedir(kernel_pmap, thread0.td_pcb);
2557 /***************************************************
2558 * Pmap allocation/deallocation routines.
2559 ***************************************************/
2562 * Release any resources held by the given physical map.
2563 * Called when a pmap initialized by pmap_pinit is being released.
2564 * Should only be called if the map contains no valid mappings.
2567 pmap_release(pmap_t pmap)
2571 pmap_idcache_wbinv_all(pmap);
2572 pmap_tlb_flushID(pmap);
2574 if (vector_page < KERNBASE) {
2575 struct pcb *curpcb = PCPU_GET(curpcb);
2576 pcb = thread0.td_pcb;
2577 if (pmap_is_current(pmap)) {
2579 * Frob the L1 entry corresponding to the vector
2580 * page so that it contains the kernel pmap's domain
2581 * number. This will ensure pmap_remove() does not
2582 * pull the current vector page out from under us.
2585 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2586 cpu_domains(pcb->pcb_dacr);
2587 cpu_setttb(pcb->pcb_pagedir);
2590 pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE);
2592 * Make sure cpu_switch(), et al, DTRT. This is safe to do
2593 * since this process has no remaining mappings of its own.
2595 curpcb->pcb_pl1vec = pcb->pcb_pl1vec;
2596 curpcb->pcb_l1vec = pcb->pcb_l1vec;
2597 curpcb->pcb_dacr = pcb->pcb_dacr;
2598 curpcb->pcb_pagedir = pcb->pcb_pagedir;
2602 PMAP_LOCK_DESTROY(pmap);
2604 dprintf("pmap_release()\n");
2610 * Helper function for pmap_grow_l2_bucket()
2613 pmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap)
2615 struct l2_bucket *l2b;
2620 pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
2623 pa = VM_PAGE_TO_PHYS(pg);
2628 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2630 ptep = &l2b->l2b_kva[l2pte_index(va)];
2631 *ptep = L2_S_PROTO | pa | cache_mode |
2632 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE);
2638 * This is the same as pmap_alloc_l2_bucket(), except that it is only
2639 * used by pmap_growkernel().
2641 static __inline struct l2_bucket *
2642 pmap_grow_l2_bucket(pmap_t pm, vm_offset_t va)
2644 struct l2_dtable *l2;
2645 struct l2_bucket *l2b;
2646 struct l1_ttable *l1;
2653 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
2655 * No mapping at this address, as there is
2656 * no entry in the L1 table.
2657 * Need to allocate a new l2_dtable.
2659 nva = pmap_kernel_l2dtable_kva;
2660 if ((nva & PAGE_MASK) == 0) {
2662 * Need to allocate a backing page
2664 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2668 l2 = (struct l2_dtable *)nva;
2669 nva += sizeof(struct l2_dtable);
2671 if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva &
2674 * The new l2_dtable straddles a page boundary.
2675 * Map in another page to cover it.
2677 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2681 pmap_kernel_l2dtable_kva = nva;
2684 * Link it into the parent pmap
2686 pm->pm_l2[L2_IDX(l1idx)] = l2;
2687 memset(l2, 0, sizeof(*l2));
2690 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2693 * Fetch pointer to the L2 page table associated with the address.
2695 if (l2b->l2b_kva == NULL) {
2699 * No L2 page table has been allocated. Chances are, this
2700 * is because we just allocated the l2_dtable, above.
2702 nva = pmap_kernel_l2ptp_kva;
2703 ptep = (pt_entry_t *)nva;
2704 if ((nva & PAGE_MASK) == 0) {
2706 * Need to allocate a backing page
2708 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt,
2709 &pmap_kernel_l2ptp_phys))
2711 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t));
2713 memset(ptep, 0, L2_TABLE_SIZE_REAL);
2715 l2b->l2b_kva = ptep;
2716 l2b->l2b_l1idx = l1idx;
2717 l2b->l2b_phys = pmap_kernel_l2ptp_phys;
2719 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL;
2720 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL;
2723 /* Distribute new L1 entry to all other L1s */
2724 SLIST_FOREACH(l1, &l1_list, l1_link) {
2725 pl1pd = &l1->l1_kva[L1_IDX(va)];
2726 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) |
2736 * grow the number of kernel page table entries, if needed
2739 pmap_growkernel(vm_offset_t addr)
2741 pmap_t kpm = pmap_kernel();
2743 if (addr <= pmap_curmaxkvaddr)
2744 return; /* we are OK */
2747 * whoops! we need to add kernel PTPs
2750 /* Map 1MB at a time */
2751 for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE)
2752 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr);
2755 * flush out the cache, expensive but growkernel will happen so
2758 cpu_dcache_wbinv_all();
2761 kernel_vm_end = pmap_curmaxkvaddr;
2767 * Remove all pages from specified address space
2768 * this aids process exit speeds. Also, this code
2769 * is special cased for current process only, but
2770 * can have the more generic (and slightly slower)
2771 * mode enabled. This is much faster than pmap_remove
2772 * in the case of running down an entire address space.
2775 pmap_remove_pages(pmap_t pmap)
2777 struct pv_entry *pv, *npv;
2778 struct l2_bucket *l2b = NULL;
2782 vm_page_lock_queues();
2784 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) {
2785 if (pv->pv_flags & PVF_WIRED) {
2786 /* The page is wired, cannot remove it now. */
2787 npv = TAILQ_NEXT(pv, pv_plist);
2790 pmap->pm_stats.resident_count--;
2791 l2b = pmap_get_l2_bucket(pmap, pv->pv_va);
2792 KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages"));
2793 pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
2794 m = PHYS_TO_VM_PAGE(*pt & L2_ADDR_MASK);
2795 #ifdef ARM_USE_SMALL_ALLOC
2796 KASSERT((vm_offset_t)m >= alloc_firstaddr, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt));
2798 KASSERT((vm_offset_t)m >= KERNBASE, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt));
2802 npv = TAILQ_NEXT(pv, pv_plist);
2803 pmap_nuke_pv(m, pmap, pv);
2804 if (TAILQ_EMPTY(&m->md.pv_list))
2805 vm_page_flag_clear(m, PG_WRITEABLE);
2806 pmap_free_pv_entry(pv);
2807 pmap_free_l2_bucket(pmap, l2b, 1);
2809 vm_page_unlock_queues();
2810 cpu_idcache_wbinv_all();
2817 /***************************************************
2818 * Low level mapping routines.....
2819 ***************************************************/
2821 /* Map a super section into the KVA. */
2824 pmap_kenter_supersection(vm_offset_t va, uint64_t pa, int flags)
2826 pd_entry_t pd = L1_S_PROTO | L1_S_SUPERSEC | (pa & L1_SUP_OFFSET) |
2827 (((pa >> 32) & 0x8) << 20) | L1_S_PROT(PTE_KERNEL,
2828 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
2829 struct l1_ttable *l1;
2832 KASSERT(((va | pa) & L1_SUP_OFFSET) == 0,
2833 ("Not a valid section mapping"));
2834 if (flags & SECTION_CACHE)
2835 pd |= pte_l1_s_cache_mode;
2836 else if (flags & SECTION_PT)
2837 pd |= pte_l1_s_cache_mode_pt;
2838 va = va & L1_SUP_OFFSET;
2839 va_end = va + L1_SUP_SIZE;
2840 SLIST_FOREACH(l1, &l1_list, l1_link) {
2841 for (; va < va_end; va += L1_S_SIZE) {
2842 l1->l1_kva[L1_IDX(va)] = pd;
2843 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2849 /* Map a section into the KVA. */
2852 pmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags)
2854 pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL,
2855 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
2856 struct l1_ttable *l1;
2858 KASSERT(((va | pa) & L1_S_OFFSET) == 0,
2859 ("Not a valid section mapping"));
2860 if (flags & SECTION_CACHE)
2861 pd |= pte_l1_s_cache_mode;
2862 else if (flags & SECTION_PT)
2863 pd |= pte_l1_s_cache_mode_pt;
2864 SLIST_FOREACH(l1, &l1_list, l1_link) {
2865 l1->l1_kva[L1_IDX(va)] = pd;
2866 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2871 * add a wired page to the kva
2872 * note that in order for the mapping to take effect -- you
2873 * should do a invltlb after doing the pmap_kenter...
2875 static PMAP_INLINE void
2876 pmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags)
2878 struct l2_bucket *l2b;
2881 PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n",
2882 (uint32_t) va, (uint32_t) pa));
2885 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2887 l2b = pmap_grow_l2_bucket(pmap_kernel(), va);
2888 KASSERT(l2b != NULL, ("No L2 Bucket"));
2889 pte = &l2b->l2b_kva[l2pte_index(va)];
2891 PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n",
2892 (uint32_t) pte, opte, *pte));
2893 if (l2pte_valid(opte)) {
2894 cpu_dcache_wbinv_range(va, PAGE_SIZE);
2895 cpu_tlb_flushD_SE(va);
2899 l2b->l2b_occupancy++;
2901 *pte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL,
2902 VM_PROT_READ | VM_PROT_WRITE);
2903 if (flags & KENTER_CACHE)
2904 *pte |= pte_l2_s_cache_mode;
2905 if (flags & KENTER_USER)
2906 *pte |= L2_S_PROT_U;
2911 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2913 pmap_kenter_internal(va, pa, KENTER_CACHE);
2917 pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa)
2920 pmap_kenter_internal(va, pa, 0);
2924 pmap_kenter_user(vm_offset_t va, vm_paddr_t pa)
2927 pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER);
2929 * Call pmap_fault_fixup now, to make sure we'll have no exception
2930 * at the first use of the new address, or bad things will happen,
2931 * as we use one of these addresses in the exception handlers.
2933 pmap_fault_fixup(pmap_kernel(), va, VM_PROT_READ|VM_PROT_WRITE, 1);
2937 * remove a page rom the kernel pagetables
2940 pmap_kremove(vm_offset_t va)
2942 struct l2_bucket *l2b;
2943 pt_entry_t *pte, opte;
2945 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2948 KASSERT(l2b != NULL, ("No L2 Bucket"));
2949 pte = &l2b->l2b_kva[l2pte_index(va)];
2951 if (l2pte_valid(opte)) {
2952 cpu_dcache_wbinv_range(va, PAGE_SIZE);
2953 cpu_tlb_flushD_SE(va);
2961 * Used to map a range of physical addresses into kernel
2962 * virtual address space.
2964 * The value passed in '*virt' is a suggested virtual address for
2965 * the mapping. Architectures which can support a direct-mapped
2966 * physical to virtual region can return the appropriate address
2967 * within that region, leaving '*virt' unchanged. Other
2968 * architectures should map the pages starting at '*virt' and
2969 * update '*virt' with the first usable address after the mapped
2973 pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot)
2975 #ifdef ARM_USE_SMALL_ALLOC
2976 return (arm_ptovirt(start));
2978 vm_offset_t sva = *virt;
2979 vm_offset_t va = sva;
2981 PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, "
2982 "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end,
2985 while (start < end) {
2986 pmap_kenter(va, start);
2996 pmap_wb_page(vm_page_t m)
2998 struct pv_entry *pv;
3000 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
3001 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, FALSE,
3002 (pv->pv_flags & PVF_WRITE) == 0);
3006 pmap_inv_page(vm_page_t m)
3008 struct pv_entry *pv;
3010 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
3011 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, TRUE, TRUE);
3014 * Add a list of wired pages to the kva
3015 * this routine is only used for temporary
3016 * kernel mappings that do not need to have
3017 * page modification or references recorded.
3018 * Note that old mappings are simply written
3019 * over. The page *must* be wired.
3022 pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
3026 for (i = 0; i < count; i++) {
3028 pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]),
3036 * this routine jerks page mappings from the
3037 * kernel -- it is meant only for temporary mappings.
3040 pmap_qremove(vm_offset_t va, int count)
3045 for (i = 0; i < count; i++) {
3048 pmap_inv_page(PHYS_TO_VM_PAGE(pa));
3057 * pmap_object_init_pt preloads the ptes for a given object
3058 * into the specified pmap. This eliminates the blast of soft
3059 * faults on process startup and immediately after an mmap.
3062 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3063 vm_pindex_t pindex, vm_size_t size)
3066 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
3067 KASSERT(object->type == OBJT_DEVICE,
3068 ("pmap_object_init_pt: non-device object"));
3073 * pmap_is_prefaultable:
3075 * Return whether or not the specified virtual address is elgible
3079 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3084 if (!pmap_get_pde_pte(pmap, addr, &pde, &pte))
3086 KASSERT(pte != NULL, ("Valid mapping but no pte ?"));
3093 * Fetch pointers to the PDE/PTE for the given pmap/VA pair.
3094 * Returns TRUE if the mapping exists, else FALSE.
3096 * NOTE: This function is only used by a couple of arm-specific modules.
3097 * It is not safe to take any pmap locks here, since we could be right
3098 * in the middle of debugging the pmap anyway...
3100 * It is possible for this routine to return FALSE even though a valid
3101 * mapping does exist. This is because we don't lock, so the metadata
3102 * state may be inconsistent.
3104 * NOTE: We can return a NULL *ptp in the case where the L1 pde is
3105 * a "section" mapping.
3108 pmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp)
3110 struct l2_dtable *l2;
3111 pd_entry_t *pl1pd, l1pd;
3115 if (pm->pm_l1 == NULL)
3119 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx];
3122 if (l1pte_section_p(l1pd)) {
3127 if (pm->pm_l2 == NULL)
3130 l2 = pm->pm_l2[L2_IDX(l1idx)];
3133 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3137 *ptp = &ptep[l2pte_index(va)];
3142 * Routine: pmap_remove_all
3144 * Removes this physical page from
3145 * all physical maps in which it resides.
3146 * Reflects back modify bits to the pager.
3149 * Original versions of this routine were very
3150 * inefficient because they iteratively called
3151 * pmap_remove (slow...)
3154 pmap_remove_all(vm_page_t m)
3157 pt_entry_t *ptep, pte;
3158 struct l2_bucket *l2b;
3159 boolean_t flush = FALSE;
3163 #if defined(PMAP_DEBUG)
3165 * XXX this makes pmap_page_protect(NONE) illegal for non-managed
3168 if (m->flags & PG_FICTITIOUS) {
3169 panic("pmap_page_protect: illegal for unmanaged page, va: 0x%x", VM_PAGE_TO_PHYS(m));
3173 if (TAILQ_EMPTY(&m->md.pv_list))
3175 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3176 curpm = vmspace_pmap(curproc->p_vmspace);
3177 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3178 if (flush == FALSE && (pv->pv_pmap == curpm ||
3179 pv->pv_pmap == pmap_kernel()))
3181 PMAP_LOCK(pv->pv_pmap);
3182 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
3183 KASSERT(l2b != NULL, ("No l2 bucket"));
3184 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
3187 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
3188 pmap_free_l2_bucket(pv->pv_pmap, l2b, 1);
3189 if (pv->pv_flags & PVF_WIRED)
3190 pv->pv_pmap->pm_stats.wired_count--;
3191 pv->pv_pmap->pm_stats.resident_count--;
3192 flags |= pv->pv_flags;
3193 pmap_nuke_pv(m, pv->pv_pmap, pv);
3194 PMAP_UNLOCK(pv->pv_pmap);
3195 pmap_free_pv_entry(pv);
3199 if (PV_BEEN_EXECD(flags))
3200 pmap_tlb_flushID(curpm);
3202 pmap_tlb_flushD(curpm);
3204 vm_page_flag_clear(m, PG_WRITEABLE);
3209 * Set the physical protection on the
3210 * specified range of this map as requested.
3213 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3215 struct l2_bucket *l2b;
3216 pt_entry_t *ptep, pte;
3217 vm_offset_t next_bucket;
3221 if ((prot & VM_PROT_READ) == 0) {
3222 pmap_remove(pm, sva, eva);
3226 if (prot & VM_PROT_WRITE) {
3228 * If this is a read->write transition, just ignore it and let
3229 * vm_fault() take care of it later.
3234 vm_page_lock_queues();
3238 * OK, at this point, we know we're doing write-protect operation.
3239 * If the pmap is active, write-back the range.
3241 pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE);
3243 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1;
3247 next_bucket = L2_NEXT_BUCKET(sva);
3248 if (next_bucket > eva)
3251 l2b = pmap_get_l2_bucket(pm, sva);
3257 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3259 while (sva < next_bucket) {
3260 if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) {
3264 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
3265 pte &= ~L2_S_PROT_W;
3270 f = pmap_modify_pv(pg, pm, sva,
3272 pmap_vac_me_harder(pg, pm, sva);
3275 f = PVF_REF | PVF_EXEC;
3281 if (PV_BEEN_EXECD(f))
3282 pmap_tlb_flushID_SE(pm, sva);
3284 if (PV_BEEN_REFD(f))
3285 pmap_tlb_flushD_SE(pm, sva);
3295 if (PV_BEEN_EXECD(flags))
3296 pmap_tlb_flushID(pm);
3298 if (PV_BEEN_REFD(flags))
3299 pmap_tlb_flushD(pm);
3301 vm_page_unlock_queues();
3308 * Insert the given physical page (p) at
3309 * the specified virtual address (v) in the
3310 * target physical map with the protection requested.
3312 * If specified, the page will be wired down, meaning
3313 * that the related pte can not be reclaimed.
3315 * NB: This is the only routine which MAY NOT lazy-evaluate
3316 * or lose information. That is, this routine must actually
3317 * insert this page into the given map NOW.
3321 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3325 vm_page_lock_queues();
3327 pmap_enter_locked(pmap, va, m, prot, wired, M_WAITOK);
3328 vm_page_unlock_queues();
3333 * The page queues and pmap must be locked.
3336 pmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3337 boolean_t wired, int flags)
3339 struct l2_bucket *l2b = NULL;
3340 struct vm_page *opg;
3341 struct pv_entry *pve = NULL;
3342 pt_entry_t *ptep, npte, opte;
3347 PMAP_ASSERT_LOCKED(pmap);
3348 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3349 if (va == vector_page) {
3350 pa = systempage.pv_pa;
3353 pa = VM_PAGE_TO_PHYS(m);
3355 if (prot & VM_PROT_WRITE)
3356 nflags |= PVF_WRITE;
3357 if (prot & VM_PROT_EXECUTE)
3360 nflags |= PVF_WIRED;
3361 PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, "
3362 "wired = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, wired));
3364 if (pmap == pmap_kernel()) {
3365 l2b = pmap_get_l2_bucket(pmap, va);
3367 l2b = pmap_grow_l2_bucket(pmap, va);
3370 l2b = pmap_alloc_l2_bucket(pmap, va);
3372 if (flags & M_WAITOK) {
3374 vm_page_unlock_queues();
3376 vm_page_lock_queues();
3384 ptep = &l2b->l2b_kva[l2pte_index(va)];
3391 * There is already a mapping at this address.
3392 * If the physical address is different, lookup the
3395 if (l2pte_pa(opte) != pa)
3396 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte));
3402 if ((prot & (VM_PROT_ALL)) ||
3403 (!m || m->md.pvh_attrs & PVF_REF)) {
3405 * - The access type indicates that we don't need
3406 * to do referenced emulation.
3408 * - The physical page has already been referenced
3409 * so no need to re-do referenced emulation here.
3415 if (m && ((prot & VM_PROT_WRITE) != 0 ||
3416 (m->md.pvh_attrs & PVF_MOD))) {
3418 * This is a writable mapping, and the
3419 * page's mod state indicates it has
3420 * already been modified. Make it
3421 * writable from the outset.
3424 if (!(m->md.pvh_attrs & PVF_MOD))
3428 vm_page_flag_set(m, PG_REFERENCED);
3431 * Need to do page referenced emulation.
3433 npte |= L2_TYPE_INV;
3436 if (prot & VM_PROT_WRITE) {
3437 npte |= L2_S_PROT_W;
3439 vm_page_flag_set(m, PG_WRITEABLE);
3441 npte |= pte_l2_s_cache_mode;
3442 if (m && m == opg) {
3444 * We're changing the attrs of an existing mapping.
3446 oflags = pmap_modify_pv(m, pmap, va,
3447 PVF_WRITE | PVF_EXEC | PVF_WIRED |
3448 PVF_MOD | PVF_REF, nflags);
3451 * We may need to flush the cache if we're
3454 if (pmap_is_current(pmap) &&
3455 (oflags & PVF_NC) == 0 &&
3456 (opte & L2_S_PROT_W) != 0 &&
3457 (prot & VM_PROT_WRITE) == 0)
3458 cpu_dcache_wb_range(va, PAGE_SIZE);
3461 * New mapping, or changing the backing page
3462 * of an existing mapping.
3466 * Replacing an existing mapping with a new one.
3467 * It is part of our managed memory so we
3468 * must remove it from the PV list
3470 pve = pmap_remove_pv(opg, pmap, va);
3471 if (m && (m->flags & (PG_UNMANAGED | PG_FICTITIOUS)) &&
3473 pmap_free_pv_entry(pve);
3475 !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS)))
3476 pve = pmap_get_pv_entry();
3477 KASSERT(pve != NULL || m->flags & (PG_UNMANAGED |
3478 PG_FICTITIOUS), ("No pv"));
3479 oflags = pve->pv_flags;
3482 * If the old mapping was valid (ref/mod
3483 * emulation creates 'invalid' mappings
3484 * initially) then make sure to frob
3487 if ((oflags & PVF_NC) == 0 &&
3488 l2pte_valid(opte)) {
3489 if (PV_BEEN_EXECD(oflags)) {
3490 pmap_idcache_wbinv_range(pmap, va,
3493 if (PV_BEEN_REFD(oflags)) {
3494 pmap_dcache_wb_range(pmap, va,
3496 (oflags & PVF_WRITE) == 0);
3499 } else if (m && !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS)))
3500 if ((pve = pmap_get_pv_entry()) == NULL) {
3501 panic("pmap_enter: no pv entries");
3503 if (m && !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS))) {
3504 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3505 ("pmap_enter: managed mapping within the clean submap"));
3506 pmap_enter_pv(m, pve, pmap, va, nflags);
3510 * Make sure userland mappings get the right permissions
3512 if (pmap != pmap_kernel() && va != vector_page) {
3513 npte |= L2_S_PROT_U;
3517 * Keep the stats up to date
3520 l2b->l2b_occupancy++;
3521 pmap->pm_stats.resident_count++;
3526 * If this is just a wiring change, the two PTEs will be
3527 * identical, so there's no need to update the page table.
3530 boolean_t is_cached = pmap_is_current(pmap);
3535 * We only need to frob the cache/tlb if this pmap
3539 if (L1_IDX(va) != L1_IDX(vector_page) &&
3540 l2pte_valid(npte)) {
3542 * This mapping is likely to be accessed as
3543 * soon as we return to userland. Fix up the
3544 * L1 entry to avoid taking another
3545 * page/domain fault.
3547 pd_entry_t *pl1pd, l1pd;
3549 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
3550 l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) |
3552 if (*pl1pd != l1pd) {
3559 if (PV_BEEN_EXECD(oflags))
3560 pmap_tlb_flushID_SE(pmap, va);
3561 else if (PV_BEEN_REFD(oflags))
3562 pmap_tlb_flushD_SE(pmap, va);
3566 pmap_vac_me_harder(m, pmap, va);
3571 * Maps a sequence of resident pages belonging to the same object.
3572 * The sequence begins with the given page m_start. This page is
3573 * mapped at the given virtual address start. Each subsequent page is
3574 * mapped at a virtual address that is offset from start by the same
3575 * amount as the page is offset from m_start within the object. The
3576 * last page in the sequence is the page with the largest offset from
3577 * m_start that can be mapped at a virtual address less than the given
3578 * virtual address end. Not every virtual page between start and end
3579 * is mapped; only those for which a resident page exists with the
3580 * corresponding offset from m_start are mapped.
3583 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3584 vm_page_t m_start, vm_prot_t prot)
3587 vm_pindex_t diff, psize;
3589 psize = atop(end - start);
3592 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3593 pmap_enter_locked(pmap, start + ptoa(diff), m, prot &
3594 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE, M_NOWAIT);
3595 m = TAILQ_NEXT(m, listq);
3601 * this code makes some *MAJOR* assumptions:
3602 * 1. Current pmap & pmap exists.
3605 * 4. No page table pages.
3606 * but is *MUCH* faster than pmap_enter...
3610 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3614 pmap_enter_locked(pmap, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
3620 * Routine: pmap_change_wiring
3621 * Function: Change the wiring attribute for a map/virtual-address
3623 * In/out conditions:
3624 * The mapping must already exist in the pmap.
3627 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
3629 struct l2_bucket *l2b;
3630 pt_entry_t *ptep, pte;
3633 vm_page_lock_queues();
3635 l2b = pmap_get_l2_bucket(pmap, va);
3636 KASSERT(l2b, ("No l2b bucket in pmap_change_wiring"));
3637 ptep = &l2b->l2b_kva[l2pte_index(va)];
3639 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
3641 pmap_modify_pv(pg, pmap, va, PVF_WIRED, wired);
3642 vm_page_unlock_queues();
3648 * Copy the range specified by src_addr/len
3649 * from the source map to the range dst_addr/len
3650 * in the destination map.
3652 * This routine is only advisory and need not do anything.
3655 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
3656 vm_size_t len, vm_offset_t src_addr)
3662 * Routine: pmap_extract
3664 * Extract the physical page address associated
3665 * with the given map/virtual_address pair.
3668 pmap_extract(pmap_t pm, vm_offset_t va)
3670 struct l2_dtable *l2;
3672 pt_entry_t *ptep, pte;
3678 l1pd = pm->pm_l1->l1_kva[l1idx];
3679 if (l1pte_section_p(l1pd)) {
3681 * These should only happen for pmap_kernel()
3683 KASSERT(pm == pmap_kernel(), ("huh"));
3684 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3687 * Note that we can't rely on the validity of the L1
3688 * descriptor as an indication that a mapping exists.
3689 * We have to look it up in the L2 dtable.
3691 l2 = pm->pm_l2[L2_IDX(l1idx)];
3694 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3699 ptep = &ptep[l2pte_index(va)];
3707 switch (pte & L2_TYPE_MASK) {
3709 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3713 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3723 * Atomically extract and hold the physical page with the given
3724 * pmap and virtual address pair if that mapping permits the given
3729 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3731 struct l2_dtable *l2;
3733 pt_entry_t *ptep, pte;
3739 vm_page_lock_queues();
3741 l1pd = pmap->pm_l1->l1_kva[l1idx];
3742 if (l1pte_section_p(l1pd)) {
3744 * These should only happen for pmap_kernel()
3746 KASSERT(pmap == pmap_kernel(), ("huh"));
3747 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3748 if (l1pd & L1_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3749 m = PHYS_TO_VM_PAGE(pa);
3755 * Note that we can't rely on the validity of the L1
3756 * descriptor as an indication that a mapping exists.
3757 * We have to look it up in the L2 dtable.
3759 l2 = pmap->pm_l2[L2_IDX(l1idx)];
3762 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3764 vm_page_unlock_queues();
3768 ptep = &ptep[l2pte_index(va)];
3773 vm_page_unlock_queues();
3776 if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3777 switch (pte & L2_TYPE_MASK) {
3779 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3783 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3786 m = PHYS_TO_VM_PAGE(pa);
3792 vm_page_unlock_queues();
3797 * Initialize a preallocated and zeroed pmap structure,
3798 * such as one in a vmspace structure.
3802 pmap_pinit(pmap_t pmap)
3804 PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap));
3806 PMAP_LOCK_INIT(pmap);
3807 pmap_alloc_l1(pmap);
3808 bzero(pmap->pm_l2, sizeof(pmap->pm_l2));
3811 pmap->pm_active = 0;
3813 TAILQ_INIT(&pmap->pm_pvlist);
3814 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3815 pmap->pm_stats.resident_count = 1;
3816 if (vector_page < KERNBASE) {
3817 pmap_enter(pmap, vector_page, PHYS_TO_VM_PAGE(systempage.pv_pa),
3823 /***************************************************
3824 * page management routines.
3825 ***************************************************/
3829 pmap_free_pv_entry(pv_entry_t pv)
3832 uma_zfree(pvzone, pv);
3837 * get a new pv_entry, allocating a block from the system
3839 * the memory allocation is performed bypassing the malloc code
3840 * because of the possibility of allocations at interrupt time.
3843 pmap_get_pv_entry(void)
3845 pv_entry_t ret_value;
3848 if (pv_entry_count > pv_entry_high_water)
3849 pagedaemon_wakeup();
3850 ret_value = uma_zalloc(pvzone, M_NOWAIT);
3856 * Remove the given range of addresses from the specified map.
3858 * It is assumed that the start and end are properly
3859 * rounded to the page size.
3861 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3
3863 pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva)
3865 struct l2_bucket *l2b;
3866 vm_offset_t next_bucket;
3868 u_int cleanlist_idx, total, cnt;
3872 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE];
3873 u_int mappings, is_exec, is_refd;
3878 * we lock in the pmap => pv_head direction
3881 vm_page_lock_queues();
3883 if (!pmap_is_current(pm)) {
3884 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1;
3891 * Do one L2 bucket's worth at a time.
3893 next_bucket = L2_NEXT_BUCKET(sva);
3894 if (next_bucket > eva)
3897 l2b = pmap_get_l2_bucket(pm, sva);
3903 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3906 while (sva < next_bucket) {
3915 * Nothing here, move along
3922 pm->pm_stats.resident_count--;
3928 * Update flags. In a number of circumstances,
3929 * we could cluster a lot of these and do a
3930 * number of sequential pages in one go.
3932 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) {
3933 struct pv_entry *pve;
3935 pve = pmap_remove_pv(pg, pm, sva);
3937 is_exec = PV_BEEN_EXECD(pve->pv_flags);
3938 is_refd = PV_BEEN_REFD(pve->pv_flags);
3939 pmap_free_pv_entry(pve);
3943 if (!l2pte_valid(pte)) {
3945 PTE_SYNC_CURRENT(pm, ptep);
3952 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) {
3953 /* Add to the clean list. */
3954 cleanlist[cleanlist_idx].pte = ptep;
3955 cleanlist[cleanlist_idx].va =
3956 sva | (is_exec & 1);
3959 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) {
3960 /* Nuke everything if needed. */
3961 pmap_idcache_wbinv_all(pm);
3962 pmap_tlb_flushID(pm);
3965 * Roll back the previous PTE list,
3966 * and zero out the current PTE.
3969 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) {
3970 *cleanlist[cnt].pte = 0;
3980 pmap_tlb_flushID_SE(pm, sva);
3983 pmap_tlb_flushD_SE(pm, sva);
3992 * Deal with any left overs
3994 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) {
3995 total += cleanlist_idx;
3996 for (cnt = 0; cnt < cleanlist_idx; cnt++) {
3998 cleanlist[cnt].va & ~1;
3999 if (cleanlist[cnt].va & 1) {
4000 pmap_idcache_wbinv_range(pm,
4002 pmap_tlb_flushID_SE(pm, clva);
4004 pmap_dcache_wb_range(pm,
4005 clva, PAGE_SIZE, TRUE,
4007 pmap_tlb_flushD_SE(pm, clva);
4009 *cleanlist[cnt].pte = 0;
4010 PTE_SYNC_CURRENT(pm, cleanlist[cnt].pte);
4013 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE)
4017 * We are removing so much entries it's just
4018 * easier to flush the whole cache.
4020 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1;
4021 pmap_idcache_wbinv_all(pm);
4026 pmap_free_l2_bucket(pm, l2b, mappings);
4029 vm_page_unlock_queues();
4041 * Zero a given physical page by mapping it at a page hook point.
4042 * In doing the zero page op, the page we zero is mapped cachable, as with
4043 * StrongARM accesses to non-cached pages are non-burst making writing
4044 * _any_ bulk data very slow.
4046 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_CORE3)
4048 pmap_zero_page_generic(vm_paddr_t phys, int off, int size)
4050 #ifdef ARM_USE_SMALL_ALLOC
4055 struct vm_page *pg = PHYS_TO_VM_PAGE(phys);
4057 if (pg->md.pvh_list != NULL)
4058 panic("pmap_zero_page: page has mappings");
4062 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0)
4065 #ifdef ARM_USE_SMALL_ALLOC
4066 dstpg = (char *)arm_ptovirt(phys);
4067 if (off || size != PAGE_SIZE) {
4068 bzero(dstpg + off, size);
4069 cpu_dcache_wbinv_range((vm_offset_t)(dstpg + off), size);
4071 bzero_page((vm_offset_t)dstpg);
4072 cpu_dcache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE);
4078 * Hook in the page, zero it, and purge the cache for that
4079 * zeroed page. Invalidate the TLB as needed.
4081 *cdst_pte = L2_S_PROTO | phys |
4082 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
4084 cpu_tlb_flushD_SE(cdstp);
4086 if (off || size != PAGE_SIZE) {
4087 bzero((void *)(cdstp + off), size);
4088 cpu_dcache_wbinv_range(cdstp + off, size);
4091 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE);
4096 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
4098 #if ARM_MMU_XSCALE == 1
4100 pmap_zero_page_xscale(vm_paddr_t phys, int off, int size)
4103 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0)
4107 * Hook in the page, zero it, and purge the cache for that
4108 * zeroed page. Invalidate the TLB as needed.
4110 *cdst_pte = L2_S_PROTO | phys |
4111 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4112 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4114 cpu_tlb_flushD_SE(cdstp);
4116 if (off || size != PAGE_SIZE)
4117 bzero((void *)(cdstp + off), size);
4121 xscale_cache_clean_minidata();
4125 * Change the PTEs for the specified kernel mappings such that they
4126 * will use the mini data cache instead of the main data cache.
4129 pmap_use_minicache(vm_offset_t va, vm_size_t size)
4131 struct l2_bucket *l2b;
4132 pt_entry_t *ptep, *sptep, pte;
4133 vm_offset_t next_bucket, eva;
4135 #if (ARM_NMMUS > 1) || defined(CPU_XSCALE_CORE3)
4136 if (xscale_use_minidata == 0)
4143 next_bucket = L2_NEXT_BUCKET(va);
4144 if (next_bucket > eva)
4147 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
4149 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)];
4151 while (va < next_bucket) {
4153 if (!l2pte_minidata(pte)) {
4154 cpu_dcache_wbinv_range(va, PAGE_SIZE);
4155 cpu_tlb_flushD_SE(va);
4156 *ptep = pte & ~L2_B;
4161 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep));
4165 #endif /* ARM_MMU_XSCALE == 1 */
4168 * pmap_zero_page zeros the specified hardware page by mapping
4169 * the page into KVM and using bzero to clear its contents.
4172 pmap_zero_page(vm_page_t m)
4174 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), 0, PAGE_SIZE);
4179 * pmap_zero_page_area zeros the specified hardware page by mapping
4180 * the page into KVM and using bzero to clear its contents.
4182 * off and size may not cover an area beyond a single hardware page.
4185 pmap_zero_page_area(vm_page_t m, int off, int size)
4188 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), off, size);
4193 * pmap_zero_page_idle zeros the specified hardware page by mapping
4194 * the page into KVM and using bzero to clear its contents. This
4195 * is intended to be called from the vm_pagezero process only and
4199 pmap_zero_page_idle(vm_page_t m)
4209 * This is a local function used to work out the best strategy to clean
4210 * a single page referenced by its entry in the PV table. It's used by
4211 * pmap_copy_page, pmap_zero page and maybe some others later on.
4213 * Its policy is effectively:
4214 * o If there are no mappings, we don't bother doing anything with the cache.
4215 * o If there is one mapping, we clean just that page.
4216 * o If there are multiple mappings, we clean the entire cache.
4218 * So that some functions can be further optimised, it returns 0 if it didn't
4219 * clean the entire cache, or 1 if it did.
4221 * XXX One bug in this routine is that if the pv_entry has a single page
4222 * mapped at 0x00000000 a whole cache clean will be performed rather than
4223 * just the 1 page. Since this should not occur in everyday use and if it does
4224 * it will just result in not the most efficient clean for the page.
4227 pmap_clean_page(struct pv_entry *pv, boolean_t is_src)
4229 pmap_t pm, pm_to_clean = NULL;
4230 struct pv_entry *npv;
4231 u_int cache_needs_cleaning = 0;
4233 vm_offset_t page_to_clean = 0;
4236 /* nothing mapped in so nothing to flush */
4241 * Since we flush the cache each time we change to a different
4242 * user vmspace, we only need to flush the page if it is in the
4246 pm = vmspace_pmap(curproc->p_vmspace);
4250 for (npv = pv; npv; npv = TAILQ_NEXT(npv, pv_list)) {
4251 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) {
4252 flags |= npv->pv_flags;
4254 * The page is mapped non-cacheable in
4255 * this map. No need to flush the cache.
4257 if (npv->pv_flags & PVF_NC) {
4259 if (cache_needs_cleaning)
4260 panic("pmap_clean_page: "
4261 "cache inconsistency");
4264 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0)
4266 if (cache_needs_cleaning) {
4270 page_to_clean = npv->pv_va;
4271 pm_to_clean = npv->pv_pmap;
4273 cache_needs_cleaning = 1;
4276 if (page_to_clean) {
4277 if (PV_BEEN_EXECD(flags))
4278 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean,
4281 pmap_dcache_wb_range(pm_to_clean, page_to_clean,
4282 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0);
4283 } else if (cache_needs_cleaning) {
4284 if (PV_BEEN_EXECD(flags))
4285 pmap_idcache_wbinv_all(pm);
4287 pmap_dcache_wbinv_all(pm);
4295 * pmap_copy_page copies the specified (machine independent)
4296 * page by mapping the page into virtual memory and using
4297 * bcopy to copy the page, one machine dependent page at a
4304 * Copy one physical page into another, by mapping the pages into
4305 * hook points. The same comment regarding cachability as in
4306 * pmap_zero_page also applies here.
4308 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined (CPU_XSCALE_CORE3)
4310 pmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst)
4313 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4316 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst);
4318 if (dst_pg->md.pvh_list != NULL)
4319 panic("pmap_copy_page: dst page has mappings");
4324 * Clean the source page. Hold the source page's lock for
4325 * the duration of the copy so that no other mappings can
4326 * be created while we have a potentially aliased mapping.
4330 * XXX: Not needed while we call cpu_dcache_wbinv_all() in
4333 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4336 * Map the pages into the page hook points, copy them, and purge
4337 * the cache for the appropriate page. Invalidate the TLB
4341 *csrc_pte = L2_S_PROTO | src |
4342 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
4344 *cdst_pte = L2_S_PROTO | dst |
4345 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
4347 cpu_tlb_flushD_SE(csrcp);
4348 cpu_tlb_flushD_SE(cdstp);
4350 bcopy_page(csrcp, cdstp);
4352 cpu_dcache_inv_range(csrcp, PAGE_SIZE);
4353 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE);
4355 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
4357 #if ARM_MMU_XSCALE == 1
4359 pmap_copy_page_xscale(vm_paddr_t src, vm_paddr_t dst)
4362 /* XXX: Only needed for pmap_clean_page(), which is commented out. */
4363 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4366 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst);
4368 if (dst_pg->md.pvh_list != NULL)
4369 panic("pmap_copy_page: dst page has mappings");
4374 * Clean the source page. Hold the source page's lock for
4375 * the duration of the copy so that no other mappings can
4376 * be created while we have a potentially aliased mapping.
4380 * XXX: Not needed while we call cpu_dcache_wbinv_all() in
4383 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4386 * Map the pages into the page hook points, copy them, and purge
4387 * the cache for the appropriate page. Invalidate the TLB
4391 *csrc_pte = L2_S_PROTO | src |
4392 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
4393 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4395 *cdst_pte = L2_S_PROTO | dst |
4396 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4397 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4399 cpu_tlb_flushD_SE(csrcp);
4400 cpu_tlb_flushD_SE(cdstp);
4402 bcopy_page(csrcp, cdstp);
4404 xscale_cache_clean_minidata();
4406 #endif /* ARM_MMU_XSCALE == 1 */
4409 pmap_copy_page(vm_page_t src, vm_page_t dst)
4411 #ifdef ARM_USE_SMALL_ALLOC
4412 vm_offset_t srcpg, dstpg;
4415 cpu_dcache_wbinv_all();
4417 _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst),
4418 (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0)
4420 #ifdef ARM_USE_SMALL_ALLOC
4421 srcpg = arm_ptovirt(VM_PAGE_TO_PHYS(src));
4422 dstpg = arm_ptovirt(VM_PAGE_TO_PHYS(dst));
4423 bcopy_page(srcpg, dstpg);
4424 cpu_dcache_wbinv_range(dstpg, PAGE_SIZE);
4426 pmap_copy_page_func(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst));
4434 * this routine returns true if a physical page resides
4435 * in the given pmap.
4438 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4443 if (m->flags & PG_FICTITIOUS)
4447 * Not found, check current mappings returning immediately
4449 for (pv = TAILQ_FIRST(&m->md.pv_list);
4451 pv = TAILQ_NEXT(pv, pv_list)) {
4452 if (pv->pv_pmap == pmap) {
4464 * pmap_ts_referenced:
4466 * Return the count of reference bits for a page, clearing all of them.
4469 pmap_ts_referenced(vm_page_t m)
4472 if (m->flags & PG_FICTITIOUS)
4474 return (pmap_clearbit(m, PVF_REF));
4479 pmap_is_modified(vm_page_t m)
4482 if (m->md.pvh_attrs & PVF_MOD)
4490 * Clear the modify bits on the specified physical page.
4493 pmap_clear_modify(vm_page_t m)
4496 if (m->md.pvh_attrs & PVF_MOD)
4497 pmap_clearbit(m, PVF_MOD);
4502 * pmap_clear_reference:
4504 * Clear the reference bit on the specified physical page.
4507 pmap_clear_reference(vm_page_t m)
4510 if (m->md.pvh_attrs & PVF_REF)
4511 pmap_clearbit(m, PVF_REF);
4516 * Clear the write and modified bits in each of the given page's mappings.
4519 pmap_remove_write(vm_page_t m)
4522 if (m->flags & PG_WRITEABLE)
4523 pmap_clearbit(m, PVF_WRITE);
4528 * perform the pmap work for mincore
4531 pmap_mincore(pmap_t pmap, vm_offset_t addr)
4533 printf("pmap_mincore()\n");
4540 pmap_addr_hint(vm_object_t obj, vm_offset_t addr, vm_size_t size)
4548 * Map a set of physical memory pages into the kernel virtual
4549 * address space. Return a pointer to where it is mapped. This
4550 * routine is intended to be used for mapping device memory,
4554 pmap_mapdev(vm_offset_t pa, vm_size_t size)
4556 vm_offset_t va, tmpva, offset;
4558 offset = pa & PAGE_MASK;
4559 size = roundup(size, PAGE_SIZE);
4563 va = kmem_alloc_nofault(kernel_map, size);
4565 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
4566 for (tmpva = va; size > 0;) {
4567 pmap_kenter_internal(tmpva, pa, 0);
4573 return ((void *)(va + offset));
4576 #define BOOTSTRAP_DEBUG
4581 * Create a single section mapping.
4584 pmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4585 int prot, int cache)
4587 pd_entry_t *pde = (pd_entry_t *) l1pt;
4590 KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2"));
4599 fl = pte_l1_s_cache_mode;
4603 fl = pte_l1_s_cache_mode_pt;
4607 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4608 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL);
4609 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4616 * Link the L2 page table specified by l2pv.pv_pa into the L1
4617 * page table at the slot for "va".
4620 pmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv)
4622 pd_entry_t *pde = (pd_entry_t *) l1pt, proto;
4623 u_int slot = va >> L1_S_SHIFT;
4625 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO;
4627 #ifdef VERBOSE_INIT_ARM
4628 printf("pmap_link_l2pt: pa=0x%x va=0x%x\n", l2pv->pv_pa, l2pv->pv_va);
4631 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000);
4633 PTE_SYNC(&pde[slot]);
4635 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list);
4643 * Create a single page mapping.
4646 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot,
4649 pd_entry_t *pde = (pd_entry_t *) l1pt;
4653 KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin"));
4662 fl = pte_l2_s_cache_mode;
4666 fl = pte_l2_s_cache_mode_pt;
4670 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4671 panic("pmap_map_entry: no L2 table for VA 0x%08x", va);
4673 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4676 panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va);
4678 pte[l2pte_index(va)] =
4679 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl;
4680 PTE_SYNC(&pte[l2pte_index(va)]);
4686 * Map a chunk of memory using the most efficient mappings
4687 * possible (section. large page, small page) into the
4688 * provided L1 and L2 tables at the specified virtual address.
4691 pmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4692 vm_size_t size, int prot, int cache)
4694 pd_entry_t *pde = (pd_entry_t *) l1pt;
4695 pt_entry_t *pte, f1, f2s, f2l;
4699 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
4702 panic("pmap_map_chunk: no L1 table provided");
4704 #ifdef VERBOSE_INIT_ARM
4705 printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x "
4706 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache);
4718 f1 = pte_l1_s_cache_mode;
4719 f2l = pte_l2_l_cache_mode;
4720 f2s = pte_l2_s_cache_mode;
4724 f1 = pte_l1_s_cache_mode_pt;
4725 f2l = pte_l2_l_cache_mode_pt;
4726 f2s = pte_l2_s_cache_mode_pt;
4733 /* See if we can use a section mapping. */
4734 if (L1_S_MAPPABLE_P(va, pa, resid)) {
4735 #ifdef VERBOSE_INIT_ARM
4738 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4739 L1_S_PROT(PTE_KERNEL, prot) | f1 |
4740 L1_S_DOM(PMAP_DOMAIN_KERNEL);
4741 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4749 * Ok, we're going to use an L2 table. Make sure
4750 * one is actually in the corresponding L1 slot
4751 * for the current VA.
4753 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4754 panic("pmap_map_chunk: no L2 table for VA 0x%08x", va);
4756 pte = (pt_entry_t *) kernel_pt_lookup(
4757 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4759 panic("pmap_map_chunk: can't find L2 table for VA"
4761 /* See if we can use a L2 large page mapping. */
4762 if (L2_L_MAPPABLE_P(va, pa, resid)) {
4763 #ifdef VERBOSE_INIT_ARM
4766 for (i = 0; i < 16; i++) {
4767 pte[l2pte_index(va) + i] =
4769 L2_L_PROT(PTE_KERNEL, prot) | f2l;
4770 PTE_SYNC(&pte[l2pte_index(va) + i]);
4778 /* Use a small page mapping. */
4779 #ifdef VERBOSE_INIT_ARM
4782 pte[l2pte_index(va)] =
4783 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s;
4784 PTE_SYNC(&pte[l2pte_index(va)]);
4789 #ifdef VERBOSE_INIT_ARM
4796 /********************** Static device map routines ***************************/
4798 static const struct pmap_devmap *pmap_devmap_table;
4801 * Register the devmap table. This is provided in case early console
4802 * initialization needs to register mappings created by bootstrap code
4803 * before pmap_devmap_bootstrap() is called.
4806 pmap_devmap_register(const struct pmap_devmap *table)
4809 pmap_devmap_table = table;
4813 * Map all of the static regions in the devmap table, and remember
4814 * the devmap table so other parts of the kernel can look up entries
4818 pmap_devmap_bootstrap(vm_offset_t l1pt, const struct pmap_devmap *table)
4822 pmap_devmap_table = table;
4824 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
4825 #ifdef VERBOSE_INIT_ARM
4826 printf("devmap: %08x -> %08x @ %08x\n",
4827 pmap_devmap_table[i].pd_pa,
4828 pmap_devmap_table[i].pd_pa +
4829 pmap_devmap_table[i].pd_size - 1,
4830 pmap_devmap_table[i].pd_va);
4832 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va,
4833 pmap_devmap_table[i].pd_pa,
4834 pmap_devmap_table[i].pd_size,
4835 pmap_devmap_table[i].pd_prot,
4836 pmap_devmap_table[i].pd_cache);
4840 const struct pmap_devmap *
4841 pmap_devmap_find_pa(vm_paddr_t pa, vm_size_t size)
4845 if (pmap_devmap_table == NULL)
4848 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
4849 if (pa >= pmap_devmap_table[i].pd_pa &&
4850 pa + size <= pmap_devmap_table[i].pd_pa +
4851 pmap_devmap_table[i].pd_size)
4852 return (&pmap_devmap_table[i]);
4858 const struct pmap_devmap *
4859 pmap_devmap_find_va(vm_offset_t va, vm_size_t size)
4863 if (pmap_devmap_table == NULL)
4866 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
4867 if (va >= pmap_devmap_table[i].pd_va &&
4868 va + size <= pmap_devmap_table[i].pd_va +
4869 pmap_devmap_table[i].pd_size)
4870 return (&pmap_devmap_table[i]);