1 /* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */
3 * Copyright 2004 Olivier Houchard.
4 * Copyright 2003 Wasabi Systems, Inc.
7 * Written by Steve C. Woodford for Wasabi Systems, Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
39 * Copyright (c) 2002-2003 Wasabi Systems, Inc.
40 * Copyright (c) 2001 Richard Earnshaw
41 * Copyright (c) 2001-2002 Christopher Gilbert
42 * All rights reserved.
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. The name of the company nor the name of the author may be used to
50 * endorse or promote products derived from this software without specific
51 * prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
66 * Copyright (c) 1999 The NetBSD Foundation, Inc.
67 * All rights reserved.
69 * This code is derived from software contributed to The NetBSD Foundation
70 * by Charles M. Hannum.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
80 * 3. All advertising materials mentioning features or use of this software
81 * must display the following acknowledgement:
82 * This product includes software developed by the NetBSD
83 * Foundation, Inc. and its contributors.
84 * 4. Neither the name of The NetBSD Foundation nor the names of its
85 * contributors may be used to endorse or promote products derived
86 * from this software without specific prior written permission.
88 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
89 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
90 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
91 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
92 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
93 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
94 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
95 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
96 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
97 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
98 * POSSIBILITY OF SUCH DAMAGE.
102 * Copyright (c) 1994-1998 Mark Brinicombe.
103 * Copyright (c) 1994 Brini.
104 * All rights reserved.
106 * This code is derived from software written for Brini by Mark Brinicombe
108 * Redistribution and use in source and binary forms, with or without
109 * modification, are permitted provided that the following conditions
111 * 1. Redistributions of source code must retain the above copyright
112 * notice, this list of conditions and the following disclaimer.
113 * 2. Redistributions in binary form must reproduce the above copyright
114 * notice, this list of conditions and the following disclaimer in the
115 * documentation and/or other materials provided with the distribution.
116 * 3. All advertising materials mentioning features or use of this software
117 * must display the following acknowledgement:
118 * This product includes software developed by Mark Brinicombe.
119 * 4. The name of the author may not be used to endorse or promote products
120 * derived from this software without specific prior written permission.
122 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
123 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
124 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
125 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
126 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
127 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
128 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
129 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
130 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
132 * RiscBSD kernel project
136 * Machine dependant vm stuff
142 * Special compilation symbols
143 * PMAP_DEBUG - Build in pmap_debug_level code
145 /* Include header files */
149 #include <sys/cdefs.h>
150 __FBSDID("$FreeBSD$");
151 #include <sys/param.h>
152 #include <sys/systm.h>
153 #include <sys/kernel.h>
154 #include <sys/proc.h>
155 #include <sys/malloc.h>
156 #include <sys/msgbuf.h>
157 #include <sys/vmmeter.h>
158 #include <sys/mman.h>
161 #include <sys/sched.h>
166 #include <vm/vm_kern.h>
167 #include <vm/vm_object.h>
168 #include <vm/vm_map.h>
169 #include <vm/vm_page.h>
170 #include <vm/vm_pageout.h>
171 #include <vm/vm_extern.h>
172 #include <sys/lock.h>
173 #include <sys/mutex.h>
174 #include <machine/md_var.h>
175 #include <machine/vmparam.h>
176 #include <machine/cpu.h>
177 #include <machine/cpufunc.h>
178 #include <machine/pcb.h>
181 #define PDEBUG(_lev_,_stat_) \
182 if (pmap_debug_level >= (_lev_)) \
184 #define dprintf printf
186 int pmap_debug_level = 0;
188 #else /* PMAP_DEBUG */
189 #define PDEBUG(_lev_,_stat_) /* Nothing */
190 #define dprintf(x, arg...)
191 #define PMAP_INLINE __inline
192 #endif /* PMAP_DEBUG */
194 extern struct pv_addr systempage;
196 * Internal function prototypes
198 static void pmap_free_pv_entry (pv_entry_t);
199 static pv_entry_t pmap_get_pv_entry(void);
201 static void pmap_enter_locked(pmap_t, vm_offset_t, vm_page_t,
202 vm_prot_t, boolean_t, int);
203 static void pmap_vac_me_harder(struct vm_page *, pmap_t,
205 static void pmap_vac_me_kpmap(struct vm_page *, pmap_t,
207 static void pmap_vac_me_user(struct vm_page *, pmap_t, vm_offset_t);
208 static void pmap_alloc_l1(pmap_t);
209 static void pmap_free_l1(pmap_t);
210 static void pmap_use_l1(pmap_t);
212 static int pmap_clearbit(struct vm_page *, u_int);
214 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t);
215 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t);
216 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int);
217 static vm_offset_t kernel_pt_lookup(vm_paddr_t);
219 static MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1");
221 vm_offset_t avail_end; /* PA of last available physical page */
222 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
223 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
224 vm_offset_t pmap_curmaxkvaddr;
225 vm_paddr_t kernel_l1pa;
228 vm_offset_t kernel_vm_end = 0;
230 struct pmap kernel_pmap_store;
233 static pt_entry_t *csrc_pte, *cdst_pte;
234 static vm_offset_t csrcp, cdstp;
235 static struct mtx cmtx;
237 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *);
239 * These routines are called when the CPU type is identified to set up
240 * the PTE prototypes, cache modes, etc.
242 * The variables are always here, just in case LKMs need to reference
243 * them (though, they shouldn't).
246 pt_entry_t pte_l1_s_cache_mode;
247 pt_entry_t pte_l1_s_cache_mode_pt;
248 pt_entry_t pte_l1_s_cache_mask;
250 pt_entry_t pte_l2_l_cache_mode;
251 pt_entry_t pte_l2_l_cache_mode_pt;
252 pt_entry_t pte_l2_l_cache_mask;
254 pt_entry_t pte_l2_s_cache_mode;
255 pt_entry_t pte_l2_s_cache_mode_pt;
256 pt_entry_t pte_l2_s_cache_mask;
258 pt_entry_t pte_l2_s_prot_u;
259 pt_entry_t pte_l2_s_prot_w;
260 pt_entry_t pte_l2_s_prot_mask;
262 pt_entry_t pte_l1_s_proto;
263 pt_entry_t pte_l1_c_proto;
264 pt_entry_t pte_l2_s_proto;
266 void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t);
267 void (*pmap_zero_page_func)(vm_paddr_t, int, int);
269 * Which pmap is currently 'live' in the cache
271 * XXXSCW: Fix for SMP ...
273 union pmap_cache_state *pmap_cache_state;
275 /* static pt_entry_t *msgbufmap;*/
276 struct msgbuf *msgbufp = 0;
278 extern void bcopy_page(vm_offset_t, vm_offset_t);
279 extern void bzero_page(vm_offset_t);
281 extern vm_offset_t alloc_firstaddr;
286 * Metadata for L1 translation tables.
289 /* Entry on the L1 Table list */
290 SLIST_ENTRY(l1_ttable) l1_link;
292 /* Entry on the L1 Least Recently Used list */
293 TAILQ_ENTRY(l1_ttable) l1_lru;
295 /* Track how many domains are allocated from this L1 */
296 volatile u_int l1_domain_use_count;
299 * A free-list of domain numbers for this L1.
300 * We avoid using ffs() and a bitmap to track domains since ffs()
303 u_int8_t l1_domain_first;
304 u_int8_t l1_domain_free[PMAP_DOMAINS];
306 /* Physical address of this L1 page table */
307 vm_paddr_t l1_physaddr;
309 /* KVA of this L1 page table */
314 * Convert a virtual address into its L1 table index. That is, the
315 * index used to locate the L2 descriptor table pointer in an L1 table.
316 * This is basically used to index l1->l1_kva[].
318 * Each L2 descriptor table represents 1MB of VA space.
320 #define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT)
323 * L1 Page Tables are tracked using a Least Recently Used list.
324 * - New L1s are allocated from the HEAD.
325 * - Freed L1s are added to the TAIl.
326 * - Recently accessed L1s (where an 'access' is some change to one of
327 * the userland pmaps which owns this L1) are moved to the TAIL.
329 static TAILQ_HEAD(, l1_ttable) l1_lru_list;
331 * A list of all L1 tables
333 static SLIST_HEAD(, l1_ttable) l1_list;
334 static struct mtx l1_lru_lock;
337 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots.
339 * This is normally 16MB worth L2 page descriptors for any given pmap.
340 * Reference counts are maintained for L2 descriptors so they can be
344 /* The number of L2 page descriptors allocated to this l2_dtable */
347 /* List of L2 page descriptors */
349 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */
350 vm_paddr_t l2b_phys; /* Physical address of same */
351 u_short l2b_l1idx; /* This L2 table's L1 index */
352 u_short l2b_occupancy; /* How many active descriptors */
353 } l2_bucket[L2_BUCKET_SIZE];
356 /* pmap_kenter_internal flags */
357 #define KENTER_CACHE 0x1
358 #define KENTER_USER 0x2
361 * Given an L1 table index, calculate the corresponding l2_dtable index
362 * and bucket index within the l2_dtable.
364 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \
366 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1))
369 * Given a virtual address, this macro returns the
370 * virtual address required to drop into the next L2 bucket.
372 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE)
377 #define pmap_alloc_l2_dtable() \
378 (void*)uma_zalloc(l2table_zone, M_NOWAIT|M_USE_RESERVE)
379 #define pmap_free_l2_dtable(l2) \
380 uma_zfree(l2table_zone, l2)
383 * We try to map the page tables write-through, if possible. However, not
384 * all CPUs have a write-through cache mode, so on those we have to sync
385 * the cache when we frob page tables.
387 * We try to evaluate this at compile time, if possible. However, it's
388 * not always possible to do that, hence this run-time var.
390 int pmap_needs_pte_sync;
393 * Macro to determine if a mapping might be resident in the
394 * instruction cache and/or TLB
396 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC))
399 * Macro to determine if a mapping might be resident in the
400 * data cache and/or TLB
402 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0)
404 #ifndef PMAP_SHPGPERPROC
405 #define PMAP_SHPGPERPROC 200
408 #define pmap_is_current(pm) ((pm) == pmap_kernel() || \
409 curproc->p_vmspace->vm_map.pmap == (pm))
410 static uma_zone_t pvzone;
412 static uma_zone_t l2table_zone;
413 static vm_offset_t pmap_kernel_l2dtable_kva;
414 static vm_offset_t pmap_kernel_l2ptp_kva;
415 static vm_paddr_t pmap_kernel_l2ptp_phys;
416 static struct vm_object pvzone_obj;
417 static int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0;
420 * This list exists for the benefit of pmap_map_chunk(). It keeps track
421 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can
422 * find them as necessary.
424 * Note that the data on this list MUST remain valid after initarm() returns,
425 * as pmap_bootstrap() uses it to contruct L2 table metadata.
427 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list);
430 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt)
435 l1->l1_domain_use_count = 0;
436 l1->l1_domain_first = 0;
438 for (i = 0; i < PMAP_DOMAINS; i++)
439 l1->l1_domain_free[i] = i + 1;
442 * Copy the kernel's L1 entries to each new L1.
444 if (l1pt != pmap_kernel()->pm_l1->l1_kva)
445 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE);
447 if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0)
448 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt);
449 SLIST_INSERT_HEAD(&l1_list, l1, l1_link);
450 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
454 kernel_pt_lookup(vm_paddr_t pa)
458 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) {
465 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
467 pmap_pte_init_generic(void)
470 pte_l1_s_cache_mode = L1_S_B|L1_S_C;
471 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic;
473 pte_l2_l_cache_mode = L2_B|L2_C;
474 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic;
476 pte_l2_s_cache_mode = L2_B|L2_C;
477 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic;
480 * If we have a write-through cache, set B and C. If
481 * we have a write-back cache, then we assume setting
482 * only C will make those pages write-through.
484 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) {
485 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
486 pte_l2_l_cache_mode_pt = L2_B|L2_C;
487 pte_l2_s_cache_mode_pt = L2_B|L2_C;
489 pte_l1_s_cache_mode_pt = L1_S_C;
490 pte_l2_l_cache_mode_pt = L2_C;
491 pte_l2_s_cache_mode_pt = L2_C;
494 pte_l2_s_prot_u = L2_S_PROT_U_generic;
495 pte_l2_s_prot_w = L2_S_PROT_W_generic;
496 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic;
498 pte_l1_s_proto = L1_S_PROTO_generic;
499 pte_l1_c_proto = L1_C_PROTO_generic;
500 pte_l2_s_proto = L2_S_PROTO_generic;
502 pmap_copy_page_func = pmap_copy_page_generic;
503 pmap_zero_page_func = pmap_zero_page_generic;
506 #if defined(CPU_ARM8)
508 pmap_pte_init_arm8(void)
512 * ARM8 is compatible with generic, but we need to use
513 * the page tables uncached.
515 pmap_pte_init_generic();
517 pte_l1_s_cache_mode_pt = 0;
518 pte_l2_l_cache_mode_pt = 0;
519 pte_l2_s_cache_mode_pt = 0;
521 #endif /* CPU_ARM8 */
523 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH)
525 pmap_pte_init_arm9(void)
529 * ARM9 is compatible with generic, but we want to use
530 * write-through caching for now.
532 pmap_pte_init_generic();
534 pte_l1_s_cache_mode = L1_S_C;
535 pte_l2_l_cache_mode = L2_C;
536 pte_l2_s_cache_mode = L2_C;
538 pte_l1_s_cache_mode_pt = L1_S_C;
539 pte_l2_l_cache_mode_pt = L2_C;
540 pte_l2_s_cache_mode_pt = L2_C;
542 #endif /* CPU_ARM9 */
543 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
545 #if defined(CPU_ARM10)
547 pmap_pte_init_arm10(void)
551 * ARM10 is compatible with generic, but we want to use
552 * write-through caching for now.
554 pmap_pte_init_generic();
556 pte_l1_s_cache_mode = L1_S_B | L1_S_C;
557 pte_l2_l_cache_mode = L2_B | L2_C;
558 pte_l2_s_cache_mode = L2_B | L2_C;
560 pte_l1_s_cache_mode_pt = L1_S_C;
561 pte_l2_l_cache_mode_pt = L2_C;
562 pte_l2_s_cache_mode_pt = L2_C;
565 #endif /* CPU_ARM10 */
569 pmap_pte_init_sa1(void)
573 * The StrongARM SA-1 cache does not have a write-through
574 * mode. So, do the generic initialization, then reset
575 * the page table cache mode to B=1,C=1, and note that
576 * the PTEs need to be sync'd.
578 pmap_pte_init_generic();
580 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
581 pte_l2_l_cache_mode_pt = L2_B|L2_C;
582 pte_l2_s_cache_mode_pt = L2_B|L2_C;
584 pmap_needs_pte_sync = 1;
586 #endif /* ARM_MMU_SA1 == 1*/
588 #if ARM_MMU_XSCALE == 1
590 static u_int xscale_use_minidata;
594 pmap_pte_init_xscale(void)
597 int write_through = 0;
599 pte_l1_s_cache_mode = L1_S_B|L1_S_C|L1_S_XSCALE_P;
600 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale;
602 pte_l2_l_cache_mode = L2_B|L2_C;
603 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale;
605 pte_l2_s_cache_mode = L2_B|L2_C;
606 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale;
608 pte_l1_s_cache_mode_pt = L1_S_C;
609 pte_l2_l_cache_mode_pt = L2_C;
610 pte_l2_s_cache_mode_pt = L2_C;
611 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE
613 * The XScale core has an enhanced mode where writes that
614 * miss the cache cause a cache line to be allocated. This
615 * is significantly faster than the traditional, write-through
616 * behavior of this case.
618 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X);
619 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X);
620 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X);
621 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */
622 #ifdef XSCALE_CACHE_WRITE_THROUGH
624 * Some versions of the XScale core have various bugs in
625 * their cache units, the work-around for which is to run
626 * the cache in write-through mode. Unfortunately, this
627 * has a major (negative) impact on performance. So, we
628 * go ahead and run fast-and-loose, in the hopes that we
629 * don't line up the planets in a way that will trip the
632 * However, we give you the option to be slow-but-correct.
635 #elif defined(XSCALE_CACHE_WRITE_BACK)
636 /* force write back cache mode */
638 #elif defined(CPU_XSCALE_PXA2X0)
640 * Intel PXA2[15]0 processors are known to have a bug in
641 * write-back cache on revision 4 and earlier (stepping
642 * A[01] and B[012]). Fixed for C0 and later.
648 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK);
650 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) {
651 if ((id & CPU_ID_REVISION_MASK) < 5) {
652 /* write through for stepping A0-1 and B0-2 */
657 #endif /* XSCALE_CACHE_WRITE_THROUGH */
660 pte_l1_s_cache_mode = L1_S_C;
661 pte_l2_l_cache_mode = L2_C;
662 pte_l2_s_cache_mode = L2_C;
666 xscale_use_minidata = 1;
669 pte_l2_s_prot_u = L2_S_PROT_U_xscale;
670 pte_l2_s_prot_w = L2_S_PROT_W_xscale;
671 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale;
673 pte_l1_s_proto = L1_S_PROTO_xscale;
674 pte_l1_c_proto = L1_C_PROTO_xscale;
675 pte_l2_s_proto = L2_S_PROTO_xscale;
677 pmap_copy_page_func = pmap_copy_page_xscale;
678 pmap_zero_page_func = pmap_zero_page_xscale;
681 * Disable ECC protection of page table access, for now.
683 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
684 auxctl &= ~XSCALE_AUXCTL_P;
685 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
689 * xscale_setup_minidata:
691 * Set up the mini-data cache clean area. We require the
692 * caller to allocate the right amount of physically and
693 * virtually contiguous space.
695 extern vm_offset_t xscale_minidata_clean_addr;
696 extern vm_size_t xscale_minidata_clean_size; /* already initialized */
698 xscale_setup_minidata(vm_offset_t l1pt, vm_offset_t va, vm_paddr_t pa)
700 pd_entry_t *pde = (pd_entry_t *) l1pt;
705 xscale_minidata_clean_addr = va;
707 /* Round it to page size. */
708 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME;
711 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) {
712 pte = (pt_entry_t *) kernel_pt_lookup(
713 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
715 panic("xscale_setup_minidata: can't find L2 table for "
716 "VA 0x%08x", (u_int32_t) va);
717 pte[l2pte_index(va)] =
718 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
719 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X);
723 * Configure the mini-data cache for write-back with
724 * read/write-allocate.
726 * NOTE: In order to reconfigure the mini-data cache, we must
727 * make sure it contains no valid data! In order to do that,
728 * we must issue a global data cache invalidate command!
730 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED!
731 * THIS IS VERY IMPORTANT!
734 /* Invalidate data and mini-data. */
735 __asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
736 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
737 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA;
738 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
743 * Allocate an L1 translation table for the specified pmap.
744 * This is called at pmap creation time.
747 pmap_alloc_l1(pmap_t pm)
749 struct l1_ttable *l1;
753 * Remove the L1 at the head of the LRU list
755 mtx_lock(&l1_lru_lock);
756 l1 = TAILQ_FIRST(&l1_lru_list);
757 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
760 * Pick the first available domain number, and update
761 * the link to the next number.
763 domain = l1->l1_domain_first;
764 l1->l1_domain_first = l1->l1_domain_free[domain];
767 * If there are still free domain numbers in this L1,
768 * put it back on the TAIL of the LRU list.
770 if (++l1->l1_domain_use_count < PMAP_DOMAINS)
771 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
773 mtx_unlock(&l1_lru_lock);
776 * Fix up the relevant bits in the pmap structure
779 pm->pm_domain = domain;
783 * Free an L1 translation table.
784 * This is called at pmap destruction time.
787 pmap_free_l1(pmap_t pm)
789 struct l1_ttable *l1 = pm->pm_l1;
791 mtx_lock(&l1_lru_lock);
794 * If this L1 is currently on the LRU list, remove it.
796 if (l1->l1_domain_use_count < PMAP_DOMAINS)
797 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
800 * Free up the domain number which was allocated to the pmap
802 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first;
803 l1->l1_domain_first = pm->pm_domain;
804 l1->l1_domain_use_count--;
807 * The L1 now must have at least 1 free domain, so add
808 * it back to the LRU list. If the use count is zero,
809 * put it at the head of the list, otherwise it goes
812 if (l1->l1_domain_use_count == 0) {
813 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru);
815 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
817 mtx_unlock(&l1_lru_lock);
820 static PMAP_INLINE void
821 pmap_use_l1(pmap_t pm)
823 struct l1_ttable *l1;
826 * Do nothing if we're in interrupt context.
827 * Access to an L1 by the kernel pmap must not affect
830 if (pm == pmap_kernel())
836 * If the L1 is not currently on the LRU list, just return
838 if (l1->l1_domain_use_count == PMAP_DOMAINS)
841 mtx_lock(&l1_lru_lock);
844 * Check the use count again, now that we've acquired the lock
846 if (l1->l1_domain_use_count == PMAP_DOMAINS) {
847 mtx_unlock(&l1_lru_lock);
852 * Move the L1 to the back of the LRU list
854 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
855 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
857 mtx_unlock(&l1_lru_lock);
862 * Returns a pointer to the L2 bucket associated with the specified pmap
863 * and VA, or NULL if no L2 bucket exists for the address.
865 static PMAP_INLINE struct l2_bucket *
866 pmap_get_l2_bucket(pmap_t pm, vm_offset_t va)
868 struct l2_dtable *l2;
869 struct l2_bucket *l2b;
874 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL ||
875 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL)
882 * Returns a pointer to the L2 bucket associated with the specified pmap
885 * If no L2 bucket exists, perform the necessary allocations to put an L2
886 * bucket/page table in place.
888 * Note that if a new L2 bucket/page was allocated, the caller *must*
889 * increment the bucket occupancy counter appropriately *before*
890 * releasing the pmap's lock to ensure no other thread or cpu deallocates
891 * the bucket/page in the meantime.
893 static struct l2_bucket *
894 pmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va)
896 struct l2_dtable *l2;
897 struct l2_bucket *l2b;
902 PMAP_ASSERT_LOCKED(pm);
903 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
904 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
906 * No mapping at this address, as there is
907 * no entry in the L1 table.
908 * Need to allocate a new l2_dtable.
912 vm_page_unlock_queues();
913 if ((l2 = pmap_alloc_l2_dtable()) == NULL) {
914 vm_page_lock_queues();
918 vm_page_lock_queues();
920 if (pm->pm_l2[L2_IDX(l1idx)] != NULL) {
922 vm_page_unlock_queues();
923 uma_zfree(l2table_zone, l2);
924 vm_page_lock_queues();
926 l2 = pm->pm_l2[L2_IDX(l1idx)];
930 * Someone already allocated the l2_dtable while
931 * we were doing the same.
934 bzero(l2, sizeof(*l2));
936 * Link it into the parent pmap
938 pm->pm_l2[L2_IDX(l1idx)] = l2;
942 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
945 * Fetch pointer to the L2 page table associated with the address.
947 if (l2b->l2b_kva == NULL) {
951 * No L2 page table has been allocated. Chances are, this
952 * is because we just allocated the l2_dtable, above.
956 vm_page_unlock_queues();
957 ptep = (void*)uma_zalloc(l2zone, M_NOWAIT|M_USE_RESERVE);
958 vm_page_lock_queues();
960 if (l2b->l2b_kva != 0) {
961 /* We lost the race. */
963 vm_page_unlock_queues();
964 uma_zfree(l2zone, ptep);
965 vm_page_lock_queues();
967 if (l2b->l2b_kva == 0)
971 l2b->l2b_phys = vtophys(ptep);
974 * Oops, no more L2 page tables available at this
975 * time. We may need to deallocate the l2_dtable
976 * if we allocated a new one above.
978 if (l2->l2_occupancy == 0) {
979 pm->pm_l2[L2_IDX(l1idx)] = NULL;
980 pmap_free_l2_dtable(l2);
987 l2b->l2b_l1idx = l1idx;
993 static PMAP_INLINE void
994 #ifndef PMAP_INCLUDE_PTE_SYNC
995 pmap_free_l2_ptp(pt_entry_t *l2)
997 pmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2)
1000 #ifdef PMAP_INCLUDE_PTE_SYNC
1002 * Note: With a write-back cache, we may need to sync this
1003 * L2 table before re-using it.
1004 * This is because it may have belonged to a non-current
1005 * pmap, in which case the cache syncs would have been
1006 * skipped when the pages were being unmapped. If the
1007 * L2 table were then to be immediately re-allocated to
1008 * the *current* pmap, it may well contain stale mappings
1009 * which have not yet been cleared by a cache write-back
1010 * and so would still be visible to the mmu.
1013 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
1015 uma_zfree(l2zone, l2);
1018 * One or more mappings in the specified L2 descriptor table have just been
1021 * Garbage collect the metadata and descriptor table itself if necessary.
1023 * The pmap lock must be acquired when this is called (not necessary
1024 * for the kernel pmap).
1027 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count)
1029 struct l2_dtable *l2;
1030 pd_entry_t *pl1pd, l1pd;
1036 * Update the bucket's reference count according to how many
1037 * PTEs the caller has just invalidated.
1039 l2b->l2b_occupancy -= count;
1044 * Level 2 page tables allocated to the kernel pmap are never freed
1045 * as that would require checking all Level 1 page tables and
1046 * removing any references to the Level 2 page table. See also the
1047 * comment elsewhere about never freeing bootstrap L2 descriptors.
1049 * We make do with just invalidating the mapping in the L2 table.
1051 * This isn't really a big deal in practice and, in fact, leads
1052 * to a performance win over time as we don't need to continually
1055 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel())
1059 * There are no more valid mappings in this level 2 page table.
1060 * Go ahead and NULL-out the pointer in the bucket, then
1061 * free the page table.
1063 l1idx = l2b->l2b_l1idx;
1064 ptep = l2b->l2b_kva;
1065 l2b->l2b_kva = NULL;
1067 pl1pd = &pm->pm_l1->l1_kva[l1idx];
1070 * If the L1 slot matches the pmap's domain
1071 * number, then invalidate it.
1073 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK);
1074 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) {
1080 * Release the L2 descriptor table back to the pool cache.
1082 #ifndef PMAP_INCLUDE_PTE_SYNC
1083 pmap_free_l2_ptp(ptep);
1085 pmap_free_l2_ptp(!pmap_is_current(pm), ptep);
1089 * Update the reference count in the associated l2_dtable
1091 l2 = pm->pm_l2[L2_IDX(l1idx)];
1092 if (--l2->l2_occupancy > 0)
1096 * There are no more valid mappings in any of the Level 1
1097 * slots managed by this l2_dtable. Go ahead and NULL-out
1098 * the pointer in the parent pmap and free the l2_dtable.
1100 pm->pm_l2[L2_IDX(l1idx)] = NULL;
1101 pmap_free_l2_dtable(l2);
1105 * Pool cache constructors for L2 descriptor tables, metadata and pmap
1109 pmap_l2ptp_ctor(void *mem, int size, void *arg, int flags)
1111 #ifndef PMAP_INCLUDE_PTE_SYNC
1112 struct l2_bucket *l2b;
1113 pt_entry_t *ptep, pte;
1114 #ifdef ARM_USE_SMALL_ALLOC
1117 vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK;
1120 * The mappings for these page tables were initially made using
1121 * pmap_kenter() by the pool subsystem. Therefore, the cache-
1122 * mode will not be right for page table mappings. To avoid
1123 * polluting the pmap_kenter() code with a special case for
1124 * page tables, we simply fix up the cache-mode here if it's not
1127 #ifdef ARM_USE_SMALL_ALLOC
1128 pde = &kernel_pmap->pm_l1->l1_kva[L1_IDX(va)];
1129 if (!l1pte_section_p(*pde)) {
1131 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
1132 ptep = &l2b->l2b_kva[l2pte_index(va)];
1135 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
1137 * Page tables must have the cache-mode set to
1140 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
1142 cpu_tlb_flushD_SE(va);
1145 #ifdef ARM_USE_SMALL_ALLOC
1149 memset(mem, 0, L2_TABLE_SIZE_REAL);
1150 PTE_SYNC_RANGE(mem, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
1155 * A bunch of routines to conditionally flush the caches/TLB depending
1156 * on whether the specified pmap actually needs to be flushed at any
1159 static PMAP_INLINE void
1160 pmap_tlb_flushID_SE(pmap_t pm, vm_offset_t va)
1163 if (pmap_is_current(pm))
1164 cpu_tlb_flushID_SE(va);
1167 static PMAP_INLINE void
1168 pmap_tlb_flushD_SE(pmap_t pm, vm_offset_t va)
1171 if (pmap_is_current(pm))
1172 cpu_tlb_flushD_SE(va);
1175 static PMAP_INLINE void
1176 pmap_tlb_flushID(pmap_t pm)
1179 if (pmap_is_current(pm))
1182 static PMAP_INLINE void
1183 pmap_tlb_flushD(pmap_t pm)
1186 if (pmap_is_current(pm))
1190 static PMAP_INLINE void
1191 pmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len)
1194 if (pmap_is_current(pm))
1195 cpu_idcache_wbinv_range(va, len);
1198 static PMAP_INLINE void
1199 pmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len,
1200 boolean_t do_inv, boolean_t rd_only)
1203 if (pmap_is_current(pm)) {
1206 cpu_dcache_inv_range(va, len);
1208 cpu_dcache_wbinv_range(va, len);
1211 cpu_dcache_wb_range(va, len);
1215 static PMAP_INLINE void
1216 pmap_idcache_wbinv_all(pmap_t pm)
1219 if (pmap_is_current(pm))
1220 cpu_idcache_wbinv_all();
1223 static PMAP_INLINE void
1224 pmap_dcache_wbinv_all(pmap_t pm)
1227 if (pmap_is_current(pm))
1228 cpu_dcache_wbinv_all();
1234 * Make sure the pte is written out to RAM.
1235 * We need to do this for one of two cases:
1236 * - We're dealing with the kernel pmap
1237 * - There is no pmap active in the cache/tlb.
1238 * - The specified pmap is 'active' in the cache/tlb.
1240 #ifdef PMAP_INCLUDE_PTE_SYNC
1241 #define PTE_SYNC_CURRENT(pm, ptep) \
1243 if (PMAP_NEEDS_PTE_SYNC && \
1244 pmap_is_current(pm)) \
1246 } while (/*CONSTCOND*/0)
1248 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */
1252 * Since we have a virtually indexed cache, we may need to inhibit caching if
1253 * there is more than one mapping and at least one of them is writable.
1254 * Since we purge the cache on every context switch, we only need to check for
1255 * other mappings within the same pmap, or kernel_pmap.
1256 * This function is also called when a page is unmapped, to possibly reenable
1257 * caching on any remaining mappings.
1259 * The code implements the following logic, where:
1261 * KW = # of kernel read/write pages
1262 * KR = # of kernel read only pages
1263 * UW = # of user read/write pages
1264 * UR = # of user read only pages
1266 * KC = kernel mapping is cacheable
1267 * UC = user mapping is cacheable
1269 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0
1270 * +---------------------------------------------
1271 * UW=0,UR=0 | --- KC=1 KC=1 KC=0
1272 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0
1273 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0
1274 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0
1277 static const int pmap_vac_flags[4][4] = {
1278 {-1, 0, 0, PVF_KNC},
1279 {0, 0, PVF_NC, PVF_NC},
1280 {0, PVF_NC, PVF_NC, PVF_NC},
1281 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC}
1284 static PMAP_INLINE int
1285 pmap_get_vac_flags(const struct vm_page *pg)
1290 if (pg->md.kro_mappings || pg->md.krw_mappings > 1)
1292 if (pg->md.krw_mappings)
1296 if (pg->md.uro_mappings || pg->md.urw_mappings > 1)
1298 if (pg->md.urw_mappings)
1301 return (pmap_vac_flags[uidx][kidx]);
1304 static __inline void
1305 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1309 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1310 nattr = pmap_get_vac_flags(pg);
1313 pg->md.pvh_attrs &= ~PVF_NC;
1317 if (nattr == 0 && (pg->md.pvh_attrs & PVF_NC) == 0) {
1321 if (pm == pmap_kernel())
1322 pmap_vac_me_kpmap(pg, pm, va);
1324 pmap_vac_me_user(pg, pm, va);
1326 pg->md.pvh_attrs = (pg->md.pvh_attrs & ~PVF_NC) | nattr;
1330 pmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1332 u_int u_cacheable, u_entries;
1333 struct pv_entry *pv;
1334 pmap_t last_pmap = pm;
1337 * Pass one, see if there are both kernel and user pmaps for
1338 * this page. Calculate whether there are user-writable or
1339 * kernel-writable pages.
1342 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1343 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0)
1347 u_entries = pg->md.urw_mappings + pg->md.uro_mappings;
1350 * We know we have just been updating a kernel entry, so if
1351 * all user pages are already cacheable, then there is nothing
1354 if (pg->md.k_mappings == 0 && u_cacheable == u_entries)
1359 * Scan over the list again, for each entry, if it
1360 * might not be set correctly, call pmap_vac_me_user
1361 * to recalculate the settings.
1363 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1365 * We know kernel mappings will get set
1366 * correctly in other calls. We also know
1367 * that if the pmap is the same as last_pmap
1368 * then we've just handled this entry.
1370 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap)
1374 * If there are kernel entries and this page
1375 * is writable but non-cacheable, then we can
1376 * skip this entry also.
1378 if (pg->md.k_mappings &&
1379 (pv->pv_flags & (PVF_NC | PVF_WRITE)) ==
1380 (PVF_NC | PVF_WRITE))
1384 * Similarly if there are no kernel-writable
1385 * entries and the page is already
1386 * read-only/cacheable.
1388 if (pg->md.krw_mappings == 0 &&
1389 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0)
1393 * For some of the remaining cases, we know
1394 * that we must recalculate, but for others we
1395 * can't tell if they are correct or not, so
1396 * we recalculate anyway.
1398 pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0);
1401 if (pg->md.k_mappings == 0)
1405 pmap_vac_me_user(pg, pm, va);
1409 pmap_vac_me_user(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1411 pmap_t kpmap = pmap_kernel();
1412 struct pv_entry *pv, *npv;
1413 struct l2_bucket *l2b;
1414 pt_entry_t *ptep, pte;
1417 u_int cacheable_entries = 0;
1418 u_int kern_cacheable = 0;
1419 u_int other_writable = 0;
1422 * Count mappings and writable mappings in this pmap.
1423 * Include kernel mappings as part of our own.
1424 * Keep a pointer to the first one.
1426 npv = TAILQ_FIRST(&pg->md.pv_list);
1427 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1428 /* Count mappings in the same pmap */
1429 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) {
1433 /* Cacheable mappings */
1434 if ((pv->pv_flags & PVF_NC) == 0) {
1435 cacheable_entries++;
1436 if (kpmap == pv->pv_pmap)
1440 /* Writable mappings */
1441 if (pv->pv_flags & PVF_WRITE)
1444 if (pv->pv_flags & PVF_WRITE)
1449 * Enable or disable caching as necessary.
1450 * Note: the first entry might be part of the kernel pmap,
1451 * so we can't assume this is indicative of the state of the
1452 * other (maybe non-kpmap) entries.
1454 if ((entries > 1 && writable) ||
1455 (entries > 0 && pm == kpmap && other_writable)) {
1456 if (cacheable_entries == 0)
1459 for (pv = npv; pv; pv = TAILQ_NEXT(pv, pv_list)) {
1460 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) ||
1461 (pv->pv_flags & PVF_NC))
1464 pv->pv_flags |= PVF_NC;
1466 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
1467 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
1468 pte = *ptep & ~L2_S_CACHE_MASK;
1470 if ((va != pv->pv_va || pm != pv->pv_pmap) &&
1472 if (PV_BEEN_EXECD(pv->pv_flags)) {
1473 pmap_idcache_wbinv_range(pv->pv_pmap,
1474 pv->pv_va, PAGE_SIZE);
1475 pmap_tlb_flushID_SE(pv->pv_pmap,
1478 if (PV_BEEN_REFD(pv->pv_flags)) {
1479 pmap_dcache_wb_range(pv->pv_pmap,
1480 pv->pv_va, PAGE_SIZE, TRUE,
1481 (pv->pv_flags & PVF_WRITE) == 0);
1482 pmap_tlb_flushD_SE(pv->pv_pmap,
1488 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
1492 if (entries > cacheable_entries) {
1494 * Turn cacheing back on for some pages. If it is a kernel
1495 * page, only do so if there are no other writable pages.
1497 for (pv = npv; pv; pv = TAILQ_NEXT(pv, pv_list)) {
1498 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap &&
1499 (kpmap != pv->pv_pmap || other_writable)))
1502 pv->pv_flags &= ~PVF_NC;
1504 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
1505 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
1506 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode;
1508 if (l2pte_valid(pte)) {
1509 if (PV_BEEN_EXECD(pv->pv_flags)) {
1510 pmap_tlb_flushID_SE(pv->pv_pmap,
1513 if (PV_BEEN_REFD(pv->pv_flags)) {
1514 pmap_tlb_flushD_SE(pv->pv_pmap,
1520 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
1526 * Modify pte bits for all ptes corresponding to the given physical address.
1527 * We use `maskbits' rather than `clearbits' because we're always passing
1528 * constants and the latter would require an extra inversion at run-time.
1531 pmap_clearbit(struct vm_page *pg, u_int maskbits)
1533 struct l2_bucket *l2b;
1534 struct pv_entry *pv;
1535 pt_entry_t *ptep, npte, opte;
1541 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1544 * Clear saved attributes (modify, reference)
1546 pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF));
1548 if (TAILQ_EMPTY(&pg->md.pv_list)) {
1553 * Loop over all current mappings setting/clearing as appropos
1555 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1558 oflags = pv->pv_flags;
1559 pv->pv_flags &= ~maskbits;
1563 l2b = pmap_get_l2_bucket(pm, va);
1565 ptep = &l2b->l2b_kva[l2pte_index(va)];
1566 npte = opte = *ptep;
1568 if (maskbits & (PVF_WRITE|PVF_MOD)) {
1569 if ((pv->pv_flags & PVF_NC)) {
1571 * Entry is not cacheable:
1573 * Don't turn caching on again if this is a
1574 * modified emulation. This would be
1575 * inconsitent with the settings created by
1576 * pmap_vac_me_harder(). Otherwise, it's safe
1577 * to re-enable cacheing.
1579 * There's no need to call pmap_vac_me_harder()
1580 * here: all pages are losing their write
1583 if (maskbits & PVF_WRITE) {
1584 npte |= pte_l2_s_cache_mode;
1585 pv->pv_flags &= ~PVF_NC;
1588 if (opte & L2_S_PROT_W) {
1591 * Entry is writable/cacheable: check if pmap
1592 * is current if it is flush it, otherwise it
1593 * won't be in the cache
1595 if (PV_BEEN_EXECD(oflags))
1596 pmap_idcache_wbinv_range(pm, pv->pv_va,
1599 if (PV_BEEN_REFD(oflags))
1600 pmap_dcache_wb_range(pm, pv->pv_va,
1602 (maskbits & PVF_REF) ? TRUE : FALSE,
1606 /* make the pte read only */
1607 npte &= ~L2_S_PROT_W;
1609 if (maskbits & PVF_WRITE) {
1611 * Keep alias accounting up to date
1613 if (pv->pv_pmap == pmap_kernel()) {
1614 if (oflags & PVF_WRITE) {
1615 pg->md.krw_mappings--;
1616 pg->md.kro_mappings++;
1619 if (oflags & PVF_WRITE) {
1620 pg->md.urw_mappings--;
1621 pg->md.uro_mappings++;
1626 if (maskbits & PVF_REF) {
1627 if ((pv->pv_flags & PVF_NC) == 0 &&
1628 (maskbits & (PVF_WRITE|PVF_MOD)) == 0) {
1630 * Check npte here; we may have already
1631 * done the wbinv above, and the validity
1632 * of the PTE is the same for opte and
1635 if (npte & L2_S_PROT_W) {
1636 if (PV_BEEN_EXECD(oflags))
1637 pmap_idcache_wbinv_range(pm,
1638 pv->pv_va, PAGE_SIZE);
1640 if (PV_BEEN_REFD(oflags))
1641 pmap_dcache_wb_range(pm,
1642 pv->pv_va, PAGE_SIZE,
1645 if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) {
1646 /* XXXJRT need idcache_inv_range */
1647 if (PV_BEEN_EXECD(oflags))
1648 pmap_idcache_wbinv_range(pm,
1649 pv->pv_va, PAGE_SIZE);
1651 if (PV_BEEN_REFD(oflags))
1652 pmap_dcache_wb_range(pm,
1653 pv->pv_va, PAGE_SIZE,
1659 * Make the PTE invalid so that we will take a
1660 * page fault the next time the mapping is
1663 npte &= ~L2_TYPE_MASK;
1664 npte |= L2_TYPE_INV;
1671 /* Flush the TLB entry if a current pmap. */
1672 if (PV_BEEN_EXECD(oflags))
1673 pmap_tlb_flushID_SE(pm, pv->pv_va);
1675 if (PV_BEEN_REFD(oflags))
1676 pmap_tlb_flushD_SE(pm, pv->pv_va);
1683 if (maskbits & PVF_WRITE)
1684 vm_page_flag_clear(pg, PG_WRITEABLE);
1689 * main pv_entry manipulation functions:
1690 * pmap_enter_pv: enter a mapping onto a vm_page list
1691 * pmap_remove_pv: remove a mappiing from a vm_page list
1693 * NOTE: pmap_enter_pv expects to lock the pvh itself
1694 * pmap_remove_pv expects te caller to lock the pvh before calling
1698 * pmap_enter_pv: enter a mapping onto a vm_page lst
1700 * => caller should hold the proper lock on pmap_main_lock
1701 * => caller should have pmap locked
1702 * => we will gain the lock on the vm_page and allocate the new pv_entry
1703 * => caller should adjust ptp's wire_count before calling
1704 * => caller should not adjust pmap's wire_count
1707 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm,
1708 vm_offset_t va, u_int flags)
1711 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1712 PMAP_ASSERT_LOCKED(pm);
1715 pve->pv_flags = flags;
1717 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list);
1718 TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist);
1719 pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD);
1720 if (pm == pmap_kernel()) {
1721 if (flags & PVF_WRITE)
1722 pg->md.krw_mappings++;
1724 pg->md.kro_mappings++;
1726 if (flags & PVF_WRITE)
1727 pg->md.urw_mappings++;
1729 pg->md.uro_mappings++;
1730 pg->md.pv_list_count++;
1731 if (pve->pv_flags & PVF_WIRED)
1732 ++pm->pm_stats.wired_count;
1733 vm_page_flag_set(pg, PG_REFERENCED);
1738 * pmap_find_pv: Find a pv entry
1740 * => caller should hold lock on vm_page
1742 static PMAP_INLINE struct pv_entry *
1743 pmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1745 struct pv_entry *pv;
1747 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1748 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list)
1749 if (pm == pv->pv_pmap && va == pv->pv_va)
1755 * vector_page_setprot:
1757 * Manipulate the protection of the vector page.
1760 vector_page_setprot(int prot)
1762 struct l2_bucket *l2b;
1765 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page);
1767 ptep = &l2b->l2b_kva[l2pte_index(vector_page)];
1769 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot);
1771 cpu_tlb_flushD_SE(vector_page);
1776 * pmap_remove_pv: try to remove a mapping from a pv_list
1778 * => caller should hold proper lock on pmap_main_lock
1779 * => pmap should be locked
1780 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1781 * => caller should adjust ptp's wire_count and free PTP if needed
1782 * => caller should NOT adjust pmap's wire_count
1783 * => we return the removed pve
1787 pmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve)
1790 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1791 PMAP_ASSERT_LOCKED(pm);
1792 TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list);
1793 TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist);
1794 if (pve->pv_flags & PVF_WIRED)
1795 --pm->pm_stats.wired_count;
1796 pg->md.pv_list_count--;
1797 if (pg->md.pvh_attrs & PVF_MOD)
1799 if (pm == pmap_kernel()) {
1800 if (pve->pv_flags & PVF_WRITE)
1801 pg->md.krw_mappings--;
1803 pg->md.kro_mappings--;
1805 if (pve->pv_flags & PVF_WRITE)
1806 pg->md.urw_mappings--;
1808 pg->md.uro_mappings--;
1809 if (TAILQ_FIRST(&pg->md.pv_list) == NULL ||
1810 (pg->md.krw_mappings == 0 && pg->md.urw_mappings == 0)) {
1811 pg->md.pvh_attrs &= ~PVF_MOD;
1812 if (TAILQ_FIRST(&pg->md.pv_list) == NULL)
1813 pg->md.pvh_attrs &= ~PVF_REF;
1814 vm_page_flag_clear(pg, PG_WRITEABLE);
1816 if (TAILQ_FIRST(&pg->md.pv_list))
1817 vm_page_flag_set(pg, PG_REFERENCED);
1818 if (pve->pv_flags & PVF_WRITE)
1819 pmap_vac_me_harder(pg, pm, 0);
1822 static struct pv_entry *
1823 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1825 struct pv_entry *pve;
1827 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1828 pve = TAILQ_FIRST(&pg->md.pv_list);
1831 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */
1832 pmap_nuke_pv(pg, pm, pve);
1835 pve = TAILQ_NEXT(pve, pv_list);
1838 return(pve); /* return removed pve */
1842 * pmap_modify_pv: Update pv flags
1844 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1845 * => caller should NOT adjust pmap's wire_count
1846 * => caller must call pmap_vac_me_harder() if writable status of a page
1848 * => we return the old flags
1850 * Modify a physical-virtual mapping in the pv table
1853 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va,
1854 u_int clr_mask, u_int set_mask)
1856 struct pv_entry *npv;
1857 u_int flags, oflags;
1859 PMAP_ASSERT_LOCKED(pm);
1860 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1861 if ((npv = pmap_find_pv(pg, pm, va)) == NULL)
1865 * There is at least one VA mapping this page.
1868 if (clr_mask & (PVF_REF | PVF_MOD))
1869 pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD);
1871 oflags = npv->pv_flags;
1872 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask;
1874 if ((flags ^ oflags) & PVF_WIRED) {
1875 if (flags & PVF_WIRED)
1876 ++pm->pm_stats.wired_count;
1878 --pm->pm_stats.wired_count;
1881 if ((flags ^ oflags) & PVF_WRITE) {
1882 if (pm == pmap_kernel()) {
1883 if (flags & PVF_WRITE) {
1884 pg->md.krw_mappings++;
1885 pg->md.kro_mappings--;
1887 pg->md.kro_mappings++;
1888 pg->md.krw_mappings--;
1891 if (flags & PVF_WRITE) {
1892 pg->md.urw_mappings++;
1893 pg->md.uro_mappings--;
1895 pg->md.uro_mappings++;
1896 pg->md.urw_mappings--;
1898 if (pg->md.krw_mappings == 0 && pg->md.urw_mappings == 0) {
1899 pg->md.pvh_attrs &= ~PVF_MOD;
1900 vm_page_flag_clear(pg, PG_WRITEABLE);
1902 pmap_vac_me_harder(pg, pm, 0);
1908 /* Function to set the debug level of the pmap code */
1911 pmap_debug(int level)
1913 pmap_debug_level = level;
1914 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
1916 #endif /* PMAP_DEBUG */
1919 pmap_pinit0(struct pmap *pmap)
1921 PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap));
1923 dprintf("pmap_pinit0: pmap = %08x, pm_pdir = %08x\n",
1924 (u_int32_t) pmap, (u_int32_t) pmap->pm_pdir);
1925 bcopy(kernel_pmap, pmap, sizeof(*pmap));
1926 bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx));
1927 PMAP_LOCK_INIT(pmap);
1931 * Initialize a vm_page's machine-dependent fields.
1934 pmap_page_init(vm_page_t m)
1937 TAILQ_INIT(&m->md.pv_list);
1938 m->md.pv_list_count = 0;
1942 * Initialize the pmap module.
1943 * Called by vm_init, to initialize any structures that the pmap
1944 * system needs to map virtual memory.
1949 int shpgperproc = PMAP_SHPGPERPROC;
1951 PDEBUG(1, printf("pmap_init: phys_start = %08x\n"));
1954 * init the pv free list
1956 pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL,
1957 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1959 * Now it is safe to enable pv_table recording.
1961 PDEBUG(1, printf("pmap_init: done!\n"));
1963 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1965 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
1966 pv_entry_high_water = 9 * (pv_entry_max / 10);
1967 l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor,
1968 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1969 l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable),
1970 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1971 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1973 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max);
1978 pmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user)
1980 struct l2_dtable *l2;
1981 struct l2_bucket *l2b;
1982 pd_entry_t *pl1pd, l1pd;
1983 pt_entry_t *ptep, pte;
1989 vm_page_lock_queues();
1993 * If there is no l2_dtable for this address, then the process
1994 * has no business accessing it.
1996 * Note: This will catch userland processes trying to access
1999 l2 = pm->pm_l2[L2_IDX(l1idx)];
2004 * Likewise if there is no L2 descriptor table
2006 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2007 if (l2b->l2b_kva == NULL)
2011 * Check the PTE itself.
2013 ptep = &l2b->l2b_kva[l2pte_index(va)];
2019 * Catch a userland access to the vector page mapped at 0x0
2021 if (user && (pte & L2_S_PROT_U) == 0)
2023 if (va == vector_page)
2028 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) {
2030 * This looks like a good candidate for "page modified"
2033 struct pv_entry *pv;
2036 /* Extract the physical address of the page */
2037 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) {
2040 /* Get the current flags for this page. */
2042 pv = pmap_find_pv(pg, pm, va);
2048 * Do the flags say this page is writable? If not then it
2049 * is a genuine write fault. If yes then the write fault is
2050 * our fault as we did not reflect the write access in the
2051 * PTE. Now we know a write has occurred we can correct this
2052 * and also set the modified bit
2054 if ((pv->pv_flags & PVF_WRITE) == 0) {
2058 pg->md.pvh_attrs |= PVF_REF | PVF_MOD;
2060 pv->pv_flags |= PVF_REF | PVF_MOD;
2063 * Re-enable write permissions for the page. No need to call
2064 * pmap_vac_me_harder(), since this is just a
2065 * modified-emulation fault, and the PVF_WRITE bit isn't
2066 * changing. We've already set the cacheable bits based on
2067 * the assumption that we can write to this page.
2069 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W;
2073 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) {
2075 * This looks like a good candidate for "page referenced"
2078 struct pv_entry *pv;
2081 /* Extract the physical address of the page */
2082 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL)
2084 /* Get the current flags for this page. */
2086 pv = pmap_find_pv(pg, pm, va);
2090 pg->md.pvh_attrs |= PVF_REF;
2091 pv->pv_flags |= PVF_REF;
2094 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO;
2100 * We know there is a valid mapping here, so simply
2101 * fix up the L1 if necessary.
2103 pl1pd = &pm->pm_l1->l1_kva[l1idx];
2104 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO;
2105 if (*pl1pd != l1pd) {
2113 * There are bugs in the rev K SA110. This is a check for one
2116 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 &&
2117 curcpu()->ci_arm_cpurev < 3) {
2118 /* Always current pmap */
2119 if (l2pte_valid(pte)) {
2120 extern int kernel_debug;
2121 if (kernel_debug & 1) {
2122 struct proc *p = curlwp->l_proc;
2123 printf("prefetch_abort: page is already "
2124 "mapped - pte=%p *pte=%08x\n", ptep, pte);
2125 printf("prefetch_abort: pc=%08lx proc=%p "
2126 "process=%s\n", va, p, p->p_comm);
2127 printf("prefetch_abort: far=%08x fs=%x\n",
2128 cpu_faultaddress(), cpu_faultstatus());
2131 if (kernel_debug & 2)
2137 #endif /* CPU_SA110 */
2141 * If 'rv == 0' at this point, it generally indicates that there is a
2142 * stale TLB entry for the faulting address. This happens when two or
2143 * more processes are sharing an L1. Since we don't flush the TLB on
2144 * a context switch between such processes, we can take domain faults
2145 * for mappings which exist at the same VA in both processes. EVEN IF
2146 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for
2149 * This is extremely likely to happen if pmap_enter() updated the L1
2150 * entry for a recently entered mapping. In this case, the TLB is
2151 * flushed for the new mapping, but there may still be TLB entries for
2152 * other mappings belonging to other processes in the 1MB range
2153 * covered by the L1 entry.
2155 * Since 'rv == 0', we know that the L1 already contains the correct
2156 * value, so the fault must be due to a stale TLB entry.
2158 * Since we always need to flush the TLB anyway in the case where we
2159 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with
2160 * stale TLB entries dynamically.
2162 * However, the above condition can ONLY happen if the current L1 is
2163 * being shared. If it happens when the L1 is unshared, it indicates
2164 * that other parts of the pmap are not doing their job WRT managing
2167 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) {
2168 extern int last_fault_code;
2169 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n",
2171 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n",
2172 l2, l2b, ptep, pl1pd);
2173 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n",
2174 pte, l1pd, last_fault_code);
2181 cpu_tlb_flushID_SE(va);
2187 vm_page_unlock_queues();
2195 struct l2_bucket *l2b;
2196 struct l1_ttable *l1;
2198 pt_entry_t *ptep, pte;
2199 vm_offset_t va, eva;
2202 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0);
2204 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK);
2206 for (loop = 0; loop < needed; loop++, l1++) {
2207 /* Allocate a L1 page table */
2208 va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0,
2209 0xffffffff, L1_TABLE_SIZE, 0);
2212 panic("Cannot allocate L1 KVM");
2214 eva = va + L1_TABLE_SIZE;
2215 pl1pt = (pd_entry_t *)va;
2218 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2219 ptep = &l2b->l2b_kva[l2pte_index(va)];
2221 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
2224 cpu_tlb_flushD_SE(va);
2228 pmap_init_l1(l1, pl1pt);
2233 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n",
2239 * This is used to stuff certain critical values into the PCB where they
2240 * can be accessed quickly from cpu_switch() et al.
2243 pmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb)
2245 struct l2_bucket *l2b;
2247 pcb->pcb_pagedir = pm->pm_l1->l1_physaddr;
2248 pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) |
2249 (DOMAIN_CLIENT << (pm->pm_domain * 2));
2251 if (vector_page < KERNBASE) {
2252 pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)];
2253 l2b = pmap_get_l2_bucket(pm, vector_page);
2254 pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO |
2255 L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL);
2257 pcb->pcb_pl1vec = NULL;
2261 pmap_activate(struct thread *td)
2266 pm = vmspace_pmap(td->td_proc->p_vmspace);
2270 pmap_set_pcb_pagedir(pm, pcb);
2272 if (td == curthread) {
2273 u_int cur_dacr, cur_ttb;
2275 __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb));
2276 __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr));
2278 cur_ttb &= ~(L1_TABLE_SIZE - 1);
2280 if (cur_ttb == (u_int)pcb->pcb_pagedir &&
2281 cur_dacr == pcb->pcb_dacr) {
2283 * No need to switch address spaces.
2291 * We MUST, I repeat, MUST fix up the L1 entry corresponding
2292 * to 'vector_page' in the incoming L1 table before switching
2293 * to it otherwise subsequent interrupts/exceptions (including
2294 * domain faults!) will jump into hyperspace.
2296 if (pcb->pcb_pl1vec) {
2298 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2300 * Don't need to PTE_SYNC() at this point since
2301 * cpu_setttb() is about to flush both the cache
2306 cpu_domains(pcb->pcb_dacr);
2307 cpu_setttb(pcb->pcb_pagedir);
2313 pmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va)
2315 pd_entry_t *pdep, pde;
2316 pt_entry_t *ptep, pte;
2321 * Make sure the descriptor itself has the correct cache mode
2323 pdep = &kl1[L1_IDX(va)];
2326 if (l1pte_section_p(pde)) {
2327 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) {
2328 *pdep = (pde & ~L1_S_CACHE_MASK) |
2329 pte_l1_s_cache_mode_pt;
2331 cpu_dcache_wbinv_range((vm_offset_t)pdep,
2336 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2337 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2339 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep);
2341 ptep = &ptep[l2pte_index(va)];
2343 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
2344 *ptep = (pte & ~L2_S_CACHE_MASK) |
2345 pte_l2_s_cache_mode_pt;
2347 cpu_dcache_wbinv_range((vm_offset_t)ptep,
2357 pmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap,
2360 vm_offset_t va = *availp;
2361 struct l2_bucket *l2b;
2364 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2366 panic("pmap_alloc_specials: no l2b for 0x%x", va);
2368 *ptep = &l2b->l2b_kva[l2pte_index(va)];
2372 *availp = va + (PAGE_SIZE * pages);
2376 * Bootstrap the system enough to run with virtual memory.
2378 * On the arm this is called after mapping has already been enabled
2379 * and just syncs the pmap module with what has already been done.
2380 * [We can't call it easily with mapping off since the kernel is not
2381 * mapped with PA == VA, hence we would have to relocate every address
2382 * from the linked base (virtual) address "KERNBASE" to the actual
2383 * (physical) address starting relative to 0]
2385 #define PMAP_STATIC_L2_SIZE 16
2386 #ifdef ARM_USE_SMALL_ALLOC
2387 extern struct mtx smallalloc_mtx;
2391 pmap_bootstrap(vm_offset_t firstaddr, vm_offset_t lastaddr, struct pv_addr *l1pt)
2393 static struct l1_ttable static_l1;
2394 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE];
2395 struct l1_ttable *l1 = &static_l1;
2396 struct l2_dtable *l2;
2397 struct l2_bucket *l2b;
2399 pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va;
2404 int l1idx, l2idx, l2next = 0;
2406 PDEBUG(1, printf("firstaddr = %08x, loadaddr = %08x\n",
2407 firstaddr, loadaddr));
2409 virtual_avail = firstaddr;
2410 kernel_pmap = &kernel_pmap_store;
2411 kernel_pmap->pm_l1 = l1;
2412 kernel_l1pa = l1pt->pv_pa;
2415 * Scan the L1 translation table created by initarm() and create
2416 * the required metadata for all valid mappings found in it.
2418 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) {
2419 pde = kernel_l1pt[l1idx];
2422 * We're only interested in Coarse mappings.
2423 * pmap_extract() can deal with section mappings without
2424 * recourse to checking L2 metadata.
2426 if ((pde & L1_TYPE_MASK) != L1_TYPE_C)
2430 * Lookup the KVA of this L2 descriptor table
2432 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2433 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2436 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx",
2437 (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa);
2441 * Fetch the associated L2 metadata structure.
2442 * Allocate a new one if necessary.
2444 if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) {
2445 if (l2next == PMAP_STATIC_L2_SIZE)
2446 panic("pmap_bootstrap: out of static L2s");
2447 kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 =
2448 &static_l2[l2next++];
2452 * One more L1 slot tracked...
2457 * Fill in the details of the L2 descriptor in the
2458 * appropriate bucket.
2460 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2461 l2b->l2b_kva = ptep;
2463 l2b->l2b_l1idx = l1idx;
2466 * Establish an initial occupancy count for this descriptor
2469 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
2471 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) {
2472 l2b->l2b_occupancy++;
2477 * Make sure the descriptor itself has the correct cache mode.
2478 * If not, fix it, but whine about the problem. Port-meisters
2479 * should consider this a clue to fix up their initarm()
2482 if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) {
2483 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2484 "L2 pte @ %p\n", ptep);
2490 * Ensure the primary (kernel) L1 has the correct cache mode for
2491 * a page table. Bitch if it is not correctly set.
2493 for (va = (vm_offset_t)kernel_l1pt;
2494 va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) {
2495 if (pmap_set_pt_cache_mode(kernel_l1pt, va))
2496 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2497 "primary L1 @ 0x%x\n", va);
2500 cpu_dcache_wbinv_all();
2504 PMAP_LOCK_INIT(kernel_pmap);
2505 kernel_pmap->pm_active = -1;
2506 kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL;
2507 TAILQ_INIT(&kernel_pmap->pm_pvlist);
2510 * Reserve some special page table entries/VA space for temporary
2513 #define SYSMAP(c, p, v, n) \
2514 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
2516 pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte);
2517 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte);
2518 pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte);
2519 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte);
2520 size = ((lastaddr - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE;
2521 pmap_alloc_specials(&virtual_avail,
2522 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE,
2523 &pmap_kernel_l2ptp_kva, NULL);
2525 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE;
2526 pmap_alloc_specials(&virtual_avail,
2527 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE,
2528 &pmap_kernel_l2dtable_kva, NULL);
2530 pmap_alloc_specials(&virtual_avail,
2531 1, (vm_offset_t*)&_tmppt, NULL);
2532 SLIST_INIT(&l1_list);
2533 TAILQ_INIT(&l1_lru_list);
2534 mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF);
2535 pmap_init_l1(l1, kernel_l1pt);
2536 cpu_dcache_wbinv_all();
2538 virtual_avail = round_page(virtual_avail);
2539 virtual_end = lastaddr;
2540 kernel_vm_end = pmap_curmaxkvaddr;
2541 arm_nocache_startaddr = lastaddr;
2542 mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF);
2544 #ifdef ARM_USE_SMALL_ALLOC
2545 mtx_init(&smallalloc_mtx, "Small alloc page list", NULL, MTX_DEF);
2546 arm_init_smallalloc();
2548 pmap_set_pcb_pagedir(kernel_pmap, thread0.td_pcb);
2551 /***************************************************
2552 * Pmap allocation/deallocation routines.
2553 ***************************************************/
2556 * Release any resources held by the given physical map.
2557 * Called when a pmap initialized by pmap_pinit is being released.
2558 * Should only be called if the map contains no valid mappings.
2561 pmap_release(pmap_t pmap)
2565 pmap_idcache_wbinv_all(pmap);
2566 pmap_tlb_flushID(pmap);
2568 if (vector_page < KERNBASE) {
2569 struct pcb *curpcb = PCPU_GET(curpcb);
2570 pcb = thread0.td_pcb;
2571 if (pmap_is_current(pmap)) {
2573 * Frob the L1 entry corresponding to the vector
2574 * page so that it contains the kernel pmap's domain
2575 * number. This will ensure pmap_remove() does not
2576 * pull the current vector page out from under us.
2579 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2580 cpu_domains(pcb->pcb_dacr);
2581 cpu_setttb(pcb->pcb_pagedir);
2584 pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE);
2586 * Make sure cpu_switch(), et al, DTRT. This is safe to do
2587 * since this process has no remaining mappings of its own.
2589 curpcb->pcb_pl1vec = pcb->pcb_pl1vec;
2590 curpcb->pcb_l1vec = pcb->pcb_l1vec;
2591 curpcb->pcb_dacr = pcb->pcb_dacr;
2592 curpcb->pcb_pagedir = pcb->pcb_pagedir;
2596 PMAP_LOCK_DESTROY(pmap);
2598 dprintf("pmap_release()\n");
2604 * Helper function for pmap_grow_l2_bucket()
2607 pmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap)
2609 struct l2_bucket *l2b;
2614 pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
2617 pa = VM_PAGE_TO_PHYS(pg);
2622 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2624 ptep = &l2b->l2b_kva[l2pte_index(va)];
2625 *ptep = L2_S_PROTO | pa | cache_mode |
2626 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE);
2632 * This is the same as pmap_alloc_l2_bucket(), except that it is only
2633 * used by pmap_growkernel().
2635 static __inline struct l2_bucket *
2636 pmap_grow_l2_bucket(pmap_t pm, vm_offset_t va)
2638 struct l2_dtable *l2;
2639 struct l2_bucket *l2b;
2640 struct l1_ttable *l1;
2647 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
2649 * No mapping at this address, as there is
2650 * no entry in the L1 table.
2651 * Need to allocate a new l2_dtable.
2653 nva = pmap_kernel_l2dtable_kva;
2654 if ((nva & PAGE_MASK) == 0) {
2656 * Need to allocate a backing page
2658 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2662 l2 = (struct l2_dtable *)nva;
2663 nva += sizeof(struct l2_dtable);
2665 if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva &
2668 * The new l2_dtable straddles a page boundary.
2669 * Map in another page to cover it.
2671 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2675 pmap_kernel_l2dtable_kva = nva;
2678 * Link it into the parent pmap
2680 pm->pm_l2[L2_IDX(l1idx)] = l2;
2681 memset(l2, 0, sizeof(*l2));
2684 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2687 * Fetch pointer to the L2 page table associated with the address.
2689 if (l2b->l2b_kva == NULL) {
2693 * No L2 page table has been allocated. Chances are, this
2694 * is because we just allocated the l2_dtable, above.
2696 nva = pmap_kernel_l2ptp_kva;
2697 ptep = (pt_entry_t *)nva;
2698 if ((nva & PAGE_MASK) == 0) {
2700 * Need to allocate a backing page
2702 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt,
2703 &pmap_kernel_l2ptp_phys))
2705 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t));
2707 memset(ptep, 0, L2_TABLE_SIZE_REAL);
2709 l2b->l2b_kva = ptep;
2710 l2b->l2b_l1idx = l1idx;
2711 l2b->l2b_phys = pmap_kernel_l2ptp_phys;
2713 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL;
2714 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL;
2717 /* Distribute new L1 entry to all other L1s */
2718 SLIST_FOREACH(l1, &l1_list, l1_link) {
2719 pl1pd = &l1->l1_kva[L1_IDX(va)];
2720 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) |
2730 * grow the number of kernel page table entries, if needed
2733 pmap_growkernel(vm_offset_t addr)
2735 pmap_t kpm = pmap_kernel();
2737 if (addr <= pmap_curmaxkvaddr)
2738 return; /* we are OK */
2741 * whoops! we need to add kernel PTPs
2744 /* Map 1MB at a time */
2745 for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE)
2746 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr);
2749 * flush out the cache, expensive but growkernel will happen so
2752 cpu_dcache_wbinv_all();
2755 kernel_vm_end = pmap_curmaxkvaddr;
2761 * Remove all pages from specified address space
2762 * this aids process exit speeds. Also, this code
2763 * is special cased for current process only, but
2764 * can have the more generic (and slightly slower)
2765 * mode enabled. This is much faster than pmap_remove
2766 * in the case of running down an entire address space.
2769 pmap_remove_pages(pmap_t pmap)
2771 struct pv_entry *pv, *npv;
2772 struct l2_bucket *l2b = NULL;
2776 vm_page_lock_queues();
2778 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) {
2779 if (pv->pv_flags & PVF_WIRED) {
2780 /* The page is wired, cannot remove it now. */
2781 npv = TAILQ_NEXT(pv, pv_plist);
2784 pmap->pm_stats.resident_count--;
2785 l2b = pmap_get_l2_bucket(pmap, pv->pv_va);
2786 KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages"));
2787 pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
2788 m = PHYS_TO_VM_PAGE(*pt & L2_ADDR_MASK);
2789 #ifdef ARM_USE_SMALL_ALLOC
2790 KASSERT((vm_offset_t)m >= alloc_firstaddr, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt));
2792 KASSERT((vm_offset_t)m >= KERNBASE, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt));
2796 npv = TAILQ_NEXT(pv, pv_plist);
2797 pmap_nuke_pv(m, pmap, pv);
2798 if (TAILQ_EMPTY(&m->md.pv_list))
2799 vm_page_flag_clear(m, PG_WRITEABLE);
2800 pmap_free_pv_entry(pv);
2802 vm_page_unlock_queues();
2803 cpu_idcache_wbinv_all();
2810 /***************************************************
2811 * Low level mapping routines.....
2812 ***************************************************/
2814 /* Map a section into the KVA. */
2817 pmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags)
2819 pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL,
2820 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
2821 struct l1_ttable *l1;
2823 KASSERT(((va | pa) & L1_S_OFFSET) == 0,
2824 ("Not a valid section mapping"));
2825 if (flags & SECTION_CACHE)
2826 pd |= pte_l1_s_cache_mode;
2827 else if (flags & SECTION_PT)
2828 pd |= pte_l1_s_cache_mode_pt;
2829 SLIST_FOREACH(l1, &l1_list, l1_link) {
2830 l1->l1_kva[L1_IDX(va)] = pd;
2831 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2836 * add a wired page to the kva
2837 * note that in order for the mapping to take effect -- you
2838 * should do a invltlb after doing the pmap_kenter...
2840 static PMAP_INLINE void
2841 pmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags)
2843 struct l2_bucket *l2b;
2846 PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n",
2847 (uint32_t) va, (uint32_t) pa));
2850 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2852 l2b = pmap_grow_l2_bucket(pmap_kernel(), va);
2853 KASSERT(l2b != NULL, ("No L2 Bucket"));
2854 pte = &l2b->l2b_kva[l2pte_index(va)];
2856 PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n",
2857 (uint32_t) pte, opte, *pte));
2858 if (l2pte_valid(opte)) {
2859 cpu_dcache_wbinv_range(va, PAGE_SIZE);
2860 cpu_tlb_flushD_SE(va);
2864 l2b->l2b_occupancy++;
2866 *pte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL,
2867 VM_PROT_READ | VM_PROT_WRITE);
2868 if (flags & KENTER_CACHE)
2869 *pte |= pte_l2_s_cache_mode;
2870 if (flags & KENTER_USER)
2871 *pte |= L2_S_PROT_U;
2876 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2878 pmap_kenter_internal(va, pa, KENTER_CACHE);
2882 pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa)
2885 pmap_kenter_internal(va, pa, 0);
2889 pmap_kenter_user(vm_offset_t va, vm_paddr_t pa)
2892 pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER);
2894 * Call pmap_fault_fixup now, to make sure we'll have no exception
2895 * at the first use of the new address, or bad things will happen,
2896 * as we use one of these addresses in the exception handlers.
2898 pmap_fault_fixup(pmap_kernel(), va, VM_PROT_READ|VM_PROT_WRITE, 1);
2902 * remove a page rom the kernel pagetables
2905 pmap_kremove(vm_offset_t va)
2907 struct l2_bucket *l2b;
2908 pt_entry_t *pte, opte;
2910 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2913 KASSERT(l2b != NULL, ("No L2 Bucket"));
2914 pte = &l2b->l2b_kva[l2pte_index(va)];
2916 if (l2pte_valid(opte)) {
2917 cpu_dcache_wbinv_range(va, PAGE_SIZE);
2918 cpu_tlb_flushD_SE(va);
2926 * Used to map a range of physical addresses into kernel
2927 * virtual address space.
2929 * The value passed in '*virt' is a suggested virtual address for
2930 * the mapping. Architectures which can support a direct-mapped
2931 * physical to virtual region can return the appropriate address
2932 * within that region, leaving '*virt' unchanged. Other
2933 * architectures should map the pages starting at '*virt' and
2934 * update '*virt' with the first usable address after the mapped
2938 pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot)
2940 #ifdef ARM_USE_SMALL_ALLOC
2941 return (arm_ptovirt(start));
2943 vm_offset_t sva = *virt;
2944 vm_offset_t va = sva;
2946 PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, "
2947 "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end,
2950 while (start < end) {
2951 pmap_kenter(va, start);
2961 pmap_wb_page(vm_page_t m)
2963 struct pv_entry *pv;
2965 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
2966 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, FALSE,
2967 (pv->pv_flags & PVF_WRITE) == 0);
2971 pmap_inv_page(vm_page_t m)
2973 struct pv_entry *pv;
2975 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
2976 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, TRUE, TRUE);
2979 * Add a list of wired pages to the kva
2980 * this routine is only used for temporary
2981 * kernel mappings that do not need to have
2982 * page modification or references recorded.
2983 * Note that old mappings are simply written
2984 * over. The page *must* be wired.
2987 pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
2991 for (i = 0; i < count; i++) {
2993 pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]),
3001 * this routine jerks page mappings from the
3002 * kernel -- it is meant only for temporary mappings.
3005 pmap_qremove(vm_offset_t va, int count)
3010 for (i = 0; i < count; i++) {
3013 pmap_inv_page(PHYS_TO_VM_PAGE(pa));
3022 * pmap_object_init_pt preloads the ptes for a given object
3023 * into the specified pmap. This eliminates the blast of soft
3024 * faults on process startup and immediately after an mmap.
3027 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3028 vm_pindex_t pindex, vm_size_t size)
3031 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
3032 KASSERT(object->type == OBJT_DEVICE,
3033 ("pmap_object_init_pt: non-device object"));
3038 * pmap_is_prefaultable:
3040 * Return whether or not the specified virtual address is elgible
3044 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3049 if (!pmap_get_pde_pte(pmap, addr, &pde, &pte))
3051 KASSERT(pte != NULL, ("Valid mapping but no pte ?"));
3058 * Fetch pointers to the PDE/PTE for the given pmap/VA pair.
3059 * Returns TRUE if the mapping exists, else FALSE.
3061 * NOTE: This function is only used by a couple of arm-specific modules.
3062 * It is not safe to take any pmap locks here, since we could be right
3063 * in the middle of debugging the pmap anyway...
3065 * It is possible for this routine to return FALSE even though a valid
3066 * mapping does exist. This is because we don't lock, so the metadata
3067 * state may be inconsistent.
3069 * NOTE: We can return a NULL *ptp in the case where the L1 pde is
3070 * a "section" mapping.
3073 pmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp)
3075 struct l2_dtable *l2;
3076 pd_entry_t *pl1pd, l1pd;
3080 if (pm->pm_l1 == NULL)
3084 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx];
3087 if (l1pte_section_p(l1pd)) {
3092 if (pm->pm_l2 == NULL)
3095 l2 = pm->pm_l2[L2_IDX(l1idx)];
3098 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3102 *ptp = &ptep[l2pte_index(va)];
3107 * Routine: pmap_remove_all
3109 * Removes this physical page from
3110 * all physical maps in which it resides.
3111 * Reflects back modify bits to the pager.
3114 * Original versions of this routine were very
3115 * inefficient because they iteratively called
3116 * pmap_remove (slow...)
3119 pmap_remove_all(vm_page_t m)
3122 pt_entry_t *ptep, pte;
3123 struct l2_bucket *l2b;
3124 boolean_t flush = FALSE;
3128 #if defined(PMAP_DEBUG)
3130 * XXX this makes pmap_page_protect(NONE) illegal for non-managed
3133 if (m->flags & PG_FICTITIOUS) {
3134 panic("pmap_page_protect: illegal for unmanaged page, va: 0x%x", VM_PAGE_TO_PHYS(m));
3138 if (TAILQ_EMPTY(&m->md.pv_list))
3140 curpm = vmspace_pmap(curproc->p_vmspace);
3141 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3142 if (flush == FALSE && (pv->pv_pmap == curpm ||
3143 pv->pv_pmap == pmap_kernel()))
3145 PMAP_LOCK(pv->pv_pmap);
3146 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
3147 KASSERT(l2b != NULL, ("No l2 bucket"));
3148 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
3151 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
3152 pmap_free_l2_bucket(pv->pv_pmap, l2b, 1);
3153 if (pv->pv_flags & PVF_WIRED)
3154 pv->pv_pmap->pm_stats.wired_count--;
3155 pv->pv_pmap->pm_stats.resident_count--;
3156 flags |= pv->pv_flags;
3157 pmap_nuke_pv(m, pv->pv_pmap, pv);
3158 PMAP_UNLOCK(pv->pv_pmap);
3159 pmap_free_pv_entry(pv);
3163 if (PV_BEEN_EXECD(flags))
3164 pmap_tlb_flushID(curpm);
3166 pmap_tlb_flushD(curpm);
3168 vm_page_flag_clear(m, PG_WRITEABLE);
3173 * Set the physical protection on the
3174 * specified range of this map as requested.
3177 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3179 struct l2_bucket *l2b;
3180 pt_entry_t *ptep, pte;
3181 vm_offset_t next_bucket;
3185 if ((prot & VM_PROT_READ) == 0) {
3186 pmap_remove(pm, sva, eva);
3190 if (prot & VM_PROT_WRITE) {
3192 * If this is a read->write transition, just ignore it and let
3193 * vm_fault() take care of it later.
3198 vm_page_lock_queues();
3202 * OK, at this point, we know we're doing write-protect operation.
3203 * If the pmap is active, write-back the range.
3205 pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE);
3207 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1;
3211 next_bucket = L2_NEXT_BUCKET(sva);
3212 if (next_bucket > eva)
3215 l2b = pmap_get_l2_bucket(pm, sva);
3221 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3223 while (sva < next_bucket) {
3224 if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) {
3228 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
3229 pte &= ~L2_S_PROT_W;
3234 f = pmap_modify_pv(pg, pm, sva,
3236 pmap_vac_me_harder(pg, pm, sva);
3239 f = PVF_REF | PVF_EXEC;
3245 if (PV_BEEN_EXECD(f))
3246 pmap_tlb_flushID_SE(pm, sva);
3248 if (PV_BEEN_REFD(f))
3249 pmap_tlb_flushD_SE(pm, sva);
3259 if (PV_BEEN_EXECD(flags))
3260 pmap_tlb_flushID(pm);
3262 if (PV_BEEN_REFD(flags))
3263 pmap_tlb_flushD(pm);
3265 vm_page_unlock_queues();
3272 * Insert the given physical page (p) at
3273 * the specified virtual address (v) in the
3274 * target physical map with the protection requested.
3276 * If specified, the page will be wired down, meaning
3277 * that the related pte can not be reclaimed.
3279 * NB: This is the only routine which MAY NOT lazy-evaluate
3280 * or lose information. That is, this routine must actually
3281 * insert this page into the given map NOW.
3285 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3289 vm_page_lock_queues();
3291 pmap_enter_locked(pmap, va, m, prot, wired, M_WAITOK);
3292 vm_page_unlock_queues();
3297 * The page queues and pmap must be locked.
3300 pmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3301 boolean_t wired, int flags)
3303 struct l2_bucket *l2b = NULL;
3304 struct vm_page *opg;
3305 struct pv_entry *pve = NULL;
3306 pt_entry_t *ptep, npte, opte;
3311 PMAP_ASSERT_LOCKED(pmap);
3312 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3313 if (va == vector_page) {
3314 pa = systempage.pv_pa;
3317 pa = VM_PAGE_TO_PHYS(m);
3319 if (prot & VM_PROT_WRITE)
3320 nflags |= PVF_WRITE;
3321 if (prot & VM_PROT_EXECUTE)
3324 nflags |= PVF_WIRED;
3325 PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, "
3326 "wired = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, wired));
3328 if (pmap == pmap_kernel()) {
3329 l2b = pmap_get_l2_bucket(pmap, va);
3331 l2b = pmap_grow_l2_bucket(pmap, va);
3334 l2b = pmap_alloc_l2_bucket(pmap, va);
3336 if (flags & M_WAITOK) {
3338 vm_page_unlock_queues();
3340 vm_page_lock_queues();
3348 ptep = &l2b->l2b_kva[l2pte_index(va)];
3355 * There is already a mapping at this address.
3356 * If the physical address is different, lookup the
3359 if (l2pte_pa(opte) != pa)
3360 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte));
3366 if ((prot & (VM_PROT_ALL)) ||
3367 (!m || m->md.pvh_attrs & PVF_REF)) {
3369 * - The access type indicates that we don't need
3370 * to do referenced emulation.
3372 * - The physical page has already been referenced
3373 * so no need to re-do referenced emulation here.
3379 if (m && ((prot & VM_PROT_WRITE) != 0 ||
3380 (m->md.pvh_attrs & PVF_MOD))) {
3382 * This is a writable mapping, and the
3383 * page's mod state indicates it has
3384 * already been modified. Make it
3385 * writable from the outset.
3388 if (!(m->md.pvh_attrs & PVF_MOD))
3392 vm_page_flag_set(m, PG_REFERENCED);
3395 * Need to do page referenced emulation.
3397 npte |= L2_TYPE_INV;
3400 if (prot & VM_PROT_WRITE)
3401 npte |= L2_S_PROT_W;
3402 npte |= pte_l2_s_cache_mode;
3403 if (m && m == opg) {
3405 * We're changing the attrs of an existing mapping.
3407 oflags = pmap_modify_pv(m, pmap, va,
3408 PVF_WRITE | PVF_EXEC | PVF_WIRED |
3409 PVF_MOD | PVF_REF, nflags);
3412 * We may need to flush the cache if we're
3415 if (pmap_is_current(pmap) &&
3416 (oflags & PVF_NC) == 0 &&
3417 (opte & L2_S_PROT_W) != 0 &&
3418 (prot & VM_PROT_WRITE) == 0)
3419 cpu_dcache_wb_range(va, PAGE_SIZE);
3422 * New mapping, or changing the backing page
3423 * of an existing mapping.
3427 * Replacing an existing mapping with a new one.
3428 * It is part of our managed memory so we
3429 * must remove it from the PV list
3431 pve = pmap_remove_pv(opg, pmap, va);
3432 if (m && (m->flags & (PG_UNMANAGED | PG_FICTITIOUS)) &&
3434 pmap_free_pv_entry(pve);
3436 !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS)))
3437 pve = pmap_get_pv_entry();
3438 KASSERT(pve != NULL, ("No pv"));
3439 oflags = pve->pv_flags;
3442 * If the old mapping was valid (ref/mod
3443 * emulation creates 'invalid' mappings
3444 * initially) then make sure to frob
3447 if ((oflags & PVF_NC) == 0 &&
3448 l2pte_valid(opte)) {
3449 if (PV_BEEN_EXECD(oflags)) {
3450 pmap_idcache_wbinv_range(pmap, va,
3453 if (PV_BEEN_REFD(oflags)) {
3454 pmap_dcache_wb_range(pmap, va,
3456 (oflags & PVF_WRITE) == 0);
3459 } else if (m && !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS)))
3460 if ((pve = pmap_get_pv_entry()) == NULL) {
3461 panic("pmap_enter: no pv entries");
3463 if (m && !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS))) {
3464 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3465 ("pmap_enter: managed mapping within the clean submap"));
3466 pmap_enter_pv(m, pve, pmap, va, nflags);
3470 * Make sure userland mappings get the right permissions
3472 if (pmap != pmap_kernel() && va != vector_page) {
3473 npte |= L2_S_PROT_U;
3477 * Keep the stats up to date
3480 l2b->l2b_occupancy++;
3481 pmap->pm_stats.resident_count++;
3486 * If this is just a wiring change, the two PTEs will be
3487 * identical, so there's no need to update the page table.
3490 boolean_t is_cached = pmap_is_current(pmap);
3495 * We only need to frob the cache/tlb if this pmap
3499 if (L1_IDX(va) != L1_IDX(vector_page) &&
3500 l2pte_valid(npte)) {
3502 * This mapping is likely to be accessed as
3503 * soon as we return to userland. Fix up the
3504 * L1 entry to avoid taking another
3505 * page/domain fault.
3507 pd_entry_t *pl1pd, l1pd;
3509 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
3510 l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) |
3512 if (*pl1pd != l1pd) {
3519 if (PV_BEEN_EXECD(oflags))
3520 pmap_tlb_flushID_SE(pmap, va);
3521 else if (PV_BEEN_REFD(oflags))
3522 pmap_tlb_flushD_SE(pmap, va);
3526 pmap_vac_me_harder(m, pmap, va);
3531 * Maps a sequence of resident pages belonging to the same object.
3532 * The sequence begins with the given page m_start. This page is
3533 * mapped at the given virtual address start. Each subsequent page is
3534 * mapped at a virtual address that is offset from start by the same
3535 * amount as the page is offset from m_start within the object. The
3536 * last page in the sequence is the page with the largest offset from
3537 * m_start that can be mapped at a virtual address less than the given
3538 * virtual address end. Not every virtual page between start and end
3539 * is mapped; only those for which a resident page exists with the
3540 * corresponding offset from m_start are mapped.
3543 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3544 vm_page_t m_start, vm_prot_t prot)
3547 vm_pindex_t diff, psize;
3549 psize = atop(end - start);
3552 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3553 pmap_enter_locked(pmap, start + ptoa(diff), m, prot &
3554 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE, M_NOWAIT);
3555 m = TAILQ_NEXT(m, listq);
3561 * this code makes some *MAJOR* assumptions:
3562 * 1. Current pmap & pmap exists.
3565 * 4. No page table pages.
3566 * but is *MUCH* faster than pmap_enter...
3570 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3574 pmap_enter_locked(pmap, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
3580 * Routine: pmap_change_wiring
3581 * Function: Change the wiring attribute for a map/virtual-address
3583 * In/out conditions:
3584 * The mapping must already exist in the pmap.
3587 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
3589 struct l2_bucket *l2b;
3590 pt_entry_t *ptep, pte;
3593 vm_page_lock_queues();
3595 l2b = pmap_get_l2_bucket(pmap, va);
3596 KASSERT(l2b, ("No l2b bucket in pmap_change_wiring"));
3597 ptep = &l2b->l2b_kva[l2pte_index(va)];
3599 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
3601 pmap_modify_pv(pg, pmap, va, PVF_WIRED, wired);
3602 vm_page_unlock_queues();
3608 * Copy the range specified by src_addr/len
3609 * from the source map to the range dst_addr/len
3610 * in the destination map.
3612 * This routine is only advisory and need not do anything.
3615 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
3616 vm_size_t len, vm_offset_t src_addr)
3622 * Routine: pmap_extract
3624 * Extract the physical page address associated
3625 * with the given map/virtual_address pair.
3628 pmap_extract(pmap_t pm, vm_offset_t va)
3630 struct l2_dtable *l2;
3632 pt_entry_t *ptep, pte;
3638 l1pd = pm->pm_l1->l1_kva[l1idx];
3639 if (l1pte_section_p(l1pd)) {
3641 * These should only happen for pmap_kernel()
3643 KASSERT(pm == pmap_kernel(), ("huh"));
3644 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3647 * Note that we can't rely on the validity of the L1
3648 * descriptor as an indication that a mapping exists.
3649 * We have to look it up in the L2 dtable.
3651 l2 = pm->pm_l2[L2_IDX(l1idx)];
3654 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3659 ptep = &ptep[l2pte_index(va)];
3667 switch (pte & L2_TYPE_MASK) {
3669 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3673 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3683 * Atomically extract and hold the physical page with the given
3684 * pmap and virtual address pair if that mapping permits the given
3689 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3691 struct l2_dtable *l2;
3693 pt_entry_t *ptep, pte;
3699 vm_page_lock_queues();
3701 l1pd = pmap->pm_l1->l1_kva[l1idx];
3702 if (l1pte_section_p(l1pd)) {
3704 * These should only happen for pmap_kernel()
3706 KASSERT(pmap == pmap_kernel(), ("huh"));
3707 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3708 if (l1pd & L1_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3709 m = PHYS_TO_VM_PAGE(pa);
3715 * Note that we can't rely on the validity of the L1
3716 * descriptor as an indication that a mapping exists.
3717 * We have to look it up in the L2 dtable.
3719 l2 = pmap->pm_l2[L2_IDX(l1idx)];
3722 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3724 vm_page_unlock_queues();
3728 ptep = &ptep[l2pte_index(va)];
3733 vm_page_unlock_queues();
3736 if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3737 switch (pte & L2_TYPE_MASK) {
3739 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3743 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3746 m = PHYS_TO_VM_PAGE(pa);
3752 vm_page_unlock_queues();
3757 * Initialize a preallocated and zeroed pmap structure,
3758 * such as one in a vmspace structure.
3762 pmap_pinit(pmap_t pmap)
3764 PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap));
3766 PMAP_LOCK_INIT(pmap);
3767 pmap_alloc_l1(pmap);
3768 bzero(pmap->pm_l2, sizeof(pmap->pm_l2));
3771 pmap->pm_active = 0;
3773 TAILQ_INIT(&pmap->pm_pvlist);
3774 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3775 pmap->pm_stats.resident_count = 1;
3776 if (vector_page < KERNBASE) {
3777 pmap_enter(pmap, vector_page, PHYS_TO_VM_PAGE(systempage.pv_pa),
3783 /***************************************************
3784 * page management routines.
3785 ***************************************************/
3789 pmap_free_pv_entry(pv_entry_t pv)
3792 uma_zfree(pvzone, pv);
3797 * get a new pv_entry, allocating a block from the system
3799 * the memory allocation is performed bypassing the malloc code
3800 * because of the possibility of allocations at interrupt time.
3803 pmap_get_pv_entry(void)
3805 pv_entry_t ret_value;
3808 if (pv_entry_count > pv_entry_high_water)
3809 pagedaemon_wakeup();
3810 ret_value = uma_zalloc(pvzone, M_NOWAIT);
3816 * Remove the given range of addresses from the specified map.
3818 * It is assumed that the start and end are properly
3819 * rounded to the page size.
3821 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3
3823 pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva)
3825 struct l2_bucket *l2b;
3826 vm_offset_t next_bucket;
3828 u_int cleanlist_idx, total, cnt;
3832 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE];
3833 u_int mappings, is_exec, is_refd;
3838 * we lock in the pmap => pv_head direction
3841 vm_page_lock_queues();
3843 if (!pmap_is_current(pm)) {
3844 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1;
3851 * Do one L2 bucket's worth at a time.
3853 next_bucket = L2_NEXT_BUCKET(sva);
3854 if (next_bucket > eva)
3857 l2b = pmap_get_l2_bucket(pm, sva);
3863 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3866 while (sva < next_bucket) {
3875 * Nothing here, move along
3882 pm->pm_stats.resident_count--;
3888 * Update flags. In a number of circumstances,
3889 * we could cluster a lot of these and do a
3890 * number of sequential pages in one go.
3892 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) {
3893 struct pv_entry *pve;
3895 pve = pmap_remove_pv(pg, pm, sva);
3897 is_exec = PV_BEEN_EXECD(pve->pv_flags);
3898 is_refd = PV_BEEN_REFD(pve->pv_flags);
3899 pmap_free_pv_entry(pve);
3903 if (!l2pte_valid(pte)) {
3905 PTE_SYNC_CURRENT(pm, ptep);
3912 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) {
3913 /* Add to the clean list. */
3914 cleanlist[cleanlist_idx].pte = ptep;
3915 cleanlist[cleanlist_idx].va =
3916 sva | (is_exec & 1);
3919 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) {
3920 /* Nuke everything if needed. */
3921 pmap_idcache_wbinv_all(pm);
3922 pmap_tlb_flushID(pm);
3925 * Roll back the previous PTE list,
3926 * and zero out the current PTE.
3929 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) {
3930 *cleanlist[cnt].pte = 0;
3940 pmap_tlb_flushID_SE(pm, sva);
3943 pmap_tlb_flushD_SE(pm, sva);
3952 * Deal with any left overs
3954 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) {
3955 total += cleanlist_idx;
3956 for (cnt = 0; cnt < cleanlist_idx; cnt++) {
3958 cleanlist[cnt].va & ~1;
3959 if (cleanlist[cnt].va & 1) {
3960 pmap_idcache_wbinv_range(pm,
3962 pmap_tlb_flushID_SE(pm, clva);
3964 pmap_dcache_wb_range(pm,
3965 clva, PAGE_SIZE, TRUE,
3967 pmap_tlb_flushD_SE(pm, clva);
3969 *cleanlist[cnt].pte = 0;
3970 PTE_SYNC_CURRENT(pm, cleanlist[cnt].pte);
3973 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE)
3977 * We are removing so much entries it's just
3978 * easier to flush the whole cache.
3980 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1;
3981 pmap_idcache_wbinv_all(pm);
3986 pmap_free_l2_bucket(pm, l2b, mappings);
3989 vm_page_unlock_queues();
4001 * Zero a given physical page by mapping it at a page hook point.
4002 * In doing the zero page op, the page we zero is mapped cachable, as with
4003 * StrongARM accesses to non-cached pages are non-burst making writing
4004 * _any_ bulk data very slow.
4006 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
4008 pmap_zero_page_generic(vm_paddr_t phys, int off, int size)
4010 #ifdef ARM_USE_SMALL_ALLOC
4015 struct vm_page *pg = PHYS_TO_VM_PAGE(phys);
4017 if (pg->md.pvh_list != NULL)
4018 panic("pmap_zero_page: page has mappings");
4022 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0)
4025 #ifdef ARM_USE_SMALL_ALLOC
4026 dstpg = (char *)arm_ptovirt(phys);
4027 if (off || size != PAGE_SIZE) {
4028 bzero(dstpg + off, size);
4029 cpu_dcache_wbinv_range((vm_offset_t)(dstpg + off), size);
4031 bzero_page((vm_offset_t)dstpg);
4032 cpu_dcache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE);
4038 * Hook in the page, zero it, and purge the cache for that
4039 * zeroed page. Invalidate the TLB as needed.
4041 *cdst_pte = L2_S_PROTO | phys |
4042 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
4044 cpu_tlb_flushD_SE(cdstp);
4046 if (off || size != PAGE_SIZE) {
4047 bzero((void *)(cdstp + off), size);
4048 cpu_dcache_wbinv_range(cdstp + off, size);
4051 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE);
4056 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
4058 #if ARM_MMU_XSCALE == 1
4060 pmap_zero_page_xscale(vm_paddr_t phys, int off, int size)
4063 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0)
4067 * Hook in the page, zero it, and purge the cache for that
4068 * zeroed page. Invalidate the TLB as needed.
4070 *cdst_pte = L2_S_PROTO | phys |
4071 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4072 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4074 cpu_tlb_flushD_SE(cdstp);
4076 if (off || size != PAGE_SIZE)
4077 bzero((void *)(cdstp + off), size);
4081 xscale_cache_clean_minidata();
4085 * Change the PTEs for the specified kernel mappings such that they
4086 * will use the mini data cache instead of the main data cache.
4089 pmap_use_minicache(vm_offset_t va, vm_size_t size)
4091 struct l2_bucket *l2b;
4092 pt_entry_t *ptep, *sptep, pte;
4093 vm_offset_t next_bucket, eva;
4096 if (xscale_use_minidata == 0)
4103 next_bucket = L2_NEXT_BUCKET(va);
4104 if (next_bucket > eva)
4107 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
4109 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)];
4111 while (va < next_bucket) {
4113 if (!l2pte_minidata(pte)) {
4114 cpu_dcache_wbinv_range(va, PAGE_SIZE);
4115 cpu_tlb_flushD_SE(va);
4116 *ptep = pte & ~L2_B;
4121 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep));
4125 #endif /* ARM_MMU_XSCALE == 1 */
4128 * pmap_zero_page zeros the specified hardware page by mapping
4129 * the page into KVM and using bzero to clear its contents.
4132 pmap_zero_page(vm_page_t m)
4134 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), 0, PAGE_SIZE);
4139 * pmap_zero_page_area zeros the specified hardware page by mapping
4140 * the page into KVM and using bzero to clear its contents.
4142 * off and size may not cover an area beyond a single hardware page.
4145 pmap_zero_page_area(vm_page_t m, int off, int size)
4148 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), off, size);
4153 * pmap_zero_page_idle zeros the specified hardware page by mapping
4154 * the page into KVM and using bzero to clear its contents. This
4155 * is intended to be called from the vm_pagezero process only and
4159 pmap_zero_page_idle(vm_page_t m)
4169 * This is a local function used to work out the best strategy to clean
4170 * a single page referenced by its entry in the PV table. It's used by
4171 * pmap_copy_page, pmap_zero page and maybe some others later on.
4173 * Its policy is effectively:
4174 * o If there are no mappings, we don't bother doing anything with the cache.
4175 * o If there is one mapping, we clean just that page.
4176 * o If there are multiple mappings, we clean the entire cache.
4178 * So that some functions can be further optimised, it returns 0 if it didn't
4179 * clean the entire cache, or 1 if it did.
4181 * XXX One bug in this routine is that if the pv_entry has a single page
4182 * mapped at 0x00000000 a whole cache clean will be performed rather than
4183 * just the 1 page. Since this should not occur in everyday use and if it does
4184 * it will just result in not the most efficient clean for the page.
4187 pmap_clean_page(struct pv_entry *pv, boolean_t is_src)
4189 pmap_t pm, pm_to_clean = NULL;
4190 struct pv_entry *npv;
4191 u_int cache_needs_cleaning = 0;
4193 vm_offset_t page_to_clean = 0;
4196 /* nothing mapped in so nothing to flush */
4201 * Since we flush the cache each time we change to a different
4202 * user vmspace, we only need to flush the page if it is in the
4206 pm = vmspace_pmap(curproc->p_vmspace);
4210 for (npv = pv; npv; npv = TAILQ_NEXT(npv, pv_list)) {
4211 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) {
4212 flags |= npv->pv_flags;
4214 * The page is mapped non-cacheable in
4215 * this map. No need to flush the cache.
4217 if (npv->pv_flags & PVF_NC) {
4219 if (cache_needs_cleaning)
4220 panic("pmap_clean_page: "
4221 "cache inconsistency");
4224 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0)
4226 if (cache_needs_cleaning) {
4230 page_to_clean = npv->pv_va;
4231 pm_to_clean = npv->pv_pmap;
4233 cache_needs_cleaning = 1;
4236 if (page_to_clean) {
4237 if (PV_BEEN_EXECD(flags))
4238 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean,
4241 pmap_dcache_wb_range(pm_to_clean, page_to_clean,
4242 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0);
4243 } else if (cache_needs_cleaning) {
4244 if (PV_BEEN_EXECD(flags))
4245 pmap_idcache_wbinv_all(pm);
4247 pmap_dcache_wbinv_all(pm);
4255 * pmap_copy_page copies the specified (machine independent)
4256 * page by mapping the page into virtual memory and using
4257 * bcopy to copy the page, one machine dependent page at a
4264 * Copy one physical page into another, by mapping the pages into
4265 * hook points. The same comment regarding cachability as in
4266 * pmap_zero_page also applies here.
4268 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
4270 pmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst)
4273 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4276 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst);
4278 if (dst_pg->md.pvh_list != NULL)
4279 panic("pmap_copy_page: dst page has mappings");
4284 * Clean the source page. Hold the source page's lock for
4285 * the duration of the copy so that no other mappings can
4286 * be created while we have a potentially aliased mapping.
4290 * XXX: Not needed while we call cpu_dcache_wbinv_all() in
4293 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4296 * Map the pages into the page hook points, copy them, and purge
4297 * the cache for the appropriate page. Invalidate the TLB
4301 *csrc_pte = L2_S_PROTO | src |
4302 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
4304 *cdst_pte = L2_S_PROTO | dst |
4305 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
4307 cpu_tlb_flushD_SE(csrcp);
4308 cpu_tlb_flushD_SE(cdstp);
4310 bcopy_page(csrcp, cdstp);
4312 cpu_dcache_inv_range(csrcp, PAGE_SIZE);
4313 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE);
4315 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
4317 #if ARM_MMU_XSCALE == 1
4319 pmap_copy_page_xscale(vm_paddr_t src, vm_paddr_t dst)
4322 /* XXX: Only needed for pmap_clean_page(), which is commented out. */
4323 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4326 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst);
4328 if (dst_pg->md.pvh_list != NULL)
4329 panic("pmap_copy_page: dst page has mappings");
4334 * Clean the source page. Hold the source page's lock for
4335 * the duration of the copy so that no other mappings can
4336 * be created while we have a potentially aliased mapping.
4340 * XXX: Not needed while we call cpu_dcache_wbinv_all() in
4343 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4346 * Map the pages into the page hook points, copy them, and purge
4347 * the cache for the appropriate page. Invalidate the TLB
4351 *csrc_pte = L2_S_PROTO | src |
4352 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
4353 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4355 *cdst_pte = L2_S_PROTO | dst |
4356 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4357 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4359 cpu_tlb_flushD_SE(csrcp);
4360 cpu_tlb_flushD_SE(cdstp);
4362 bcopy_page(csrcp, cdstp);
4364 xscale_cache_clean_minidata();
4366 #endif /* ARM_MMU_XSCALE == 1 */
4369 pmap_copy_page(vm_page_t src, vm_page_t dst)
4371 #ifdef ARM_USE_SMALL_ALLOC
4372 vm_offset_t srcpg, dstpg;
4375 cpu_dcache_wbinv_all();
4377 _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst),
4378 (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0)
4380 #ifdef ARM_USE_SMALL_ALLOC
4381 srcpg = arm_ptovirt(VM_PAGE_TO_PHYS(src));
4382 dstpg = arm_ptovirt(VM_PAGE_TO_PHYS(dst));
4383 bcopy_page(srcpg, dstpg);
4384 cpu_dcache_wbinv_range(dstpg, PAGE_SIZE);
4386 pmap_copy_page_func(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst));
4394 * this routine returns true if a physical page resides
4395 * in the given pmap.
4398 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4403 if (m->flags & PG_FICTITIOUS)
4407 * Not found, check current mappings returning immediately
4409 for (pv = TAILQ_FIRST(&m->md.pv_list);
4411 pv = TAILQ_NEXT(pv, pv_list)) {
4412 if (pv->pv_pmap == pmap) {
4424 * pmap_ts_referenced:
4426 * Return the count of reference bits for a page, clearing all of them.
4429 pmap_ts_referenced(vm_page_t m)
4431 return (pmap_clearbit(m, PVF_REF));
4436 pmap_is_modified(vm_page_t m)
4439 if (m->md.pvh_attrs & PVF_MOD)
4447 * Clear the modify bits on the specified physical page.
4450 pmap_clear_modify(vm_page_t m)
4453 if (m->md.pvh_attrs & PVF_MOD)
4454 pmap_clearbit(m, PVF_MOD);
4459 * pmap_clear_reference:
4461 * Clear the reference bit on the specified physical page.
4464 pmap_clear_reference(vm_page_t m)
4467 if (m->md.pvh_attrs & PVF_REF)
4468 pmap_clearbit(m, PVF_REF);
4473 * Clear the write and modified bits in each of the given page's mappings.
4476 pmap_remove_write(vm_page_t m)
4479 if (m->flags & PG_WRITEABLE)
4480 pmap_clearbit(m, PVF_WRITE);
4485 * perform the pmap work for mincore
4488 pmap_mincore(pmap_t pmap, vm_offset_t addr)
4490 printf("pmap_mincore()\n");
4497 pmap_addr_hint(vm_object_t obj, vm_offset_t addr, vm_size_t size)
4505 * Map a set of physical memory pages into the kernel virtual
4506 * address space. Return a pointer to where it is mapped. This
4507 * routine is intended to be used for mapping device memory,
4511 pmap_mapdev(vm_offset_t pa, vm_size_t size)
4513 vm_offset_t va, tmpva, offset;
4515 offset = pa & PAGE_MASK;
4516 size = roundup(size, PAGE_SIZE);
4520 va = kmem_alloc_nofault(kernel_map, size);
4522 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
4523 for (tmpva = va; size > 0;) {
4524 pmap_kenter_internal(tmpva, pa, 0);
4530 return ((void *)(va + offset));
4533 #define BOOTSTRAP_DEBUG
4538 * Create a single section mapping.
4541 pmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4542 int prot, int cache)
4544 pd_entry_t *pde = (pd_entry_t *) l1pt;
4547 KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2"));
4556 fl = pte_l1_s_cache_mode;
4560 fl = pte_l1_s_cache_mode_pt;
4564 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4565 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL);
4566 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4573 * Link the L2 page table specified by l2pv.pv_pa into the L1
4574 * page table at the slot for "va".
4577 pmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv)
4579 pd_entry_t *pde = (pd_entry_t *) l1pt, proto;
4580 u_int slot = va >> L1_S_SHIFT;
4582 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO;
4584 #ifdef VERBOSE_INIT_ARM
4585 printf("pmap_link_l2pt: pa=0x%x va=0x%x\n", l2pv->pv_pa, l2pv->pv_va);
4588 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000);
4590 PTE_SYNC(&pde[slot]);
4592 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list);
4600 * Create a single page mapping.
4603 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot,
4606 pd_entry_t *pde = (pd_entry_t *) l1pt;
4610 KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin"));
4619 fl = pte_l2_s_cache_mode;
4623 fl = pte_l2_s_cache_mode_pt;
4627 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4628 panic("pmap_map_entry: no L2 table for VA 0x%08x", va);
4630 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4633 panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va);
4635 pte[l2pte_index(va)] =
4636 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl;
4637 PTE_SYNC(&pte[l2pte_index(va)]);
4643 * Map a chunk of memory using the most efficient mappings
4644 * possible (section. large page, small page) into the
4645 * provided L1 and L2 tables at the specified virtual address.
4648 pmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4649 vm_size_t size, int prot, int cache)
4651 pd_entry_t *pde = (pd_entry_t *) l1pt;
4652 pt_entry_t *pte, f1, f2s, f2l;
4656 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
4659 panic("pmap_map_chunk: no L1 table provided");
4661 #ifdef VERBOSE_INIT_ARM
4662 printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x "
4663 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache);
4675 f1 = pte_l1_s_cache_mode;
4676 f2l = pte_l2_l_cache_mode;
4677 f2s = pte_l2_s_cache_mode;
4681 f1 = pte_l1_s_cache_mode_pt;
4682 f2l = pte_l2_l_cache_mode_pt;
4683 f2s = pte_l2_s_cache_mode_pt;
4690 /* See if we can use a section mapping. */
4691 if (L1_S_MAPPABLE_P(va, pa, resid)) {
4692 #ifdef VERBOSE_INIT_ARM
4695 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4696 L1_S_PROT(PTE_KERNEL, prot) | f1 |
4697 L1_S_DOM(PMAP_DOMAIN_KERNEL);
4698 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4706 * Ok, we're going to use an L2 table. Make sure
4707 * one is actually in the corresponding L1 slot
4708 * for the current VA.
4710 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4711 panic("pmap_map_chunk: no L2 table for VA 0x%08x", va);
4713 pte = (pt_entry_t *) kernel_pt_lookup(
4714 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4716 panic("pmap_map_chunk: can't find L2 table for VA"
4718 /* See if we can use a L2 large page mapping. */
4719 if (L2_L_MAPPABLE_P(va, pa, resid)) {
4720 #ifdef VERBOSE_INIT_ARM
4723 for (i = 0; i < 16; i++) {
4724 pte[l2pte_index(va) + i] =
4726 L2_L_PROT(PTE_KERNEL, prot) | f2l;
4727 PTE_SYNC(&pte[l2pte_index(va) + i]);
4735 /* Use a small page mapping. */
4736 #ifdef VERBOSE_INIT_ARM
4739 pte[l2pte_index(va)] =
4740 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s;
4741 PTE_SYNC(&pte[l2pte_index(va)]);
4746 #ifdef VERBOSE_INIT_ARM
4753 /********************** Static device map routines ***************************/
4755 static const struct pmap_devmap *pmap_devmap_table;
4758 * Register the devmap table. This is provided in case early console
4759 * initialization needs to register mappings created by bootstrap code
4760 * before pmap_devmap_bootstrap() is called.
4763 pmap_devmap_register(const struct pmap_devmap *table)
4766 pmap_devmap_table = table;
4770 * Map all of the static regions in the devmap table, and remember
4771 * the devmap table so other parts of the kernel can look up entries
4775 pmap_devmap_bootstrap(vm_offset_t l1pt, const struct pmap_devmap *table)
4779 pmap_devmap_table = table;
4781 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
4782 #ifdef VERBOSE_INIT_ARM
4783 printf("devmap: %08x -> %08x @ %08x\n",
4784 pmap_devmap_table[i].pd_pa,
4785 pmap_devmap_table[i].pd_pa +
4786 pmap_devmap_table[i].pd_size - 1,
4787 pmap_devmap_table[i].pd_va);
4789 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va,
4790 pmap_devmap_table[i].pd_pa,
4791 pmap_devmap_table[i].pd_size,
4792 pmap_devmap_table[i].pd_prot,
4793 pmap_devmap_table[i].pd_cache);
4797 const struct pmap_devmap *
4798 pmap_devmap_find_pa(vm_paddr_t pa, vm_size_t size)
4802 if (pmap_devmap_table == NULL)
4805 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
4806 if (pa >= pmap_devmap_table[i].pd_pa &&
4807 pa + size <= pmap_devmap_table[i].pd_pa +
4808 pmap_devmap_table[i].pd_size)
4809 return (&pmap_devmap_table[i]);
4815 const struct pmap_devmap *
4816 pmap_devmap_find_va(vm_offset_t va, vm_size_t size)
4820 if (pmap_devmap_table == NULL)
4823 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
4824 if (va >= pmap_devmap_table[i].pd_va &&
4825 va + size <= pmap_devmap_table[i].pd_va +
4826 pmap_devmap_table[i].pd_size)
4827 return (&pmap_devmap_table[i]);