1 /* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */
3 * Copyright 2004 Olivier Houchard.
4 * Copyright 2003 Wasabi Systems, Inc.
7 * Written by Steve C. Woodford for Wasabi Systems, Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
39 * Copyright (c) 2002-2003 Wasabi Systems, Inc.
40 * Copyright (c) 2001 Richard Earnshaw
41 * Copyright (c) 2001-2002 Christopher Gilbert
42 * All rights reserved.
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. The name of the company nor the name of the author may be used to
50 * endorse or promote products derived from this software without specific
51 * prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
66 * Copyright (c) 1999 The NetBSD Foundation, Inc.
67 * All rights reserved.
69 * This code is derived from software contributed to The NetBSD Foundation
70 * by Charles M. Hannum.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
81 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
82 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
83 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
84 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
85 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
86 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
87 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
88 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
89 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
90 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
91 * POSSIBILITY OF SUCH DAMAGE.
95 * Copyright (c) 1994-1998 Mark Brinicombe.
96 * Copyright (c) 1994 Brini.
97 * All rights reserved.
99 * This code is derived from software written for Brini by Mark Brinicombe
101 * Redistribution and use in source and binary forms, with or without
102 * modification, are permitted provided that the following conditions
104 * 1. Redistributions of source code must retain the above copyright
105 * notice, this list of conditions and the following disclaimer.
106 * 2. Redistributions in binary form must reproduce the above copyright
107 * notice, this list of conditions and the following disclaimer in the
108 * documentation and/or other materials provided with the distribution.
109 * 3. All advertising materials mentioning features or use of this software
110 * must display the following acknowledgement:
111 * This product includes software developed by Mark Brinicombe.
112 * 4. The name of the author may not be used to endorse or promote products
113 * derived from this software without specific prior written permission.
115 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
116 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
117 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
118 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
119 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
120 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
121 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
122 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
123 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
125 * RiscBSD kernel project
129 * Machine dependant vm stuff
135 * Special compilation symbols
136 * PMAP_DEBUG - Build in pmap_debug_level code
138 /* Include header files */
142 #include <sys/cdefs.h>
143 __FBSDID("$FreeBSD$");
144 #include <sys/param.h>
145 #include <sys/systm.h>
146 #include <sys/kernel.h>
148 #include <sys/lock.h>
149 #include <sys/proc.h>
150 #include <sys/malloc.h>
151 #include <sys/msgbuf.h>
152 #include <sys/mutex.h>
153 #include <sys/vmmeter.h>
154 #include <sys/mman.h>
155 #include <sys/rwlock.h>
157 #include <sys/sched.h>
160 #include <vm/vm_param.h>
163 #include <vm/vm_kern.h>
164 #include <vm/vm_object.h>
165 #include <vm/vm_map.h>
166 #include <vm/vm_page.h>
167 #include <vm/vm_pageout.h>
168 #include <vm/vm_phys.h>
169 #include <vm/vm_extern.h>
171 #include <machine/md_var.h>
172 #include <machine/cpu.h>
173 #include <machine/cpufunc.h>
174 #include <machine/pcb.h>
177 #define PDEBUG(_lev_,_stat_) \
178 if (pmap_debug_level >= (_lev_)) \
180 #define dprintf printf
182 int pmap_debug_level = 0;
184 #else /* PMAP_DEBUG */
185 #define PDEBUG(_lev_,_stat_) /* Nothing */
186 #define dprintf(x, arg...)
187 #define PMAP_INLINE __inline
188 #endif /* PMAP_DEBUG */
190 extern struct pv_addr systempage;
192 extern int last_fault_code;
195 * Internal function prototypes
197 static void pmap_free_pv_entry (pv_entry_t);
198 static pv_entry_t pmap_get_pv_entry(void);
200 static void pmap_enter_locked(pmap_t, vm_offset_t, vm_page_t,
201 vm_prot_t, boolean_t, int);
202 static vm_paddr_t pmap_extract_locked(pmap_t pmap, vm_offset_t va);
203 static void pmap_fix_cache(struct vm_page *, pmap_t, vm_offset_t);
204 static void pmap_alloc_l1(pmap_t);
205 static void pmap_free_l1(pmap_t);
207 static int pmap_clearbit(struct vm_page *, u_int);
209 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t);
210 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t);
211 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int);
212 static vm_offset_t kernel_pt_lookup(vm_paddr_t);
214 static MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1");
216 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
217 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
218 vm_offset_t pmap_curmaxkvaddr;
219 vm_paddr_t kernel_l1pa;
221 vm_offset_t kernel_vm_end = 0;
223 vm_offset_t vm_max_kernel_address;
225 struct pmap kernel_pmap_store;
227 static pt_entry_t *csrc_pte, *cdst_pte;
228 static vm_offset_t csrcp, cdstp;
229 static struct mtx cmtx;
231 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *);
233 * These routines are called when the CPU type is identified to set up
234 * the PTE prototypes, cache modes, etc.
236 * The variables are always here, just in case LKMs need to reference
237 * them (though, they shouldn't).
240 pt_entry_t pte_l1_s_cache_mode;
241 pt_entry_t pte_l1_s_cache_mode_pt;
242 pt_entry_t pte_l1_s_cache_mask;
244 pt_entry_t pte_l2_l_cache_mode;
245 pt_entry_t pte_l2_l_cache_mode_pt;
246 pt_entry_t pte_l2_l_cache_mask;
248 pt_entry_t pte_l2_s_cache_mode;
249 pt_entry_t pte_l2_s_cache_mode_pt;
250 pt_entry_t pte_l2_s_cache_mask;
252 pt_entry_t pte_l2_s_prot_u;
253 pt_entry_t pte_l2_s_prot_w;
254 pt_entry_t pte_l2_s_prot_mask;
256 pt_entry_t pte_l1_s_proto;
257 pt_entry_t pte_l1_c_proto;
258 pt_entry_t pte_l2_s_proto;
260 void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t);
261 void (*pmap_copy_page_offs_func)(vm_paddr_t a_phys,
262 vm_offset_t a_offs, vm_paddr_t b_phys, vm_offset_t b_offs,
264 void (*pmap_zero_page_func)(vm_paddr_t, int, int);
266 struct msgbuf *msgbufp = 0;
271 static caddr_t crashdumpmap;
273 extern void bcopy_page(vm_offset_t, vm_offset_t);
274 extern void bzero_page(vm_offset_t);
276 extern vm_offset_t alloc_firstaddr;
281 * Metadata for L1 translation tables.
284 /* Entry on the L1 Table list */
285 SLIST_ENTRY(l1_ttable) l1_link;
287 /* Entry on the L1 Least Recently Used list */
288 TAILQ_ENTRY(l1_ttable) l1_lru;
290 /* Track how many domains are allocated from this L1 */
291 volatile u_int l1_domain_use_count;
294 * A free-list of domain numbers for this L1.
295 * We avoid using ffs() and a bitmap to track domains since ffs()
298 u_int8_t l1_domain_first;
299 u_int8_t l1_domain_free[PMAP_DOMAINS];
301 /* Physical address of this L1 page table */
302 vm_paddr_t l1_physaddr;
304 /* KVA of this L1 page table */
309 * Convert a virtual address into its L1 table index. That is, the
310 * index used to locate the L2 descriptor table pointer in an L1 table.
311 * This is basically used to index l1->l1_kva[].
313 * Each L2 descriptor table represents 1MB of VA space.
315 #define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT)
318 * L1 Page Tables are tracked using a Least Recently Used list.
319 * - New L1s are allocated from the HEAD.
320 * - Freed L1s are added to the TAIl.
321 * - Recently accessed L1s (where an 'access' is some change to one of
322 * the userland pmaps which owns this L1) are moved to the TAIL.
324 static TAILQ_HEAD(, l1_ttable) l1_lru_list;
326 * A list of all L1 tables
328 static SLIST_HEAD(, l1_ttable) l1_list;
329 static struct mtx l1_lru_lock;
332 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots.
334 * This is normally 16MB worth L2 page descriptors for any given pmap.
335 * Reference counts are maintained for L2 descriptors so they can be
339 /* The number of L2 page descriptors allocated to this l2_dtable */
342 /* List of L2 page descriptors */
344 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */
345 vm_paddr_t l2b_phys; /* Physical address of same */
346 u_short l2b_l1idx; /* This L2 table's L1 index */
347 u_short l2b_occupancy; /* How many active descriptors */
348 } l2_bucket[L2_BUCKET_SIZE];
351 /* pmap_kenter_internal flags */
352 #define KENTER_CACHE 0x1
353 #define KENTER_USER 0x2
356 * Given an L1 table index, calculate the corresponding l2_dtable index
357 * and bucket index within the l2_dtable.
359 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \
361 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1))
364 * Given a virtual address, this macro returns the
365 * virtual address required to drop into the next L2 bucket.
367 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE)
370 * We try to map the page tables write-through, if possible. However, not
371 * all CPUs have a write-through cache mode, so on those we have to sync
372 * the cache when we frob page tables.
374 * We try to evaluate this at compile time, if possible. However, it's
375 * not always possible to do that, hence this run-time var.
377 int pmap_needs_pte_sync;
380 * Macro to determine if a mapping might be resident in the
381 * instruction cache and/or TLB
383 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC))
386 * Macro to determine if a mapping might be resident in the
387 * data cache and/or TLB
389 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0)
391 #ifndef PMAP_SHPGPERPROC
392 #define PMAP_SHPGPERPROC 200
395 #define pmap_is_current(pm) ((pm) == pmap_kernel() || \
396 curproc->p_vmspace->vm_map.pmap == (pm))
397 static uma_zone_t pvzone = NULL;
399 static uma_zone_t l2table_zone;
400 static vm_offset_t pmap_kernel_l2dtable_kva;
401 static vm_offset_t pmap_kernel_l2ptp_kva;
402 static vm_paddr_t pmap_kernel_l2ptp_phys;
403 static int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0;
404 static struct rwlock pvh_global_lock;
406 void pmap_copy_page_offs_generic(vm_paddr_t a_phys, vm_offset_t a_offs,
407 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt);
408 #if ARM_MMU_XSCALE == 1
409 void pmap_copy_page_offs_xscale(vm_paddr_t a_phys, vm_offset_t a_offs,
410 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt);
414 * This list exists for the benefit of pmap_map_chunk(). It keeps track
415 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can
416 * find them as necessary.
418 * Note that the data on this list MUST remain valid after initarm() returns,
419 * as pmap_bootstrap() uses it to contruct L2 table metadata.
421 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list);
424 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt)
429 l1->l1_domain_use_count = 0;
430 l1->l1_domain_first = 0;
432 for (i = 0; i < PMAP_DOMAINS; i++)
433 l1->l1_domain_free[i] = i + 1;
436 * Copy the kernel's L1 entries to each new L1.
438 if (l1pt != pmap_kernel()->pm_l1->l1_kva)
439 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE);
441 if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0)
442 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt);
443 SLIST_INSERT_HEAD(&l1_list, l1, l1_link);
444 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
448 kernel_pt_lookup(vm_paddr_t pa)
452 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) {
459 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
461 pmap_pte_init_generic(void)
464 pte_l1_s_cache_mode = L1_S_B|L1_S_C;
465 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic;
467 pte_l2_l_cache_mode = L2_B|L2_C;
468 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic;
470 pte_l2_s_cache_mode = L2_B|L2_C;
471 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic;
474 * If we have a write-through cache, set B and C. If
475 * we have a write-back cache, then we assume setting
476 * only C will make those pages write-through.
478 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) {
479 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
480 pte_l2_l_cache_mode_pt = L2_B|L2_C;
481 pte_l2_s_cache_mode_pt = L2_B|L2_C;
483 pte_l1_s_cache_mode_pt = L1_S_C;
484 pte_l2_l_cache_mode_pt = L2_C;
485 pte_l2_s_cache_mode_pt = L2_C;
488 pte_l2_s_prot_u = L2_S_PROT_U_generic;
489 pte_l2_s_prot_w = L2_S_PROT_W_generic;
490 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic;
492 pte_l1_s_proto = L1_S_PROTO_generic;
493 pte_l1_c_proto = L1_C_PROTO_generic;
494 pte_l2_s_proto = L2_S_PROTO_generic;
496 pmap_copy_page_func = pmap_copy_page_generic;
497 pmap_copy_page_offs_func = pmap_copy_page_offs_generic;
498 pmap_zero_page_func = pmap_zero_page_generic;
501 #if defined(CPU_ARM8)
503 pmap_pte_init_arm8(void)
507 * ARM8 is compatible with generic, but we need to use
508 * the page tables uncached.
510 pmap_pte_init_generic();
512 pte_l1_s_cache_mode_pt = 0;
513 pte_l2_l_cache_mode_pt = 0;
514 pte_l2_s_cache_mode_pt = 0;
516 #endif /* CPU_ARM8 */
518 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH)
520 pmap_pte_init_arm9(void)
524 * ARM9 is compatible with generic, but we want to use
525 * write-through caching for now.
527 pmap_pte_init_generic();
529 pte_l1_s_cache_mode = L1_S_C;
530 pte_l2_l_cache_mode = L2_C;
531 pte_l2_s_cache_mode = L2_C;
533 pte_l1_s_cache_mode_pt = L1_S_C;
534 pte_l2_l_cache_mode_pt = L2_C;
535 pte_l2_s_cache_mode_pt = L2_C;
537 #endif /* CPU_ARM9 */
538 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
540 #if defined(CPU_ARM10)
542 pmap_pte_init_arm10(void)
546 * ARM10 is compatible with generic, but we want to use
547 * write-through caching for now.
549 pmap_pte_init_generic();
551 pte_l1_s_cache_mode = L1_S_B | L1_S_C;
552 pte_l2_l_cache_mode = L2_B | L2_C;
553 pte_l2_s_cache_mode = L2_B | L2_C;
555 pte_l1_s_cache_mode_pt = L1_S_C;
556 pte_l2_l_cache_mode_pt = L2_C;
557 pte_l2_s_cache_mode_pt = L2_C;
560 #endif /* CPU_ARM10 */
564 pmap_pte_init_sa1(void)
568 * The StrongARM SA-1 cache does not have a write-through
569 * mode. So, do the generic initialization, then reset
570 * the page table cache mode to B=1,C=1, and note that
571 * the PTEs need to be sync'd.
573 pmap_pte_init_generic();
575 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
576 pte_l2_l_cache_mode_pt = L2_B|L2_C;
577 pte_l2_s_cache_mode_pt = L2_B|L2_C;
579 pmap_needs_pte_sync = 1;
581 #endif /* ARM_MMU_SA1 == 1*/
583 #if ARM_MMU_XSCALE == 1
584 #if (ARM_NMMUS > 1) || defined (CPU_XSCALE_CORE3)
585 static u_int xscale_use_minidata;
589 pmap_pte_init_xscale(void)
592 int write_through = 0;
594 pte_l1_s_cache_mode = L1_S_B|L1_S_C|L1_S_XSCALE_P;
595 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale;
597 pte_l2_l_cache_mode = L2_B|L2_C;
598 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale;
600 pte_l2_s_cache_mode = L2_B|L2_C;
601 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale;
603 pte_l1_s_cache_mode_pt = L1_S_C;
604 pte_l2_l_cache_mode_pt = L2_C;
605 pte_l2_s_cache_mode_pt = L2_C;
606 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE
608 * The XScale core has an enhanced mode where writes that
609 * miss the cache cause a cache line to be allocated. This
610 * is significantly faster than the traditional, write-through
611 * behavior of this case.
613 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X);
614 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X);
615 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X);
616 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */
617 #ifdef XSCALE_CACHE_WRITE_THROUGH
619 * Some versions of the XScale core have various bugs in
620 * their cache units, the work-around for which is to run
621 * the cache in write-through mode. Unfortunately, this
622 * has a major (negative) impact on performance. So, we
623 * go ahead and run fast-and-loose, in the hopes that we
624 * don't line up the planets in a way that will trip the
627 * However, we give you the option to be slow-but-correct.
630 #elif defined(XSCALE_CACHE_WRITE_BACK)
631 /* force write back cache mode */
633 #elif defined(CPU_XSCALE_PXA2X0)
635 * Intel PXA2[15]0 processors are known to have a bug in
636 * write-back cache on revision 4 and earlier (stepping
637 * A[01] and B[012]). Fixed for C0 and later.
643 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK);
645 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) {
646 if ((id & CPU_ID_REVISION_MASK) < 5) {
647 /* write through for stepping A0-1 and B0-2 */
652 #endif /* XSCALE_CACHE_WRITE_THROUGH */
655 pte_l1_s_cache_mode = L1_S_C;
656 pte_l2_l_cache_mode = L2_C;
657 pte_l2_s_cache_mode = L2_C;
661 xscale_use_minidata = 1;
664 pte_l2_s_prot_u = L2_S_PROT_U_xscale;
665 pte_l2_s_prot_w = L2_S_PROT_W_xscale;
666 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale;
668 pte_l1_s_proto = L1_S_PROTO_xscale;
669 pte_l1_c_proto = L1_C_PROTO_xscale;
670 pte_l2_s_proto = L2_S_PROTO_xscale;
672 #ifdef CPU_XSCALE_CORE3
673 pmap_copy_page_func = pmap_copy_page_generic;
674 pmap_copy_page_offs_func = pmap_copy_page_offs_generic;
675 pmap_zero_page_func = pmap_zero_page_generic;
676 xscale_use_minidata = 0;
677 /* Make sure it is L2-cachable */
678 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_T);
679 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode &~ L1_S_XSCALE_P;
680 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_T) ;
681 pte_l2_l_cache_mode_pt = pte_l1_s_cache_mode;
682 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_T);
683 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode;
686 pmap_copy_page_func = pmap_copy_page_xscale;
687 pmap_copy_page_offs_func = pmap_copy_page_offs_xscale;
688 pmap_zero_page_func = pmap_zero_page_xscale;
692 * Disable ECC protection of page table access, for now.
694 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
695 auxctl &= ~XSCALE_AUXCTL_P;
696 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
700 * xscale_setup_minidata:
702 * Set up the mini-data cache clean area. We require the
703 * caller to allocate the right amount of physically and
704 * virtually contiguous space.
706 extern vm_offset_t xscale_minidata_clean_addr;
707 extern vm_size_t xscale_minidata_clean_size; /* already initialized */
709 xscale_setup_minidata(vm_offset_t l1pt, vm_offset_t va, vm_paddr_t pa)
711 pd_entry_t *pde = (pd_entry_t *) l1pt;
716 xscale_minidata_clean_addr = va;
718 /* Round it to page size. */
719 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME;
722 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) {
723 pte = (pt_entry_t *) kernel_pt_lookup(
724 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
726 panic("xscale_setup_minidata: can't find L2 table for "
727 "VA 0x%08x", (u_int32_t) va);
728 pte[l2pte_index(va)] =
729 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
730 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X);
734 * Configure the mini-data cache for write-back with
735 * read/write-allocate.
737 * NOTE: In order to reconfigure the mini-data cache, we must
738 * make sure it contains no valid data! In order to do that,
739 * we must issue a global data cache invalidate command!
741 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED!
742 * THIS IS VERY IMPORTANT!
745 /* Invalidate data and mini-data. */
746 __asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
747 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
748 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA;
749 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
754 * Allocate an L1 translation table for the specified pmap.
755 * This is called at pmap creation time.
758 pmap_alloc_l1(pmap_t pm)
760 struct l1_ttable *l1;
764 * Remove the L1 at the head of the LRU list
766 mtx_lock(&l1_lru_lock);
767 l1 = TAILQ_FIRST(&l1_lru_list);
768 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
771 * Pick the first available domain number, and update
772 * the link to the next number.
774 domain = l1->l1_domain_first;
775 l1->l1_domain_first = l1->l1_domain_free[domain];
778 * If there are still free domain numbers in this L1,
779 * put it back on the TAIL of the LRU list.
781 if (++l1->l1_domain_use_count < PMAP_DOMAINS)
782 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
784 mtx_unlock(&l1_lru_lock);
787 * Fix up the relevant bits in the pmap structure
790 pm->pm_domain = domain + 1;
794 * Free an L1 translation table.
795 * This is called at pmap destruction time.
798 pmap_free_l1(pmap_t pm)
800 struct l1_ttable *l1 = pm->pm_l1;
802 mtx_lock(&l1_lru_lock);
805 * If this L1 is currently on the LRU list, remove it.
807 if (l1->l1_domain_use_count < PMAP_DOMAINS)
808 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
811 * Free up the domain number which was allocated to the pmap
813 l1->l1_domain_free[pm->pm_domain - 1] = l1->l1_domain_first;
814 l1->l1_domain_first = pm->pm_domain - 1;
815 l1->l1_domain_use_count--;
818 * The L1 now must have at least 1 free domain, so add
819 * it back to the LRU list. If the use count is zero,
820 * put it at the head of the list, otherwise it goes
823 if (l1->l1_domain_use_count == 0) {
824 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru);
826 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
828 mtx_unlock(&l1_lru_lock);
832 * Returns a pointer to the L2 bucket associated with the specified pmap
833 * and VA, or NULL if no L2 bucket exists for the address.
835 static PMAP_INLINE struct l2_bucket *
836 pmap_get_l2_bucket(pmap_t pm, vm_offset_t va)
838 struct l2_dtable *l2;
839 struct l2_bucket *l2b;
844 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL ||
845 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL)
852 * Returns a pointer to the L2 bucket associated with the specified pmap
855 * If no L2 bucket exists, perform the necessary allocations to put an L2
856 * bucket/page table in place.
858 * Note that if a new L2 bucket/page was allocated, the caller *must*
859 * increment the bucket occupancy counter appropriately *before*
860 * releasing the pmap's lock to ensure no other thread or cpu deallocates
861 * the bucket/page in the meantime.
863 static struct l2_bucket *
864 pmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va)
866 struct l2_dtable *l2;
867 struct l2_bucket *l2b;
872 PMAP_ASSERT_LOCKED(pm);
873 rw_assert(&pvh_global_lock, RA_WLOCKED);
874 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
876 * No mapping at this address, as there is
877 * no entry in the L1 table.
878 * Need to allocate a new l2_dtable.
881 rw_wunlock(&pvh_global_lock);
882 if ((l2 = uma_zalloc(l2table_zone, M_NOWAIT)) == NULL) {
883 rw_wlock(&pvh_global_lock);
887 rw_wlock(&pvh_global_lock);
889 if (pm->pm_l2[L2_IDX(l1idx)] != NULL) {
891 * Someone already allocated the l2_dtable while
892 * we were doing the same.
894 uma_zfree(l2table_zone, l2);
895 l2 = pm->pm_l2[L2_IDX(l1idx)];
897 bzero(l2, sizeof(*l2));
899 * Link it into the parent pmap
901 pm->pm_l2[L2_IDX(l1idx)] = l2;
905 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
908 * Fetch pointer to the L2 page table associated with the address.
910 if (l2b->l2b_kva == NULL) {
914 * No L2 page table has been allocated. Chances are, this
915 * is because we just allocated the l2_dtable, above.
918 rw_wunlock(&pvh_global_lock);
919 ptep = uma_zalloc(l2zone, M_NOWAIT);
920 rw_wlock(&pvh_global_lock);
922 if (l2b->l2b_kva != 0) {
923 /* We lost the race. */
924 uma_zfree(l2zone, ptep);
927 l2b->l2b_phys = vtophys(ptep);
930 * Oops, no more L2 page tables available at this
931 * time. We may need to deallocate the l2_dtable
932 * if we allocated a new one above.
934 if (l2->l2_occupancy == 0) {
935 pm->pm_l2[L2_IDX(l1idx)] = NULL;
936 uma_zfree(l2table_zone, l2);
943 l2b->l2b_l1idx = l1idx;
949 static PMAP_INLINE void
950 #ifndef PMAP_INCLUDE_PTE_SYNC
951 pmap_free_l2_ptp(pt_entry_t *l2)
953 pmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2)
956 #ifdef PMAP_INCLUDE_PTE_SYNC
958 * Note: With a write-back cache, we may need to sync this
959 * L2 table before re-using it.
960 * This is because it may have belonged to a non-current
961 * pmap, in which case the cache syncs would have been
962 * skipped when the pages were being unmapped. If the
963 * L2 table were then to be immediately re-allocated to
964 * the *current* pmap, it may well contain stale mappings
965 * which have not yet been cleared by a cache write-back
966 * and so would still be visible to the mmu.
969 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
971 uma_zfree(l2zone, l2);
974 * One or more mappings in the specified L2 descriptor table have just been
977 * Garbage collect the metadata and descriptor table itself if necessary.
979 * The pmap lock must be acquired when this is called (not necessary
980 * for the kernel pmap).
983 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count)
985 struct l2_dtable *l2;
986 pd_entry_t *pl1pd, l1pd;
992 * Update the bucket's reference count according to how many
993 * PTEs the caller has just invalidated.
995 l2b->l2b_occupancy -= count;
1000 * Level 2 page tables allocated to the kernel pmap are never freed
1001 * as that would require checking all Level 1 page tables and
1002 * removing any references to the Level 2 page table. See also the
1003 * comment elsewhere about never freeing bootstrap L2 descriptors.
1005 * We make do with just invalidating the mapping in the L2 table.
1007 * This isn't really a big deal in practice and, in fact, leads
1008 * to a performance win over time as we don't need to continually
1011 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel())
1015 * There are no more valid mappings in this level 2 page table.
1016 * Go ahead and NULL-out the pointer in the bucket, then
1017 * free the page table.
1019 l1idx = l2b->l2b_l1idx;
1020 ptep = l2b->l2b_kva;
1021 l2b->l2b_kva = NULL;
1023 pl1pd = &pm->pm_l1->l1_kva[l1idx];
1026 * If the L1 slot matches the pmap's domain
1027 * number, then invalidate it.
1029 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK);
1030 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) {
1036 * Release the L2 descriptor table back to the pool cache.
1038 #ifndef PMAP_INCLUDE_PTE_SYNC
1039 pmap_free_l2_ptp(ptep);
1041 pmap_free_l2_ptp(!pmap_is_current(pm), ptep);
1045 * Update the reference count in the associated l2_dtable
1047 l2 = pm->pm_l2[L2_IDX(l1idx)];
1048 if (--l2->l2_occupancy > 0)
1052 * There are no more valid mappings in any of the Level 1
1053 * slots managed by this l2_dtable. Go ahead and NULL-out
1054 * the pointer in the parent pmap and free the l2_dtable.
1056 pm->pm_l2[L2_IDX(l1idx)] = NULL;
1057 uma_zfree(l2table_zone, l2);
1061 * Pool cache constructors for L2 descriptor tables, metadata and pmap
1065 pmap_l2ptp_ctor(void *mem, int size, void *arg, int flags)
1067 #ifndef PMAP_INCLUDE_PTE_SYNC
1068 struct l2_bucket *l2b;
1069 pt_entry_t *ptep, pte;
1070 #ifdef ARM_USE_SMALL_ALLOC
1073 vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK;
1076 * The mappings for these page tables were initially made using
1077 * pmap_kenter() by the pool subsystem. Therefore, the cache-
1078 * mode will not be right for page table mappings. To avoid
1079 * polluting the pmap_kenter() code with a special case for
1080 * page tables, we simply fix up the cache-mode here if it's not
1083 #ifdef ARM_USE_SMALL_ALLOC
1084 pde = &kernel_pmap->pm_l1->l1_kva[L1_IDX(va)];
1085 if (!l1pte_section_p(*pde)) {
1087 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
1088 ptep = &l2b->l2b_kva[l2pte_index(va)];
1091 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
1093 * Page tables must have the cache-mode set to
1096 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
1098 cpu_tlb_flushD_SE(va);
1101 #ifdef ARM_USE_SMALL_ALLOC
1105 memset(mem, 0, L2_TABLE_SIZE_REAL);
1106 PTE_SYNC_RANGE(mem, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
1111 * A bunch of routines to conditionally flush the caches/TLB depending
1112 * on whether the specified pmap actually needs to be flushed at any
1115 static PMAP_INLINE void
1116 pmap_tlb_flushID_SE(pmap_t pm, vm_offset_t va)
1119 if (pmap_is_current(pm))
1120 cpu_tlb_flushID_SE(va);
1123 static PMAP_INLINE void
1124 pmap_tlb_flushD_SE(pmap_t pm, vm_offset_t va)
1127 if (pmap_is_current(pm))
1128 cpu_tlb_flushD_SE(va);
1131 static PMAP_INLINE void
1132 pmap_tlb_flushID(pmap_t pm)
1135 if (pmap_is_current(pm))
1138 static PMAP_INLINE void
1139 pmap_tlb_flushD(pmap_t pm)
1142 if (pmap_is_current(pm))
1147 pmap_has_valid_mapping(pmap_t pm, vm_offset_t va)
1152 if (pmap_get_pde_pte(pm, va, &pde, &ptep) &&
1153 ptep && ((*ptep & L2_TYPE_MASK) != L2_TYPE_INV))
1159 static PMAP_INLINE void
1160 pmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len)
1164 CTR4(KTR_PMAP, "pmap_dcache_wbinv_range: pmap %p is_kernel %d va 0x%08x"
1165 " len 0x%x ", pm, pm == pmap_kernel(), va, len);
1167 if (pmap_is_current(pm) || pm == pmap_kernel()) {
1168 rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len);
1170 if (pmap_has_valid_mapping(pm, va)) {
1171 cpu_idcache_wbinv_range(va, rest);
1172 cpu_l2cache_wbinv_range(va, rest);
1176 rest = MIN(PAGE_SIZE, len);
1181 static PMAP_INLINE void
1182 pmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len, boolean_t do_inv,
1187 CTR4(KTR_PMAP, "pmap_dcache_wb_range: pmap %p is_kernel %d va 0x%08x "
1188 "len 0x%x ", pm, pm == pmap_kernel(), va, len);
1189 CTR2(KTR_PMAP, " do_inv %d rd_only %d", do_inv, rd_only);
1191 if (pmap_is_current(pm)) {
1192 rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len);
1194 if (pmap_has_valid_mapping(pm, va)) {
1195 if (do_inv && rd_only) {
1196 cpu_dcache_inv_range(va, rest);
1197 cpu_l2cache_inv_range(va, rest);
1198 } else if (do_inv) {
1199 cpu_dcache_wbinv_range(va, rest);
1200 cpu_l2cache_wbinv_range(va, rest);
1201 } else if (!rd_only) {
1202 cpu_dcache_wb_range(va, rest);
1203 cpu_l2cache_wb_range(va, rest);
1209 rest = MIN(PAGE_SIZE, len);
1214 static PMAP_INLINE void
1215 pmap_idcache_wbinv_all(pmap_t pm)
1218 if (pmap_is_current(pm)) {
1219 cpu_idcache_wbinv_all();
1220 cpu_l2cache_wbinv_all();
1225 static PMAP_INLINE void
1226 pmap_dcache_wbinv_all(pmap_t pm)
1229 if (pmap_is_current(pm)) {
1230 cpu_dcache_wbinv_all();
1231 cpu_l2cache_wbinv_all();
1239 * Make sure the pte is written out to RAM.
1240 * We need to do this for one of two cases:
1241 * - We're dealing with the kernel pmap
1242 * - There is no pmap active in the cache/tlb.
1243 * - The specified pmap is 'active' in the cache/tlb.
1245 #ifdef PMAP_INCLUDE_PTE_SYNC
1246 #define PTE_SYNC_CURRENT(pm, ptep) \
1248 if (PMAP_NEEDS_PTE_SYNC && \
1249 pmap_is_current(pm)) \
1251 } while (/*CONSTCOND*/0)
1253 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */
1257 * cacheable == -1 means we must make the entry uncacheable, 1 means
1260 static __inline void
1261 pmap_set_cache_entry(pv_entry_t pv, pmap_t pm, vm_offset_t va, int cacheable)
1263 struct l2_bucket *l2b;
1264 pt_entry_t *ptep, pte;
1266 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
1267 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
1269 if (cacheable == 1) {
1270 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode;
1271 if (l2pte_valid(pte)) {
1272 if (PV_BEEN_EXECD(pv->pv_flags)) {
1273 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va);
1274 } else if (PV_BEEN_REFD(pv->pv_flags)) {
1275 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va);
1279 pte = *ptep &~ L2_S_CACHE_MASK;
1280 if ((va != pv->pv_va || pm != pv->pv_pmap) &&
1282 if (PV_BEEN_EXECD(pv->pv_flags)) {
1283 pmap_idcache_wbinv_range(pv->pv_pmap,
1284 pv->pv_va, PAGE_SIZE);
1285 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va);
1286 } else if (PV_BEEN_REFD(pv->pv_flags)) {
1287 pmap_dcache_wb_range(pv->pv_pmap,
1288 pv->pv_va, PAGE_SIZE, TRUE,
1289 (pv->pv_flags & PVF_WRITE) == 0);
1290 pmap_tlb_flushD_SE(pv->pv_pmap,
1296 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
1300 pmap_fix_cache(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1303 int writable = 0, kwritable = 0, uwritable = 0;
1304 int entries = 0, kentries = 0, uentries = 0;
1305 struct pv_entry *pv;
1307 rw_assert(&pvh_global_lock, RA_WLOCKED);
1309 /* the cache gets written back/invalidated on context switch.
1310 * therefore, if a user page shares an entry in the same page or
1311 * with the kernel map and at least one is writable, then the
1312 * cache entry must be set write-through.
1315 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1316 /* generate a count of the pv_entry uses */
1317 if (pv->pv_flags & PVF_WRITE) {
1318 if (pv->pv_pmap == pmap_kernel())
1320 else if (pv->pv_pmap == pm)
1324 if (pv->pv_pmap == pmap_kernel())
1327 if (pv->pv_pmap == pm)
1333 * check if the user duplicate mapping has
1336 if ((pm != pmap_kernel()) && (((uentries > 1) && uwritable) ||
1340 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1341 /* check for user uncachable conditions - order is important */
1342 if (pm != pmap_kernel() &&
1343 (pv->pv_pmap == pm || pv->pv_pmap == pmap_kernel())) {
1345 if ((uentries > 1 && uwritable) || uwritable > 1) {
1347 /* user duplicate mapping */
1348 if (pv->pv_pmap != pmap_kernel())
1349 pv->pv_flags |= PVF_MWC;
1351 if (!(pv->pv_flags & PVF_NC)) {
1352 pv->pv_flags |= PVF_NC;
1353 pmap_set_cache_entry(pv, pm, va, -1);
1356 } else /* no longer a duplicate user */
1357 pv->pv_flags &= ~PVF_MWC;
1361 * check for kernel uncachable conditions
1362 * kernel writable or kernel readable with writable user entry
1364 if ((kwritable && (entries || kentries > 1)) ||
1366 ((kwritable != writable) && kentries &&
1367 (pv->pv_pmap == pmap_kernel() ||
1368 (pv->pv_flags & PVF_WRITE) ||
1369 (pv->pv_flags & PVF_MWC)))) {
1371 if (!(pv->pv_flags & PVF_NC)) {
1372 pv->pv_flags |= PVF_NC;
1373 pmap_set_cache_entry(pv, pm, va, -1);
1378 /* kernel and user are cachable */
1379 if ((pm == pmap_kernel()) && !(pv->pv_flags & PVF_MWC) &&
1380 (pv->pv_flags & PVF_NC)) {
1382 pv->pv_flags &= ~PVF_NC;
1383 if (pg->md.pv_memattr != VM_MEMATTR_UNCACHEABLE)
1384 pmap_set_cache_entry(pv, pm, va, 1);
1387 /* user is no longer sharable and writable */
1388 if (pm != pmap_kernel() &&
1389 (pv->pv_pmap == pm || pv->pv_pmap == pmap_kernel()) &&
1390 !pmwc && (pv->pv_flags & PVF_NC)) {
1392 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1393 if (pg->md.pv_memattr != VM_MEMATTR_UNCACHEABLE)
1394 pmap_set_cache_entry(pv, pm, va, 1);
1398 if ((kwritable == 0) && (writable == 0)) {
1399 pg->md.pvh_attrs &= ~PVF_MOD;
1400 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1406 * Modify pte bits for all ptes corresponding to the given physical address.
1407 * We use `maskbits' rather than `clearbits' because we're always passing
1408 * constants and the latter would require an extra inversion at run-time.
1411 pmap_clearbit(struct vm_page *pg, u_int maskbits)
1413 struct l2_bucket *l2b;
1414 struct pv_entry *pv;
1415 pt_entry_t *ptep, npte, opte;
1421 rw_wlock(&pvh_global_lock);
1423 if (maskbits & PVF_WRITE)
1424 maskbits |= PVF_MOD;
1426 * Clear saved attributes (modify, reference)
1428 pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF));
1430 if (TAILQ_EMPTY(&pg->md.pv_list)) {
1431 rw_wunlock(&pvh_global_lock);
1436 * Loop over all current mappings setting/clearing as appropos
1438 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1441 oflags = pv->pv_flags;
1443 if (!(oflags & maskbits)) {
1444 if ((maskbits & PVF_WRITE) && (pv->pv_flags & PVF_NC)) {
1445 if (pg->md.pv_memattr !=
1446 VM_MEMATTR_UNCACHEABLE) {
1448 l2b = pmap_get_l2_bucket(pm, va);
1449 ptep = &l2b->l2b_kva[l2pte_index(va)];
1450 *ptep |= pte_l2_s_cache_mode;
1454 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1458 pv->pv_flags &= ~maskbits;
1462 l2b = pmap_get_l2_bucket(pm, va);
1464 ptep = &l2b->l2b_kva[l2pte_index(va)];
1465 npte = opte = *ptep;
1467 if (maskbits & (PVF_WRITE|PVF_MOD)) {
1468 if ((pv->pv_flags & PVF_NC)) {
1470 * Entry is not cacheable:
1472 * Don't turn caching on again if this is a
1473 * modified emulation. This would be
1474 * inconsitent with the settings created by
1475 * pmap_fix_cache(). Otherwise, it's safe
1476 * to re-enable cacheing.
1478 * There's no need to call pmap_fix_cache()
1479 * here: all pages are losing their write
1482 if (maskbits & PVF_WRITE) {
1483 if (pg->md.pv_memattr !=
1484 VM_MEMATTR_UNCACHEABLE)
1485 npte |= pte_l2_s_cache_mode;
1486 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1489 if (opte & L2_S_PROT_W) {
1492 * Entry is writable/cacheable: check if pmap
1493 * is current if it is flush it, otherwise it
1494 * won't be in the cache
1496 if (PV_BEEN_EXECD(oflags))
1497 pmap_idcache_wbinv_range(pm, pv->pv_va,
1500 if (PV_BEEN_REFD(oflags))
1501 pmap_dcache_wb_range(pm, pv->pv_va,
1503 (maskbits & PVF_REF) ? TRUE : FALSE,
1507 /* make the pte read only */
1508 npte &= ~L2_S_PROT_W;
1511 if (maskbits & PVF_REF) {
1512 if ((pv->pv_flags & PVF_NC) == 0 &&
1513 (maskbits & (PVF_WRITE|PVF_MOD)) == 0) {
1515 * Check npte here; we may have already
1516 * done the wbinv above, and the validity
1517 * of the PTE is the same for opte and
1520 if (npte & L2_S_PROT_W) {
1521 if (PV_BEEN_EXECD(oflags))
1522 pmap_idcache_wbinv_range(pm,
1523 pv->pv_va, PAGE_SIZE);
1525 if (PV_BEEN_REFD(oflags))
1526 pmap_dcache_wb_range(pm,
1527 pv->pv_va, PAGE_SIZE,
1530 if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) {
1531 /* XXXJRT need idcache_inv_range */
1532 if (PV_BEEN_EXECD(oflags))
1533 pmap_idcache_wbinv_range(pm,
1534 pv->pv_va, PAGE_SIZE);
1536 if (PV_BEEN_REFD(oflags))
1537 pmap_dcache_wb_range(pm,
1538 pv->pv_va, PAGE_SIZE,
1544 * Make the PTE invalid so that we will take a
1545 * page fault the next time the mapping is
1548 npte &= ~L2_TYPE_MASK;
1549 npte |= L2_TYPE_INV;
1556 /* Flush the TLB entry if a current pmap. */
1557 if (PV_BEEN_EXECD(oflags))
1558 pmap_tlb_flushID_SE(pm, pv->pv_va);
1560 if (PV_BEEN_REFD(oflags))
1561 pmap_tlb_flushD_SE(pm, pv->pv_va);
1568 if (maskbits & PVF_WRITE)
1569 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1570 rw_wunlock(&pvh_global_lock);
1575 * main pv_entry manipulation functions:
1576 * pmap_enter_pv: enter a mapping onto a vm_page list
1577 * pmap_remove_pv: remove a mappiing from a vm_page list
1579 * NOTE: pmap_enter_pv expects to lock the pvh itself
1580 * pmap_remove_pv expects the caller to lock the pvh before calling
1584 * pmap_enter_pv: enter a mapping onto a vm_page's PV list
1586 * => caller should hold the proper lock on pvh_global_lock
1587 * => caller should have pmap locked
1588 * => we will (someday) gain the lock on the vm_page's PV list
1589 * => caller should adjust ptp's wire_count before calling
1590 * => caller should not adjust pmap's wire_count
1593 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm,
1594 vm_offset_t va, u_int flags)
1597 rw_assert(&pvh_global_lock, RA_WLOCKED);
1598 PMAP_ASSERT_LOCKED(pm);
1599 if (pg->md.pv_kva != 0) {
1600 pve->pv_pmap = kernel_pmap;
1601 pve->pv_va = pg->md.pv_kva;
1602 pve->pv_flags = PVF_WRITE | PVF_UNMAN;
1603 if (pm != kernel_pmap)
1604 PMAP_LOCK(kernel_pmap);
1605 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list);
1606 TAILQ_INSERT_HEAD(&kernel_pmap->pm_pvlist, pve, pv_plist);
1607 if (pm != kernel_pmap)
1608 PMAP_UNLOCK(kernel_pmap);
1610 if ((pve = pmap_get_pv_entry()) == NULL)
1611 panic("pmap_kenter_pv: no pv entries");
1615 pve->pv_flags = flags;
1616 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list);
1617 TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist);
1618 pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD);
1619 if (pve->pv_flags & PVF_WIRED)
1620 ++pm->pm_stats.wired_count;
1621 vm_page_aflag_set(pg, PGA_REFERENCED);
1626 * pmap_find_pv: Find a pv entry
1628 * => caller should hold lock on vm_page
1630 static PMAP_INLINE struct pv_entry *
1631 pmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1633 struct pv_entry *pv;
1635 rw_assert(&pvh_global_lock, RA_WLOCKED);
1636 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list)
1637 if (pm == pv->pv_pmap && va == pv->pv_va)
1643 * vector_page_setprot:
1645 * Manipulate the protection of the vector page.
1648 vector_page_setprot(int prot)
1650 struct l2_bucket *l2b;
1653 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page);
1655 ptep = &l2b->l2b_kva[l2pte_index(vector_page)];
1657 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot);
1659 cpu_tlb_flushD_SE(vector_page);
1664 * pmap_remove_pv: try to remove a mapping from a pv_list
1666 * => caller should hold proper lock on pmap_main_lock
1667 * => pmap should be locked
1668 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1669 * => caller should adjust ptp's wire_count and free PTP if needed
1670 * => caller should NOT adjust pmap's wire_count
1671 * => we return the removed pve
1675 pmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve)
1678 struct pv_entry *pv;
1679 rw_assert(&pvh_global_lock, RA_WLOCKED);
1680 PMAP_ASSERT_LOCKED(pm);
1681 TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list);
1682 TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist);
1683 if (pve->pv_flags & PVF_WIRED)
1684 --pm->pm_stats.wired_count;
1685 if (pg->md.pvh_attrs & PVF_MOD)
1687 if (TAILQ_FIRST(&pg->md.pv_list) == NULL)
1688 pg->md.pvh_attrs &= ~PVF_REF;
1690 vm_page_aflag_set(pg, PGA_REFERENCED);
1691 if ((pve->pv_flags & PVF_NC) && ((pm == pmap_kernel()) ||
1692 (pve->pv_flags & PVF_WRITE) || !(pve->pv_flags & PVF_MWC)))
1693 pmap_fix_cache(pg, pm, 0);
1694 else if (pve->pv_flags & PVF_WRITE) {
1695 TAILQ_FOREACH(pve, &pg->md.pv_list, pv_list)
1696 if (pve->pv_flags & PVF_WRITE)
1699 pg->md.pvh_attrs &= ~PVF_MOD;
1700 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1703 pv = TAILQ_FIRST(&pg->md.pv_list);
1704 if (pv != NULL && (pv->pv_flags & PVF_UNMAN) &&
1705 TAILQ_NEXT(pv, pv_list) == NULL) {
1707 pg->md.pv_kva = pv->pv_va;
1708 /* a recursive pmap_nuke_pv */
1709 TAILQ_REMOVE(&pg->md.pv_list, pv, pv_list);
1710 TAILQ_REMOVE(&pm->pm_pvlist, pv, pv_plist);
1711 if (pv->pv_flags & PVF_WIRED)
1712 --pm->pm_stats.wired_count;
1713 pg->md.pvh_attrs &= ~PVF_REF;
1714 pg->md.pvh_attrs &= ~PVF_MOD;
1715 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1716 pmap_free_pv_entry(pv);
1720 static struct pv_entry *
1721 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1723 struct pv_entry *pve;
1725 rw_assert(&pvh_global_lock, RA_WLOCKED);
1726 pve = TAILQ_FIRST(&pg->md.pv_list);
1729 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */
1730 pmap_nuke_pv(pg, pm, pve);
1733 pve = TAILQ_NEXT(pve, pv_list);
1736 if (pve == NULL && pg->md.pv_kva == va)
1739 return(pve); /* return removed pve */
1743 * pmap_modify_pv: Update pv flags
1745 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1746 * => caller should NOT adjust pmap's wire_count
1747 * => we return the old flags
1749 * Modify a physical-virtual mapping in the pv table
1752 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va,
1753 u_int clr_mask, u_int set_mask)
1755 struct pv_entry *npv;
1756 u_int flags, oflags;
1758 PMAP_ASSERT_LOCKED(pm);
1759 rw_assert(&pvh_global_lock, RA_WLOCKED);
1760 if ((npv = pmap_find_pv(pg, pm, va)) == NULL)
1764 * There is at least one VA mapping this page.
1767 if (clr_mask & (PVF_REF | PVF_MOD))
1768 pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD);
1770 oflags = npv->pv_flags;
1771 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask;
1773 if ((flags ^ oflags) & PVF_WIRED) {
1774 if (flags & PVF_WIRED)
1775 ++pm->pm_stats.wired_count;
1777 --pm->pm_stats.wired_count;
1780 if ((flags ^ oflags) & PVF_WRITE)
1781 pmap_fix_cache(pg, pm, 0);
1786 /* Function to set the debug level of the pmap code */
1789 pmap_debug(int level)
1791 pmap_debug_level = level;
1792 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
1794 #endif /* PMAP_DEBUG */
1797 pmap_pinit0(struct pmap *pmap)
1799 PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap));
1801 bcopy(kernel_pmap, pmap, sizeof(*pmap));
1802 bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx));
1803 PMAP_LOCK_INIT(pmap);
1807 * Initialize a vm_page's machine-dependent fields.
1810 pmap_page_init(vm_page_t m)
1813 TAILQ_INIT(&m->md.pv_list);
1814 m->md.pv_memattr = VM_MEMATTR_DEFAULT;
1818 * Initialize the pmap module.
1819 * Called by vm_init, to initialize any structures that the pmap
1820 * system needs to map virtual memory.
1825 int shpgperproc = PMAP_SHPGPERPROC;
1827 PDEBUG(1, printf("pmap_init: phys_start = %08x\n", PHYSADDR));
1829 l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor,
1830 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1831 l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable), NULL,
1832 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1835 * Initialize the PV entry allocator.
1837 pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL,
1838 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1839 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1840 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
1841 uma_zone_reserve_kva(pvzone, pv_entry_max);
1842 pv_entry_high_water = 9 * (pv_entry_max / 10);
1845 * Now it is safe to enable pv_table recording.
1847 PDEBUG(1, printf("pmap_init: done!\n"));
1851 pmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user)
1853 struct l2_dtable *l2;
1854 struct l2_bucket *l2b;
1855 pd_entry_t *pl1pd, l1pd;
1856 pt_entry_t *ptep, pte;
1862 rw_wlock(&pvh_global_lock);
1866 * If there is no l2_dtable for this address, then the process
1867 * has no business accessing it.
1869 * Note: This will catch userland processes trying to access
1872 l2 = pm->pm_l2[L2_IDX(l1idx)];
1877 * Likewise if there is no L2 descriptor table
1879 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
1880 if (l2b->l2b_kva == NULL)
1884 * Check the PTE itself.
1886 ptep = &l2b->l2b_kva[l2pte_index(va)];
1892 * Catch a userland access to the vector page mapped at 0x0
1894 if (user && (pte & L2_S_PROT_U) == 0)
1896 if (va == vector_page)
1901 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) {
1903 * This looks like a good candidate for "page modified"
1906 struct pv_entry *pv;
1909 /* Extract the physical address of the page */
1910 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) {
1913 /* Get the current flags for this page. */
1915 pv = pmap_find_pv(pg, pm, va);
1921 * Do the flags say this page is writable? If not then it
1922 * is a genuine write fault. If yes then the write fault is
1923 * our fault as we did not reflect the write access in the
1924 * PTE. Now we know a write has occurred we can correct this
1925 * and also set the modified bit
1927 if ((pv->pv_flags & PVF_WRITE) == 0) {
1931 pg->md.pvh_attrs |= PVF_REF | PVF_MOD;
1933 pv->pv_flags |= PVF_REF | PVF_MOD;
1936 * Re-enable write permissions for the page. No need to call
1937 * pmap_fix_cache(), since this is just a
1938 * modified-emulation fault, and the PVF_WRITE bit isn't
1939 * changing. We've already set the cacheable bits based on
1940 * the assumption that we can write to this page.
1942 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W;
1946 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) {
1948 * This looks like a good candidate for "page referenced"
1951 struct pv_entry *pv;
1954 /* Extract the physical address of the page */
1955 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL)
1957 /* Get the current flags for this page. */
1959 pv = pmap_find_pv(pg, pm, va);
1963 pg->md.pvh_attrs |= PVF_REF;
1964 pv->pv_flags |= PVF_REF;
1967 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO;
1973 * We know there is a valid mapping here, so simply
1974 * fix up the L1 if necessary.
1976 pl1pd = &pm->pm_l1->l1_kva[l1idx];
1977 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO;
1978 if (*pl1pd != l1pd) {
1986 * There are bugs in the rev K SA110. This is a check for one
1989 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 &&
1990 curcpu()->ci_arm_cpurev < 3) {
1991 /* Always current pmap */
1992 if (l2pte_valid(pte)) {
1993 extern int kernel_debug;
1994 if (kernel_debug & 1) {
1995 struct proc *p = curlwp->l_proc;
1996 printf("prefetch_abort: page is already "
1997 "mapped - pte=%p *pte=%08x\n", ptep, pte);
1998 printf("prefetch_abort: pc=%08lx proc=%p "
1999 "process=%s\n", va, p, p->p_comm);
2000 printf("prefetch_abort: far=%08x fs=%x\n",
2001 cpu_faultaddress(), cpu_faultstatus());
2004 if (kernel_debug & 2)
2010 #endif /* CPU_SA110 */
2014 * If 'rv == 0' at this point, it generally indicates that there is a
2015 * stale TLB entry for the faulting address. This happens when two or
2016 * more processes are sharing an L1. Since we don't flush the TLB on
2017 * a context switch between such processes, we can take domain faults
2018 * for mappings which exist at the same VA in both processes. EVEN IF
2019 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for
2022 * This is extremely likely to happen if pmap_enter() updated the L1
2023 * entry for a recently entered mapping. In this case, the TLB is
2024 * flushed for the new mapping, but there may still be TLB entries for
2025 * other mappings belonging to other processes in the 1MB range
2026 * covered by the L1 entry.
2028 * Since 'rv == 0', we know that the L1 already contains the correct
2029 * value, so the fault must be due to a stale TLB entry.
2031 * Since we always need to flush the TLB anyway in the case where we
2032 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with
2033 * stale TLB entries dynamically.
2035 * However, the above condition can ONLY happen if the current L1 is
2036 * being shared. If it happens when the L1 is unshared, it indicates
2037 * that other parts of the pmap are not doing their job WRT managing
2040 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) {
2041 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n",
2042 pm, (u_long)va, ftype);
2043 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n",
2044 l2, l2b, ptep, pl1pd);
2045 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n",
2046 pte, l1pd, last_fault_code);
2053 cpu_tlb_flushID_SE(va);
2059 rw_wunlock(&pvh_global_lock);
2067 struct l2_bucket *l2b;
2068 struct l1_ttable *l1;
2070 pt_entry_t *ptep, pte;
2071 vm_offset_t va, eva;
2074 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0);
2076 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK);
2078 for (loop = 0; loop < needed; loop++, l1++) {
2079 /* Allocate a L1 page table */
2080 va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0,
2081 0xffffffff, L1_TABLE_SIZE, 0);
2084 panic("Cannot allocate L1 KVM");
2086 eva = va + L1_TABLE_SIZE;
2087 pl1pt = (pd_entry_t *)va;
2090 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2091 ptep = &l2b->l2b_kva[l2pte_index(va)];
2093 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
2096 cpu_tlb_flushD_SE(va);
2100 pmap_init_l1(l1, pl1pt);
2105 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n",
2111 * This is used to stuff certain critical values into the PCB where they
2112 * can be accessed quickly from cpu_switch() et al.
2115 pmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb)
2117 struct l2_bucket *l2b;
2119 pcb->pcb_pagedir = pm->pm_l1->l1_physaddr;
2120 pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) |
2121 (DOMAIN_CLIENT << (pm->pm_domain * 2));
2123 if (vector_page < KERNBASE) {
2124 pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)];
2125 l2b = pmap_get_l2_bucket(pm, vector_page);
2126 pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO |
2127 L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL);
2129 pcb->pcb_pl1vec = NULL;
2133 pmap_activate(struct thread *td)
2138 pm = vmspace_pmap(td->td_proc->p_vmspace);
2142 pmap_set_pcb_pagedir(pm, pcb);
2144 if (td == curthread) {
2145 u_int cur_dacr, cur_ttb;
2147 __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb));
2148 __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr));
2150 cur_ttb &= ~(L1_TABLE_SIZE - 1);
2152 if (cur_ttb == (u_int)pcb->pcb_pagedir &&
2153 cur_dacr == pcb->pcb_dacr) {
2155 * No need to switch address spaces.
2163 * We MUST, I repeat, MUST fix up the L1 entry corresponding
2164 * to 'vector_page' in the incoming L1 table before switching
2165 * to it otherwise subsequent interrupts/exceptions (including
2166 * domain faults!) will jump into hyperspace.
2168 if (pcb->pcb_pl1vec) {
2170 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2172 * Don't need to PTE_SYNC() at this point since
2173 * cpu_setttb() is about to flush both the cache
2178 cpu_domains(pcb->pcb_dacr);
2179 cpu_setttb(pcb->pcb_pagedir);
2185 pmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va)
2187 pd_entry_t *pdep, pde;
2188 pt_entry_t *ptep, pte;
2193 * Make sure the descriptor itself has the correct cache mode
2195 pdep = &kl1[L1_IDX(va)];
2198 if (l1pte_section_p(pde)) {
2199 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) {
2200 *pdep = (pde & ~L1_S_CACHE_MASK) |
2201 pte_l1_s_cache_mode_pt;
2203 cpu_dcache_wbinv_range((vm_offset_t)pdep,
2205 cpu_l2cache_wbinv_range((vm_offset_t)pdep,
2210 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2211 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2213 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep);
2215 ptep = &ptep[l2pte_index(va)];
2217 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
2218 *ptep = (pte & ~L2_S_CACHE_MASK) |
2219 pte_l2_s_cache_mode_pt;
2221 cpu_dcache_wbinv_range((vm_offset_t)ptep,
2223 cpu_l2cache_wbinv_range((vm_offset_t)ptep,
2233 pmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap,
2236 vm_offset_t va = *availp;
2237 struct l2_bucket *l2b;
2240 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2242 panic("pmap_alloc_specials: no l2b for 0x%x", va);
2244 *ptep = &l2b->l2b_kva[l2pte_index(va)];
2248 *availp = va + (PAGE_SIZE * pages);
2252 * Bootstrap the system enough to run with virtual memory.
2254 * On the arm this is called after mapping has already been enabled
2255 * and just syncs the pmap module with what has already been done.
2256 * [We can't call it easily with mapping off since the kernel is not
2257 * mapped with PA == VA, hence we would have to relocate every address
2258 * from the linked base (virtual) address "KERNBASE" to the actual
2259 * (physical) address starting relative to 0]
2261 #define PMAP_STATIC_L2_SIZE 16
2262 #ifdef ARM_USE_SMALL_ALLOC
2263 extern struct mtx smallalloc_mtx;
2267 pmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt)
2269 static struct l1_ttable static_l1;
2270 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE];
2271 struct l1_ttable *l1 = &static_l1;
2272 struct l2_dtable *l2;
2273 struct l2_bucket *l2b;
2275 pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va;
2280 int l1idx, l2idx, l2next = 0;
2282 PDEBUG(1, printf("firstaddr = %08x, lastaddr = %08x\n",
2283 firstaddr, vm_max_kernel_address));
2285 virtual_avail = firstaddr;
2286 kernel_pmap->pm_l1 = l1;
2287 kernel_l1pa = l1pt->pv_pa;
2290 * Scan the L1 translation table created by initarm() and create
2291 * the required metadata for all valid mappings found in it.
2293 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) {
2294 pde = kernel_l1pt[l1idx];
2297 * We're only interested in Coarse mappings.
2298 * pmap_extract() can deal with section mappings without
2299 * recourse to checking L2 metadata.
2301 if ((pde & L1_TYPE_MASK) != L1_TYPE_C)
2305 * Lookup the KVA of this L2 descriptor table
2307 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2308 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2311 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx",
2312 (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa);
2316 * Fetch the associated L2 metadata structure.
2317 * Allocate a new one if necessary.
2319 if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) {
2320 if (l2next == PMAP_STATIC_L2_SIZE)
2321 panic("pmap_bootstrap: out of static L2s");
2322 kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 =
2323 &static_l2[l2next++];
2327 * One more L1 slot tracked...
2332 * Fill in the details of the L2 descriptor in the
2333 * appropriate bucket.
2335 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2336 l2b->l2b_kva = ptep;
2338 l2b->l2b_l1idx = l1idx;
2341 * Establish an initial occupancy count for this descriptor
2344 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
2346 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) {
2347 l2b->l2b_occupancy++;
2352 * Make sure the descriptor itself has the correct cache mode.
2353 * If not, fix it, but whine about the problem. Port-meisters
2354 * should consider this a clue to fix up their initarm()
2357 if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) {
2358 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2359 "L2 pte @ %p\n", ptep);
2365 * Ensure the primary (kernel) L1 has the correct cache mode for
2366 * a page table. Bitch if it is not correctly set.
2368 for (va = (vm_offset_t)kernel_l1pt;
2369 va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) {
2370 if (pmap_set_pt_cache_mode(kernel_l1pt, va))
2371 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2372 "primary L1 @ 0x%x\n", va);
2375 cpu_dcache_wbinv_all();
2376 cpu_l2cache_wbinv_all();
2380 PMAP_LOCK_INIT(kernel_pmap);
2381 CPU_FILL(&kernel_pmap->pm_active);
2382 kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL;
2383 TAILQ_INIT(&kernel_pmap->pm_pvlist);
2386 * Initialize the global pv list lock.
2388 rw_init_flags(&pvh_global_lock, "pmap pv global", RW_RECURSE);
2391 * Reserve some special page table entries/VA space for temporary
2394 #define SYSMAP(c, p, v, n) \
2395 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
2397 pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte);
2398 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte);
2399 pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte);
2400 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte);
2401 size = ((vm_max_kernel_address - pmap_curmaxkvaddr) + L1_S_OFFSET) /
2403 pmap_alloc_specials(&virtual_avail,
2404 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE,
2405 &pmap_kernel_l2ptp_kva, NULL);
2407 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE;
2408 pmap_alloc_specials(&virtual_avail,
2409 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE,
2410 &pmap_kernel_l2dtable_kva, NULL);
2412 pmap_alloc_specials(&virtual_avail,
2413 1, (vm_offset_t*)&_tmppt, NULL);
2414 pmap_alloc_specials(&virtual_avail,
2415 MAXDUMPPGS, (vm_offset_t *)&crashdumpmap, NULL);
2416 SLIST_INIT(&l1_list);
2417 TAILQ_INIT(&l1_lru_list);
2418 mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF);
2419 pmap_init_l1(l1, kernel_l1pt);
2420 cpu_dcache_wbinv_all();
2421 cpu_l2cache_wbinv_all();
2423 virtual_avail = round_page(virtual_avail);
2424 virtual_end = vm_max_kernel_address;
2425 kernel_vm_end = pmap_curmaxkvaddr;
2426 arm_nocache_startaddr = vm_max_kernel_address;
2427 mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF);
2429 #ifdef ARM_USE_SMALL_ALLOC
2430 mtx_init(&smallalloc_mtx, "Small alloc page list", NULL, MTX_DEF);
2431 arm_init_smallalloc();
2433 pmap_set_pcb_pagedir(kernel_pmap, thread0.td_pcb);
2436 /***************************************************
2437 * Pmap allocation/deallocation routines.
2438 ***************************************************/
2441 * Release any resources held by the given physical map.
2442 * Called when a pmap initialized by pmap_pinit is being released.
2443 * Should only be called if the map contains no valid mappings.
2446 pmap_release(pmap_t pmap)
2450 pmap_idcache_wbinv_all(pmap);
2451 cpu_l2cache_wbinv_all();
2452 pmap_tlb_flushID(pmap);
2454 if (vector_page < KERNBASE) {
2455 struct pcb *curpcb = PCPU_GET(curpcb);
2456 pcb = thread0.td_pcb;
2457 if (pmap_is_current(pmap)) {
2459 * Frob the L1 entry corresponding to the vector
2460 * page so that it contains the kernel pmap's domain
2461 * number. This will ensure pmap_remove() does not
2462 * pull the current vector page out from under us.
2465 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2466 cpu_domains(pcb->pcb_dacr);
2467 cpu_setttb(pcb->pcb_pagedir);
2470 pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE);
2472 * Make sure cpu_switch(), et al, DTRT. This is safe to do
2473 * since this process has no remaining mappings of its own.
2475 curpcb->pcb_pl1vec = pcb->pcb_pl1vec;
2476 curpcb->pcb_l1vec = pcb->pcb_l1vec;
2477 curpcb->pcb_dacr = pcb->pcb_dacr;
2478 curpcb->pcb_pagedir = pcb->pcb_pagedir;
2483 dprintf("pmap_release()\n");
2489 * Helper function for pmap_grow_l2_bucket()
2492 pmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap)
2494 struct l2_bucket *l2b;
2499 pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
2502 pa = VM_PAGE_TO_PHYS(pg);
2507 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2509 ptep = &l2b->l2b_kva[l2pte_index(va)];
2510 *ptep = L2_S_PROTO | pa | cache_mode |
2511 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE);
2517 * This is the same as pmap_alloc_l2_bucket(), except that it is only
2518 * used by pmap_growkernel().
2520 static __inline struct l2_bucket *
2521 pmap_grow_l2_bucket(pmap_t pm, vm_offset_t va)
2523 struct l2_dtable *l2;
2524 struct l2_bucket *l2b;
2525 struct l1_ttable *l1;
2532 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
2534 * No mapping at this address, as there is
2535 * no entry in the L1 table.
2536 * Need to allocate a new l2_dtable.
2538 nva = pmap_kernel_l2dtable_kva;
2539 if ((nva & PAGE_MASK) == 0) {
2541 * Need to allocate a backing page
2543 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2547 l2 = (struct l2_dtable *)nva;
2548 nva += sizeof(struct l2_dtable);
2550 if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva &
2553 * The new l2_dtable straddles a page boundary.
2554 * Map in another page to cover it.
2556 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2560 pmap_kernel_l2dtable_kva = nva;
2563 * Link it into the parent pmap
2565 pm->pm_l2[L2_IDX(l1idx)] = l2;
2566 memset(l2, 0, sizeof(*l2));
2569 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2572 * Fetch pointer to the L2 page table associated with the address.
2574 if (l2b->l2b_kva == NULL) {
2578 * No L2 page table has been allocated. Chances are, this
2579 * is because we just allocated the l2_dtable, above.
2581 nva = pmap_kernel_l2ptp_kva;
2582 ptep = (pt_entry_t *)nva;
2583 if ((nva & PAGE_MASK) == 0) {
2585 * Need to allocate a backing page
2587 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt,
2588 &pmap_kernel_l2ptp_phys))
2590 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t));
2592 memset(ptep, 0, L2_TABLE_SIZE_REAL);
2594 l2b->l2b_kva = ptep;
2595 l2b->l2b_l1idx = l1idx;
2596 l2b->l2b_phys = pmap_kernel_l2ptp_phys;
2598 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL;
2599 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL;
2602 /* Distribute new L1 entry to all other L1s */
2603 SLIST_FOREACH(l1, &l1_list, l1_link) {
2604 pl1pd = &l1->l1_kva[L1_IDX(va)];
2605 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) |
2615 * grow the number of kernel page table entries, if needed
2618 pmap_growkernel(vm_offset_t addr)
2620 pmap_t kpm = pmap_kernel();
2622 if (addr <= pmap_curmaxkvaddr)
2623 return; /* we are OK */
2626 * whoops! we need to add kernel PTPs
2629 /* Map 1MB at a time */
2630 for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE)
2631 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr);
2634 * flush out the cache, expensive but growkernel will happen so
2637 cpu_dcache_wbinv_all();
2638 cpu_l2cache_wbinv_all();
2641 kernel_vm_end = pmap_curmaxkvaddr;
2646 * Remove all pages from specified address space
2647 * this aids process exit speeds. Also, this code
2648 * is special cased for current process only, but
2649 * can have the more generic (and slightly slower)
2650 * mode enabled. This is much faster than pmap_remove
2651 * in the case of running down an entire address space.
2654 pmap_remove_pages(pmap_t pmap)
2656 struct pv_entry *pv, *npv;
2657 struct l2_bucket *l2b = NULL;
2661 rw_wlock(&pvh_global_lock);
2663 cpu_idcache_wbinv_all();
2664 cpu_l2cache_wbinv_all();
2665 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) {
2666 if (pv->pv_flags & PVF_WIRED || pv->pv_flags & PVF_UNMAN) {
2667 /* Cannot remove wired or unmanaged pages now. */
2668 npv = TAILQ_NEXT(pv, pv_plist);
2671 pmap->pm_stats.resident_count--;
2672 l2b = pmap_get_l2_bucket(pmap, pv->pv_va);
2673 KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages"));
2674 pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
2675 m = PHYS_TO_VM_PAGE(*pt & L2_ADDR_MASK);
2676 #ifdef ARM_USE_SMALL_ALLOC
2677 KASSERT((vm_offset_t)m >= alloc_firstaddr, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt));
2679 KASSERT((vm_offset_t)m >= KERNBASE, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt));
2683 npv = TAILQ_NEXT(pv, pv_plist);
2684 pmap_nuke_pv(m, pmap, pv);
2685 if (TAILQ_EMPTY(&m->md.pv_list))
2686 vm_page_aflag_clear(m, PGA_WRITEABLE);
2687 pmap_free_pv_entry(pv);
2688 pmap_free_l2_bucket(pmap, l2b, 1);
2690 rw_wunlock(&pvh_global_lock);
2697 /***************************************************
2698 * Low level mapping routines.....
2699 ***************************************************/
2701 #ifdef ARM_HAVE_SUPERSECTIONS
2702 /* Map a super section into the KVA. */
2705 pmap_kenter_supersection(vm_offset_t va, uint64_t pa, int flags)
2707 pd_entry_t pd = L1_S_PROTO | L1_S_SUPERSEC | (pa & L1_SUP_FRAME) |
2708 (((pa >> 32) & 0xf) << 20) | L1_S_PROT(PTE_KERNEL,
2709 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
2710 struct l1_ttable *l1;
2711 vm_offset_t va0, va_end;
2713 KASSERT(((va | pa) & L1_SUP_OFFSET) == 0,
2714 ("Not a valid super section mapping"));
2715 if (flags & SECTION_CACHE)
2716 pd |= pte_l1_s_cache_mode;
2717 else if (flags & SECTION_PT)
2718 pd |= pte_l1_s_cache_mode_pt;
2719 va0 = va & L1_SUP_FRAME;
2720 va_end = va + L1_SUP_SIZE;
2721 SLIST_FOREACH(l1, &l1_list, l1_link) {
2723 for (; va < va_end; va += L1_S_SIZE) {
2724 l1->l1_kva[L1_IDX(va)] = pd;
2725 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2731 /* Map a section into the KVA. */
2734 pmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags)
2736 pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL,
2737 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
2738 struct l1_ttable *l1;
2740 KASSERT(((va | pa) & L1_S_OFFSET) == 0,
2741 ("Not a valid section mapping"));
2742 if (flags & SECTION_CACHE)
2743 pd |= pte_l1_s_cache_mode;
2744 else if (flags & SECTION_PT)
2745 pd |= pte_l1_s_cache_mode_pt;
2746 SLIST_FOREACH(l1, &l1_list, l1_link) {
2747 l1->l1_kva[L1_IDX(va)] = pd;
2748 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2753 * Make a temporary mapping for a physical address. This is only intended
2754 * to be used for panic dumps.
2757 pmap_kenter_temp(vm_paddr_t pa, int i)
2761 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
2762 pmap_kenter(va, pa);
2763 return ((void *)crashdumpmap);
2767 * add a wired page to the kva
2768 * note that in order for the mapping to take effect -- you
2769 * should do a invltlb after doing the pmap_kenter...
2771 static PMAP_INLINE void
2772 pmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags)
2774 struct l2_bucket *l2b;
2777 struct pv_entry *pve;
2780 PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n",
2781 (uint32_t) va, (uint32_t) pa));
2784 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2786 l2b = pmap_grow_l2_bucket(pmap_kernel(), va);
2787 KASSERT(l2b != NULL, ("No L2 Bucket"));
2788 pte = &l2b->l2b_kva[l2pte_index(va)];
2790 PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n",
2791 (uint32_t) pte, opte, *pte));
2792 if (l2pte_valid(opte)) {
2796 l2b->l2b_occupancy++;
2798 *pte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL,
2799 VM_PROT_READ | VM_PROT_WRITE);
2800 if (flags & KENTER_CACHE)
2801 *pte |= pte_l2_s_cache_mode;
2802 if (flags & KENTER_USER)
2803 *pte |= L2_S_PROT_U;
2807 * A kernel mapping may not be the page's only mapping, so create a PV
2808 * entry to ensure proper caching.
2810 * The existence test for the pvzone is used to delay the recording of
2811 * kernel mappings until the VM system is fully initialized.
2813 * This expects the physical memory to have a vm_page_array entry.
2815 if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa)) != NULL) {
2816 rw_wlock(&pvh_global_lock);
2817 if (!TAILQ_EMPTY(&m->md.pv_list) || m->md.pv_kva != 0) {
2818 if ((pve = pmap_get_pv_entry()) == NULL)
2819 panic("pmap_kenter_internal: no pv entries");
2820 PMAP_LOCK(pmap_kernel());
2821 pmap_enter_pv(m, pve, pmap_kernel(), va,
2822 PVF_WRITE | PVF_UNMAN);
2823 pmap_fix_cache(m, pmap_kernel(), va);
2824 PMAP_UNLOCK(pmap_kernel());
2828 rw_wunlock(&pvh_global_lock);
2833 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2835 pmap_kenter_internal(va, pa, KENTER_CACHE);
2839 pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa)
2842 pmap_kenter_internal(va, pa, 0);
2846 pmap_kenter_user(vm_offset_t va, vm_paddr_t pa)
2849 pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER);
2851 * Call pmap_fault_fixup now, to make sure we'll have no exception
2852 * at the first use of the new address, or bad things will happen,
2853 * as we use one of these addresses in the exception handlers.
2855 pmap_fault_fixup(pmap_kernel(), va, VM_PROT_READ|VM_PROT_WRITE, 1);
2859 pmap_kextract(vm_offset_t va)
2862 return (pmap_extract_locked(kernel_pmap, va));
2866 * remove a page from the kernel pagetables
2869 pmap_kremove(vm_offset_t va)
2871 struct l2_bucket *l2b;
2872 pt_entry_t *pte, opte;
2873 struct pv_entry *pve;
2877 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2880 KASSERT(l2b != NULL, ("No L2 Bucket"));
2881 pte = &l2b->l2b_kva[l2pte_index(va)];
2883 if (l2pte_valid(opte)) {
2884 /* pa = vtophs(va) taken from pmap_extract() */
2885 switch (opte & L2_TYPE_MASK) {
2887 pa = (opte & L2_L_FRAME) | (va & L2_L_OFFSET);
2890 pa = (opte & L2_S_FRAME) | (va & L2_S_OFFSET);
2893 /* note: should never have to remove an allocation
2894 * before the pvzone is initialized.
2896 rw_wlock(&pvh_global_lock);
2897 PMAP_LOCK(pmap_kernel());
2898 if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa)) &&
2899 (pve = pmap_remove_pv(m, pmap_kernel(), va)))
2900 pmap_free_pv_entry(pve);
2901 PMAP_UNLOCK(pmap_kernel());
2902 rw_wunlock(&pvh_global_lock);
2903 va = va & ~PAGE_MASK;
2904 cpu_dcache_wbinv_range(va, PAGE_SIZE);
2905 cpu_l2cache_wbinv_range(va, PAGE_SIZE);
2906 cpu_tlb_flushD_SE(va);
2914 * Used to map a range of physical addresses into kernel
2915 * virtual address space.
2917 * The value passed in '*virt' is a suggested virtual address for
2918 * the mapping. Architectures which can support a direct-mapped
2919 * physical to virtual region can return the appropriate address
2920 * within that region, leaving '*virt' unchanged. Other
2921 * architectures should map the pages starting at '*virt' and
2922 * update '*virt' with the first usable address after the mapped
2926 pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot)
2928 #ifdef ARM_USE_SMALL_ALLOC
2929 return (arm_ptovirt(start));
2931 vm_offset_t sva = *virt;
2932 vm_offset_t va = sva;
2934 PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, "
2935 "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end,
2938 while (start < end) {
2939 pmap_kenter(va, start);
2949 pmap_wb_page(vm_page_t m)
2951 struct pv_entry *pv;
2953 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
2954 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, FALSE,
2955 (pv->pv_flags & PVF_WRITE) == 0);
2959 pmap_inv_page(vm_page_t m)
2961 struct pv_entry *pv;
2963 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
2964 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, TRUE, TRUE);
2967 * Add a list of wired pages to the kva
2968 * this routine is only used for temporary
2969 * kernel mappings that do not need to have
2970 * page modification or references recorded.
2971 * Note that old mappings are simply written
2972 * over. The page *must* be wired.
2975 pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
2979 for (i = 0; i < count; i++) {
2981 pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]),
2989 * this routine jerks page mappings from the
2990 * kernel -- it is meant only for temporary mappings.
2993 pmap_qremove(vm_offset_t va, int count)
2998 for (i = 0; i < count; i++) {
3001 pmap_inv_page(PHYS_TO_VM_PAGE(pa));
3010 * pmap_object_init_pt preloads the ptes for a given object
3011 * into the specified pmap. This eliminates the blast of soft
3012 * faults on process startup and immediately after an mmap.
3015 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3016 vm_pindex_t pindex, vm_size_t size)
3019 VM_OBJECT_ASSERT_WLOCKED(object);
3020 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3021 ("pmap_object_init_pt: non-device object"));
3026 * pmap_is_prefaultable:
3028 * Return whether or not the specified virtual address is elgible
3032 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3037 if (!pmap_get_pde_pte(pmap, addr, &pde, &pte))
3039 KASSERT(pte != NULL, ("Valid mapping but no pte ?"));
3046 * Fetch pointers to the PDE/PTE for the given pmap/VA pair.
3047 * Returns TRUE if the mapping exists, else FALSE.
3049 * NOTE: This function is only used by a couple of arm-specific modules.
3050 * It is not safe to take any pmap locks here, since we could be right
3051 * in the middle of debugging the pmap anyway...
3053 * It is possible for this routine to return FALSE even though a valid
3054 * mapping does exist. This is because we don't lock, so the metadata
3055 * state may be inconsistent.
3057 * NOTE: We can return a NULL *ptp in the case where the L1 pde is
3058 * a "section" mapping.
3061 pmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp)
3063 struct l2_dtable *l2;
3064 pd_entry_t *pl1pd, l1pd;
3068 if (pm->pm_l1 == NULL)
3072 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx];
3075 if (l1pte_section_p(l1pd)) {
3080 if (pm->pm_l2 == NULL)
3083 l2 = pm->pm_l2[L2_IDX(l1idx)];
3086 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3090 *ptp = &ptep[l2pte_index(va)];
3095 * Routine: pmap_remove_all
3097 * Removes this physical page from
3098 * all physical maps in which it resides.
3099 * Reflects back modify bits to the pager.
3102 * Original versions of this routine were very
3103 * inefficient because they iteratively called
3104 * pmap_remove (slow...)
3107 pmap_remove_all(vm_page_t m)
3111 struct l2_bucket *l2b;
3112 boolean_t flush = FALSE;
3116 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3117 ("pmap_remove_all: page %p is not managed", m));
3118 if (TAILQ_EMPTY(&m->md.pv_list))
3120 rw_wlock(&pvh_global_lock);
3121 pmap_remove_write(m);
3122 curpm = vmspace_pmap(curproc->p_vmspace);
3123 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3124 if (flush == FALSE && (pv->pv_pmap == curpm ||
3125 pv->pv_pmap == pmap_kernel()))
3128 PMAP_LOCK(pv->pv_pmap);
3130 * Cached contents were written-back in pmap_remove_write(),
3131 * but we still have to invalidate the cache entry to make
3132 * sure stale data are not retrieved when another page will be
3133 * mapped under this virtual address.
3135 if (pmap_is_current(pv->pv_pmap)) {
3136 cpu_dcache_inv_range(pv->pv_va, PAGE_SIZE);
3137 if (pmap_has_valid_mapping(pv->pv_pmap, pv->pv_va))
3138 cpu_l2cache_inv_range(pv->pv_va, PAGE_SIZE);
3141 if (pv->pv_flags & PVF_UNMAN) {
3142 /* remove the pv entry, but do not remove the mapping
3143 * and remember this is a kernel mapped page
3145 m->md.pv_kva = pv->pv_va;
3147 /* remove the mapping and pv entry */
3148 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
3149 KASSERT(l2b != NULL, ("No l2 bucket"));
3150 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
3152 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
3153 pmap_free_l2_bucket(pv->pv_pmap, l2b, 1);
3154 pv->pv_pmap->pm_stats.resident_count--;
3155 flags |= pv->pv_flags;
3157 pmap_nuke_pv(m, pv->pv_pmap, pv);
3158 PMAP_UNLOCK(pv->pv_pmap);
3159 pmap_free_pv_entry(pv);
3163 if (PV_BEEN_EXECD(flags))
3164 pmap_tlb_flushID(curpm);
3166 pmap_tlb_flushD(curpm);
3168 vm_page_aflag_clear(m, PGA_WRITEABLE);
3169 rw_wunlock(&pvh_global_lock);
3174 * Set the physical protection on the
3175 * specified range of this map as requested.
3178 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3180 struct l2_bucket *l2b;
3181 pt_entry_t *ptep, pte;
3182 vm_offset_t next_bucket;
3186 CTR4(KTR_PMAP, "pmap_protect: pmap %p sva 0x%08x eva 0x%08x prot %x",
3187 pm, sva, eva, prot);
3189 if ((prot & VM_PROT_READ) == 0) {
3190 pmap_remove(pm, sva, eva);
3194 if (prot & VM_PROT_WRITE) {
3196 * If this is a read->write transition, just ignore it and let
3197 * vm_fault() take care of it later.
3202 rw_wlock(&pvh_global_lock);
3206 * OK, at this point, we know we're doing write-protect operation.
3207 * If the pmap is active, write-back the range.
3209 pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE);
3211 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1;
3215 next_bucket = L2_NEXT_BUCKET(sva);
3216 if (next_bucket > eva)
3219 l2b = pmap_get_l2_bucket(pm, sva);
3225 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3227 while (sva < next_bucket) {
3228 if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) {
3232 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
3233 pte &= ~L2_S_PROT_W;
3237 if (!(pg->oflags & VPO_UNMANAGED)) {
3238 f = pmap_modify_pv(pg, pm, sva,
3249 if (PV_BEEN_EXECD(f))
3250 pmap_tlb_flushID_SE(pm, sva);
3252 if (PV_BEEN_REFD(f))
3253 pmap_tlb_flushD_SE(pm, sva);
3263 if (PV_BEEN_EXECD(flags))
3264 pmap_tlb_flushID(pm);
3266 if (PV_BEEN_REFD(flags))
3267 pmap_tlb_flushD(pm);
3269 rw_wunlock(&pvh_global_lock);
3276 * Insert the given physical page (p) at
3277 * the specified virtual address (v) in the
3278 * target physical map with the protection requested.
3280 * If specified, the page will be wired down, meaning
3281 * that the related pte can not be reclaimed.
3283 * NB: This is the only routine which MAY NOT lazy-evaluate
3284 * or lose information. That is, this routine must actually
3285 * insert this page into the given map NOW.
3289 pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
3290 vm_prot_t prot, boolean_t wired)
3293 rw_wlock(&pvh_global_lock);
3295 pmap_enter_locked(pmap, va, m, prot, wired, M_WAITOK);
3296 rw_wunlock(&pvh_global_lock);
3301 * The pvh global and pmap locks must be held.
3304 pmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3305 boolean_t wired, int flags)
3307 struct l2_bucket *l2b = NULL;
3308 struct vm_page *opg;
3309 struct pv_entry *pve = NULL;
3310 pt_entry_t *ptep, npte, opte;
3315 PMAP_ASSERT_LOCKED(pmap);
3316 rw_assert(&pvh_global_lock, RA_WLOCKED);
3317 if (va == vector_page) {
3318 pa = systempage.pv_pa;
3321 KASSERT((m->oflags & VPO_UNMANAGED) != 0 ||
3322 vm_page_xbusied(m) || (flags & M_NOWAIT) != 0,
3323 ("pmap_enter_locked: page %p is not busy", m));
3324 pa = VM_PAGE_TO_PHYS(m);
3327 if (prot & VM_PROT_WRITE)
3328 nflags |= PVF_WRITE;
3329 if (prot & VM_PROT_EXECUTE)
3332 nflags |= PVF_WIRED;
3333 PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, "
3334 "wired = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, wired));
3336 if (pmap == pmap_kernel()) {
3337 l2b = pmap_get_l2_bucket(pmap, va);
3339 l2b = pmap_grow_l2_bucket(pmap, va);
3342 l2b = pmap_alloc_l2_bucket(pmap, va);
3344 if (flags & M_WAITOK) {
3346 rw_wunlock(&pvh_global_lock);
3348 rw_wlock(&pvh_global_lock);
3356 ptep = &l2b->l2b_kva[l2pte_index(va)];
3363 * There is already a mapping at this address.
3364 * If the physical address is different, lookup the
3367 if (l2pte_pa(opte) != pa)
3368 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte));
3374 if ((prot & (VM_PROT_ALL)) ||
3375 (!m || m->md.pvh_attrs & PVF_REF)) {
3377 * - The access type indicates that we don't need
3378 * to do referenced emulation.
3380 * - The physical page has already been referenced
3381 * so no need to re-do referenced emulation here.
3387 if (m && ((prot & VM_PROT_WRITE) != 0 ||
3388 (m->md.pvh_attrs & PVF_MOD))) {
3390 * This is a writable mapping, and the
3391 * page's mod state indicates it has
3392 * already been modified. Make it
3393 * writable from the outset.
3396 if (!(m->md.pvh_attrs & PVF_MOD))
3400 vm_page_aflag_set(m, PGA_REFERENCED);
3403 * Need to do page referenced emulation.
3405 npte |= L2_TYPE_INV;
3408 if (prot & VM_PROT_WRITE) {
3409 npte |= L2_S_PROT_W;
3411 (m->oflags & VPO_UNMANAGED) == 0)
3412 vm_page_aflag_set(m, PGA_WRITEABLE);
3414 if (m->md.pv_memattr != VM_MEMATTR_UNCACHEABLE)
3415 npte |= pte_l2_s_cache_mode;
3416 if (m && m == opg) {
3418 * We're changing the attrs of an existing mapping.
3420 oflags = pmap_modify_pv(m, pmap, va,
3421 PVF_WRITE | PVF_EXEC | PVF_WIRED |
3422 PVF_MOD | PVF_REF, nflags);
3425 * We may need to flush the cache if we're
3428 if (pmap_is_current(pmap) &&
3429 (oflags & PVF_NC) == 0 &&
3430 (opte & L2_S_PROT_W) != 0 &&
3431 (prot & VM_PROT_WRITE) == 0 &&
3432 (opte & L2_TYPE_MASK) != L2_TYPE_INV) {
3433 cpu_dcache_wb_range(va, PAGE_SIZE);
3434 cpu_l2cache_wb_range(va, PAGE_SIZE);
3438 * New mapping, or changing the backing page
3439 * of an existing mapping.
3443 * Replacing an existing mapping with a new one.
3444 * It is part of our managed memory so we
3445 * must remove it from the PV list
3447 if ((pve = pmap_remove_pv(opg, pmap, va))) {
3449 /* note for patch: the oflags/invalidation was moved
3450 * because PG_FICTITIOUS pages could free the pve
3452 oflags = pve->pv_flags;
3454 * If the old mapping was valid (ref/mod
3455 * emulation creates 'invalid' mappings
3456 * initially) then make sure to frob
3459 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) {
3460 if (PV_BEEN_EXECD(oflags)) {
3461 pmap_idcache_wbinv_range(pmap, va,
3464 if (PV_BEEN_REFD(oflags)) {
3465 pmap_dcache_wb_range(pmap, va,
3467 (oflags & PVF_WRITE) == 0);
3471 /* free/allocate a pv_entry for UNMANAGED pages if
3472 * this physical page is not/is already mapped.
3475 if (m && (m->oflags & VPO_UNMANAGED) &&
3477 TAILQ_EMPTY(&m->md.pv_list)) {
3478 pmap_free_pv_entry(pve);
3482 (!(m->oflags & VPO_UNMANAGED) || m->md.pv_kva ||
3483 !TAILQ_EMPTY(&m->md.pv_list)))
3484 pve = pmap_get_pv_entry();
3486 (!(m->oflags & VPO_UNMANAGED) || m->md.pv_kva ||
3487 !TAILQ_EMPTY(&m->md.pv_list)))
3488 pve = pmap_get_pv_entry();
3491 if ((m->oflags & VPO_UNMANAGED)) {
3492 if (!TAILQ_EMPTY(&m->md.pv_list) ||
3494 KASSERT(pve != NULL, ("No pv"));
3495 nflags |= PVF_UNMAN;
3496 pmap_enter_pv(m, pve, pmap, va, nflags);
3500 KASSERT(va < kmi.clean_sva ||
3501 va >= kmi.clean_eva,
3502 ("pmap_enter: managed mapping within the clean submap"));
3503 KASSERT(pve != NULL, ("No pv"));
3504 pmap_enter_pv(m, pve, pmap, va, nflags);
3509 * Make sure userland mappings get the right permissions
3511 if (pmap != pmap_kernel() && va != vector_page) {
3512 npte |= L2_S_PROT_U;
3516 * Keep the stats up to date
3519 l2b->l2b_occupancy++;
3520 pmap->pm_stats.resident_count++;
3524 * If this is just a wiring change, the two PTEs will be
3525 * identical, so there's no need to update the page table.
3528 boolean_t is_cached = pmap_is_current(pmap);
3533 * We only need to frob the cache/tlb if this pmap
3537 if (L1_IDX(va) != L1_IDX(vector_page) &&
3538 l2pte_valid(npte)) {
3540 * This mapping is likely to be accessed as
3541 * soon as we return to userland. Fix up the
3542 * L1 entry to avoid taking another
3543 * page/domain fault.
3545 pd_entry_t *pl1pd, l1pd;
3547 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
3548 l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) |
3550 if (*pl1pd != l1pd) {
3557 if (PV_BEEN_EXECD(oflags))
3558 pmap_tlb_flushID_SE(pmap, va);
3559 else if (PV_BEEN_REFD(oflags))
3560 pmap_tlb_flushD_SE(pmap, va);
3564 pmap_fix_cache(m, pmap, va);
3569 * Maps a sequence of resident pages belonging to the same object.
3570 * The sequence begins with the given page m_start. This page is
3571 * mapped at the given virtual address start. Each subsequent page is
3572 * mapped at a virtual address that is offset from start by the same
3573 * amount as the page is offset from m_start within the object. The
3574 * last page in the sequence is the page with the largest offset from
3575 * m_start that can be mapped at a virtual address less than the given
3576 * virtual address end. Not every virtual page between start and end
3577 * is mapped; only those for which a resident page exists with the
3578 * corresponding offset from m_start are mapped.
3581 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3582 vm_page_t m_start, vm_prot_t prot)
3585 vm_pindex_t diff, psize;
3587 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3589 psize = atop(end - start);
3591 rw_wlock(&pvh_global_lock);
3593 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3594 pmap_enter_locked(pmap, start + ptoa(diff), m, prot &
3595 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE, M_NOWAIT);
3596 m = TAILQ_NEXT(m, listq);
3598 rw_wunlock(&pvh_global_lock);
3603 * this code makes some *MAJOR* assumptions:
3604 * 1. Current pmap & pmap exists.
3607 * 4. No page table pages.
3608 * but is *MUCH* faster than pmap_enter...
3612 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3615 rw_wlock(&pvh_global_lock);
3617 pmap_enter_locked(pmap, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
3619 rw_wunlock(&pvh_global_lock);
3624 * Routine: pmap_change_wiring
3625 * Function: Change the wiring attribute for a map/virtual-address
3627 * In/out conditions:
3628 * The mapping must already exist in the pmap.
3631 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
3633 struct l2_bucket *l2b;
3634 pt_entry_t *ptep, pte;
3637 rw_wlock(&pvh_global_lock);
3639 l2b = pmap_get_l2_bucket(pmap, va);
3640 KASSERT(l2b, ("No l2b bucket in pmap_change_wiring"));
3641 ptep = &l2b->l2b_kva[l2pte_index(va)];
3643 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
3645 pmap_modify_pv(pg, pmap, va, PVF_WIRED, wired ? PVF_WIRED : 0);
3646 rw_wunlock(&pvh_global_lock);
3652 * Copy the range specified by src_addr/len
3653 * from the source map to the range dst_addr/len
3654 * in the destination map.
3656 * This routine is only advisory and need not do anything.
3659 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
3660 vm_size_t len, vm_offset_t src_addr)
3666 * Routine: pmap_extract
3668 * Extract the physical page address associated
3669 * with the given map/virtual_address pair.
3672 pmap_extract(pmap_t pmap, vm_offset_t va)
3677 pa = pmap_extract_locked(pmap, va);
3683 pmap_extract_locked(pmap_t pmap, vm_offset_t va)
3685 struct l2_dtable *l2;
3687 pt_entry_t *ptep, pte;
3691 if (pmap != kernel_pmap)
3692 PMAP_ASSERT_LOCKED(pmap);
3694 l1pd = pmap->pm_l1->l1_kva[l1idx];
3695 if (l1pte_section_p(l1pd)) {
3697 * These should only happen for the kernel pmap.
3699 KASSERT(pmap == kernel_pmap, ("unexpected section"));
3700 /* XXX: what to do about the bits > 32 ? */
3701 if (l1pd & L1_S_SUPERSEC)
3702 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3704 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3707 * Note that we can't rely on the validity of the L1
3708 * descriptor as an indication that a mapping exists.
3709 * We have to look it up in the L2 dtable.
3711 l2 = pmap->pm_l2[L2_IDX(l1idx)];
3713 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL)
3715 pte = ptep[l2pte_index(va)];
3718 switch (pte & L2_TYPE_MASK) {
3720 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3723 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3731 * Atomically extract and hold the physical page with the given
3732 * pmap and virtual address pair if that mapping permits the given
3737 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3739 struct l2_dtable *l2;
3741 pt_entry_t *ptep, pte;
3742 vm_paddr_t pa, paddr;
3750 l1pd = pmap->pm_l1->l1_kva[l1idx];
3751 if (l1pte_section_p(l1pd)) {
3753 * These should only happen for pmap_kernel()
3755 KASSERT(pmap == pmap_kernel(), ("huh"));
3756 /* XXX: what to do about the bits > 32 ? */
3757 if (l1pd & L1_S_SUPERSEC)
3758 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3760 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3761 if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr))
3763 if (l1pd & L1_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3764 m = PHYS_TO_VM_PAGE(pa);
3770 * Note that we can't rely on the validity of the L1
3771 * descriptor as an indication that a mapping exists.
3772 * We have to look it up in the L2 dtable.
3774 l2 = pmap->pm_l2[L2_IDX(l1idx)];
3777 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3782 ptep = &ptep[l2pte_index(va)];
3789 if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3790 switch (pte & L2_TYPE_MASK) {
3792 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3796 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3799 if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr))
3801 m = PHYS_TO_VM_PAGE(pa);
3807 PA_UNLOCK_COND(paddr);
3812 * Initialize a preallocated and zeroed pmap structure,
3813 * such as one in a vmspace structure.
3817 pmap_pinit(pmap_t pmap)
3819 PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap));
3821 pmap_alloc_l1(pmap);
3822 bzero(pmap->pm_l2, sizeof(pmap->pm_l2));
3824 CPU_ZERO(&pmap->pm_active);
3826 TAILQ_INIT(&pmap->pm_pvlist);
3827 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3828 pmap->pm_stats.resident_count = 1;
3829 if (vector_page < KERNBASE) {
3830 pmap_enter(pmap, vector_page,
3831 VM_PROT_READ, PHYS_TO_VM_PAGE(systempage.pv_pa),
3838 /***************************************************
3839 * page management routines.
3840 ***************************************************/
3844 pmap_free_pv_entry(pv_entry_t pv)
3847 uma_zfree(pvzone, pv);
3852 * get a new pv_entry, allocating a block from the system
3854 * the memory allocation is performed bypassing the malloc code
3855 * because of the possibility of allocations at interrupt time.
3858 pmap_get_pv_entry(void)
3860 pv_entry_t ret_value;
3863 if (pv_entry_count > pv_entry_high_water)
3864 pagedaemon_wakeup();
3865 ret_value = uma_zalloc(pvzone, M_NOWAIT);
3870 * Remove the given range of addresses from the specified map.
3872 * It is assumed that the start and end are properly
3873 * rounded to the page size.
3875 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3
3877 pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva)
3879 struct l2_bucket *l2b;
3880 vm_offset_t next_bucket;
3883 u_int mappings, is_exec, is_refd;
3888 * we lock in the pmap => pv_head direction
3891 rw_wlock(&pvh_global_lock);
3896 * Do one L2 bucket's worth at a time.
3898 next_bucket = L2_NEXT_BUCKET(sva);
3899 if (next_bucket > eva)
3902 l2b = pmap_get_l2_bucket(pm, sva);
3908 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3911 while (sva < next_bucket) {
3920 * Nothing here, move along
3927 pm->pm_stats.resident_count--;
3933 * Update flags. In a number of circumstances,
3934 * we could cluster a lot of these and do a
3935 * number of sequential pages in one go.
3937 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) {
3938 struct pv_entry *pve;
3940 pve = pmap_remove_pv(pg, pm, sva);
3942 is_exec = PV_BEEN_EXECD(pve->pv_flags);
3943 is_refd = PV_BEEN_REFD(pve->pv_flags);
3944 pmap_free_pv_entry(pve);
3948 if (l2pte_valid(pte) && pmap_is_current(pm)) {
3949 if (total < PMAP_REMOVE_CLEAN_LIST_SIZE) {
3952 cpu_idcache_wbinv_range(sva,
3954 cpu_l2cache_wbinv_range(sva,
3956 cpu_tlb_flushID_SE(sva);
3957 } else if (is_refd) {
3958 cpu_dcache_wbinv_range(sva,
3960 cpu_l2cache_wbinv_range(sva,
3962 cpu_tlb_flushD_SE(sva);
3964 } else if (total == PMAP_REMOVE_CLEAN_LIST_SIZE) {
3965 /* flushall will also only get set for
3966 * for a current pmap
3968 cpu_idcache_wbinv_all();
3969 cpu_l2cache_wbinv_all();
3982 pmap_free_l2_bucket(pm, l2b, mappings);
3985 rw_wunlock(&pvh_global_lock);
3994 * Zero a given physical page by mapping it at a page hook point.
3995 * In doing the zero page op, the page we zero is mapped cachable, as with
3996 * StrongARM accesses to non-cached pages are non-burst making writing
3997 * _any_ bulk data very slow.
3999 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_CORE3)
4001 pmap_zero_page_generic(vm_paddr_t phys, int off, int size)
4003 #ifdef ARM_USE_SMALL_ALLOC
4007 if (_arm_bzero && size >= _min_bzero_size &&
4008 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0)
4011 #ifdef ARM_USE_SMALL_ALLOC
4012 dstpg = (char *)arm_ptovirt(phys);
4013 if (off || size != PAGE_SIZE) {
4014 bzero(dstpg + off, size);
4015 cpu_dcache_wbinv_range((vm_offset_t)(dstpg + off), size);
4016 cpu_l2cache_wbinv_range((vm_offset_t)(dstpg + off), size);
4018 bzero_page((vm_offset_t)dstpg);
4019 cpu_dcache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE);
4020 cpu_l2cache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE);
4026 * Hook in the page, zero it, invalidate the TLB as needed.
4028 * Note the temporary zero-page mapping must be a non-cached page in
4029 * order to work without corruption when write-allocate is enabled.
4031 *cdst_pte = L2_S_PROTO | phys | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE);
4033 cpu_tlb_flushD_SE(cdstp);
4035 if (off || size != PAGE_SIZE)
4036 bzero((void *)(cdstp + off), size);
4043 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
4045 #if ARM_MMU_XSCALE == 1
4047 pmap_zero_page_xscale(vm_paddr_t phys, int off, int size)
4049 #ifdef ARM_USE_SMALL_ALLOC
4053 if (_arm_bzero && size >= _min_bzero_size &&
4054 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0)
4056 #ifdef ARM_USE_SMALL_ALLOC
4057 dstpg = (char *)arm_ptovirt(phys);
4058 if (off || size != PAGE_SIZE) {
4059 bzero(dstpg + off, size);
4060 cpu_dcache_wbinv_range((vm_offset_t)(dstpg + off), size);
4062 bzero_page((vm_offset_t)dstpg);
4063 cpu_dcache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE);
4068 * Hook in the page, zero it, and purge the cache for that
4069 * zeroed page. Invalidate the TLB as needed.
4071 *cdst_pte = L2_S_PROTO | phys |
4072 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4073 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4075 cpu_tlb_flushD_SE(cdstp);
4077 if (off || size != PAGE_SIZE)
4078 bzero((void *)(cdstp + off), size);
4082 xscale_cache_clean_minidata();
4087 * Change the PTEs for the specified kernel mappings such that they
4088 * will use the mini data cache instead of the main data cache.
4091 pmap_use_minicache(vm_offset_t va, vm_size_t size)
4093 struct l2_bucket *l2b;
4094 pt_entry_t *ptep, *sptep, pte;
4095 vm_offset_t next_bucket, eva;
4097 #if (ARM_NMMUS > 1) || defined(CPU_XSCALE_CORE3)
4098 if (xscale_use_minidata == 0)
4105 next_bucket = L2_NEXT_BUCKET(va);
4106 if (next_bucket > eva)
4109 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
4111 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)];
4113 while (va < next_bucket) {
4115 if (!l2pte_minidata(pte)) {
4116 cpu_dcache_wbinv_range(va, PAGE_SIZE);
4117 cpu_tlb_flushD_SE(va);
4118 *ptep = pte & ~L2_B;
4123 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep));
4127 #endif /* ARM_MMU_XSCALE == 1 */
4130 * pmap_zero_page zeros the specified hardware page by mapping
4131 * the page into KVM and using bzero to clear its contents.
4134 pmap_zero_page(vm_page_t m)
4136 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), 0, PAGE_SIZE);
4141 * pmap_zero_page_area zeros the specified hardware page by mapping
4142 * the page into KVM and using bzero to clear its contents.
4144 * off and size may not cover an area beyond a single hardware page.
4147 pmap_zero_page_area(vm_page_t m, int off, int size)
4150 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), off, size);
4155 * pmap_zero_page_idle zeros the specified hardware page by mapping
4156 * the page into KVM and using bzero to clear its contents. This
4157 * is intended to be called from the vm_pagezero process only and
4161 pmap_zero_page_idle(vm_page_t m)
4171 * This is a local function used to work out the best strategy to clean
4172 * a single page referenced by its entry in the PV table. It should be used by
4173 * pmap_copy_page, pmap_zero page and maybe some others later on.
4175 * Its policy is effectively:
4176 * o If there are no mappings, we don't bother doing anything with the cache.
4177 * o If there is one mapping, we clean just that page.
4178 * o If there are multiple mappings, we clean the entire cache.
4180 * So that some functions can be further optimised, it returns 0 if it didn't
4181 * clean the entire cache, or 1 if it did.
4183 * XXX One bug in this routine is that if the pv_entry has a single page
4184 * mapped at 0x00000000 a whole cache clean will be performed rather than
4185 * just the 1 page. Since this should not occur in everyday use and if it does
4186 * it will just result in not the most efficient clean for the page.
4188 * We don't yet use this function but may want to.
4191 pmap_clean_page(struct pv_entry *pv, boolean_t is_src)
4193 pmap_t pm, pm_to_clean = NULL;
4194 struct pv_entry *npv;
4195 u_int cache_needs_cleaning = 0;
4197 vm_offset_t page_to_clean = 0;
4200 /* nothing mapped in so nothing to flush */
4205 * Since we flush the cache each time we change to a different
4206 * user vmspace, we only need to flush the page if it is in the
4210 pm = vmspace_pmap(curproc->p_vmspace);
4214 for (npv = pv; npv; npv = TAILQ_NEXT(npv, pv_list)) {
4215 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) {
4216 flags |= npv->pv_flags;
4218 * The page is mapped non-cacheable in
4219 * this map. No need to flush the cache.
4221 if (npv->pv_flags & PVF_NC) {
4223 if (cache_needs_cleaning)
4224 panic("pmap_clean_page: "
4225 "cache inconsistency");
4228 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0)
4230 if (cache_needs_cleaning) {
4234 page_to_clean = npv->pv_va;
4235 pm_to_clean = npv->pv_pmap;
4237 cache_needs_cleaning = 1;
4240 if (page_to_clean) {
4241 if (PV_BEEN_EXECD(flags))
4242 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean,
4245 pmap_dcache_wb_range(pm_to_clean, page_to_clean,
4246 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0);
4247 } else if (cache_needs_cleaning) {
4248 if (PV_BEEN_EXECD(flags))
4249 pmap_idcache_wbinv_all(pm);
4251 pmap_dcache_wbinv_all(pm);
4259 * pmap_copy_page copies the specified (machine independent)
4260 * page by mapping the page into virtual memory and using
4261 * bcopy to copy the page, one machine dependent page at a
4268 * Copy one physical page into another, by mapping the pages into
4269 * hook points. The same comment regarding cachability as in
4270 * pmap_zero_page also applies here.
4272 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined (CPU_XSCALE_CORE3)
4274 pmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst)
4277 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4281 * Clean the source page. Hold the source page's lock for
4282 * the duration of the copy so that no other mappings can
4283 * be created while we have a potentially aliased mapping.
4287 * XXX: Not needed while we call cpu_dcache_wbinv_all() in
4290 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4293 * Map the pages into the page hook points, copy them, and purge
4294 * the cache for the appropriate page. Invalidate the TLB
4298 *csrc_pte = L2_S_PROTO | src |
4299 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
4301 *cdst_pte = L2_S_PROTO | dst |
4302 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
4304 cpu_tlb_flushD_SE(csrcp);
4305 cpu_tlb_flushD_SE(cdstp);
4307 bcopy_page(csrcp, cdstp);
4309 cpu_dcache_inv_range(csrcp, PAGE_SIZE);
4310 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE);
4311 cpu_l2cache_inv_range(csrcp, PAGE_SIZE);
4312 cpu_l2cache_wbinv_range(cdstp, PAGE_SIZE);
4316 pmap_copy_page_offs_generic(vm_paddr_t a_phys, vm_offset_t a_offs,
4317 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt)
4321 *csrc_pte = L2_S_PROTO | a_phys |
4322 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
4324 *cdst_pte = L2_S_PROTO | b_phys |
4325 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
4327 cpu_tlb_flushD_SE(csrcp);
4328 cpu_tlb_flushD_SE(cdstp);
4330 bcopy((char *)csrcp + a_offs, (char *)cdstp + b_offs, cnt);
4332 cpu_dcache_inv_range(csrcp + a_offs, cnt);
4333 cpu_dcache_wbinv_range(cdstp + b_offs, cnt);
4334 cpu_l2cache_inv_range(csrcp + a_offs, cnt);
4335 cpu_l2cache_wbinv_range(cdstp + b_offs, cnt);
4337 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
4339 #if ARM_MMU_XSCALE == 1
4341 pmap_copy_page_xscale(vm_paddr_t src, vm_paddr_t dst)
4344 /* XXX: Only needed for pmap_clean_page(), which is commented out. */
4345 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4349 * Clean the source page. Hold the source page's lock for
4350 * the duration of the copy so that no other mappings can
4351 * be created while we have a potentially aliased mapping.
4355 * XXX: Not needed while we call cpu_dcache_wbinv_all() in
4358 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4361 * Map the pages into the page hook points, copy them, and purge
4362 * the cache for the appropriate page. Invalidate the TLB
4366 *csrc_pte = L2_S_PROTO | src |
4367 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
4368 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4370 *cdst_pte = L2_S_PROTO | dst |
4371 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4372 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4374 cpu_tlb_flushD_SE(csrcp);
4375 cpu_tlb_flushD_SE(cdstp);
4377 bcopy_page(csrcp, cdstp);
4379 xscale_cache_clean_minidata();
4383 pmap_copy_page_offs_xscale(vm_paddr_t a_phys, vm_offset_t a_offs,
4384 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt)
4388 *csrc_pte = L2_S_PROTO | a_phys |
4389 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
4390 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X);
4392 *cdst_pte = L2_S_PROTO | b_phys |
4393 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4394 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X);
4396 cpu_tlb_flushD_SE(csrcp);
4397 cpu_tlb_flushD_SE(cdstp);
4399 bcopy((char *)csrcp + a_offs, (char *)cdstp + b_offs, cnt);
4401 xscale_cache_clean_minidata();
4403 #endif /* ARM_MMU_XSCALE == 1 */
4406 pmap_copy_page(vm_page_t src, vm_page_t dst)
4408 #ifdef ARM_USE_SMALL_ALLOC
4409 vm_offset_t srcpg, dstpg;
4412 cpu_dcache_wbinv_all();
4413 cpu_l2cache_wbinv_all();
4414 if (_arm_memcpy && PAGE_SIZE >= _min_memcpy_size &&
4415 _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst),
4416 (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0)
4418 #ifdef ARM_USE_SMALL_ALLOC
4419 srcpg = arm_ptovirt(VM_PAGE_TO_PHYS(src));
4420 dstpg = arm_ptovirt(VM_PAGE_TO_PHYS(dst));
4421 bcopy_page(srcpg, dstpg);
4422 cpu_dcache_wbinv_range(dstpg, PAGE_SIZE);
4423 cpu_l2cache_wbinv_range(dstpg, PAGE_SIZE);
4425 pmap_copy_page_func(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst));
4429 int unmapped_buf_allowed = 1;
4432 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4433 vm_offset_t b_offset, int xfersize)
4435 vm_page_t a_pg, b_pg;
4436 vm_offset_t a_pg_offset, b_pg_offset;
4438 #ifdef ARM_USE_SMALL_ALLOC
4439 vm_offset_t a_va, b_va;
4442 cpu_dcache_wbinv_all();
4443 cpu_l2cache_wbinv_all();
4444 while (xfersize > 0) {
4445 a_pg = ma[a_offset >> PAGE_SHIFT];
4446 a_pg_offset = a_offset & PAGE_MASK;
4447 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4448 b_pg = mb[b_offset >> PAGE_SHIFT];
4449 b_pg_offset = b_offset & PAGE_MASK;
4450 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4451 #ifdef ARM_USE_SMALL_ALLOC
4452 a_va = arm_ptovirt(VM_PAGE_TO_PHYS(a_pg)) + a_pg_offset;
4453 b_va = arm_ptovirt(VM_PAGE_TO_PHYS(b_pg)) + b_pg_offset;
4454 bcopy((char *)a_va, (char *)b_va, cnt);
4455 cpu_dcache_wbinv_range(b_va, cnt);
4456 cpu_l2cache_wbinv_range(b_va, cnt);
4458 pmap_copy_page_offs_func(VM_PAGE_TO_PHYS(a_pg), a_pg_offset,
4459 VM_PAGE_TO_PHYS(b_pg), b_pg_offset, cnt);
4468 * this routine returns true if a physical page resides
4469 * in the given pmap.
4472 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4478 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4479 ("pmap_page_exists_quick: page %p is not managed", m));
4481 rw_wlock(&pvh_global_lock);
4482 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4483 if (pv->pv_pmap == pmap) {
4491 rw_wunlock(&pvh_global_lock);
4496 * pmap_page_wired_mappings:
4498 * Return the number of managed mappings to the given physical page
4502 pmap_page_wired_mappings(vm_page_t m)
4508 if ((m->oflags & VPO_UNMANAGED) != 0)
4510 rw_wlock(&pvh_global_lock);
4511 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
4512 if ((pv->pv_flags & PVF_WIRED) != 0)
4514 rw_wunlock(&pvh_global_lock);
4519 * This function is advisory.
4522 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4527 * pmap_ts_referenced:
4529 * Return the count of reference bits for a page, clearing all of them.
4532 pmap_ts_referenced(vm_page_t m)
4535 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4536 ("pmap_ts_referenced: page %p is not managed", m));
4537 return (pmap_clearbit(m, PVF_REF));
4542 pmap_is_modified(vm_page_t m)
4545 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4546 ("pmap_is_modified: page %p is not managed", m));
4547 if (m->md.pvh_attrs & PVF_MOD)
4555 * Clear the modify bits on the specified physical page.
4558 pmap_clear_modify(vm_page_t m)
4561 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4562 ("pmap_clear_modify: page %p is not managed", m));
4563 VM_OBJECT_ASSERT_WLOCKED(m->object);
4564 KASSERT(!vm_page_xbusied(m),
4565 ("pmap_clear_modify: page %p is exclusive busied", m));
4568 * If the page is not PGA_WRITEABLE, then no mappings can be modified.
4569 * If the object containing the page is locked and the page is not
4570 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
4572 if ((m->aflags & PGA_WRITEABLE) == 0)
4574 if (m->md.pvh_attrs & PVF_MOD)
4575 pmap_clearbit(m, PVF_MOD);
4580 * pmap_is_referenced:
4582 * Return whether or not the specified physical page was referenced
4583 * in any physical maps.
4586 pmap_is_referenced(vm_page_t m)
4589 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4590 ("pmap_is_referenced: page %p is not managed", m));
4591 return ((m->md.pvh_attrs & PVF_REF) != 0);
4596 * Clear the write and modified bits in each of the given page's mappings.
4599 pmap_remove_write(vm_page_t m)
4602 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4603 ("pmap_remove_write: page %p is not managed", m));
4606 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4607 * set by another thread while the object is locked. Thus,
4608 * if PGA_WRITEABLE is clear, no page table entries need updating.
4610 VM_OBJECT_ASSERT_WLOCKED(m->object);
4611 if (vm_page_xbusied(m) || (m->aflags & PGA_WRITEABLE) != 0)
4612 pmap_clearbit(m, PVF_WRITE);
4617 * perform the pmap work for mincore
4620 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
4622 struct l2_bucket *l2b;
4623 pt_entry_t *ptep, pte;
4631 l2b = pmap_get_l2_bucket(pmap, addr);
4636 ptep = &l2b->l2b_kva[l2pte_index(addr)];
4638 if (!l2pte_valid(pte)) {
4642 val = MINCORE_INCORE;
4643 if (pte & L2_S_PROT_W)
4644 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4647 m = PHYS_TO_VM_PAGE(pa);
4648 if (m != NULL && !(m->oflags & VPO_UNMANAGED))
4652 * The ARM pmap tries to maintain a per-mapping
4653 * reference bit. The trouble is that it's kept in
4654 * the PV entry, not the PTE, so it's costly to access
4655 * here. You would need to acquire the pvh global
4656 * lock, call pmap_find_pv(), and introduce a custom
4657 * version of vm_page_pa_tryrelock() that releases and
4658 * reacquires the pvh global lock. In the end, I
4659 * doubt it's worthwhile. This may falsely report
4660 * the given address as referenced.
4662 if ((m->md.pvh_attrs & PVF_REF) != 0)
4663 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4665 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
4666 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
4667 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
4668 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
4672 PA_UNLOCK_COND(*locked_pa);
4679 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
4685 * Increase the starting virtual address of the given mapping if a
4686 * different alignment might result in more superpage mappings.
4689 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
4690 vm_offset_t *addr, vm_size_t size)
4696 * Map a set of physical memory pages into the kernel virtual
4697 * address space. Return a pointer to where it is mapped. This
4698 * routine is intended to be used for mapping device memory,
4702 pmap_mapdev(vm_offset_t pa, vm_size_t size)
4704 vm_offset_t va, tmpva, offset;
4706 offset = pa & PAGE_MASK;
4707 size = roundup(size, PAGE_SIZE);
4711 va = kva_alloc(size);
4713 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
4714 for (tmpva = va; size > 0;) {
4715 pmap_kenter_internal(tmpva, pa, 0);
4721 return ((void *)(va + offset));
4724 #define BOOTSTRAP_DEBUG
4729 * Create a single section mapping.
4732 pmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4733 int prot, int cache)
4735 pd_entry_t *pde = (pd_entry_t *) l1pt;
4738 KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2"));
4747 fl = pte_l1_s_cache_mode;
4751 fl = pte_l1_s_cache_mode_pt;
4755 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4756 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL);
4757 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4764 * Link the L2 page table specified by l2pv.pv_pa into the L1
4765 * page table at the slot for "va".
4768 pmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv)
4770 pd_entry_t *pde = (pd_entry_t *) l1pt, proto;
4771 u_int slot = va >> L1_S_SHIFT;
4773 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO;
4775 #ifdef VERBOSE_INIT_ARM
4776 printf("pmap_link_l2pt: pa=0x%x va=0x%x\n", l2pv->pv_pa, l2pv->pv_va);
4779 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000);
4781 PTE_SYNC(&pde[slot]);
4783 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list);
4791 * Create a single page mapping.
4794 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot,
4797 pd_entry_t *pde = (pd_entry_t *) l1pt;
4801 KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin"));
4810 fl = pte_l2_s_cache_mode;
4814 fl = pte_l2_s_cache_mode_pt;
4818 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4819 panic("pmap_map_entry: no L2 table for VA 0x%08x", va);
4821 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4824 panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va);
4826 pte[l2pte_index(va)] =
4827 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl;
4828 PTE_SYNC(&pte[l2pte_index(va)]);
4834 * Map a chunk of memory using the most efficient mappings
4835 * possible (section. large page, small page) into the
4836 * provided L1 and L2 tables at the specified virtual address.
4839 pmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4840 vm_size_t size, int prot, int cache)
4842 pd_entry_t *pde = (pd_entry_t *) l1pt;
4843 pt_entry_t *pte, f1, f2s, f2l;
4847 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
4850 panic("pmap_map_chunk: no L1 table provided");
4852 #ifdef VERBOSE_INIT_ARM
4853 printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x "
4854 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache);
4866 f1 = pte_l1_s_cache_mode;
4867 f2l = pte_l2_l_cache_mode;
4868 f2s = pte_l2_s_cache_mode;
4872 f1 = pte_l1_s_cache_mode_pt;
4873 f2l = pte_l2_l_cache_mode_pt;
4874 f2s = pte_l2_s_cache_mode_pt;
4881 /* See if we can use a section mapping. */
4882 if (L1_S_MAPPABLE_P(va, pa, resid)) {
4883 #ifdef VERBOSE_INIT_ARM
4886 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4887 L1_S_PROT(PTE_KERNEL, prot) | f1 |
4888 L1_S_DOM(PMAP_DOMAIN_KERNEL);
4889 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4897 * Ok, we're going to use an L2 table. Make sure
4898 * one is actually in the corresponding L1 slot
4899 * for the current VA.
4901 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4902 panic("pmap_map_chunk: no L2 table for VA 0x%08x", va);
4904 pte = (pt_entry_t *) kernel_pt_lookup(
4905 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4907 panic("pmap_map_chunk: can't find L2 table for VA"
4909 /* See if we can use a L2 large page mapping. */
4910 if (L2_L_MAPPABLE_P(va, pa, resid)) {
4911 #ifdef VERBOSE_INIT_ARM
4914 for (i = 0; i < 16; i++) {
4915 pte[l2pte_index(va) + i] =
4917 L2_L_PROT(PTE_KERNEL, prot) | f2l;
4918 PTE_SYNC(&pte[l2pte_index(va) + i]);
4926 /* Use a small page mapping. */
4927 #ifdef VERBOSE_INIT_ARM
4930 pte[l2pte_index(va)] =
4931 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s;
4932 PTE_SYNC(&pte[l2pte_index(va)]);
4937 #ifdef VERBOSE_INIT_ARM
4944 /********************** Static device map routines ***************************/
4946 static const struct pmap_devmap *pmap_devmap_table;
4949 * Register the devmap table. This is provided in case early console
4950 * initialization needs to register mappings created by bootstrap code
4951 * before pmap_devmap_bootstrap() is called.
4954 pmap_devmap_register(const struct pmap_devmap *table)
4957 pmap_devmap_table = table;
4961 * Map all of the static regions in the devmap table, and remember
4962 * the devmap table so other parts of the kernel can look up entries
4966 pmap_devmap_bootstrap(vm_offset_t l1pt, const struct pmap_devmap *table)
4970 pmap_devmap_table = table;
4972 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
4973 #ifdef VERBOSE_INIT_ARM
4974 printf("devmap: %08x -> %08x @ %08x\n",
4975 pmap_devmap_table[i].pd_pa,
4976 pmap_devmap_table[i].pd_pa +
4977 pmap_devmap_table[i].pd_size - 1,
4978 pmap_devmap_table[i].pd_va);
4980 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va,
4981 pmap_devmap_table[i].pd_pa,
4982 pmap_devmap_table[i].pd_size,
4983 pmap_devmap_table[i].pd_prot,
4984 pmap_devmap_table[i].pd_cache);
4988 const struct pmap_devmap *
4989 pmap_devmap_find_pa(vm_paddr_t pa, vm_size_t size)
4993 if (pmap_devmap_table == NULL)
4996 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
4997 if (pa >= pmap_devmap_table[i].pd_pa &&
4998 pa + size <= pmap_devmap_table[i].pd_pa +
4999 pmap_devmap_table[i].pd_size)
5000 return (&pmap_devmap_table[i]);
5006 const struct pmap_devmap *
5007 pmap_devmap_find_va(vm_offset_t va, vm_size_t size)
5011 if (pmap_devmap_table == NULL)
5014 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
5015 if (va >= pmap_devmap_table[i].pd_va &&
5016 va + size <= pmap_devmap_table[i].pd_va +
5017 pmap_devmap_table[i].pd_size)
5018 return (&pmap_devmap_table[i]);
5025 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5028 * Remember the memattr in a field that gets used to set the appropriate
5029 * bits in the PTEs as mappings are established.
5031 m->md.pv_memattr = ma;
5034 * It appears that this function can only be called before any mappings
5035 * for the page are established on ARM. If this ever changes, this code
5036 * will need to walk the pv_list and make each of the existing mappings
5037 * uncacheable, being careful to sync caches and PTEs (and maybe
5038 * invalidate TLB?) for any current mapping it modifies.
5040 if (m->md.pv_kva != 0 || TAILQ_FIRST(&m->md.pv_list) != NULL)
5041 panic("Can't change memattr on page with existing mappings");