1 /* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */
3 * Copyright 2004 Olivier Houchard.
4 * Copyright 2003 Wasabi Systems, Inc.
7 * Written by Steve C. Woodford for Wasabi Systems, Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
39 * Copyright (c) 2002-2003 Wasabi Systems, Inc.
40 * Copyright (c) 2001 Richard Earnshaw
41 * Copyright (c) 2001-2002 Christopher Gilbert
42 * All rights reserved.
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. The name of the company nor the name of the author may be used to
50 * endorse or promote products derived from this software without specific
51 * prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
66 * Copyright (c) 1999 The NetBSD Foundation, Inc.
67 * All rights reserved.
69 * This code is derived from software contributed to The NetBSD Foundation
70 * by Charles M. Hannum.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
80 * 3. All advertising materials mentioning features or use of this software
81 * must display the following acknowledgement:
82 * This product includes software developed by the NetBSD
83 * Foundation, Inc. and its contributors.
84 * 4. Neither the name of The NetBSD Foundation nor the names of its
85 * contributors may be used to endorse or promote products derived
86 * from this software without specific prior written permission.
88 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
89 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
90 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
91 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
92 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
93 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
94 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
95 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
96 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
97 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
98 * POSSIBILITY OF SUCH DAMAGE.
102 * Copyright (c) 1994-1998 Mark Brinicombe.
103 * Copyright (c) 1994 Brini.
104 * All rights reserved.
106 * This code is derived from software written for Brini by Mark Brinicombe
108 * Redistribution and use in source and binary forms, with or without
109 * modification, are permitted provided that the following conditions
111 * 1. Redistributions of source code must retain the above copyright
112 * notice, this list of conditions and the following disclaimer.
113 * 2. Redistributions in binary form must reproduce the above copyright
114 * notice, this list of conditions and the following disclaimer in the
115 * documentation and/or other materials provided with the distribution.
116 * 3. All advertising materials mentioning features or use of this software
117 * must display the following acknowledgement:
118 * This product includes software developed by Mark Brinicombe.
119 * 4. The name of the author may not be used to endorse or promote products
120 * derived from this software without specific prior written permission.
122 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
123 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
124 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
125 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
126 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
127 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
128 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
129 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
130 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
132 * RiscBSD kernel project
136 * Machine dependant vm stuff
142 * Special compilation symbols
143 * PMAP_DEBUG - Build in pmap_debug_level code
145 /* Include header files */
149 #include <sys/cdefs.h>
150 __FBSDID("$FreeBSD$");
151 #include <sys/param.h>
152 #include <sys/systm.h>
153 #include <sys/kernel.h>
154 #include <sys/proc.h>
155 #include <sys/malloc.h>
156 #include <sys/msgbuf.h>
157 #include <sys/vmmeter.h>
158 #include <sys/mman.h>
161 #include <sys/sched.h>
166 #include <vm/vm_kern.h>
167 #include <vm/vm_object.h>
168 #include <vm/vm_map.h>
169 #include <vm/vm_page.h>
170 #include <vm/vm_pageout.h>
171 #include <vm/vm_extern.h>
172 #include <sys/lock.h>
173 #include <sys/mutex.h>
174 #include <machine/md_var.h>
175 #include <machine/vmparam.h>
176 #include <machine/cpu.h>
177 #include <machine/cpufunc.h>
178 #include <machine/pcb.h>
181 #define PDEBUG(_lev_,_stat_) \
182 if (pmap_debug_level >= (_lev_)) \
184 #define dprintf printf
186 int pmap_debug_level = 0;
188 #else /* PMAP_DEBUG */
189 #define PDEBUG(_lev_,_stat_) /* Nothing */
190 #define dprintf(x, arg...)
191 #define PMAP_INLINE __inline
192 #endif /* PMAP_DEBUG */
194 extern struct pv_addr systempage;
196 * Internal function prototypes
198 static void pmap_free_pv_entry (pv_entry_t);
199 static pv_entry_t pmap_get_pv_entry(void);
201 static void pmap_enter_locked(pmap_t, vm_offset_t, vm_page_t,
202 vm_prot_t, boolean_t);
203 static void pmap_vac_me_harder(struct vm_page *, pmap_t,
205 static void pmap_vac_me_kpmap(struct vm_page *, pmap_t,
207 static void pmap_vac_me_user(struct vm_page *, pmap_t, vm_offset_t);
208 static void pmap_alloc_l1(pmap_t);
209 static void pmap_free_l1(pmap_t);
210 static void pmap_use_l1(pmap_t);
212 static int pmap_clearbit(struct vm_page *, u_int);
214 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t);
215 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t);
216 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int);
217 static vm_offset_t kernel_pt_lookup(vm_paddr_t);
219 static MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1");
221 vm_offset_t avail_end; /* PA of last available physical page */
222 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
223 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
224 vm_offset_t pmap_curmaxkvaddr;
225 vm_paddr_t kernel_l1pa;
228 vm_offset_t kernel_vm_end = 0;
230 struct pmap kernel_pmap_store;
233 static pt_entry_t *csrc_pte, *cdst_pte;
234 static vm_offset_t csrcp, cdstp;
235 static struct mtx cmtx;
237 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *);
239 * These routines are called when the CPU type is identified to set up
240 * the PTE prototypes, cache modes, etc.
242 * The variables are always here, just in case LKMs need to reference
243 * them (though, they shouldn't).
246 pt_entry_t pte_l1_s_cache_mode;
247 pt_entry_t pte_l1_s_cache_mode_pt;
248 pt_entry_t pte_l1_s_cache_mask;
250 pt_entry_t pte_l2_l_cache_mode;
251 pt_entry_t pte_l2_l_cache_mode_pt;
252 pt_entry_t pte_l2_l_cache_mask;
254 pt_entry_t pte_l2_s_cache_mode;
255 pt_entry_t pte_l2_s_cache_mode_pt;
256 pt_entry_t pte_l2_s_cache_mask;
258 pt_entry_t pte_l2_s_prot_u;
259 pt_entry_t pte_l2_s_prot_w;
260 pt_entry_t pte_l2_s_prot_mask;
262 pt_entry_t pte_l1_s_proto;
263 pt_entry_t pte_l1_c_proto;
264 pt_entry_t pte_l2_s_proto;
266 void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t);
267 void (*pmap_zero_page_func)(vm_paddr_t, int, int);
269 * Which pmap is currently 'live' in the cache
271 * XXXSCW: Fix for SMP ...
273 union pmap_cache_state *pmap_cache_state;
275 /* static pt_entry_t *msgbufmap;*/
276 struct msgbuf *msgbufp = 0;
278 extern void bcopy_page(vm_offset_t, vm_offset_t);
279 extern void bzero_page(vm_offset_t);
284 * Metadata for L1 translation tables.
287 /* Entry on the L1 Table list */
288 SLIST_ENTRY(l1_ttable) l1_link;
290 /* Entry on the L1 Least Recently Used list */
291 TAILQ_ENTRY(l1_ttable) l1_lru;
293 /* Track how many domains are allocated from this L1 */
294 volatile u_int l1_domain_use_count;
297 * A free-list of domain numbers for this L1.
298 * We avoid using ffs() and a bitmap to track domains since ffs()
301 u_int8_t l1_domain_first;
302 u_int8_t l1_domain_free[PMAP_DOMAINS];
304 /* Physical address of this L1 page table */
305 vm_paddr_t l1_physaddr;
307 /* KVA of this L1 page table */
312 * Convert a virtual address into its L1 table index. That is, the
313 * index used to locate the L2 descriptor table pointer in an L1 table.
314 * This is basically used to index l1->l1_kva[].
316 * Each L2 descriptor table represents 1MB of VA space.
318 #define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT)
321 * L1 Page Tables are tracked using a Least Recently Used list.
322 * - New L1s are allocated from the HEAD.
323 * - Freed L1s are added to the TAIl.
324 * - Recently accessed L1s (where an 'access' is some change to one of
325 * the userland pmaps which owns this L1) are moved to the TAIL.
327 static TAILQ_HEAD(, l1_ttable) l1_lru_list;
329 * A list of all L1 tables
331 static SLIST_HEAD(, l1_ttable) l1_list;
332 static struct mtx l1_lru_lock;
335 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots.
337 * This is normally 16MB worth L2 page descriptors for any given pmap.
338 * Reference counts are maintained for L2 descriptors so they can be
342 /* The number of L2 page descriptors allocated to this l2_dtable */
345 /* List of L2 page descriptors */
347 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */
348 vm_paddr_t l2b_phys; /* Physical address of same */
349 u_short l2b_l1idx; /* This L2 table's L1 index */
350 u_short l2b_occupancy; /* How many active descriptors */
351 } l2_bucket[L2_BUCKET_SIZE];
354 /* pmap_kenter_internal flags */
355 #define KENTER_CACHE 0x1
356 #define KENTER_USER 0x2
359 * Given an L1 table index, calculate the corresponding l2_dtable index
360 * and bucket index within the l2_dtable.
362 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \
364 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1))
367 * Given a virtual address, this macro returns the
368 * virtual address required to drop into the next L2 bucket.
370 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE)
375 #define pmap_alloc_l2_dtable() \
376 (void*)uma_zalloc(l2table_zone, M_NOWAIT)
377 #define pmap_free_l2_dtable(l2) \
378 uma_zfree(l2table_zone, l2)
381 * We try to map the page tables write-through, if possible. However, not
382 * all CPUs have a write-through cache mode, so on those we have to sync
383 * the cache when we frob page tables.
385 * We try to evaluate this at compile time, if possible. However, it's
386 * not always possible to do that, hence this run-time var.
388 int pmap_needs_pte_sync;
391 * Macro to determine if a mapping might be resident in the
392 * instruction cache and/or TLB
394 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC))
397 * Macro to determine if a mapping might be resident in the
398 * data cache and/or TLB
400 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0)
402 #ifndef PMAP_SHPGPERPROC
403 #define PMAP_SHPGPERPROC 200
406 #define pmap_is_current(pm) ((pm) == pmap_kernel() || \
407 curproc->p_vmspace->vm_map.pmap == (pm))
408 static uma_zone_t pvzone;
410 static uma_zone_t l2table_zone;
411 static vm_offset_t pmap_kernel_l2dtable_kva;
412 static vm_offset_t pmap_kernel_l2ptp_kva;
413 static vm_paddr_t pmap_kernel_l2ptp_phys;
414 static struct vm_object pvzone_obj;
415 static struct vm_object l2zone_obj;
416 static int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0;
417 int pmap_pagedaemon_waken = 0;
420 * This list exists for the benefit of pmap_map_chunk(). It keeps track
421 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can
422 * find them as necessary.
424 * Note that the data on this list MUST remain valid after initarm() returns,
425 * as pmap_bootstrap() uses it to contruct L2 table metadata.
427 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list);
430 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt)
435 l1->l1_domain_use_count = 0;
436 l1->l1_domain_first = 0;
438 for (i = 0; i < PMAP_DOMAINS; i++)
439 l1->l1_domain_free[i] = i + 1;
442 * Copy the kernel's L1 entries to each new L1.
444 if (l1pt != pmap_kernel()->pm_l1->l1_kva)
445 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE);
447 if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0)
448 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt);
449 SLIST_INSERT_HEAD(&l1_list, l1, l1_link);
450 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
454 kernel_pt_lookup(vm_paddr_t pa)
458 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) {
459 #ifndef ARM32_NEW_VM_LAYOUT
460 if (pv->pv_pa == (pa & ~PAGE_MASK)) {
461 return (pv->pv_va | (pa & PAGE_MASK));
471 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
473 pmap_pte_init_generic(void)
476 pte_l1_s_cache_mode = L1_S_B|L1_S_C;
477 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic;
479 pte_l2_l_cache_mode = L2_B|L2_C;
480 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic;
482 pte_l2_s_cache_mode = L2_B|L2_C;
483 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic;
486 * If we have a write-through cache, set B and C. If
487 * we have a write-back cache, then we assume setting
488 * only C will make those pages write-through.
490 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) {
491 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
492 pte_l2_l_cache_mode_pt = L2_B|L2_C;
493 pte_l2_s_cache_mode_pt = L2_B|L2_C;
495 pte_l1_s_cache_mode_pt = L1_S_C;
496 pte_l2_l_cache_mode_pt = L2_C;
497 pte_l2_s_cache_mode_pt = L2_C;
500 pte_l2_s_prot_u = L2_S_PROT_U_generic;
501 pte_l2_s_prot_w = L2_S_PROT_W_generic;
502 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic;
504 pte_l1_s_proto = L1_S_PROTO_generic;
505 pte_l1_c_proto = L1_C_PROTO_generic;
506 pte_l2_s_proto = L2_S_PROTO_generic;
508 pmap_copy_page_func = pmap_copy_page_generic;
509 pmap_zero_page_func = pmap_zero_page_generic;
512 #if defined(CPU_ARM8)
514 pmap_pte_init_arm8(void)
518 * ARM8 is compatible with generic, but we need to use
519 * the page tables uncached.
521 pmap_pte_init_generic();
523 pte_l1_s_cache_mode_pt = 0;
524 pte_l2_l_cache_mode_pt = 0;
525 pte_l2_s_cache_mode_pt = 0;
527 #endif /* CPU_ARM8 */
529 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH)
531 pmap_pte_init_arm9(void)
535 * ARM9 is compatible with generic, but we want to use
536 * write-through caching for now.
538 pmap_pte_init_generic();
540 pte_l1_s_cache_mode = L1_S_C;
541 pte_l2_l_cache_mode = L2_C;
542 pte_l2_s_cache_mode = L2_C;
544 pte_l1_s_cache_mode_pt = L1_S_C;
545 pte_l2_l_cache_mode_pt = L2_C;
546 pte_l2_s_cache_mode_pt = L2_C;
548 #endif /* CPU_ARM9 */
549 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
551 #if defined(CPU_ARM10)
553 pmap_pte_init_arm10(void)
557 * ARM10 is compatible with generic, but we want to use
558 * write-through caching for now.
560 pmap_pte_init_generic();
562 pte_l1_s_cache_mode = L1_S_B | L1_S_C;
563 pte_l2_l_cache_mode = L2_B | L2_C;
564 pte_l2_s_cache_mode = L2_B | L2_C;
566 pte_l1_s_cache_mode_pt = L1_S_C;
567 pte_l2_l_cache_mode_pt = L2_C;
568 pte_l2_s_cache_mode_pt = L2_C;
571 #endif /* CPU_ARM10 */
575 pmap_pte_init_sa1(void)
579 * The StrongARM SA-1 cache does not have a write-through
580 * mode. So, do the generic initialization, then reset
581 * the page table cache mode to B=1,C=1, and note that
582 * the PTEs need to be sync'd.
584 pmap_pte_init_generic();
586 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
587 pte_l2_l_cache_mode_pt = L2_B|L2_C;
588 pte_l2_s_cache_mode_pt = L2_B|L2_C;
590 pmap_needs_pte_sync = 1;
592 #endif /* ARM_MMU_SA1 == 1*/
594 #if ARM_MMU_XSCALE == 1
596 static u_int xscale_use_minidata;
600 pmap_pte_init_xscale(void)
603 int write_through = 0;
605 pte_l1_s_cache_mode = L1_S_B|L1_S_C|L1_S_XSCALE_P;
606 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale;
608 pte_l2_l_cache_mode = L2_B|L2_C;
609 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale;
611 pte_l2_s_cache_mode = L2_B|L2_C;
612 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale;
614 pte_l1_s_cache_mode_pt = L1_S_C;
615 pte_l2_l_cache_mode_pt = L2_C;
616 pte_l2_s_cache_mode_pt = L2_C;
617 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE
619 * The XScale core has an enhanced mode where writes that
620 * miss the cache cause a cache line to be allocated. This
621 * is significantly faster than the traditional, write-through
622 * behavior of this case.
624 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X);
625 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X);
626 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X);
627 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */
628 #ifdef XSCALE_CACHE_WRITE_THROUGH
630 * Some versions of the XScale core have various bugs in
631 * their cache units, the work-around for which is to run
632 * the cache in write-through mode. Unfortunately, this
633 * has a major (negative) impact on performance. So, we
634 * go ahead and run fast-and-loose, in the hopes that we
635 * don't line up the planets in a way that will trip the
638 * However, we give you the option to be slow-but-correct.
641 #elif defined(XSCALE_CACHE_WRITE_BACK)
642 /* force write back cache mode */
644 #elif defined(CPU_XSCALE_PXA2X0)
646 * Intel PXA2[15]0 processors are known to have a bug in
647 * write-back cache on revision 4 and earlier (stepping
648 * A[01] and B[012]). Fixed for C0 and later.
654 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK);
656 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) {
657 if ((id & CPU_ID_REVISION_MASK) < 5) {
658 /* write through for stepping A0-1 and B0-2 */
663 #endif /* XSCALE_CACHE_WRITE_THROUGH */
666 pte_l1_s_cache_mode = L1_S_C;
667 pte_l2_l_cache_mode = L2_C;
668 pte_l2_s_cache_mode = L2_C;
672 xscale_use_minidata = 1;
675 pte_l2_s_prot_u = L2_S_PROT_U_xscale;
676 pte_l2_s_prot_w = L2_S_PROT_W_xscale;
677 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale;
679 pte_l1_s_proto = L1_S_PROTO_xscale;
680 pte_l1_c_proto = L1_C_PROTO_xscale;
681 pte_l2_s_proto = L2_S_PROTO_xscale;
683 pmap_copy_page_func = pmap_copy_page_xscale;
684 pmap_zero_page_func = pmap_zero_page_xscale;
687 * Disable ECC protection of page table access, for now.
689 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
690 auxctl &= ~XSCALE_AUXCTL_P;
691 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
695 * xscale_setup_minidata:
697 * Set up the mini-data cache clean area. We require the
698 * caller to allocate the right amount of physically and
699 * virtually contiguous space.
701 extern vm_offset_t xscale_minidata_clean_addr;
702 extern vm_size_t xscale_minidata_clean_size; /* already initialized */
704 xscale_setup_minidata(vm_offset_t l1pt, vm_offset_t va, vm_paddr_t pa)
706 pd_entry_t *pde = (pd_entry_t *) l1pt;
711 xscale_minidata_clean_addr = va;
713 /* Round it to page size. */
714 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME;
717 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) {
718 #ifndef ARM32_NEW_VM_LAYOUT
720 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME);
722 pte = (pt_entry_t *) kernel_pt_lookup(
723 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
726 panic("xscale_setup_minidata: can't find L2 table for "
727 "VA 0x%08x", (u_int32_t) va);
728 #ifndef ARM32_NEW_VM_LAYOUT
729 pte[(va >> PAGE_SHIFT) & 0x3ff] =
731 pte[l2pte_index(va)] =
733 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
734 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X);
738 * Configure the mini-data cache for write-back with
739 * read/write-allocate.
741 * NOTE: In order to reconfigure the mini-data cache, we must
742 * make sure it contains no valid data! In order to do that,
743 * we must issue a global data cache invalidate command!
745 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED!
746 * THIS IS VERY IMPORTANT!
749 /* Invalidate data and mini-data. */
750 __asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
751 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
752 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA;
753 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
758 * Allocate an L1 translation table for the specified pmap.
759 * This is called at pmap creation time.
762 pmap_alloc_l1(pmap_t pm)
764 struct l1_ttable *l1;
768 * Remove the L1 at the head of the LRU list
770 mtx_lock(&l1_lru_lock);
771 l1 = TAILQ_FIRST(&l1_lru_list);
772 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
775 * Pick the first available domain number, and update
776 * the link to the next number.
778 domain = l1->l1_domain_first;
779 l1->l1_domain_first = l1->l1_domain_free[domain];
782 * If there are still free domain numbers in this L1,
783 * put it back on the TAIL of the LRU list.
785 if (++l1->l1_domain_use_count < PMAP_DOMAINS)
786 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
788 mtx_unlock(&l1_lru_lock);
791 * Fix up the relevant bits in the pmap structure
794 pm->pm_domain = domain;
798 * Free an L1 translation table.
799 * This is called at pmap destruction time.
802 pmap_free_l1(pmap_t pm)
804 struct l1_ttable *l1 = pm->pm_l1;
806 mtx_lock(&l1_lru_lock);
809 * If this L1 is currently on the LRU list, remove it.
811 if (l1->l1_domain_use_count < PMAP_DOMAINS)
812 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
815 * Free up the domain number which was allocated to the pmap
817 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first;
818 l1->l1_domain_first = pm->pm_domain;
819 l1->l1_domain_use_count--;
822 * The L1 now must have at least 1 free domain, so add
823 * it back to the LRU list. If the use count is zero,
824 * put it at the head of the list, otherwise it goes
827 if (l1->l1_domain_use_count == 0) {
828 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru);
830 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
832 mtx_unlock(&l1_lru_lock);
835 static PMAP_INLINE void
836 pmap_use_l1(pmap_t pm)
838 struct l1_ttable *l1;
841 * Do nothing if we're in interrupt context.
842 * Access to an L1 by the kernel pmap must not affect
845 if (pm == pmap_kernel())
851 * If the L1 is not currently on the LRU list, just return
853 if (l1->l1_domain_use_count == PMAP_DOMAINS)
856 mtx_lock(&l1_lru_lock);
859 * Check the use count again, now that we've acquired the lock
861 if (l1->l1_domain_use_count == PMAP_DOMAINS) {
862 mtx_unlock(&l1_lru_lock);
867 * Move the L1 to the back of the LRU list
869 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
870 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
872 mtx_unlock(&l1_lru_lock);
877 * Returns a pointer to the L2 bucket associated with the specified pmap
878 * and VA, or NULL if no L2 bucket exists for the address.
880 static PMAP_INLINE struct l2_bucket *
881 pmap_get_l2_bucket(pmap_t pm, vm_offset_t va)
883 struct l2_dtable *l2;
884 struct l2_bucket *l2b;
889 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL ||
890 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL)
897 * Returns a pointer to the L2 bucket associated with the specified pmap
900 * If no L2 bucket exists, perform the necessary allocations to put an L2
901 * bucket/page table in place.
903 * Note that if a new L2 bucket/page was allocated, the caller *must*
904 * increment the bucket occupancy counter appropriately *before*
905 * releasing the pmap's lock to ensure no other thread or cpu deallocates
906 * the bucket/page in the meantime.
908 static struct l2_bucket *
909 pmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va)
911 struct l2_dtable *l2;
912 struct l2_bucket *l2b;
917 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
918 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
920 * No mapping at this address, as there is
921 * no entry in the L1 table.
922 * Need to allocate a new l2_dtable.
925 vm_page_unlock_queues();
926 if ((l2 = pmap_alloc_l2_dtable()) == NULL) {
927 vm_page_lock_queues();
930 vm_page_lock_queues();
931 if (pm->pm_l2[L2_IDX(l1idx)] != NULL) {
932 vm_page_unlock_queues();
933 uma_zfree(l2table_zone, l2);
934 vm_page_lock_queues();
935 l2 = pm->pm_l2[L2_IDX(l1idx)];
939 * Someone already allocated the l2_dtable while
940 * we were doing the same.
943 bzero(l2, sizeof(*l2));
945 * Link it into the parent pmap
947 pm->pm_l2[L2_IDX(l1idx)] = l2;
951 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
954 * Fetch pointer to the L2 page table associated with the address.
956 if (l2b->l2b_kva == NULL) {
960 * No L2 page table has been allocated. Chances are, this
961 * is because we just allocated the l2_dtable, above.
964 vm_page_unlock_queues();
965 ptep = (void*)uma_zalloc(l2zone, M_NOWAIT);
966 vm_page_lock_queues();
967 if (l2b->l2b_kva != 0) {
968 /* We lost the race. */
969 vm_page_unlock_queues();
970 uma_zfree(l2zone, ptep);
971 vm_page_lock_queues();
972 if (l2b->l2b_kva == 0)
976 l2b->l2b_phys = vtophys(ptep);
979 * Oops, no more L2 page tables available at this
980 * time. We may need to deallocate the l2_dtable
981 * if we allocated a new one above.
983 if (l2->l2_occupancy == 0) {
984 pm->pm_l2[L2_IDX(l1idx)] = NULL;
985 pmap_free_l2_dtable(l2);
992 l2b->l2b_l1idx = l1idx;
998 static PMAP_INLINE void
999 #ifndef PMAP_INCLUDE_PTE_SYNC
1000 pmap_free_l2_ptp(pt_entry_t *l2)
1002 pmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2)
1005 #ifdef PMAP_INCLUDE_PTE_SYNC
1007 * Note: With a write-back cache, we may need to sync this
1008 * L2 table before re-using it.
1009 * This is because it may have belonged to a non-current
1010 * pmap, in which case the cache syncs would have been
1011 * skipped when the pages were being unmapped. If the
1012 * L2 table were then to be immediately re-allocated to
1013 * the *current* pmap, it may well contain stale mappings
1014 * which have not yet been cleared by a cache write-back
1015 * and so would still be visible to the mmu.
1018 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
1020 uma_zfree(l2zone, l2);
1023 * One or more mappings in the specified L2 descriptor table have just been
1026 * Garbage collect the metadata and descriptor table itself if necessary.
1028 * The pmap lock must be acquired when this is called (not necessary
1029 * for the kernel pmap).
1032 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count)
1034 struct l2_dtable *l2;
1035 pd_entry_t *pl1pd, l1pd;
1041 * Update the bucket's reference count according to how many
1042 * PTEs the caller has just invalidated.
1044 l2b->l2b_occupancy -= count;
1049 * Level 2 page tables allocated to the kernel pmap are never freed
1050 * as that would require checking all Level 1 page tables and
1051 * removing any references to the Level 2 page table. See also the
1052 * comment elsewhere about never freeing bootstrap L2 descriptors.
1054 * We make do with just invalidating the mapping in the L2 table.
1056 * This isn't really a big deal in practice and, in fact, leads
1057 * to a performance win over time as we don't need to continually
1060 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel())
1064 * There are no more valid mappings in this level 2 page table.
1065 * Go ahead and NULL-out the pointer in the bucket, then
1066 * free the page table.
1068 l1idx = l2b->l2b_l1idx;
1069 ptep = l2b->l2b_kva;
1070 l2b->l2b_kva = NULL;
1072 pl1pd = &pm->pm_l1->l1_kva[l1idx];
1075 * If the L1 slot matches the pmap's domain
1076 * number, then invalidate it.
1078 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK);
1079 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) {
1085 * Release the L2 descriptor table back to the pool cache.
1087 #ifndef PMAP_INCLUDE_PTE_SYNC
1088 pmap_free_l2_ptp(ptep);
1090 pmap_free_l2_ptp(!pmap_is_current(pm), ptep);
1094 * Update the reference count in the associated l2_dtable
1096 l2 = pm->pm_l2[L2_IDX(l1idx)];
1097 if (--l2->l2_occupancy > 0)
1101 * There are no more valid mappings in any of the Level 1
1102 * slots managed by this l2_dtable. Go ahead and NULL-out
1103 * the pointer in the parent pmap and free the l2_dtable.
1105 pm->pm_l2[L2_IDX(l1idx)] = NULL;
1106 pmap_free_l2_dtable(l2);
1110 * Pool cache constructors for L2 descriptor tables, metadata and pmap
1114 pmap_l2ptp_ctor(void *mem, int size, void *arg, int flags)
1116 #ifndef PMAP_INCLUDE_PTE_SYNC
1117 struct l2_bucket *l2b;
1118 pt_entry_t *ptep, pte;
1119 #ifdef ARM_USE_SMALL_ALLOC
1122 vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK;
1125 * The mappings for these page tables were initially made using
1126 * pmap_kenter() by the pool subsystem. Therefore, the cache-
1127 * mode will not be right for page table mappings. To avoid
1128 * polluting the pmap_kenter() code with a special case for
1129 * page tables, we simply fix up the cache-mode here if it's not
1132 #ifdef ARM_USE_SMALL_ALLOC
1133 pde = &kernel_pmap->pm_l1->l1_kva[L1_IDX(va)];
1134 if (!l1pte_section_p(*pde)) {
1136 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
1137 ptep = &l2b->l2b_kva[l2pte_index(va)];
1140 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
1142 * Page tables must have the cache-mode set to
1145 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
1147 cpu_tlb_flushD_SE(va);
1151 #ifdef ARM_USE_SMALL_ALLOC
1155 memset(mem, 0, L2_TABLE_SIZE_REAL);
1156 PTE_SYNC_RANGE(mem, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
1161 * A bunch of routines to conditionally flush the caches/TLB depending
1162 * on whether the specified pmap actually needs to be flushed at any
1165 static PMAP_INLINE void
1166 pmap_tlb_flushID_SE(pmap_t pm, vm_offset_t va)
1169 if (pmap_is_current(pm))
1170 cpu_tlb_flushID_SE(va);
1173 static PMAP_INLINE void
1174 pmap_tlb_flushD_SE(pmap_t pm, vm_offset_t va)
1177 if (pmap_is_current(pm))
1178 cpu_tlb_flushD_SE(va);
1181 static PMAP_INLINE void
1182 pmap_tlb_flushID(pmap_t pm)
1185 if (pmap_is_current(pm))
1188 static PMAP_INLINE void
1189 pmap_tlb_flushD(pmap_t pm)
1192 if (pmap_is_current(pm))
1196 static PMAP_INLINE void
1197 pmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len)
1200 if (pmap_is_current(pm))
1201 cpu_idcache_wbinv_range(va, len);
1204 static PMAP_INLINE void
1205 pmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len,
1206 boolean_t do_inv, boolean_t rd_only)
1209 if (pmap_is_current(pm)) {
1212 cpu_dcache_inv_range(va, len);
1214 cpu_dcache_wbinv_range(va, len);
1217 cpu_dcache_wb_range(va, len);
1221 static PMAP_INLINE void
1222 pmap_idcache_wbinv_all(pmap_t pm)
1225 if (pmap_is_current(pm))
1226 cpu_idcache_wbinv_all();
1229 static PMAP_INLINE void
1230 pmap_dcache_wbinv_all(pmap_t pm)
1233 if (pmap_is_current(pm))
1234 cpu_dcache_wbinv_all();
1240 * Make sure the pte is written out to RAM.
1241 * We need to do this for one of two cases:
1242 * - We're dealing with the kernel pmap
1243 * - There is no pmap active in the cache/tlb.
1244 * - The specified pmap is 'active' in the cache/tlb.
1246 #ifdef PMAP_INCLUDE_PTE_SYNC
1247 #define PTE_SYNC_CURRENT(pm, ptep) \
1249 if (PMAP_NEEDS_PTE_SYNC && \
1250 pmap_is_current(pm)) \
1252 } while (/*CONSTCOND*/0)
1254 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */
1258 * Since we have a virtually indexed cache, we may need to inhibit caching if
1259 * there is more than one mapping and at least one of them is writable.
1260 * Since we purge the cache on every context switch, we only need to check for
1261 * other mappings within the same pmap, or kernel_pmap.
1262 * This function is also called when a page is unmapped, to possibly reenable
1263 * caching on any remaining mappings.
1265 * The code implements the following logic, where:
1267 * KW = # of kernel read/write pages
1268 * KR = # of kernel read only pages
1269 * UW = # of user read/write pages
1270 * UR = # of user read only pages
1272 * KC = kernel mapping is cacheable
1273 * UC = user mapping is cacheable
1275 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0
1276 * +---------------------------------------------
1277 * UW=0,UR=0 | --- KC=1 KC=1 KC=0
1278 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0
1279 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0
1280 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0
1283 static const int pmap_vac_flags[4][4] = {
1284 {-1, 0, 0, PVF_KNC},
1285 {0, 0, PVF_NC, PVF_NC},
1286 {0, PVF_NC, PVF_NC, PVF_NC},
1287 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC}
1290 static PMAP_INLINE int
1291 pmap_get_vac_flags(const struct vm_page *pg)
1296 if (pg->md.kro_mappings || pg->md.krw_mappings > 1)
1298 if (pg->md.krw_mappings)
1302 if (pg->md.uro_mappings || pg->md.urw_mappings > 1)
1304 if (pg->md.urw_mappings)
1307 return (pmap_vac_flags[uidx][kidx]);
1310 static __inline void
1311 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1315 nattr = pmap_get_vac_flags(pg);
1318 pg->md.pvh_attrs &= ~PVF_NC;
1322 if (nattr == 0 && (pg->md.pvh_attrs & PVF_NC) == 0) {
1326 if (pm == pmap_kernel())
1327 pmap_vac_me_kpmap(pg, pm, va);
1329 pmap_vac_me_user(pg, pm, va);
1331 pg->md.pvh_attrs = (pg->md.pvh_attrs & ~PVF_NC) | nattr;
1335 pmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1337 u_int u_cacheable, u_entries;
1338 struct pv_entry *pv;
1339 pmap_t last_pmap = pm;
1342 * Pass one, see if there are both kernel and user pmaps for
1343 * this page. Calculate whether there are user-writable or
1344 * kernel-writable pages.
1347 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1348 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0)
1352 u_entries = pg->md.urw_mappings + pg->md.uro_mappings;
1355 * We know we have just been updating a kernel entry, so if
1356 * all user pages are already cacheable, then there is nothing
1359 if (pg->md.k_mappings == 0 && u_cacheable == u_entries)
1364 * Scan over the list again, for each entry, if it
1365 * might not be set correctly, call pmap_vac_me_user
1366 * to recalculate the settings.
1368 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1370 * We know kernel mappings will get set
1371 * correctly in other calls. We also know
1372 * that if the pmap is the same as last_pmap
1373 * then we've just handled this entry.
1375 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap)
1379 * If there are kernel entries and this page
1380 * is writable but non-cacheable, then we can
1381 * skip this entry also.
1383 if (pg->md.k_mappings &&
1384 (pv->pv_flags & (PVF_NC | PVF_WRITE)) ==
1385 (PVF_NC | PVF_WRITE))
1389 * Similarly if there are no kernel-writable
1390 * entries and the page is already
1391 * read-only/cacheable.
1393 if (pg->md.krw_mappings == 0 &&
1394 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0)
1398 * For some of the remaining cases, we know
1399 * that we must recalculate, but for others we
1400 * can't tell if they are correct or not, so
1401 * we recalculate anyway.
1403 pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0);
1406 if (pg->md.k_mappings == 0)
1410 pmap_vac_me_user(pg, pm, va);
1414 pmap_vac_me_user(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1416 pmap_t kpmap = pmap_kernel();
1417 struct pv_entry *pv, *npv;
1418 struct l2_bucket *l2b;
1419 pt_entry_t *ptep, pte;
1422 u_int cacheable_entries = 0;
1423 u_int kern_cacheable = 0;
1424 u_int other_writable = 0;
1427 * Count mappings and writable mappings in this pmap.
1428 * Include kernel mappings as part of our own.
1429 * Keep a pointer to the first one.
1431 npv = TAILQ_FIRST(&pg->md.pv_list);
1432 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1433 /* Count mappings in the same pmap */
1434 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) {
1438 /* Cacheable mappings */
1439 if ((pv->pv_flags & PVF_NC) == 0) {
1440 cacheable_entries++;
1441 if (kpmap == pv->pv_pmap)
1445 /* Writable mappings */
1446 if (pv->pv_flags & PVF_WRITE)
1449 if (pv->pv_flags & PVF_WRITE)
1454 * Enable or disable caching as necessary.
1455 * Note: the first entry might be part of the kernel pmap,
1456 * so we can't assume this is indicative of the state of the
1457 * other (maybe non-kpmap) entries.
1459 if ((entries > 1 && writable) ||
1460 (entries > 0 && pm == kpmap && other_writable)) {
1461 if (cacheable_entries == 0)
1464 for (pv = npv; pv; pv = TAILQ_NEXT(pv, pv_list)) {
1465 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) ||
1466 (pv->pv_flags & PVF_NC))
1469 pv->pv_flags |= PVF_NC;
1471 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
1472 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
1473 pte = *ptep & ~L2_S_CACHE_MASK;
1475 if ((va != pv->pv_va || pm != pv->pv_pmap) &&
1477 if (PV_BEEN_EXECD(pv->pv_flags)) {
1478 pmap_idcache_wbinv_range(pv->pv_pmap,
1479 pv->pv_va, PAGE_SIZE);
1480 pmap_tlb_flushID_SE(pv->pv_pmap,
1483 if (PV_BEEN_REFD(pv->pv_flags)) {
1484 pmap_dcache_wb_range(pv->pv_pmap,
1485 pv->pv_va, PAGE_SIZE, TRUE,
1486 (pv->pv_flags & PVF_WRITE) == 0);
1487 pmap_tlb_flushD_SE(pv->pv_pmap,
1493 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
1497 if (entries > cacheable_entries) {
1499 * Turn cacheing back on for some pages. If it is a kernel
1500 * page, only do so if there are no other writable pages.
1502 for (pv = npv; pv; pv = TAILQ_NEXT(pv, pv_list)) {
1503 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap &&
1504 (kpmap != pv->pv_pmap || other_writable)))
1507 pv->pv_flags &= ~PVF_NC;
1509 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
1510 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
1511 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode;
1513 if (l2pte_valid(pte)) {
1514 if (PV_BEEN_EXECD(pv->pv_flags)) {
1515 pmap_tlb_flushID_SE(pv->pv_pmap,
1518 if (PV_BEEN_REFD(pv->pv_flags)) {
1519 pmap_tlb_flushD_SE(pv->pv_pmap,
1525 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
1531 * Modify pte bits for all ptes corresponding to the given physical address.
1532 * We use `maskbits' rather than `clearbits' because we're always passing
1533 * constants and the latter would require an extra inversion at run-time.
1536 pmap_clearbit(struct vm_page *pg, u_int maskbits)
1538 struct l2_bucket *l2b;
1539 struct pv_entry *pv;
1540 pt_entry_t *ptep, npte, opte;
1546 PMAP_HEAD_TO_MAP_LOCK();
1547 simple_lock(&pg->mdpage.pvh_slock);
1551 * Clear saved attributes (modify, reference)
1553 pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF));
1555 if (TAILQ_EMPTY(&pg->md.pv_list)) {
1557 simple_unlock(&pg->mdpage.pvh_slock);
1558 PMAP_HEAD_TO_MAP_UNLOCK();
1564 * Loop over all current mappings setting/clearing as appropos
1566 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1569 oflags = pv->pv_flags;
1570 pv->pv_flags &= ~maskbits;
1573 pmap_acquire_pmap_lock(pm);
1576 l2b = pmap_get_l2_bucket(pm, va);
1578 ptep = &l2b->l2b_kva[l2pte_index(va)];
1579 npte = opte = *ptep;
1581 if (maskbits & (PVF_WRITE|PVF_MOD)) {
1582 if ((pv->pv_flags & PVF_NC)) {
1584 * Entry is not cacheable:
1586 * Don't turn caching on again if this is a
1587 * modified emulation. This would be
1588 * inconsitent with the settings created by
1589 * pmap_vac_me_harder(). Otherwise, it's safe
1590 * to re-enable cacheing.
1592 * There's no need to call pmap_vac_me_harder()
1593 * here: all pages are losing their write
1596 if (maskbits & PVF_WRITE) {
1597 npte |= pte_l2_s_cache_mode;
1598 pv->pv_flags &= ~PVF_NC;
1601 if (opte & L2_S_PROT_W) {
1604 * Entry is writable/cacheable: check if pmap
1605 * is current if it is flush it, otherwise it
1606 * won't be in the cache
1608 if (PV_BEEN_EXECD(oflags))
1609 pmap_idcache_wbinv_range(pm, pv->pv_va,
1612 if (PV_BEEN_REFD(oflags))
1613 pmap_dcache_wb_range(pm, pv->pv_va,
1615 (maskbits & PVF_REF) ? TRUE : FALSE,
1619 /* make the pte read only */
1620 npte &= ~L2_S_PROT_W;
1622 if (maskbits & PVF_WRITE) {
1624 * Keep alias accounting up to date
1626 if (pv->pv_pmap == pmap_kernel()) {
1627 if (oflags & PVF_WRITE) {
1628 pg->md.krw_mappings--;
1629 pg->md.kro_mappings++;
1632 if (oflags & PVF_WRITE) {
1633 pg->md.urw_mappings--;
1634 pg->md.uro_mappings++;
1639 if (maskbits & PVF_REF) {
1640 if ((pv->pv_flags & PVF_NC) == 0 &&
1641 (maskbits & (PVF_WRITE|PVF_MOD)) == 0) {
1643 * Check npte here; we may have already
1644 * done the wbinv above, and the validity
1645 * of the PTE is the same for opte and
1648 if (npte & L2_S_PROT_W) {
1649 if (PV_BEEN_EXECD(oflags))
1650 pmap_idcache_wbinv_range(pm,
1651 pv->pv_va, PAGE_SIZE);
1653 if (PV_BEEN_REFD(oflags))
1654 pmap_dcache_wb_range(pm,
1655 pv->pv_va, PAGE_SIZE,
1658 if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) {
1659 /* XXXJRT need idcache_inv_range */
1660 if (PV_BEEN_EXECD(oflags))
1661 pmap_idcache_wbinv_range(pm,
1662 pv->pv_va, PAGE_SIZE);
1664 if (PV_BEEN_REFD(oflags))
1665 pmap_dcache_wb_range(pm,
1666 pv->pv_va, PAGE_SIZE,
1672 * Make the PTE invalid so that we will take a
1673 * page fault the next time the mapping is
1676 npte &= ~L2_TYPE_MASK;
1677 npte |= L2_TYPE_INV;
1684 /* Flush the TLB entry if a current pmap. */
1685 if (PV_BEEN_EXECD(oflags))
1686 pmap_tlb_flushID_SE(pm, pv->pv_va);
1688 if (PV_BEEN_REFD(oflags))
1689 pmap_tlb_flushD_SE(pm, pv->pv_va);
1693 pmap_release_pmap_lock(pm);
1699 simple_unlock(&pg->mdpage.pvh_slock);
1700 PMAP_HEAD_TO_MAP_UNLOCK();
1702 if (maskbits & PVF_WRITE)
1703 vm_page_flag_clear(pg, PG_WRITEABLE);
1708 * main pv_entry manipulation functions:
1709 * pmap_enter_pv: enter a mapping onto a vm_page list
1710 * pmap_remove_pv: remove a mappiing from a vm_page list
1712 * NOTE: pmap_enter_pv expects to lock the pvh itself
1713 * pmap_remove_pv expects te caller to lock the pvh before calling
1717 * pmap_enter_pv: enter a mapping onto a vm_page lst
1719 * => caller should hold the proper lock on pmap_main_lock
1720 * => caller should have pmap locked
1721 * => we will gain the lock on the vm_page and allocate the new pv_entry
1722 * => caller should adjust ptp's wire_count before calling
1723 * => caller should not adjust pmap's wire_count
1726 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm,
1727 vm_offset_t va, u_int flags)
1733 pve->pv_flags = flags;
1736 mtx_lock(&pg->md.pvh_mtx);
1738 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list);
1739 TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist);
1740 pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD);
1741 if (pm == pmap_kernel()) {
1742 if (flags & PVF_WRITE)
1743 pg->md.krw_mappings++;
1745 pg->md.kro_mappings++;
1747 if (flags & PVF_WRITE)
1748 pg->md.urw_mappings++;
1750 pg->md.uro_mappings++;
1751 pg->md.pv_list_count++;
1753 mtx_unlock(&pg->md.pvh_mtx);
1755 if (pve->pv_flags & PVF_WIRED)
1756 ++pm->pm_stats.wired_count;
1757 vm_page_flag_set(pg, PG_REFERENCED);
1762 * pmap_find_pv: Find a pv entry
1764 * => caller should hold lock on vm_page
1766 static PMAP_INLINE struct pv_entry *
1767 pmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1769 struct pv_entry *pv;
1771 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list)
1772 if (pm == pv->pv_pmap && va == pv->pv_va)
1778 * vector_page_setprot:
1780 * Manipulate the protection of the vector page.
1783 vector_page_setprot(int prot)
1785 struct l2_bucket *l2b;
1788 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page);
1790 ptep = &l2b->l2b_kva[l2pte_index(vector_page)];
1792 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot);
1794 cpu_tlb_flushD_SE(vector_page);
1799 * pmap_remove_pv: try to remove a mapping from a pv_list
1801 * => caller should hold proper lock on pmap_main_lock
1802 * => pmap should be locked
1803 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1804 * => caller should adjust ptp's wire_count and free PTP if needed
1805 * => caller should NOT adjust pmap's wire_count
1806 * => we return the removed pve
1810 pmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve)
1813 TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list);
1814 TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist);
1815 if (pve->pv_flags & PVF_WIRED)
1816 --pm->pm_stats.wired_count;
1817 pg->md.pv_list_count--;
1818 if (pg->md.pvh_attrs & PVF_MOD)
1820 if (pm == pmap_kernel()) {
1821 if (pve->pv_flags & PVF_WRITE)
1822 pg->md.krw_mappings--;
1824 pg->md.kro_mappings--;
1826 if (pve->pv_flags & PVF_WRITE)
1827 pg->md.urw_mappings--;
1829 pg->md.uro_mappings--;
1830 if (TAILQ_FIRST(&pg->md.pv_list) == NULL ||
1831 (pg->md.krw_mappings == 0 && pg->md.urw_mappings == 0)) {
1832 pg->md.pvh_attrs &= ~PVF_MOD;
1833 if (TAILQ_FIRST(&pg->md.pv_list) == NULL)
1834 pg->md.pvh_attrs &= ~PVF_REF;
1835 vm_page_flag_clear(pg, PG_WRITEABLE);
1837 if (TAILQ_FIRST(&pg->md.pv_list))
1838 vm_page_flag_set(pg, PG_REFERENCED);
1839 if (pve->pv_flags & PVF_WRITE)
1840 pmap_vac_me_harder(pg, pm, 0);
1843 static struct pv_entry *
1844 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1846 struct pv_entry *pve;
1848 pve = TAILQ_FIRST(&pg->md.pv_list);
1851 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */
1852 pmap_nuke_pv(pg, pm, pve);
1855 pve = TAILQ_NEXT(pve, pv_list);
1858 return(pve); /* return removed pve */
1862 * pmap_modify_pv: Update pv flags
1864 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1865 * => caller should NOT adjust pmap's wire_count
1866 * => caller must call pmap_vac_me_harder() if writable status of a page
1868 * => we return the old flags
1870 * Modify a physical-virtual mapping in the pv table
1873 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va,
1874 u_int clr_mask, u_int set_mask)
1876 struct pv_entry *npv;
1877 u_int flags, oflags;
1879 if ((npv = pmap_find_pv(pg, pm, va)) == NULL)
1883 * There is at least one VA mapping this page.
1886 if (clr_mask & (PVF_REF | PVF_MOD))
1887 pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD);
1889 oflags = npv->pv_flags;
1890 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask;
1892 if ((flags ^ oflags) & PVF_WIRED) {
1893 if (flags & PVF_WIRED)
1894 ++pm->pm_stats.wired_count;
1896 --pm->pm_stats.wired_count;
1899 if ((flags ^ oflags) & PVF_WRITE) {
1900 if (pm == pmap_kernel()) {
1901 if (flags & PVF_WRITE) {
1902 pg->md.krw_mappings++;
1903 pg->md.kro_mappings--;
1905 pg->md.kro_mappings++;
1906 pg->md.krw_mappings--;
1909 if (flags & PVF_WRITE) {
1910 pg->md.urw_mappings++;
1911 pg->md.uro_mappings--;
1913 pg->md.uro_mappings++;
1914 pg->md.urw_mappings--;
1916 if (pg->md.krw_mappings == 0 && pg->md.urw_mappings == 0) {
1917 pg->md.pvh_attrs &= ~PVF_MOD;
1918 vm_page_flag_clear(pg, PG_WRITEABLE);
1920 pmap_vac_me_harder(pg, pm, 0);
1926 /* Function to set the debug level of the pmap code */
1929 pmap_debug(int level)
1931 pmap_debug_level = level;
1932 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
1934 #endif /* PMAP_DEBUG */
1937 pmap_pinit0(struct pmap *pmap)
1939 PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap));
1941 dprintf("pmap_pinit0: pmap = %08x, pm_pdir = %08x\n",
1942 (u_int32_t) pmap, (u_int32_t) pmap->pm_pdir);
1943 bcopy(kernel_pmap, pmap, sizeof(*pmap));
1944 bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx));
1945 PMAP_LOCK_INIT(pmap);
1949 * Initialize a vm_page's machine-dependent fields.
1952 pmap_page_init(vm_page_t m)
1955 TAILQ_INIT(&m->md.pv_list);
1956 m->md.pv_list_count = 0;
1960 * Initialize the pmap module.
1961 * Called by vm_init, to initialize any structures that the pmap
1962 * system needs to map virtual memory.
1967 int shpgperproc = PMAP_SHPGPERPROC;
1969 PDEBUG(1, printf("pmap_init: phys_start = %08x\n"));
1972 * init the pv free list
1974 pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL,
1975 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1977 * Now it is safe to enable pv_table recording.
1979 PDEBUG(1, printf("pmap_init: done!\n"));
1981 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1983 pv_entry_max = shpgperproc * maxproc + vm_page_array_size;
1984 pv_entry_high_water = 9 * (pv_entry_max / 10);
1985 l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor,
1986 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1987 l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable),
1988 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1989 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1991 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max);
1992 uma_zone_set_obj(l2zone, &l2zone_obj, pv_entry_max);
1997 pmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user)
1999 struct l2_dtable *l2;
2000 struct l2_bucket *l2b;
2001 pd_entry_t *pl1pd, l1pd;
2002 pt_entry_t *ptep, pte;
2008 PMAP_MAP_TO_HEAD_LOCK();
2009 pmap_acquire_pmap_lock(pm);
2014 * If there is no l2_dtable for this address, then the process
2015 * has no business accessing it.
2017 * Note: This will catch userland processes trying to access
2020 l2 = pm->pm_l2[L2_IDX(l1idx)];
2025 * Likewise if there is no L2 descriptor table
2027 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2028 if (l2b->l2b_kva == NULL)
2032 * Check the PTE itself.
2034 ptep = &l2b->l2b_kva[l2pte_index(va)];
2040 * Catch a userland access to the vector page mapped at 0x0
2042 if (user && (pte & L2_S_PROT_U) == 0)
2044 if (va == vector_page)
2049 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) {
2051 * This looks like a good candidate for "page modified"
2054 struct pv_entry *pv;
2057 /* Extract the physical address of the page */
2058 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) {
2061 /* Get the current flags for this page. */
2063 pv = pmap_find_pv(pg, pm, va);
2069 * Do the flags say this page is writable? If not then it
2070 * is a genuine write fault. If yes then the write fault is
2071 * our fault as we did not reflect the write access in the
2072 * PTE. Now we know a write has occurred we can correct this
2073 * and also set the modified bit
2075 if ((pv->pv_flags & PVF_WRITE) == 0) {
2079 pg->md.pvh_attrs |= PVF_REF | PVF_MOD;
2081 pv->pv_flags |= PVF_REF | PVF_MOD;
2084 * Re-enable write permissions for the page. No need to call
2085 * pmap_vac_me_harder(), since this is just a
2086 * modified-emulation fault, and the PVF_WRITE bit isn't
2087 * changing. We've already set the cacheable bits based on
2088 * the assumption that we can write to this page.
2090 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W;
2094 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) {
2096 * This looks like a good candidate for "page referenced"
2099 struct pv_entry *pv;
2102 /* Extract the physical address of the page */
2103 vm_page_lock_queues();
2104 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) {
2105 vm_page_unlock_queues();
2108 /* Get the current flags for this page. */
2110 pv = pmap_find_pv(pg, pm, va);
2112 vm_page_unlock_queues();
2116 pg->md.pvh_attrs |= PVF_REF;
2117 pv->pv_flags |= PVF_REF;
2120 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO;
2123 vm_page_unlock_queues();
2127 * We know there is a valid mapping here, so simply
2128 * fix up the L1 if necessary.
2130 pl1pd = &pm->pm_l1->l1_kva[l1idx];
2131 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO;
2132 if (*pl1pd != l1pd) {
2140 * There are bugs in the rev K SA110. This is a check for one
2143 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 &&
2144 curcpu()->ci_arm_cpurev < 3) {
2145 /* Always current pmap */
2146 if (l2pte_valid(pte)) {
2147 extern int kernel_debug;
2148 if (kernel_debug & 1) {
2149 struct proc *p = curlwp->l_proc;
2150 printf("prefetch_abort: page is already "
2151 "mapped - pte=%p *pte=%08x\n", ptep, pte);
2152 printf("prefetch_abort: pc=%08lx proc=%p "
2153 "process=%s\n", va, p, p->p_comm);
2154 printf("prefetch_abort: far=%08x fs=%x\n",
2155 cpu_faultaddress(), cpu_faultstatus());
2158 if (kernel_debug & 2)
2164 #endif /* CPU_SA110 */
2168 * If 'rv == 0' at this point, it generally indicates that there is a
2169 * stale TLB entry for the faulting address. This happens when two or
2170 * more processes are sharing an L1. Since we don't flush the TLB on
2171 * a context switch between such processes, we can take domain faults
2172 * for mappings which exist at the same VA in both processes. EVEN IF
2173 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for
2176 * This is extremely likely to happen if pmap_enter() updated the L1
2177 * entry for a recently entered mapping. In this case, the TLB is
2178 * flushed for the new mapping, but there may still be TLB entries for
2179 * other mappings belonging to other processes in the 1MB range
2180 * covered by the L1 entry.
2182 * Since 'rv == 0', we know that the L1 already contains the correct
2183 * value, so the fault must be due to a stale TLB entry.
2185 * Since we always need to flush the TLB anyway in the case where we
2186 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with
2187 * stale TLB entries dynamically.
2189 * However, the above condition can ONLY happen if the current L1 is
2190 * being shared. If it happens when the L1 is unshared, it indicates
2191 * that other parts of the pmap are not doing their job WRT managing
2194 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) {
2195 extern int last_fault_code;
2196 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n",
2198 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n",
2199 l2, l2b, ptep, pl1pd);
2200 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n",
2201 pte, l1pd, last_fault_code);
2208 cpu_tlb_flushID_SE(va);
2215 pmap_release_pmap_lock(pm);
2216 PMAP_MAP_TO_HEAD_UNLOCK();
2224 struct l2_bucket *l2b;
2225 struct l1_ttable *l1;
2227 pt_entry_t *ptep, pte;
2228 vm_offset_t va, eva;
2231 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0);
2233 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK);
2235 for (loop = 0; loop < needed; loop++, l1++) {
2236 /* Allocate a L1 page table */
2237 va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0,
2238 0xffffffff, L1_TABLE_SIZE, 0);
2241 panic("Cannot allocate L1 KVM");
2243 eva = va + L1_TABLE_SIZE;
2244 pl1pt = (pd_entry_t *)va;
2247 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2248 ptep = &l2b->l2b_kva[l2pte_index(va)];
2250 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
2253 cpu_tlb_flushD_SE(va);
2257 pmap_init_l1(l1, pl1pt);
2262 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n",
2268 * This is used to stuff certain critical values into the PCB where they
2269 * can be accessed quickly from cpu_switch() et al.
2272 pmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb)
2274 struct l2_bucket *l2b;
2276 pcb->pcb_pagedir = pm->pm_l1->l1_physaddr;
2277 pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) |
2278 (DOMAIN_CLIENT << (pm->pm_domain * 2));
2280 if (vector_page < KERNBASE) {
2281 pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)];
2282 l2b = pmap_get_l2_bucket(pm, vector_page);
2283 pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO |
2284 L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL);
2286 pcb->pcb_pl1vec = NULL;
2290 pmap_activate(struct thread *td)
2296 pm = vmspace_pmap(td->td_proc->p_vmspace);
2300 pmap_set_pcb_pagedir(pm, pcb);
2302 if (td == curthread) {
2303 u_int cur_dacr, cur_ttb;
2305 __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb));
2306 __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr));
2308 cur_ttb &= ~(L1_TABLE_SIZE - 1);
2310 if (cur_ttb == (u_int)pcb->pcb_pagedir &&
2311 cur_dacr == pcb->pcb_dacr) {
2313 * No need to switch address spaces.
2321 * We MUST, I repeat, MUST fix up the L1 entry corresponding
2322 * to 'vector_page' in the incoming L1 table before switching
2323 * to it otherwise subsequent interrupts/exceptions (including
2324 * domain faults!) will jump into hyperspace.
2326 if (pcb->pcb_pl1vec) {
2328 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2330 * Don't need to PTE_SYNC() at this point since
2331 * cpu_setttb() is about to flush both the cache
2336 cpu_domains(pcb->pcb_dacr);
2337 cpu_setttb(pcb->pcb_pagedir);
2345 pmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va)
2347 pd_entry_t *pdep, pde;
2348 pt_entry_t *ptep, pte;
2353 * Make sure the descriptor itself has the correct cache mode
2355 pdep = &kl1[L1_IDX(va)];
2358 if (l1pte_section_p(pde)) {
2359 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) {
2360 *pdep = (pde & ~L1_S_CACHE_MASK) |
2361 pte_l1_s_cache_mode_pt;
2363 cpu_dcache_wbinv_range((vm_offset_t)pdep,
2368 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2369 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2371 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep);
2373 ptep = &ptep[l2pte_index(va)];
2375 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
2376 *ptep = (pte & ~L2_S_CACHE_MASK) |
2377 pte_l2_s_cache_mode_pt;
2379 cpu_dcache_wbinv_range((vm_offset_t)ptep,
2389 pmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap,
2392 vm_offset_t va = *availp;
2393 struct l2_bucket *l2b;
2396 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2398 panic("pmap_alloc_specials: no l2b for 0x%x", va);
2400 *ptep = &l2b->l2b_kva[l2pte_index(va)];
2404 *availp = va + (PAGE_SIZE * pages);
2408 * Bootstrap the system enough to run with virtual memory.
2410 * On the arm this is called after mapping has already been enabled
2411 * and just syncs the pmap module with what has already been done.
2412 * [We can't call it easily with mapping off since the kernel is not
2413 * mapped with PA == VA, hence we would have to relocate every address
2414 * from the linked base (virtual) address "KERNBASE" to the actual
2415 * (physical) address starting relative to 0]
2417 #define PMAP_STATIC_L2_SIZE 16
2418 #ifdef ARM_USE_SMALL_ALLOC
2419 extern struct mtx smallalloc_mtx;
2420 extern vm_offset_t alloc_curaddr;
2421 extern vm_offset_t alloc_firstaddr;
2425 pmap_bootstrap(vm_offset_t firstaddr, vm_offset_t lastaddr, struct pv_addr *l1pt)
2427 static struct l1_ttable static_l1;
2428 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE];
2429 struct l1_ttable *l1 = &static_l1;
2430 struct l2_dtable *l2;
2431 struct l2_bucket *l2b;
2433 pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va;
2438 int l1idx, l2idx, l2next = 0;
2440 PDEBUG(1, printf("firstaddr = %08x, loadaddr = %08x\n",
2441 firstaddr, loadaddr));
2443 virtual_avail = firstaddr;
2444 kernel_pmap = &kernel_pmap_store;
2445 kernel_pmap->pm_l1 = l1;
2446 kernel_l1pa = l1pt->pv_pa;
2449 * Scan the L1 translation table created by initarm() and create
2450 * the required metadata for all valid mappings found in it.
2452 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) {
2453 pde = kernel_l1pt[l1idx];
2456 * We're only interested in Coarse mappings.
2457 * pmap_extract() can deal with section mappings without
2458 * recourse to checking L2 metadata.
2460 if ((pde & L1_TYPE_MASK) != L1_TYPE_C)
2464 * Lookup the KVA of this L2 descriptor table
2466 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2467 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2470 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx",
2471 (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa);
2475 * Fetch the associated L2 metadata structure.
2476 * Allocate a new one if necessary.
2478 if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) {
2479 if (l2next == PMAP_STATIC_L2_SIZE)
2480 panic("pmap_bootstrap: out of static L2s");
2481 kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 =
2482 &static_l2[l2next++];
2486 * One more L1 slot tracked...
2491 * Fill in the details of the L2 descriptor in the
2492 * appropriate bucket.
2494 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2495 l2b->l2b_kva = ptep;
2497 l2b->l2b_l1idx = l1idx;
2500 * Establish an initial occupancy count for this descriptor
2503 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
2505 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) {
2506 l2b->l2b_occupancy++;
2511 * Make sure the descriptor itself has the correct cache mode.
2512 * If not, fix it, but whine about the problem. Port-meisters
2513 * should consider this a clue to fix up their initarm()
2516 if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) {
2517 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2518 "L2 pte @ %p\n", ptep);
2524 * Ensure the primary (kernel) L1 has the correct cache mode for
2525 * a page table. Bitch if it is not correctly set.
2527 for (va = (vm_offset_t)kernel_l1pt;
2528 va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) {
2529 if (pmap_set_pt_cache_mode(kernel_l1pt, va))
2530 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2531 "primary L1 @ 0x%x\n", va);
2534 cpu_dcache_wbinv_all();
2538 PMAP_LOCK_INIT(kernel_pmap);
2539 kernel_pmap->pm_active = -1;
2540 kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL;
2541 TAILQ_INIT(&kernel_pmap->pm_pvlist);
2544 * Reserve some special page table entries/VA space for temporary
2547 #define SYSMAP(c, p, v, n) \
2548 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
2550 pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte);
2551 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte);
2552 pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte);
2553 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte);
2554 size = ((lastaddr - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE;
2555 pmap_alloc_specials(&virtual_avail,
2556 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE,
2557 &pmap_kernel_l2ptp_kva, NULL);
2559 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE;
2560 pmap_alloc_specials(&virtual_avail,
2561 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE,
2562 &pmap_kernel_l2dtable_kva, NULL);
2564 pmap_alloc_specials(&virtual_avail,
2565 1, (vm_offset_t*)&_tmppt, NULL);
2566 SLIST_INIT(&l1_list);
2567 TAILQ_INIT(&l1_lru_list);
2568 mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF);
2569 pmap_init_l1(l1, kernel_l1pt);
2570 cpu_dcache_wbinv_all();
2572 virtual_avail = round_page(virtual_avail);
2573 virtual_end = lastaddr;
2574 kernel_vm_end = pmap_curmaxkvaddr;
2575 arm_nocache_startaddr = lastaddr;
2576 mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF);
2578 #ifdef ARM_USE_SMALL_ALLOC
2579 mtx_init(&smallalloc_mtx, "Small alloc page list", NULL, MTX_DEF);
2580 alloc_firstaddr = alloc_curaddr = arm_nocache_startaddr +
2581 ARM_NOCACHE_KVA_SIZE;
2585 /***************************************************
2586 * Pmap allocation/deallocation routines.
2587 ***************************************************/
2590 * Release any resources held by the given physical map.
2591 * Called when a pmap initialized by pmap_pinit is being released.
2592 * Should only be called if the map contains no valid mappings.
2595 pmap_release(pmap_t pmap)
2599 pmap_idcache_wbinv_all(pmap);
2600 pmap_tlb_flushID(pmap);
2602 if (vector_page < KERNBASE) {
2603 struct pcb *curpcb = PCPU_GET(curpcb);
2604 pcb = thread0.td_pcb;
2605 if (pmap_is_current(pmap)) {
2607 * Frob the L1 entry corresponding to the vector
2608 * page so that it contains the kernel pmap's domain
2609 * number. This will ensure pmap_remove() does not
2610 * pull the current vector page out from under us.
2613 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2614 cpu_domains(pcb->pcb_dacr);
2615 cpu_setttb(pcb->pcb_pagedir);
2618 pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE);
2620 * Make sure cpu_switch(), et al, DTRT. This is safe to do
2621 * since this process has no remaining mappings of its own.
2623 curpcb->pcb_pl1vec = pcb->pcb_pl1vec;
2624 curpcb->pcb_l1vec = pcb->pcb_l1vec;
2625 curpcb->pcb_dacr = pcb->pcb_dacr;
2626 curpcb->pcb_pagedir = pcb->pcb_pagedir;
2630 PMAP_LOCK_DESTROY(pmap);
2632 dprintf("pmap_release()\n");
2638 * Helper function for pmap_grow_l2_bucket()
2641 pmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap)
2643 struct l2_bucket *l2b;
2648 pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
2651 pa = VM_PAGE_TO_PHYS(pg);
2656 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2658 ptep = &l2b->l2b_kva[l2pte_index(va)];
2659 *ptep = L2_S_PROTO | pa | cache_mode |
2660 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE);
2666 * This is the same as pmap_alloc_l2_bucket(), except that it is only
2667 * used by pmap_growkernel().
2669 static __inline struct l2_bucket *
2670 pmap_grow_l2_bucket(pmap_t pm, vm_offset_t va)
2672 struct l2_dtable *l2;
2673 struct l2_bucket *l2b;
2674 struct l1_ttable *l1;
2681 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
2683 * No mapping at this address, as there is
2684 * no entry in the L1 table.
2685 * Need to allocate a new l2_dtable.
2687 nva = pmap_kernel_l2dtable_kva;
2688 if ((nva & PAGE_MASK) == 0) {
2690 * Need to allocate a backing page
2692 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2696 l2 = (struct l2_dtable *)nva;
2697 nva += sizeof(struct l2_dtable);
2699 if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva &
2702 * The new l2_dtable straddles a page boundary.
2703 * Map in another page to cover it.
2705 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2709 pmap_kernel_l2dtable_kva = nva;
2712 * Link it into the parent pmap
2714 pm->pm_l2[L2_IDX(l1idx)] = l2;
2715 memset(l2, 0, sizeof(*l2));
2718 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2721 * Fetch pointer to the L2 page table associated with the address.
2723 if (l2b->l2b_kva == NULL) {
2727 * No L2 page table has been allocated. Chances are, this
2728 * is because we just allocated the l2_dtable, above.
2730 nva = pmap_kernel_l2ptp_kva;
2731 ptep = (pt_entry_t *)nva;
2732 if ((nva & PAGE_MASK) == 0) {
2734 * Need to allocate a backing page
2736 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt,
2737 &pmap_kernel_l2ptp_phys))
2739 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t));
2741 memset(ptep, 0, L2_TABLE_SIZE_REAL);
2743 l2b->l2b_kva = ptep;
2744 l2b->l2b_l1idx = l1idx;
2745 l2b->l2b_phys = pmap_kernel_l2ptp_phys;
2747 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL;
2748 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL;
2751 /* Distribute new L1 entry to all other L1s */
2752 SLIST_FOREACH(l1, &l1_list, l1_link) {
2753 pl1pd = &l1->l1_kva[L1_IDX(va)];
2754 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) |
2764 * grow the number of kernel page table entries, if needed
2767 pmap_growkernel(vm_offset_t addr)
2769 pmap_t kpm = pmap_kernel();
2772 if (addr <= pmap_curmaxkvaddr)
2773 return; /* we are OK */
2776 * whoops! we need to add kernel PTPs
2779 s = splhigh(); /* to be safe */
2781 /* Map 1MB at a time */
2782 for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE)
2783 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr);
2786 * flush out the cache, expensive but growkernel will happen so
2789 cpu_dcache_wbinv_all();
2792 kernel_vm_end = pmap_curmaxkvaddr;
2798 * pmap_page_protect:
2800 * Lower the permission for all mappings to a given page.
2803 pmap_page_protect(vm_page_t m, vm_prot_t prot)
2806 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE:
2807 case VM_PROT_READ|VM_PROT_WRITE:
2811 case VM_PROT_READ|VM_PROT_EXECUTE:
2812 pmap_clearbit(m, PVF_WRITE);
2824 * Remove all pages from specified address space
2825 * this aids process exit speeds. Also, this code
2826 * is special cased for current process only, but
2827 * can have the more generic (and slightly slower)
2828 * mode enabled. This is much faster than pmap_remove
2829 * in the case of running down an entire address space.
2832 pmap_remove_pages(pmap_t pmap)
2834 struct pv_entry *pv, *npv;
2835 struct l2_bucket *l2b = NULL;
2839 vm_page_lock_queues();
2840 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) {
2841 if (pv->pv_flags & PVF_WIRED) {
2842 /* The page is wired, cannot remove it now. */
2843 npv = TAILQ_NEXT(pv, pv_plist);
2846 pmap->pm_stats.resident_count--;
2847 l2b = pmap_get_l2_bucket(pmap, pv->pv_va);
2848 KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages"));
2849 pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
2850 m = PHYS_TO_VM_PAGE(*pt & L2_ADDR_MASK);
2853 npv = TAILQ_NEXT(pv, pv_plist);
2854 pmap_nuke_pv(m, pmap, pv);
2855 if (TAILQ_EMPTY(&m->md.pv_list))
2856 vm_page_flag_clear(m, PG_WRITEABLE);
2857 pmap_free_pv_entry(pv);
2859 vm_page_unlock_queues();
2860 cpu_idcache_wbinv_all();
2866 /***************************************************
2867 * Low level mapping routines.....
2868 ***************************************************/
2870 /* Map a section into the KVA. */
2873 pmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags)
2875 pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL,
2876 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
2877 struct l1_ttable *l1;
2879 KASSERT(((va | pa) & L1_S_OFFSET) == 0,
2880 ("Not a valid section mapping"));
2881 if (flags & SECTION_CACHE)
2882 pd |= pte_l1_s_cache_mode;
2883 else if (flags & SECTION_PT)
2884 pd |= pte_l1_s_cache_mode_pt;
2885 SLIST_FOREACH(l1, &l1_list, l1_link) {
2886 l1->l1_kva[L1_IDX(va)] = pd;
2887 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2892 * add a wired page to the kva
2893 * note that in order for the mapping to take effect -- you
2894 * should do a invltlb after doing the pmap_kenter...
2896 static PMAP_INLINE void
2897 pmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags)
2899 struct l2_bucket *l2b;
2902 PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n",
2903 (uint32_t) va, (uint32_t) pa));
2906 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2908 l2b = pmap_grow_l2_bucket(pmap_kernel(), va);
2909 KASSERT(l2b != NULL, ("No L2 Bucket"));
2910 pte = &l2b->l2b_kva[l2pte_index(va)];
2912 PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n",
2913 (uint32_t) pte, opte, *pte));
2914 if (l2pte_valid(opte)) {
2915 cpu_dcache_wbinv_range(va, PAGE_SIZE);
2916 cpu_tlb_flushD_SE(va);
2920 l2b->l2b_occupancy++;
2922 *pte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL,
2923 VM_PROT_READ | VM_PROT_WRITE);
2924 if (flags & KENTER_CACHE)
2925 *pte |= pte_l2_s_cache_mode;
2926 if (flags & KENTER_USER)
2927 *pte |= L2_S_PROT_U;
2932 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2934 pmap_kenter_internal(va, pa, KENTER_CACHE);
2938 pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa)
2941 pmap_kenter_internal(va, pa, 0);
2945 pmap_kenter_user(vm_offset_t va, vm_paddr_t pa)
2948 pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER);
2950 * Call pmap_fault_fixup now, to make sure we'll have no exception
2951 * at the first use of the new address, or bad things will happen,
2952 * as we use one of these addresses in the exception handlers.
2954 pmap_fault_fixup(pmap_kernel(), va, VM_PROT_READ|VM_PROT_WRITE, 1);
2958 * remove a page rom the kernel pagetables
2961 pmap_kremove(vm_offset_t va)
2963 struct l2_bucket *l2b;
2964 pt_entry_t *pte, opte;
2966 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2969 KASSERT(l2b != NULL, ("No L2 Bucket"));
2970 pte = &l2b->l2b_kva[l2pte_index(va)];
2972 if (l2pte_valid(opte)) {
2973 cpu_dcache_wbinv_range(va, PAGE_SIZE);
2974 cpu_tlb_flushD_SE(va);
2982 * Used to map a range of physical addresses into kernel
2983 * virtual address space.
2985 * The value passed in '*virt' is a suggested virtual address for
2986 * the mapping. Architectures which can support a direct-mapped
2987 * physical to virtual region can return the appropriate address
2988 * within that region, leaving '*virt' unchanged. Other
2989 * architectures should map the pages starting at '*virt' and
2990 * update '*virt' with the first usable address after the mapped
2994 pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot)
2996 vm_offset_t sva = *virt;
2997 vm_offset_t va = sva;
2999 PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, "
3000 "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end,
3003 while (start < end) {
3004 pmap_kenter(va, start);
3013 pmap_wb_page(vm_page_t m)
3015 struct pv_entry *pv;
3017 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
3018 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, FALSE,
3019 (pv->pv_flags & PVF_WRITE) == 0);
3023 pmap_inv_page(vm_page_t m)
3025 struct pv_entry *pv;
3027 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
3028 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, TRUE, TRUE);
3031 * Add a list of wired pages to the kva
3032 * this routine is only used for temporary
3033 * kernel mappings that do not need to have
3034 * page modification or references recorded.
3035 * Note that old mappings are simply written
3036 * over. The page *must* be wired.
3039 pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
3043 for (i = 0; i < count; i++) {
3045 pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]),
3053 * this routine jerks page mappings from the
3054 * kernel -- it is meant only for temporary mappings.
3057 pmap_qremove(vm_offset_t va, int count)
3062 for (i = 0; i < count; i++) {
3065 pmap_inv_page(PHYS_TO_VM_PAGE(pa));
3074 * pmap_object_init_pt preloads the ptes for a given object
3075 * into the specified pmap. This eliminates the blast of soft
3076 * faults on process startup and immediately after an mmap.
3079 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3080 vm_pindex_t pindex, vm_size_t size)
3083 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
3084 KASSERT(object->type == OBJT_DEVICE,
3085 ("pmap_object_init_pt: non-device object"));
3090 * pmap_is_prefaultable:
3092 * Return whether or not the specified virtual address is elgible
3096 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3101 if (!pmap_get_pde_pte(pmap, addr, &pde, &pte))
3103 KASSERT(pte != NULL, ("Valid mapping but no pte ?"));
3110 * Fetch pointers to the PDE/PTE for the given pmap/VA pair.
3111 * Returns TRUE if the mapping exists, else FALSE.
3113 * NOTE: This function is only used by a couple of arm-specific modules.
3114 * It is not safe to take any pmap locks here, since we could be right
3115 * in the middle of debugging the pmap anyway...
3117 * It is possible for this routine to return FALSE even though a valid
3118 * mapping does exist. This is because we don't lock, so the metadata
3119 * state may be inconsistent.
3121 * NOTE: We can return a NULL *ptp in the case where the L1 pde is
3122 * a "section" mapping.
3125 pmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp)
3127 struct l2_dtable *l2;
3128 pd_entry_t *pl1pd, l1pd;
3132 if (pm->pm_l1 == NULL)
3136 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx];
3139 if (l1pte_section_p(l1pd)) {
3144 if (pm->pm_l2 == NULL)
3147 l2 = pm->pm_l2[L2_IDX(l1idx)];
3150 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3154 *ptp = &ptep[l2pte_index(va)];
3159 * Routine: pmap_remove_all
3161 * Removes this physical page from
3162 * all physical maps in which it resides.
3163 * Reflects back modify bits to the pager.
3166 * Original versions of this routine were very
3167 * inefficient because they iteratively called
3168 * pmap_remove (slow...)
3171 pmap_remove_all(vm_page_t m)
3174 pt_entry_t *ptep, pte;
3175 struct l2_bucket *l2b;
3176 boolean_t flush = FALSE;
3180 #if defined(PMAP_DEBUG)
3182 * XXX this makes pmap_page_protect(NONE) illegal for non-managed
3185 if (m->flags & PG_FICTITIOUS) {
3186 panic("pmap_page_protect: illegal for unmanaged page, va: 0x%x", VM_PAGE_TO_PHYS(m));
3190 if (TAILQ_EMPTY(&m->md.pv_list))
3192 curpm = vmspace_pmap(curproc->p_vmspace);
3193 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3194 if (flush == FALSE && (pv->pv_pmap == curpm ||
3195 pv->pv_pmap == pmap_kernel()))
3197 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
3198 KASSERT(l2b != NULL, ("No l2 bucket"));
3199 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
3202 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
3203 pmap_free_l2_bucket(pv->pv_pmap, l2b, 1);
3204 if (pv->pv_flags & PVF_WIRED)
3205 pv->pv_pmap->pm_stats.wired_count--;
3206 pv->pv_pmap->pm_stats.resident_count--;
3207 flags |= pv->pv_flags;
3208 pmap_nuke_pv(m, pv->pv_pmap, pv);
3209 pmap_free_pv_entry(pv);
3213 if (PV_BEEN_EXECD(flags))
3214 pmap_tlb_flushID(curpm);
3216 pmap_tlb_flushD(curpm);
3218 vm_page_flag_clear(m, PG_WRITEABLE);
3223 * Set the physical protection on the
3224 * specified range of this map as requested.
3227 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3229 struct l2_bucket *l2b;
3230 pt_entry_t *ptep, pte;
3231 vm_offset_t next_bucket;
3235 if ((prot & VM_PROT_READ) == 0) {
3237 pmap_remove(pm, sva, eva);
3242 if (prot & VM_PROT_WRITE) {
3244 * If this is a read->write transition, just ignore it and let
3245 * vm_fault() take care of it later.
3253 * OK, at this point, we know we're doing write-protect operation.
3254 * If the pmap is active, write-back the range.
3256 pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE);
3258 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1;
3261 vm_page_lock_queues();
3263 next_bucket = L2_NEXT_BUCKET(sva);
3264 if (next_bucket > eva)
3267 l2b = pmap_get_l2_bucket(pm, sva);
3273 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3275 while (sva < next_bucket) {
3276 if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) {
3280 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
3281 pte &= ~L2_S_PROT_W;
3286 f = pmap_modify_pv(pg, pm, sva,
3288 pmap_vac_me_harder(pg, pm, sva);
3291 f = PVF_REF | PVF_EXEC;
3297 if (PV_BEEN_EXECD(f))
3298 pmap_tlb_flushID_SE(pm, sva);
3300 if (PV_BEEN_REFD(f))
3301 pmap_tlb_flushD_SE(pm, sva);
3311 if (PV_BEEN_EXECD(flags))
3312 pmap_tlb_flushID(pm);
3314 if (PV_BEEN_REFD(flags))
3315 pmap_tlb_flushD(pm);
3317 vm_page_unlock_queues();
3324 * Insert the given physical page (p) at
3325 * the specified virtual address (v) in the
3326 * target physical map with the protection requested.
3328 * If specified, the page will be wired down, meaning
3329 * that the related pte can not be reclaimed.
3331 * NB: This is the only routine which MAY NOT lazy-evaluate
3332 * or lose information. That is, this routine must actually
3333 * insert this page into the given map NOW.
3337 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3341 vm_page_lock_queues();
3342 pmap_enter_locked(pmap, va, m, prot, wired);
3343 vm_page_unlock_queues();
3347 * The page queues and pmap must be locked.
3350 pmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3353 struct l2_bucket *l2b = NULL;
3354 struct vm_page *opg;
3355 struct pv_entry *pve = NULL;
3356 pt_entry_t *ptep, npte, opte;
3361 PMAP_ASSERT_LOCKED(pmap);
3362 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3363 if (va == vector_page) {
3364 pa = systempage.pv_pa;
3367 pa = VM_PAGE_TO_PHYS(m);
3369 if (prot & VM_PROT_WRITE)
3370 nflags |= PVF_WRITE;
3371 if (prot & VM_PROT_EXECUTE)
3374 nflags |= PVF_WIRED;
3375 PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, "
3376 "wired = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, wired));
3378 if (pmap == pmap_kernel()) {
3379 l2b = pmap_get_l2_bucket(pmap, va);
3381 l2b = pmap_grow_l2_bucket(pmap, va);
3383 l2b = pmap_alloc_l2_bucket(pmap, va);
3384 KASSERT(l2b != NULL,
3385 ("pmap_enter: failed to allocate l2 bucket"));
3386 ptep = &l2b->l2b_kva[l2pte_index(va)];
3393 * There is already a mapping at this address.
3394 * If the physical address is different, lookup the
3397 if (l2pte_pa(opte) != pa)
3398 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte));
3404 if ((prot & (VM_PROT_ALL)) ||
3405 (!m || m->md.pvh_attrs & PVF_REF)) {
3407 * - The access type indicates that we don't need
3408 * to do referenced emulation.
3410 * - The physical page has already been referenced
3411 * so no need to re-do referenced emulation here.
3417 if (m && ((prot & VM_PROT_WRITE) != 0 ||
3418 (m->md.pvh_attrs & PVF_MOD))) {
3420 * This is a writable mapping, and the
3421 * page's mod state indicates it has
3422 * already been modified. Make it
3423 * writable from the outset.
3426 if (!(m->md.pvh_attrs & PVF_MOD))
3430 vm_page_flag_set(m, PG_REFERENCED);
3433 * Need to do page referenced emulation.
3435 npte |= L2_TYPE_INV;
3438 if (prot & VM_PROT_WRITE)
3439 npte |= L2_S_PROT_W;
3440 npte |= pte_l2_s_cache_mode;
3441 if (m && m == opg) {
3443 * We're changing the attrs of an existing mapping.
3446 simple_lock(&pg->mdpage.pvh_slock);
3448 oflags = pmap_modify_pv(m, pmap, va,
3449 PVF_WRITE | PVF_EXEC | PVF_WIRED |
3450 PVF_MOD | PVF_REF, nflags);
3452 simple_unlock(&pg->mdpage.pvh_slock);
3456 * We may need to flush the cache if we're
3459 if (pmap_is_current(pmap) &&
3460 (oflags & PVF_NC) == 0 &&
3461 (opte & L2_S_PROT_W) != 0 &&
3462 (prot & VM_PROT_WRITE) == 0)
3463 cpu_dcache_wb_range(va, PAGE_SIZE);
3466 * New mapping, or changing the backing page
3467 * of an existing mapping.
3471 * Replacing an existing mapping with a new one.
3472 * It is part of our managed memory so we
3473 * must remove it from the PV list
3476 simple_lock(&opg->mdpage.pvh_slock);
3478 pve = pmap_remove_pv(opg, pmap, va);
3479 if (m && (m->flags & (PG_UNMANAGED | PG_FICTITIOUS)) &&
3481 pmap_free_pv_entry(pve);
3483 !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS)))
3484 pve = pmap_get_pv_entry();
3485 KASSERT(pve != NULL, ("No pv"));
3487 simple_unlock(&opg->mdpage.pvh_slock);
3489 oflags = pve->pv_flags;
3492 * If the old mapping was valid (ref/mod
3493 * emulation creates 'invalid' mappings
3494 * initially) then make sure to frob
3497 if ((oflags & PVF_NC) == 0 &&
3498 l2pte_valid(opte)) {
3499 if (PV_BEEN_EXECD(oflags)) {
3500 pmap_idcache_wbinv_range(pmap, va,
3503 if (PV_BEEN_REFD(oflags)) {
3504 pmap_dcache_wb_range(pmap, va,
3506 (oflags & PVF_WRITE) == 0);
3509 } else if (m && !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS)))
3510 if ((pve = pmap_get_pv_entry()) == NULL) {
3511 panic("pmap_enter: no pv entries");
3513 if (m && !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS))) {
3514 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3515 ("pmap_enter: managed mapping within the clean submap"));
3516 pmap_enter_pv(m, pve, pmap, va, nflags);
3520 * Make sure userland mappings get the right permissions
3522 if (pmap != pmap_kernel() && va != vector_page) {
3523 npte |= L2_S_PROT_U;
3527 * Keep the stats up to date
3530 l2b->l2b_occupancy++;
3531 pmap->pm_stats.resident_count++;
3536 * If this is just a wiring change, the two PTEs will be
3537 * identical, so there's no need to update the page table.
3540 boolean_t is_cached = pmap_is_current(pmap);
3545 * We only need to frob the cache/tlb if this pmap
3549 if (L1_IDX(va) != L1_IDX(vector_page) &&
3550 l2pte_valid(npte)) {
3552 * This mapping is likely to be accessed as
3553 * soon as we return to userland. Fix up the
3554 * L1 entry to avoid taking another
3555 * page/domain fault.
3557 pd_entry_t *pl1pd, l1pd;
3559 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
3560 l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) |
3562 if (*pl1pd != l1pd) {
3569 if (PV_BEEN_EXECD(oflags))
3570 pmap_tlb_flushID_SE(pmap, va);
3571 else if (PV_BEEN_REFD(oflags))
3572 pmap_tlb_flushD_SE(pmap, va);
3576 pmap_vac_me_harder(m, pmap, va);
3581 * Maps a sequence of resident pages belonging to the same object.
3582 * The sequence begins with the given page m_start. This page is
3583 * mapped at the given virtual address start. Each subsequent page is
3584 * mapped at a virtual address that is offset from start by the same
3585 * amount as the page is offset from m_start within the object. The
3586 * last page in the sequence is the page with the largest offset from
3587 * m_start that can be mapped at a virtual address less than the given
3588 * virtual address end. Not every virtual page between start and end
3589 * is mapped; only those for which a resident page exists with the
3590 * corresponding offset from m_start are mapped.
3593 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3594 vm_page_t m_start, vm_prot_t prot)
3597 vm_pindex_t diff, psize;
3599 psize = atop(end - start);
3602 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3603 pmap_enter_locked(pmap, start + ptoa(diff), m, prot &
3604 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
3605 m = TAILQ_NEXT(m, listq);
3611 * this code makes some *MAJOR* assumptions:
3612 * 1. Current pmap & pmap exists.
3615 * 4. No page table pages.
3616 * but is *MUCH* faster than pmap_enter...
3620 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3625 pmap_enter_locked(pmap, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
3632 * Routine: pmap_change_wiring
3633 * Function: Change the wiring attribute for a map/virtual-address
3635 * In/out conditions:
3636 * The mapping must already exist in the pmap.
3639 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
3641 struct l2_bucket *l2b;
3642 pt_entry_t *ptep, pte;
3646 l2b = pmap_get_l2_bucket(pmap, va);
3647 KASSERT(l2b, ("No l2b bucket in pmap_change_wiring"));
3648 ptep = &l2b->l2b_kva[l2pte_index(va)];
3650 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
3652 pmap_modify_pv(pg, pmap, va, PVF_WIRED, wired);
3658 * Copy the range specified by src_addr/len
3659 * from the source map to the range dst_addr/len
3660 * in the destination map.
3662 * This routine is only advisory and need not do anything.
3665 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
3666 vm_size_t len, vm_offset_t src_addr)
3672 * Routine: pmap_extract
3674 * Extract the physical page address associated
3675 * with the given map/virtual_address pair.
3678 pmap_extract(pmap_t pm, vm_offset_t va)
3680 struct l2_dtable *l2;
3681 pd_entry_t *pl1pd, l1pd;
3682 pt_entry_t *ptep, pte;
3686 pl1pd = &pm->pm_l1->l1_kva[l1idx];
3689 if (l1pte_section_p(l1pd)) {
3691 * These should only happen for pmap_kernel()
3693 KASSERT(pm == pmap_kernel(), ("huh"));
3694 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3697 * Note that we can't rely on the validity of the L1
3698 * descriptor as an indication that a mapping exists.
3699 * We have to look it up in the L2 dtable.
3701 l2 = pm->pm_l2[L2_IDX(l1idx)];
3704 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3708 ptep = &ptep[l2pte_index(va)];
3714 switch (pte & L2_TYPE_MASK) {
3716 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3720 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3729 * Atomically extract and hold the physical page with the given
3730 * pmap and virtual address pair if that mapping permits the given
3735 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3737 struct l2_dtable *l2;
3738 pd_entry_t *pl1pd, l1pd;
3739 pt_entry_t *ptep, pte;
3744 pl1pd = &pmap->pm_l1->l1_kva[l1idx];
3747 vm_page_lock_queues();
3749 if (l1pte_section_p(l1pd)) {
3751 * These should only happen for pmap_kernel()
3753 KASSERT(pmap == pmap_kernel(), ("huh"));
3754 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3755 if (l1pd & L1_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3756 m = PHYS_TO_VM_PAGE(pa);
3762 * Note that we can't rely on the validity of the L1
3763 * descriptor as an indication that a mapping exists.
3764 * We have to look it up in the L2 dtable.
3766 l2 = pmap->pm_l2[L2_IDX(l1idx)];
3769 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3771 vm_page_unlock_queues();
3775 ptep = &ptep[l2pte_index(va)];
3780 vm_page_unlock_queues();
3783 if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3784 switch (pte & L2_TYPE_MASK) {
3786 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3790 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3793 m = PHYS_TO_VM_PAGE(pa);
3799 vm_page_unlock_queues();
3804 * Initialize a preallocated and zeroed pmap structure,
3805 * such as one in a vmspace structure.
3809 pmap_pinit(pmap_t pmap)
3811 PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap));
3813 PMAP_LOCK_INIT(pmap);
3814 pmap_alloc_l1(pmap);
3815 bzero(pmap->pm_l2, sizeof(pmap->pm_l2));
3818 pmap->pm_active = 0;
3820 TAILQ_INIT(&pmap->pm_pvlist);
3821 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3822 pmap->pm_stats.resident_count = 1;
3823 if (vector_page < KERNBASE) {
3824 pmap_enter(pmap, vector_page, PHYS_TO_VM_PAGE(systempage.pv_pa),
3830 /***************************************************
3831 * page management routines.
3832 ***************************************************/
3836 pmap_free_pv_entry(pv_entry_t pv)
3839 uma_zfree(pvzone, pv);
3844 * get a new pv_entry, allocating a block from the system
3846 * the memory allocation is performed bypassing the malloc code
3847 * because of the possibility of allocations at interrupt time.
3850 pmap_get_pv_entry(void)
3852 pv_entry_t ret_value;
3855 if ((pv_entry_count > pv_entry_high_water) &&
3856 (pmap_pagedaemon_waken == 0)) {
3857 pmap_pagedaemon_waken = 1;
3858 wakeup (&vm_pages_needed);
3860 ret_value = uma_zalloc(pvzone, M_NOWAIT);
3866 * Remove the given range of addresses from the specified map.
3868 * It is assumed that the start and end are properly
3869 * rounded to the page size.
3871 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3
3873 pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva)
3875 struct l2_bucket *l2b;
3876 vm_offset_t next_bucket;
3878 u_int cleanlist_idx, total, cnt;
3882 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE];
3883 u_int mappings, is_exec, is_refd;
3888 * we lock in the pmap => pv_head direction
3891 PMAP_MAP_TO_HEAD_LOCK();
3892 pmap_acquire_pmap_lock(pm);
3895 vm_page_lock_queues();
3896 if (!pmap_is_current(pm)) {
3897 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1;
3904 * Do one L2 bucket's worth at a time.
3906 next_bucket = L2_NEXT_BUCKET(sva);
3907 if (next_bucket > eva)
3910 l2b = pmap_get_l2_bucket(pm, sva);
3916 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3919 while (sva < next_bucket) {
3928 * Nothing here, move along
3935 pm->pm_stats.resident_count--;
3941 * Update flags. In a number of circumstances,
3942 * we could cluster a lot of these and do a
3943 * number of sequential pages in one go.
3945 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) {
3946 struct pv_entry *pve;
3948 simple_lock(&pg->mdpage.pvh_slock);
3950 pve = pmap_remove_pv(pg, pm, sva);
3953 simple_unlock(&pg->mdpage.pvh_slock);
3956 PV_BEEN_EXECD(pve->pv_flags);
3958 PV_BEEN_REFD(pve->pv_flags);
3959 pmap_free_pv_entry(pve);
3963 if (!l2pte_valid(pte)) {
3965 PTE_SYNC_CURRENT(pm, ptep);
3972 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) {
3973 /* Add to the clean list. */
3974 cleanlist[cleanlist_idx].pte = ptep;
3975 cleanlist[cleanlist_idx].va =
3976 sva | (is_exec & 1);
3979 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) {
3980 /* Nuke everything if needed. */
3981 pmap_idcache_wbinv_all(pm);
3982 pmap_tlb_flushID(pm);
3985 * Roll back the previous PTE list,
3986 * and zero out the current PTE.
3989 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) {
3990 *cleanlist[cnt].pte = 0;
4000 pmap_tlb_flushID_SE(pm, sva);
4003 pmap_tlb_flushD_SE(pm, sva);
4012 * Deal with any left overs
4014 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) {
4015 total += cleanlist_idx;
4016 for (cnt = 0; cnt < cleanlist_idx; cnt++) {
4018 cleanlist[cnt].va & ~1;
4019 if (cleanlist[cnt].va & 1) {
4020 pmap_idcache_wbinv_range(pm,
4022 pmap_tlb_flushID_SE(pm, clva);
4024 pmap_dcache_wb_range(pm,
4025 clva, PAGE_SIZE, TRUE,
4027 pmap_tlb_flushD_SE(pm, clva);
4029 *cleanlist[cnt].pte = 0;
4030 PTE_SYNC_CURRENT(pm, cleanlist[cnt].pte);
4033 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE)
4037 * We are removing so much entries it's just
4038 * easier to flush the whole cache.
4040 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1;
4041 pmap_idcache_wbinv_all(pm);
4046 pmap_free_l2_bucket(pm, l2b, mappings);
4049 vm_page_unlock_queues();
4053 pmap_release_pmap_lock(pm);
4054 PMAP_MAP_TO_HEAD_UNLOCK();
4064 * Zero a given physical page by mapping it at a page hook point.
4065 * In doing the zero page op, the page we zero is mapped cachable, as with
4066 * StrongARM accesses to non-cached pages are non-burst making writing
4067 * _any_ bulk data very slow.
4069 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
4071 pmap_zero_page_generic(vm_paddr_t phys, int off, int size)
4074 struct vm_page *pg = PHYS_TO_VM_PAGE(phys);
4076 if (pg->md.pvh_list != NULL)
4077 panic("pmap_zero_page: page has mappings");
4081 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0)
4087 * Hook in the page, zero it, and purge the cache for that
4088 * zeroed page. Invalidate the TLB as needed.
4090 *cdst_pte = L2_S_PROTO | phys |
4091 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
4093 cpu_tlb_flushD_SE(cdstp);
4095 if (off || size != PAGE_SIZE)
4096 bzero((void *)(cdstp + off), size);
4100 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE);
4102 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
4104 #if ARM_MMU_XSCALE == 1
4106 pmap_zero_page_xscale(vm_paddr_t phys, int off, int size)
4110 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0)
4114 * Hook in the page, zero it, and purge the cache for that
4115 * zeroed page. Invalidate the TLB as needed.
4117 *cdst_pte = L2_S_PROTO | phys |
4118 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4119 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4121 cpu_tlb_flushD_SE(cdstp);
4123 if (off || size != PAGE_SIZE)
4124 bzero((void *)(cdstp + off), size);
4128 xscale_cache_clean_minidata();
4132 * Change the PTEs for the specified kernel mappings such that they
4133 * will use the mini data cache instead of the main data cache.
4136 pmap_use_minicache(vm_offset_t va, vm_size_t size)
4138 struct l2_bucket *l2b;
4139 pt_entry_t *ptep, *sptep, pte;
4140 vm_offset_t next_bucket, eva;
4143 if (xscale_use_minidata == 0)
4150 next_bucket = L2_NEXT_BUCKET(va);
4151 if (next_bucket > eva)
4154 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
4156 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)];
4158 while (va < next_bucket) {
4160 if (!l2pte_minidata(pte)) {
4161 cpu_dcache_wbinv_range(va, PAGE_SIZE);
4162 cpu_tlb_flushD_SE(va);
4163 *ptep = pte & ~L2_B;
4168 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep));
4172 #endif /* ARM_MMU_XSCALE == 1 */
4175 * pmap_zero_page zeros the specified hardware page by mapping
4176 * the page into KVM and using bzero to clear its contents.
4179 pmap_zero_page(vm_page_t m)
4181 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), 0, PAGE_SIZE);
4186 * pmap_zero_page_area zeros the specified hardware page by mapping
4187 * the page into KVM and using bzero to clear its contents.
4189 * off and size may not cover an area beyond a single hardware page.
4192 pmap_zero_page_area(vm_page_t m, int off, int size)
4195 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), off, size);
4200 * pmap_zero_page_idle zeros the specified hardware page by mapping
4201 * the page into KVM and using bzero to clear its contents. This
4202 * is intended to be called from the vm_pagezero process only and
4206 pmap_zero_page_idle(vm_page_t m)
4216 * This is a local function used to work out the best strategy to clean
4217 * a single page referenced by its entry in the PV table. It's used by
4218 * pmap_copy_page, pmap_zero page and maybe some others later on.
4220 * Its policy is effectively:
4221 * o If there are no mappings, we don't bother doing anything with the cache.
4222 * o If there is one mapping, we clean just that page.
4223 * o If there are multiple mappings, we clean the entire cache.
4225 * So that some functions can be further optimised, it returns 0 if it didn't
4226 * clean the entire cache, or 1 if it did.
4228 * XXX One bug in this routine is that if the pv_entry has a single page
4229 * mapped at 0x00000000 a whole cache clean will be performed rather than
4230 * just the 1 page. Since this should not occur in everyday use and if it does
4231 * it will just result in not the most efficient clean for the page.
4234 pmap_clean_page(struct pv_entry *pv, boolean_t is_src)
4236 pmap_t pm, pm_to_clean = NULL;
4237 struct pv_entry *npv;
4238 u_int cache_needs_cleaning = 0;
4240 vm_offset_t page_to_clean = 0;
4243 /* nothing mapped in so nothing to flush */
4248 * Since we flush the cache each time we change to a different
4249 * user vmspace, we only need to flush the page if it is in the
4253 pm = vmspace_pmap(curproc->p_vmspace);
4257 for (npv = pv; npv; npv = TAILQ_NEXT(npv, pv_list)) {
4258 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) {
4259 flags |= npv->pv_flags;
4261 * The page is mapped non-cacheable in
4262 * this map. No need to flush the cache.
4264 if (npv->pv_flags & PVF_NC) {
4266 if (cache_needs_cleaning)
4267 panic("pmap_clean_page: "
4268 "cache inconsistency");
4271 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0)
4273 if (cache_needs_cleaning) {
4277 page_to_clean = npv->pv_va;
4278 pm_to_clean = npv->pv_pmap;
4280 cache_needs_cleaning = 1;
4283 if (page_to_clean) {
4284 if (PV_BEEN_EXECD(flags))
4285 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean,
4288 pmap_dcache_wb_range(pm_to_clean, page_to_clean,
4289 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0);
4290 } else if (cache_needs_cleaning) {
4291 if (PV_BEEN_EXECD(flags))
4292 pmap_idcache_wbinv_all(pm);
4294 pmap_dcache_wbinv_all(pm);
4302 * pmap_copy_page copies the specified (machine independent)
4303 * page by mapping the page into virtual memory and using
4304 * bcopy to copy the page, one machine dependent page at a
4311 * Copy one physical page into another, by mapping the pages into
4312 * hook points. The same comment regarding cachability as in
4313 * pmap_zero_page also applies here.
4315 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
4317 pmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst)
4320 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4323 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst);
4325 if (dst_pg->md.pvh_list != NULL)
4326 panic("pmap_copy_page: dst page has mappings");
4331 * Clean the source page. Hold the source page's lock for
4332 * the duration of the copy so that no other mappings can
4333 * be created while we have a potentially aliased mapping.
4336 mtx_lock(&src_pg->md.pvh_mtx);
4340 * XXX: Not needed while we call cpu_dcache_wbinv_all() in
4343 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4346 * Map the pages into the page hook points, copy them, and purge
4347 * the cache for the appropriate page. Invalidate the TLB
4351 *csrc_pte = L2_S_PROTO | src |
4352 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
4354 *cdst_pte = L2_S_PROTO | dst |
4355 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
4357 cpu_tlb_flushD_SE(csrcp);
4358 cpu_tlb_flushD_SE(cdstp);
4360 bcopy_page(csrcp, cdstp);
4362 cpu_dcache_inv_range(csrcp, PAGE_SIZE);
4364 mtx_lock(&src_pg->md.pvh_mtx);
4366 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE);
4368 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
4370 #if ARM_MMU_XSCALE == 1
4372 pmap_copy_page_xscale(vm_paddr_t src, vm_paddr_t dst)
4375 /* XXX: Only needed for pmap_clean_page(), which is commented out. */
4376 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4379 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst);
4381 if (dst_pg->md.pvh_list != NULL)
4382 panic("pmap_copy_page: dst page has mappings");
4387 * Clean the source page. Hold the source page's lock for
4388 * the duration of the copy so that no other mappings can
4389 * be created while we have a potentially aliased mapping.
4393 * XXX: Not needed while we call cpu_dcache_wbinv_all() in
4396 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4399 * Map the pages into the page hook points, copy them, and purge
4400 * the cache for the appropriate page. Invalidate the TLB
4404 *csrc_pte = L2_S_PROTO | src |
4405 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
4406 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4408 *cdst_pte = L2_S_PROTO | dst |
4409 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4410 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4412 cpu_tlb_flushD_SE(csrcp);
4413 cpu_tlb_flushD_SE(cdstp);
4415 bcopy_page(csrcp, cdstp);
4417 xscale_cache_clean_minidata();
4419 #endif /* ARM_MMU_XSCALE == 1 */
4422 pmap_copy_page(vm_page_t src, vm_page_t dst)
4424 cpu_dcache_wbinv_all();
4426 _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst),
4427 (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0)
4429 pmap_copy_page_func(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst));
4436 * this routine returns true if a physical page resides
4437 * in the given pmap.
4440 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4446 if (m->flags & PG_FICTITIOUS)
4452 * Not found, check current mappings returning immediately
4454 for (pv = TAILQ_FIRST(&m->md.pv_list);
4456 pv = TAILQ_NEXT(pv, pv_list)) {
4457 if (pv->pv_pmap == pmap) {
4471 * pmap_ts_referenced:
4473 * Return the count of reference bits for a page, clearing all of them.
4476 pmap_ts_referenced(vm_page_t m)
4478 return (pmap_clearbit(m, PVF_REF));
4483 pmap_is_modified(vm_page_t m)
4486 if (m->md.pvh_attrs & PVF_MOD)
4494 * Clear the modify bits on the specified physical page.
4497 pmap_clear_modify(vm_page_t m)
4500 if (m->md.pvh_attrs & PVF_MOD)
4501 pmap_clearbit(m, PVF_MOD);
4506 * pmap_clear_reference:
4508 * Clear the reference bit on the specified physical page.
4511 pmap_clear_reference(vm_page_t m)
4514 if (m->md.pvh_attrs & PVF_REF)
4515 pmap_clearbit(m, PVF_REF);
4520 * perform the pmap work for mincore
4523 pmap_mincore(pmap_t pmap, vm_offset_t addr)
4525 printf("pmap_mincore()\n");
4532 pmap_addr_hint(vm_object_t obj, vm_offset_t addr, vm_size_t size)
4540 * Map a set of physical memory pages into the kernel virtual
4541 * address space. Return a pointer to where it is mapped. This
4542 * routine is intended to be used for mapping device memory,
4546 pmap_mapdev(vm_offset_t pa, vm_size_t size)
4548 vm_offset_t va, tmpva, offset;
4550 offset = pa & PAGE_MASK;
4551 size = roundup(size, PAGE_SIZE);
4555 va = kmem_alloc_nofault(kernel_map, size);
4557 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
4558 for (tmpva = va; size > 0;) {
4559 pmap_kenter_internal(tmpva, pa, 0);
4565 return ((void *)(va + offset));
4568 #define BOOTSTRAP_DEBUG
4573 * Create a single section mapping.
4576 pmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4577 int prot, int cache)
4579 pd_entry_t *pde = (pd_entry_t *) l1pt;
4582 KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2"));
4591 fl = pte_l1_s_cache_mode;
4595 fl = pte_l1_s_cache_mode_pt;
4599 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4600 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL);
4601 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4608 * Link the L2 page table specified by "pa" into the L1
4609 * page table at the slot for "va".
4612 pmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv)
4614 pd_entry_t *pde = (pd_entry_t *) l1pt, proto;
4615 u_int slot = va >> L1_S_SHIFT;
4617 #ifndef ARM32_NEW_VM_LAYOUT
4618 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0, ("blah"));
4619 KASSERT((l2pv->pv_pa & PAGE_MASK) == 0, ("ouin"));
4622 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO;
4624 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000);
4625 #ifdef ARM32_NEW_VM_LAYOUT
4626 PTE_SYNC(&pde[slot]);
4628 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400);
4629 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800);
4630 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00);
4631 PTE_SYNC_RANGE(&pde[slot + 0], 4);
4634 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list);
4642 * Create a single page mapping.
4645 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot,
4648 pd_entry_t *pde = (pd_entry_t *) l1pt;
4652 KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin"));
4661 fl = pte_l2_s_cache_mode;
4665 fl = pte_l2_s_cache_mode_pt;
4669 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4670 panic("pmap_map_entry: no L2 table for VA 0x%08x", va);
4672 #ifndef ARM32_NEW_VM_LAYOUT
4673 pte = (pt_entry_t *)
4674 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME);
4676 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4680 panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va);
4682 #ifndef ARM32_NEW_VM_LAYOUT
4683 pte[(va >> PAGE_SHIFT) & 0x3ff] =
4684 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl;
4685 PTE_SYNC(&pte[(va >> PAGE_SHIFT) & 0x3ff]);
4687 pte[l2pte_index(va)] =
4688 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl;
4689 PTE_SYNC(&pte[l2pte_index(va)]);
4696 * Map a chunk of memory using the most efficient mappings
4697 * possible (section. large page, small page) into the
4698 * provided L1 and L2 tables at the specified virtual address.
4701 pmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4702 vm_size_t size, int prot, int cache)
4704 pd_entry_t *pde = (pd_entry_t *) l1pt;
4705 pt_entry_t *pte, f1, f2s, f2l;
4709 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
4712 panic("pmap_map_chunk: no L1 table provided");
4714 #ifdef VERBOSE_INIT_ARM
4715 printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x "
4716 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache);
4728 f1 = pte_l1_s_cache_mode;
4729 f2l = pte_l2_l_cache_mode;
4730 f2s = pte_l2_s_cache_mode;
4734 f1 = pte_l1_s_cache_mode_pt;
4735 f2l = pte_l2_l_cache_mode_pt;
4736 f2s = pte_l2_s_cache_mode_pt;
4743 /* See if we can use a section mapping. */
4744 if (L1_S_MAPPABLE_P(va, pa, resid)) {
4745 #ifdef VERBOSE_INIT_ARM
4748 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4749 L1_S_PROT(PTE_KERNEL, prot) | f1 |
4750 L1_S_DOM(PMAP_DOMAIN_KERNEL);
4751 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4759 * Ok, we're going to use an L2 table. Make sure
4760 * one is actually in the corresponding L1 slot
4761 * for the current VA.
4763 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4764 panic("pmap_map_chunk: no L2 table for VA 0x%08x", va);
4766 #ifndef ARM32_NEW_VM_LAYOUT
4767 pte = (pt_entry_t *)
4768 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME);
4770 pte = (pt_entry_t *) kernel_pt_lookup(
4771 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4774 panic("pmap_map_chunk: can't find L2 table for VA"
4776 /* See if we can use a L2 large page mapping. */
4777 if (L2_L_MAPPABLE_P(va, pa, resid)) {
4778 #ifdef VERBOSE_INIT_ARM
4781 for (i = 0; i < 16; i++) {
4782 #ifndef ARM32_NEW_VM_LAYOUT
4783 pte[((va >> PAGE_SHIFT) & 0x3f0) + i] =
4785 L2_L_PROT(PTE_KERNEL, prot) | f2l;
4786 PTE_SYNC(&pte[((va >> PAGE_SHIFT) & 0x3f0) + i]);
4788 pte[l2pte_index(va) + i] =
4790 L2_L_PROT(PTE_KERNEL, prot) | f2l;
4791 PTE_SYNC(&pte[l2pte_index(va) + i]);
4800 /* Use a small page mapping. */
4801 #ifdef VERBOSE_INIT_ARM
4804 #ifndef ARM32_NEW_VM_LAYOUT
4805 pte[(va >> PAGE_SHIFT) & 0x3ff] =
4806 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s;
4807 PTE_SYNC(&pte[(va >> PAGE_SHIFT) & 0x3ff]);
4809 pte[l2pte_index(va)] =
4810 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s;
4811 PTE_SYNC(&pte[l2pte_index(va)]);
4817 #ifdef VERBOSE_INIT_ARM
4824 /********************** Static device map routines ***************************/
4826 static const struct pmap_devmap *pmap_devmap_table;
4829 * Register the devmap table. This is provided in case early console
4830 * initialization needs to register mappings created by bootstrap code
4831 * before pmap_devmap_bootstrap() is called.
4834 pmap_devmap_register(const struct pmap_devmap *table)
4837 pmap_devmap_table = table;
4841 * Map all of the static regions in the devmap table, and remember
4842 * the devmap table so other parts of the kernel can look up entries
4846 pmap_devmap_bootstrap(vm_offset_t l1pt, const struct pmap_devmap *table)
4850 pmap_devmap_table = table;
4852 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
4853 #ifdef VERBOSE_INIT_ARM
4854 printf("devmap: %08x -> %08x @ %08x\n",
4855 pmap_devmap_table[i].pd_pa,
4856 pmap_devmap_table[i].pd_pa +
4857 pmap_devmap_table[i].pd_size - 1,
4858 pmap_devmap_table[i].pd_va);
4860 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va,
4861 pmap_devmap_table[i].pd_pa,
4862 pmap_devmap_table[i].pd_size,
4863 pmap_devmap_table[i].pd_prot,
4864 pmap_devmap_table[i].pd_cache);
4868 const struct pmap_devmap *
4869 pmap_devmap_find_pa(vm_paddr_t pa, vm_size_t size)
4873 if (pmap_devmap_table == NULL)
4876 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
4877 if (pa >= pmap_devmap_table[i].pd_pa &&
4878 pa + size <= pmap_devmap_table[i].pd_pa +
4879 pmap_devmap_table[i].pd_size)
4880 return (&pmap_devmap_table[i]);
4886 const struct pmap_devmap *
4887 pmap_devmap_find_va(vm_offset_t va, vm_size_t size)
4891 if (pmap_devmap_table == NULL)
4894 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
4895 if (va >= pmap_devmap_table[i].pd_va &&
4896 va + size <= pmap_devmap_table[i].pd_va +
4897 pmap_devmap_table[i].pd_size)
4898 return (&pmap_devmap_table[i]);