2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * Performance Monitoring Unit
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
38 #include "opt_hwpmc_hooks.h"
39 #include "opt_platform.h"
41 #include <sys/param.h>
42 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #include <sys/module.h>
46 #include <sys/malloc.h>
48 #include <sys/timeet.h>
49 #include <sys/timetc.h>
51 #include <sys/pmckern.h>
54 #include <dev/ofw/openfirm.h>
55 #include <dev/ofw/ofw_bus.h>
56 #include <dev/ofw/ofw_bus_subr.h>
59 #include <machine/bus.h>
60 #include <machine/cpu.h>
61 #include <machine/intr.h>
73 struct pmu_intr irq[MAX_RLEN];
79 uint32_t ccnt_hi[MAXCPU];
82 #define PMU_OVSR_C 0x80000000 /* Cycle Counter */
83 #define PMU_IESR_C 0x80000000 /* Cycle Counter */
92 #if defined(__arm__) && (__ARM_ARCH > 6)
95 cpu = PCPU_GET(cpuid);
97 r = cp15_pmovsr_get();
99 atomic_add_32(&ccnt_hi[cpu], 1);
100 /* Clear the event. */
102 cp15_pmovsr_set(PMU_OVSR_C);
109 /* Only call into the HWPMC framework if we know there is work. */
110 if (r != 0 && pmc_intr) {
116 return (FILTER_HANDLED);
120 pmu_parse_affinity(struct pmu_softc *sc, struct pmu_intr *irq, phandle_t xref,
128 err = OF_getencprop(OF_node_from_xref(xref), "reg", &mpidr,
131 device_printf(sc->dev, "missing 'reg' property\n");
136 for (i = 0; i < MAXCPU; i++) {
138 if (pcpu != NULL && pcpu->pc_mpidr == mpidr) {
144 device_printf(sc->dev, "Cannot find CPU with MPIDR: 0x%08X\n", mpidr);
149 pmu_parse_intr(struct pmu_softc *sc)
152 phandle_t node, *cpus;
153 int rid, err, ncpus, i;
156 node = ofw_bus_get_node(sc->dev);
157 has_affinity = OF_hasprop(node, "interrupt-affinity");
159 for (i = 0; i < MAX_RLEN; i++)
160 sc->irq[i].cpuid = -1;
164 ncpus = OF_getencprop_alloc_multi(node, "interrupt-affinity",
165 sizeof(*cpus), (void **)&cpus);
167 device_printf(sc->dev,
168 "Cannot read interrupt affinity property\n");
173 /* Process first interrupt */
175 sc->irq[0].res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &rid,
176 RF_ACTIVE | RF_SHAREABLE);
178 if (sc->irq[0].res == NULL) {
179 device_printf(sc->dev, "Cannot get interrupt\n");
184 /* Check if PMU have one per-CPU interrupt */
185 if (intr_is_per_cpu(sc->irq[0].res)) {
187 device_printf(sc->dev,
188 "Per CPU interupt have declared affinity\n");
196 * PMU with set of generic interrupts (one per core)
197 * Each one must be binded to exact core.
199 err = pmu_parse_affinity(sc, sc->irq + 0, has_affinity ? cpus[0]: 0,
202 device_printf(sc->dev, "Cannot parse affinity for CPUid: 0\n");
206 for (i = 1; i < MAX_RLEN; i++) {
208 sc->irq[i].res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
209 &rid, RF_ACTIVE | RF_SHAREABLE);
210 if (sc->irq[i].res == NULL)
213 if (intr_is_per_cpu(sc->irq[i].res))
215 device_printf(sc->dev, "Unexpected per CPU interupt\n");
220 if (has_affinity && i >= ncpus) {
221 device_printf(sc->dev, "Missing value in interrupt "
222 "affinity property\n");
227 err = pmu_parse_affinity(sc, sc->irq + i,
228 has_affinity ? cpus[i]: 0, i);
230 device_printf(sc->dev,
231 "Cannot parse affinity for CPUid: %d.\n", i);
242 pmu_attach(device_t dev)
244 struct pmu_softc *sc;
245 #if defined(__arm__) && (__ARM_ARCH > 6)
250 sc = device_get_softc(dev);
253 err = pmu_parse_intr(sc);
257 for (i = 0; i < MAX_RLEN; i++) {
258 if (sc->irq[i].res == NULL)
260 err = bus_setup_intr(dev, sc->irq[i].res,
261 INTR_MPSAFE | INTR_TYPE_MISC, pmu_intr, NULL, NULL,
265 "Unable to setup interrupt handler.\n");
268 if (sc->irq[i].cpuid != -1) {
269 err = bus_bind_intr(dev, sc->irq[i].res,
272 device_printf(sc->dev,
273 "Unable to bind interrupt.\n");
279 #if defined(__arm__) && (__ARM_ARCH > 6)
280 /* Initialize to 0. */
281 for (i = 0; i < MAXCPU; i++)
284 /* Enable the interrupt to fire on overflow. */
285 iesr = cp15_pminten_get();
287 cp15_pminten_set(iesr);
289 /* Need this for getcyclecount() fast path. */
296 for (i = 1; i < MAX_RLEN; i++) {
297 if (sc->irq[i].ih != NULL)
298 bus_teardown_intr(dev, sc->irq[i].res, sc->irq[i].ih);
299 if (sc->irq[i].res != NULL)
300 bus_release_resource(dev, SYS_RES_IRQ, i,
307 static struct ofw_compat_data compat_data[] = {
308 {"arm,armv8-pmuv3", 1},
309 {"arm,cortex-a77-pmu", 1},
310 {"arm,cortex-a76-pmu", 1},
311 {"arm,cortex-a75-pmu", 1},
312 {"arm,cortex-a73-pmu", 1},
313 {"arm,cortex-a72-pmu", 1},
314 {"arm,cortex-a65-pmu", 1},
315 {"arm,cortex-a57-pmu", 1},
316 {"arm,cortex-a55-pmu", 1},
317 {"arm,cortex-a53-pmu", 1},
318 {"arm,cortex-a34-pmu", 1},
320 {"arm,cortex-a17-pmu", 1},
321 {"arm,cortex-a15-pmu", 1},
322 {"arm,cortex-a12-pmu", 1},
323 {"arm,cortex-a9-pmu", 1},
324 {"arm,cortex-a8-pmu", 1},
325 {"arm,cortex-a7-pmu", 1},
326 {"arm,cortex-a5-pmu", 1},
327 {"arm,arm11mpcore-pmu", 1},
328 {"arm,arm1176-pmu", 1},
329 {"arm,arm1136-pmu", 1},
330 {"qcom,krait-pmu", 1},
335 pmu_fdt_probe(device_t dev)
338 if (!ofw_bus_status_okay(dev))
341 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
342 device_set_desc(dev, "Performance Monitoring Unit");
343 return (BUS_PROBE_DEFAULT);
349 static device_method_t pmu_fdt_methods[] = {
350 DEVMETHOD(device_probe, pmu_fdt_probe),
351 DEVMETHOD(device_attach, pmu_attach),
355 static driver_t pmu_fdt_driver = {
358 sizeof(struct pmu_softc),
361 static devclass_t pmu_fdt_devclass;
363 DRIVER_MODULE(pmu, simplebus, pmu_fdt_driver, pmu_fdt_devclass, 0, 0);