2 * Copyright (c) 2013 Ed Schouten <ed@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/stdatomic.h>
32 #include <sys/types.h>
34 #include <machine/atomic.h>
35 #include <machine/cpufunc.h>
36 #include <machine/sysarch.h>
39 * Executing statements with interrupts disabled.
42 #if defined(_KERNEL) && !defined(SMP)
43 #define WITHOUT_INTERRUPTS(s) do { \
46 regs = intr_disable(); \
50 #endif /* _KERNEL && !SMP */
55 * It turns out __sync_synchronize() does not emit any code when used
56 * with GCC 4.2. Implement our own version that does work reliably.
58 * Although __sync_lock_test_and_set() should only perform an acquire
59 * barrier, make it do a full barrier like the other functions. This
60 * should make <stdatomic.h>'s atomic_exchange_explicit() work reliably.
63 #if defined(_KERNEL) && !defined(SMP)
68 __asm volatile ("" : : : "memory");
79 #if defined(__CLANG_ATOMICS) || defined(__GNUC_ATOMICS)
82 * New C11 __atomic_* API.
85 /* ARMv6+ systems should be supported by the compiler. */
88 /* Clang doesn't allow us to reimplement builtins without this. */
90 #pragma redefine_extname __sync_synchronize_ext __sync_synchronize
91 #define __sync_synchronize __sync_synchronize_ext
95 __sync_synchronize(void)
102 #error "On SMP systems we should have proper atomic operations."
106 * On uniprocessor systems, we can perform the atomic operations by
107 * disabling interrupts.
110 #define EMIT_LOAD_N(N, uintN_t) \
112 __atomic_load_##N(uintN_t *mem, int model __unused) \
116 WITHOUT_INTERRUPTS({ \
122 #define EMIT_STORE_N(N, uintN_t) \
124 __atomic_store_##N(uintN_t *mem, uintN_t val, int model __unused) \
127 WITHOUT_INTERRUPTS({ \
132 #define EMIT_COMPARE_EXCHANGE_N(N, uintN_t) \
134 __atomic_compare_exchange_##N(uintN_t *mem, uintN_t *expected, \
135 uintN_t desired, int success __unused, int failure __unused) \
139 WITHOUT_INTERRUPTS({ \
140 if (*mem == *expected) { \
151 #define EMIT_FETCH_OP_N(N, uintN_t, name, op) \
153 __atomic_##name##_##N(uintN_t *mem, uintN_t val, int model __unused) \
157 WITHOUT_INTERRUPTS({ \
164 #define EMIT_ALL_OPS_N(N, uintN_t) \
165 EMIT_LOAD_N(N, uintN_t) \
166 EMIT_STORE_N(N, uintN_t) \
167 EMIT_COMPARE_EXCHANGE_N(N, uintN_t) \
168 EMIT_FETCH_OP_N(N, uintN_t, exchange, =) \
169 EMIT_FETCH_OP_N(N, uintN_t, fetch_add, +=) \
170 EMIT_FETCH_OP_N(N, uintN_t, fetch_and, &=) \
171 EMIT_FETCH_OP_N(N, uintN_t, fetch_or, |=) \
172 EMIT_FETCH_OP_N(N, uintN_t, fetch_sub, -=) \
173 EMIT_FETCH_OP_N(N, uintN_t, fetch_xor, ^=)
175 EMIT_ALL_OPS_N(1, uint8_t)
176 EMIT_ALL_OPS_N(2, uint16_t)
177 EMIT_ALL_OPS_N(4, uint32_t)
178 EMIT_ALL_OPS_N(8, uint64_t)
179 #undef EMIT_ALL_OPS_N
184 * For userspace on uniprocessor systems, we can implement the atomic
185 * operations by using a Restartable Atomic Sequence. This makes the
186 * kernel restart the code from the beginning when interrupted.
189 #define EMIT_LOAD_N(N, uintN_t) \
191 __atomic_load_##N(uintN_t *mem, int model __unused) \
197 #define EMIT_STORE_N(N, uintN_t) \
199 __atomic_store_##N(uintN_t *mem, uintN_t val, int model __unused) \
205 #define EMIT_EXCHANGE_N(N, uintN_t, ldr, str) \
207 __atomic_exchange_##N(uintN_t *mem, uintN_t val, int model __unused) \
209 uint32_t old, temp, ras_start; \
211 ras_start = ARM_RAS_START; \
213 /* Set up Restartable Atomic Sequence. */ \
218 "\tstr %2, [%5, #4]\n" \
220 "\t"ldr" %0, %4\n" /* Load old value. */ \
221 "\t"str" %3, %1\n" /* Store new value. */ \
223 /* Tear down Restartable Atomic Sequence. */ \
225 "\tmov %2, #0x00000000\n" \
227 "\tmov %2, #0xffffffff\n" \
228 "\tstr %2, [%5, #4]\n" \
229 : "=&r" (old), "=m" (*mem), "=&r" (temp) \
230 : "r" (val), "m" (*mem), "r" (ras_start)); \
234 #define EMIT_COMPARE_EXCHANGE_N(N, uintN_t, ldr, streq) \
236 __atomic_compare_exchange_##N(uintN_t *mem, uintN_t *pexpected, \
237 uintN_t desired, int success __unused, int failure __unused) \
239 uint32_t expected, old, temp, ras_start; \
241 expected = *pexpected; \
242 ras_start = ARM_RAS_START; \
244 /* Set up Restartable Atomic Sequence. */ \
249 "\tstr %2, [%6, #4]\n" \
251 "\t"ldr" %0, %5\n" /* Load old value. */ \
252 "\tcmp %0, %3\n" /* Compare to expected value. */\
253 "\t"streq" %4, %1\n" /* Store new value. */ \
255 /* Tear down Restartable Atomic Sequence. */ \
257 "\tmov %2, #0x00000000\n" \
259 "\tmov %2, #0xffffffff\n" \
260 "\tstr %2, [%6, #4]\n" \
261 : "=&r" (old), "=m" (*mem), "=&r" (temp) \
262 : "r" (expected), "r" (desired), "m" (*mem), \
264 if (old == expected) { \
272 #define EMIT_FETCH_OP_N(N, uintN_t, ldr, str, name, op, ret) \
274 __atomic_##name##_##N(uintN_t *mem, uintN_t val, int model __unused) \
276 uint32_t old, new, ras_start; \
278 ras_start = ARM_RAS_START; \
280 /* Set up Restartable Atomic Sequence. */ \
285 "\tstr %2, [%5, #4]\n" \
287 "\t"ldr" %0, %4\n" /* Load old value. */ \
288 "\t"op" %2, %0, %3\n" /* Calculate new value. */ \
289 "\t"str" %2, %1\n" /* Store new value. */ \
291 /* Tear down Restartable Atomic Sequence. */ \
293 "\tmov %2, #0x00000000\n" \
295 "\tmov %2, #0xffffffff\n" \
296 "\tstr %2, [%5, #4]\n" \
297 : "=&r" (old), "=m" (*mem), "=&r" (new) \
298 : "r" (val), "m" (*mem), "r" (ras_start)); \
302 #define EMIT_ALL_OPS_N(N, uintN_t, ldr, str, streq) \
303 EMIT_LOAD_N(N, uintN_t) \
304 EMIT_STORE_N(N, uintN_t) \
305 EMIT_EXCHANGE_N(N, uintN_t, ldr, str) \
306 EMIT_COMPARE_EXCHANGE_N(N, uintN_t, ldr, streq) \
307 EMIT_FETCH_OP_N(N, uintN_t, ldr, str, fetch_add, "add", old) \
308 EMIT_FETCH_OP_N(N, uintN_t, ldr, str, fetch_and, "and", old) \
309 EMIT_FETCH_OP_N(N, uintN_t, ldr, str, fetch_or, "orr", old) \
310 EMIT_FETCH_OP_N(N, uintN_t, ldr, str, fetch_sub, "sub", old) \
311 EMIT_FETCH_OP_N(N, uintN_t, ldr, str, fetch_xor, "eor", old) \
312 EMIT_FETCH_OP_N(N, uintN_t, ldr, str, add_fetch, "add", new) \
313 EMIT_FETCH_OP_N(N, uintN_t, ldr, str, and_fetch, "and", new) \
314 EMIT_FETCH_OP_N(N, uintN_t, ldr, str, or_fetch, "orr", new) \
315 EMIT_FETCH_OP_N(N, uintN_t, ldr, str, sub_fetch, "sub", new) \
316 EMIT_FETCH_OP_N(N, uintN_t, ldr, str, xor_fetch, "eor", new)
318 EMIT_ALL_OPS_N(1, uint8_t, "ldrb", "strb", "strbeq")
319 EMIT_ALL_OPS_N(2, uint16_t, "ldrh", "strh", "strheq")
320 EMIT_ALL_OPS_N(4, uint32_t, "ldr", "str", "streq")
321 #undef EMIT_ALL_OPS_N
325 #endif /* __ARM_ARCH */
327 #endif /* __CLANG_ATOMICS || __GNUC_ATOMICS */
329 #if defined(__SYNC_ATOMICS) || defined(EMIT_SYNC_ATOMICS)
332 #pragma redefine_extname __sync_lock_test_and_set_1_c __sync_lock_test_and_set_1
333 #pragma redefine_extname __sync_lock_test_and_set_2_c __sync_lock_test_and_set_2
334 #pragma redefine_extname __sync_lock_test_and_set_4_c __sync_lock_test_and_set_4
335 #pragma redefine_extname __sync_val_compare_and_swap_1_c __sync_val_compare_and_swap_1
336 #pragma redefine_extname __sync_val_compare_and_swap_2_c __sync_val_compare_and_swap_2
337 #pragma redefine_extname __sync_val_compare_and_swap_4_c __sync_val_compare_and_swap_4
338 #pragma redefine_extname __sync_fetch_and_add_1_c __sync_fetch_and_add_1
339 #pragma redefine_extname __sync_fetch_and_add_2_c __sync_fetch_and_add_2
340 #pragma redefine_extname __sync_fetch_and_add_4_c __sync_fetch_and_add_4
341 #pragma redefine_extname __sync_fetch_and_and_1_c __sync_fetch_and_and_1
342 #pragma redefine_extname __sync_fetch_and_and_2_c __sync_fetch_and_and_2
343 #pragma redefine_extname __sync_fetch_and_and_4_c __sync_fetch_and_and_4
344 #pragma redefine_extname __sync_fetch_and_or_1_c __sync_fetch_and_or_1
345 #pragma redefine_extname __sync_fetch_and_or_2_c __sync_fetch_and_or_2
346 #pragma redefine_extname __sync_fetch_and_or_4_c __sync_fetch_and_or_4
347 #pragma redefine_extname __sync_fetch_and_xor_1_c __sync_fetch_and_xor_1
348 #pragma redefine_extname __sync_fetch_and_xor_2_c __sync_fetch_and_xor_2
349 #pragma redefine_extname __sync_fetch_and_xor_4_c __sync_fetch_and_xor_4
350 #pragma redefine_extname __sync_fetch_and_sub_1_c __sync_fetch_and_sub_1
351 #pragma redefine_extname __sync_fetch_and_sub_2_c __sync_fetch_and_sub_2
352 #pragma redefine_extname __sync_fetch_and_sub_4_c __sync_fetch_and_sub_4
361 /* Implementations for old GCC versions, lacking support for atomics. */
369 * Given a memory address pointing to an 8-bit or 16-bit integer, return
370 * the address of the 32-bit word containing it.
373 static inline uint32_t *
374 round_to_word(void *ptr)
377 return ((uint32_t *)((intptr_t)ptr & ~3));
381 * Utility functions for loading and storing 8-bit and 16-bit integers
382 * in 32-bit words at an offset corresponding with the location of the
387 put_1(reg_t *r, const uint8_t *offset_ptr, uint8_t val)
391 offset = (intptr_t)offset_ptr & 3;
395 static inline uint8_t
396 get_1(const reg_t *r, const uint8_t *offset_ptr)
400 offset = (intptr_t)offset_ptr & 3;
401 return (r->v8[offset]);
405 put_2(reg_t *r, const uint16_t *offset_ptr, uint16_t val)
413 offset = (intptr_t)offset_ptr & 3;
415 r->v8[offset] = bytes.out[0];
416 r->v8[offset + 1] = bytes.out[1];
419 static inline uint16_t
420 get_2(const reg_t *r, const uint16_t *offset_ptr)
428 offset = (intptr_t)offset_ptr & 3;
429 bytes.in[0] = r->v8[offset];
430 bytes.in[1] = r->v8[offset + 1];
435 * 8-bit and 16-bit routines.
437 * These operations are not natively supported by the CPU, so we use
438 * some shifting and bitmasking on top of the 32-bit instructions.
441 #define EMIT_LOCK_TEST_AND_SET_N(N, uintN_t) \
443 __sync_lock_test_and_set_##N##_c(uintN_t *mem, uintN_t val) \
446 reg_t val32, negmask, old; \
447 uint32_t temp1, temp2; \
449 mem32 = round_to_word(mem); \
450 val32.v32 = 0x00000000; \
451 put_##N(&val32, mem, val); \
452 negmask.v32 = 0xffffffff; \
453 put_##N(&negmask, mem, 0); \
458 "\tldrex %0, %6\n" /* Load old value. */ \
459 "\tand %2, %5, %0\n" /* Remove the old value. */ \
460 "\torr %2, %2, %4\n" /* Put in the new value. */ \
461 "\tstrex %3, %2, %1\n" /* Attempt to store. */ \
462 "\tcmp %3, #0\n" /* Did it succeed? */ \
463 "\tbne 1b\n" /* Spin if failed. */ \
464 : "=&r" (old.v32), "=m" (*mem32), "=&r" (temp1), \
466 : "r" (val32.v32), "r" (negmask.v32), "m" (*mem32)); \
467 return (get_##N(&old, mem)); \
470 EMIT_LOCK_TEST_AND_SET_N(1, uint8_t)
471 EMIT_LOCK_TEST_AND_SET_N(2, uint16_t)
473 #define EMIT_VAL_COMPARE_AND_SWAP_N(N, uintN_t) \
475 __sync_val_compare_and_swap_##N##_c(uintN_t *mem, uintN_t expected, \
479 reg_t expected32, desired32, posmask, old; \
480 uint32_t negmask, temp1, temp2; \
482 mem32 = round_to_word(mem); \
483 expected32.v32 = 0x00000000; \
484 put_##N(&expected32, mem, expected); \
485 desired32.v32 = 0x00000000; \
486 put_##N(&desired32, mem, desired); \
487 posmask.v32 = 0x00000000; \
488 put_##N(&posmask, mem, ~0); \
489 negmask = ~posmask.v32; \
494 "\tldrex %0, %8\n" /* Load old value. */ \
495 "\tand %2, %6, %0\n" /* Isolate the old value. */ \
496 "\tcmp %2, %4\n" /* Compare to expected value. */\
497 "\tbne 2f\n" /* Values are unequal. */ \
498 "\tand %2, %7, %0\n" /* Remove the old value. */ \
499 "\torr %2, %5\n" /* Put in the new value. */ \
500 "\tstrex %3, %2, %1\n" /* Attempt to store. */ \
501 "\tcmp %3, #0\n" /* Did it succeed? */ \
502 "\tbne 1b\n" /* Spin if failed. */ \
504 : "=&r" (old), "=m" (*mem32), "=&r" (temp1), \
506 : "r" (expected32.v32), "r" (desired32.v32), \
507 "r" (posmask.v32), "r" (negmask), "m" (*mem32)); \
508 return (get_##N(&old, mem)); \
511 EMIT_VAL_COMPARE_AND_SWAP_N(1, uint8_t)
512 EMIT_VAL_COMPARE_AND_SWAP_N(2, uint16_t)
514 #define EMIT_ARITHMETIC_FETCH_AND_OP_N(N, uintN_t, name, op) \
516 __sync_##name##_##N##_c(uintN_t *mem, uintN_t val) \
519 reg_t val32, posmask, old; \
520 uint32_t negmask, temp1, temp2; \
522 mem32 = round_to_word(mem); \
523 val32.v32 = 0x00000000; \
524 put_##N(&val32, mem, val); \
525 posmask.v32 = 0x00000000; \
526 put_##N(&posmask, mem, ~0); \
527 negmask = ~posmask.v32; \
532 "\tldrex %0, %7\n" /* Load old value. */ \
533 "\t"op" %2, %0, %4\n" /* Calculate new value. */ \
534 "\tand %2, %5\n" /* Isolate the new value. */ \
535 "\tand %3, %6, %0\n" /* Remove the old value. */ \
536 "\torr %2, %2, %3\n" /* Put in the new value. */ \
537 "\tstrex %3, %2, %1\n" /* Attempt to store. */ \
538 "\tcmp %3, #0\n" /* Did it succeed? */ \
539 "\tbne 1b\n" /* Spin if failed. */ \
540 : "=&r" (old.v32), "=m" (*mem32), "=&r" (temp1), \
542 : "r" (val32.v32), "r" (posmask.v32), "r" (negmask), \
544 return (get_##N(&old, mem)); \
547 EMIT_ARITHMETIC_FETCH_AND_OP_N(1, uint8_t, fetch_and_add, "add")
548 EMIT_ARITHMETIC_FETCH_AND_OP_N(1, uint8_t, fetch_and_sub, "sub")
549 EMIT_ARITHMETIC_FETCH_AND_OP_N(2, uint16_t, fetch_and_add, "add")
550 EMIT_ARITHMETIC_FETCH_AND_OP_N(2, uint16_t, fetch_and_sub, "sub")
552 #define EMIT_BITWISE_FETCH_AND_OP_N(N, uintN_t, name, op, idempotence) \
554 __sync_##name##_##N##_c(uintN_t *mem, uintN_t val) \
558 uint32_t temp1, temp2; \
560 mem32 = round_to_word(mem); \
561 val32.v32 = idempotence ? 0xffffffff : 0x00000000; \
562 put_##N(&val32, mem, val); \
567 "\tldrex %0, %5\n" /* Load old value. */ \
568 "\t"op" %2, %4, %0\n" /* Calculate new value. */ \
569 "\tstrex %3, %2, %1\n" /* Attempt to store. */ \
570 "\tcmp %3, #0\n" /* Did it succeed? */ \
571 "\tbne 1b\n" /* Spin if failed. */ \
572 : "=&r" (old.v32), "=m" (*mem32), "=&r" (temp1), \
574 : "r" (val32.v32), "m" (*mem32)); \
575 return (get_##N(&old, mem)); \
578 EMIT_BITWISE_FETCH_AND_OP_N(1, uint8_t, fetch_and_and, "and", 1)
579 EMIT_BITWISE_FETCH_AND_OP_N(1, uint8_t, fetch_and_or, "orr", 0)
580 EMIT_BITWISE_FETCH_AND_OP_N(1, uint8_t, fetch_and_xor, "eor", 0)
581 EMIT_BITWISE_FETCH_AND_OP_N(2, uint16_t, fetch_and_and, "and", 1)
582 EMIT_BITWISE_FETCH_AND_OP_N(2, uint16_t, fetch_and_or, "orr", 0)
583 EMIT_BITWISE_FETCH_AND_OP_N(2, uint16_t, fetch_and_xor, "eor", 0)
590 __sync_lock_test_and_set_4_c(uint32_t *mem, uint32_t val)
597 "\tldrex %0, %4\n" /* Load old value. */
598 "\tstrex %2, %3, %1\n" /* Attempt to store. */
599 "\tcmp %2, #0\n" /* Did it succeed? */
600 "\tbne 1b\n" /* Spin if failed. */
601 : "=&r" (old), "=m" (*mem), "=&r" (temp)
602 : "r" (val), "m" (*mem));
607 __sync_val_compare_and_swap_4_c(uint32_t *mem, uint32_t expected,
615 "\tldrex %0, %5\n" /* Load old value. */
616 "\tcmp %0, %3\n" /* Compare to expected value. */
617 "\tbne 2f\n" /* Values are unequal. */
618 "\tstrex %2, %4, %1\n" /* Attempt to store. */
619 "\tcmp %2, #0\n" /* Did it succeed? */
620 "\tbne 1b\n" /* Spin if failed. */
622 : "=&r" (old), "=m" (*mem), "=&r" (temp)
623 : "r" (expected), "r" (desired), "m" (*mem));
627 #define EMIT_FETCH_AND_OP_4(name, op) \
629 __sync_##name##_4##_c(uint32_t *mem, uint32_t val) \
631 uint32_t old, temp1, temp2; \
636 "\tldrex %0, %5\n" /* Load old value. */ \
637 "\t"op" %2, %0, %4\n" /* Calculate new value. */ \
638 "\tstrex %3, %2, %1\n" /* Attempt to store. */ \
639 "\tcmp %3, #0\n" /* Did it succeed? */ \
640 "\tbne 1b\n" /* Spin if failed. */ \
641 : "=&r" (old), "=m" (*mem), "=&r" (temp1), \
643 : "r" (val), "m" (*mem)); \
647 EMIT_FETCH_AND_OP_4(fetch_and_add, "add")
648 EMIT_FETCH_AND_OP_4(fetch_and_and, "and")
649 EMIT_FETCH_AND_OP_4(fetch_and_or, "orr")
650 EMIT_FETCH_AND_OP_4(fetch_and_sub, "sub")
651 EMIT_FETCH_AND_OP_4(fetch_and_xor, "eor")
654 __strong_reference(__sync_lock_test_and_set_1_c, __sync_lock_test_and_set_1);
655 __strong_reference(__sync_lock_test_and_set_2_c, __sync_lock_test_and_set_2);
656 __strong_reference(__sync_lock_test_and_set_4_c, __sync_lock_test_and_set_4);
657 __strong_reference(__sync_val_compare_and_swap_1_c, __sync_val_compare_and_swap_1);
658 __strong_reference(__sync_val_compare_and_swap_2_c, __sync_val_compare_and_swap_2);
659 __strong_reference(__sync_val_compare_and_swap_4_c, __sync_val_compare_and_swap_4);
660 __strong_reference(__sync_fetch_and_add_1_c, __sync_fetch_and_add_1);
661 __strong_reference(__sync_fetch_and_add_2_c, __sync_fetch_and_add_2);
662 __strong_reference(__sync_fetch_and_add_4_c, __sync_fetch_and_add_4);
663 __strong_reference(__sync_fetch_and_and_1_c, __sync_fetch_and_and_1);
664 __strong_reference(__sync_fetch_and_and_2_c, __sync_fetch_and_and_2);
665 __strong_reference(__sync_fetch_and_and_4_c, __sync_fetch_and_and_4);
666 __strong_reference(__sync_fetch_and_sub_1_c, __sync_fetch_and_sub_1);
667 __strong_reference(__sync_fetch_and_sub_2_c, __sync_fetch_and_sub_2);
668 __strong_reference(__sync_fetch_and_sub_4_c, __sync_fetch_and_sub_4);
669 __strong_reference(__sync_fetch_and_or_1_c, __sync_fetch_and_or_1);
670 __strong_reference(__sync_fetch_and_or_2_c, __sync_fetch_and_or_2);
671 __strong_reference(__sync_fetch_and_or_4_c, __sync_fetch_and_or_4);
672 __strong_reference(__sync_fetch_and_xor_1_c, __sync_fetch_and_xor_1);
673 __strong_reference(__sync_fetch_and_xor_2_c, __sync_fetch_and_xor_2);
674 __strong_reference(__sync_fetch_and_xor_4_c, __sync_fetch_and_xor_4);
677 #else /* __ARM_ARCH < 6 */
682 #error "On SMP systems we should have proper atomic operations."
686 * On uniprocessor systems, we can perform the atomic operations by
687 * disabling interrupts.
690 #define EMIT_VAL_COMPARE_AND_SWAP_N(N, uintN_t) \
692 __sync_val_compare_and_swap_##N(uintN_t *mem, uintN_t expected, \
697 WITHOUT_INTERRUPTS({ \
699 if (*mem == expected) \
705 #define EMIT_FETCH_AND_OP_N(N, uintN_t, name, op) \
707 __sync_##name##_##N(uintN_t *mem, uintN_t val) \
711 WITHOUT_INTERRUPTS({ \
718 #define EMIT_ALL_OPS_N(N, uintN_t) \
719 EMIT_VAL_COMPARE_AND_SWAP_N(N, uintN_t) \
720 EMIT_FETCH_AND_OP_N(N, uintN_t, lock_test_and_set, =) \
721 EMIT_FETCH_AND_OP_N(N, uintN_t, fetch_and_add, +=) \
722 EMIT_FETCH_AND_OP_N(N, uintN_t, fetch_and_and, &=) \
723 EMIT_FETCH_AND_OP_N(N, uintN_t, fetch_and_or, |=) \
724 EMIT_FETCH_AND_OP_N(N, uintN_t, fetch_and_sub, -=) \
725 EMIT_FETCH_AND_OP_N(N, uintN_t, fetch_and_xor, ^=)
727 EMIT_ALL_OPS_N(1, uint8_t)
728 EMIT_ALL_OPS_N(2, uint16_t)
729 EMIT_ALL_OPS_N(4, uint32_t)
730 EMIT_ALL_OPS_N(8, uint64_t)
731 #undef EMIT_ALL_OPS_N
736 * For userspace on uniprocessor systems, we can implement the atomic
737 * operations by using a Restartable Atomic Sequence. This makes the
738 * kernel restart the code from the beginning when interrupted.
741 #define EMIT_LOCK_TEST_AND_SET_N(N, uintN_t, ldr, str) \
743 __sync_lock_test_and_set_##N##_c(uintN_t *mem, uintN_t val) \
745 uint32_t old, temp, ras_start; \
747 ras_start = ARM_RAS_START; \
749 /* Set up Restartable Atomic Sequence. */ \
754 "\tstr %2, [%5, #4]\n" \
756 "\t"ldr" %0, %4\n" /* Load old value. */ \
757 "\t"str" %3, %1\n" /* Store new value. */ \
759 /* Tear down Restartable Atomic Sequence. */ \
761 "\tmov %2, #0x00000000\n" \
763 "\tmov %2, #0xffffffff\n" \
764 "\tstr %2, [%5, #4]\n" \
765 : "=&r" (old), "=m" (*mem), "=&r" (temp) \
766 : "r" (val), "m" (*mem), "r" (ras_start)); \
770 #define EMIT_VAL_COMPARE_AND_SWAP_N(N, uintN_t, ldr, streq) \
772 __sync_val_compare_and_swap_##N##_c(uintN_t *mem, uintN_t expected, \
775 uint32_t old, temp, ras_start; \
777 ras_start = ARM_RAS_START; \
779 /* Set up Restartable Atomic Sequence. */ \
784 "\tstr %2, [%6, #4]\n" \
786 "\t"ldr" %0, %5\n" /* Load old value. */ \
787 "\tcmp %0, %3\n" /* Compare to expected value. */\
788 "\t"streq" %4, %1\n" /* Store new value. */ \
790 /* Tear down Restartable Atomic Sequence. */ \
792 "\tmov %2, #0x00000000\n" \
794 "\tmov %2, #0xffffffff\n" \
795 "\tstr %2, [%6, #4]\n" \
796 : "=&r" (old), "=m" (*mem), "=&r" (temp) \
797 : "r" (expected), "r" (desired), "m" (*mem), \
802 #define EMIT_FETCH_AND_OP_N(N, uintN_t, ldr, str, name, op) \
804 __sync_##name##_##N##_c(uintN_t *mem, uintN_t val) \
806 uint32_t old, temp, ras_start; \
808 ras_start = ARM_RAS_START; \
810 /* Set up Restartable Atomic Sequence. */ \
815 "\tstr %2, [%5, #4]\n" \
817 "\t"ldr" %0, %4\n" /* Load old value. */ \
818 "\t"op" %2, %0, %3\n" /* Calculate new value. */ \
819 "\t"str" %2, %1\n" /* Store new value. */ \
821 /* Tear down Restartable Atomic Sequence. */ \
823 "\tmov %2, #0x00000000\n" \
825 "\tmov %2, #0xffffffff\n" \
826 "\tstr %2, [%5, #4]\n" \
827 : "=&r" (old), "=m" (*mem), "=&r" (temp) \
828 : "r" (val), "m" (*mem), "r" (ras_start)); \
832 #define EMIT_ALL_OPS_N(N, uintN_t, ldr, str, streq) \
833 EMIT_LOCK_TEST_AND_SET_N(N, uintN_t, ldr, str) \
834 EMIT_VAL_COMPARE_AND_SWAP_N(N, uintN_t, ldr, streq) \
835 EMIT_FETCH_AND_OP_N(N, uintN_t, ldr, str, fetch_and_add, "add") \
836 EMIT_FETCH_AND_OP_N(N, uintN_t, ldr, str, fetch_and_and, "and") \
837 EMIT_FETCH_AND_OP_N(N, uintN_t, ldr, str, fetch_and_or, "orr") \
838 EMIT_FETCH_AND_OP_N(N, uintN_t, ldr, str, fetch_and_sub, "sub") \
839 EMIT_FETCH_AND_OP_N(N, uintN_t, ldr, str, fetch_and_xor, "eor")
842 EMIT_ALL_OPS_N(1, uint8_t, "ldrb", "strb", "strbeq")
843 EMIT_ALL_OPS_N(2, uint16_t, "ldrh", "strh", "strheq")
845 EMIT_ALL_OPS_N(1, uint8_t, "ldrb", "strb", "streqb")
846 EMIT_ALL_OPS_N(2, uint16_t, "ldrh", "strh", "streqh")
848 EMIT_ALL_OPS_N(4, uint32_t, "ldr", "str", "streq")
851 __strong_reference(__sync_lock_test_and_set_1_c, __sync_lock_test_and_set_1);
852 __strong_reference(__sync_lock_test_and_set_2_c, __sync_lock_test_and_set_2);
853 __strong_reference(__sync_lock_test_and_set_4_c, __sync_lock_test_and_set_4);
854 __strong_reference(__sync_val_compare_and_swap_1_c, __sync_val_compare_and_swap_1);
855 __strong_reference(__sync_val_compare_and_swap_2_c, __sync_val_compare_and_swap_2);
856 __strong_reference(__sync_val_compare_and_swap_4_c, __sync_val_compare_and_swap_4);
857 __strong_reference(__sync_fetch_and_add_1_c, __sync_fetch_and_add_1);
858 __strong_reference(__sync_fetch_and_add_2_c, __sync_fetch_and_add_2);
859 __strong_reference(__sync_fetch_and_add_4_c, __sync_fetch_and_add_4);
860 __strong_reference(__sync_fetch_and_and_1_c, __sync_fetch_and_and_1);
861 __strong_reference(__sync_fetch_and_and_2_c, __sync_fetch_and_and_2);
862 __strong_reference(__sync_fetch_and_and_4_c, __sync_fetch_and_and_4);
863 __strong_reference(__sync_fetch_and_sub_1_c, __sync_fetch_and_sub_1);
864 __strong_reference(__sync_fetch_and_sub_2_c, __sync_fetch_and_sub_2);
865 __strong_reference(__sync_fetch_and_sub_4_c, __sync_fetch_and_sub_4);
866 __strong_reference(__sync_fetch_and_or_1_c, __sync_fetch_and_or_1);
867 __strong_reference(__sync_fetch_and_or_2_c, __sync_fetch_and_or_2);
868 __strong_reference(__sync_fetch_and_or_4_c, __sync_fetch_and_or_4);
869 __strong_reference(__sync_fetch_and_xor_1_c, __sync_fetch_and_xor_1);
870 __strong_reference(__sync_fetch_and_xor_2_c, __sync_fetch_and_xor_2);
871 __strong_reference(__sync_fetch_and_xor_4_c, __sync_fetch_and_xor_4);
872 #endif /* __ARM_ARCH */
878 #endif /* __SYNC_ATOMICS */