2 * Copyright (c) 2013 Ed Schouten <ed@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/stdatomic.h>
32 #include <sys/types.h>
34 #include <machine/acle-compat.h>
35 #include <machine/atomic.h>
36 #include <machine/cpufunc.h>
37 #include <machine/sysarch.h>
40 * Executing statements with interrupts disabled.
43 #if defined(_KERNEL) && !defined(SMP)
44 #define WITHOUT_INTERRUPTS(s) do { \
47 regs = intr_disable(); \
51 #endif /* _KERNEL && !SMP */
56 * It turns out __sync_synchronize() does not emit any code when used
57 * with GCC 4.2. Implement our own version that does work reliably.
59 * Although __sync_lock_test_and_set() should only perform an acquire
60 * barrier, make it do a full barrier like the other functions. This
61 * should make <stdatomic.h>'s atomic_exchange_explicit() work reliably.
64 #if defined(_KERNEL) && !defined(SMP)
69 __asm volatile ("" : : : "memory");
80 #if defined(__CLANG_ATOMICS) || defined(__GNUC_ATOMICS)
83 * New C11 __atomic_* API.
86 /* ARMv6+ systems should be supported by the compiler. */
89 /* Clang doesn't allow us to reimplement builtins without this. */
91 #pragma redefine_extname __sync_synchronize_ext __sync_synchronize
92 #define __sync_synchronize __sync_synchronize_ext
96 __sync_synchronize(void)
103 #error "On SMP systems we should have proper atomic operations."
107 * On uniprocessor systems, we can perform the atomic operations by
108 * disabling interrupts.
111 #define EMIT_LOAD_N(N, uintN_t) \
113 __atomic_load_##N(uintN_t *mem, int model __unused) \
117 WITHOUT_INTERRUPTS({ \
123 #define EMIT_STORE_N(N, uintN_t) \
125 __atomic_store_##N(uintN_t *mem, uintN_t val, int model __unused) \
128 WITHOUT_INTERRUPTS({ \
133 #define EMIT_COMPARE_EXCHANGE_N(N, uintN_t) \
135 __atomic_compare_exchange_##N(uintN_t *mem, uintN_t *expected, \
136 uintN_t desired, int success __unused, int failure __unused) \
140 WITHOUT_INTERRUPTS({ \
141 if (*mem == *expected) { \
152 #define EMIT_FETCH_OP_N(N, uintN_t, name, op) \
154 __atomic_##name##_##N(uintN_t *mem, uintN_t val, int model __unused) \
158 WITHOUT_INTERRUPTS({ \
165 #define EMIT_ALL_OPS_N(N, uintN_t) \
166 EMIT_LOAD_N(N, uintN_t) \
167 EMIT_STORE_N(N, uintN_t) \
168 EMIT_COMPARE_EXCHANGE_N(N, uintN_t) \
169 EMIT_FETCH_OP_N(N, uintN_t, exchange, =) \
170 EMIT_FETCH_OP_N(N, uintN_t, fetch_add, +=) \
171 EMIT_FETCH_OP_N(N, uintN_t, fetch_and, &=) \
172 EMIT_FETCH_OP_N(N, uintN_t, fetch_or, |=) \
173 EMIT_FETCH_OP_N(N, uintN_t, fetch_sub, -=) \
174 EMIT_FETCH_OP_N(N, uintN_t, fetch_xor, ^=)
176 EMIT_ALL_OPS_N(1, uint8_t)
177 EMIT_ALL_OPS_N(2, uint16_t)
178 EMIT_ALL_OPS_N(4, uint32_t)
179 EMIT_ALL_OPS_N(8, uint64_t)
180 #undef EMIT_ALL_OPS_N
185 * For userspace on uniprocessor systems, we can implement the atomic
186 * operations by using a Restartable Atomic Sequence. This makes the
187 * kernel restart the code from the beginning when interrupted.
190 #define EMIT_LOAD_N(N, uintN_t) \
192 __atomic_load_##N(uintN_t *mem, int model __unused) \
198 #define EMIT_STORE_N(N, uintN_t) \
200 __atomic_store_##N(uintN_t *mem, uintN_t val, int model __unused) \
206 #define EMIT_EXCHANGE_N(N, uintN_t, ldr, str) \
208 __atomic_exchange_##N(uintN_t *mem, uintN_t val, int model __unused) \
210 uint32_t old, temp, ras_start; \
212 ras_start = ARM_RAS_START; \
214 /* Set up Restartable Atomic Sequence. */ \
219 "\tstr %2, [%5, #4]\n" \
221 "\t"ldr" %0, %4\n" /* Load old value. */ \
222 "\t"str" %3, %1\n" /* Store new value. */ \
224 /* Tear down Restartable Atomic Sequence. */ \
226 "\tmov %2, #0x00000000\n" \
228 "\tmov %2, #0xffffffff\n" \
229 "\tstr %2, [%5, #4]\n" \
230 : "=&r" (old), "=m" (*mem), "=&r" (temp) \
231 : "r" (val), "m" (*mem), "r" (ras_start)); \
235 #define EMIT_COMPARE_EXCHANGE_N(N, uintN_t, ldr, streq) \
237 __atomic_compare_exchange_##N(uintN_t *mem, uintN_t *pexpected, \
238 uintN_t desired, int success __unused, int failure __unused) \
240 uint32_t expected, old, temp, ras_start; \
242 expected = *pexpected; \
243 ras_start = ARM_RAS_START; \
245 /* Set up Restartable Atomic Sequence. */ \
250 "\tstr %2, [%6, #4]\n" \
252 "\t"ldr" %0, %5\n" /* Load old value. */ \
253 "\tcmp %0, %3\n" /* Compare to expected value. */\
254 "\t"streq" %4, %1\n" /* Store new value. */ \
256 /* Tear down Restartable Atomic Sequence. */ \
258 "\tmov %2, #0x00000000\n" \
260 "\tmov %2, #0xffffffff\n" \
261 "\tstr %2, [%6, #4]\n" \
262 : "=&r" (old), "=m" (*mem), "=&r" (temp) \
263 : "r" (expected), "r" (desired), "m" (*mem), \
265 if (old == expected) { \
273 #define EMIT_FETCH_OP_N(N, uintN_t, ldr, str, name, op, ret) \
275 __atomic_##name##_##N(uintN_t *mem, uintN_t val, int model __unused) \
277 uint32_t old, new, ras_start; \
279 ras_start = ARM_RAS_START; \
281 /* Set up Restartable Atomic Sequence. */ \
286 "\tstr %2, [%5, #4]\n" \
288 "\t"ldr" %0, %4\n" /* Load old value. */ \
289 "\t"op" %2, %0, %3\n" /* Calculate new value. */ \
290 "\t"str" %2, %1\n" /* Store new value. */ \
292 /* Tear down Restartable Atomic Sequence. */ \
294 "\tmov %2, #0x00000000\n" \
296 "\tmov %2, #0xffffffff\n" \
297 "\tstr %2, [%5, #4]\n" \
298 : "=&r" (old), "=m" (*mem), "=&r" (new) \
299 : "r" (val), "m" (*mem), "r" (ras_start)); \
303 #define EMIT_ALL_OPS_N(N, uintN_t, ldr, str, streq) \
304 EMIT_LOAD_N(N, uintN_t) \
305 EMIT_STORE_N(N, uintN_t) \
306 EMIT_EXCHANGE_N(N, uintN_t, ldr, str) \
307 EMIT_COMPARE_EXCHANGE_N(N, uintN_t, ldr, streq) \
308 EMIT_FETCH_OP_N(N, uintN_t, ldr, str, fetch_add, "add", old) \
309 EMIT_FETCH_OP_N(N, uintN_t, ldr, str, fetch_and, "and", old) \
310 EMIT_FETCH_OP_N(N, uintN_t, ldr, str, fetch_or, "orr", old) \
311 EMIT_FETCH_OP_N(N, uintN_t, ldr, str, fetch_sub, "sub", old) \
312 EMIT_FETCH_OP_N(N, uintN_t, ldr, str, fetch_xor, "eor", old) \
313 EMIT_FETCH_OP_N(N, uintN_t, ldr, str, add_fetch, "add", new) \
314 EMIT_FETCH_OP_N(N, uintN_t, ldr, str, and_fetch, "and", new) \
315 EMIT_FETCH_OP_N(N, uintN_t, ldr, str, or_fetch, "orr", new) \
316 EMIT_FETCH_OP_N(N, uintN_t, ldr, str, sub_fetch, "sub", new) \
317 EMIT_FETCH_OP_N(N, uintN_t, ldr, str, xor_fetch, "eor", new)
319 EMIT_ALL_OPS_N(1, uint8_t, "ldrb", "strb", "strbeq")
320 EMIT_ALL_OPS_N(2, uint16_t, "ldrh", "strh", "strheq")
321 EMIT_ALL_OPS_N(4, uint32_t, "ldr", "str", "streq")
322 #undef EMIT_ALL_OPS_N
326 #endif /* __ARM_ARCH */
328 #endif /* __CLANG_ATOMICS || __GNUC_ATOMICS */
330 #if defined(__SYNC_ATOMICS) || defined(EMIT_SYNC_ATOMICS)
333 #pragma redefine_extname __sync_lock_test_and_set_1_c __sync_lock_test_and_set_1
334 #pragma redefine_extname __sync_lock_test_and_set_2_c __sync_lock_test_and_set_2
335 #pragma redefine_extname __sync_lock_test_and_set_4_c __sync_lock_test_and_set_4
336 #pragma redefine_extname __sync_val_compare_and_swap_1_c __sync_val_compare_and_swap_1
337 #pragma redefine_extname __sync_val_compare_and_swap_2_c __sync_val_compare_and_swap_2
338 #pragma redefine_extname __sync_val_compare_and_swap_4_c __sync_val_compare_and_swap_4
339 #pragma redefine_extname __sync_fetch_and_add_1_c __sync_fetch_and_add_1
340 #pragma redefine_extname __sync_fetch_and_add_2_c __sync_fetch_and_add_2
341 #pragma redefine_extname __sync_fetch_and_add_4_c __sync_fetch_and_add_4
342 #pragma redefine_extname __sync_fetch_and_and_1_c __sync_fetch_and_and_1
343 #pragma redefine_extname __sync_fetch_and_and_2_c __sync_fetch_and_and_2
344 #pragma redefine_extname __sync_fetch_and_and_4_c __sync_fetch_and_and_4
345 #pragma redefine_extname __sync_fetch_and_or_1_c __sync_fetch_and_or_1
346 #pragma redefine_extname __sync_fetch_and_or_2_c __sync_fetch_and_or_2
347 #pragma redefine_extname __sync_fetch_and_or_4_c __sync_fetch_and_or_4
348 #pragma redefine_extname __sync_fetch_and_xor_1_c __sync_fetch_and_xor_1
349 #pragma redefine_extname __sync_fetch_and_xor_2_c __sync_fetch_and_xor_2
350 #pragma redefine_extname __sync_fetch_and_xor_4_c __sync_fetch_and_xor_4
351 #pragma redefine_extname __sync_fetch_and_sub_1_c __sync_fetch_and_sub_1
352 #pragma redefine_extname __sync_fetch_and_sub_2_c __sync_fetch_and_sub_2
353 #pragma redefine_extname __sync_fetch_and_sub_4_c __sync_fetch_and_sub_4
362 /* Implementations for old GCC versions, lacking support for atomics. */
370 * Given a memory address pointing to an 8-bit or 16-bit integer, return
371 * the address of the 32-bit word containing it.
374 static inline uint32_t *
375 round_to_word(void *ptr)
378 return ((uint32_t *)((intptr_t)ptr & ~3));
382 * Utility functions for loading and storing 8-bit and 16-bit integers
383 * in 32-bit words at an offset corresponding with the location of the
388 put_1(reg_t *r, const uint8_t *offset_ptr, uint8_t val)
392 offset = (intptr_t)offset_ptr & 3;
396 static inline uint8_t
397 get_1(const reg_t *r, const uint8_t *offset_ptr)
401 offset = (intptr_t)offset_ptr & 3;
402 return (r->v8[offset]);
406 put_2(reg_t *r, const uint16_t *offset_ptr, uint16_t val)
414 offset = (intptr_t)offset_ptr & 3;
416 r->v8[offset] = bytes.out[0];
417 r->v8[offset + 1] = bytes.out[1];
420 static inline uint16_t
421 get_2(const reg_t *r, const uint16_t *offset_ptr)
429 offset = (intptr_t)offset_ptr & 3;
430 bytes.in[0] = r->v8[offset];
431 bytes.in[1] = r->v8[offset + 1];
436 * 8-bit and 16-bit routines.
438 * These operations are not natively supported by the CPU, so we use
439 * some shifting and bitmasking on top of the 32-bit instructions.
442 #define EMIT_LOCK_TEST_AND_SET_N(N, uintN_t) \
444 __sync_lock_test_and_set_##N##_c(uintN_t *mem, uintN_t val) \
447 reg_t val32, negmask, old; \
448 uint32_t temp1, temp2; \
450 mem32 = round_to_word(mem); \
451 val32.v32 = 0x00000000; \
452 put_##N(&val32, mem, val); \
453 negmask.v32 = 0xffffffff; \
454 put_##N(&negmask, mem, 0); \
459 "\tldrex %0, %6\n" /* Load old value. */ \
460 "\tand %2, %5, %0\n" /* Remove the old value. */ \
461 "\torr %2, %2, %4\n" /* Put in the new value. */ \
462 "\tstrex %3, %2, %1\n" /* Attempt to store. */ \
463 "\tcmp %3, #0\n" /* Did it succeed? */ \
464 "\tbne 1b\n" /* Spin if failed. */ \
465 : "=&r" (old.v32), "=m" (*mem32), "=&r" (temp1), \
467 : "r" (val32.v32), "r" (negmask.v32), "m" (*mem32)); \
468 return (get_##N(&old, mem)); \
471 EMIT_LOCK_TEST_AND_SET_N(1, uint8_t)
472 EMIT_LOCK_TEST_AND_SET_N(2, uint16_t)
474 #define EMIT_VAL_COMPARE_AND_SWAP_N(N, uintN_t) \
476 __sync_val_compare_and_swap_##N##_c(uintN_t *mem, uintN_t expected, \
480 reg_t expected32, desired32, posmask, old; \
481 uint32_t negmask, temp1, temp2; \
483 mem32 = round_to_word(mem); \
484 expected32.v32 = 0x00000000; \
485 put_##N(&expected32, mem, expected); \
486 desired32.v32 = 0x00000000; \
487 put_##N(&desired32, mem, desired); \
488 posmask.v32 = 0x00000000; \
489 put_##N(&posmask, mem, ~0); \
490 negmask = ~posmask.v32; \
495 "\tldrex %0, %8\n" /* Load old value. */ \
496 "\tand %2, %6, %0\n" /* Isolate the old value. */ \
497 "\tcmp %2, %4\n" /* Compare to expected value. */\
498 "\tbne 2f\n" /* Values are unequal. */ \
499 "\tand %2, %7, %0\n" /* Remove the old value. */ \
500 "\torr %2, %5\n" /* Put in the new value. */ \
501 "\tstrex %3, %2, %1\n" /* Attempt to store. */ \
502 "\tcmp %3, #0\n" /* Did it succeed? */ \
503 "\tbne 1b\n" /* Spin if failed. */ \
505 : "=&r" (old), "=m" (*mem32), "=&r" (temp1), \
507 : "r" (expected32.v32), "r" (desired32.v32), \
508 "r" (posmask.v32), "r" (negmask), "m" (*mem32)); \
509 return (get_##N(&old, mem)); \
512 EMIT_VAL_COMPARE_AND_SWAP_N(1, uint8_t)
513 EMIT_VAL_COMPARE_AND_SWAP_N(2, uint16_t)
515 #define EMIT_ARITHMETIC_FETCH_AND_OP_N(N, uintN_t, name, op) \
517 __sync_##name##_##N##_c(uintN_t *mem, uintN_t val) \
520 reg_t val32, posmask, old; \
521 uint32_t negmask, temp1, temp2; \
523 mem32 = round_to_word(mem); \
524 val32.v32 = 0x00000000; \
525 put_##N(&val32, mem, val); \
526 posmask.v32 = 0x00000000; \
527 put_##N(&posmask, mem, ~0); \
528 negmask = ~posmask.v32; \
533 "\tldrex %0, %7\n" /* Load old value. */ \
534 "\t"op" %2, %0, %4\n" /* Calculate new value. */ \
535 "\tand %2, %5\n" /* Isolate the new value. */ \
536 "\tand %3, %6, %0\n" /* Remove the old value. */ \
537 "\torr %2, %2, %3\n" /* Put in the new value. */ \
538 "\tstrex %3, %2, %1\n" /* Attempt to store. */ \
539 "\tcmp %3, #0\n" /* Did it succeed? */ \
540 "\tbne 1b\n" /* Spin if failed. */ \
541 : "=&r" (old.v32), "=m" (*mem32), "=&r" (temp1), \
543 : "r" (val32.v32), "r" (posmask.v32), "r" (negmask), \
545 return (get_##N(&old, mem)); \
548 EMIT_ARITHMETIC_FETCH_AND_OP_N(1, uint8_t, fetch_and_add, "add")
549 EMIT_ARITHMETIC_FETCH_AND_OP_N(1, uint8_t, fetch_and_sub, "sub")
550 EMIT_ARITHMETIC_FETCH_AND_OP_N(2, uint16_t, fetch_and_add, "add")
551 EMIT_ARITHMETIC_FETCH_AND_OP_N(2, uint16_t, fetch_and_sub, "sub")
553 #define EMIT_BITWISE_FETCH_AND_OP_N(N, uintN_t, name, op, idempotence) \
555 __sync_##name##_##N##_c(uintN_t *mem, uintN_t val) \
559 uint32_t temp1, temp2; \
561 mem32 = round_to_word(mem); \
562 val32.v32 = idempotence ? 0xffffffff : 0x00000000; \
563 put_##N(&val32, mem, val); \
568 "\tldrex %0, %5\n" /* Load old value. */ \
569 "\t"op" %2, %4, %0\n" /* Calculate new value. */ \
570 "\tstrex %3, %2, %1\n" /* Attempt to store. */ \
571 "\tcmp %3, #0\n" /* Did it succeed? */ \
572 "\tbne 1b\n" /* Spin if failed. */ \
573 : "=&r" (old.v32), "=m" (*mem32), "=&r" (temp1), \
575 : "r" (val32.v32), "m" (*mem32)); \
576 return (get_##N(&old, mem)); \
579 EMIT_BITWISE_FETCH_AND_OP_N(1, uint8_t, fetch_and_and, "and", 1)
580 EMIT_BITWISE_FETCH_AND_OP_N(1, uint8_t, fetch_and_or, "orr", 0)
581 EMIT_BITWISE_FETCH_AND_OP_N(1, uint8_t, fetch_and_xor, "eor", 0)
582 EMIT_BITWISE_FETCH_AND_OP_N(2, uint16_t, fetch_and_and, "and", 1)
583 EMIT_BITWISE_FETCH_AND_OP_N(2, uint16_t, fetch_and_or, "orr", 0)
584 EMIT_BITWISE_FETCH_AND_OP_N(2, uint16_t, fetch_and_xor, "eor", 0)
591 __sync_lock_test_and_set_4_c(uint32_t *mem, uint32_t val)
598 "\tldrex %0, %4\n" /* Load old value. */
599 "\tstrex %2, %3, %1\n" /* Attempt to store. */
600 "\tcmp %2, #0\n" /* Did it succeed? */
601 "\tbne 1b\n" /* Spin if failed. */
602 : "=&r" (old), "=m" (*mem), "=&r" (temp)
603 : "r" (val), "m" (*mem));
608 __sync_val_compare_and_swap_4_c(uint32_t *mem, uint32_t expected,
616 "\tldrex %0, %5\n" /* Load old value. */
617 "\tcmp %0, %3\n" /* Compare to expected value. */
618 "\tbne 2f\n" /* Values are unequal. */
619 "\tstrex %2, %4, %1\n" /* Attempt to store. */
620 "\tcmp %2, #0\n" /* Did it succeed? */
621 "\tbne 1b\n" /* Spin if failed. */
623 : "=&r" (old), "=m" (*mem), "=&r" (temp)
624 : "r" (expected), "r" (desired), "m" (*mem));
628 #define EMIT_FETCH_AND_OP_4(name, op) \
630 __sync_##name##_4##_c(uint32_t *mem, uint32_t val) \
632 uint32_t old, temp1, temp2; \
637 "\tldrex %0, %5\n" /* Load old value. */ \
638 "\t"op" %2, %0, %4\n" /* Calculate new value. */ \
639 "\tstrex %3, %2, %1\n" /* Attempt to store. */ \
640 "\tcmp %3, #0\n" /* Did it succeed? */ \
641 "\tbne 1b\n" /* Spin if failed. */ \
642 : "=&r" (old), "=m" (*mem), "=&r" (temp1), \
644 : "r" (val), "m" (*mem)); \
648 EMIT_FETCH_AND_OP_4(fetch_and_add, "add")
649 EMIT_FETCH_AND_OP_4(fetch_and_and, "and")
650 EMIT_FETCH_AND_OP_4(fetch_and_or, "orr")
651 EMIT_FETCH_AND_OP_4(fetch_and_sub, "sub")
652 EMIT_FETCH_AND_OP_4(fetch_and_xor, "eor")
655 __strong_reference(__sync_lock_test_and_set_1_c, __sync_lock_test_and_set_1);
656 __strong_reference(__sync_lock_test_and_set_2_c, __sync_lock_test_and_set_2);
657 __strong_reference(__sync_lock_test_and_set_4_c, __sync_lock_test_and_set_4);
658 __strong_reference(__sync_val_compare_and_swap_1_c, __sync_val_compare_and_swap_1);
659 __strong_reference(__sync_val_compare_and_swap_2_c, __sync_val_compare_and_swap_2);
660 __strong_reference(__sync_val_compare_and_swap_4_c, __sync_val_compare_and_swap_4);
661 __strong_reference(__sync_fetch_and_add_1_c, __sync_fetch_and_add_1);
662 __strong_reference(__sync_fetch_and_add_2_c, __sync_fetch_and_add_2);
663 __strong_reference(__sync_fetch_and_add_4_c, __sync_fetch_and_add_4);
664 __strong_reference(__sync_fetch_and_and_1_c, __sync_fetch_and_and_1);
665 __strong_reference(__sync_fetch_and_and_2_c, __sync_fetch_and_and_2);
666 __strong_reference(__sync_fetch_and_and_4_c, __sync_fetch_and_and_4);
667 __strong_reference(__sync_fetch_and_sub_1_c, __sync_fetch_and_sub_1);
668 __strong_reference(__sync_fetch_and_sub_2_c, __sync_fetch_and_sub_2);
669 __strong_reference(__sync_fetch_and_sub_4_c, __sync_fetch_and_sub_4);
670 __strong_reference(__sync_fetch_and_or_1_c, __sync_fetch_and_or_1);
671 __strong_reference(__sync_fetch_and_or_2_c, __sync_fetch_and_or_2);
672 __strong_reference(__sync_fetch_and_or_4_c, __sync_fetch_and_or_4);
673 __strong_reference(__sync_fetch_and_xor_1_c, __sync_fetch_and_xor_1);
674 __strong_reference(__sync_fetch_and_xor_2_c, __sync_fetch_and_xor_2);
675 __strong_reference(__sync_fetch_and_xor_4_c, __sync_fetch_and_xor_4);
678 #else /* __ARM_ARCH < 6 */
683 #error "On SMP systems we should have proper atomic operations."
687 * On uniprocessor systems, we can perform the atomic operations by
688 * disabling interrupts.
691 #define EMIT_VAL_COMPARE_AND_SWAP_N(N, uintN_t) \
693 __sync_val_compare_and_swap_##N(uintN_t *mem, uintN_t expected, \
698 WITHOUT_INTERRUPTS({ \
700 if (*mem == expected) \
706 #define EMIT_FETCH_AND_OP_N(N, uintN_t, name, op) \
708 __sync_##name##_##N(uintN_t *mem, uintN_t val) \
712 WITHOUT_INTERRUPTS({ \
719 #define EMIT_ALL_OPS_N(N, uintN_t) \
720 EMIT_VAL_COMPARE_AND_SWAP_N(N, uintN_t) \
721 EMIT_FETCH_AND_OP_N(N, uintN_t, lock_test_and_set, =) \
722 EMIT_FETCH_AND_OP_N(N, uintN_t, fetch_and_add, +=) \
723 EMIT_FETCH_AND_OP_N(N, uintN_t, fetch_and_and, &=) \
724 EMIT_FETCH_AND_OP_N(N, uintN_t, fetch_and_or, |=) \
725 EMIT_FETCH_AND_OP_N(N, uintN_t, fetch_and_sub, -=) \
726 EMIT_FETCH_AND_OP_N(N, uintN_t, fetch_and_xor, ^=)
728 EMIT_ALL_OPS_N(1, uint8_t)
729 EMIT_ALL_OPS_N(2, uint16_t)
730 EMIT_ALL_OPS_N(4, uint32_t)
731 EMIT_ALL_OPS_N(8, uint64_t)
732 #undef EMIT_ALL_OPS_N
737 * For userspace on uniprocessor systems, we can implement the atomic
738 * operations by using a Restartable Atomic Sequence. This makes the
739 * kernel restart the code from the beginning when interrupted.
742 #define EMIT_LOCK_TEST_AND_SET_N(N, uintN_t, ldr, str) \
744 __sync_lock_test_and_set_##N##_c(uintN_t *mem, uintN_t val) \
746 uint32_t old, temp, ras_start; \
748 ras_start = ARM_RAS_START; \
750 /* Set up Restartable Atomic Sequence. */ \
755 "\tstr %2, [%5, #4]\n" \
757 "\t"ldr" %0, %4\n" /* Load old value. */ \
758 "\t"str" %3, %1\n" /* Store new value. */ \
760 /* Tear down Restartable Atomic Sequence. */ \
762 "\tmov %2, #0x00000000\n" \
764 "\tmov %2, #0xffffffff\n" \
765 "\tstr %2, [%5, #4]\n" \
766 : "=&r" (old), "=m" (*mem), "=&r" (temp) \
767 : "r" (val), "m" (*mem), "r" (ras_start)); \
771 #define EMIT_VAL_COMPARE_AND_SWAP_N(N, uintN_t, ldr, streq) \
773 __sync_val_compare_and_swap_##N##_c(uintN_t *mem, uintN_t expected, \
776 uint32_t old, temp, ras_start; \
778 ras_start = ARM_RAS_START; \
780 /* Set up Restartable Atomic Sequence. */ \
785 "\tstr %2, [%6, #4]\n" \
787 "\t"ldr" %0, %5\n" /* Load old value. */ \
788 "\tcmp %0, %3\n" /* Compare to expected value. */\
789 "\t"streq" %4, %1\n" /* Store new value. */ \
791 /* Tear down Restartable Atomic Sequence. */ \
793 "\tmov %2, #0x00000000\n" \
795 "\tmov %2, #0xffffffff\n" \
796 "\tstr %2, [%6, #4]\n" \
797 : "=&r" (old), "=m" (*mem), "=&r" (temp) \
798 : "r" (expected), "r" (desired), "m" (*mem), \
803 #define EMIT_FETCH_AND_OP_N(N, uintN_t, ldr, str, name, op) \
805 __sync_##name##_##N##_c(uintN_t *mem, uintN_t val) \
807 uint32_t old, temp, ras_start; \
809 ras_start = ARM_RAS_START; \
811 /* Set up Restartable Atomic Sequence. */ \
816 "\tstr %2, [%5, #4]\n" \
818 "\t"ldr" %0, %4\n" /* Load old value. */ \
819 "\t"op" %2, %0, %3\n" /* Calculate new value. */ \
820 "\t"str" %2, %1\n" /* Store new value. */ \
822 /* Tear down Restartable Atomic Sequence. */ \
824 "\tmov %2, #0x00000000\n" \
826 "\tmov %2, #0xffffffff\n" \
827 "\tstr %2, [%5, #4]\n" \
828 : "=&r" (old), "=m" (*mem), "=&r" (temp) \
829 : "r" (val), "m" (*mem), "r" (ras_start)); \
833 #define EMIT_ALL_OPS_N(N, uintN_t, ldr, str, streq) \
834 EMIT_LOCK_TEST_AND_SET_N(N, uintN_t, ldr, str) \
835 EMIT_VAL_COMPARE_AND_SWAP_N(N, uintN_t, ldr, streq) \
836 EMIT_FETCH_AND_OP_N(N, uintN_t, ldr, str, fetch_and_add, "add") \
837 EMIT_FETCH_AND_OP_N(N, uintN_t, ldr, str, fetch_and_and, "and") \
838 EMIT_FETCH_AND_OP_N(N, uintN_t, ldr, str, fetch_and_or, "orr") \
839 EMIT_FETCH_AND_OP_N(N, uintN_t, ldr, str, fetch_and_sub, "sub") \
840 EMIT_FETCH_AND_OP_N(N, uintN_t, ldr, str, fetch_and_xor, "eor")
843 EMIT_ALL_OPS_N(1, uint8_t, "ldrb", "strb", "strbeq")
844 EMIT_ALL_OPS_N(2, uint16_t, "ldrh", "strh", "strheq")
846 EMIT_ALL_OPS_N(1, uint8_t, "ldrb", "strb", "streqb")
847 EMIT_ALL_OPS_N(2, uint16_t, "ldrh", "strh", "streqh")
849 EMIT_ALL_OPS_N(4, uint32_t, "ldr", "str", "streq")
852 __strong_reference(__sync_lock_test_and_set_1_c, __sync_lock_test_and_set_1);
853 __strong_reference(__sync_lock_test_and_set_2_c, __sync_lock_test_and_set_2);
854 __strong_reference(__sync_lock_test_and_set_4_c, __sync_lock_test_and_set_4);
855 __strong_reference(__sync_val_compare_and_swap_1_c, __sync_val_compare_and_swap_1);
856 __strong_reference(__sync_val_compare_and_swap_2_c, __sync_val_compare_and_swap_2);
857 __strong_reference(__sync_val_compare_and_swap_4_c, __sync_val_compare_and_swap_4);
858 __strong_reference(__sync_fetch_and_add_1_c, __sync_fetch_and_add_1);
859 __strong_reference(__sync_fetch_and_add_2_c, __sync_fetch_and_add_2);
860 __strong_reference(__sync_fetch_and_add_4_c, __sync_fetch_and_add_4);
861 __strong_reference(__sync_fetch_and_and_1_c, __sync_fetch_and_and_1);
862 __strong_reference(__sync_fetch_and_and_2_c, __sync_fetch_and_and_2);
863 __strong_reference(__sync_fetch_and_and_4_c, __sync_fetch_and_and_4);
864 __strong_reference(__sync_fetch_and_sub_1_c, __sync_fetch_and_sub_1);
865 __strong_reference(__sync_fetch_and_sub_2_c, __sync_fetch_and_sub_2);
866 __strong_reference(__sync_fetch_and_sub_4_c, __sync_fetch_and_sub_4);
867 __strong_reference(__sync_fetch_and_or_1_c, __sync_fetch_and_or_1);
868 __strong_reference(__sync_fetch_and_or_2_c, __sync_fetch_and_or_2);
869 __strong_reference(__sync_fetch_and_or_4_c, __sync_fetch_and_or_4);
870 __strong_reference(__sync_fetch_and_xor_1_c, __sync_fetch_and_xor_1);
871 __strong_reference(__sync_fetch_and_xor_2_c, __sync_fetch_and_xor_2);
872 __strong_reference(__sync_fetch_and_xor_4_c, __sync_fetch_and_xor_4);
873 #endif /* __ARM_ARCH */
879 #endif /* __SYNC_ATOMICS */