1 /* $NetBSD: cpuswitch.S,v 1.41 2003/11/15 08:44:18 scw Exp $ */
4 * Copyright 2003 Wasabi Systems, Inc.
7 * Written by Steve C. Woodford for Wasabi Systems, Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
38 * Copyright (c) 1994-1998 Mark Brinicombe.
39 * Copyright (c) 1994 Brini.
40 * All rights reserved.
42 * This code is derived from software written for Brini by Mark Brinicombe
44 * Redistribution and use in source and binary forms, with or without
45 * modification, are permitted provided that the following conditions
47 * 1. Redistributions of source code must retain the above copyright
48 * notice, this list of conditions and the following disclaimer.
49 * 2. Redistributions in binary form must reproduce the above copyright
50 * notice, this list of conditions and the following disclaimer in the
51 * documentation and/or other materials provided with the distribution.
52 * 3. All advertising materials mentioning features or use of this software
53 * must display the following acknowledgement:
54 * This product includes software developed by Brini.
55 * 4. The name of the company nor the name of the author may be used to
56 * endorse or promote products derived from this software without specific
57 * prior written permission.
59 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
60 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
61 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
62 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
63 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
64 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
65 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
71 * RiscBSD kernel project
75 * cpu switching functions
82 #include "opt_sched.h"
84 #include <machine/asm.h>
85 #include <machine/asmacros.h>
86 #include <machine/armreg.h>
87 #include <machine/vfp.h>
89 __FBSDID("$FreeBSD$");
92 #define GET_PCPU(tmp, tmp2) \
96 .fpu vfp /* allow VFP instructions */
100 .word _C_LABEL(__pcpu)
102 .word _C_LABEL(blocked_lock)
105 #define DOMAIN_CLIENT 0x01
108 .word _C_LABEL(cpufuncs)
111 * cpu_throw(oldtd, newtd)
113 * Remove current thread state, then select the next thread to run
114 * and load its state.
126 #ifdef VFP /* This thread is dying, disable */
127 bl _C_LABEL(vfp_discard) /* VFP without preserving state. */
131 ldr r7, [r5, #(TD_PCB)] /* r7 = new thread's PCB */
133 /* Switch to lwp0 context */
137 ldr pc, [r9, #CF_IDCACHE_WBINV_ALL]
138 ldr r0, [r7, #(PCB_PL1VEC)]
139 ldr r1, [r7, #(PCB_DACR)]
141 * r0 = Pointer to L1 slot for vector_page (or NULL)
149 * Ensure the vector table is accessible by fixing up lwp0's L1
151 cmp r0, #0 /* No need to fixup vector table? */
152 ldrne r3, [r0] /* But if yes, fetch current value */
153 ldrne r2, [r7, #(PCB_L1VEC)] /* Fetch new vector_page value */
154 mcr p15, 0, r1, c3, c0, 0 /* Update DACR for lwp0's context */
155 cmpne r3, r2 /* Stuffing the same value? */
156 strne r2, [r0] /* Store if not. */
158 #ifdef PMAP_INCLUDE_PTE_SYNC
160 * Need to sync the cache to make sure that last store is
161 * visible to the MMU.
165 ldrne pc, [r9, #CF_DCACHE_WB_RANGE]
166 #endif /* PMAP_INCLUDE_PTE_SYNC */
169 * Note: We don't do the same optimisation as cpu_switch() with
170 * respect to avoiding flushing the TLB if we're switching to
171 * the same L1 since this process' VM space may be about to go
172 * away, so we don't want *any* turds left in the TLB.
175 /* Switch the memory to the new process */
176 ldr r0, [r7, #(PCB_PAGEDIR)]
178 ldr pc, [r9, #CF_CONTEXT_SWITCH]
181 /* Hook in a new pcb */
182 str r7, [r6, #PC_CURPCB]
183 /* We have a new curthread now so make a note it */
184 str r5, [r6, #PC_CURTHREAD]
187 ldr r6, [r5, #(TD_MD + MD_TP)]
188 ldr r4, =ARM_TP_ADDRESS
190 ldr r6, [r5, #(TD_MD + MD_RAS_START)]
191 str r6, [r4, #4] /* ARM_RAS_START */
192 ldr r6, [r5, #(TD_MD + MD_RAS_END)]
193 str r6, [r4, #8] /* ARM_RAS_END */
195 /* Restore all the saved registers and exit */
197 ldmia r3, {r4-r12, sp, pc}
201 * cpu_switch(oldtd, newtd, lock)
203 * Save the current thread state, then select the next thread to run
204 * and load its state.
207 * r2 = lock (new lock for old thread)
210 /* Interrupts are disabled. */
211 /* Save all the registers in the old thread's pcb. */
212 ldr r3, [r0, #(TD_PCB)]
214 /* Restore all the saved registers and exit */
216 stmia r3, {r4-r12, sp, lr, pc}
218 mov r6, r2 /* Save the mutex */
220 /* rem: r0 = old lwp */
221 /* rem: interrupts are disabled */
223 /* Process is now on a processor. */
224 /* We have a new curthread now so make a note it */
226 str r1, [r7, #PC_CURTHREAD]
228 /* Hook in a new pcb */
229 ldr r2, [r1, #TD_PCB]
230 str r2, [r7, #PC_CURPCB]
232 /* Stage two : Save old context */
234 /* Get the user structure for the old thread. */
235 ldr r2, [r0, #(TD_PCB)]
236 mov r4, r0 /* Save the old thread. */
238 /* Store the old tp; userland can change it on armv4. */
239 ldr r3, =ARM_TP_ADDRESS
241 str r9, [r0, #(TD_MD + MD_TP)]
243 str r9, [r0, #(TD_MD + MD_RAS_START)]
245 str r9, [r0, #(TD_MD + MD_RAS_END)]
248 ldr r9, [r1, #(TD_MD + MD_TP)]
250 ldr r9, [r1, #(TD_MD + MD_RAS_START)]
252 ldr r9, [r1, #(TD_MD + MD_RAS_END)]
255 /* Get the user structure for the new process in r9 */
256 ldr r9, [r1, #(TD_PCB)]
258 /* rem: r2 = old PCB */
259 /* rem: r9 = new PCB */
260 /* rem: interrupts are enabled */
263 fmrx r0, fpexc /* If the VFP is enabled */
264 tst r0, #(VFPEXC_EN) /* the current thread has */
265 movne r1, #1 /* used it, so go save */
266 addne r0, r2, #(PCB_VFPSTATE) /* the state into the PCB */
267 blne _C_LABEL(vfp_store) /* and disable the VFP. */
270 /* r0-r3 now free! */
272 /* Third phase : restore saved context */
274 /* rem: r2 = old PCB */
275 /* rem: r9 = new PCB */
277 ldr r5, [r9, #(PCB_DACR)] /* r5 = new DACR */
278 mov r2, #DOMAIN_CLIENT
279 cmp r5, r2, lsl #(PMAP_DOMAIN_KERNEL * 2) /* Sw to kernel thread? */
280 beq .Lcs_context_switched /* Yup. Don't flush cache */
281 mrc p15, 0, r0, c3, c0, 0 /* r0 = old DACR */
283 * Get the new L1 table pointer into r11. If we're switching to
284 * an LWP with the same address space as the outgoing one, we can
285 * skip the cache purge and the TTB load.
287 * To avoid data dep stalls that would happen anyway, we try
288 * and get some useful work done in the mean time.
290 mrc p15, 0, r10, c2, c0, 0 /* r10 = old L1 */
291 ldr r11, [r9, #(PCB_PAGEDIR)] /* r11 = new L1 */
293 teq r10, r11 /* Same L1? */
294 cmpeq r0, r5 /* Same DACR? */
295 beq .Lcs_context_switched /* yes! */
298 * Definitely need to flush the cache.
303 ldr pc, [r1, #CF_IDCACHE_WBINV_ALL]
305 .Lcs_cache_purge_skipped:
307 /* rem: r9 = new PCB */
308 /* rem: r10 = old L1 */
309 /* rem: r11 = new L1 */
312 ldr r7, [r9, #(PCB_PL1VEC)]
315 * Ensure the vector table is accessible by fixing up the L1
317 cmp r7, #0 /* No need to fixup vector table? */
318 ldrne r2, [r7] /* But if yes, fetch current value */
319 ldrne r0, [r9, #(PCB_L1VEC)] /* Fetch new vector_page value */
320 mcr p15, 0, r5, c3, c0, 0 /* Update DACR for new context */
321 cmpne r2, r0 /* Stuffing the same value? */
322 #ifndef PMAP_INCLUDE_PTE_SYNC
323 strne r0, [r7] /* Nope, update it */
326 str r0, [r7] /* Otherwise, update it */
329 * Need to sync the cache to make sure that last store is
330 * visible to the MMU.
336 ldr pc, [r2, #CF_DCACHE_WB_RANGE]
339 #endif /* PMAP_INCLUDE_PTE_SYNC */
341 cmp r10, r11 /* Switching to the same L1? */
343 beq .Lcs_same_l1 /* Yup. */
345 * Do a full context switch, including full TLB flush.
349 ldr pc, [r10, #CF_CONTEXT_SWITCH]
351 b .Lcs_context_switched
354 * We're switching to a different process in the same L1.
355 * In this situation, we only need to flush the TLB for the
356 * vector_page mapping, and even then only if r7 is non-NULL.
360 movne r0, #0 /* We *know* vector_page's VA is 0x0 */
362 ldrne pc, [r10, #CF_TLB_FLUSHID_SE]
364 .Lcs_context_switched:
366 /* Release the old thread */
367 str r6, [r4, #TD_LOCK]
369 /* XXXSCW: Safe to re-enable FIQs here */
371 /* rem: r9 = new PCB */
373 /* Restore all the saved registers and exit */
375 ldmia r3, {r4-r12, sp, pc}