2 * Copyright 2014 Olivier Houchard <cognet@FreeBSD.org>
3 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
4 * Copyright 2014 Michal Meloun <meloun@miracle.cz>
5 * Copyright 2014 Andrew Turner <andrew@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include "opt_ktrace.h"
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
37 #include <sys/systm.h>
39 #include <sys/kernel.h>
41 #include <sys/mutex.h>
42 #include <sys/signalvar.h>
44 #include <sys/vmmeter.h>
47 #include <sys/ktrace.h>
52 #include <vm/vm_kern.h>
53 #include <vm/vm_map.h>
54 #include <vm/vm_extern.h>
55 #include <vm/vm_param.h>
57 #include <machine/cpu.h>
58 #include <machine/frame.h>
59 #include <machine/machdep.h>
60 #include <machine/pcb.h>
64 #include <machine/db_machdep.h>
68 #include <sys/dtrace_bsd.h>
71 extern char cachebailout[];
74 int last_fault_code; /* For the benefit of pmap_fault_fixup() */
83 typedef int abort_func_t(struct trapframe *, u_int, u_int, u_int, u_int,
84 struct thread *, struct ksig *);
86 static abort_func_t abort_fatal;
87 static abort_func_t abort_align;
88 static abort_func_t abort_icache;
96 * How are the aborts handled?
99 * - Always fatal as we do not know what does it mean.
100 * Imprecise External Abort:
101 * - Always fatal, but can be handled somehow in the future.
102 * Now, due to PCIe buggy hardware, ignored.
103 * Precise External Abort:
104 * - Always fatal, but who knows in the future???
106 * - Special handling.
107 * External Translation Abort (L1 & L2)
108 * - Always fatal as something is screwed up in page tables or hardware.
109 * Domain Fault (L1 & L2):
110 * - Always fatal as we do not play game with domains.
112 * - Everything should be aligned in kernel with exception of user to kernel
113 * and vice versa data copying, so if pcb_onfault is not set, it's fatal.
114 * We generate signal in case of abort from user mode.
115 * Instruction cache maintenance:
116 * - According to manual, this is translation fault during cache maintenance
117 * operation. So, it could be really complex in SMP case and fuzzy too
118 * for cache operations working on virtual addresses. For now, we will
119 * consider this abort as fatal. In fact, no cache maintenance on
120 * not mapped virtual addresses should be called. As cache maintenance
121 * operation (except DMB, DSB, and Flush Prefetch Buffer) are priviledged,
122 * the abort is fatal for user mode as well for now. (This is good place to
123 * note that cache maintenance on virtual address fill TLB.)
124 * Acces Bit (L1 & L2):
125 * - Fast hardware emulation for kernel and user mode.
126 * Translation Fault (L1 & L2):
127 * - Standard fault mechanism is held including vm_fault().
128 * Permission Fault (L1 & L2):
129 * - Fast hardware emulation of modify bits and in other cases, standard
130 * fault mechanism is held including vm_fault().
133 static const struct abort aborts[] = {
134 {abort_fatal, "Undefined Code (0x000)"},
135 {abort_align, "Alignment Fault"},
136 {abort_fatal, "Debug Event"},
137 {NULL, "Access Bit (L1)"},
138 {NULL, "Instruction cache maintenance"},
139 {NULL, "Translation Fault (L1)"},
140 {NULL, "Access Bit (L2)"},
141 {NULL, "Translation Fault (L2)"},
143 {abort_fatal, "External Abort"},
144 {abort_fatal, "Domain Fault (L1)"},
145 {abort_fatal, "Undefined Code (0x00A)"},
146 {abort_fatal, "Domain Fault (L2)"},
147 {abort_fatal, "External Translation Abort (L1)"},
148 {NULL, "Permission Fault (L1)"},
149 {abort_fatal, "External Translation Abort (L2)"},
150 {NULL, "Permission Fault (L2)"},
152 {abort_fatal, "TLB Conflict Abort"},
153 {abort_fatal, "Undefined Code (0x401)"},
154 {abort_fatal, "Undefined Code (0x402)"},
155 {abort_fatal, "Undefined Code (0x403)"},
156 {abort_fatal, "Undefined Code (0x404)"},
157 {abort_fatal, "Undefined Code (0x405)"},
158 {abort_fatal, "Asynchronous External Abort"},
159 {abort_fatal, "Undefined Code (0x407)"},
161 {abort_fatal, "Asynchronous Parity Error on Memory Access"},
162 {abort_fatal, "Parity Error on Memory Access"},
163 {abort_fatal, "Undefined Code (0x40A)"},
164 {abort_fatal, "Undefined Code (0x40B)"},
165 {abort_fatal, "Parity Error on Translation (L1)"},
166 {abort_fatal, "Undefined Code (0x40D)"},
167 {abort_fatal, "Parity Error on Translation (L2)"},
168 {abort_fatal, "Undefined Code (0x40F)"}
172 call_trapsignal(struct thread *td, int sig, int code, vm_offset_t addr)
176 CTR4(KTR_TRAP, "%s: addr: %#x, sig: %d, code: %d",
177 __func__, addr, sig, code);
180 * TODO: some info would be nice to know
181 * if we are serving data or prefetch abort.
184 ksiginfo_init_trap(&ksi);
187 ksi.ksi_addr = (void *)addr;
188 trapsignal(td, &ksi);
192 * abort_imprecise() handles the following abort:
194 * FAULT_EA_IMPREC - Imprecise External Abort
196 * The imprecise means that we don't know where the abort happened,
197 * thus FAR is undefined. The abort should not never fire, but hot
198 * plugging or accidental hardware failure can be the cause of it.
199 * If the abort happens, it can even be on different (thread) context.
200 * Without any additional support, the abort is fatal, as we do not
201 * know what really happened.
203 * QQQ: Some additional functionality, like pcb_onfault but global,
204 * can be implemented. Imprecise handlers could be registered
205 * which tell us if the abort is caused by something they know
206 * about. They should return one of three codes like:
210 * The handlers should be called until some of them returns
211 * FAULT_IS_MINE value or all was called. If all handlers return
212 * FAULT_IS_NOT_MINE value, then the abort is fatal.
215 abort_imprecise(struct trapframe *tf, u_int fsr, u_int prefetch, bool usermode)
219 * XXX - We can got imprecise abort as result of access
220 * to not-present PCI/PCIe configuration space.
225 abort_fatal(tf, FAULT_EA_IMPREC, fsr, 0, prefetch, curthread, NULL);
228 * Returning from this function means that we ignore
229 * the abort for good reason. Note that imprecise abort
230 * could fire any time even in user mode.
236 userret(curthread, tf);
241 * abort_debug() handles the following abort:
243 * FAULT_DEBUG - Debug Event
247 abort_debug(struct trapframe *tf, u_int fsr, u_int prefetch, bool usermode,
255 call_trapsignal(td, SIGTRAP, TRAP_BRKPT, far);
259 kdb_trap((prefetch) ? T_BREAKPOINT : T_WATCHPOINT, 0, tf);
261 printf("No debugger in kernel.\n");
269 * FAR, FSR, and everything what can be lost after enabling
270 * interrupts must be grabbed before the interrupts will be
271 * enabled. Note that when interrupts will be enabled, we
272 * could even migrate to another CPU ...
274 * TODO: move quick cases to ASM
277 abort_handler(struct trapframe *tf, int prefetch)
298 fsr = (prefetch) ? cp15_ifsr_get(): cp15_dfsr_get();
300 far = (prefetch) ? cp15_ifar_get() : cp15_dfar_get();
302 far = (prefetch) ? TRAPF_PC(tf) : cp15_dfar_get();
305 idx = FSR_TO_FAULT(fsr);
306 usermode = TRAPF_USERMODE(tf); /* Abort came from user mode? */
309 * Apply BP hardening by flushing the branch prediction cache
310 * for prefaults on kernel addresses.
312 if (__predict_false(prefetch && far > VM_MAXUSER_ADDRESS &&
313 (idx == FAULT_TRAN_L2 || idx == FAULT_PERM_L2))) {
314 bp_harden = PCPU_GET(bp_harden_kind);
315 if (bp_harden == PCPU_BP_HARDEN_KIND_BPIALL)
317 else if (bp_harden == PCPU_BP_HARDEN_KIND_ICIALLU)
324 CTR6(KTR_TRAP, "%s: fsr %#x (idx %u) far %#x prefetch %u usermode %d",
325 __func__, fsr, idx, far, prefetch, usermode);
328 * Firstly, handle aborts that are not directly related to mapping.
330 if (__predict_false(idx == FAULT_EA_IMPREC)) {
331 abort_imprecise(tf, fsr, prefetch, usermode);
335 if (__predict_false(idx == FAULT_DEBUG)) {
336 abort_debug(tf, fsr, prefetch, usermode, far);
341 * ARM has a set of unprivileged load and store instructions
342 * (LDRT/LDRBT/STRT/STRBT ...) which are supposed to be used in other
343 * than user mode and OS should recognize their aborts and behave
344 * appropriately. However, there is no way how to do that reasonably
345 * in general unless we restrict the handling somehow.
347 * For now, these instructions are used only in copyin()/copyout()
348 * like functions where usermode buffers are checked in advance that
349 * they are not from KVA space. Thus, no action is needed here.
353 * (1) Handle access and R/W hardware emulation aborts.
354 * (2) Check that abort is not on pmap essential address ranges.
355 * There is no way how to fix it, so we don't even try.
357 rv = pmap_fault(PCPU_GET(curpmap), far, fsr, idx, usermode);
358 if (rv == KERN_SUCCESS)
366 if (rv == KERN_INVALID_ADDRESS)
369 if (__predict_false((td->td_pflags & TDP_NOFAULTING) != 0)) {
371 * Due to both processor errata and lazy TLB invalidation when
372 * access restrictions are removed from virtual pages, memory
373 * accesses that are allowed by the physical mapping layer may
374 * nonetheless cause one spurious page fault per virtual page.
375 * When the thread is executing a "no faulting" section that
376 * is bracketed by vm_fault_{disable,enable}_pagefaults(),
377 * every page fault is treated as a spurious page fault,
378 * unless it accesses the same virtual address as the most
379 * recent page fault within the same "no faulting" section.
381 if (td->td_md.md_spurflt_addr != far ||
382 (td->td_pflags & TDP_RESETSPUR) != 0) {
383 td->td_md.md_spurflt_addr = far;
384 td->td_pflags &= ~TDP_RESETSPUR;
386 tlb_flush_local(far & ~PAGE_MASK);
391 * If we get a page fault while in a critical section, then
392 * it is most likely a fatal kernel page fault. The kernel
393 * is already going to panic trying to get a sleep lock to
394 * do the VM lookup, so just consider it a fatal trap so the
395 * kernel can print out a useful trap message and even get
398 * If we get a page fault while holding a non-sleepable
399 * lock, then it is most likely a fatal kernel page fault.
400 * If WITNESS is enabled, then it's going to whine about
401 * bogus LORs with various VM locks, so just skip to the
402 * fatal trap handling directly.
404 if (td->td_critnest != 0 ||
405 WITNESS_CHECK(WARN_SLEEPOK | WARN_GIANTOK, NULL,
406 "Kernel page fault") != 0) {
407 abort_fatal(tf, idx, fsr, far, prefetch, td, &ksig);
412 /* Re-enable interrupts if they were enabled previously. */
413 if (td->td_md.md_spinlock_count == 0) {
414 if (__predict_true(tf->tf_spsr & PSR_I) == 0)
415 enable_interrupts(PSR_I);
416 if (__predict_true(tf->tf_spsr & PSR_F) == 0)
417 enable_interrupts(PSR_F);
423 if (td->td_cowgen != p->p_cowgen)
424 thread_cow_update(td);
427 /* Invoke the appropriate handler, if necessary. */
428 if (__predict_false(aborts[idx].func != NULL)) {
429 if ((aborts[idx].func)(tf, idx, fsr, far, prefetch, td, &ksig))
435 * At this point, we're dealing with one of the following aborts:
437 * FAULT_ICACHE - I-cache maintenance
438 * FAULT_TRAN_xx - Translation
439 * FAULT_PERM_xx - Permission
443 * Don't pass faulting cache operation to vm_fault(). We don't want
444 * to handle all vm stuff at this moment.
447 if (__predict_false(pcb->pcb_onfault == cachebailout)) {
448 tf->tf_r0 = far; /* return failing address */
449 tf->tf_pc = (register_t)pcb->pcb_onfault;
453 /* Handle remaining I-cache aborts. */
454 if (idx == FAULT_ICACHE) {
455 if (abort_icache(tf, idx, fsr, far, prefetch, td, &ksig))
460 va = trunc_page(far);
461 if (va >= KERNBASE) {
463 * Don't allow user-mode faults in kernel address space.
471 * This is a fault on non-kernel virtual memory. If curproc
472 * is NULL or curproc->p_vmspace is NULL the fault is fatal.
474 vm = (p != NULL) ? p->p_vmspace : NULL;
479 if (!usermode && (td->td_intr_nesting_level != 0 ||
480 pcb->pcb_onfault == NULL)) {
481 abort_fatal(tf, idx, fsr, far, prefetch, td, &ksig);
486 ftype = (fsr & FSR_WNR) ? VM_PROT_WRITE : VM_PROT_READ;
488 ftype |= VM_PROT_EXECUTE;
491 last_fault_code = fsr;
495 onfault = pcb->pcb_onfault;
496 pcb->pcb_onfault = NULL;
499 /* Fault in the page. */
500 rv = vm_fault(map, va, ftype, VM_FAULT_NORMAL);
503 pcb->pcb_onfault = onfault;
506 if (__predict_true(rv == KERN_SUCCESS))
510 if (td->td_intr_nesting_level == 0 &&
511 pcb->pcb_onfault != NULL) {
513 tf->tf_pc = (int)pcb->pcb_onfault;
516 CTR2(KTR_TRAP, "%s: vm_fault() failed with %d", __func__, rv);
517 abort_fatal(tf, idx, fsr, far, prefetch, td, &ksig);
522 ksig.code = (rv == KERN_PROTECTION_FAILURE) ? SEGV_ACCERR : SEGV_MAPERR;
526 call_trapsignal(td, ksig.sig, ksig.code, ksig.addr);
533 * abort_fatal() handles the following data aborts:
535 * FAULT_DEBUG - Debug Event
536 * FAULT_ACCESS_xx - Acces Bit
537 * FAULT_EA_PREC - Precise External Abort
538 * FAULT_DOMAIN_xx - Domain Fault
539 * FAULT_EA_TRAN_xx - External Translation Abort
540 * FAULT_EA_IMPREC - Imprecise External Abort
541 * + all undefined codes for ABORT
543 * We should never see these on a properly functioning system.
545 * This function is also called by the other handlers if they
546 * detect a fatal problem.
548 * Note: If 'l' is NULL, we assume we're dealing with a prefetch abort.
551 abort_fatal(struct trapframe *tf, u_int idx, u_int fsr, u_int far,
552 u_int prefetch, struct thread *td, struct ksig *ksig)
558 usermode = TRAPF_USERMODE(tf);
561 if (dtrace_trap_func != NULL && (*dtrace_trap_func)(tf, far))
566 mode = usermode ? "user" : "kernel";
567 rw_mode = fsr & FSR_WNR ? "write" : "read";
568 disable_interrupts(PSR_I|PSR_F);
571 printf("Fatal %s mode data abort: '%s' on %s\n", mode,
572 aborts[idx].desc, rw_mode);
573 printf("trapframe: %p\nFSR=%08x, FAR=", tf, fsr);
574 if (idx != FAULT_EA_IMPREC)
575 printf("%08x, ", far);
578 printf("spsr=%08x\n", tf->tf_spsr);
580 printf("Fatal %s mode prefetch abort at 0x%08x\n",
582 printf("trapframe: %p, spsr=%08x\n", tf, tf->tf_spsr);
585 printf("r0 =%08x, r1 =%08x, r2 =%08x, r3 =%08x\n",
586 tf->tf_r0, tf->tf_r1, tf->tf_r2, tf->tf_r3);
587 printf("r4 =%08x, r5 =%08x, r6 =%08x, r7 =%08x\n",
588 tf->tf_r4, tf->tf_r5, tf->tf_r6, tf->tf_r7);
589 printf("r8 =%08x, r9 =%08x, r10=%08x, r11=%08x\n",
590 tf->tf_r8, tf->tf_r9, tf->tf_r10, tf->tf_r11);
591 printf("r12=%08x, ", tf->tf_r12);
594 printf("usp=%08x, ulr=%08x",
595 tf->tf_usr_sp, tf->tf_usr_lr);
597 printf("ssp=%08x, slr=%08x",
598 tf->tf_svc_sp, tf->tf_svc_lr);
599 printf(", pc =%08x\n\n", tf->tf_pc);
602 if (debugger_on_panic || kdb_active)
603 kdb_trap(fsr, 0, tf);
605 panic("Fatal abort");
610 * abort_align() handles the following data abort:
612 * FAULT_ALIGN - Alignment fault
614 * Everything should be aligned in kernel with exception of user to kernel
615 * and vice versa data copying, so if pcb_onfault is not set, it's fatal.
616 * We generate signal in case of abort from user mode.
619 abort_align(struct trapframe *tf, u_int idx, u_int fsr, u_int far,
620 u_int prefetch, struct thread *td, struct ksig *ksig)
624 usermode = TRAPF_USERMODE(tf);
626 if (td->td_intr_nesting_level == 0 && td != NULL &&
627 td->td_pcb->pcb_onfault != NULL) {
629 tf->tf_pc = (int)td->td_pcb->pcb_onfault;
632 abort_fatal(tf, idx, fsr, far, prefetch, td, ksig);
634 /* Deliver a bus error signal to the process */
635 ksig->code = BUS_ADRALN;
642 * abort_icache() handles the following data abort:
644 * FAULT_ICACHE - Instruction cache maintenance
646 * According to manual, FAULT_ICACHE is translation fault during cache
647 * maintenance operation. In fact, no cache maintenance operation on
648 * not mapped virtual addresses should be called. As cache maintenance
649 * operation (except DMB, DSB, and Flush Prefetch Buffer) are priviledged,
650 * the abort is concider as fatal for now. However, all the matter with
651 * cache maintenance operation on virtual addresses could be really complex
652 * and fuzzy in SMP case, so maybe in future standard fault mechanism
653 * should be held here including vm_fault() calling.
656 abort_icache(struct trapframe *tf, u_int idx, u_int fsr, u_int far,
657 u_int prefetch, struct thread *td, struct ksig *ksig)
660 abort_fatal(tf, idx, fsr, far, prefetch, td, ksig);