2 * Copyright (c) 2009 Sylvestre Gallon. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #ifndef ARM_AT91_AT91_AICREG_H
29 #define ARM_AT91_AT91_AICREG_H
31 /* Interrupt Controller */
32 #define IC_SMR (0) /* Source mode register */
33 #define IC_SVR (128) /* Source vector register */
34 #define IC_IVR (256) /* IRQ vector register */
35 #define IC_FVR (260) /* FIQ vector register */
36 #define IC_ISR (264) /* Interrupt status register */
37 #define IC_IPR (268) /* Interrupt pending register */
38 #define IC_IMR (272) /* Interrupt status register */
39 #define IC_CISR (276) /* Core interrupt status register */
40 #define IC_IECR (288) /* Interrupt enable command register */
41 #define IC_IDCR (292) /* Interrupt disable command register */
42 #define IC_ICCR (296) /* Interrupt clear command register */
43 #define IC_ISCR (300) /* Interrupt set command register */
44 #define IC_EOICR (304) /* End of interrupt command register */
45 #define IC_SPU (308) /* Spurious vector register */
46 #define IC_DCR (312) /* Debug control register */
47 #define IC_FFER (320) /* Fast forcing enable register */
48 #define IC_FFDR (324) /* Fast forcing disable register */
49 #define IC_FFSR (328) /* Fast forcing status register */
51 #endif /*ARM_AT91_AT91_AICREG_H*/