2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1994-1998 Mark Brinicombe.
5 * Copyright (c) 1994 Brini.
8 * This code is derived from software written for Brini by Mark Brinicombe
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Brini.
21 * 4. The name of the company nor the name of the author may be used to
22 * endorse or promote products derived from this software without specific
23 * prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * RiscBSD kernel project
41 * Machine dependent functions for kernel setup
43 * This file needs a lot of work.
48 #include "opt_kstack_pages.h"
49 #include "opt_platform.h"
51 #include <sys/cdefs.h>
52 __FBSDID("$FreeBSD$");
54 #define _ARM32_BUS_DMA_PRIVATE
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/sysproto.h>
58 #include <sys/signalvar.h>
59 #include <sys/imgact.h>
60 #include <sys/kernel.h>
62 #include <sys/linker.h>
64 #include <sys/malloc.h>
65 #include <sys/mutex.h>
68 #include <sys/ptrace.h>
75 #include <sys/msgbuf.h>
76 #include <sys/devmap.h>
77 #include <machine/physmem.h>
78 #include <machine/reg.h>
79 #include <machine/cpu.h>
80 #include <machine/board.h>
84 #include <vm/vm_object.h>
85 #include <vm/vm_page.h>
86 #include <vm/vm_map.h>
87 #include <machine/vmparam.h>
88 #include <machine/pcb.h>
89 #include <machine/undefined.h>
90 #include <machine/machdep.h>
91 #include <machine/metadata.h>
92 #include <machine/armreg.h>
93 #include <machine/bus.h>
94 #include <sys/reboot.h>
96 #include <arm/at91/at91board.h>
97 #include <arm/at91/at91var.h>
98 #include <arm/at91/at91soc.h>
99 #include <arm/at91/at91_usartreg.h>
100 #include <arm/at91/at91rm92reg.h>
101 #include <arm/at91/at91sam9g20reg.h>
102 #include <arm/at91/at91sam9g45reg.h>
108 /* Page table for mapping proc0 zero page */
109 #define KERNEL_PT_SYS 0
110 #define KERNEL_PT_KERN 1
111 #define KERNEL_PT_KERN_NUM 22
112 /* L2 table for mapping after kernel */
113 #define KERNEL_PT_AFKERNEL KERNEL_PT_KERN + KERNEL_PT_KERN_NUM
114 #define KERNEL_PT_AFKERNEL_NUM 5
116 /* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */
117 #define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM)
119 struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
121 /* Static device mappings. */
122 const struct devmap_entry at91_devmap[] = {
124 * Map the critical on-board devices. The interrupt vector at
125 * 0xffff0000 makes it impossible to map them PA == VA, so we map all
126 * 0xfffxxxxx addresses to 0xdffxxxxx. This covers all critical devices
127 * on all members of the AT91SAM9 and AT91RM9200 families.
134 /* There's a notion that we should do the rest of these lazily. */
136 * We can't just map the OHCI registers VA == PA, because
137 * AT91xx_xxx_BASE belongs to the userland address space.
138 * We could just choose a different virtual address, but a better
139 * solution would probably be to just use pmap_mapdev() to allocate
140 * KVA, as we don't need the OHCI controller before the vm
141 * initialization is done. However, the AT91 resource allocation
142 * system doesn't know how to use pmap_mapdev() yet.
143 * Care must be taken to ensure PA and VM address do not overlap
148 * Add the ohci controller, and anything else that might be
149 * on this chip select for a VA/PA mapping.
151 /* Internal Memory 1MB */
152 AT91RM92_OHCI_VA_BASE,
157 /* CompactFlash controller. Portion of EBI CS4 1MB */
163 * The next two should be good for the 9260, 9261 and 9G20 since
164 * addresses mapping is the same.
167 /* Internal Memory 1MB */
168 AT91SAM9G20_OHCI_VA_BASE,
169 AT91SAM9G20_OHCI_BASE,
174 AT91SAM9G20_NAND_VA_BASE,
175 AT91SAM9G20_NAND_BASE,
176 AT91SAM9G20_NAND_SIZE,
179 * The next should be good for the 9G45.
182 /* Internal Memory 1MB */
183 AT91SAM9G45_OHCI_VA_BASE,
184 AT91SAM9G45_OHCI_BASE,
190 #ifdef LINUX_BOOT_ABI
192 static int memsize[];
198 uint32_t cr, mdr, mr, *SDRAMC;
199 int banks, rows, cols, bw;
200 #ifdef LINUX_BOOT_ABI
202 * If we found any ATAGs that were for memory, return the first bank.
208 if (at91_is_rm92()) {
209 SDRAMC = (uint32_t *)(AT91_BASE + AT91RM92_SDRAMC_BASE);
210 cr = SDRAMC[AT91RM92_SDRAMC_CR / 4];
211 mr = SDRAMC[AT91RM92_SDRAMC_MR / 4];
212 banks = (cr & AT91RM92_SDRAMC_CR_NB_4) ? 2 : 1;
213 rows = ((cr & AT91RM92_SDRAMC_CR_NR_MASK) >> 2) + 11;
214 cols = (cr & AT91RM92_SDRAMC_CR_NC_MASK) + 8;
215 bw = (mr & AT91RM92_SDRAMC_MR_DBW_16) ? 1 : 2;
216 } else if (at91_cpu_is(AT91_T_SAM9G45)) {
217 SDRAMC = (uint32_t *)(AT91_BASE + AT91SAM9G45_DDRSDRC0_BASE);
218 cr = SDRAMC[AT91SAM9G45_DDRSDRC_CR / 4];
219 mdr = SDRAMC[AT91SAM9G45_DDRSDRC_MDR / 4];
221 rows = ((cr & AT91SAM9G45_DDRSDRC_CR_NR_MASK) >> 2) + 11;
222 cols = (cr & AT91SAM9G45_DDRSDRC_CR_NC_MASK) + 8;
223 bw = (mdr & AT91SAM9G45_DDRSDRC_MDR_DBW_16) ? 1 : 2;
225 /* Fix the calculation for DDR memory */
226 mdr &= AT91SAM9G45_DDRSDRC_MDR_MASK;
227 if (mdr & AT91SAM9G45_DDRSDRC_MDR_LPDDR1 ||
228 mdr & AT91SAM9G45_DDRSDRC_MDR_DDR2) {
229 /* The cols value is 1 higher for DDR */
231 /* DDR has 4 internal banks. */
236 * This should be good for the 9260, 9261, 9G20, 9G35 and 9X25
237 * as addresses and registers are the same.
239 SDRAMC = (uint32_t *)(AT91_BASE + AT91SAM9G20_SDRAMC_BASE);
240 cr = SDRAMC[AT91SAM9G20_SDRAMC_CR / 4];
241 mr = SDRAMC[AT91SAM9G20_SDRAMC_MR / 4];
242 banks = (cr & AT91SAM9G20_SDRAMC_CR_NB_4) ? 2 : 1;
243 rows = ((cr & AT91SAM9G20_SDRAMC_CR_NR_MASK) >> 2) + 11;
244 cols = (cr & AT91SAM9G20_SDRAMC_CR_NC_MASK) + 8;
245 bw = (cr & AT91SAM9G20_SDRAMC_CR_DBW_16) ? 1 : 2;
248 return (1 << (cols + rows + banks + bw));
251 static const char *soc_type_name[] = {
252 [AT91_T_CAP9] = "at91cap9",
253 [AT91_T_RM9200] = "at91rm9200",
254 [AT91_T_SAM9260] = "at91sam9260",
255 [AT91_T_SAM9261] = "at91sam9261",
256 [AT91_T_SAM9263] = "at91sam9263",
257 [AT91_T_SAM9G10] = "at91sam9g10",
258 [AT91_T_SAM9G20] = "at91sam9g20",
259 [AT91_T_SAM9G45] = "at91sam9g45",
260 [AT91_T_SAM9N12] = "at91sam9n12",
261 [AT91_T_SAM9RL] = "at91sam9rl",
262 [AT91_T_SAM9X5] = "at91sam9x5",
263 [AT91_T_NONE] = "UNKNOWN"
266 static const char *soc_subtype_name[] = {
267 [AT91_ST_NONE] = "UNKNOWN",
268 [AT91_ST_RM9200_BGA] = "at91rm9200_bga",
269 [AT91_ST_RM9200_PQFP] = "at91rm9200_pqfp",
270 [AT91_ST_SAM9XE] = "at91sam9xe",
271 [AT91_ST_SAM9G45] = "at91sam9g45",
272 [AT91_ST_SAM9M10] = "at91sam9m10",
273 [AT91_ST_SAM9G46] = "at91sam9g46",
274 [AT91_ST_SAM9M11] = "at91sam9m11",
275 [AT91_ST_SAM9G15] = "at91sam9g15",
276 [AT91_ST_SAM9G25] = "at91sam9g25",
277 [AT91_ST_SAM9G35] = "at91sam9g35",
278 [AT91_ST_SAM9X25] = "at91sam9x25",
279 [AT91_ST_SAM9X35] = "at91sam9x35",
282 struct at91_soc_info soc_info;
285 * Read the SoC ID from the CIDR register and try to match it against the
286 * values we know. If we find a good one, we return true. If not, we
287 * return false. When we find a good one, we also find the subtype
291 at91_try_id(uint32_t dbgu_base)
295 soc_info.cidr = *(volatile uint32_t *)(AT91_BASE + dbgu_base +
297 socid = soc_info.cidr & ~AT91_CPU_VERSION_MASK;
299 soc_info.type = AT91_T_NONE;
300 soc_info.subtype = AT91_ST_NONE;
301 soc_info.family = (soc_info.cidr & AT91_CPU_FAMILY_MASK) >> 20;
302 soc_info.exid = *(volatile uint32_t *)(AT91_BASE + dbgu_base +
307 soc_info.type = AT91_T_CAP9;
309 case AT91_CPU_RM9200:
310 soc_info.type = AT91_T_RM9200;
312 case AT91_CPU_SAM9XE128:
313 case AT91_CPU_SAM9XE256:
314 case AT91_CPU_SAM9XE512:
315 case AT91_CPU_SAM9260:
316 soc_info.type = AT91_T_SAM9260;
317 if (soc_info.family == AT91_FAMILY_SAM9XE)
318 soc_info.subtype = AT91_ST_SAM9XE;
320 case AT91_CPU_SAM9261:
321 soc_info.type = AT91_T_SAM9261;
323 case AT91_CPU_SAM9263:
324 soc_info.type = AT91_T_SAM9263;
326 case AT91_CPU_SAM9G10:
327 soc_info.type = AT91_T_SAM9G10;
329 case AT91_CPU_SAM9G20:
330 soc_info.type = AT91_T_SAM9G20;
332 case AT91_CPU_SAM9G45:
333 soc_info.type = AT91_T_SAM9G45;
335 case AT91_CPU_SAM9N12:
336 soc_info.type = AT91_T_SAM9N12;
338 case AT91_CPU_SAM9RL64:
339 soc_info.type = AT91_T_SAM9RL;
341 case AT91_CPU_SAM9X5:
342 soc_info.type = AT91_T_SAM9X5;
348 switch (soc_info.type) {
350 switch (soc_info.exid) {
351 case AT91_EXID_SAM9G45:
352 soc_info.subtype = AT91_ST_SAM9G45;
354 case AT91_EXID_SAM9G46:
355 soc_info.subtype = AT91_ST_SAM9G46;
357 case AT91_EXID_SAM9M10:
358 soc_info.subtype = AT91_ST_SAM9M10;
360 case AT91_EXID_SAM9M11:
361 soc_info.subtype = AT91_ST_SAM9M11;
366 switch (soc_info.exid) {
367 case AT91_EXID_SAM9G15:
368 soc_info.subtype = AT91_ST_SAM9G15;
370 case AT91_EXID_SAM9G25:
371 soc_info.subtype = AT91_ST_SAM9G25;
373 case AT91_EXID_SAM9G35:
374 soc_info.subtype = AT91_ST_SAM9G35;
376 case AT91_EXID_SAM9X25:
377 soc_info.subtype = AT91_ST_SAM9X25;
379 case AT91_EXID_SAM9X35:
380 soc_info.subtype = AT91_ST_SAM9X35;
388 * Disable interrupts in the DBGU unit...
390 *(volatile uint32_t *)(AT91_BASE + dbgu_base + USART_IDR) = 0xffffffff;
393 * Save the name for later...
395 snprintf(soc_info.name, sizeof(soc_info.name), "%s%s%s",
396 soc_type_name[soc_info.type],
397 soc_info.subtype == AT91_ST_NONE ? "" : " subtype ",
398 soc_info.subtype == AT91_ST_NONE ? "" :
399 soc_subtype_name[soc_info.subtype]);
402 * try to get the matching CPU support.
404 soc_info.soc_data = at91_match_soc(soc_info.type, soc_info.subtype);
405 soc_info.dbgu_base = AT91_BASE + dbgu_base;
414 if (!at91_try_id(AT91_DBGU0))
415 at91_try_id(AT91_DBGU1);
418 #ifdef ARM_MANY_BOARD
419 /* likely belongs in arm/arm/machdep.c, but since board_init is still at91 only... */
420 SET_DECLARE(arm_board_set, const struct arm_board);
422 /* Not yet fully functional, but enough to build ATMEL config */
431 /* Physical and virtual addresses for some global pages */
433 struct pv_addr msgbufpv;
434 struct pv_addr kernelstack;
435 struct pv_addr systempage;
436 struct pv_addr irqstack;
437 struct pv_addr abtstack;
438 struct pv_addr undstack;
441 initarm(struct arm_boot_params *abp)
443 struct pv_addr kernel_l1pt;
444 struct pv_addr dpcpu;
447 vm_offset_t freemempos;
448 vm_offset_t afterkern;
450 vm_offset_t lastaddr;
452 lastaddr = parse_boot_param(abp);
453 arm_physmem_kernaddr = abp->abp_physaddr;
457 /* Do basic tuning, hz etc */
460 freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK;
461 /* Define a macro to simplify memory allocation */
462 #define valloc_pages(var, np) \
463 alloc_pages((var).pv_va, (np)); \
464 (var).pv_pa = (var).pv_va + (abp->abp_physaddr - KERNVIRTADDR);
466 #define alloc_pages(var, np) \
467 (var) = freemempos; \
468 freemempos += (np * PAGE_SIZE); \
469 memset((char *)(var), 0, ((np) * PAGE_SIZE));
471 while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
472 freemempos += PAGE_SIZE;
473 valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
474 for (i = 0; i < NUM_KERNEL_PTS; ++i) {
475 if (!(i % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
476 valloc_pages(kernel_pt_table[i],
477 L2_TABLE_SIZE / PAGE_SIZE);
479 kernel_pt_table[i].pv_va = freemempos -
480 (i % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
482 kernel_pt_table[i].pv_pa =
483 kernel_pt_table[i].pv_va - KERNVIRTADDR +
488 * Allocate a page for the system page mapped to 0x00000000
489 * or 0xffff0000. This page will just contain the system vectors
490 * and can be shared by all processes.
492 valloc_pages(systempage, 1);
494 /* Allocate dynamic per-cpu area. */
495 valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
496 dpcpu_init((void *)dpcpu.pv_va, 0);
498 /* Allocate stacks for all modes */
499 valloc_pages(irqstack, IRQ_STACK_SIZE * MAXCPU);
500 valloc_pages(abtstack, ABT_STACK_SIZE * MAXCPU);
501 valloc_pages(undstack, UND_STACK_SIZE * MAXCPU);
502 valloc_pages(kernelstack, kstack_pages * MAXCPU);
503 valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
506 * Now we start construction of the L1 page table
507 * We start by mapping the L2 page tables into the L1.
508 * This means that we can replace L1 mappings later on if necessary
510 l1pagetable = kernel_l1pt.pv_va;
512 /* Map the L2 pages tables in the L1 page table */
513 pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH,
514 &kernel_pt_table[KERNEL_PT_SYS]);
515 for (i = 0; i < KERNEL_PT_KERN_NUM; i++)
516 pmap_link_l2pt(l1pagetable, KERNBASE + i * L1_S_SIZE,
517 &kernel_pt_table[KERNEL_PT_KERN + i]);
518 pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR,
519 rounddown2(((uint32_t)lastaddr - KERNBASE) + PAGE_SIZE, PAGE_SIZE),
520 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
521 afterkern = round_page(rounddown2(lastaddr + L1_S_SIZE, L1_S_SIZE));
522 for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
523 pmap_link_l2pt(l1pagetable, afterkern + i * L1_S_SIZE,
524 &kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
527 /* Map the vector page. */
528 pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
529 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
531 /* Map the DPCPU pages */
532 pmap_map_chunk(l1pagetable, dpcpu.pv_va, dpcpu.pv_pa, DPCPU_SIZE,
533 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
535 /* Map the stack pages */
536 pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa,
537 IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
538 pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa,
539 ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
540 pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa,
541 UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
542 pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa,
543 kstack_pages * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
545 pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa,
546 L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
547 pmap_map_chunk(l1pagetable, msgbufpv.pv_va, msgbufpv.pv_pa,
548 msgbufsize, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
550 for (i = 0; i < NUM_KERNEL_PTS; ++i) {
551 pmap_map_chunk(l1pagetable, kernel_pt_table[i].pv_va,
552 kernel_pt_table[i].pv_pa, L2_TABLE_SIZE,
553 VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
556 devmap_bootstrap(l1pagetable, at91_devmap);
557 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | DOMAIN_CLIENT);
558 cpu_setttb(kernel_l1pt.pv_pa);
560 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2));
565 * Initialize all the clocks, so that the console can work. We can only
566 * do this if at91_soc_id() was able to fill in the support data. Even
567 * if we can't init the clocks, still try to do a console init so we can
568 * try to print the error message about missing soc support. There's a
569 * chance the printf will work if the bootloader set up the DBGU.
571 if (soc_info.soc_data != NULL) {
572 soc_info.soc_data->soc_clock_init();
573 at91_pmc_init_clock();
578 if (soc_info.soc_data == NULL)
579 printf("Warning: No soc support for %s found.\n", soc_info.name);
581 memsize = board_init();
583 printf("board_init() failed, cannot determine ram size; "
585 memsize = 16 * 1024 * 1024;
588 /* Enable MMU (set SCTLR), and do other cpu-specific setup. */
589 cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE);
593 * Pages were allocated during the secondary bootstrap for the
594 * stacks for different CPU modes.
595 * We must now set the r13 registers in the different CPU modes to
596 * point to these stacks.
597 * Since the ARM stacks use STMFD etc. we must set r13 to the top end
598 * of the stack memory.
603 * We must now clean the cache again....
604 * Cleaning may be done by reading new data to displace any
605 * dirty data in the cache. This will have happened in cpu_setttb()
606 * but since we are boot strapping the addresses used for the read
607 * may have just been remapped and thus the cache could be out
608 * of sync. A re-clean after the switch will cure this.
609 * After booting there are no gross relocations of the kernel thus
610 * this problem will not occur after initarm().
612 cpu_idcache_wbinv_all();
616 init_proc0(kernelstack.pv_va);
618 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
620 pmap_curmaxkvaddr = afterkern + L1_S_SIZE * (KERNEL_PT_KERN_NUM - 1);
621 /* Always use the 256MB of KVA we have available between the kernel and devices */
622 vm_max_kernel_address = KERNVIRTADDR + (256 << 20);
623 pmap_bootstrap(freemempos, &kernel_l1pt);
624 msgbufp = (void*)msgbufpv.pv_va;
625 msgbufinit(msgbufp, msgbufsize);
629 * Add the physical ram we have available.
631 * Exclude the kernel, and all the things we allocated which immediately
632 * follow the kernel, from the VM allocation pool but not from crash
633 * dumps. virtual_avail is a global variable which tracks the kva we've
634 * "allocated" while setting up pmaps.
636 * Prepare the list of physical memory available to the vm subsystem.
638 arm_physmem_hardware_region(PHYSADDR, memsize);
639 arm_physmem_exclude_region(abp->abp_physaddr,
640 virtual_avail - KERNVIRTADDR, EXFLAG_NOALLOC);
641 arm_physmem_init_kernel_globals();
643 init_param2(physmem);
645 return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
646 sizeof(struct pcb)));
651 * These functions are handled elsewhere, so make them nops here.
654 cpu_startprofclock(void)
660 cpu_stopprofclock(void)
676 if (soc_info.soc_data)
677 soc_info.soc_data->soc_delay(n);
685 if (soc_info.soc_data)
686 soc_info.soc_data->soc_reset();