2 * Copyright (c) 2006 Bernd Walter. All rights reserved.
3 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
4 * Copyright (c) 2010 Greg Ansley. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include "opt_platform.h"
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
38 #include <sys/endian.h>
39 #include <sys/kernel.h>
40 #include <sys/kthread.h>
42 #include <sys/malloc.h>
43 #include <sys/module.h>
44 #include <sys/mutex.h>
45 #include <sys/queue.h>
46 #include <sys/resource.h>
48 #include <sys/sysctl.h>
50 #include <sys/timetc.h>
51 #include <sys/watchdog.h>
53 #include <machine/bus.h>
54 #include <machine/cpu.h>
55 #include <machine/cpufunc.h>
56 #include <machine/resource.h>
57 #include <machine/intr.h>
59 #include <arm/at91/at91var.h>
60 #include <arm/at91/at91_mcireg.h>
61 #include <arm/at91/at91_pdcreg.h>
63 #include <dev/mmc/bridge.h>
64 #include <dev/mmc/mmcreg.h>
65 #include <dev/mmc/mmcbrvar.h>
68 #include <dev/fdt/fdt_common.h>
69 #include <dev/ofw/ofw_bus.h>
70 #include <dev/ofw/ofw_bus_subr.h>
78 * About running the MCI bus above 25MHz
80 * Historically, the MCI bus has been run at 30MHz on systems with a 60MHz
81 * master clock, in part due to a bug in dev/mmc.c making always request
82 * 30MHz, and in part over clocking the bus because 15MHz was too slow.
83 * Fixing that bug causes the mmc driver to request a 25MHz clock (as it
84 * should) and the logic in at91_mci_update_ios() picks the highest speed that
85 * doesn't exceed that limit. With a 60MHz MCK that would be 15MHz, and
86 * that's a real performance buzzkill when you've been getting away with 30MHz
89 * By defining AT91_MCI_ALLOW_OVERCLOCK (or setting the allow_overclock=1
90 * device hint or sysctl) you can enable logic in at91_mci_update_ios() to
91 * overlcock the SD bus a little by running it at MCK / 2 when the requested
92 * speed is 25MHz and the next highest speed is 15MHz or less. This appears
93 * to work on virtually all SD cards, since it is what this driver has been
94 * doing prior to the introduction of this option, where the overclocking vs
95 * underclocking decision was automaticly "overclock". Modern SD cards can
96 * run at 45mhz/1-bit in standard mode (high speed mode enable commands not
97 * sent) without problems.
99 * Speaking of high-speed mode, the rm9200 manual says the MCI device supports
100 * the SD v1.0 specification and can run up to 50MHz. This is interesting in
101 * that the SD v1.0 spec caps the speed at 25MHz; high speed mode was added in
102 * the v1.10 spec. Furthermore, high speed mode doesn't just crank up the
103 * clock, it alters the signal timing. The rm9200 MCI device doesn't support
104 * these altered timings. So while speeds over 25MHz may work, they only work
105 * in what the SD spec calls "default" speed mode, and it amounts to violating
106 * the spec by overclocking the bus.
108 * If you also enable 4-wire mode it's possible transfers faster than 25MHz
109 * will fail. On the AT91RM9200, due to bugs in the bus contention logic, if
110 * you have the USB host device and OHCI driver enabled will fail. Even
111 * underclocking to 15MHz, intermittant overrun and underrun errors occur.
112 * Note that you don't even need to have usb devices attached to the system,
113 * the errors begin to occur as soon as the OHCI driver sets the register bit
114 * to enable periodic transfers. It appears (based on brief investigation)
115 * that the usb host controller uses so much ASB bandwidth that sometimes the
116 * DMA for MCI transfers doesn't get a bus grant in time and data gets
117 * dropped. Adding even a modicum of network activity changes the symptom
118 * from intermittant to very frequent. Members of the AT91SAM9 family have
119 * corrected this problem, or are at least better about their use of the bus.
121 #ifndef AT91_MCI_ALLOW_OVERCLOCK
122 #define AT91_MCI_ALLOW_OVERCLOCK 1
126 * Allocate 2 bounce buffers we'll use to endian-swap the data due to the rm9200
127 * erratum. We use a pair of buffers because when reading that lets us begin
128 * endian-swapping the data in the first buffer while the DMA is reading into
129 * the second buffer. (We can't use the same trick for writing because we might
130 * not get all the data in the 2nd buffer swapped before the hardware needs it;
131 * dealing with that would add complexity to the driver.)
133 * The buffers are sized at 16K each due to the way the busdma cache sync
134 * operations work on arm. A dcache_inv_range() operation on a range larger
135 * than 16K gets turned into a dcache_wbinv_all(). That needlessly flushes the
136 * entire data cache, impacting overall system performance.
139 #define BBSIZE (16*1024)
140 #define MAX_BLOCKS ((BBSIZE*BBCOUNT)/512)
142 static int mci_debug;
144 struct at91_mci_softc {
145 void *intrhand; /* Interrupt handle */
148 #define CAP_HAS_4WIRE 1 /* Has 4 wire bus */
149 #define CAP_NEEDS_BYTESWAP 2 /* broken hardware needing bounce */
150 #define CAP_MCI1_REV2XX 4 /* MCI 1 rev 2.x */
152 #define PENDING_CMD 0x01
153 #define PENDING_STOP 0x02
154 #define CMD_MULTIREAD 0x10
155 #define CMD_MULTIWRITE 0x20
158 struct resource *irq_res; /* IRQ resource */
159 struct resource *mem_res; /* Memory resource */
161 bus_dma_tag_t dmatag;
162 struct mmc_host host;
164 struct mmc_request *req;
165 struct mmc_command *curcmd;
166 bus_dmamap_t bbuf_map[BBCOUNT];
167 char * bbuf_vaddr[BBCOUNT]; /* bounce bufs in KVA space */
168 uint32_t bbuf_len[BBCOUNT]; /* len currently queued for bounce buf */
169 uint32_t bbuf_curidx; /* which bbuf is the active DMA buffer */
170 uint32_t xfer_offset; /* offset so far into caller's buf */
173 /* bus entry points */
174 static int at91_mci_probe(device_t dev);
175 static int at91_mci_attach(device_t dev);
176 static int at91_mci_detach(device_t dev);
177 static void at91_mci_intr(void *);
179 /* helper routines */
180 static int at91_mci_activate(device_t dev);
181 static void at91_mci_deactivate(device_t dev);
182 static int at91_mci_is_mci1rev2xx(void);
184 #define AT91_MCI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
185 #define AT91_MCI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
186 #define AT91_MCI_LOCK_INIT(_sc) \
187 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
189 #define AT91_MCI_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
190 #define AT91_MCI_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
191 #define AT91_MCI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
193 static inline uint32_t
194 RD4(struct at91_mci_softc *sc, bus_size_t off)
196 return (bus_read_4(sc->mem_res, off));
200 WR4(struct at91_mci_softc *sc, bus_size_t off, uint32_t val)
202 bus_write_4(sc->mem_res, off, val);
206 at91_bswap_buf(struct at91_mci_softc *sc, void * dptr, void * sptr, uint32_t memsize)
208 uint32_t * dst = (uint32_t *)dptr;
209 uint32_t * src = (uint32_t *)sptr;
213 * If the hardware doesn't need byte-swapping, let bcopy() do the
214 * work. Use bounce buffer even if we don't need byteswap, since
215 * buffer may straddle a page boundry, and we don't handle
216 * multi-segment transfers in hardware. Seen from 'bsdlabel -w' which
217 * uses raw geom access to the volume. Greg Ansley (gja (at)
220 if (!(sc->sc_cap & CAP_NEEDS_BYTESWAP)) {
221 memcpy(dptr, sptr, memsize);
226 * Nice performance boost for slightly unrolling this loop.
227 * (But very little extra boost for further unrolling it.)
229 for (i = 0; i < memsize; i += 16) {
230 *dst++ = bswap32(*src++);
231 *dst++ = bswap32(*src++);
232 *dst++ = bswap32(*src++);
233 *dst++ = bswap32(*src++);
236 /* Mop up the last 1-3 words, if any. */
237 for (i = 0; i < (memsize & 0x0F); i += 4) {
238 *dst++ = bswap32(*src++);
243 at91_mci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
247 *(bus_addr_t *)arg = segs[0].ds_addr;
251 at91_mci_pdc_disable(struct at91_mci_softc *sc)
253 WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS);
256 WR4(sc, PDC_RNPR, 0);
257 WR4(sc, PDC_RNCR, 0);
260 WR4(sc, PDC_TNPR, 0);
261 WR4(sc, PDC_TNCR, 0);
265 * Reset the controller, then restore most of the current state.
267 * This is called after detecting an error. It's also called after stopping a
268 * multi-block write, to un-wedge the device so that it will handle the NOTBUSY
269 * signal correctly. See comments in at91_mci_stop_done() for more details.
271 static void at91_mci_reset(struct at91_mci_softc *sc)
278 at91_mci_pdc_disable(sc);
280 /* save current state */
282 imr = RD4(sc, MCI_IMR);
283 mr = RD4(sc, MCI_MR) & 0x7fff;
284 sdcr = RD4(sc, MCI_SDCR);
285 dtor = RD4(sc, MCI_DTOR);
287 /* reset the controller */
289 WR4(sc, MCI_IDR, 0xffffffff);
290 WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST);
294 WR4(sc, MCI_CR, MCI_CR_MCIEN|MCI_CR_PWSEN);
296 WR4(sc, MCI_SDCR, sdcr);
297 WR4(sc, MCI_DTOR, dtor);
298 WR4(sc, MCI_IER, imr);
301 * Make sure sdio interrupts will fire. Not sure why reading
302 * SR ensures that, but this is in the linux driver.
309 at91_mci_init(device_t dev)
311 struct at91_mci_softc *sc = device_get_softc(dev);
314 WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST); /* device into reset */
315 WR4(sc, MCI_IDR, 0xffffffff); /* Turn off interrupts */
316 WR4(sc, MCI_DTOR, MCI_DTOR_DTOMUL_1M | 1);
317 val = MCI_MR_PDCMODE;
318 val |= 0x34a; /* PWSDIV = 3; CLKDIV = 74 */
319 // if (sc->sc_cap & CAP_MCI1_REV2XX)
320 // val |= MCI_MR_RDPROOF | MCI_MR_WRPROOF;
321 WR4(sc, MCI_MR, val);
322 #ifndef AT91_MCI_SLOT_B
323 WR4(sc, MCI_SDCR, 0); /* SLOT A, 1 bit bus */
326 * XXX Really should add second "unit" but nobody using using
327 * a two slot card that we know of. XXX
329 WR4(sc, MCI_SDCR, 1); /* SLOT B, 1 bit bus */
332 * Enable controller, including power-save. The slower clock
333 * of the power-save mode is only in effect when there is no
334 * transfer in progress, so it can be left in this mode all
337 WR4(sc, MCI_CR, MCI_CR_MCIEN|MCI_CR_PWSEN);
341 at91_mci_fini(device_t dev)
343 struct at91_mci_softc *sc = device_get_softc(dev);
345 WR4(sc, MCI_IDR, 0xffffffff); /* Turn off interrupts */
346 at91_mci_pdc_disable(sc);
347 WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST); /* device into reset */
351 at91_mci_probe(device_t dev)
354 if (!ofw_bus_is_compatible(dev, "atmel,hsmci"))
357 device_set_desc(dev, "MCI mmc/sd host bridge");
362 at91_mci_attach(device_t dev)
364 struct at91_mci_softc *sc = device_get_softc(dev);
365 struct sysctl_ctx_list *sctx;
366 struct sysctl_oid *soid;
370 sctx = device_get_sysctl_ctx(dev);
371 soid = device_get_sysctl_tree(dev);
376 sc->sc_cap |= CAP_NEEDS_BYTESWAP;
378 * MCI1 Rev 2 controllers need some workarounds, flag if so.
380 if (at91_mci_is_mci1rev2xx())
381 sc->sc_cap |= CAP_MCI1_REV2XX;
383 err = at91_mci_activate(dev);
387 AT91_MCI_LOCK_INIT(sc);
393 * Allocate DMA tags and maps and bounce buffers.
395 * The parms in the tag_create call cause the dmamem_alloc call to
396 * create each bounce buffer as a single contiguous buffer of BBSIZE
397 * bytes aligned to a 4096 byte boundary.
399 * Do not use DMA_COHERENT for these buffers because that maps the
400 * memory as non-cachable, which prevents cache line burst fills/writes,
401 * which is something we need since we're trying to overlap the
402 * byte-swapping with the DMA operations.
404 err = bus_dma_tag_create(bus_get_dma_tag(dev), 4096, 0,
405 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
406 BBSIZE, 1, BBSIZE, 0, NULL, NULL, &sc->dmatag);
410 for (i = 0; i < BBCOUNT; ++i) {
411 err = bus_dmamem_alloc(sc->dmatag, (void **)&sc->bbuf_vaddr[i],
412 BUS_DMA_NOWAIT, &sc->bbuf_map[i]);
418 * Activate the interrupt
420 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
421 NULL, at91_mci_intr, sc, &sc->intrhand);
423 AT91_MCI_LOCK_DESTROY(sc);
428 * Allow 4-wire to be initially set via #define.
429 * Allow a device hint to override that.
430 * Allow a sysctl to override that.
432 #if defined(AT91_MCI_HAS_4WIRE) && AT91_MCI_HAS_4WIRE != 0
435 resource_int_value(device_get_name(dev), device_get_unit(dev),
436 "4wire", &sc->has_4wire);
437 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "4wire",
438 CTLFLAG_RW, &sc->has_4wire, 0, "has 4 wire SD Card bus");
440 sc->sc_cap |= CAP_HAS_4WIRE;
442 sc->allow_overclock = AT91_MCI_ALLOW_OVERCLOCK;
443 resource_int_value(device_get_name(dev), device_get_unit(dev),
444 "allow_overclock", &sc->allow_overclock);
445 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "allow_overclock",
446 CTLFLAG_RW, &sc->allow_overclock, 0,
447 "Allow up to 30MHz clock for 25MHz request when next highest speed 15MHz or less.");
450 * Our real min freq is master_clock/512, but upper driver layers are
451 * going to set the min speed during card discovery, and the right speed
452 * for that is 400kHz, so advertise a safe value just under that.
454 * For max speed, while the rm9200 manual says the max is 50mhz, it also
455 * says it supports only the SD v1.0 spec, which means the real limit is
456 * 25mhz. On the other hand, historical use has been to slightly violate
457 * the standard by running the bus at 30MHz. For more information on
458 * that, see the comments at the top of this file.
460 sc->host.f_min = 375000;
461 sc->host.f_max = at91_master_clock / 2;
462 if (sc->host.f_max > 25000000)
463 sc->host.f_max = 25000000;
464 sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
466 if (sc->sc_cap & CAP_HAS_4WIRE)
467 sc->host.caps |= MMC_CAP_4_BIT_DATA;
469 child = device_add_child(dev, "mmc", 0);
470 device_set_ivars(dev, &sc->host);
471 err = bus_generic_attach(dev);
474 at91_mci_deactivate(dev);
479 at91_mci_detach(device_t dev)
481 struct at91_mci_softc *sc = device_get_softc(dev);
484 at91_mci_deactivate(dev);
486 bus_dmamem_free(sc->dmatag, sc->bbuf_vaddr[0], sc->bbuf_map[0]);
487 bus_dmamem_free(sc->dmatag, sc->bbuf_vaddr[1], sc->bbuf_map[1]);
488 bus_dma_tag_destroy(sc->dmatag);
490 return (EBUSY); /* XXX */
494 at91_mci_activate(device_t dev)
496 struct at91_mci_softc *sc;
499 sc = device_get_softc(dev);
501 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
503 if (sc->mem_res == NULL)
507 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
509 if (sc->irq_res == NULL)
514 at91_mci_deactivate(dev);
519 at91_mci_deactivate(device_t dev)
521 struct at91_mci_softc *sc;
523 sc = device_get_softc(dev);
525 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
527 bus_generic_detach(sc->dev);
529 bus_release_resource(dev, SYS_RES_MEMORY,
530 rman_get_rid(sc->mem_res), sc->mem_res);
533 bus_release_resource(dev, SYS_RES_IRQ,
534 rman_get_rid(sc->irq_res), sc->irq_res);
540 at91_mci_is_mci1rev2xx(void)
543 switch (soc_info.type) {
557 at91_mci_update_ios(device_t brdev, device_t reqdev)
559 struct at91_mci_softc *sc;
564 sc = device_get_softc(brdev);
568 * Calculate our closest available clock speed that doesn't exceed the
571 * When overclocking is allowed, the requested clock is 25MHz, the
572 * computed frequency is 15MHz or smaller and clockdiv is 1, use
573 * clockdiv of 0 to double that. If less than 12.5MHz, double
574 * regardless of the overclocking setting.
576 * Whatever we come up with, store it back into ios->clock so that the
577 * upper layer drivers can report the actual speed of the bus.
579 if (ios->clock == 0) {
580 WR4(sc, MCI_CR, MCI_CR_MCIDIS);
583 WR4(sc, MCI_CR, MCI_CR_MCIEN|MCI_CR_PWSEN);
584 if ((at91_master_clock % (ios->clock * 2)) == 0)
585 clkdiv = ((at91_master_clock / ios->clock) / 2) - 1;
587 clkdiv = (at91_master_clock / ios->clock) / 2;
588 freq = at91_master_clock / ((clkdiv+1) * 2);
589 if (clkdiv == 1 && ios->clock == 25000000 && freq <= 15000000) {
590 if (sc->allow_overclock || freq <= 12500000) {
592 freq = at91_master_clock / ((clkdiv+1) * 2);
597 if (ios->bus_width == bus_width_4)
598 WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) | MCI_SDCR_SDCBUS);
600 WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) & ~MCI_SDCR_SDCBUS);
601 WR4(sc, MCI_MR, (RD4(sc, MCI_MR) & ~MCI_MR_CLKDIV) | clkdiv);
602 /* Do we need a settle time here? */
603 /* XXX We need to turn the device on/off here with a GPIO pin */
608 at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd)
611 struct mmc_data *data;
616 /* XXX Upper layers don't always set this */
619 /* Begin setting up command register. */
623 if (sc->host.ios.bus_mode == opendrain)
624 cmdr |= MCI_CMDR_OPDCMD;
626 /* Set up response handling. Allow max timeout for responses. */
628 if (MMC_RSP(cmd->flags) == MMC_RSP_NONE)
629 cmdr |= MCI_CMDR_RSPTYP_NO;
631 cmdr |= MCI_CMDR_MAXLAT;
632 if (cmd->flags & MMC_RSP_136)
633 cmdr |= MCI_CMDR_RSPTYP_136;
635 cmdr |= MCI_CMDR_RSPTYP_48;
639 * If there is no data transfer, just set up the right interrupt mask
640 * and start the command.
642 * The interrupt mask needs to be CMDRDY plus all non-data-transfer
643 * errors. It's important to leave the transfer-related errors out, to
644 * avoid spurious timeout or crc errors on a STOP command following a
645 * multiblock read. When a multiblock read is in progress, sending a
646 * STOP in the middle of a block occasionally triggers such errors, but
647 * we're totally disinterested in them because we've already gotten all
648 * the data we wanted without error before sending the STOP command.
652 uint32_t ier = MCI_SR_CMDRDY |
653 MCI_SR_RTOE | MCI_SR_RENDE |
654 MCI_SR_RCRCE | MCI_SR_RDIRE | MCI_SR_RINDE;
656 at91_mci_pdc_disable(sc);
658 if (cmd->opcode == MMC_STOP_TRANSMISSION)
659 cmdr |= MCI_CMDR_TRCMD_STOP;
661 /* Ignore response CRC on CMD2 and ACMD41, per standard. */
663 if (cmd->opcode == MMC_SEND_OP_COND ||
664 cmd->opcode == ACMD_SD_SEND_OP_COND)
665 ier &= ~MCI_SR_RCRCE;
668 printf("CMDR %x (opcode %d) ARGR %x no data\n",
669 cmdr, cmd->opcode, cmd->arg);
671 WR4(sc, MCI_ARGR, cmd->arg);
672 WR4(sc, MCI_CMDR, cmdr);
673 WR4(sc, MCI_IDR, 0xffffffff);
674 WR4(sc, MCI_IER, ier);
678 /* There is data, set up the transfer-related parts of the command. */
680 if (data->flags & MMC_DATA_READ)
681 cmdr |= MCI_CMDR_TRDIR;
683 if (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE))
684 cmdr |= MCI_CMDR_TRCMD_START;
686 if (data->flags & MMC_DATA_STREAM)
687 cmdr |= MCI_CMDR_TRTYP_STREAM;
688 else if (data->flags & MMC_DATA_MULTI) {
689 cmdr |= MCI_CMDR_TRTYP_MULTIPLE;
690 sc->flags |= (data->flags & MMC_DATA_READ) ?
691 CMD_MULTIREAD : CMD_MULTIWRITE;
695 * Disable PDC until we're ready.
697 * Set block size and turn on PDC mode for dma xfer.
698 * Note that the block size is the smaller of the amount of data to be
699 * transferred, or 512 bytes. The 512 size is fixed by the standard;
700 * smaller blocks are possible, but never larger.
703 WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
705 mr = RD4(sc,MCI_MR) & ~MCI_MR_BLKLEN;
706 mr |= min(data->len, 512) << 16;
707 WR4(sc, MCI_MR, mr | MCI_MR_PDCMODE|MCI_MR_PDCPADV);
712 * Use bounce buffers even if we don't need to byteswap, because doing
713 * multi-block IO with large DMA buffers is way fast (compared to
714 * single-block IO), even after incurring the overhead of also copying
715 * from/to the caller's buffers (which may be in non-contiguous physical
718 * In an ideal non-byteswap world we could create a dma tag that allows
719 * for discontiguous segments and do the IO directly from/to the
720 * caller's buffer(s), using ENDRX/ENDTX interrupts to chain the
721 * discontiguous buffers through the PDC. Someday.
723 * If a read is bigger than 2k, split it in half so that we can start
724 * byte-swapping the first half while the second half is on the wire.
725 * It would be best if we could split it into 8k chunks, but we can't
726 * always keep up with the byte-swapping due to other system activity,
727 * and if an RXBUFF interrupt happens while we're still handling the
728 * byte-swap from the prior buffer (IE, we haven't returned from
729 * handling the prior interrupt yet), then data will get dropped on the
730 * floor and we can't easily recover from that. The right fix for that
731 * would be to have the interrupt handling only keep the DMA flowing and
732 * enqueue filled buffers to be byte-swapped in a non-interrupt context.
733 * Even that won't work on the write side of things though; in that
734 * context we have to have all the data ready to go before starting the
737 * XXX what about stream transfers?
742 if (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) {
744 uint32_t remaining = data->len;
748 if (remaining > (BBCOUNT*BBSIZE))
749 panic("IO read size exceeds MAXDATA\n");
751 if (data->flags & MMC_DATA_READ) {
752 if (remaining > 2048) // XXX
756 err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[0],
757 sc->bbuf_vaddr[0], len, at91_mci_getaddr,
758 &paddr, BUS_DMA_NOWAIT);
760 panic("IO read dmamap_load failed\n");
761 bus_dmamap_sync(sc->dmatag, sc->bbuf_map[0],
762 BUS_DMASYNC_PREREAD);
763 WR4(sc, PDC_RPR, paddr);
764 WR4(sc, PDC_RCR, len / 4);
765 sc->bbuf_len[0] = len;
767 if (remaining == 0) {
771 err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[1],
772 sc->bbuf_vaddr[1], len, at91_mci_getaddr,
773 &paddr, BUS_DMA_NOWAIT);
775 panic("IO read dmamap_load failed\n");
776 bus_dmamap_sync(sc->dmatag, sc->bbuf_map[1],
777 BUS_DMASYNC_PREREAD);
778 WR4(sc, PDC_RNPR, paddr);
779 WR4(sc, PDC_RNCR, len / 4);
780 sc->bbuf_len[1] = len;
783 WR4(sc, PDC_PTCR, PDC_PTCR_RXTEN);
785 len = min(BBSIZE, remaining);
787 * If this is MCI1 revision 2xx controller, apply
788 * a work-around for the "Data Write Operation and
789 * number of bytes" erratum.
791 if ((sc->sc_cap & CAP_MCI1_REV2XX) && len < 12) {
793 memset(sc->bbuf_vaddr[0], 0, 12);
795 at91_bswap_buf(sc, sc->bbuf_vaddr[0], data->data, len);
796 err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[0],
797 sc->bbuf_vaddr[0], len, at91_mci_getaddr,
798 &paddr, BUS_DMA_NOWAIT);
800 panic("IO write dmamap_load failed\n");
801 bus_dmamap_sync(sc->dmatag, sc->bbuf_map[0],
802 BUS_DMASYNC_PREWRITE);
803 WR4(sc, PDC_TPR,paddr);
804 WR4(sc, PDC_TCR, len / 4);
805 sc->bbuf_len[0] = len;
807 if (remaining == 0) {
811 at91_bswap_buf(sc, sc->bbuf_vaddr[1],
812 ((char *)data->data)+BBSIZE, len);
813 err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[1],
814 sc->bbuf_vaddr[1], len, at91_mci_getaddr,
815 &paddr, BUS_DMA_NOWAIT);
817 panic("IO write dmamap_load failed\n");
818 bus_dmamap_sync(sc->dmatag, sc->bbuf_map[1],
819 BUS_DMASYNC_PREWRITE);
820 WR4(sc, PDC_TNPR, paddr);
821 WR4(sc, PDC_TNCR, len / 4);
822 sc->bbuf_len[1] = len;
825 /* do not enable PDC xfer until CMDRDY asserted */
827 data->xfer_len = 0; /* XXX what's this? appears to be unused. */
831 printf("CMDR %x (opcode %d) ARGR %x with data len %d\n",
832 cmdr, cmd->opcode, cmd->arg, cmd->data->len);
834 WR4(sc, MCI_ARGR, cmd->arg);
835 WR4(sc, MCI_CMDR, cmdr);
836 WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_CMDRDY);
840 at91_mci_next_operation(struct at91_mci_softc *sc)
842 struct mmc_request *req;
848 if (sc->flags & PENDING_CMD) {
849 sc->flags &= ~PENDING_CMD;
850 at91_mci_start_cmd(sc, req->cmd);
852 } else if (sc->flags & PENDING_STOP) {
853 sc->flags &= ~PENDING_STOP;
854 at91_mci_start_cmd(sc, req->stop);
858 WR4(sc, MCI_IDR, 0xffffffff);
861 //printf("req done\n");
866 at91_mci_request(device_t brdev, device_t reqdev, struct mmc_request *req)
868 struct at91_mci_softc *sc = device_get_softc(brdev);
871 if (sc->req != NULL) {
875 //printf("new req\n");
877 sc->flags = PENDING_CMD;
879 sc->flags |= PENDING_STOP;
880 at91_mci_next_operation(sc);
886 at91_mci_get_ro(device_t brdev, device_t reqdev)
892 at91_mci_acquire_host(device_t brdev, device_t reqdev)
894 struct at91_mci_softc *sc = device_get_softc(brdev);
899 msleep(sc, &sc->sc_mtx, PZERO, "mciah", hz / 5);
906 at91_mci_release_host(device_t brdev, device_t reqdev)
908 struct at91_mci_softc *sc = device_get_softc(brdev);
918 at91_mci_read_done(struct at91_mci_softc *sc, uint32_t sr)
920 struct mmc_command *cmd = sc->curcmd;
921 char * dataptr = (char *)cmd->data->data;
922 uint32_t curidx = sc->bbuf_curidx;
923 uint32_t len = sc->bbuf_len[curidx];
926 * We arrive here when a DMA transfer for a read is done, whether it's
927 * a single or multi-block read.
929 * We byte-swap the buffer that just completed, and if that is the
930 * last buffer that's part of this read then we move on to the next
931 * operation, otherwise we wait for another ENDRX for the next bufer.
934 bus_dmamap_sync(sc->dmatag, sc->bbuf_map[curidx], BUS_DMASYNC_POSTREAD);
935 bus_dmamap_unload(sc->dmatag, sc->bbuf_map[curidx]);
937 at91_bswap_buf(sc, dataptr + sc->xfer_offset, sc->bbuf_vaddr[curidx], len);
940 printf("read done sr %x curidx %d len %d xfer_offset %d\n",
941 sr, curidx, len, sc->xfer_offset);
944 sc->xfer_offset += len;
945 sc->bbuf_curidx = !curidx; /* swap buffers */
948 * If we've transferred all the data, move on to the next operation.
950 * If we're still transferring the last buffer, RNCR is already zero but
951 * we have to write a zero anyway to clear the ENDRX status so we don't
952 * re-interrupt until the last buffer is done.
954 if (sc->xfer_offset == cmd->data->len) {
955 WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
956 cmd->error = MMC_ERR_NONE;
957 at91_mci_next_operation(sc);
959 WR4(sc, PDC_RNCR, 0);
960 WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_ENDRX);
965 at91_mci_write_done(struct at91_mci_softc *sc, uint32_t sr)
967 struct mmc_command *cmd = sc->curcmd;
970 * We arrive here when the entire DMA transfer for a write is done,
971 * whether it's a single or multi-block write. If it's multi-block we
972 * have to immediately move on to the next operation which is to send
973 * the stop command. If it's a single-block transfer we need to wait
974 * for NOTBUSY, but if that's already asserted we can avoid another
975 * interrupt and just move on to completing the request right away.
978 WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
980 bus_dmamap_sync(sc->dmatag, sc->bbuf_map[sc->bbuf_curidx],
981 BUS_DMASYNC_POSTWRITE);
982 bus_dmamap_unload(sc->dmatag, sc->bbuf_map[sc->bbuf_curidx]);
984 if ((cmd->data->flags & MMC_DATA_MULTI) || (sr & MCI_SR_NOTBUSY)) {
985 cmd->error = MMC_ERR_NONE;
986 at91_mci_next_operation(sc);
988 WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_NOTBUSY);
993 at91_mci_notbusy(struct at91_mci_softc *sc)
995 struct mmc_command *cmd = sc->curcmd;
998 * We arrive here by either completion of a single-block write, or
999 * completion of the stop command that ended a multi-block write (and,
1000 * I suppose, after a card-select or erase, but I haven't tested
1001 * those). Anyway, we're done and it's time to move on to the next
1005 cmd->error = MMC_ERR_NONE;
1006 at91_mci_next_operation(sc);
1010 at91_mci_stop_done(struct at91_mci_softc *sc, uint32_t sr)
1012 struct mmc_command *cmd = sc->curcmd;
1015 * We arrive here after receiving CMDRDY for a MMC_STOP_TRANSMISSION
1016 * command. Depending on the operation being stopped, we may have to
1017 * do some unusual things to work around hardware bugs.
1021 * This is known to be true of at91rm9200 hardware; it may or may not
1022 * apply to more recent chips:
1024 * After stopping a multi-block write, the NOTBUSY bit in MCI_SR does
1025 * not properly reflect the actual busy state of the card as signaled
1026 * on the DAT0 line; it always claims the card is not-busy. If we
1027 * believe that and let operations continue, following commands will
1028 * fail with response timeouts (except of course MMC_SEND_STATUS -- it
1029 * indicates the card is busy in the PRG state, which was the smoking
1030 * gun that showed MCI_SR NOTBUSY was not tracking DAT0 correctly).
1032 * The atmel docs are emphatic: "This flag [NOTBUSY] must be used only
1033 * for Write Operations." I guess technically since we sent a stop
1034 * it's not a write operation anymore. But then just what did they
1035 * think it meant for the stop command to have "...an optional busy
1036 * signal transmitted on the data line" according to the SD spec?
1038 * I tried a variety of things to un-wedge the MCI and get the status
1039 * register to reflect NOTBUSY correctly again, but the only thing
1040 * that worked was a full device reset. It feels like an awfully big
1041 * hammer, but doing a full reset after every multiblock write is
1042 * still faster than doing single-block IO (by almost two orders of
1043 * magnitude: 20KB/sec improves to about 1.8MB/sec best case).
1045 * After doing the reset, wait for a NOTBUSY interrupt before
1046 * continuing with the next operation.
1048 * This workaround breaks multiwrite on the rev2xx parts, but some other
1049 * workaround is needed.
1051 if ((sc->flags & CMD_MULTIWRITE) && (sc->sc_cap & CAP_NEEDS_BYTESWAP)) {
1053 WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_NOTBUSY);
1058 * This is known to be true of at91rm9200 hardware; it may or may not
1059 * apply to more recent chips:
1061 * After stopping a multi-block read, loop to read and discard any
1062 * data that coasts in after we sent the stop command. The docs don't
1063 * say anything about it, but empirical testing shows that 1-3
1064 * additional words of data get buffered up in some unmentioned
1065 * internal fifo and if we don't read and discard them here they end
1066 * up on the front of the next read DMA transfer we do.
1068 * This appears to be unnecessary for rev2xx parts.
1070 if ((sc->flags & CMD_MULTIREAD) && (sc->sc_cap & CAP_NEEDS_BYTESWAP)) {
1075 sr = RD4(sc, MCI_SR);
1076 if (sr & MCI_SR_RXRDY) {
1080 } while (sr & MCI_SR_RXRDY);
1084 cmd->error = MMC_ERR_NONE;
1085 at91_mci_next_operation(sc);
1090 at91_mci_cmdrdy(struct at91_mci_softc *sc, uint32_t sr)
1092 struct mmc_command *cmd = sc->curcmd;
1099 * We get here at the end of EVERY command. We retrieve the command
1100 * response (if any) then decide what to do next based on the command.
1103 if (cmd->flags & MMC_RSP_PRESENT) {
1104 for (i = 0; i < ((cmd->flags & MMC_RSP_136) ? 4 : 1); i++) {
1105 cmd->resp[i] = RD4(sc, MCI_RSPR + i * 4);
1107 printf("RSPR[%d] = %x sr=%x\n", i, cmd->resp[i], sr);
1112 * If this was a stop command, go handle the various special
1113 * conditions (read: bugs) that have to be dealt with following a stop.
1115 if (cmd->opcode == MMC_STOP_TRANSMISSION) {
1116 at91_mci_stop_done(sc, sr);
1121 * If this command can continue to assert BUSY beyond the response then
1122 * we need to wait for NOTBUSY before the command is really done.
1124 * Note that this may not work properly on the at91rm9200. It certainly
1125 * doesn't work for the STOP command that follows a multi-block write,
1126 * so post-stop CMDRDY is handled separately; see the special handling
1127 * in at91_mci_stop_done().
1129 * Beside STOP, there are other R1B-type commands that use the busy
1130 * signal after CMDRDY: CMD7 (card select), CMD28-29 (write protect),
1131 * CMD38 (erase). I haven't tested any of them, but I rather expect
1132 * them all to have the same sort of problem with MCI_SR not actually
1133 * reflecting the state of the DAT0-line busy indicator. So this code
1134 * may need to grow some sort of special handling for them too. (This
1135 * just in: CMD7 isn't a problem right now because dev/mmc.c incorrectly
1136 * sets the response flags to R1 rather than R1B.) XXX
1138 if ((cmd->flags & MMC_RSP_BUSY)) {
1139 WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_NOTBUSY);
1144 * If there is a data transfer with this command, then...
1145 * - If it's a read, we need to wait for ENDRX.
1146 * - If it's a write, now is the time to enable the PDC, and we need
1147 * to wait for a BLKE that follows a TXBUFE, because if we're doing
1148 * a split transfer we get a BLKE after the first half (when TPR/TCR
1149 * get loaded from TNPR/TNCR). So first we wait for the TXBUFE, and
1150 * the handling for that interrupt will then invoke the wait for the
1151 * subsequent BLKE which indicates actual completion.
1155 if (cmd->data->flags & MMC_DATA_READ) {
1158 ier = MCI_SR_TXBUFE;
1159 WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN);
1161 WR4(sc, MCI_IER, MCI_SR_ERROR | ier);
1166 * If we made it to here, we don't need to wait for anything more for
1167 * the current command, move on to the next command (will complete the
1168 * request if there is no next command).
1170 cmd->error = MMC_ERR_NONE;
1171 at91_mci_next_operation(sc);
1175 at91_mci_intr(void *arg)
1177 struct at91_mci_softc *sc = (struct at91_mci_softc*)arg;
1178 struct mmc_command *cmd = sc->curcmd;
1183 sr = RD4(sc, MCI_SR);
1184 isr = sr & RD4(sc, MCI_IMR);
1187 printf("i 0x%x sr 0x%x\n", isr, sr);
1190 * All interrupts are one-shot; disable it now.
1191 * The next operation will re-enable whatever interrupts it wants.
1193 WR4(sc, MCI_IDR, isr);
1194 if (isr & MCI_SR_ERROR) {
1195 if (isr & (MCI_SR_RTOE | MCI_SR_DTOE))
1196 cmd->error = MMC_ERR_TIMEOUT;
1197 else if (isr & (MCI_SR_RCRCE | MCI_SR_DCRCE))
1198 cmd->error = MMC_ERR_BADCRC;
1199 else if (isr & (MCI_SR_OVRE | MCI_SR_UNRE))
1200 cmd->error = MMC_ERR_FIFO;
1202 cmd->error = MMC_ERR_FAILED;
1204 * CMD8 is used to probe for SDHC cards, a standard SD card
1205 * will get a response timeout; don't report it because it's a
1206 * normal and expected condition. One might argue that all
1207 * error reporting should be left to higher levels, but when
1208 * they report at all it's always EIO, which isn't very
1209 * helpful. XXX bootverbose?
1211 if (cmd->opcode != 8) {
1212 device_printf(sc->dev,
1213 "IO error; status MCI_SR = 0x%x cmd opcode = %d%s\n",
1215 (cmd->opcode != 12) ? "" :
1216 (sc->flags & CMD_MULTIREAD) ? " after read" : " after write");
1219 at91_mci_next_operation(sc);
1221 if (isr & MCI_SR_TXBUFE) {
1222 // printf("TXBUFE\n");
1224 * We need to wait for a BLKE that follows TXBUFE
1225 * (intermediate BLKEs might happen after ENDTXes if
1226 * we're chaining multiple buffers). If BLKE is also
1227 * asserted at the time we get TXBUFE, we can avoid
1228 * another interrupt and process it right away, below.
1230 if (sr & MCI_SR_BLKE)
1233 WR4(sc, MCI_IER, MCI_SR_BLKE);
1235 if (isr & MCI_SR_RXBUFF) {
1236 // printf("RXBUFF\n");
1238 if (isr & MCI_SR_ENDTX) {
1239 // printf("ENDTX\n");
1241 if (isr & MCI_SR_ENDRX) {
1242 // printf("ENDRX\n");
1243 at91_mci_read_done(sc, sr);
1245 if (isr & MCI_SR_NOTBUSY) {
1246 // printf("NOTBUSY\n");
1247 at91_mci_notbusy(sc);
1249 if (isr & MCI_SR_DTIP) {
1250 // printf("Data transfer in progress\n");
1252 if (isr & MCI_SR_BLKE) {
1253 // printf("Block transfer end\n");
1254 at91_mci_write_done(sc, sr);
1256 if (isr & MCI_SR_TXRDY) {
1257 // printf("Ready to transmit\n");
1259 if (isr & MCI_SR_RXRDY) {
1260 // printf("Ready to receive\n");
1262 if (isr & MCI_SR_CMDRDY) {
1263 // printf("Command ready\n");
1264 at91_mci_cmdrdy(sc, sr);
1267 AT91_MCI_UNLOCK(sc);
1271 at91_mci_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
1273 struct at91_mci_softc *sc = device_get_softc(bus);
1278 case MMCBR_IVAR_BUS_MODE:
1279 *(int *)result = sc->host.ios.bus_mode;
1281 case MMCBR_IVAR_BUS_WIDTH:
1282 *(int *)result = sc->host.ios.bus_width;
1284 case MMCBR_IVAR_CHIP_SELECT:
1285 *(int *)result = sc->host.ios.chip_select;
1287 case MMCBR_IVAR_CLOCK:
1288 *(int *)result = sc->host.ios.clock;
1290 case MMCBR_IVAR_F_MIN:
1291 *(int *)result = sc->host.f_min;
1293 case MMCBR_IVAR_F_MAX:
1294 *(int *)result = sc->host.f_max;
1296 case MMCBR_IVAR_HOST_OCR:
1297 *(int *)result = sc->host.host_ocr;
1299 case MMCBR_IVAR_MODE:
1300 *(int *)result = sc->host.mode;
1302 case MMCBR_IVAR_OCR:
1303 *(int *)result = sc->host.ocr;
1305 case MMCBR_IVAR_POWER_MODE:
1306 *(int *)result = sc->host.ios.power_mode;
1308 case MMCBR_IVAR_VDD:
1309 *(int *)result = sc->host.ios.vdd;
1311 case MMCBR_IVAR_CAPS:
1312 if (sc->has_4wire) {
1313 sc->sc_cap |= CAP_HAS_4WIRE;
1314 sc->host.caps |= MMC_CAP_4_BIT_DATA;
1316 sc->sc_cap &= ~CAP_HAS_4WIRE;
1317 sc->host.caps &= ~MMC_CAP_4_BIT_DATA;
1319 *(int *)result = sc->host.caps;
1321 case MMCBR_IVAR_MAX_DATA:
1323 * Something is wrong with the 2x parts and multiblock, so
1324 * just do 1 block at a time for now, which really kills
1327 if (sc->sc_cap & CAP_MCI1_REV2XX)
1330 *(int *)result = MAX_BLOCKS;
1337 at91_mci_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
1339 struct at91_mci_softc *sc = device_get_softc(bus);
1344 case MMCBR_IVAR_BUS_MODE:
1345 sc->host.ios.bus_mode = value;
1347 case MMCBR_IVAR_BUS_WIDTH:
1348 sc->host.ios.bus_width = value;
1350 case MMCBR_IVAR_CHIP_SELECT:
1351 sc->host.ios.chip_select = value;
1353 case MMCBR_IVAR_CLOCK:
1354 sc->host.ios.clock = value;
1356 case MMCBR_IVAR_MODE:
1357 sc->host.mode = value;
1359 case MMCBR_IVAR_OCR:
1360 sc->host.ocr = value;
1362 case MMCBR_IVAR_POWER_MODE:
1363 sc->host.ios.power_mode = value;
1365 case MMCBR_IVAR_VDD:
1366 sc->host.ios.vdd = value;
1368 /* These are read-only */
1369 case MMCBR_IVAR_CAPS:
1370 case MMCBR_IVAR_HOST_OCR:
1371 case MMCBR_IVAR_F_MIN:
1372 case MMCBR_IVAR_F_MAX:
1373 case MMCBR_IVAR_MAX_DATA:
1379 static device_method_t at91_mci_methods[] = {
1381 DEVMETHOD(device_probe, at91_mci_probe),
1382 DEVMETHOD(device_attach, at91_mci_attach),
1383 DEVMETHOD(device_detach, at91_mci_detach),
1386 DEVMETHOD(bus_read_ivar, at91_mci_read_ivar),
1387 DEVMETHOD(bus_write_ivar, at91_mci_write_ivar),
1390 DEVMETHOD(mmcbr_update_ios, at91_mci_update_ios),
1391 DEVMETHOD(mmcbr_request, at91_mci_request),
1392 DEVMETHOD(mmcbr_get_ro, at91_mci_get_ro),
1393 DEVMETHOD(mmcbr_acquire_host, at91_mci_acquire_host),
1394 DEVMETHOD(mmcbr_release_host, at91_mci_release_host),
1399 static driver_t at91_mci_driver = {
1402 sizeof(struct at91_mci_softc),
1405 static devclass_t at91_mci_devclass;
1408 DRIVER_MODULE(at91_mci, simplebus, at91_mci_driver, at91_mci_devclass, NULL,
1411 DRIVER_MODULE(at91_mci, atmelarm, at91_mci_driver, at91_mci_devclass, NULL,