2 * Copyright (c) 2006 Bernd Walter. All rights reserved.
3 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
4 * Copyright (c) 2010 Greg Ansley. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include "opt_platform.h"
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/endian.h>
37 #include <sys/kernel.h>
39 #include <sys/malloc.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
42 #include <sys/resource.h>
44 #include <sys/sysctl.h>
46 #include <machine/bus.h>
47 #include <machine/resource.h>
48 #include <machine/intr.h>
50 #include <arm/at91/at91var.h>
51 #include <arm/at91/at91_mcireg.h>
52 #include <arm/at91/at91_pdcreg.h>
54 #include <dev/mmc/bridge.h>
55 #include <dev/mmc/mmcbrvar.h>
58 #include <dev/ofw/ofw_bus.h>
59 #include <dev/ofw/ofw_bus_subr.h>
67 * About running the MCI bus above 25MHz
69 * Historically, the MCI bus has been run at 30MHz on systems with a 60MHz
70 * master clock, in part due to a bug in dev/mmc.c making always request
71 * 30MHz, and in part over clocking the bus because 15MHz was too slow.
72 * Fixing that bug causes the mmc driver to request a 25MHz clock (as it
73 * should) and the logic in at91_mci_update_ios() picks the highest speed that
74 * doesn't exceed that limit. With a 60MHz MCK that would be 15MHz, and
75 * that's a real performance buzzkill when you've been getting away with 30MHz
78 * By defining AT91_MCI_ALLOW_OVERCLOCK (or setting the allow_overclock=1
79 * device hint or sysctl) you can enable logic in at91_mci_update_ios() to
80 * overlcock the SD bus a little by running it at MCK / 2 when the requested
81 * speed is 25MHz and the next highest speed is 15MHz or less. This appears
82 * to work on virtually all SD cards, since it is what this driver has been
83 * doing prior to the introduction of this option, where the overclocking vs
84 * underclocking decision was automatically "overclock". Modern SD cards can
85 * run at 45mhz/1-bit in standard mode (high speed mode enable commands not
86 * sent) without problems.
88 * Speaking of high-speed mode, the rm9200 manual says the MCI device supports
89 * the SD v1.0 specification and can run up to 50MHz. This is interesting in
90 * that the SD v1.0 spec caps the speed at 25MHz; high speed mode was added in
91 * the v1.10 spec. Furthermore, high speed mode doesn't just crank up the
92 * clock, it alters the signal timing. The rm9200 MCI device doesn't support
93 * these altered timings. So while speeds over 25MHz may work, they only work
94 * in what the SD spec calls "default" speed mode, and it amounts to violating
95 * the spec by overclocking the bus.
97 * If you also enable 4-wire mode it's possible transfers faster than 25MHz
98 * will fail. On the AT91RM9200, due to bugs in the bus contention logic, if
99 * you have the USB host device and OHCI driver enabled will fail. Even
100 * underclocking to 15MHz, intermittant overrun and underrun errors occur.
101 * Note that you don't even need to have usb devices attached to the system,
102 * the errors begin to occur as soon as the OHCI driver sets the register bit
103 * to enable periodic transfers. It appears (based on brief investigation)
104 * that the usb host controller uses so much ASB bandwidth that sometimes the
105 * DMA for MCI transfers doesn't get a bus grant in time and data gets
106 * dropped. Adding even a modicum of network activity changes the symptom
107 * from intermittant to very frequent. Members of the AT91SAM9 family have
108 * corrected this problem, or are at least better about their use of the bus.
110 #ifndef AT91_MCI_ALLOW_OVERCLOCK
111 #define AT91_MCI_ALLOW_OVERCLOCK 1
115 * Allocate 2 bounce buffers we'll use to endian-swap the data due to the rm9200
116 * erratum. We use a pair of buffers because when reading that lets us begin
117 * endian-swapping the data in the first buffer while the DMA is reading into
118 * the second buffer. (We can't use the same trick for writing because we might
119 * not get all the data in the 2nd buffer swapped before the hardware needs it;
120 * dealing with that would add complexity to the driver.)
122 * The buffers are sized at 16K each due to the way the busdma cache sync
123 * operations work on arm. A dcache_inv_range() operation on a range larger
124 * than 16K gets turned into a dcache_wbinv_all(). That needlessly flushes the
125 * entire data cache, impacting overall system performance.
128 #define BBSIZE (16*1024)
129 #define MAX_BLOCKS ((BBSIZE*BBCOUNT)/512)
131 static int mci_debug;
133 struct at91_mci_softc {
134 void *intrhand; /* Interrupt handle */
137 #define CAP_HAS_4WIRE 1 /* Has 4 wire bus */
138 #define CAP_NEEDS_BYTESWAP 2 /* broken hardware needing bounce */
139 #define CAP_MCI1_REV2XX 4 /* MCI 1 rev 2.x */
141 #define PENDING_CMD 0x01
142 #define PENDING_STOP 0x02
143 #define CMD_MULTIREAD 0x10
144 #define CMD_MULTIWRITE 0x20
147 struct resource *irq_res; /* IRQ resource */
148 struct resource *mem_res; /* Memory resource */
150 bus_dma_tag_t dmatag;
151 struct mmc_host host;
153 struct mmc_request *req;
154 struct mmc_command *curcmd;
155 bus_dmamap_t bbuf_map[BBCOUNT];
156 char * bbuf_vaddr[BBCOUNT]; /* bounce bufs in KVA space */
157 uint32_t bbuf_len[BBCOUNT]; /* len currently queued for bounce buf */
158 uint32_t bbuf_curidx; /* which bbuf is the active DMA buffer */
159 uint32_t xfer_offset; /* offset so far into caller's buf */
162 /* bus entry points */
163 static int at91_mci_probe(device_t dev);
164 static int at91_mci_attach(device_t dev);
165 static int at91_mci_detach(device_t dev);
166 static void at91_mci_intr(void *);
168 /* helper routines */
169 static int at91_mci_activate(device_t dev);
170 static void at91_mci_deactivate(device_t dev);
171 static int at91_mci_is_mci1rev2xx(void);
173 #define AT91_MCI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
174 #define AT91_MCI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
175 #define AT91_MCI_LOCK_INIT(_sc) \
176 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
178 #define AT91_MCI_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
179 #define AT91_MCI_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
180 #define AT91_MCI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
182 static inline uint32_t
183 RD4(struct at91_mci_softc *sc, bus_size_t off)
185 return (bus_read_4(sc->mem_res, off));
189 WR4(struct at91_mci_softc *sc, bus_size_t off, uint32_t val)
191 bus_write_4(sc->mem_res, off, val);
195 at91_bswap_buf(struct at91_mci_softc *sc, void * dptr, void * sptr, uint32_t memsize)
197 uint32_t * dst = (uint32_t *)dptr;
198 uint32_t * src = (uint32_t *)sptr;
202 * If the hardware doesn't need byte-swapping, let bcopy() do the
203 * work. Use bounce buffer even if we don't need byteswap, since
204 * buffer may straddle a page boundary, and we don't handle
205 * multi-segment transfers in hardware. Seen from 'bsdlabel -w' which
206 * uses raw geom access to the volume. Greg Ansley (gja (at)
209 if (!(sc->sc_cap & CAP_NEEDS_BYTESWAP)) {
210 memcpy(dptr, sptr, memsize);
215 * Nice performance boost for slightly unrolling this loop.
216 * (But very little extra boost for further unrolling it.)
218 for (i = 0; i < memsize; i += 16) {
219 *dst++ = bswap32(*src++);
220 *dst++ = bswap32(*src++);
221 *dst++ = bswap32(*src++);
222 *dst++ = bswap32(*src++);
225 /* Mop up the last 1-3 words, if any. */
226 for (i = 0; i < (memsize & 0x0F); i += 4) {
227 *dst++ = bswap32(*src++);
232 at91_mci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
236 *(bus_addr_t *)arg = segs[0].ds_addr;
240 at91_mci_pdc_disable(struct at91_mci_softc *sc)
242 WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS);
245 WR4(sc, PDC_RNPR, 0);
246 WR4(sc, PDC_RNCR, 0);
249 WR4(sc, PDC_TNPR, 0);
250 WR4(sc, PDC_TNCR, 0);
254 * Reset the controller, then restore most of the current state.
256 * This is called after detecting an error. It's also called after stopping a
257 * multi-block write, to un-wedge the device so that it will handle the NOTBUSY
258 * signal correctly. See comments in at91_mci_stop_done() for more details.
260 static void at91_mci_reset(struct at91_mci_softc *sc)
267 at91_mci_pdc_disable(sc);
269 /* save current state */
271 imr = RD4(sc, MCI_IMR);
272 mr = RD4(sc, MCI_MR) & 0x7fff;
273 sdcr = RD4(sc, MCI_SDCR);
274 dtor = RD4(sc, MCI_DTOR);
276 /* reset the controller */
278 WR4(sc, MCI_IDR, 0xffffffff);
279 WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST);
283 WR4(sc, MCI_CR, MCI_CR_MCIEN|MCI_CR_PWSEN);
285 WR4(sc, MCI_SDCR, sdcr);
286 WR4(sc, MCI_DTOR, dtor);
287 WR4(sc, MCI_IER, imr);
290 * Make sure sdio interrupts will fire. Not sure why reading
291 * SR ensures that, but this is in the linux driver.
298 at91_mci_init(device_t dev)
300 struct at91_mci_softc *sc = device_get_softc(dev);
303 WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST); /* device into reset */
304 WR4(sc, MCI_IDR, 0xffffffff); /* Turn off interrupts */
305 WR4(sc, MCI_DTOR, MCI_DTOR_DTOMUL_1M | 1);
306 val = MCI_MR_PDCMODE;
307 val |= 0x34a; /* PWSDIV = 3; CLKDIV = 74 */
308 // if (sc->sc_cap & CAP_MCI1_REV2XX)
309 // val |= MCI_MR_RDPROOF | MCI_MR_WRPROOF;
310 WR4(sc, MCI_MR, val);
311 #ifndef AT91_MCI_SLOT_B
312 WR4(sc, MCI_SDCR, 0); /* SLOT A, 1 bit bus */
315 * XXX Really should add second "unit" but nobody using using
316 * a two slot card that we know of. XXX
318 WR4(sc, MCI_SDCR, 1); /* SLOT B, 1 bit bus */
321 * Enable controller, including power-save. The slower clock
322 * of the power-save mode is only in effect when there is no
323 * transfer in progress, so it can be left in this mode all
326 WR4(sc, MCI_CR, MCI_CR_MCIEN|MCI_CR_PWSEN);
330 at91_mci_fini(device_t dev)
332 struct at91_mci_softc *sc = device_get_softc(dev);
334 WR4(sc, MCI_IDR, 0xffffffff); /* Turn off interrupts */
335 at91_mci_pdc_disable(sc);
336 WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST); /* device into reset */
340 at91_mci_probe(device_t dev)
343 if (!ofw_bus_is_compatible(dev, "atmel,hsmci"))
346 device_set_desc(dev, "MCI mmc/sd host bridge");
351 at91_mci_attach(device_t dev)
353 struct at91_mci_softc *sc = device_get_softc(dev);
354 struct sysctl_ctx_list *sctx;
355 struct sysctl_oid *soid;
359 sctx = device_get_sysctl_ctx(dev);
360 soid = device_get_sysctl_tree(dev);
365 sc->sc_cap |= CAP_NEEDS_BYTESWAP;
367 * MCI1 Rev 2 controllers need some workarounds, flag if so.
369 if (at91_mci_is_mci1rev2xx())
370 sc->sc_cap |= CAP_MCI1_REV2XX;
372 err = at91_mci_activate(dev);
376 AT91_MCI_LOCK_INIT(sc);
382 * Allocate DMA tags and maps and bounce buffers.
384 * The parms in the tag_create call cause the dmamem_alloc call to
385 * create each bounce buffer as a single contiguous buffer of BBSIZE
386 * bytes aligned to a 4096 byte boundary.
388 * Do not use DMA_COHERENT for these buffers because that maps the
389 * memory as non-cachable, which prevents cache line burst fills/writes,
390 * which is something we need since we're trying to overlap the
391 * byte-swapping with the DMA operations.
393 err = bus_dma_tag_create(bus_get_dma_tag(dev), 4096, 0,
394 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
395 BBSIZE, 1, BBSIZE, 0, NULL, NULL, &sc->dmatag);
399 for (i = 0; i < BBCOUNT; ++i) {
400 err = bus_dmamem_alloc(sc->dmatag, (void **)&sc->bbuf_vaddr[i],
401 BUS_DMA_NOWAIT, &sc->bbuf_map[i]);
407 * Activate the interrupt
409 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
410 NULL, at91_mci_intr, sc, &sc->intrhand);
412 AT91_MCI_LOCK_DESTROY(sc);
417 * Allow 4-wire to be initially set via #define.
418 * Allow a device hint to override that.
419 * Allow a sysctl to override that.
421 #if defined(AT91_MCI_HAS_4WIRE) && AT91_MCI_HAS_4WIRE != 0
424 resource_int_value(device_get_name(dev), device_get_unit(dev),
425 "4wire", &sc->has_4wire);
426 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "4wire",
427 CTLFLAG_RW, &sc->has_4wire, 0, "has 4 wire SD Card bus");
429 sc->sc_cap |= CAP_HAS_4WIRE;
431 sc->allow_overclock = AT91_MCI_ALLOW_OVERCLOCK;
432 resource_int_value(device_get_name(dev), device_get_unit(dev),
433 "allow_overclock", &sc->allow_overclock);
434 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "allow_overclock",
435 CTLFLAG_RW, &sc->allow_overclock, 0,
436 "Allow up to 30MHz clock for 25MHz request when next highest speed 15MHz or less.");
438 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "debug",
439 CTLFLAG_RWTUN, &mci_debug, 0, "enable debug output");
442 * Our real min freq is master_clock/512, but upper driver layers are
443 * going to set the min speed during card discovery, and the right speed
444 * for that is 400kHz, so advertise a safe value just under that.
446 * For max speed, while the rm9200 manual says the max is 50mhz, it also
447 * says it supports only the SD v1.0 spec, which means the real limit is
448 * 25mhz. On the other hand, historical use has been to slightly violate
449 * the standard by running the bus at 30MHz. For more information on
450 * that, see the comments at the top of this file.
452 sc->host.f_min = 375000;
453 sc->host.f_max = at91_master_clock / 2;
454 if (sc->host.f_max > 25000000)
455 sc->host.f_max = 25000000;
456 sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
458 if (sc->sc_cap & CAP_HAS_4WIRE)
459 sc->host.caps |= MMC_CAP_4_BIT_DATA;
461 child = device_add_child(dev, "mmc", 0);
462 device_set_ivars(dev, &sc->host);
463 err = bus_generic_attach(dev);
466 at91_mci_deactivate(dev);
471 at91_mci_detach(device_t dev)
473 struct at91_mci_softc *sc = device_get_softc(dev);
476 at91_mci_deactivate(dev);
478 bus_dmamem_free(sc->dmatag, sc->bbuf_vaddr[0], sc->bbuf_map[0]);
479 bus_dmamem_free(sc->dmatag, sc->bbuf_vaddr[1], sc->bbuf_map[1]);
480 bus_dma_tag_destroy(sc->dmatag);
482 return (EBUSY); /* XXX */
486 at91_mci_activate(device_t dev)
488 struct at91_mci_softc *sc;
491 sc = device_get_softc(dev);
493 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
495 if (sc->mem_res == NULL)
499 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
501 if (sc->irq_res == NULL)
506 at91_mci_deactivate(dev);
511 at91_mci_deactivate(device_t dev)
513 struct at91_mci_softc *sc;
515 sc = device_get_softc(dev);
517 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
519 bus_generic_detach(sc->dev);
521 bus_release_resource(dev, SYS_RES_MEMORY,
522 rman_get_rid(sc->mem_res), sc->mem_res);
525 bus_release_resource(dev, SYS_RES_IRQ,
526 rman_get_rid(sc->irq_res), sc->irq_res);
532 at91_mci_is_mci1rev2xx(void)
535 switch (soc_info.type) {
549 at91_mci_update_ios(device_t brdev, device_t reqdev)
551 struct at91_mci_softc *sc;
556 sc = device_get_softc(brdev);
560 * Calculate our closest available clock speed that doesn't exceed the
563 * When overclocking is allowed, the requested clock is 25MHz, the
564 * computed frequency is 15MHz or smaller and clockdiv is 1, use
565 * clockdiv of 0 to double that. If less than 12.5MHz, double
566 * regardless of the overclocking setting.
568 * Whatever we come up with, store it back into ios->clock so that the
569 * upper layer drivers can report the actual speed of the bus.
571 if (ios->clock == 0) {
572 WR4(sc, MCI_CR, MCI_CR_MCIDIS);
575 WR4(sc, MCI_CR, MCI_CR_MCIEN|MCI_CR_PWSEN);
576 if ((at91_master_clock % (ios->clock * 2)) == 0)
577 clkdiv = ((at91_master_clock / ios->clock) / 2) - 1;
579 clkdiv = (at91_master_clock / ios->clock) / 2;
580 freq = at91_master_clock / ((clkdiv+1) * 2);
581 if (clkdiv == 1 && ios->clock == 25000000 && freq <= 15000000) {
582 if (sc->allow_overclock || freq <= 12500000) {
584 freq = at91_master_clock / ((clkdiv+1) * 2);
589 if (ios->bus_width == bus_width_4)
590 WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) | MCI_SDCR_SDCBUS);
592 WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) & ~MCI_SDCR_SDCBUS);
593 WR4(sc, MCI_MR, (RD4(sc, MCI_MR) & ~MCI_MR_CLKDIV) | clkdiv);
594 /* Do we need a settle time here? */
595 /* XXX We need to turn the device on/off here with a GPIO pin */
600 at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd)
603 struct mmc_data *data;
608 /* XXX Upper layers don't always set this */
611 /* Begin setting up command register. */
615 if (sc->host.ios.bus_mode == opendrain)
616 cmdr |= MCI_CMDR_OPDCMD;
618 /* Set up response handling. Allow max timeout for responses. */
620 if (MMC_RSP(cmd->flags) == MMC_RSP_NONE)
621 cmdr |= MCI_CMDR_RSPTYP_NO;
623 cmdr |= MCI_CMDR_MAXLAT;
624 if (cmd->flags & MMC_RSP_136)
625 cmdr |= MCI_CMDR_RSPTYP_136;
627 cmdr |= MCI_CMDR_RSPTYP_48;
631 * If there is no data transfer, just set up the right interrupt mask
632 * and start the command.
634 * The interrupt mask needs to be CMDRDY plus all non-data-transfer
635 * errors. It's important to leave the transfer-related errors out, to
636 * avoid spurious timeout or crc errors on a STOP command following a
637 * multiblock read. When a multiblock read is in progress, sending a
638 * STOP in the middle of a block occasionally triggers such errors, but
639 * we're totally disinterested in them because we've already gotten all
640 * the data we wanted without error before sending the STOP command.
644 uint32_t ier = MCI_SR_CMDRDY |
645 MCI_SR_RTOE | MCI_SR_RENDE |
646 MCI_SR_RCRCE | MCI_SR_RDIRE | MCI_SR_RINDE;
648 at91_mci_pdc_disable(sc);
650 if (cmd->opcode == MMC_STOP_TRANSMISSION)
651 cmdr |= MCI_CMDR_TRCMD_STOP;
653 /* Ignore response CRC on CMD2 and ACMD41, per standard. */
655 if (cmd->opcode == MMC_SEND_OP_COND ||
656 cmd->opcode == ACMD_SD_SEND_OP_COND)
657 ier &= ~MCI_SR_RCRCE;
660 printf("CMDR %x (opcode %d) ARGR %x no data\n",
661 cmdr, cmd->opcode, cmd->arg);
663 WR4(sc, MCI_ARGR, cmd->arg);
664 WR4(sc, MCI_CMDR, cmdr);
665 WR4(sc, MCI_IDR, 0xffffffff);
666 WR4(sc, MCI_IER, ier);
670 /* There is data, set up the transfer-related parts of the command. */
672 if (data->flags & MMC_DATA_READ)
673 cmdr |= MCI_CMDR_TRDIR;
675 if (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE))
676 cmdr |= MCI_CMDR_TRCMD_START;
678 if (data->flags & MMC_DATA_STREAM)
679 cmdr |= MCI_CMDR_TRTYP_STREAM;
680 else if (data->flags & MMC_DATA_MULTI) {
681 cmdr |= MCI_CMDR_TRTYP_MULTIPLE;
682 sc->flags |= (data->flags & MMC_DATA_READ) ?
683 CMD_MULTIREAD : CMD_MULTIWRITE;
687 * Disable PDC until we're ready.
689 * Set block size and turn on PDC mode for dma xfer.
690 * Note that the block size is the smaller of the amount of data to be
691 * transferred, or 512 bytes. The 512 size is fixed by the standard;
692 * smaller blocks are possible, but never larger.
695 WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
697 mr = RD4(sc,MCI_MR) & ~MCI_MR_BLKLEN;
698 mr |= min(data->len, 512) << 16;
699 WR4(sc, MCI_MR, mr | MCI_MR_PDCMODE|MCI_MR_PDCPADV);
704 * Use bounce buffers even if we don't need to byteswap, because doing
705 * multi-block IO with large DMA buffers is way fast (compared to
706 * single-block IO), even after incurring the overhead of also copying
707 * from/to the caller's buffers (which may be in non-contiguous physical
710 * In an ideal non-byteswap world we could create a dma tag that allows
711 * for discontiguous segments and do the IO directly from/to the
712 * caller's buffer(s), using ENDRX/ENDTX interrupts to chain the
713 * discontiguous buffers through the PDC. Someday.
715 * If a read is bigger than 2k, split it in half so that we can start
716 * byte-swapping the first half while the second half is on the wire.
717 * It would be best if we could split it into 8k chunks, but we can't
718 * always keep up with the byte-swapping due to other system activity,
719 * and if an RXBUFF interrupt happens while we're still handling the
720 * byte-swap from the prior buffer (IE, we haven't returned from
721 * handling the prior interrupt yet), then data will get dropped on the
722 * floor and we can't easily recover from that. The right fix for that
723 * would be to have the interrupt handling only keep the DMA flowing and
724 * enqueue filled buffers to be byte-swapped in a non-interrupt context.
725 * Even that won't work on the write side of things though; in that
726 * context we have to have all the data ready to go before starting the
729 * XXX what about stream transfers?
734 if (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) {
736 uint32_t remaining = data->len;
740 if (remaining > (BBCOUNT*BBSIZE))
741 panic("IO read size exceeds MAXDATA\n");
743 if (data->flags & MMC_DATA_READ) {
744 if (remaining > 2048) // XXX
748 err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[0],
749 sc->bbuf_vaddr[0], len, at91_mci_getaddr,
750 &paddr, BUS_DMA_NOWAIT);
752 panic("IO read dmamap_load failed\n");
753 bus_dmamap_sync(sc->dmatag, sc->bbuf_map[0],
754 BUS_DMASYNC_PREREAD);
755 WR4(sc, PDC_RPR, paddr);
756 WR4(sc, PDC_RCR, len / 4);
757 sc->bbuf_len[0] = len;
759 if (remaining == 0) {
763 err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[1],
764 sc->bbuf_vaddr[1], len, at91_mci_getaddr,
765 &paddr, BUS_DMA_NOWAIT);
767 panic("IO read dmamap_load failed\n");
768 bus_dmamap_sync(sc->dmatag, sc->bbuf_map[1],
769 BUS_DMASYNC_PREREAD);
770 WR4(sc, PDC_RNPR, paddr);
771 WR4(sc, PDC_RNCR, len / 4);
772 sc->bbuf_len[1] = len;
775 WR4(sc, PDC_PTCR, PDC_PTCR_RXTEN);
777 len = min(BBSIZE, remaining);
778 at91_bswap_buf(sc, sc->bbuf_vaddr[0], data->data, len);
779 err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[0],
780 sc->bbuf_vaddr[0], len, at91_mci_getaddr,
781 &paddr, BUS_DMA_NOWAIT);
783 panic("IO write dmamap_load failed\n");
784 bus_dmamap_sync(sc->dmatag, sc->bbuf_map[0],
785 BUS_DMASYNC_PREWRITE);
787 * Erratum workaround: PDC transfer length on a write
788 * must not be smaller than 12 bytes (3 words); only
789 * blklen bytes (set above) are actually transferred.
791 WR4(sc, PDC_TPR,paddr);
792 WR4(sc, PDC_TCR, (len < 12) ? 3 : len / 4);
793 sc->bbuf_len[0] = len;
795 if (remaining == 0) {
799 at91_bswap_buf(sc, sc->bbuf_vaddr[1],
800 ((char *)data->data)+BBSIZE, len);
801 err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[1],
802 sc->bbuf_vaddr[1], len, at91_mci_getaddr,
803 &paddr, BUS_DMA_NOWAIT);
805 panic("IO write dmamap_load failed\n");
806 bus_dmamap_sync(sc->dmatag, sc->bbuf_map[1],
807 BUS_DMASYNC_PREWRITE);
808 WR4(sc, PDC_TNPR, paddr);
809 WR4(sc, PDC_TNCR, (len < 12) ? 3 : len / 4);
810 sc->bbuf_len[1] = len;
813 /* do not enable PDC xfer until CMDRDY asserted */
815 data->xfer_len = 0; /* XXX what's this? appears to be unused. */
819 printf("CMDR %x (opcode %d) ARGR %x with data len %d\n",
820 cmdr, cmd->opcode, cmd->arg, cmd->data->len);
822 WR4(sc, MCI_ARGR, cmd->arg);
823 WR4(sc, MCI_CMDR, cmdr);
824 WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_CMDRDY);
828 at91_mci_next_operation(struct at91_mci_softc *sc)
830 struct mmc_request *req;
836 if (sc->flags & PENDING_CMD) {
837 sc->flags &= ~PENDING_CMD;
838 at91_mci_start_cmd(sc, req->cmd);
840 } else if (sc->flags & PENDING_STOP) {
841 sc->flags &= ~PENDING_STOP;
842 at91_mci_start_cmd(sc, req->stop);
846 WR4(sc, MCI_IDR, 0xffffffff);
849 //printf("req done\n");
854 at91_mci_request(device_t brdev, device_t reqdev, struct mmc_request *req)
856 struct at91_mci_softc *sc = device_get_softc(brdev);
859 if (sc->req != NULL) {
863 //printf("new req\n");
865 sc->flags = PENDING_CMD;
867 sc->flags |= PENDING_STOP;
868 at91_mci_next_operation(sc);
874 at91_mci_get_ro(device_t brdev, device_t reqdev)
880 at91_mci_acquire_host(device_t brdev, device_t reqdev)
882 struct at91_mci_softc *sc = device_get_softc(brdev);
887 msleep(sc, &sc->sc_mtx, PZERO, "mciah", hz / 5);
894 at91_mci_release_host(device_t brdev, device_t reqdev)
896 struct at91_mci_softc *sc = device_get_softc(brdev);
906 at91_mci_read_done(struct at91_mci_softc *sc, uint32_t sr)
908 struct mmc_command *cmd = sc->curcmd;
909 char * dataptr = (char *)cmd->data->data;
910 uint32_t curidx = sc->bbuf_curidx;
911 uint32_t len = sc->bbuf_len[curidx];
914 * We arrive here when a DMA transfer for a read is done, whether it's
915 * a single or multi-block read.
917 * We byte-swap the buffer that just completed, and if that is the
918 * last buffer that's part of this read then we move on to the next
919 * operation, otherwise we wait for another ENDRX for the next bufer.
922 bus_dmamap_sync(sc->dmatag, sc->bbuf_map[curidx], BUS_DMASYNC_POSTREAD);
923 bus_dmamap_unload(sc->dmatag, sc->bbuf_map[curidx]);
925 at91_bswap_buf(sc, dataptr + sc->xfer_offset, sc->bbuf_vaddr[curidx], len);
928 printf("read done sr %x curidx %d len %d xfer_offset %d\n",
929 sr, curidx, len, sc->xfer_offset);
932 sc->xfer_offset += len;
933 sc->bbuf_curidx = !curidx; /* swap buffers */
936 * If we've transferred all the data, move on to the next operation.
938 * If we're still transferring the last buffer, RNCR is already zero but
939 * we have to write a zero anyway to clear the ENDRX status so we don't
940 * re-interrupt until the last buffer is done.
942 if (sc->xfer_offset == cmd->data->len) {
943 WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
944 cmd->error = MMC_ERR_NONE;
945 at91_mci_next_operation(sc);
947 WR4(sc, PDC_RNCR, 0);
948 WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_ENDRX);
953 at91_mci_write_done(struct at91_mci_softc *sc, uint32_t sr)
955 struct mmc_command *cmd = sc->curcmd;
958 * We arrive here when the entire DMA transfer for a write is done,
959 * whether it's a single or multi-block write. If it's multi-block we
960 * have to immediately move on to the next operation which is to send
961 * the stop command. If it's a single-block transfer we need to wait
962 * for NOTBUSY, but if that's already asserted we can avoid another
963 * interrupt and just move on to completing the request right away.
966 WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
968 bus_dmamap_sync(sc->dmatag, sc->bbuf_map[sc->bbuf_curidx],
969 BUS_DMASYNC_POSTWRITE);
970 bus_dmamap_unload(sc->dmatag, sc->bbuf_map[sc->bbuf_curidx]);
972 if ((cmd->data->flags & MMC_DATA_MULTI) || (sr & MCI_SR_NOTBUSY)) {
973 cmd->error = MMC_ERR_NONE;
974 at91_mci_next_operation(sc);
976 WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_NOTBUSY);
981 at91_mci_notbusy(struct at91_mci_softc *sc)
983 struct mmc_command *cmd = sc->curcmd;
986 * We arrive here by either completion of a single-block write, or
987 * completion of the stop command that ended a multi-block write (and,
988 * I suppose, after a card-select or erase, but I haven't tested
989 * those). Anyway, we're done and it's time to move on to the next
993 cmd->error = MMC_ERR_NONE;
994 at91_mci_next_operation(sc);
998 at91_mci_stop_done(struct at91_mci_softc *sc, uint32_t sr)
1000 struct mmc_command *cmd = sc->curcmd;
1003 * We arrive here after receiving CMDRDY for a MMC_STOP_TRANSMISSION
1004 * command. Depending on the operation being stopped, we may have to
1005 * do some unusual things to work around hardware bugs.
1009 * This is known to be true of at91rm9200 hardware; it may or may not
1010 * apply to more recent chips:
1012 * After stopping a multi-block write, the NOTBUSY bit in MCI_SR does
1013 * not properly reflect the actual busy state of the card as signaled
1014 * on the DAT0 line; it always claims the card is not-busy. If we
1015 * believe that and let operations continue, following commands will
1016 * fail with response timeouts (except of course MMC_SEND_STATUS -- it
1017 * indicates the card is busy in the PRG state, which was the smoking
1018 * gun that showed MCI_SR NOTBUSY was not tracking DAT0 correctly).
1020 * The atmel docs are emphatic: "This flag [NOTBUSY] must be used only
1021 * for Write Operations." I guess technically since we sent a stop
1022 * it's not a write operation anymore. But then just what did they
1023 * think it meant for the stop command to have "...an optional busy
1024 * signal transmitted on the data line" according to the SD spec?
1026 * I tried a variety of things to un-wedge the MCI and get the status
1027 * register to reflect NOTBUSY correctly again, but the only thing
1028 * that worked was a full device reset. It feels like an awfully big
1029 * hammer, but doing a full reset after every multiblock write is
1030 * still faster than doing single-block IO (by almost two orders of
1031 * magnitude: 20KB/sec improves to about 1.8MB/sec best case).
1033 * After doing the reset, wait for a NOTBUSY interrupt before
1034 * continuing with the next operation.
1036 * This workaround breaks multiwrite on the rev2xx parts, but some other
1037 * workaround is needed.
1039 if ((sc->flags & CMD_MULTIWRITE) && (sc->sc_cap & CAP_NEEDS_BYTESWAP)) {
1041 WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_NOTBUSY);
1046 * This is known to be true of at91rm9200 hardware; it may or may not
1047 * apply to more recent chips:
1049 * After stopping a multi-block read, loop to read and discard any
1050 * data that coasts in after we sent the stop command. The docs don't
1051 * say anything about it, but empirical testing shows that 1-3
1052 * additional words of data get buffered up in some unmentioned
1053 * internal fifo and if we don't read and discard them here they end
1054 * up on the front of the next read DMA transfer we do.
1056 * This appears to be unnecessary for rev2xx parts.
1058 if ((sc->flags & CMD_MULTIREAD) && (sc->sc_cap & CAP_NEEDS_BYTESWAP)) {
1063 sr = RD4(sc, MCI_SR);
1064 if (sr & MCI_SR_RXRDY) {
1068 } while (sr & MCI_SR_RXRDY);
1072 cmd->error = MMC_ERR_NONE;
1073 at91_mci_next_operation(sc);
1078 at91_mci_cmdrdy(struct at91_mci_softc *sc, uint32_t sr)
1080 struct mmc_command *cmd = sc->curcmd;
1087 * We get here at the end of EVERY command. We retrieve the command
1088 * response (if any) then decide what to do next based on the command.
1091 if (cmd->flags & MMC_RSP_PRESENT) {
1092 for (i = 0; i < ((cmd->flags & MMC_RSP_136) ? 4 : 1); i++) {
1093 cmd->resp[i] = RD4(sc, MCI_RSPR + i * 4);
1095 printf("RSPR[%d] = %x sr=%x\n", i, cmd->resp[i], sr);
1100 * If this was a stop command, go handle the various special
1101 * conditions (read: bugs) that have to be dealt with following a stop.
1103 if (cmd->opcode == MMC_STOP_TRANSMISSION) {
1104 at91_mci_stop_done(sc, sr);
1109 * If this command can continue to assert BUSY beyond the response then
1110 * we need to wait for NOTBUSY before the command is really done.
1112 * Note that this may not work properly on the at91rm9200. It certainly
1113 * doesn't work for the STOP command that follows a multi-block write,
1114 * so post-stop CMDRDY is handled separately; see the special handling
1115 * in at91_mci_stop_done().
1117 * Beside STOP, there are other R1B-type commands that use the busy
1118 * signal after CMDRDY: CMD7 (card select), CMD28-29 (write protect),
1119 * CMD38 (erase). I haven't tested any of them, but I rather expect
1120 * them all to have the same sort of problem with MCI_SR not actually
1121 * reflecting the state of the DAT0-line busy indicator. So this code
1122 * may need to grow some sort of special handling for them too. (This
1123 * just in: CMD7 isn't a problem right now because dev/mmc.c incorrectly
1124 * sets the response flags to R1 rather than R1B.) XXX
1126 if ((cmd->flags & MMC_RSP_BUSY)) {
1127 WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_NOTBUSY);
1132 * If there is a data transfer with this command, then...
1133 * - If it's a read, we need to wait for ENDRX.
1134 * - If it's a write, now is the time to enable the PDC, and we need
1135 * to wait for a BLKE that follows a TXBUFE, because if we're doing
1136 * a split transfer we get a BLKE after the first half (when TPR/TCR
1137 * get loaded from TNPR/TNCR). So first we wait for the TXBUFE, and
1138 * the handling for that interrupt will then invoke the wait for the
1139 * subsequent BLKE which indicates actual completion.
1143 if (cmd->data->flags & MMC_DATA_READ) {
1146 ier = MCI_SR_TXBUFE;
1147 WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN);
1149 WR4(sc, MCI_IER, MCI_SR_ERROR | ier);
1154 * If we made it to here, we don't need to wait for anything more for
1155 * the current command, move on to the next command (will complete the
1156 * request if there is no next command).
1158 cmd->error = MMC_ERR_NONE;
1159 at91_mci_next_operation(sc);
1163 at91_mci_intr(void *arg)
1165 struct at91_mci_softc *sc = (struct at91_mci_softc*)arg;
1166 struct mmc_command *cmd = sc->curcmd;
1171 sr = RD4(sc, MCI_SR);
1172 isr = sr & RD4(sc, MCI_IMR);
1175 printf("i 0x%x sr 0x%x\n", isr, sr);
1178 * All interrupts are one-shot; disable it now.
1179 * The next operation will re-enable whatever interrupts it wants.
1181 WR4(sc, MCI_IDR, isr);
1182 if (isr & MCI_SR_ERROR) {
1183 if (isr & (MCI_SR_RTOE | MCI_SR_DTOE))
1184 cmd->error = MMC_ERR_TIMEOUT;
1185 else if (isr & (MCI_SR_RCRCE | MCI_SR_DCRCE))
1186 cmd->error = MMC_ERR_BADCRC;
1187 else if (isr & (MCI_SR_OVRE | MCI_SR_UNRE))
1188 cmd->error = MMC_ERR_FIFO;
1190 cmd->error = MMC_ERR_FAILED;
1192 * CMD8 is used to probe for SDHC cards, a standard SD card
1193 * will get a response timeout; don't report it because it's a
1194 * normal and expected condition. One might argue that all
1195 * error reporting should be left to higher levels, but when
1196 * they report at all it's always EIO, which isn't very
1197 * helpful. XXX bootverbose?
1199 if (cmd->opcode != 8) {
1200 device_printf(sc->dev,
1201 "IO error; status MCI_SR = 0x%b cmd opcode = %d%s\n",
1202 sr, MCI_SR_BITSTRING, cmd->opcode,
1203 (cmd->opcode != 12) ? "" :
1204 (sc->flags & CMD_MULTIREAD) ? " after read" : " after write");
1205 /* XXX not sure RTOE needs a full reset, just a retry */
1208 at91_mci_next_operation(sc);
1210 if (isr & MCI_SR_TXBUFE) {
1211 // printf("TXBUFE\n");
1213 * We need to wait for a BLKE that follows TXBUFE
1214 * (intermediate BLKEs might happen after ENDTXes if
1215 * we're chaining multiple buffers). If BLKE is also
1216 * asserted at the time we get TXBUFE, we can avoid
1217 * another interrupt and process it right away, below.
1219 if (sr & MCI_SR_BLKE)
1222 WR4(sc, MCI_IER, MCI_SR_BLKE);
1224 if (isr & MCI_SR_RXBUFF) {
1225 // printf("RXBUFF\n");
1227 if (isr & MCI_SR_ENDTX) {
1228 // printf("ENDTX\n");
1230 if (isr & MCI_SR_ENDRX) {
1231 // printf("ENDRX\n");
1232 at91_mci_read_done(sc, sr);
1234 if (isr & MCI_SR_NOTBUSY) {
1235 // printf("NOTBUSY\n");
1236 at91_mci_notbusy(sc);
1238 if (isr & MCI_SR_DTIP) {
1239 // printf("Data transfer in progress\n");
1241 if (isr & MCI_SR_BLKE) {
1242 // printf("Block transfer end\n");
1243 at91_mci_write_done(sc, sr);
1245 if (isr & MCI_SR_TXRDY) {
1246 // printf("Ready to transmit\n");
1248 if (isr & MCI_SR_RXRDY) {
1249 // printf("Ready to receive\n");
1251 if (isr & MCI_SR_CMDRDY) {
1252 // printf("Command ready\n");
1253 at91_mci_cmdrdy(sc, sr);
1256 AT91_MCI_UNLOCK(sc);
1260 at91_mci_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
1262 struct at91_mci_softc *sc = device_get_softc(bus);
1267 case MMCBR_IVAR_BUS_MODE:
1268 *(int *)result = sc->host.ios.bus_mode;
1270 case MMCBR_IVAR_BUS_WIDTH:
1271 *(int *)result = sc->host.ios.bus_width;
1273 case MMCBR_IVAR_CHIP_SELECT:
1274 *(int *)result = sc->host.ios.chip_select;
1276 case MMCBR_IVAR_CLOCK:
1277 *(int *)result = sc->host.ios.clock;
1279 case MMCBR_IVAR_F_MIN:
1280 *(int *)result = sc->host.f_min;
1282 case MMCBR_IVAR_F_MAX:
1283 *(int *)result = sc->host.f_max;
1285 case MMCBR_IVAR_HOST_OCR:
1286 *(int *)result = sc->host.host_ocr;
1288 case MMCBR_IVAR_MODE:
1289 *(int *)result = sc->host.mode;
1291 case MMCBR_IVAR_OCR:
1292 *(int *)result = sc->host.ocr;
1294 case MMCBR_IVAR_POWER_MODE:
1295 *(int *)result = sc->host.ios.power_mode;
1297 case MMCBR_IVAR_VDD:
1298 *(int *)result = sc->host.ios.vdd;
1300 case MMCBR_IVAR_CAPS:
1301 if (sc->has_4wire) {
1302 sc->sc_cap |= CAP_HAS_4WIRE;
1303 sc->host.caps |= MMC_CAP_4_BIT_DATA;
1305 sc->sc_cap &= ~CAP_HAS_4WIRE;
1306 sc->host.caps &= ~MMC_CAP_4_BIT_DATA;
1308 *(int *)result = sc->host.caps;
1310 case MMCBR_IVAR_MAX_DATA:
1312 * Something is wrong with the 2x parts and multiblock, so
1313 * just do 1 block at a time for now, which really kills
1316 if (sc->sc_cap & CAP_MCI1_REV2XX)
1319 *(int *)result = MAX_BLOCKS;
1326 at91_mci_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
1328 struct at91_mci_softc *sc = device_get_softc(bus);
1333 case MMCBR_IVAR_BUS_MODE:
1334 sc->host.ios.bus_mode = value;
1336 case MMCBR_IVAR_BUS_WIDTH:
1337 sc->host.ios.bus_width = value;
1339 case MMCBR_IVAR_CHIP_SELECT:
1340 sc->host.ios.chip_select = value;
1342 case MMCBR_IVAR_CLOCK:
1343 sc->host.ios.clock = value;
1345 case MMCBR_IVAR_MODE:
1346 sc->host.mode = value;
1348 case MMCBR_IVAR_OCR:
1349 sc->host.ocr = value;
1351 case MMCBR_IVAR_POWER_MODE:
1352 sc->host.ios.power_mode = value;
1354 case MMCBR_IVAR_VDD:
1355 sc->host.ios.vdd = value;
1357 /* These are read-only */
1358 case MMCBR_IVAR_CAPS:
1359 case MMCBR_IVAR_HOST_OCR:
1360 case MMCBR_IVAR_F_MIN:
1361 case MMCBR_IVAR_F_MAX:
1362 case MMCBR_IVAR_MAX_DATA:
1368 static device_method_t at91_mci_methods[] = {
1370 DEVMETHOD(device_probe, at91_mci_probe),
1371 DEVMETHOD(device_attach, at91_mci_attach),
1372 DEVMETHOD(device_detach, at91_mci_detach),
1375 DEVMETHOD(bus_read_ivar, at91_mci_read_ivar),
1376 DEVMETHOD(bus_write_ivar, at91_mci_write_ivar),
1379 DEVMETHOD(mmcbr_update_ios, at91_mci_update_ios),
1380 DEVMETHOD(mmcbr_request, at91_mci_request),
1381 DEVMETHOD(mmcbr_get_ro, at91_mci_get_ro),
1382 DEVMETHOD(mmcbr_acquire_host, at91_mci_acquire_host),
1383 DEVMETHOD(mmcbr_release_host, at91_mci_release_host),
1388 static driver_t at91_mci_driver = {
1391 sizeof(struct at91_mci_softc),
1394 static devclass_t at91_mci_devclass;
1397 DRIVER_MODULE(at91_mci, simplebus, at91_mci_driver, at91_mci_devclass, NULL,
1400 DRIVER_MODULE(at91_mci, atmelarm, at91_mci_driver, at91_mci_devclass, NULL,
1404 MMC_DECLARE_BRIDGE(at91_mci);