2 * Copyright (c) 2006 Bernd Walter. All rights reserved.
3 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
29 #include <sys/param.h>
30 #include <sys/systm.h>
34 #include <sys/endian.h>
35 #include <sys/kernel.h>
36 #include <sys/kthread.h>
38 #include <sys/malloc.h>
39 #include <sys/module.h>
40 #include <sys/mutex.h>
41 #include <sys/queue.h>
42 #include <sys/resource.h>
45 #include <sys/timetc.h>
46 #include <sys/watchdog.h>
48 #include <machine/bus.h>
49 #include <machine/cpu.h>
50 #include <machine/cpufunc.h>
51 #include <machine/resource.h>
52 #include <machine/frame.h>
53 #include <machine/intr.h>
54 #include <arm/at91/at91rm92reg.h>
55 #include <arm/at91/at91var.h>
56 #include <arm/at91/at91_mcireg.h>
57 #include <arm/at91/at91_pdcreg.h>
58 #include <dev/mmc/bridge.h>
59 #include <dev/mmc/mmcreg.h>
60 #include <dev/mmc/mmcbrvar.h>
66 struct at91_mci_softc {
67 void *intrhand; /* Interrupt handle */
71 #define STOP_STARTED 2
72 struct resource *irq_res; /* IRQ resource */
73 struct resource *mem_res; /* Memory resource */
81 struct mmc_request *req;
82 struct mmc_command *curcmd;
83 char bounce_buffer[BBSZ];
86 static inline uint32_t
87 RD4(struct at91_mci_softc *sc, bus_size_t off)
89 return bus_read_4(sc->mem_res, off);
93 WR4(struct at91_mci_softc *sc, bus_size_t off, uint32_t val)
95 bus_write_4(sc->mem_res, off, val);
98 /* bus entry points */
99 static int at91_mci_probe(device_t dev);
100 static int at91_mci_attach(device_t dev);
101 static int at91_mci_detach(device_t dev);
102 static void at91_mci_intr(void *);
104 /* helper routines */
105 static int at91_mci_activate(device_t dev);
106 static void at91_mci_deactivate(device_t dev);
108 #define AT91_MCI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
109 #define AT91_MCI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
110 #define AT91_MCI_LOCK_INIT(_sc) \
111 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
113 #define AT91_MCI_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
114 #define AT91_MCI_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
115 #define AT91_MCI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
118 at91_mci_pdc_disable(struct at91_mci_softc *sc)
120 WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS);
123 WR4(sc, PDC_RNPR, 0);
124 WR4(sc, PDC_RNCR, 0);
127 WR4(sc, PDC_TNPR, 0);
128 WR4(sc, PDC_TNCR, 0);
132 at91_mci_init(device_t dev)
134 struct at91_mci_softc *sc = device_get_softc(dev);
136 WR4(sc, MCI_CR, MCI_CR_MCIEN); /* Enable controller */
137 WR4(sc, MCI_IDR, 0xffffffff); /* Turn off interrupts */
138 WR4(sc, MCI_DTOR, MCI_DTOR_DTOMUL_1M | 1);
139 WR4(sc, MCI_MR, 0x834a); // XXX GROSS HACK FROM LINUX
140 WR4(sc, MCI_SDCR, 0); /* SLOT A, 1 bit bus */
144 at91_mci_fini(device_t dev)
146 struct at91_mci_softc *sc = device_get_softc(dev);
148 WR4(sc, MCI_IDR, 0xffffffff); /* Turn off interrupts */
149 at91_mci_pdc_disable(sc);
150 WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST); /* Put the device into reset */
154 at91_mci_probe(device_t dev)
157 device_set_desc(dev, "MCI mmc/sd host bridge");
162 at91_mci_attach(device_t dev)
164 struct at91_mci_softc *sc = device_get_softc(dev);
169 err = at91_mci_activate(dev);
173 AT91_MCI_LOCK_INIT(sc);
176 * Allocate DMA tags and maps
178 err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
179 BUS_SPACE_MAXADDR, NULL, NULL, MAXPHYS, 1, MAXPHYS,
180 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->dmatag);
184 err = bus_dmamap_create(sc->dmatag, 0, &sc->map);
192 * Activate the interrupt
194 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
195 at91_mci_intr, sc, &sc->intrhand);
197 AT91_MCI_LOCK_DESTROY(sc);
200 sc->host.f_min = 375000;
201 sc->host.f_max = 30000000;
202 sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
203 sc->host.caps = MMC_CAP_4_BIT_DATA;
204 child = device_add_child(dev, "mmc", 0);
205 device_set_ivars(dev, &sc->host);
206 err = bus_generic_attach(dev);
209 at91_mci_deactivate(dev);
214 at91_mci_detach(device_t dev)
217 at91_mci_deactivate(dev);
218 return (EBUSY); /* XXX */
222 at91_mci_activate(device_t dev)
224 struct at91_mci_softc *sc;
227 sc = device_get_softc(dev);
229 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
231 if (sc->mem_res == NULL)
234 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
236 if (sc->irq_res == NULL)
240 at91_mci_deactivate(dev);
245 at91_mci_deactivate(device_t dev)
247 struct at91_mci_softc *sc;
249 sc = device_get_softc(dev);
251 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
253 bus_generic_detach(sc->dev);
255 bus_release_resource(dev, SYS_RES_IOPORT,
256 rman_get_rid(sc->mem_res), sc->mem_res);
259 bus_release_resource(dev, SYS_RES_IRQ,
260 rman_get_rid(sc->irq_res), sc->irq_res);
266 at91_mci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
270 *(bus_addr_t *)arg = segs[0].ds_addr;
274 at91_mci_update_ios(device_t brdev, device_t reqdev)
276 uint32_t at91_master_clock = AT91C_MASTER_CLOCK;
277 struct at91_mci_softc *sc;
278 struct mmc_host *host;
282 sc = device_get_softc(brdev);
286 if (ios->clock == 0) {
287 WR4(sc, MCI_CR, MCI_CR_MCIDIS);
290 WR4(sc, MCI_CR, MCI_CR_MCIEN);
291 if ((at91_master_clock % (ios->clock * 2)) == 0)
292 clkdiv = ((at91_master_clock / ios->clock) / 2) - 1;
294 clkdiv = (at91_master_clock / ios->clock) / 2;
296 if (ios->bus_width == bus_width_4 && sc->wire4) {
297 device_printf(sc->dev, "Setting controller bus width to 4\n");
298 WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) | MCI_SDCR_SDCBUS);
300 device_printf(sc->dev, "Setting controller bus width to 1\n");
301 WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) & ~MCI_SDCR_SDCBUS);
303 WR4(sc, MCI_MR, (RD4(sc, MCI_MR) & ~MCI_MR_CLKDIV) | clkdiv);
306 if (sc->power_mode == MMC_POWER_OFF)
307 gpio_set(sc->vcc_pin, 0);
309 gpio_set(sc->vcc_pin, 1);
316 at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd)
318 uint32_t cmdr, ier = 0, mr;
321 struct mmc_data *data;
322 struct mmc_request *req;
323 size_t block_size = 1 << 9; // Fixed, per mmc/sd spec for 2GB cards
331 if (MMC_RSP(cmd->flags) == MMC_RSP_NONE)
332 cmdr |= MCI_CMDR_RSPTYP_NO;
334 /* Allow big timeout for responses */
335 cmdr |= MCI_CMDR_MAXLAT;
336 if (cmd->flags & MMC_RSP_136)
337 cmdr |= MCI_CMDR_RSPTYP_136;
339 cmdr |= MCI_CMDR_RSPTYP_48;
341 if (cmd->opcode == MMC_STOP_TRANSMISSION)
342 cmdr |= MCI_CMDR_TRCMD_STOP;
343 if (sc->host.ios.bus_mode == opendrain)
344 cmdr |= MCI_CMDR_OPDCMD;
346 // The no data case is fairly simple
347 at91_mci_pdc_disable(sc);
348 // printf("CMDR %x ARGR %x\n", cmdr, cmd->arg);
349 WR4(sc, MCI_ARGR, cmd->arg);
350 WR4(sc, MCI_CMDR, cmdr);
351 WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_CMDRDY);
354 if (data->flags & MMC_DATA_READ)
355 cmdr |= MCI_CMDR_TRDIR;
356 if (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE))
357 cmdr |= MCI_CMDR_TRCMD_START;
358 if (data->flags & MMC_DATA_STREAM)
359 cmdr |= MCI_CMDR_TRTYP_STREAM;
360 if (data->flags & MMC_DATA_MULTI)
361 cmdr |= MCI_CMDR_TRTYP_MULTIPLE;
362 // Set block size and turn on PDC mode for dma xfer and disable
363 // PDC until we're ready.
364 mr = RD4(sc, MCI_MR) & ~MCI_MR_BLKLEN;
365 WR4(sc, MCI_MR, mr | (block_size << 16) | MCI_MR_PDCMODE);
366 WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
367 if (cmdr & MCI_CMDR_TRCMD_START) {
368 if (cmdr & MCI_CMDR_TRDIR)
369 vaddr = cmd->data->data;
371 if (data->len != BBSZ)
372 panic("Write multiblock write support");
373 vaddr = sc->bounce_buffer;
374 src = (uint32_t *)cmd->data->data;
375 dst = (uint32_t *)vaddr;
376 for (i = 0; i < data->len / 4; i++)
377 dst[i] = bswap32(src[i]);
380 if (bus_dmamap_load(sc->dmatag, sc->map, vaddr, data->len,
381 at91_mci_getaddr, &paddr, 0) != 0) {
382 if (req->cmd->flags & STOP_STARTED)
383 req->stop->error = MMC_ERR_NO_MEMORY;
385 req->cmd->error = MMC_ERR_NO_MEMORY;
392 if (cmdr & MCI_CMDR_TRDIR) {
393 bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_PREREAD);
394 WR4(sc, PDC_RPR, paddr);
395 WR4(sc, PDC_RCR, data->len / 4);
398 bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_PREWRITE);
399 WR4(sc, PDC_TPR, paddr);
400 WR4(sc, PDC_TCR, data->len / 4);
404 // printf("CMDR %x ARGR %x with data\n", cmdr, cmd->arg);
405 WR4(sc, MCI_ARGR, cmd->arg);
406 WR4(sc, MCI_CMDR, cmdr);
407 if (cmdr & MCI_CMDR_TRCMD_START) {
408 if (cmdr & MCI_CMDR_TRDIR)
409 WR4(sc, PDC_PTCR, PDC_PTCR_RXTEN);
411 WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN);
413 WR4(sc, MCI_IER, MCI_SR_ERROR | ier);
417 at91_mci_start(struct at91_mci_softc *sc)
419 struct mmc_request *req;
425 if (!(sc->flags & CMD_STARTED)) {
426 sc->flags |= CMD_STARTED;
427 // printf("Starting CMD\n");
428 at91_mci_start_cmd(sc, req->cmd);
431 if (!(sc->flags & STOP_STARTED) && req->stop) {
432 // printf("Starting Stop\n");
433 sc->flags |= STOP_STARTED;
434 at91_mci_start_cmd(sc, req->stop);
437 /* We must be done -- bad idea to do this while locked? */
444 at91_mci_request(device_t brdev, device_t reqdev, struct mmc_request *req)
446 struct at91_mci_softc *sc = device_get_softc(brdev);
449 // XXX do we want to be able to queue up multiple commands?
450 // XXX sounds like a good idea, but all protocols are sync, so
451 // XXX maybe the idea is naive...
452 if (sc->req != NULL) {
464 at91_mci_get_ro(device_t brdev, device_t reqdev)
470 at91_mci_acquire_host(device_t brdev, device_t reqdev)
472 struct at91_mci_softc *sc = device_get_softc(brdev);
477 msleep(sc, &sc->sc_mtx, PZERO, "mciah", hz / 5);
484 at91_mci_release_host(device_t brdev, device_t reqdev)
486 struct at91_mci_softc *sc = device_get_softc(brdev);
496 at91_mci_read_done(struct at91_mci_softc *sc)
499 struct mmc_command *cmd;
503 bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_POSTREAD);
504 bus_dmamap_unload(sc->dmatag, sc->map);
506 walker = (uint32_t *)cmd->data->data;
507 len = cmd->data->len / 4;
508 for (i = 0; i < len; i++)
509 walker[i] = bswap32(walker[i]);
510 // Finish up the sequence...
511 WR4(sc, MCI_IDR, MCI_SR_ENDRX);
512 WR4(sc, MCI_IER, MCI_SR_RXBUFF);
513 WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
517 at91_mci_xmit_done(struct at91_mci_softc *sc)
519 // Finish up the sequence...
520 WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
521 WR4(sc, MCI_IDR, MCI_SR_TXBUFE);
522 WR4(sc, MCI_IER, MCI_SR_NOTBUSY);
523 bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_POSTWRITE);
524 bus_dmamap_unload(sc->dmatag, sc->map);
529 at91_mci_intr(void *arg)
531 struct at91_mci_softc *sc = (struct at91_mci_softc*)arg;
534 struct mmc_command *cmd;
537 sr = RD4(sc, MCI_SR) & RD4(sc, MCI_IMR);
538 // printf("i 0x%x\n", sr);
540 if (sr & MCI_SR_ERROR) {
541 // Ignore CRC errors on CMD2 and ACMD47, per relevant standards
542 if ((sr & MCI_SR_RCRCE) && (cmd->opcode == MMC_SEND_OP_COND ||
543 cmd->opcode == ACMD_SD_SEND_OP_COND))
544 cmd->error = MMC_ERR_NONE;
545 else if (sr & (MCI_SR_RTOE | MCI_SR_DTOE))
546 cmd->error = MMC_ERR_TIMEOUT;
547 else if (sr & (MCI_SR_RCRCE | MCI_SR_DCRCE))
548 cmd->error = MMC_ERR_BADCRC;
549 else if (sr & (MCI_SR_OVRE | MCI_SR_UNRE))
550 cmd->error = MMC_ERR_FIFO;
552 cmd->error = MMC_ERR_FAILED;
554 if (sc->mapped && cmd->error) {
555 bus_dmamap_unload(sc->dmatag, sc->map);
559 if (sr & MCI_SR_TXBUFE) {
560 // printf("TXBUFE\n");
561 at91_mci_xmit_done(sc);
563 if (sr & MCI_SR_RXBUFF) {
564 // printf("RXBUFF\n");
565 WR4(sc, MCI_IDR, MCI_SR_RXBUFF);
566 WR4(sc, MCI_IER, MCI_SR_CMDRDY);
568 if (sr & MCI_SR_ENDTX) {
569 // printf("ENDTX\n");
571 if (sr & MCI_SR_ENDRX) {
572 // printf("ENDRX\n");
573 at91_mci_read_done(sc);
575 if (sr & MCI_SR_NOTBUSY) {
576 // printf("NOTBUSY\n");
577 WR4(sc, MCI_IDR, MCI_SR_NOTBUSY);
578 WR4(sc, MCI_IER, MCI_SR_CMDRDY);
580 if (sr & MCI_SR_DTIP) {
581 // printf("Data transfer in progress\n");
583 if (sr & MCI_SR_BLKE) {
584 // printf("Block transfer end\n");
586 if (sr & MCI_SR_TXRDY) {
587 // printf("Ready to transmit\n");
589 if (sr & MCI_SR_RXRDY) {
590 // printf("Ready to receive\n");
592 if (sr & MCI_SR_CMDRDY) {
593 // printf("Command ready\n");
595 cmd->error = MMC_ERR_NONE;
599 WR4(sc, MCI_IDR, 0xffffffff);
600 if (cmd != NULL && (cmd->flags & MMC_RSP_PRESENT)) {
601 for (i = 0; i < ((cmd->flags & MMC_RSP_136) ? 4 : 1);
603 cmd->resp[i] = RD4(sc, MCI_RSPR + i * 4);
604 // printf("RSPR[%d] = %x\n", i, cmd->resp[i]);
613 at91_mci_read_ivar(device_t bus, device_t child, int which, u_char *result)
615 struct at91_mci_softc *sc = device_get_softc(bus);
620 case MMCBR_IVAR_BUS_MODE:
621 *(int *)result = sc->host.ios.bus_mode;
623 case MMCBR_IVAR_BUS_WIDTH:
624 *(int *)result = sc->host.ios.bus_width;
626 case MMCBR_IVAR_CHIP_SELECT:
627 *(int *)result = sc->host.ios.chip_select;
629 case MMCBR_IVAR_CLOCK:
630 *(int *)result = sc->host.ios.clock;
632 case MMCBR_IVAR_F_MIN:
633 *(int *)result = sc->host.f_min;
635 case MMCBR_IVAR_F_MAX:
636 *(int *)result = sc->host.f_max;
638 case MMCBR_IVAR_HOST_OCR:
639 *(int *)result = sc->host.host_ocr;
641 case MMCBR_IVAR_MODE:
642 *(int *)result = sc->host.mode;
645 *(int *)result = sc->host.ocr;
647 case MMCBR_IVAR_POWER_MODE:
648 *(int *)result = sc->host.ios.power_mode;
651 *(int *)result = sc->host.ios.vdd;
658 at91_mci_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
660 struct at91_mci_softc *sc = device_get_softc(bus);
665 case MMCBR_IVAR_BUS_MODE:
666 sc->host.ios.bus_mode = value;
668 case MMCBR_IVAR_BUS_WIDTH:
669 sc->host.ios.bus_width = value;
671 case MMCBR_IVAR_CHIP_SELECT:
672 sc->host.ios.chip_select = value;
674 case MMCBR_IVAR_CLOCK:
675 sc->host.ios.clock = value;
677 case MMCBR_IVAR_MODE:
678 sc->host.mode = value;
681 sc->host.ocr = value;
683 case MMCBR_IVAR_POWER_MODE:
684 sc->host.ios.power_mode = value;
687 sc->host.ios.vdd = value;
689 case MMCBR_IVAR_HOST_OCR:
690 case MMCBR_IVAR_F_MIN:
691 case MMCBR_IVAR_F_MAX:
697 static device_method_t at91_mci_methods[] = {
699 DEVMETHOD(device_probe, at91_mci_probe),
700 DEVMETHOD(device_attach, at91_mci_attach),
701 DEVMETHOD(device_detach, at91_mci_detach),
704 DEVMETHOD(bus_read_ivar, at91_mci_read_ivar),
705 DEVMETHOD(bus_write_ivar, at91_mci_write_ivar),
708 DEVMETHOD(mmcbr_update_ios, at91_mci_update_ios),
709 DEVMETHOD(mmcbr_request, at91_mci_request),
710 DEVMETHOD(mmcbr_get_ro, at91_mci_get_ro),
711 DEVMETHOD(mmcbr_acquire_host, at91_mci_acquire_host),
712 DEVMETHOD(mmcbr_release_host, at91_mci_release_host),
717 static driver_t at91_mci_driver = {
720 sizeof(struct at91_mci_softc),
722 static devclass_t at91_mci_devclass;
725 DRIVER_MODULE(at91_mci, atmelarm, at91_mci_driver, at91_mci_devclass, 0, 0);