2 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
3 * Copyright (c) 2010 Greg Ansley. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include "opt_platform.h"
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
39 #include <sys/resource.h>
41 #include <sys/timetc.h>
43 #include <machine/bus.h>
44 #include <machine/resource.h>
45 #include <machine/intr.h>
46 #include <arm/at91/at91reg.h>
47 #include <arm/at91/at91var.h>
49 #include <arm/at91/at91_pmcreg.h>
50 #include <arm/at91/at91_pmcvar.h>
53 #include <dev/ofw/ofw_bus.h>
54 #include <dev/ofw/ofw_bus_subr.h>
57 static struct at91_pmc_softc {
58 bus_space_tag_t sc_st;
59 bus_space_handle_t sc_sh;
60 struct resource *mem_res; /* Memory resource */
64 static uint32_t pllb_init;
66 MALLOC_DECLARE(M_PMC);
67 MALLOC_DEFINE(M_PMC, "at91_pmc_clocks", "AT91 PMC Clock descriptors");
69 #define AT91_PMC_BASE 0xffffc00
71 static void at91_pmc_set_pllb_mode(struct at91_pmc_clock *, int);
72 static void at91_pmc_set_upll_mode(struct at91_pmc_clock *, int);
73 static void at91_pmc_set_sys_mode(struct at91_pmc_clock *, int);
74 static void at91_pmc_set_periph_mode(struct at91_pmc_clock *, int);
75 static void at91_pmc_clock_alias(const char *name, const char *alias);
77 static struct at91_pmc_clock slck = {
78 .name = "slck", /* 32,768 Hz slow clock */
86 * NOTE: Clocks for "ordinary peripheral" devices e.g. spi0, udp0, uhp0 etc.
87 * are now created automatically. Only "system" clocks need be defined here.
89 static struct at91_pmc_clock main_ck = {
90 .name = "main", /* Main clock */
94 .pmc_mask = PMC_IER_MOSCS,
97 static struct at91_pmc_clock plla = {
98 .name = "plla", /* PLLA Clock, used for CPU clocking */
104 .pmc_mask = PMC_IER_LOCKA,
107 static struct at91_pmc_clock pllb = {
108 .name = "pllb", /* PLLB Clock, used for USB functions */
114 .pmc_mask = PMC_IER_LOCKB,
115 .set_mode = &at91_pmc_set_pllb_mode,
118 /* Used by USB on at91sam9g45 */
119 static struct at91_pmc_clock upll = {
120 .name = "upll", /* UTMI PLL, used for USB functions on 9G45 family */
126 .pmc_mask = (1 << 6),
127 .set_mode = &at91_pmc_set_upll_mode,
130 static struct at91_pmc_clock udpck = {
133 .pmc_mask = PMC_SCER_UDP,
134 .set_mode = at91_pmc_set_sys_mode
137 static struct at91_pmc_clock uhpck = {
140 .pmc_mask = PMC_SCER_UHP,
141 .set_mode = at91_pmc_set_sys_mode
144 static struct at91_pmc_clock mck = {
145 .name = "mck", /* Master (Peripheral) Clock */
146 .pmc_mask = PMC_IER_MCKRDY,
150 static struct at91_pmc_clock cpu = {
151 .name = "cpu", /* CPU Clock */
153 .pmc_mask = PMC_SCER_PCK,
157 /* "+32" or the automatic peripheral clocks */
158 static struct at91_pmc_clock *clock_list[16+32] = {
170 static inline uint32_t
171 RD4(struct at91_pmc_softc *sc, bus_size_t off)
175 uint32_t *p = (uint32_t *)(AT91_BASE + AT91_PMC_BASE + off);
179 return (bus_read_4(sc->mem_res, off));
183 WR4(struct at91_pmc_softc *sc, bus_size_t off, uint32_t val)
187 uint32_t *p = (uint32_t *)(AT91_BASE + AT91_PMC_BASE + off);
191 bus_write_4(sc->mem_res, off, val);
195 * The following is unused currently since we don't ever set the PLLA
196 * frequency of the device. If we did, we'd have to also pay attention
197 * to the ICPLLA bit in the PMC_PLLICPR register for frequencies lower
198 * than ~600MHz, which the PMC code doesn't do right now.
201 at91_pmc_800mhz_plla_outb(int freq)
206 * Set OUTA, per the data sheet. See Table 46-16 titled
207 * PLLA Frequency Regarding ICPLLA and OUTA in the SAM9X25 doc,
208 * Table 46-17 in the SAM9G20 doc, or Table 46-16 in the SAM9G45 doc.
209 * Note: the frequencies overlap by 5MHz, so we add 3 here to
210 * center shoot the transition.
213 freq /= 1000000; /* MHz */
216 freq += 3; /* Allow for overlap. */
217 outa = 3 - ((freq / 50) & 3); /* 750 / 50 = 7, see table */
218 return (1 << 29)| (outa << 14);
222 at91_pmc_800mhz_pllb_outb(int freq)
229 at91_pmc_set_pllb_mode(struct at91_pmc_clock *clk, int on)
231 struct at91_pmc_softc *sc = pmc_softc;
234 value = on ? pllb_init : 0;
237 * Only write to the register if the value is changing. Besides being
238 * good common sense, this works around RM9200 Errata #26 (CKGR_PLL[AB]R
239 * must not be written with the same value currently in the register).
241 if (RD4(sc, CKGR_PLLBR) != value) {
242 WR4(sc, CKGR_PLLBR, value);
243 while (on && (RD4(sc, PMC_SR) & PMC_IER_LOCKB) != PMC_IER_LOCKB)
249 at91_pmc_set_upll_mode(struct at91_pmc_clock *clk, int on)
251 struct at91_pmc_softc *sc = pmc_softc;
256 value = CKGR_UCKR_UPLLEN | CKGR_UCKR_BIASEN;
260 WR4(sc, CKGR_UCKR, RD4(sc, CKGR_UCKR) | value);
261 while ((RD4(sc, PMC_SR) & PMC_IER_LOCKU) != on)
264 WR4(sc, PMC_USB, PMC_USB_USBDIV(9) | PMC_USB_USBS);
265 WR4(sc, PMC_SCER, PMC_SCER_UHP_SAM9);
269 at91_pmc_set_sys_mode(struct at91_pmc_clock *clk, int on)
271 struct at91_pmc_softc *sc = pmc_softc;
273 WR4(sc, on ? PMC_SCER : PMC_SCDR, clk->pmc_mask);
275 while ((RD4(sc, PMC_SCSR) & clk->pmc_mask) != clk->pmc_mask)
278 while ((RD4(sc, PMC_SCSR) & clk->pmc_mask) == clk->pmc_mask)
283 at91_pmc_set_periph_mode(struct at91_pmc_clock *clk, int on)
285 struct at91_pmc_softc *sc = pmc_softc;
287 WR4(sc, on ? PMC_PCER : PMC_PCDR, clk->pmc_mask);
289 while ((RD4(sc, PMC_PCSR) & clk->pmc_mask) != clk->pmc_mask)
292 while ((RD4(sc, PMC_PCSR) & clk->pmc_mask) == clk->pmc_mask)
296 struct at91_pmc_clock *
297 at91_pmc_clock_add(const char *name, uint32_t irq,
298 struct at91_pmc_clock *parent)
300 struct at91_pmc_clock *clk;
303 clk = malloc(sizeof(*clk), M_PMC, M_NOWAIT | M_ZERO);
307 buflen = strlen(name) + 1;
308 clk->name = malloc(buflen, M_PMC, M_NOWAIT);
309 if (clk->name == NULL)
312 strlcpy(clk->name, name, buflen);
313 clk->pmc_mask = 1 << irq;
314 clk->set_mode = &at91_pmc_set_periph_mode;
318 clk->parent = parent;
320 for (i = 0; i < nitems(clock_list); i++) {
321 if (clock_list[i] == NULL) {
328 if (clk->name != NULL)
329 free(clk->name, M_PMC);
333 panic("could not allocate pmc clock '%s'", name);
338 at91_pmc_clock_alias(const char *name, const char *alias)
340 struct at91_pmc_clock *clk, *alias_clk;
342 clk = at91_pmc_clock_ref(name);
344 alias_clk = at91_pmc_clock_add(alias, 0, clk->parent);
346 if (clk && alias_clk) {
347 alias_clk->hz = clk->hz;
348 alias_clk->pmc_mask = clk->pmc_mask;
349 alias_clk->set_mode = clk->set_mode;
353 struct at91_pmc_clock *
354 at91_pmc_clock_ref(const char *name)
358 for (i = 0; i < nitems(clock_list); i++) {
359 if (clock_list[i] == NULL)
361 if (strcmp(name, clock_list[i]->name) == 0)
362 return (clock_list[i]);
369 at91_pmc_clock_deref(struct at91_pmc_clock *clk)
376 at91_pmc_clock_enable(struct at91_pmc_clock *clk)
381 /* XXX LOCKING? XXX */
383 at91_pmc_clock_enable(clk->parent);
384 if (clk->refcnt++ == 0 && clk->set_mode)
385 clk->set_mode(clk, 1);
389 at91_pmc_clock_disable(struct at91_pmc_clock *clk)
394 /* XXX LOCKING? XXX */
395 if (--clk->refcnt == 0 && clk->set_mode)
396 clk->set_mode(clk, 0);
398 at91_pmc_clock_disable(clk->parent);
402 at91_pmc_pll_rate(struct at91_pmc_clock *clk, uint32_t reg)
404 uint32_t mul, div, freq;
406 freq = clk->parent->hz;
407 div = (reg >> clk->pll_div_shift) & clk->pll_div_mask;
408 mul = (reg >> clk->pll_mul_shift) & clk->pll_mul_mask;
411 printf("pll = (%d / %d) * %d = %d\n",
412 freq, div, mul + 1, (freq/div) * (mul+1));
415 if (div != 0 && mul != 0) {
426 at91_pmc_pll_calc(struct at91_pmc_clock *clk, uint32_t out_freq)
428 uint32_t i, div = 0, mul = 0, diff = 1 << 30;
430 unsigned ret = 0x3e00;
432 if (out_freq > clk->pll_max_out)
435 for (i = 1; i < 256; i++) {
437 uint32_t input, mul1;
439 input = clk->parent->hz / i;
440 if (input < clk->pll_min_in)
442 if (input > clk->pll_max_in)
445 mul1 = out_freq / input;
446 if (mul1 > (clk->pll_mul_mask + 1))
451 diff1 = out_freq - input * mul1;
462 if (diff > (out_freq >> PMC_PLL_SHIFT_TOL))
465 if (clk->set_outb != NULL)
466 ret |= clk->set_outb(out_freq);
469 ((mul - 1) << clk->pll_mul_shift) |
470 (div << clk->pll_div_shift));
475 #if !defined(AT91C_MAIN_CLOCK)
476 static const unsigned int at91_main_clock_tbl[] = {
477 3000000, 3276800, 3686400, 3840000, 4000000,
478 4433619, 4915200, 5000000, 5242880, 6000000,
479 6144000, 6400000, 6553600, 7159090, 7372800,
480 7864320, 8000000, 9830400, 10000000, 11059200,
481 12000000, 12288000, 13560000, 14318180, 14745600,
482 16000000, 17344700, 18432000, 20000000
484 #define MAIN_CLOCK_TBL_LEN nitems(at91_main_clock_tbl)
488 at91_pmc_sense_main_clock(void)
490 #if !defined(AT91C_MAIN_CLOCK)
491 unsigned int ckgr_val;
492 unsigned int diff, matchdiff, freq;
495 ckgr_val = (RD4(NULL, CKGR_MCFR) & CKGR_MCFR_MAINF_MASK) << 11;
498 * Clocks up to 50MHz can be connected to some models. If
499 * the frequency is >= 21MHz, assume that the slow clock can
500 * measure it correctly, and that any error can be adequately
501 * compensated for by roudning to the nearest 500Hz. Users
502 * with fast, or odd-ball clocks will need to set
503 * AT91C_MAIN_CLOCK in the kernel config file.
505 if (ckgr_val >= 21000000)
506 return (rounddown(ckgr_val + 250, 500));
509 * Try to find the standard frequency that match best.
511 freq = at91_main_clock_tbl[0];
512 matchdiff = abs(ckgr_val - at91_main_clock_tbl[0]);
513 for (i = 1; i < MAIN_CLOCK_TBL_LEN; i++) {
514 diff = abs(ckgr_val - at91_main_clock_tbl[i]);
515 if (diff < matchdiff) {
516 freq = at91_main_clock_tbl[i];
522 return (AT91C_MAIN_CLOCK);
527 at91_pmc_init_clock(void)
529 struct at91_pmc_softc *sc = NULL;
530 unsigned int main_clock;
534 soc_info.soc_data->soc_clock_init();
536 main_clock = at91_pmc_sense_main_clock();
538 if (at91_is_sam9() || at91_is_sam9xe()) {
539 uhpck.pmc_mask = PMC_SCER_UHP_SAM9;
540 udpck.pmc_mask = PMC_SCER_UDP_SAM9;
543 /* There is no pllb on AT91SAM9G45 */
544 if (at91_cpu_is(AT91_T_SAM9G45)) {
545 uhpck.parent = &upll;
546 uhpck.pmc_mask = PMC_SCER_UHP_SAM9;
549 mckr = RD4(sc, PMC_MCKR);
550 main_ck.hz = main_clock;
553 * Note: this means outa calc code for plla never used since
554 * we never change it. If we did, we'd also have to mind
555 * ICPLLA to get the charge pump current right.
557 at91_pmc_pll_rate(&plla, RD4(sc, CKGR_PLLAR));
559 if (at91_cpu_is(AT91_T_SAM9G45) && (mckr & PMC_MCKR_PLLADIV2))
563 * Initialize the usb clock. This sets up pllb, but disables the
564 * actual clock. XXX except for the if 0 :(
566 if (!at91_cpu_is(AT91_T_SAM9G45)) {
567 pllb_init = at91_pmc_pll_calc(&pllb, 48000000 * 2) | 0x10000000;
568 at91_pmc_pll_rate(&pllb, pllb_init);
570 /* Turn off USB clocks */
571 at91_pmc_set_periph_mode(&ohci_clk, 0);
572 at91_pmc_set_periph_mode(&udc_clk, 0);
576 if (at91_is_rm92()) {
577 WR4(sc, PMC_SCDR, PMC_SCER_UHP | PMC_SCER_UDP);
578 WR4(sc, PMC_SCER, PMC_SCER_MCKUDP);
580 WR4(sc, PMC_SCDR, PMC_SCER_UHP_SAM9 | PMC_SCER_UDP_SAM9);
583 * MCK and PCU derive from one of the primary clocks. Initialize
586 mck.parent = clock_list[mckr & 0x3];
587 mck.parent->refcnt++;
589 cpu.hz = mck.hz = mck.parent->hz /
590 (1 << ((mckr & PMC_MCKR_PRES_MASK) >> 2));
592 mdiv = (mckr & PMC_MCKR_MDIV_MASK) >> 8;
593 if (at91_is_sam9() || at91_is_sam9xe()) {
595 * On AT91SAM9G45 when mdiv == 3 we need to divide
596 * MCK by 3 but not, for example, on 9g20.
598 if (!at91_cpu_is(AT91_T_SAM9G45) || mdiv <= 2)
603 mck.hz /= (1 + mdiv);
605 /* Only found on SAM9G20 */
606 if (at91_cpu_is(AT91_T_SAM9G20))
607 cpu.hz /= (mckr & PMC_MCKR_PDIV) ? 2 : 1;
609 at91_master_clock = mck.hz;
611 /* These clocks refrenced by "special" names */
612 at91_pmc_clock_alias("ohci0", "ohci_clk");
613 at91_pmc_clock_alias("udp0", "udp_clk");
615 /* Turn off "Progamable" clocks */
616 WR4(sc, PMC_SCDR, PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2 |
619 /* XXX kludge, turn on all peripherals */
620 WR4(sc, PMC_PCER, 0xffffffff);
622 /* Disable all interrupts for PMC */
623 WR4(sc, PMC_IDR, 0xffffffff);
627 at91_pmc_deactivate(device_t dev)
629 struct at91_pmc_softc *sc;
631 sc = device_get_softc(dev);
632 bus_generic_detach(sc->dev);
634 bus_release_resource(dev, SYS_RES_IOPORT,
635 rman_get_rid(sc->mem_res), sc->mem_res);
640 at91_pmc_activate(device_t dev)
642 struct at91_pmc_softc *sc;
645 sc = device_get_softc(dev);
647 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
649 if (sc->mem_res == NULL)
653 at91_pmc_deactivate(dev);
658 at91_pmc_probe(device_t dev)
661 if (!ofw_bus_is_compatible(dev, "atmel,at91rm9200-pmc") &&
662 !ofw_bus_is_compatible(dev, "atmel,at91sam9260-pmc") &&
663 !ofw_bus_is_compatible(dev, "atmel,at91sam9g45-pmc") &&
664 !ofw_bus_is_compatible(dev, "atmel,at91sam9x5-pmc"))
667 device_set_desc(dev, "PMC");
672 at91_pmc_attach(device_t dev)
676 pmc_softc = device_get_softc(dev);
677 pmc_softc->dev = dev;
678 if ((err = at91_pmc_activate(dev)) != 0)
682 * Configure main clock frequency.
684 at91_pmc_init_clock();
687 * Display info about clocks previously computed
690 "Primary: %d Hz PLLA: %d MHz CPU: %d MHz MCK: %d MHz\n",
693 cpu.hz / 1000000, mck.hz / 1000000);
698 static device_method_t at91_pmc_methods[] = {
699 DEVMETHOD(device_probe, at91_pmc_probe),
700 DEVMETHOD(device_attach, at91_pmc_attach),
704 static driver_t at91_pmc_driver = {
707 sizeof(struct at91_pmc_softc),
709 static devclass_t at91_pmc_devclass;
712 EARLY_DRIVER_MODULE(at91_pmc, simplebus, at91_pmc_driver, at91_pmc_devclass,
713 NULL, NULL, BUS_PASS_CPU);
715 EARLY_DRIVER_MODULE(at91_pmc, atmelarm, at91_pmc_driver, at91_pmc_devclass,
716 NULL, NULL, BUS_PASS_CPU);