2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
5 * Copyright (c) 2010 Greg Ansley. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include "opt_platform.h"
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
41 #include <sys/resource.h>
43 #include <sys/timetc.h>
45 #include <machine/bus.h>
46 #include <machine/resource.h>
47 #include <machine/intr.h>
48 #include <arm/at91/at91reg.h>
49 #include <arm/at91/at91var.h>
51 #include <arm/at91/at91_pmcreg.h>
52 #include <arm/at91/at91_pmcvar.h>
55 #include <dev/ofw/ofw_bus.h>
56 #include <dev/ofw/ofw_bus_subr.h>
59 static struct at91_pmc_softc {
60 bus_space_tag_t sc_st;
61 bus_space_handle_t sc_sh;
62 struct resource *mem_res; /* Memory resource */
66 static uint32_t pllb_init;
68 MALLOC_DECLARE(M_PMC_CLK);
69 MALLOC_DEFINE(M_PMC_CLK, "at91_pmc_clocks", "AT91 PMC Clock descriptors");
71 #define AT91_PMC_BASE 0xffffc00
73 static void at91_pmc_set_pllb_mode(struct at91_pmc_clock *, int);
74 static void at91_pmc_set_upll_mode(struct at91_pmc_clock *, int);
75 static void at91_pmc_set_sys_mode(struct at91_pmc_clock *, int);
76 static void at91_pmc_set_periph_mode(struct at91_pmc_clock *, int);
77 static void at91_pmc_clock_alias(const char *name, const char *alias);
79 static struct at91_pmc_clock slck = {
80 .name = "slck", /* 32,768 Hz slow clock */
88 * NOTE: Clocks for "ordinary peripheral" devices e.g. spi0, udp0, uhp0 etc.
89 * are now created automatically. Only "system" clocks need be defined here.
91 static struct at91_pmc_clock main_ck = {
92 .name = "main", /* Main clock */
96 .pmc_mask = PMC_IER_MOSCS,
99 static struct at91_pmc_clock plla = {
100 .name = "plla", /* PLLA Clock, used for CPU clocking */
106 .pmc_mask = PMC_IER_LOCKA,
109 static struct at91_pmc_clock pllb = {
110 .name = "pllb", /* PLLB Clock, used for USB functions */
116 .pmc_mask = PMC_IER_LOCKB,
117 .set_mode = &at91_pmc_set_pllb_mode,
120 /* Used by USB on at91sam9g45 */
121 static struct at91_pmc_clock upll = {
122 .name = "upll", /* UTMI PLL, used for USB functions on 9G45 family */
128 .pmc_mask = (1 << 6),
129 .set_mode = &at91_pmc_set_upll_mode,
132 static struct at91_pmc_clock udpck = {
135 .pmc_mask = PMC_SCER_UDP,
136 .set_mode = at91_pmc_set_sys_mode
139 static struct at91_pmc_clock uhpck = {
142 .pmc_mask = PMC_SCER_UHP,
143 .set_mode = at91_pmc_set_sys_mode
146 static struct at91_pmc_clock mck = {
147 .name = "mck", /* Master (Peripheral) Clock */
148 .pmc_mask = PMC_IER_MCKRDY,
152 static struct at91_pmc_clock cpu = {
153 .name = "cpu", /* CPU Clock */
155 .pmc_mask = PMC_SCER_PCK,
159 /* "+32" or the automatic peripheral clocks */
160 static struct at91_pmc_clock *clock_list[16+32] = {
172 static inline uint32_t
173 RD4(struct at91_pmc_softc *sc, bus_size_t off)
177 uint32_t *p = (uint32_t *)(AT91_BASE + AT91_PMC_BASE + off);
181 return (bus_read_4(sc->mem_res, off));
185 WR4(struct at91_pmc_softc *sc, bus_size_t off, uint32_t val)
189 uint32_t *p = (uint32_t *)(AT91_BASE + AT91_PMC_BASE + off);
193 bus_write_4(sc->mem_res, off, val);
197 * The following is unused currently since we don't ever set the PLLA
198 * frequency of the device. If we did, we'd have to also pay attention
199 * to the ICPLLA bit in the PMC_PLLICPR register for frequencies lower
200 * than ~600MHz, which the PMC code doesn't do right now.
203 at91_pmc_800mhz_plla_outb(int freq)
208 * Set OUTA, per the data sheet. See Table 46-16 titled
209 * PLLA Frequency Regarding ICPLLA and OUTA in the SAM9X25 doc,
210 * Table 46-17 in the SAM9G20 doc, or Table 46-16 in the SAM9G45 doc.
211 * Note: the frequencies overlap by 5MHz, so we add 3 here to
212 * center shoot the transition.
215 freq /= 1000000; /* MHz */
218 freq += 3; /* Allow for overlap. */
219 outa = 3 - ((freq / 50) & 3); /* 750 / 50 = 7, see table */
220 return (1 << 29)| (outa << 14);
224 at91_pmc_800mhz_pllb_outb(int freq)
231 at91_pmc_set_pllb_mode(struct at91_pmc_clock *clk, int on)
233 struct at91_pmc_softc *sc = pmc_softc;
236 value = on ? pllb_init : 0;
239 * Only write to the register if the value is changing. Besides being
240 * good common sense, this works around RM9200 Errata #26 (CKGR_PLL[AB]R
241 * must not be written with the same value currently in the register).
243 if (RD4(sc, CKGR_PLLBR) != value) {
244 WR4(sc, CKGR_PLLBR, value);
245 while (on && (RD4(sc, PMC_SR) & PMC_IER_LOCKB) != PMC_IER_LOCKB)
251 at91_pmc_set_upll_mode(struct at91_pmc_clock *clk, int on)
253 struct at91_pmc_softc *sc = pmc_softc;
258 value = CKGR_UCKR_UPLLEN | CKGR_UCKR_BIASEN;
262 WR4(sc, CKGR_UCKR, RD4(sc, CKGR_UCKR) | value);
263 while ((RD4(sc, PMC_SR) & PMC_IER_LOCKU) != on)
266 WR4(sc, PMC_USB, PMC_USB_USBDIV(9) | PMC_USB_USBS);
267 WR4(sc, PMC_SCER, PMC_SCER_UHP_SAM9);
271 at91_pmc_set_sys_mode(struct at91_pmc_clock *clk, int on)
273 struct at91_pmc_softc *sc = pmc_softc;
275 WR4(sc, on ? PMC_SCER : PMC_SCDR, clk->pmc_mask);
277 while ((RD4(sc, PMC_SCSR) & clk->pmc_mask) != clk->pmc_mask)
280 while ((RD4(sc, PMC_SCSR) & clk->pmc_mask) == clk->pmc_mask)
285 at91_pmc_set_periph_mode(struct at91_pmc_clock *clk, int on)
287 struct at91_pmc_softc *sc = pmc_softc;
289 WR4(sc, on ? PMC_PCER : PMC_PCDR, clk->pmc_mask);
291 while ((RD4(sc, PMC_PCSR) & clk->pmc_mask) != clk->pmc_mask)
294 while ((RD4(sc, PMC_PCSR) & clk->pmc_mask) == clk->pmc_mask)
298 struct at91_pmc_clock *
299 at91_pmc_clock_add(const char *name, uint32_t irq,
300 struct at91_pmc_clock *parent)
302 struct at91_pmc_clock *clk;
305 clk = malloc(sizeof(*clk), M_PMC_CLK, M_NOWAIT | M_ZERO);
309 buflen = strlen(name) + 1;
310 clk->name = malloc(buflen, M_PMC_CLK, M_NOWAIT);
311 if (clk->name == NULL)
314 strlcpy(clk->name, name, buflen);
315 clk->pmc_mask = 1 << irq;
316 clk->set_mode = &at91_pmc_set_periph_mode;
320 clk->parent = parent;
322 for (i = 0; i < nitems(clock_list); i++) {
323 if (clock_list[i] == NULL) {
330 if (clk->name != NULL)
331 free(clk->name, M_PMC_CLK);
332 free(clk, M_PMC_CLK);
335 panic("could not allocate pmc clock '%s'", name);
340 at91_pmc_clock_alias(const char *name, const char *alias)
342 struct at91_pmc_clock *clk, *alias_clk;
344 clk = at91_pmc_clock_ref(name);
346 alias_clk = at91_pmc_clock_add(alias, 0, clk->parent);
348 if (clk && alias_clk) {
349 alias_clk->hz = clk->hz;
350 alias_clk->pmc_mask = clk->pmc_mask;
351 alias_clk->set_mode = clk->set_mode;
355 struct at91_pmc_clock *
356 at91_pmc_clock_ref(const char *name)
360 for (i = 0; i < nitems(clock_list); i++) {
361 if (clock_list[i] == NULL)
363 if (strcmp(name, clock_list[i]->name) == 0)
364 return (clock_list[i]);
371 at91_pmc_clock_deref(struct at91_pmc_clock *clk)
378 at91_pmc_clock_enable(struct at91_pmc_clock *clk)
383 /* XXX LOCKING? XXX */
385 at91_pmc_clock_enable(clk->parent);
386 if (clk->refcnt++ == 0 && clk->set_mode)
387 clk->set_mode(clk, 1);
391 at91_pmc_clock_disable(struct at91_pmc_clock *clk)
396 /* XXX LOCKING? XXX */
397 if (--clk->refcnt == 0 && clk->set_mode)
398 clk->set_mode(clk, 0);
400 at91_pmc_clock_disable(clk->parent);
404 at91_pmc_pll_rate(struct at91_pmc_clock *clk, uint32_t reg)
406 uint32_t mul, div, freq;
408 freq = clk->parent->hz;
409 div = (reg >> clk->pll_div_shift) & clk->pll_div_mask;
410 mul = (reg >> clk->pll_mul_shift) & clk->pll_mul_mask;
413 printf("pll = (%d / %d) * %d = %d\n",
414 freq, div, mul + 1, (freq/div) * (mul+1));
417 if (div != 0 && mul != 0) {
428 at91_pmc_pll_calc(struct at91_pmc_clock *clk, uint32_t out_freq)
430 uint32_t i, div = 0, mul = 0, diff = 1 << 30;
432 unsigned ret = 0x3e00;
434 if (out_freq > clk->pll_max_out)
437 for (i = 1; i < 256; i++) {
439 uint32_t input, mul1;
441 input = clk->parent->hz / i;
442 if (input < clk->pll_min_in)
444 if (input > clk->pll_max_in)
447 mul1 = out_freq / input;
448 if (mul1 > (clk->pll_mul_mask + 1))
453 diff1 = out_freq - input * mul1;
464 if (diff > (out_freq >> PMC_PLL_SHIFT_TOL))
467 if (clk->set_outb != NULL)
468 ret |= clk->set_outb(out_freq);
471 ((mul - 1) << clk->pll_mul_shift) |
472 (div << clk->pll_div_shift));
477 #if !defined(AT91C_MAIN_CLOCK)
478 static const unsigned int at91_main_clock_tbl[] = {
479 3000000, 3276800, 3686400, 3840000, 4000000,
480 4433619, 4915200, 5000000, 5242880, 6000000,
481 6144000, 6400000, 6553600, 7159090, 7372800,
482 7864320, 8000000, 9830400, 10000000, 11059200,
483 12000000, 12288000, 13560000, 14318180, 14745600,
484 16000000, 17344700, 18432000, 20000000
486 #define MAIN_CLOCK_TBL_LEN nitems(at91_main_clock_tbl)
490 at91_pmc_sense_main_clock(void)
492 #if !defined(AT91C_MAIN_CLOCK)
493 unsigned int ckgr_val;
494 unsigned int diff, matchdiff, freq;
497 ckgr_val = (RD4(NULL, CKGR_MCFR) & CKGR_MCFR_MAINF_MASK) << 11;
500 * Clocks up to 50MHz can be connected to some models. If
501 * the frequency is >= 21MHz, assume that the slow clock can
502 * measure it correctly, and that any error can be adequately
503 * compensated for by roudning to the nearest 500Hz. Users
504 * with fast, or odd-ball clocks will need to set
505 * AT91C_MAIN_CLOCK in the kernel config file.
507 if (ckgr_val >= 21000000)
508 return (rounddown(ckgr_val + 250, 500));
511 * Try to find the standard frequency that match best.
513 freq = at91_main_clock_tbl[0];
514 matchdiff = abs(ckgr_val - at91_main_clock_tbl[0]);
515 for (i = 1; i < MAIN_CLOCK_TBL_LEN; i++) {
516 diff = abs(ckgr_val - at91_main_clock_tbl[i]);
517 if (diff < matchdiff) {
518 freq = at91_main_clock_tbl[i];
524 return (AT91C_MAIN_CLOCK);
529 at91_pmc_init_clock(void)
531 struct at91_pmc_softc *sc = NULL;
532 unsigned int main_clock;
536 soc_info.soc_data->soc_clock_init();
538 main_clock = at91_pmc_sense_main_clock();
540 if (at91_is_sam9() || at91_is_sam9xe()) {
541 uhpck.pmc_mask = PMC_SCER_UHP_SAM9;
542 udpck.pmc_mask = PMC_SCER_UDP_SAM9;
545 /* There is no pllb on AT91SAM9G45 */
546 if (at91_cpu_is(AT91_T_SAM9G45)) {
547 uhpck.parent = &upll;
548 uhpck.pmc_mask = PMC_SCER_UHP_SAM9;
551 mckr = RD4(sc, PMC_MCKR);
552 main_ck.hz = main_clock;
555 * Note: this means outa calc code for plla never used since
556 * we never change it. If we did, we'd also have to mind
557 * ICPLLA to get the charge pump current right.
559 at91_pmc_pll_rate(&plla, RD4(sc, CKGR_PLLAR));
561 if (at91_cpu_is(AT91_T_SAM9G45) && (mckr & PMC_MCKR_PLLADIV2))
565 * Initialize the usb clock. This sets up pllb, but disables the
566 * actual clock. XXX except for the if 0 :(
568 if (!at91_cpu_is(AT91_T_SAM9G45)) {
569 pllb_init = at91_pmc_pll_calc(&pllb, 48000000 * 2) | 0x10000000;
570 at91_pmc_pll_rate(&pllb, pllb_init);
572 /* Turn off USB clocks */
573 at91_pmc_set_periph_mode(&ohci_clk, 0);
574 at91_pmc_set_periph_mode(&udc_clk, 0);
578 if (at91_is_rm92()) {
579 WR4(sc, PMC_SCDR, PMC_SCER_UHP | PMC_SCER_UDP);
580 WR4(sc, PMC_SCER, PMC_SCER_MCKUDP);
582 WR4(sc, PMC_SCDR, PMC_SCER_UHP_SAM9 | PMC_SCER_UDP_SAM9);
585 * MCK and PCU derive from one of the primary clocks. Initialize
588 mck.parent = clock_list[mckr & 0x3];
589 mck.parent->refcnt++;
591 cpu.hz = mck.hz = mck.parent->hz /
592 (1 << ((mckr & PMC_MCKR_PRES_MASK) >> 2));
594 mdiv = (mckr & PMC_MCKR_MDIV_MASK) >> 8;
595 if (at91_is_sam9() || at91_is_sam9xe()) {
597 * On AT91SAM9G45 when mdiv == 3 we need to divide
598 * MCK by 3 but not, for example, on 9g20.
600 if (!at91_cpu_is(AT91_T_SAM9G45) || mdiv <= 2)
605 mck.hz /= (1 + mdiv);
607 /* Only found on SAM9G20 */
608 if (at91_cpu_is(AT91_T_SAM9G20))
609 cpu.hz /= (mckr & PMC_MCKR_PDIV) ? 2 : 1;
611 at91_master_clock = mck.hz;
613 /* These clocks refrenced by "special" names */
614 at91_pmc_clock_alias("ohci0", "ohci_clk");
615 at91_pmc_clock_alias("udp0", "udp_clk");
617 /* Turn off "Progamable" clocks */
618 WR4(sc, PMC_SCDR, PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2 |
621 /* XXX kludge, turn on all peripherals */
622 WR4(sc, PMC_PCER, 0xffffffff);
624 /* Disable all interrupts for PMC */
625 WR4(sc, PMC_IDR, 0xffffffff);
629 at91_pmc_deactivate(device_t dev)
631 struct at91_pmc_softc *sc;
633 sc = device_get_softc(dev);
634 bus_generic_detach(sc->dev);
636 bus_release_resource(dev, SYS_RES_IOPORT,
637 rman_get_rid(sc->mem_res), sc->mem_res);
642 at91_pmc_activate(device_t dev)
644 struct at91_pmc_softc *sc;
647 sc = device_get_softc(dev);
649 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
651 if (sc->mem_res == NULL)
655 at91_pmc_deactivate(dev);
660 at91_pmc_probe(device_t dev)
663 if (!ofw_bus_is_compatible(dev, "atmel,at91rm9200-pmc") &&
664 !ofw_bus_is_compatible(dev, "atmel,at91sam9260-pmc") &&
665 !ofw_bus_is_compatible(dev, "atmel,at91sam9g45-pmc") &&
666 !ofw_bus_is_compatible(dev, "atmel,at91sam9x5-pmc"))
669 device_set_desc(dev, "PMC");
674 at91_pmc_attach(device_t dev)
678 pmc_softc = device_get_softc(dev);
679 pmc_softc->dev = dev;
680 if ((err = at91_pmc_activate(dev)) != 0)
684 * Configure main clock frequency.
686 at91_pmc_init_clock();
689 * Display info about clocks previously computed
692 "Primary: %d Hz PLLA: %d MHz CPU: %d MHz MCK: %d MHz\n",
695 cpu.hz / 1000000, mck.hz / 1000000);
700 static device_method_t at91_pmc_methods[] = {
701 DEVMETHOD(device_probe, at91_pmc_probe),
702 DEVMETHOD(device_attach, at91_pmc_attach),
706 static driver_t at91_pmc_driver = {
709 sizeof(struct at91_pmc_softc),
711 static devclass_t at91_pmc_devclass;
714 EARLY_DRIVER_MODULE(at91_pmc, simplebus, at91_pmc_driver, at91_pmc_devclass,
715 NULL, NULL, BUS_PASS_CPU);
717 EARLY_DRIVER_MODULE(at91_pmc, atmelarm, at91_pmc_driver, at91_pmc_devclass,
718 NULL, NULL, BUS_PASS_CPU);