2 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
3 * Copyright (c) 2010 Greg Ansley. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include "opt_platform.h"
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
39 #include <sys/resource.h>
41 #include <sys/timetc.h>
43 #include <machine/bus.h>
44 #include <machine/resource.h>
45 #include <machine/intr.h>
46 #include <arm/at91/at91reg.h>
47 #include <arm/at91/at91var.h>
49 #include <arm/at91/at91_pmcreg.h>
50 #include <arm/at91/at91_pmcvar.h>
53 #include <dev/fdt/fdt_common.h>
54 #include <dev/ofw/ofw_bus.h>
55 #include <dev/ofw/ofw_bus_subr.h>
58 static struct at91_pmc_softc {
59 bus_space_tag_t sc_st;
60 bus_space_handle_t sc_sh;
61 struct resource *mem_res; /* Memory resource */
65 static uint32_t pllb_init;
67 MALLOC_DECLARE(M_PMC);
68 MALLOC_DEFINE(M_PMC, "at91_pmc_clocks", "AT91 PMC Clock descriptors");
70 #define AT91_PMC_BASE 0xffffc00
72 static void at91_pmc_set_pllb_mode(struct at91_pmc_clock *, int);
73 static void at91_pmc_set_upll_mode(struct at91_pmc_clock *, int);
74 static void at91_pmc_set_sys_mode(struct at91_pmc_clock *, int);
75 static void at91_pmc_set_periph_mode(struct at91_pmc_clock *, int);
76 static void at91_pmc_clock_alias(const char *name, const char *alias);
78 static struct at91_pmc_clock slck = {
79 .name = "slck", /* 32,768 Hz slow clock */
87 * NOTE: Clocks for "ordinary peripheral" devices e.g. spi0, udp0, uhp0 etc.
88 * are now created automatically. Only "system" clocks need be defined here.
90 static struct at91_pmc_clock main_ck = {
91 .name = "main", /* Main clock */
95 .pmc_mask = PMC_IER_MOSCS,
98 static struct at91_pmc_clock plla = {
99 .name = "plla", /* PLLA Clock, used for CPU clocking */
105 .pmc_mask = PMC_IER_LOCKA,
108 static struct at91_pmc_clock pllb = {
109 .name = "pllb", /* PLLB Clock, used for USB functions */
115 .pmc_mask = PMC_IER_LOCKB,
116 .set_mode = &at91_pmc_set_pllb_mode,
119 /* Used by USB on at91sam9g45 */
120 static struct at91_pmc_clock upll = {
121 .name = "upll", /* UTMI PLL, used for USB functions on 9G45 family */
127 .pmc_mask = (1 << 6),
128 .set_mode = &at91_pmc_set_upll_mode,
131 static struct at91_pmc_clock udpck = {
134 .pmc_mask = PMC_SCER_UDP,
135 .set_mode = at91_pmc_set_sys_mode
138 static struct at91_pmc_clock uhpck = {
141 .pmc_mask = PMC_SCER_UHP,
142 .set_mode = at91_pmc_set_sys_mode
145 static struct at91_pmc_clock mck = {
146 .name = "mck", /* Master (Peripheral) Clock */
147 .pmc_mask = PMC_IER_MCKRDY,
151 static struct at91_pmc_clock cpu = {
152 .name = "cpu", /* CPU Clock */
154 .pmc_mask = PMC_SCER_PCK,
158 /* "+32" or the automatic peripheral clocks */
159 static struct at91_pmc_clock *clock_list[16+32] = {
171 static inline uint32_t
172 RD4(struct at91_pmc_softc *sc, bus_size_t off)
176 uint32_t *p = (uint32_t *)(AT91_BASE + AT91_PMC_BASE + off);
180 return (bus_read_4(sc->mem_res, off));
184 WR4(struct at91_pmc_softc *sc, bus_size_t off, uint32_t val)
188 uint32_t *p = (uint32_t *)(AT91_BASE + AT91_PMC_BASE + off);
192 bus_write_4(sc->mem_res, off, val);
196 * The following is unused currently since we don't ever set the PLLA
197 * frequency of the device. If we did, we'd have to also pay attention
198 * to the ICPLLA bit in the PMC_PLLICPR register for frequencies lower
199 * than ~600MHz, which the PMC code doesn't do right now.
202 at91_pmc_800mhz_plla_outb(int freq)
207 * Set OUTA, per the data sheet. See Table 46-16 titled
208 * PLLA Frequency Regarding ICPLLA and OUTA in the SAM9X25 doc,
209 * Table 46-17 in the SAM9G20 doc, or Table 46-16 in the SAM9G45 doc.
210 * Note: the frequencies overlap by 5MHz, so we add 3 here to
211 * center shoot the transition.
214 freq /= 1000000; /* MHz */
217 freq += 3; /* Allow for overlap. */
218 outa = 3 - ((freq / 50) & 3); /* 750 / 50 = 7, see table */
219 return (1 << 29)| (outa << 14);
223 at91_pmc_800mhz_pllb_outb(int freq)
230 at91_pmc_set_pllb_mode(struct at91_pmc_clock *clk, int on)
232 struct at91_pmc_softc *sc = pmc_softc;
235 value = on ? pllb_init : 0;
238 * Only write to the register if the value is changing. Besides being
239 * good common sense, this works around RM9200 Errata #26 (CKGR_PLL[AB]R
240 * must not be written with the same value currently in the register).
242 if (RD4(sc, CKGR_PLLBR) != value) {
243 WR4(sc, CKGR_PLLBR, value);
244 while (on && (RD4(sc, PMC_SR) & PMC_IER_LOCKB) != PMC_IER_LOCKB)
250 at91_pmc_set_upll_mode(struct at91_pmc_clock *clk, int on)
252 struct at91_pmc_softc *sc = pmc_softc;
257 value = CKGR_UCKR_UPLLEN | CKGR_UCKR_BIASEN;
261 WR4(sc, CKGR_UCKR, RD4(sc, CKGR_UCKR) | value);
262 while ((RD4(sc, PMC_SR) & PMC_IER_LOCKU) != on)
265 WR4(sc, PMC_USB, PMC_USB_USBDIV(9) | PMC_USB_USBS);
266 WR4(sc, PMC_SCER, PMC_SCER_UHP_SAM9);
270 at91_pmc_set_sys_mode(struct at91_pmc_clock *clk, int on)
272 struct at91_pmc_softc *sc = pmc_softc;
274 WR4(sc, on ? PMC_SCER : PMC_SCDR, clk->pmc_mask);
276 while ((RD4(sc, PMC_SCSR) & clk->pmc_mask) != clk->pmc_mask)
279 while ((RD4(sc, PMC_SCSR) & clk->pmc_mask) == clk->pmc_mask)
284 at91_pmc_set_periph_mode(struct at91_pmc_clock *clk, int on)
286 struct at91_pmc_softc *sc = pmc_softc;
288 WR4(sc, on ? PMC_PCER : PMC_PCDR, clk->pmc_mask);
290 while ((RD4(sc, PMC_PCSR) & clk->pmc_mask) != clk->pmc_mask)
293 while ((RD4(sc, PMC_PCSR) & clk->pmc_mask) == clk->pmc_mask)
297 struct at91_pmc_clock *
298 at91_pmc_clock_add(const char *name, uint32_t irq,
299 struct at91_pmc_clock *parent)
301 struct at91_pmc_clock *clk;
304 clk = malloc(sizeof(*clk), M_PMC, M_NOWAIT | M_ZERO);
308 buflen = strlen(name) + 1;
309 clk->name = malloc(buflen, M_PMC, M_NOWAIT);
310 if (clk->name == NULL)
313 strlcpy(clk->name, name, buflen);
314 clk->pmc_mask = 1 << irq;
315 clk->set_mode = &at91_pmc_set_periph_mode;
319 clk->parent = parent;
321 for (i = 0; i < nitems(clock_list); i++) {
322 if (clock_list[i] == NULL) {
329 if (clk->name != NULL)
330 free(clk->name, M_PMC);
334 panic("could not allocate pmc clock '%s'", name);
339 at91_pmc_clock_alias(const char *name, const char *alias)
341 struct at91_pmc_clock *clk, *alias_clk;
343 clk = at91_pmc_clock_ref(name);
345 alias_clk = at91_pmc_clock_add(alias, 0, clk->parent);
347 if (clk && alias_clk) {
348 alias_clk->hz = clk->hz;
349 alias_clk->pmc_mask = clk->pmc_mask;
350 alias_clk->set_mode = clk->set_mode;
354 struct at91_pmc_clock *
355 at91_pmc_clock_ref(const char *name)
359 for (i = 0; i < nitems(clock_list); i++) {
360 if (clock_list[i] == NULL)
362 if (strcmp(name, clock_list[i]->name) == 0)
363 return (clock_list[i]);
370 at91_pmc_clock_deref(struct at91_pmc_clock *clk)
377 at91_pmc_clock_enable(struct at91_pmc_clock *clk)
382 /* XXX LOCKING? XXX */
384 at91_pmc_clock_enable(clk->parent);
385 if (clk->refcnt++ == 0 && clk->set_mode)
386 clk->set_mode(clk, 1);
390 at91_pmc_clock_disable(struct at91_pmc_clock *clk)
395 /* XXX LOCKING? XXX */
396 if (--clk->refcnt == 0 && clk->set_mode)
397 clk->set_mode(clk, 0);
399 at91_pmc_clock_disable(clk->parent);
403 at91_pmc_pll_rate(struct at91_pmc_clock *clk, uint32_t reg)
405 uint32_t mul, div, freq;
407 freq = clk->parent->hz;
408 div = (reg >> clk->pll_div_shift) & clk->pll_div_mask;
409 mul = (reg >> clk->pll_mul_shift) & clk->pll_mul_mask;
412 printf("pll = (%d / %d) * %d = %d\n",
413 freq, div, mul + 1, (freq/div) * (mul+1));
416 if (div != 0 && mul != 0) {
427 at91_pmc_pll_calc(struct at91_pmc_clock *clk, uint32_t out_freq)
429 uint32_t i, div = 0, mul = 0, diff = 1 << 30;
431 unsigned ret = 0x3e00;
433 if (out_freq > clk->pll_max_out)
436 for (i = 1; i < 256; i++) {
438 uint32_t input, mul1;
440 input = clk->parent->hz / i;
441 if (input < clk->pll_min_in)
443 if (input > clk->pll_max_in)
446 mul1 = out_freq / input;
447 if (mul1 > (clk->pll_mul_mask + 1))
452 diff1 = out_freq - input * mul1;
463 if (diff > (out_freq >> PMC_PLL_SHIFT_TOL))
466 if (clk->set_outb != NULL)
467 ret |= clk->set_outb(out_freq);
470 ((mul - 1) << clk->pll_mul_shift) |
471 (div << clk->pll_div_shift));
476 #if !defined(AT91C_MAIN_CLOCK)
477 static const unsigned int at91_main_clock_tbl[] = {
478 3000000, 3276800, 3686400, 3840000, 4000000,
479 4433619, 4915200, 5000000, 5242880, 6000000,
480 6144000, 6400000, 6553600, 7159090, 7372800,
481 7864320, 8000000, 9830400, 10000000, 11059200,
482 12000000, 12288000, 13560000, 14318180, 14745600,
483 16000000, 17344700, 18432000, 20000000
485 #define MAIN_CLOCK_TBL_LEN nitems(at91_main_clock_tbl)
489 at91_pmc_sense_main_clock(void)
491 #if !defined(AT91C_MAIN_CLOCK)
492 unsigned int ckgr_val;
493 unsigned int diff, matchdiff, freq;
496 ckgr_val = (RD4(NULL, CKGR_MCFR) & CKGR_MCFR_MAINF_MASK) << 11;
499 * Clocks up to 50MHz can be connected to some models. If
500 * the frequency is >= 21MHz, assume that the slow clock can
501 * measure it correctly, and that any error can be adequately
502 * compensated for by roudning to the nearest 500Hz. Users
503 * with fast, or odd-ball clocks will need to set
504 * AT91C_MAIN_CLOCK in the kernel config file.
506 if (ckgr_val >= 21000000)
507 return (rounddown(ckgr_val + 250, 500));
510 * Try to find the standard frequency that match best.
512 freq = at91_main_clock_tbl[0];
513 matchdiff = abs(ckgr_val - at91_main_clock_tbl[0]);
514 for (i = 1; i < MAIN_CLOCK_TBL_LEN; i++) {
515 diff = abs(ckgr_val - at91_main_clock_tbl[i]);
516 if (diff < matchdiff) {
517 freq = at91_main_clock_tbl[i];
523 return (AT91C_MAIN_CLOCK);
528 at91_pmc_init_clock(void)
530 struct at91_pmc_softc *sc = NULL;
531 unsigned int main_clock;
535 soc_info.soc_data->soc_clock_init();
537 main_clock = at91_pmc_sense_main_clock();
539 if (at91_is_sam9() || at91_is_sam9xe()) {
540 uhpck.pmc_mask = PMC_SCER_UHP_SAM9;
541 udpck.pmc_mask = PMC_SCER_UDP_SAM9;
544 /* There is no pllb on AT91SAM9G45 */
545 if (at91_cpu_is(AT91_T_SAM9G45)) {
546 uhpck.parent = &upll;
547 uhpck.pmc_mask = PMC_SCER_UHP_SAM9;
550 mckr = RD4(sc, PMC_MCKR);
551 main_ck.hz = main_clock;
554 * Note: this means outa calc code for plla never used since
555 * we never change it. If we did, we'd also have to mind
556 * ICPLLA to get the charge pump current right.
558 at91_pmc_pll_rate(&plla, RD4(sc, CKGR_PLLAR));
560 if (at91_cpu_is(AT91_T_SAM9G45) && (mckr & PMC_MCKR_PLLADIV2))
564 * Initialize the usb clock. This sets up pllb, but disables the
565 * actual clock. XXX except for the if 0 :(
567 if (!at91_cpu_is(AT91_T_SAM9G45)) {
568 pllb_init = at91_pmc_pll_calc(&pllb, 48000000 * 2) | 0x10000000;
569 at91_pmc_pll_rate(&pllb, pllb_init);
571 /* Turn off USB clocks */
572 at91_pmc_set_periph_mode(&ohci_clk, 0);
573 at91_pmc_set_periph_mode(&udc_clk, 0);
577 if (at91_is_rm92()) {
578 WR4(sc, PMC_SCDR, PMC_SCER_UHP | PMC_SCER_UDP);
579 WR4(sc, PMC_SCER, PMC_SCER_MCKUDP);
581 WR4(sc, PMC_SCDR, PMC_SCER_UHP_SAM9 | PMC_SCER_UDP_SAM9);
584 * MCK and PCU derive from one of the primary clocks. Initialize
587 mck.parent = clock_list[mckr & 0x3];
588 mck.parent->refcnt++;
590 cpu.hz = mck.hz = mck.parent->hz /
591 (1 << ((mckr & PMC_MCKR_PRES_MASK) >> 2));
593 mdiv = (mckr & PMC_MCKR_MDIV_MASK) >> 8;
594 if (at91_is_sam9() || at91_is_sam9xe()) {
596 * On AT91SAM9G45 when mdiv == 3 we need to divide
597 * MCK by 3 but not, for example, on 9g20.
599 if (!at91_cpu_is(AT91_T_SAM9G45) || mdiv <= 2)
604 mck.hz /= (1 + mdiv);
606 /* Only found on SAM9G20 */
607 if (at91_cpu_is(AT91_T_SAM9G20))
608 cpu.hz /= (mckr & PMC_MCKR_PDIV) ? 2 : 1;
610 at91_master_clock = mck.hz;
612 /* These clocks refrenced by "special" names */
613 at91_pmc_clock_alias("ohci0", "ohci_clk");
614 at91_pmc_clock_alias("udp0", "udp_clk");
616 /* Turn off "Progamable" clocks */
617 WR4(sc, PMC_SCDR, PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2 |
620 /* XXX kludge, turn on all peripherals */
621 WR4(sc, PMC_PCER, 0xffffffff);
623 /* Disable all interrupts for PMC */
624 WR4(sc, PMC_IDR, 0xffffffff);
628 at91_pmc_deactivate(device_t dev)
630 struct at91_pmc_softc *sc;
632 sc = device_get_softc(dev);
633 bus_generic_detach(sc->dev);
635 bus_release_resource(dev, SYS_RES_IOPORT,
636 rman_get_rid(sc->mem_res), sc->mem_res);
641 at91_pmc_activate(device_t dev)
643 struct at91_pmc_softc *sc;
646 sc = device_get_softc(dev);
648 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
650 if (sc->mem_res == NULL)
654 at91_pmc_deactivate(dev);
659 at91_pmc_probe(device_t dev)
662 if (!ofw_bus_is_compatible(dev, "atmel,at91rm9200-pmc") &&
663 !ofw_bus_is_compatible(dev, "atmel,at91sam9260-pmc") &&
664 !ofw_bus_is_compatible(dev, "atmel,at91sam9g45-pmc") &&
665 !ofw_bus_is_compatible(dev, "atmel,at91sam9x5-pmc"))
668 device_set_desc(dev, "PMC");
673 at91_pmc_attach(device_t dev)
677 pmc_softc = device_get_softc(dev);
678 pmc_softc->dev = dev;
679 if ((err = at91_pmc_activate(dev)) != 0)
683 * Configure main clock frequency.
685 at91_pmc_init_clock();
688 * Display info about clocks previously computed
691 "Primary: %d Hz PLLA: %d MHz CPU: %d MHz MCK: %d MHz\n",
694 cpu.hz / 1000000, mck.hz / 1000000);
699 static device_method_t at91_pmc_methods[] = {
700 DEVMETHOD(device_probe, at91_pmc_probe),
701 DEVMETHOD(device_attach, at91_pmc_attach),
705 static driver_t at91_pmc_driver = {
708 sizeof(struct at91_pmc_softc),
710 static devclass_t at91_pmc_devclass;
713 EARLY_DRIVER_MODULE(at91_pmc, simplebus, at91_pmc_driver, at91_pmc_devclass,
714 NULL, NULL, BUS_PASS_CPU);
716 EARLY_DRIVER_MODULE(at91_pmc, atmelarm, at91_pmc_driver, at91_pmc_devclass,
717 NULL, NULL, BUS_PASS_CPU);