2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2014 M. Warner Losh. All rights reserved.
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7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
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11 * 2. Redistributions in binary form must reproduce the above copyright
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30 #ifndef ARM_AT91_AT91_SMC_H
31 #define ARM_AT91_AT91_SMC_H
34 #define SMC_SETUP 0x00
35 #define SMC_PULSE 0x04
36 #define SMC_CYCLE 0x08
39 #define SMC_CS_OFF(cs) (0x10 * (cs))
42 #define SMC_SETUP_NCS_RD_SETUP(x) ((x) << 24)
43 #define SMC_SETUP_NRD_SETUP(x) ((x) << 16)
44 #define SMC_SETUP_NCS_WR_SETUP(x) ((x) << 8)
45 #define SMC_SETUP_NWE_SETUP(x) (x)
48 #define SMC_PULSE_NCS_RD_PULSE(x) ((x) << 24)
49 #define SMC_PULSE_NRD_PULSE(x) ((x) << 16)
50 #define SMC_PULSE_NCS_WR_PULSE(x) ((x) << 8)
51 #define SMC_PULSE_NWE_PULSE(x) (x)
54 #define SMC_CYCLE_NRD_CYCLE(x) ((x) << 16)
55 #define SMC_CYCLE_NWE_CYCLE(x) (x)
58 #define SMC_MODE_READ (1 << 0)
59 #define SMC_MODE_WRITE (1 << 1)
60 #define SMC_MODE_EXNW_DISABLED (0 << 4)
61 #define SMC_MODE_EXNW_FROZEN_MODE (2 << 4)
62 #define SMC_MODE_EXNW_READY_MODE (3 << 4)
63 #define SMC_MODE_BAT (1 << 8)
64 #define SMC_MODE_DBW_8BIT (0 << 12)
65 #define SMC_MODE_DBW_16BIT (1 << 12)
66 #define SMC_MODE_DBW_32_BIT (2 << 12)
67 #define SMC_MODE_TDF_CYCLES(x) ((x) << 16)
68 #define SMC_MODE_TDF_MODE (1 << 20)
69 #define SMC_MODE_PMEN (1 << 24)
70 #define SMC_PS_4BYTE (0 << 28)
71 #define SMC_PS_8BYTE (1 << 28)
72 #define SMC_PS_16BYTE (2 << 28)
73 #define SMC_PS_32BYTE (3 << 28)
76 * structure to ease init. See the SMC chapter in the datasheet for
77 * the appropriate SoC you are using for details.
98 uint8_t mode; /* Combo of READ/WRITE/EXNW fields */
108 * Convenience routine to fill in SMC registers for a given chip select.
110 void at91_smc_setup(int id, int cs, const struct at91_smc_init *smc);
113 * Disable/Enable different External Bus Interfaces (EBI)
115 void at91_ebi_enable(int cs);
116 void at91_ebi_disable(int cs);
118 #endif /* ARM_AT91_AT91_SMC_H */