2 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 #include <sys/cdefs.h>
26 __FBSDID("$FreeBSD$");
28 #include <sys/param.h>
29 #include <sys/systm.h>
32 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
39 #include <machine/bus.h>
41 #include <arm/at91/at91_spireg.h>
42 #include <arm/at91/at91_pdcreg.h>
44 #include <dev/spibus/spi.h>
45 #include "spibus_if.h"
49 device_t dev; /* Myself */
50 void *intrhand; /* Interrupt handle */
51 struct resource *irq_res; /* IRQ resource */
52 struct resource *mem_res; /* Memory resource */
53 struct mtx sc_mtx; /* basically a perimeter lock */
54 bus_dma_tag_t dmatag; /* bus dma tag for mbufs */
55 bus_dmamap_t map[4]; /* Maps for the transaction */
58 static inline uint32_t
59 RD4(struct at91_spi_softc *sc, bus_size_t off)
61 return bus_read_4(sc->mem_res, off);
65 WR4(struct at91_spi_softc *sc, bus_size_t off, uint32_t val)
67 bus_write_4(sc->mem_res, off, val);
70 #define AT91_SPI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
71 #define AT91_SPI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
72 #define AT91_SPI_LOCK_INIT(_sc) \
73 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
75 #define AT91_SPI_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
76 #define AT91_SPI_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
77 #define AT91_SPI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
79 static devclass_t at91_spi_devclass;
81 /* bus entry points */
83 static int at91_spi_probe(device_t dev);
84 static int at91_spi_attach(device_t dev);
85 static int at91_spi_detach(device_t dev);
88 static int at91_spi_activate(device_t dev);
89 static void at91_spi_deactivate(device_t dev);
92 at91_spi_probe(device_t dev)
94 device_set_desc(dev, "SPI");
99 at91_spi_attach(device_t dev)
101 struct at91_spi_softc *sc = device_get_softc(dev);
105 err = at91_spi_activate(dev);
109 AT91_SPI_LOCK_INIT(sc);
112 * Allocate DMA tags and maps
114 err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
115 BUS_SPACE_MAXADDR, NULL, NULL, 2058, 1, 2048, BUS_DMA_ALLOCNOW,
116 NULL, NULL, &sc->dmatag);
119 for (i = 0; i < 4; i++) {
120 err = bus_dmamap_create(sc->dmatag, 0, &sc->map[i]);
126 WR4(sc, SPI_CR, SPI_CR_SWRST);
128 WR4(sc, SPI_MR, (0xf << 24) | SPI_MR_MSTR | SPI_MR_MODFDIS |
131 WR4(sc, SPI_CSR0, SPI_CSR_CPOL | (4 << 16) | (2 << 8));
132 WR4(sc, SPI_CR, SPI_CR_SPIEN);
134 WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS);
135 WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS);
136 WR4(sc, PDC_RNPR, 0);
137 WR4(sc, PDC_RNCR, 0);
138 WR4(sc, PDC_TNPR, 0);
139 WR4(sc, PDC_TNCR, 0);
144 WR4(sc, PDC_PTCR, PDC_PTCR_RXTEN);
145 WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN);
149 device_add_child(dev, "spibus", -1);
150 bus_generic_attach(dev);
153 at91_spi_deactivate(dev);
158 at91_spi_detach(device_t dev)
160 return (EBUSY); /* XXX */
164 at91_spi_activate(device_t dev)
166 struct at91_spi_softc *sc;
169 sc = device_get_softc(dev);
171 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
173 if (sc->mem_res == NULL)
176 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
178 if (sc->mem_res == NULL)
182 at91_spi_deactivate(dev);
187 at91_spi_deactivate(device_t dev)
189 struct at91_spi_softc *sc;
191 sc = device_get_softc(dev);
193 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
195 bus_generic_detach(sc->dev);
197 bus_release_resource(dev, SYS_RES_IOPORT,
198 rman_get_rid(sc->mem_res), sc->mem_res);
201 bus_release_resource(dev, SYS_RES_IRQ,
202 rman_get_rid(sc->irq_res), sc->irq_res);
208 at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
212 *(bus_addr_t *)arg = segs[0].ds_addr;
216 at91_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
218 struct at91_spi_softc *sc;
222 sc = device_get_softc(dev);
223 WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS);
225 if (bus_dmamap_load(sc->dmatag, sc->map[i], cmd->tx_cmd,
226 cmd->tx_cmd_sz, at91_getaddr, &addr, 0) != 0)
228 WR4(sc, PDC_TPR, addr);
229 WR4(sc, PDC_TCR, cmd->tx_cmd_sz);
230 bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREWRITE);
232 if (bus_dmamap_load(sc->dmatag, sc->map[i], cmd->tx_data,
233 cmd->tx_data_sz, at91_getaddr, &addr, 0) != 0)
235 WR4(sc, PDC_TNPR, addr);
236 WR4(sc, PDC_TNCR, cmd->tx_cmd_sz);
237 bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREWRITE);
239 if (bus_dmamap_load(sc->dmatag, sc->map[i], cmd->rx_cmd,
240 cmd->tx_cmd_sz, at91_getaddr, &addr, 0) != 0)
242 WR4(sc, PDC_RPR, addr);
243 WR4(sc, PDC_RCR, cmd->tx_cmd_sz);
244 bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREREAD);
246 if (bus_dmamap_load(sc->dmatag, sc->map[i], cmd->rx_data,
247 cmd->tx_data_sz, at91_getaddr, &addr, 0) != 0)
249 WR4(sc, PDC_RNPR, addr);
250 WR4(sc, PDC_RNCR, cmd->tx_data_sz);
251 bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREREAD);
253 WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN | PDC_PTCR_RXTEN);
255 // wait for completion
256 // XXX should be done as an ISR of some sort.
257 while (RD4(sc, SPI_SR) & SPI_SR_ENDRX)
260 // Sync the buffers after the DMA is done, and unload them.
261 bus_dmamap_sync(sc->dmatag, sc->map[0], BUS_DMASYNC_POSTWRITE);
262 bus_dmamap_sync(sc->dmatag, sc->map[1], BUS_DMASYNC_POSTWRITE);
263 bus_dmamap_sync(sc->dmatag, sc->map[2], BUS_DMASYNC_POSTREAD);
264 bus_dmamap_sync(sc->dmatag, sc->map[3], BUS_DMASYNC_POSTREAD);
265 for (i = 0; i < 4; i++)
266 bus_dmamap_unload(sc->dmatag, sc->map[i]);
270 bus_dmamap_unload(sc->dmatag, sc->map[i]);
274 static device_method_t at91_spi_methods[] = {
275 /* Device interface */
276 DEVMETHOD(device_probe, at91_spi_probe),
277 DEVMETHOD(device_attach, at91_spi_attach),
278 DEVMETHOD(device_detach, at91_spi_detach),
280 /* spibus interface */
281 DEVMETHOD(spibus_transfer, at91_spi_transfer),
285 static driver_t at91_spi_driver = {
288 sizeof(struct at91_spi_softc),
291 DRIVER_MODULE(at91_spi, atmelarm, at91_spi_driver, at91_spi_devclass, 0, 0);