2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef ARM_AT91_AT91_SSCREG_H
31 #define ARM_AT91_AT91_SSCREG_H
34 #define SSC_CR 0x00 /* Control Register */
35 #define SSC_CMR 0x04 /* Clock Mode Register */
38 #define SSC_RCMR 0x10 /* Receive Clock Mode Register */
39 #define SSC_RFMR 0x14 /* Receive Frame Mode Register */
40 #define SSC_TCMR 0x18 /* Transmit Clock Mode Register */
41 #define SSC_TFMR 0x1c /* Transmit Frame Mode register */
42 #define SSC_RHR 0x20 /* Receive Holding Register */
43 #define SSC_THR 0x24 /* Transmit Holding Register */
46 #define SSC_RSHR 0x30 /* Receive Sync Holding Register */
47 #define SSC_TSHR 0x34 /* Transmit Sync Holding Register */
50 #define SSC_SR 0x40 /* Status Register */
51 #define SSC_IER 0x44 /* Interrupt Enable Register */
52 #define SSC_IDR 0x48 /* Interrupt Disable Register */
53 #define SSC_IMR 0x4c /* Interrupt Mask Register */
54 /* And PDC registers */
57 #define SSC_CR_RXEN (1u << 0) /* RXEN: Receive Enable */
58 #define SSC_CR_RXDIS (1u << 1) /* RXDIS: Receive Disable */
59 #define SSC_CR_TXEN (1u << 8) /* TXEN: Transmit Enable */
60 #define SSC_CR_TXDIS (1u << 9) /* TXDIS: Transmit Disable */
61 #define SSC_CR_SWRST (1u << 15) /* SWRST: Software Reset */
64 #define SSC_CMR_DIV 0xfffu /* DIV: Clock Divider mask */
67 #define SSC_RCMR_PERIOD (0xffu << 24) /* PERIOD: Receive Period Divider sel*/
68 #define SSC_RCMR_STTDLY (0xffu << 16) /* STTDLY: Receive Start Delay */
69 #define SSC_RCMR_START (0xfu << 8) /* START: Receive Start Sel */
70 #define SSC_RCMR_START_CONT (0u << 8)
71 #define SSC_RCMR_START_TX_START (1u << 8)
72 #define SSC_RCMR_START_LOW_RF (2u << 8)
73 #define SSC_RCMR_START_HIGH_RF (3u << 8)
74 #define SSC_RCMR_START_FALL_EDGE_RF (4u << 8)
75 #define SSC_RCMR_START_RISE_EDGE_RF (5u << 8)
76 #define SSC_RCMR_START_LEVEL_CHANGE_RF (6u << 8)
77 #define SSC_RCMR_START_ANY_EDGE_RF (7u << 8)
78 #define SSC_RCMR_CKI (1u << 5) /* CKI: Receive Clock Inversion */
79 #define SSC_RCMR_CKO (7u << 2) /* CKO: Receive Clock Output Mode Sel*/
80 #define SSC_RCMR_CKO_NONE (0u << 2)
81 #define SSC_RCMR_CKO_CONTINUOUS (1u << 2)
82 #define SSC_RCMR_CKS (3u) /* CKS: Receive Clock Selection */
83 #define SSC_RCMR_CKS_DIVIDED (0)
84 #define SSC_RCMR_CKS_TK_CLOCK (1)
85 #define SSC_RCMR_CKS_RK (2)
88 #define SSC_RFMR_FSEDGE (1u << 24) /* FSEDGE: Frame Sync Edge Detection */
89 #define SSC_RFMR_FSOS (7u << 20) /* FSOS: Receive frame Sync Out sel */
90 #define SSC_RFMR_FSOS_NONE (0u << 20)
91 #define SSC_RFMR_FSOS_NEG_PULSE (1u << 20)
92 #define SSC_RFMR_FSOS_POS_PULSE (2u << 20)
93 #define SSC_RFMR_FSOS_LOW (3u << 20)
94 #define SSC_RFMR_FSOS_HIGH (4u << 20)
95 #define SSC_RFMR_FSOS_TOGGLE (5u << 20)
96 #define SSC_RFMR_FSLEN (0xfu << 16) /* FSLEN: Receive Frame Sync Length */
97 #define SSC_RFMR_DATNB (0xfu << 8) /* DATNB: Data Number per Frame */
98 #define SSC_RFMR_MSFBF (1u << 7) /* MSBF: Most Significant Bit First */
99 #define SSC_RFMR_LOOP (1u << 5) /* LOOP: Loop Mode */
100 #define SSC_RFMR_DATLEN (0x1fu << 0) /* DATLEN: Data Length */
103 #define SSC_TCMR_PERIOD (0xffu << 24) /* PERIOD: Receive Period Divider sel*/
104 #define SSC_TCMR_STTDLY (0xffu << 16) /* STTDLY: Receive Start Delay */
105 #define SSC_TCMR_START (0xfu << 8) /* START: Receive Start Sel */
106 #define SSC_TCMR_START_CONT (0u << 8)
107 #define SSC_TCMR_START_RX_START (1u << 8)
108 #define SSC_TCMR_START_LOW_RF (2u << 8)
109 #define SSC_TCMR_START_HIGH_RF (3u << 8)
110 #define SSC_TCMR_START_FALL_EDGE_RF (4u << 8)
111 #define SSC_TCMR_START_RISE_EDGE_RF (5u << 8)
112 #define SSC_TCMR_START_LEVEL_CHANGE_RF (6u << 8)
113 #define SSC_TCMR_START_ANY_EDGE_RF (7u << 8)
114 #define SSC_TCMR_CKI (1u << 5) /* CKI: Receive Clock Inversion */
115 #define SSC_TCMR_CKO (7u << 2) /* CKO: Receive Clock Output Mode Sel*/
116 #define SSC_TCMR_CKO_NONE (0u << 2)
117 #define SSC_TCMR_CKO_CONTINUOUS (1u << 2)
118 #define SSC_TCMR_CKS (3u) /* CKS: Receive Clock Selection */
119 #define SSC_TCMR_CKS_DIVIDED (0)
120 #define SSC_TCMR_CKS_RK_CLOCK (1)
121 #define SSC_TCMR_CKS_TK (2)
124 #define SSC_TFMR_FSEDGE (1u << 24) /* FSEDGE: Frame Sync Edge Detection */
125 #define SSC_TFMR_FSOS (7u << 20) /* FSOS: Receive frame Sync Out sel */
126 #define SSC_TFMR_FSOS_NONE (0u << 20)
127 #define SSC_TFMR_FSOS_NEG_PULSE (1u << 20)
128 #define SSC_TFMR_FSOS_POS_PULSE (2u << 20)
129 #define SSC_TFMR_FSOS_LOW (3u << 20)
130 #define SSC_TFMR_FSOS_HIGH (4u << 20)
131 #define SSC_TFMR_FSOS_TOGGLE (5u << 20)
132 #define SSC_TFMR_FSLEN (0xfu << 16) /* FSLEN: Receive Frame Sync Length */
133 #define SSC_TFMR_DATNB (0xfu << 8) /* DATNB: Data Number per Frame */
134 #define SSC_TFMR_MSFBF (1u << 7) /* MSBF: Most Significant Bit First */
135 #define SSC_TFMR_DATDEF (1u << 5) /* DATDEF: Data Default Value */
136 #define SSC_TFMR_DATLEN (0x1fu << 0) /* DATLEN: Data Length */
139 #define SSC_SR_TXRDY (1u << 0)
140 #define SSC_SR_TXEMPTY (1u << 1)
141 #define SSC_SR_ENDTX (1u << 2)
142 #define SSC_SR_TXBUFE (1u << 3)
143 #define SSC_SR_RXRDY (1u << 4)
144 #define SSC_SR_OVRUN (1u << 5)
145 #define SSC_SR_ENDRX (1u << 6)
146 #define SSC_SR_RXBUFF (1u << 7)
147 #define SSC_SR_TXSYN (1u << 10)
148 #define SSC_SR_RSSYN (1u << 11)
149 #define SSC_SR_TXEN (1u << 16)
150 #define SSC_SR_RXEN (1u << 17)
152 #endif /* ARM_AT91_AT91_SSCREG_H */