2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2005 Gallon Sylvestre. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #ifndef ARM_AT91_AT91WDTREG_H
33 #define ARM_AT91_AT91WDTREG_H
36 #define WDT_CLOCK (32768)
38 #define WDT_DIV (128) /* Clock is slow clock / 128 */
40 #define WDT_CR 0x0 /* Control Register */
41 #define WDT_MR 0x4 /* Mode Register */
42 #define WDT_SR 0x8 /* Status Register */
45 #define WDT_KEY (0xa5<<24)
46 #define WDT_WDRSTT 0x1
49 #define WDT_WDV(x) (x & 0xfff) /* counter value*/
50 #define WDT_WDFIEN (1<<12) /* enable interrupt */
51 #define WDT_WDRSTEN (1<<13) /* enable reset */
52 #define WDT_WDRPROC (1<<14) /* processor reset */
53 #define WDT_WDDIS (1<<15) /* disable */
54 #define WDT_WDD(x) ((x & 0xfff) << 16) /* delta value */
55 #define WDT_WDDBGHLT (1<<28) /* halt in debug */
56 #define WDT_WDIDLEHLT (1<<29) /* halt in idle */
62 #endif /* ARM_AT91_AT91WDTREG_H */