2 * Copyright (c) 2005 Olivier Houchard. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #ifndef AT91RM92REG_H_
29 #define AT91RM92REG_H_
31 /* Chip Specific limits */
32 #define RM9200_PLL_A_MIN_IN_FREQ 1000000 /* 1 MHz */
33 #define RM9200_PLL_A_MAX_IN_FREQ 32000000 /* 32 MHz */
34 #define RM9200_PLL_A_MIN_OUT_FREQ 80000000 /* 80 MHz */
35 #define RM9200_PLL_A_MAX_OUT_FREQ 180000000 /* 180 MHz */
36 #define RM9200_PLL_A_MUL_SHIFT 16
37 #define RM9200_PLL_A_MUL_MASK 0x7FF
38 #define RM9200_PLL_A_DIV_SHIFT 0
39 #define RM9200_PLL_A_DIV_MASK 0xFF
42 * PLL B input frequency spec sheet says it must be between 1MHz and 32MHz,
43 * but it works down as low as 100kHz, a frequency necessary for some
44 * output frequencies to work.
46 * PLL Max output frequency is 240MHz. The errata says 180MHz is the max
47 * for some revisions of this part. Be more permissive and optimistic.
49 #define RM9200_PLL_B_MIN_IN_FREQ 100000 /* 100 KHz */
50 #define RM9200_PLL_B_MAX_IN_FREQ 32000000 /* 32 MHz */
51 #define RM9200_PLL_B_MIN_OUT_FREQ 30000000 /* 30 MHz */
52 #define RM9200_PLL_B_MAX_OUT_FREQ 240000000 /* 240 MHz */
53 #define RM9200_PLL_B_MUL_SHIFT 16
54 #define RM9200_PLL_B_MUL_MASK 0x7FF
55 #define RM9200_PLL_B_DIV_SHIFT 0
56 #define RM9200_PLL_B_DIV_MASK 0xFF
59 * Memory map, from datasheet :
60 * 0x00000000 - 0x0ffffffff : Internal Memories
61 * 0x10000000 - 0x1ffffffff : Chip Select 0
62 * 0x20000000 - 0x2ffffffff : Chip Select 1
63 * 0x30000000 - 0x3ffffffff : Chip Select 2
64 * 0x40000000 - 0x4ffffffff : Chip Select 3
65 * 0x50000000 - 0x5ffffffff : Chip Select 4
66 * 0x60000000 - 0x6ffffffff : Chip Select 5
67 * 0x70000000 - 0x7ffffffff : Chip Select 6
68 * 0x80000000 - 0x8ffffffff : Chip Select 7
69 * 0x90000000 - 0xeffffffff : Undefined (Abort)
70 * 0xf0000000 - 0xfffffffff : Peripherals
75 #define AT91RM92_USART_SIZE 0x4000
76 #define AT91RM92_USART0_BASE 0xffc0000
77 #define AT91RM92_USART0_PDC 0xffc0100
78 #define AT91RM92_USART0_SIZE AT91RM92_USART_SIZE
79 #define AT91RM92_USART1_BASE 0xffc4000
80 #define AT91RM92_USART1_PDC 0xffc4100
81 #define AT91RM92_USART1_SIZE AT91RM92_USART_SIZE
82 #define AT91RM92_USART2_BASE 0xffc8000
83 #define AT91RM92_USART2_PDC 0xffc8100
84 #define AT91RM92_USART2_SIZE AT91RM92_USART_SIZE
85 #define AT91RM92_USART3_BASE 0xffcc000
86 #define AT91RM92_USART3_PDC 0xffcc100
87 #define AT91RM92_USART3_SIZE AT91RM92_USART_SIZE
89 /* System Registers */
91 #define AT91RM92_SYS_BASE 0xffff000
92 #define AT91RM92_SYS_SIZE 0x1000
97 #define AT91RM92_PIO_SIZE 0x200
98 #define AT91RM92_PIOA_BASE 0xffff400
99 #define AT91RM92_PIOA_SIZE AT91RM92_PIO_SIZE
100 #define AT91RM92_PIOB_BASE 0xffff600
101 #define AT91RM92_PIOB_SIZE AT91RM92_PIO_SIZE
102 #define AT91RM92_PIOC_BASE 0xffff800
103 #define AT91RM92_PIOC_SIZE AT91RM92_PIO_SIZE
104 #define AT91RM92_PIOD_BASE 0xffffa00
105 #define AT91RM92_PIOD_SIZE AT91RM92_PIO_SIZE
110 #define AT91RM92_PMC_BASE 0xffffc00
111 #define AT91RM92_PMC_SIZE 0x100
116 * 1: System peripheral (System timer, RTC, DBGU)
117 * 2: PIO Controller A
118 * 3: PIO Controller B
119 * 4: PIO Controller C
120 * 5: PIO Controller D
126 * 11: USB device port
127 * 12: Two-wire interface
132 * 17: Timer Counter 0
133 * 18: Timer Counter 1
134 * 19: Timer Counter 2
135 * 20: Timer Counter 3
136 * 21: Timer Counter 4
137 * 22: Timer Counter 5
149 #define AT91RM92_IRQ_SYSTEM 1
150 #define AT91RM92_IRQ_PIOA 2
151 #define AT91RM92_IRQ_PIOB 3
152 #define AT91RM92_IRQ_PIOC 4
153 #define AT91RM92_IRQ_PIOD 5
154 #define AT91RM92_IRQ_USART0 6
155 #define AT91RM92_IRQ_USART1 7
156 #define AT91RM92_IRQ_USART2 8
157 #define AT91RM92_IRQ_USART3 9
158 #define AT91RM92_IRQ_MCI 10
159 #define AT91RM92_IRQ_UDP 11
160 #define AT91RM92_IRQ_TWI 12
161 #define AT91RM92_IRQ_SPI 13
162 #define AT91RM92_IRQ_SSC0 14
163 #define AT91RM92_IRQ_SSC1 15
164 #define AT91RM92_IRQ_SSC2 16
165 #define AT91RM92_IRQ_TC0 17,18,19
166 #define AT91RM92_IRQ_TC0C0 17
167 #define AT91RM92_IRQ_TC0C1 18
168 #define AT91RM92_IRQ_TC0C2 19
169 #define AT91RM92_IRQ_TC1 20,21,22
170 #define AT91RM92_IRQ_TC1C1 20
171 #define AT91RM92_IRQ_TC1C2 21
172 #define AT91RM92_IRQ_TC1C3 22
173 #define AT91RM92_IRQ_UHP 23
174 #define AT91RM92_IRQ_EMAC 24
175 #define AT91RM92_IRQ_AIC_IRQ0 25
176 #define AT91RM92_IRQ_AIC_IRQ1 26
177 #define AT91RM92_IRQ_AIC_IRQ2 27
178 #define AT91RM92_IRQ_AIC_IRQ3 28
179 #define AT91RM92_IRQ_AIC_IRQ4 29
180 #define AT91RM92_IRQ_AIC_IRQ5 30
181 #define AT91RM92_IRQ_AIC_IRQ6 31
184 #define AT91RM92_IRQ_DBGU AT91RM92_IRQ_SYSTEM
185 #define AT91RM92_IRQ_PMC AT91RM92_IRQ_SYSTEM
186 #define AT91RM92_IRQ_ST AT91RM92_IRQ_SYSTEM
187 #define AT91RM92_IRQ_RTC AT91RM92_IRQ_SYSTEM
188 #define AT91RM92_IRQ_MC AT91RM92_IRQ_SYSTEM
189 #define AT91RM92_IRQ_OHCI AT91RM92_IRQ_UHP
190 #define AT91RM92_IRQ_AIC -1
191 #define AT91RM92_IRQ_CF -1
195 #define AT91RM92_AIC_BASE 0xffff000
196 #define AT91RM92_AIC_SIZE 0x200
199 #define AT91RM92_DBGU_BASE 0xffff200
200 #define AT91RM92_DBGU_SIZE 0x200
202 #define AT91RM92_RTC_BASE 0xffffe00
203 #define AT91RM92_RTC_SIZE 0x100
205 #define AT91RM92_MC_BASE 0xfffff00
206 #define AT91RM92_MC_SIZE 0x100
208 #define AT91RM92_ST_BASE 0xffffd00
209 #define AT91RM92_ST_SIZE 0x100
211 #define AT91RM92_SPI_BASE 0xffe0000
212 #define AT91RM92_SPI_SIZE 0x4000
213 #define AT91RM92_SPI_PDC 0xffe0100
215 #define AT91RM92_SSC_SIZE 0x4000
216 #define AT91RM92_SSC0_BASE 0xffd0000
217 #define AT91RM92_SSC0_PDC 0xffd0100
218 #define AT91RM92_SSC0_SIZE AT91RM92_SSC_SIZE
220 #define AT91RM92_SSC1_BASE 0xffd4000
221 #define AT91RM92_SSC1_PDC 0xffd4100
222 #define AT91RM92_SSC1_SIZE AT91RM92_SSC_SIZE
224 #define AT91RM92_SSC2_BASE 0xffd8000
225 #define AT91RM92_SSC2_PDC 0xffd8100
226 #define AT91RM92_SSC2_SIZE AT91RM92_SSC_SIZE
228 #define AT91RM92_EMAC_BASE 0xffbc000
229 #define AT91RM92_EMAC_SIZE 0x4000
231 #define AT91RM92_TWI_BASE 0xffb8000
232 #define AT91RM92_TWI_SIZE 0x4000
234 #define AT91RM92_MCI_BASE 0xffb4000
235 #define AT91RM92_MCI_PDC 0xffb4100
236 #define AT91RM92_MCI_SIZE 0x4000
238 #define AT91RM92_UDP_BASE 0xffb0000
239 #define AT91RM92_UDP_SIZE 0x4000
241 #define AT91RM92_TC_SIZE 0x4000
242 #define AT91RM92_TC0_BASE 0xffa0000
243 #define AT91RM92_TC0_SIZE AT91RM92_TC_SIZE
244 #define AT91RM92_TC0C0_BASE 0xffa0000
245 #define AT91RM92_TC0C1_BASE 0xffa0040
246 #define AT91RM92_TC0C2_BASE 0xffa0080
248 #define AT91RM92_TC1_BASE 0xffa4000
249 #define AT91RM92_TC1_SIZE AT91RM92_TC_SIZE
250 #define AT91RM92_TC1C0_BASE 0xffa4000
251 #define AT91RM92_TC1C1_BASE 0xffa4040
252 #define AT91RM92_TC1C2_BASE 0xffa4080
254 /* XXX Needs to be carfully coordinated with
255 * other * soc's so phyical and vm address
256 * mapping are unique. XXX
258 #define AT91RM92_OHCI_VA_BASE 0xdfe00000
259 #define AT91RM92_OHCI_BASE 0x00300000
260 #define AT91RM92_OHCI_SIZE 0x00100000
262 #define AT91RM92_CF_VA_BASE 0xdfd00000
263 #define AT91RM92_CF_BASE 0x51400000
264 #define AT91RM92_CF_SIZE 0x00100000
268 #define AT91RM92_SDRAMC_BASE 0xfffff90
269 #define AT91RM92_SDRAMC_MR 0x00
270 #define AT91RM92_SDRAMC_MR_MODE_NORMAL 0
271 #define AT91RM92_SDRAMC_MR_MODE_NOP 1
272 #define AT91RM92_SDRAMC_MR_MODE_PRECHARGE 2
273 #define AT91RM92_SDRAMC_MR_MODE_LOAD_MODE_REGISTER 3
274 #define AT91RM92_SDRAMC_MR_MODE_REFRESH 4
275 #define AT91RM92_SDRAMC_MR_DBW_16 0x10
276 #define AT91RM92_SDRAMC_TR 0x04
277 #define AT91RM92_SDRAMC_CR 0x08
278 #define AT91RM92_SDRAMC_CR_NC_8 0x0
279 #define AT91RM92_SDRAMC_CR_NC_9 0x1
280 #define AT91RM92_SDRAMC_CR_NC_10 0x2
281 #define AT91RM92_SDRAMC_CR_NC_11 0x3
282 #define AT91RM92_SDRAMC_CR_NC_MASK 0x00000003
283 #define AT91RM92_SDRAMC_CR_NR_11 0x0
284 #define AT91RM92_SDRAMC_CR_NR_12 0x4
285 #define AT91RM92_SDRAMC_CR_NR_13 0x8
286 #define AT91RM92_SDRAMC_CR_NR_RES 0xc
287 #define AT91RM92_SDRAMC_CR_NR_MASK 0x0000000c
288 #define AT91RM92_SDRAMC_CR_NB_2 0x00
289 #define AT91RM92_SDRAMC_CR_NB_4 0x10
290 #define AT91RM92_SDRAMC_CR_NB_MASK 0x00000010
291 #define AT91RM92_SDRAMC_CR_NCAS_MASK 0x00000060
292 #define AT91RM92_SDRAMC_CR_TWR_MASK 0x00000780
293 #define AT91RM92_SDRAMC_CR_TRC_MASK 0x00007800
294 #define AT91RM92_SDRAMC_CR_TRP_MASK 0x00078000
295 #define AT91RM92_SDRAMC_CR_TRCD_MASK 0x00780000
296 #define AT91RM92_SDRAMC_CR_TRAS_MASK 0x07800000
297 #define AT91RM92_SDRAMC_CR_TXSR_MASK 0x78000000
298 #define AT91RM92_SDRAMC_SRR 0x0c
299 #define AT91RM92_SDRAMC_LPR 0x10
300 #define AT91RM92_SDRAMC_IER 0x14
301 #define AT91RM92_SDRAMC_IDR 0x18
302 #define AT91RM92_SDRAMC_IMR 0x1c
303 #define AT91RM92_SDRAMC_ISR 0x20
304 #define AT91RM92_SDRAMC_IER_RES 0x1
306 #endif /* AT91RM92REG_H_ */