2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2010 Greg Ansley. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef AT91SAM9260REG_H_
31 #define AT91SAM9260REG_H_
33 /* Chip Specific limits */
34 #define SAM9260_PLL_A_MIN_IN_FREQ 1000000 /* 1 Mhz */
35 #define SAM9260_PLL_A_MAX_IN_FREQ 32000000 /* 32 Mhz */
36 #define SAM9260_PLL_A_MIN_OUT_FREQ 80000000 /* 80 Mhz */
37 #define SAM9260_PLL_A_MAX_OUT_FREQ 240000000 /* 240 Mhz */
38 #define SAM9260_PLL_A_MUL_SHIFT 16
39 #define SAM9260_PLL_A_MUL_MASK 0x3FF
40 #define SAM9260_PLL_A_DIV_SHIFT 0
41 #define SAM9260_PLL_A_DIV_MASK 0xFF
43 #define SAM9260_PLL_B_MIN_IN_FREQ 1000000 /* 1 Mhz */
44 #define SAM9260_PLL_B_MAX_IN_FREQ 5000000 /* 5 Mhz */
45 #define SAM9260_PLL_B_MIN_OUT_FREQ 70000000 /* 70 Mhz */
46 #define SAM9260_PLL_B_MAX_OUT_FREQ 130000000 /* 130 Mhz */
47 #define SAM9260_PLL_B_MUL_SHIFT 16
48 #define SAM9260_PLL_B_MUL_MASK 0x3FF
49 #define SAM9260_PLL_B_DIV_SHIFT 0
50 #define SAM9260_PLL_B_DIV_MASK 0xFF
53 * Memory map, from datasheet :
54 * 0x00000000 - 0x0ffffffff : Internal Memories
55 * 0x10000000 - 0x1ffffffff : Chip Select 0
56 * 0x20000000 - 0x2ffffffff : Chip Select 1
57 * 0x30000000 - 0x3ffffffff : Chip Select 2
58 * 0x40000000 - 0x4ffffffff : Chip Select 3
59 * 0x50000000 - 0x5ffffffff : Chip Select 4
60 * 0x60000000 - 0x6ffffffff : Chip Select 5
61 * 0x70000000 - 0x7ffffffff : Chip Select 6
62 * 0x80000000 - 0x8ffffffff : Chip Select 7
63 * 0x90000000 - 0xeffffffff : Undefined (Abort)
64 * 0xf0000000 - 0xfffffffff : Peripherals
67 #define AT91_CHIPSELECT_0 0x10000000
68 #define AT91_CHIPSELECT_1 0x20000000
69 #define AT91_CHIPSELECT_2 0x30000000
70 #define AT91_CHIPSELECT_3 0x40000000
71 #define AT91_CHIPSELECT_4 0x50000000
72 #define AT91_CHIPSELECT_5 0x60000000
73 #define AT91_CHIPSELECT_6 0x70000000
74 #define AT91_CHIPSELECT_7 0x80000000
77 #define AT91SAM9260_EMAC_BASE 0xffc4000
78 #define AT91SAM9260_EMAC_SIZE 0x4000
80 #define AT91SAM9260_RSTC_BASE 0xffffd00
81 #define AT91SAM9260_RSTC_SIZE 0x10
84 #define RSTC_PROCRST (1 << 0)
85 #define RSTC_PERRST (1 << 2)
86 #define RSTC_KEY (0xa5 << 24)
90 #define AT91SAM9260_USART_SIZE 0x4000
91 #define AT91SAM9260_USART0_BASE 0xffb0000
92 #define AT91SAM9260_USART0_PDC 0xffb0100
93 #define AT91SAM9260_USART0_SIZE AT91SAM9260_USART_SIZE
94 #define AT91SAM9260_USART1_BASE 0xffb4000
95 #define AT91SAM9260_USART1_PDC 0xffb4100
96 #define AT91SAM9260_USART1_SIZE AT91SAM9260_USART_SIZE
97 #define AT91SAM9260_USART2_BASE 0xffb8000
98 #define AT91SAM9260_USART2_PDC 0xffb8100
99 #define AT91SAM9260_USART2_SIZE AT91SAM9260_USART_SIZE
100 #define AT91SAM9260_USART3_BASE 0xffd0000
101 #define AT91SAM9260_USART3_PDC 0xffd0100
102 #define AT91SAM9260_USART3_SIZE AT91SAM9260_USART_SIZE
103 #define AT91SAM9260_USART4_BASE 0xffd4000
104 #define AT91SAM9260_USART4_PDC 0xffd4100
105 #define AT91SAM9260_USART4_SIZE AT91SAM9260_USART_SIZE
106 #define AT91SAM9260_USART5_BASE 0xffd8000
107 #define AT91SAM9260_USART5_PDC 0xffd8100
108 #define AT91SAM9260_USART5_SIZE AT91SAM9260_USART_SIZE
111 #define AT91SAM9260_TC0_BASE 0xffa0000
112 #define AT91SAM9260_TC0_SIZE 0x4000
113 #define AT91SAM9260_TC0C0_BASE 0xffa0000
114 #define AT91SAM9260_TC0C1_BASE 0xffa0040
115 #define AT91SAM9260_TC0C2_BASE 0xffa0080
117 #define AT91SAM9260_TC1_BASE 0xffdc000
118 #define AT91SAM9260_TC1_SIZE 0x4000
122 #define AT91SAM9260_SPI0_BASE 0xffc8000
124 #define AT91SAM9260_SPI0_SIZE 0x4000
125 #define AT91SAM9260_IRQ_SPI0 12
127 #define AT91SAM9260_SPI1_BASE 0xffcc000
128 #define AT91SAM9260_SPI1_SIZE 0x4000
129 #define AT91SAM9260_IRQ_SPI1 13
131 /* System Registers */
132 #define AT91SAM9260_SYS_BASE 0xffff000
133 #define AT91SAM9260_SYS_SIZE 0x1000
135 #define AT91SAM9260_MATRIX_BASE 0xfffee00
136 #define AT91SAM9260_MATRIX_SIZE 0x1000
137 #define AT91SAM9260_EBICSA 0x011C
139 #define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
141 #define AT91SAM9260_DBGU_BASE 0xffff200
142 #define AT91SAM9260_DBGU_SIZE 0x200
147 #define AT91SAM9260_PIOA_BASE 0xffff400
148 #define AT91SAM9260_PIOA_SIZE 0x200
149 #define AT91SAM9260_PIOB_BASE 0xffff600
150 #define AT91SAM9260_PIOB_SIZE 0x200
151 #define AT91SAM9260_PIOC_BASE 0xffff800
152 #define AT91SAM9260_PIOC_SIZE 0x200
154 #define AT91RM92_PMC_BASE 0xffffc00
155 #define AT91RM92_PMC_SIZE 0x100
159 * 1: System peripheral (System timer, RTC, DBGU)
160 * 2: PIO Controller A
161 * 3: PIO Controller B
162 * 4: PIO Controller C
168 * 10: USB device port
169 * 11: Two-wire interface
175 * 17: Timer Counter 0
176 * 18: Timer Counter 1
177 * 19: Timer Counter 2
184 * 26: Timer Counter 3
185 * 27: Timer Counter 4
186 * 28: Timer Counter 5
192 #define AT91SAM9260_IRQ_SYSTEM 1
193 #define AT91SAM9260_IRQ_PIOA 2
194 #define AT91SAM9260_IRQ_PIOB 3
195 #define AT91SAM9260_IRQ_PIOC 4
196 #define AT91SAM9260_IRQ_USART0 6
197 #define AT91SAM9260_IRQ_USART1 7
198 #define AT91SAM9260_IRQ_USART2 8
199 #define AT91SAM9260_IRQ_MCI 9
200 #define AT91SAM9260_IRQ_UDP 10
201 #define AT91SAM9260_IRQ_TWI 11
202 #define AT91SAM9260_IRQ_SPI0 12
203 #define AT91SAM9260_IRQ_SPI1 13
204 #define AT91SAM9260_IRQ_SSC0 14
205 #define AT91SAM9260_IRQ_SSC1 15
206 #define AT91SAM9260_IRQ_SSC2 16
207 #define AT91SAM9260_IRQ_TC0 17
208 #define AT91SAM9260_IRQ_TC1 18
209 #define AT91SAM9260_IRQ_TC2 19
210 #define AT91SAM9260_IRQ_UHP 20
211 #define AT91SAM9260_IRQ_EMAC 21
212 #define AT91SAM9260_IRQ_USART3 23
213 #define AT91SAM9260_IRQ_USART4 24
214 #define AT91SAM9260_IRQ_USART5 25
215 #define AT91SAM9260_IRQ_AICBASE 29
218 #define AT91SAM9260_IRQ_DBGU AT91SAM9260_IRQ_SYSTEM
219 #define AT91SAM9260_IRQ_PMC AT91SAM9260_IRQ_SYSTEM
220 #define AT91SAM9260_IRQ_WDT AT91SAM9260_IRQ_SYSTEM
221 #define AT91SAM9260_IRQ_PIT AT91SAM9260_IRQ_SYSTEM
222 #define AT91SAM9260_IRQ_RSTC AT91SAM9260_IRQ_SYSTEM
223 #define AT91SAM9260_IRQ_OHCI AT91SAM9260_IRQ_UHP
224 #define AT91SAM9260_IRQ_NAND (-1)
225 #define AT91SAM9260_IRQ_AIC (-1)
227 #define AT91SAM9260_AIC_BASE 0xffff000
228 #define AT91SAM9260_AIC_SIZE 0x200
232 #define AT91SAM9260_WDT_BASE 0xffffd40
233 #define AT91SAM9260_WDT_SIZE 0x10
235 #define AT91SAM9260_PIT_BASE 0xffffd30
236 #define AT91SAM9260_PIT_SIZE 0x10
238 #define AT91SAM9260_SMC_BASE 0xfffec00
239 #define AT91SAM9260_SMC_SIZE 0x200
241 #define AT91SAM9260_PMC_BASE 0xffffc00
242 #define AT91SAM9260_PMC_SIZE 0x100
244 #define AT91SAM9260_UDP_BASE 0xffa4000
245 #define AT91SAM9260_UDP_SIZE 0x4000
247 #define AT91SAM9260_MCI_BASE 0xffa8000
248 #define AT91SAM9260_MCI_SIZE 0x4000
250 #define AT91SAM9260_TWI_BASE 0xffaC000
251 #define AT91SAM9260_TWI_SIZE 0x4000
253 /* XXX Needs to be carfully coordinated with
254 * other * soc's so phyical and vm address
255 * mapping are unique. XXX
257 #define AT91SAM9260_OHCI_VA_BASE 0xdfc00000
258 #define AT91SAM9260_OHCI_BASE 0x00500000
259 #define AT91SAM9260_OHCI_SIZE 0x00100000
261 #define AT91SAM9260_NAND_VA_BASE 0xe0000000
262 #define AT91SAM9260_NAND_BASE 0x40000000
263 #define AT91SAM9260_NAND_SIZE 0x10000000
267 #define AT91SAM9260_SDRAMC_BASE 0xfffea00
268 #define AT91SAM9260_SDRAMC_MR 0x00
269 #define AT91SAM9260_SDRAMC_MR_MODE_NORMAL 0
270 #define AT91SAM9260_SDRAMC_MR_MODE_NOP 1
271 #define AT91SAM9260_SDRAMC_MR_MODE_PRECHARGE 2
272 #define AT91SAM9260_SDRAMC_MR_MODE_LOAD_MODE_REGISTER 3
273 #define AT91SAM9260_SDRAMC_MR_MODE_REFRESH 4
274 #define AT91SAM9260_SDRAMC_TR 0x04
275 #define AT91SAM9260_SDRAMC_CR 0x08
276 #define AT91SAM9260_SDRAMC_CR_NC_8 0x0
277 #define AT91SAM9260_SDRAMC_CR_NC_9 0x1
278 #define AT91SAM9260_SDRAMC_CR_NC_10 0x2
279 #define AT91SAM9260_SDRAMC_CR_NC_11 0x3
280 #define AT91SAM9260_SDRAMC_CR_NC_MASK 0x00000003
281 #define AT91SAM9260_SDRAMC_CR_NR_11 0x0
282 #define AT91SAM9260_SDRAMC_CR_NR_12 0x4
283 #define AT91SAM9260_SDRAMC_CR_NR_13 0x8
284 #define AT91SAM9260_SDRAMC_CR_NR_RES 0xc
285 #define AT91SAM9260_SDRAMC_CR_NR_MASK 0x0000000c
286 #define AT91SAM9260_SDRAMC_CR_NB_2 0x00
287 #define AT91SAM9260_SDRAMC_CR_NB_4 0x10
288 #define AT91SAM9260_SDRAMC_CR_DBW_16 0x80
289 #define AT91SAM9260_SDRAMC_CR_NB_MASK 0x00000010
290 #define AT91SAM9260_SDRAMC_CR_NCAS_MASK 0x00000060
291 #define AT91SAM9260_SDRAMC_CR_TWR_MASK 0x00000780
292 #define AT91SAM9260_SDRAMC_CR_TRC_MASK 0x00007800
293 #define AT91SAM9260_SDRAMC_CR_TRP_MASK 0x00078000
294 #define AT91SAM9260_SDRAMC_CR_TRCD_MASK 0x00780000
295 #define AT91SAM9260_SDRAMC_CR_TRAS_MASK 0x07800000
296 #define AT91SAM9260_SDRAMC_CR_TXSR_MASK 0x78000000
297 #define AT91SAM9260_SDRAMC_HSR 0x0c
298 #define AT91SAM9260_SDRAMC_LPR 0x10
299 #define AT91SAM9260_SDRAMC_IER 0x14
300 #define AT91SAM9260_SDRAMC_IDR 0x18
301 #define AT91SAM9260_SDRAMC_IMR 0x1c
302 #define AT91SAM9260_SDRAMC_ISR 0x20
303 #define AT91SAM9260_SDRAMC_MDR 0x24
305 #endif /* AT91SAM9260REG_H_*/