2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2009 Sylvestre Gallon. All rights reserved.
5 * Copyright (c) 2010 Greg Ansley. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #ifndef AT91SAM9G20REG_H_
32 #define AT91SAM9G20REG_H_
34 /* Chip Specific limits */
35 #define SAM9G20_PLL_A_MIN_IN_FREQ 2000000 /* 2 Mhz */
36 #define SAM9G20_PLL_A_MAX_IN_FREQ 32000000 /* 32 Mhz */
37 #define SAM9G20_PLL_A_MIN_OUT_FREQ 400000000 /* 400 Mhz */
38 #define SAM9G20_PLL_A_MAX_OUT_FREQ 800000000 /* 800 Mhz */
39 #define SAM9G20_PLL_A_MUL_SHIFT 16
40 #define SAM9G20_PLL_A_MUL_MASK 0xFF
41 #define SAM9G20_PLL_A_DIV_SHIFT 0
42 #define SAM9G20_PLL_A_DIV_MASK 0xFF
44 #define SAM9G20_PLL_B_MIN_IN_FREQ 2000000 /* 2 Mhz */
45 #define SAM9G20_PLL_B_MAX_IN_FREQ 32000000 /* 32 Mhz */
46 #define SAM9G20_PLL_B_MIN_OUT_FREQ 30000000 /* 30 Mhz */
47 #define SAM9G20_PLL_B_MAX_OUT_FREQ 100000000 /* 100 Mhz */
48 #define SAM9G20_PLL_B_MUL_SHIFT 16
49 #define SAM9G20_PLL_B_MUL_MASK 0x3F
50 #define SAM9G20_PLL_B_DIV_SHIFT 0
51 #define SAM9G20_PLL_B_DIV_MASK 0xFF
54 * Memory map, from datasheet :
55 * 0x00000000 - 0x0ffffffff : Internal Memories
56 * 0x10000000 - 0x1ffffffff : Chip Select 0
57 * 0x20000000 - 0x2ffffffff : Chip Select 1
58 * 0x30000000 - 0x3ffffffff : Chip Select 2
59 * 0x40000000 - 0x4ffffffff : Chip Select 3
60 * 0x50000000 - 0x5ffffffff : Chip Select 4
61 * 0x60000000 - 0x6ffffffff : Chip Select 5
62 * 0x70000000 - 0x7ffffffff : Chip Select 6
63 * 0x80000000 - 0x8ffffffff : Chip Select 7
64 * 0x90000000 - 0xeffffffff : Undefined (Abort)
65 * 0xf0000000 - 0xfffffffff : Peripherals
68 #define AT91_CHIPSELECT_0 0x10000000
69 #define AT91_CHIPSELECT_1 0x20000000
70 #define AT91_CHIPSELECT_2 0x30000000
71 #define AT91_CHIPSELECT_3 0x40000000
72 #define AT91_CHIPSELECT_4 0x50000000
73 #define AT91_CHIPSELECT_5 0x60000000
74 #define AT91_CHIPSELECT_6 0x70000000
75 #define AT91_CHIPSELECT_7 0x80000000
78 #define AT91SAM9G20_EMAC_BASE 0xffc4000
79 #define AT91SAM9G20_EMAC_SIZE 0x4000
81 #define AT91SAM9G20_RSTC_BASE 0xffffd00
82 #define AT91SAM9G20_RSTC_SIZE 0x10
85 #define RSTC_PROCRST (1 << 0)
86 #define RSTC_PERRST (1 << 2)
87 #define RSTC_KEY (0xa5 << 24)
91 #define AT91SAM9G20_USART_SIZE 0x4000
92 #define AT91SAM9G20_USART0_BASE 0xffb0000
93 #define AT91SAM9G20_USART0_PDC 0xffb0100
94 #define AT91SAM9G20_USART0_SIZE AT91SAM9G20_USART_SIZE
95 #define AT91SAM9G20_USART1_BASE 0xffb4000
96 #define AT91SAM9G20_USART1_PDC 0xffb4100
97 #define AT91SAM9G20_USART1_SIZE AT91SAM9G20_USART_SIZE
98 #define AT91SAM9G20_USART2_BASE 0xffb8000
99 #define AT91SAM9G20_USART2_PDC 0xffb8100
100 #define AT91SAM9G20_USART2_SIZE AT91SAM9G20_USART_SIZE
101 #define AT91SAM9G20_USART3_BASE 0xffd0000
102 #define AT91SAM9G20_USART3_PDC 0xffd0100
103 #define AT91SAM9G20_USART3_SIZE AT91SAM9G20_USART_SIZE
104 #define AT91SAM9G20_USART4_BASE 0xffd4000
105 #define AT91SAM9G20_USART4_PDC 0xffd4100
106 #define AT91SAM9G20_USART4_SIZE AT91SAM9G20_USART_SIZE
107 #define AT91SAM9G20_USART5_BASE 0xffd8000
108 #define AT91SAM9G20_USART5_PDC 0xffd8100
109 #define AT91SAM9G20_USART5_SIZE AT91SAM9G20_USART_SIZE
112 #define AT91SAM9G20_TC0_BASE 0xffa0000
113 #define AT91SAM9G20_TC0_SIZE 0x4000
114 #define AT91SAM9G20_TC0C0_BASE 0xffa0000
115 #define AT91SAM9G20_TC0C1_BASE 0xffa0040
116 #define AT91SAM9G20_TC0C2_BASE 0xffa0080
118 #define AT91SAM9G20_TC1_BASE 0xffdc000
119 #define AT91SAM9G20_TC1_SIZE 0x4000
123 #define AT91SAM9G20_SPI0_BASE 0xffc8000
125 #define AT91SAM9G20_SPI0_SIZE 0x4000
126 #define AT91SAM9G20_IRQ_SPI0 12
128 #define AT91SAM9G20_SPI1_BASE 0xffcc000
129 #define AT91SAM9G20_SPI1_SIZE 0x4000
130 #define AT91SAM9G20_IRQ_SPI1 13
132 /* System Registers */
133 #define AT91SAM9G20_SYS_BASE 0xffff000
134 #define AT91SAM9G20_SYS_SIZE 0x1000
136 #define AT91SAM9G20_MATRIX_BASE 0xfffee00
137 #define AT91SAM9G20_MATRIX_SIZE 0x1000
138 #define AT91SAM9G20_EBICSA 0x011C
140 #define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
142 #define AT91SAM9G20_DBGU_BASE 0xffff200
143 #define AT91SAM9G20_DBGU_SIZE 0x200
148 #define AT91SAM9G20_PIOA_BASE 0xffff400
149 #define AT91SAM9G20_PIOA_SIZE 0x200
150 #define AT91SAM9G20_PIOB_BASE 0xffff600
151 #define AT91SAM9G20_PIOB_SIZE 0x200
152 #define AT91SAM9G20_PIOC_BASE 0xffff800
153 #define AT91SAM9G20_PIOC_SIZE 0x200
155 #define AT91RM92_PMC_BASE 0xffffc00
156 #define AT91RM92_PMC_SIZE 0x100
160 * 1: System peripheral (System timer, RTC, DBGU)
161 * 2: PIO Controller A
162 * 3: PIO Controller B
163 * 4: PIO Controller C
169 * 10: USB device port
170 * 11: Two-wire interface
176 * 17: Timer Counter 0
177 * 18: Timer Counter 1
178 * 19: Timer Counter 2
185 * 26: Timer Counter 3
186 * 27: Timer Counter 4
187 * 28: Timer Counter 5
193 #define AT91SAM9G20_IRQ_SYSTEM 1
194 #define AT91SAM9G20_IRQ_PIOA 2
195 #define AT91SAM9G20_IRQ_PIOB 3
196 #define AT91SAM9G20_IRQ_PIOC 4
197 #define AT91SAM9G20_IRQ_USART0 6
198 #define AT91SAM9G20_IRQ_USART1 7
199 #define AT91SAM9G20_IRQ_USART2 8
200 #define AT91SAM9G20_IRQ_MCI 9
201 #define AT91SAM9G20_IRQ_UDP 10
202 #define AT91SAM9G20_IRQ_TWI 11
203 #define AT91SAM9G20_IRQ_SPI0 12
204 #define AT91SAM9G20_IRQ_SPI1 13
205 #define AT91SAM9G20_IRQ_SSC0 14
206 #define AT91SAM9G20_IRQ_SSC1 15
207 #define AT91SAM9G20_IRQ_SSC2 16
208 #define AT91SAM9G20_IRQ_TC0 17
209 #define AT91SAM9G20_IRQ_TC1 18
210 #define AT91SAM9G20_IRQ_TC2 19
211 #define AT91SAM9G20_IRQ_UHP 20
212 #define AT91SAM9G20_IRQ_EMAC 21
213 #define AT91SAM9G20_IRQ_USART3 23
214 #define AT91SAM9G20_IRQ_USART4 24
215 #define AT91SAM9G20_IRQ_USART5 25
216 #define AT91SAM9G20_IRQ_AICBASE 29
219 #define AT91SAM9G20_IRQ_DBGU AT91SAM9G20_IRQ_SYSTEM
220 #define AT91SAM9G20_IRQ_PMC AT91SAM9G20_IRQ_SYSTEM
221 #define AT91SAM9G20_IRQ_WDT AT91SAM9G20_IRQ_SYSTEM
222 #define AT91SAM9G20_IRQ_PIT AT91SAM9G20_IRQ_SYSTEM
223 #define AT91SAM9G20_IRQ_RSTC AT91SAM9G20_IRQ_SYSTEM
224 #define AT91SAM9G20_IRQ_OHCI AT91SAM9G20_IRQ_UHP
225 #define AT91SAM9G20_IRQ_NAND (-1)
226 #define AT91SAM9G20_IRQ_AIC (-1)
228 #define AT91SAM9G20_AIC_BASE 0xffff000
229 #define AT91SAM9G20_AIC_SIZE 0x200
233 #define AT91SAM9G20_WDT_BASE 0xffffd40
234 #define AT91SAM9G20_WDT_SIZE 0x10
236 #define AT91SAM9G20_PIT_BASE 0xffffd30
237 #define AT91SAM9G20_PIT_SIZE 0x10
239 #define AT91SAM9G20_SMC_BASE 0xfffec00
240 #define AT91SAM9G20_SMC_SIZE 0x200
242 #define AT91SAM9G20_PMC_BASE 0xffffc00
243 #define AT91SAM9G20_PMC_SIZE 0x100
245 #define AT91SAM9G20_UDP_BASE 0xffa4000
246 #define AT91SAM9G20_UDP_SIZE 0x4000
248 #define AT91SAM9G20_MCI_BASE 0xffa8000
249 #define AT91SAM9G20_MCI_SIZE 0x4000
251 #define AT91SAM9G20_TWI_BASE 0xffaC000
252 #define AT91SAM9G20_TWI_SIZE 0x4000
254 /* XXX Needs to be carfully coordinated with
255 * other * soc's so phyical and vm address
256 * mapping are unique. XXX
258 #define AT91SAM9G20_OHCI_VA_BASE 0xdfc00000
259 #define AT91SAM9G20_OHCI_BASE 0x00500000
260 #define AT91SAM9G20_OHCI_SIZE 0x00100000
262 #define AT91SAM9G20_NAND_VA_BASE 0xe0000000
263 #define AT91SAM9G20_NAND_BASE 0x40000000
264 #define AT91SAM9G20_NAND_SIZE 0x10000000
267 #define AT91SAM9G20_SDRAMC_BASE 0xfffea00
268 #define AT91SAM9G20_SDRAMC_MR 0x00
269 #define AT91SAM9G20_SDRAMC_MR_MODE_NORMAL 0
270 #define AT91SAM9G20_SDRAMC_MR_MODE_NOP 1
271 #define AT91SAM9G20_SDRAMC_MR_MODE_PRECHARGE 2
272 #define AT91SAM9G20_SDRAMC_MR_MODE_LOAD_MODE_REGISTER 3
273 #define AT91SAM9G20_SDRAMC_MR_MODE_REFRESH 4
274 #define AT91SAM9G20_SDRAMC_TR 0x04
275 #define AT91SAM9G20_SDRAMC_CR 0x08
276 #define AT91SAM9G20_SDRAMC_CR_NC_8 0x0
277 #define AT91SAM9G20_SDRAMC_CR_NC_9 0x1
278 #define AT91SAM9G20_SDRAMC_CR_NC_10 0x2
279 #define AT91SAM9G20_SDRAMC_CR_NC_11 0x3
280 #define AT91SAM9G20_SDRAMC_CR_NC_MASK 0x00000003
281 #define AT91SAM9G20_SDRAMC_CR_NR_11 0x0
282 #define AT91SAM9G20_SDRAMC_CR_NR_12 0x4
283 #define AT91SAM9G20_SDRAMC_CR_NR_13 0x8
284 #define AT91SAM9G20_SDRAMC_CR_NR_RES 0xc
285 #define AT91SAM9G20_SDRAMC_CR_NR_MASK 0x0000000c
286 #define AT91SAM9G20_SDRAMC_CR_NB_2 0x00
287 #define AT91SAM9G20_SDRAMC_CR_NB_4 0x10
288 #define AT91SAM9G20_SDRAMC_CR_DBW_16 0x80
289 #define AT91SAM9G20_SDRAMC_CR_NB_MASK 0x00000010
290 #define AT91SAM9G20_SDRAMC_CR_NCAS_MASK 0x00000060
291 #define AT91SAM9G20_SDRAMC_CR_TWR_MASK 0x00000780
292 #define AT91SAM9G20_SDRAMC_CR_TRC_MASK 0x00007800
293 #define AT91SAM9G20_SDRAMC_CR_TRP_MASK 0x00078000
294 #define AT91SAM9G20_SDRAMC_CR_TRCD_MASK 0x00780000
295 #define AT91SAM9G20_SDRAMC_CR_TRAS_MASK 0x07800000
296 #define AT91SAM9G20_SDRAMC_CR_TXSR_MASK 0x78000000
297 #define AT91SAM9G20_SDRAMC_HSR 0x0c
298 #define AT91SAM9G20_SDRAMC_LPR 0x10
299 #define AT91SAM9G20_SDRAMC_IER 0x14
300 #define AT91SAM9G20_SDRAMC_IDR 0x18
301 #define AT91SAM9G20_SDRAMC_IMR 0x1c
302 #define AT91SAM9G20_SDRAMC_ISR 0x20
303 #define AT91SAM9G20_SDRAMC_MDR 0x24
305 #endif /* AT91SAM9G20REG_H_*/