sys/arm/at91/at91sam9g45reg.h

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2009 Sylvestre Gallon.  All rights reserved.
   5  * Copyright (c) 2010 Greg Ansley.  All rights reserved.
   6  * Copyright (c) 2012 Andrew Turner.  All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  */
  29
  30 /* $FreeBSD$ */
  31
  32 #ifndef AT91SAM9G45REG_H_
  33 #define AT91SAM9G45REG_H_
  34
  35 /* Chip Specific limits */
  36 #define SAM9G45_PLL_A_MIN_IN_FREQ         2000000 /*   2 Mhz */
  37 #define SAM9G45_PLL_A_MAX_IN_FREQ        32000000 /*  32 Mhz */
  38 #define SAM9G45_PLL_A_MIN_OUT_FREQ      400000000 /* 400 Mhz */
  39 #define SAM9G45_PLL_A_MAX_OUT_FREQ      800000000 /* 800 Mhz */
  40 #define SAM9G45_PLL_A_MUL_SHIFT 16
  41 #define SAM9G45_PLL_A_MUL_MASK 0xFF
  42 #define SAM9G45_PLL_A_DIV_SHIFT 0
  43 #define SAM9G45_PLL_A_DIV_MASK 0xFF
  44
  45 /*
  46  * Memory map, from datasheet :
  47  * 0x00000000 - 0x0ffffffff : Internal Memories
  48  * 0x10000000 - 0x1ffffffff : Chip Select 0
  49  * 0x20000000 - 0x2ffffffff : Chip Select 1
  50  * 0x30000000 - 0x3ffffffff : Chip Select 2
  51  * 0x40000000 - 0x4ffffffff : Chip Select 3
  52  * 0x50000000 - 0x5ffffffff : Chip Select 4
  53  * 0x60000000 - 0x6ffffffff : Chip Select 5
  54  * 0x70000000 - 0x7ffffffff : DDR SDRC 0
  55  * 0x80000000 - 0xeffffffff : Undefined (Abort)
  56  * 0xf0000000 - 0xfffffffff : Peripherals
  57  */
  58
  59 #define AT91_CHIPSELECT_0 0x10000000
  60 #define AT91_CHIPSELECT_1 0x20000000
  61 #define AT91_CHIPSELECT_2 0x30000000
  62 #define AT91_CHIPSELECT_3 0x40000000
  63 #define AT91_CHIPSELECT_4 0x50000000
  64 #define AT91_CHIPSELECT_5 0x60000000
  65
  66
  67 #define AT91SAM9G45_EMAC_BASE   0xffbc000
  68 #define AT91SAM9G45_EMAC_SIZE   0x4000
  69
  70 #define AT91SAM9G45_RSTC_BASE   0xffffd00
  71 #define AT91SAM9G45_RSTC_SIZE   0x10
  72
  73 /* USART*/
  74
  75 #define AT91SAM9G45_USART_SIZE  0x4000
  76 #define AT91SAM9G45_USART0_BASE 0xff8c000
  77 #define AT91SAM9G45_USART0_SIZE AT91SAM9G45_USART_SIZE
  78 #define AT91SAM9G45_USART1_BASE 0xff90000
  79 #define AT91SAM9G45_USART1_SIZE AT91SAM9G45_USART_SIZE
  80 #define AT91SAM9G45_USART2_BASE 0xff94000
  81 #define AT91SAM9G45_USART2_SIZE AT91SAM9G45_USART_SIZE
  82 #define AT91SAM9G45_USART3_BASE 0xff98000
  83 #define AT91SAM9G45_USART3_SIZE AT91SAM9G45_USART_SIZE
  84
  85 /*TC*/
  86 #define AT91SAM9G45_TC0_BASE    0xff7c000
  87 #define AT91SAM9G45_TC0_SIZE    0x4000
  88 #define AT91SAM9G45_TC0C0_BASE  0xff7c000
  89 #define AT91SAM9G45_TC0C1_BASE  0xff7c040
  90 #define AT91SAM9G45_TC0C2_BASE  0xff7c080
  91
  92 #define AT91SAM9G45_TC1_BASE    0xffd4000
  93 #define AT91SAM9G45_TC1_SIZE    0x4000
  94 #define AT91SAM9G45_TC1C0_BASE  0xffd4000
  95 #define AT91SAM9G45_TC1C1_BASE  0xffd4040
  96 #define AT91SAM9G45_TC1C2_BASE  0xffd4080
  97
  98 /*SPI*/
  99
 100 #define AT91SAM9G45_SPI0_BASE   0xffa48000
 101 #define AT91SAM9G45_SPI0_SIZE   0x4000
 102
 103 #define AT91SAM9G45_SPI1_BASE   0xffa8000
 104 #define AT91SAM9G45_SPI1_SIZE   0x4000
 105
 106 /* System Registers */
 107 #define AT91SAM9G45_SYS_BASE    0xffff000
 108 #define AT91SAM9G45_SYS_SIZE    0x1000
 109
 110 #define AT91SAM9G45_MATRIX_BASE 0xfffea00
 111 #define AT91SAM9G45_MATRIX_SIZE 0x200
 112
 113 #define AT91SAM9G45_DBGU_BASE   0xfffee00
 114 #define AT91SAM9G45_DBGU_SIZE   0x200
 115
 116 /*
 117  * PIO
 118  */
 119 #define AT91SAM9G45_PIOA_BASE   0xffff200
 120 #define AT91SAM9G45_PIOA_SIZE   0x200
 121 #define AT91SAM9G45_PIOB_BASE   0xffff400
 122 #define AT91SAM9G45_PIOB_SIZE   0x200
 123 #define AT91SAM9G45_PIOC_BASE   0xffff600
 124 #define AT91SAM9G45_PIOC_SIZE   0x200
 125 #define AT91SAM9G45_PIOD_BASE   0xffff800
 126 #define AT91SAM9G45_PIOD_SIZE   0x200
 127 #define AT91SAM9G45_PIOE_BASE   0xffffa00
 128 #define AT91SAM9G45_PIOE_SIZE   0x200
 129
 130 #define AT91SAM9G45_PMC_BASE    0xffffc00
 131 #define AT91SAM9G45_PMC_SIZE    0x100
 132
 133 /* IRQs : */
 134 /*
 135  * 0: AIC
 136  * 1: System peripheral (System timer, RTC, DBGU)
 137  * 2: PIO Controller A
 138  * 3: PIO Controller B
 139  * 4: PIO Controller C
 140  * 5: PIO Controller D/E
 141  * 6: TRNG
 142  * 7: USART 0
 143  * 8: USART 1
 144  * 9: USART 2
 145  * 10: USART 3
 146  * 11: Multimedia Card interface 0
 147  * 12: Two-wire interface 0
 148  * 13: Two-wire interface 1
 149  * 14: SPI 0
 150  * 15: SPI 1
 151  * 16: SSC 0
 152  * 17: SSC 1
 153  * 18: Timer Counter 0, 1, 2, 3, 4, 5
 154  * 19: PWM
 155  * 20: Touch Screen ADC
 156  * 21: DMA
 157  * 22: USB Host port
 158  * 23: LCD
 159  * 24: AC97
 160  * 25: EMAC
 161  * 26: Image Sensor Interface
 162  * 27: USB Device High Speed
 163  * 28: -
 164  * 29: Multimedia Card interface 1
 165  * 30: Reserved
 166  * 31: AIC
 167  */
 168
 169 #define AT91SAM9G45_IRQ_SYSTEM  1
 170 #define AT91SAM9G45_IRQ_PIOA    2
 171 #define AT91SAM9G45_IRQ_PIOB    3
 172 #define AT91SAM9G45_IRQ_PIOC    4
 173 #define AT91SAM9G45_IRQ_PIODE   5
 174 #define AT91SAM9G45_IRQ_TRNG    6
 175 #define AT91SAM9G45_IRQ_USART0  7
 176 #define AT91SAM9G45_IRQ_USART1  8
 177 #define AT91SAM9G45_IRQ_USART2  9
 178 #define AT91SAM9G45_IRQ_USART3  10
 179 #define AT91SAM9G45_IRQ_HSMCI0  11
 180 #define AT91SAM9G45_IRQ_TWI0    12
 181 #define AT91SAM9G45_IRQ_TWI1    13
 182 #define AT91SAM9G45_IRQ_SPI0    14
 183 #define AT91SAM9G45_IRQ_SPI1    15
 184 #define AT91SAM9G45_IRQ_SSC0    16
 185 #define AT91SAM9G45_IRQ_SSC1    17
 186 #define AT91SAM9G45_IRQ_TC0_TC5 18
 187 #define AT91SAM9G45_IRQ_PWM     19
 188 #define AT91SAM9G45_IRQ_TSADCC  20
 189 #define AT91SAM9G45_IRQ_DMA     21
 190 #define AT91SAM9G45_IRQ_UHP     22
 191 #define AT91SAM9G45_IRQ_LCDC    23
 192 #define AT91SAM9G45_IRQ_AC97C   24
 193 #define AT91SAM9G45_IRQ_EMAC    25
 194 #define AT91SAM9G45_IRQ_ISI     26
 195 #define AT91SAM9G45_IRQ_UDPHS   27
 196 /* Reserved 28 */
 197 #define AT91SAM9G45_IRQ_HSMCI1  29
 198 /* Reserved 30 */
 199 #define AT91SAM9G45_IRQ_AICBASE 31
 200
 201 /* Alias */
 202 #define AT91SAM9G45_IRQ_DBGU    AT91SAM9G45_IRQ_SYSTEM
 203 #define AT91SAM9G45_IRQ_PMC     AT91SAM9G45_IRQ_SYSTEM
 204 #define AT91SAM9G45_IRQ_WDT     AT91SAM9G45_IRQ_SYSTEM
 205 #define AT91SAM9G45_IRQ_PIT     AT91SAM9G45_IRQ_SYSTEM
 206 #define AT91SAM9G45_IRQ_RSTC    AT91SAM9G45_IRQ_SYSTEM
 207 #define AT91SAM9G45_IRQ_PIOD    AT91SAM9G45_IRQ_PIODE
 208 #define AT91SAM9G45_IRQ_PIOE    AT91SAM9G45_IRQ_PIODE
 209 #define AT91SAM9G45_IRQ_OHCI    AT91SAM9G45_IRQ_UHP
 210 #define AT91SAM9G45_IRQ_TC0     AT91SAM9G45_IRQ_TC0_TC5
 211 #define AT91SAM9G45_IRQ_TC1     AT91SAM9G45_IRQ_TC0_TC5
 212 #define AT91SAM9G45_IRQ_TC2     AT91SAM9G45_IRQ_TC0_TC5
 213 #define AT91SAM9G45_IRQ_TC3     AT91SAM9G45_IRQ_TC0_TC5
 214 #define AT91SAM9G45_IRQ_TC4     AT91SAM9G45_IRQ_TC0_TC5
 215 #define AT91SAM9G45_IRQ_TC5     AT91SAM9G45_IRQ_TC0_TC5
 216 #define AT91SAM9G45_IRQ_NAND    (-1)
 217
 218 #define AT91SAM9G45_AIC_BASE    0xffff000
 219 #define AT91SAM9G45_AIC_SIZE    0x200
 220
 221 /* Timer */
 222
 223 #define AT91SAM9G45_WDT_BASE    0xffffd40
 224 #define AT91SAM9G45_WDT_SIZE    0x10
 225
 226 #define AT91SAM9G45_PIT_BASE    0xffffd30
 227 #define AT91SAM9G45_PIT_SIZE    0x10
 228
 229 #define AT91SAM9G45_SMC_BASE    0xfffe800
 230 #define AT91SAM9G45_SMC_SIZE    0x200
 231
 232 #define AT91SAM9G45_HSMCI0_BASE 0xff80000
 233 #define AT91SAM9G45_HSMCI0_SIZE 0x4000
 234
 235 #define AT91SAM9G45_HSMCI1_BASE 0xffd0000
 236 #define AT91SAM9G45_HSMCI1_SIZE 0x4000
 237
 238 #define AT91SAM9G45_TWI0_BASE   0xff84000
 239 #define AT91SAM9G45_TWI0_SIZE   0x4000
 240 #define AT91SAM9G45_TWI1_BASE   0xff88000
 241 #define AT91SAM9G45_TWI1_SIZE   0x4000
 242
 243 /* XXX Needs to be carfully coordinated with
 244  * other * soc's so phyical and vm address
 245  * mapping are unique. XXX
 246  */
 247 #define AT91SAM9G45_OHCI_VA_BASE 0xdfb00000
 248 #define AT91SAM9G45_OHCI_BASE   0x00700000
 249 #define AT91SAM9G45_OHCI_SIZE   0x00100000
 250
 251 #define AT91SAM9G45_NAND_VA_BASE 0xe0000000
 252 #define AT91SAM9G45_NAND_BASE   0x40000000
 253 #define AT91SAM9G45_NAND_SIZE   0x10000000
 254
 255
 256 /* DDRSDRC */
 257 #define AT91SAM9G45_DDRSDRC1_BASE       0xfffea00
 258 #define AT91SAM9G45_DDRSDRC0_BASE       0xfffe600
 259 #define AT91SAM9G45_DDRSDRC_MR          0x00
 260 #define AT91SAM9G45_DDRSDRC_TR          0x04
 261 #define AT91SAM9G45_DDRSDRC_CR          0x08
 262 #define AT91SAM9G45_DDRSDRC_CR_NC_8     0x0
 263 #define AT91SAM9G45_DDRSDRC_CR_NC_9     0x1
 264 #define AT91SAM9G45_DDRSDRC_CR_NC_10    0x2
 265 #define AT91SAM9G45_DDRSDRC_CR_NC_11    0x3
 266 #define AT91SAM9G45_DDRSDRC_CR_NC_MASK  0x00000003
 267 #define AT91SAM9G45_DDRSDRC_CR_NR_11    0x0
 268 #define AT91SAM9G45_DDRSDRC_CR_NR_12    0x4
 269 #define AT91SAM9G45_DDRSDRC_CR_NR_13    0x8
 270 #define AT91SAM9G45_DDRSDRC_CR_NR_14    0xc
 271 #define AT91SAM9G45_DDRSDRC_CR_NR_MASK  0x0000000c
 272 #define AT91SAM9G45_DDRSDRC_TPR0        0x0c
 273 #define AT91SAM9G45_DDRSDRC_TPR1        0x10
 274 #define AT91SAM9G45_DDRSDRC_TPR2        0x14
 275 /* Reserved 0x18 */
 276 #define AT91SAM9G45_DDRSDRC_LPR         0x1c
 277 #define AT91SAM9G45_DDRSDRC_MDR         0x20
 278 #define AT91SAM9G45_DDRSDRC_MDR_SDR     0x0
 279 #define AT91SAM9G45_DDRSDRC_MDR_LPSDR   0x1
 280 #define AT91SAM9G45_DDRSDRC_MDR_LPDDR1  0x3
 281 #define AT91SAM9G45_DDRSDRC_MDR_DDR2    0x6
 282 #define AT91SAM9G45_DDRSDRC_MDR_MASK    0x00000007
 283 #define AT91SAM9G45_DDRSDRC_MDR_DBW_16  0x10
 284 #define AT91SAM9G45_DDRSDRC_DLL         0x24
 285 #define AT91SAM9G45_DDRSDRC_HSR         0x2c
 286 #define AT91SAM9G45_DDRSDRC_DELAY1R     0x40
 287 #define AT91SAM9G45_DDRSDRC_DELAY2R     0x44
 288 #define AT91SAM9G45_DDRSDRC_DELAY3R     0x48
 289 #define AT91SAM9G45_DDRSDRC_DELAY4R     0x4c
 290 /* Reserved 0x50 - 0xe0 */
 291 #define AT91SAM9G45_DDRSDRC_WPMR        0xe4
 292 #define AT91SAM9G45_DDRSDRC_WPSR        0xe8
 293
 294 #endif /* AT91SAM9G45REG_H_*/
 295