sys/arm/at91/at91sam9x5reg.h

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2009 Sylvestre Gallon.  All rights reserved.
   5  * Copyright (c) 2010 Greg Ansley.  All rights reserved.
   6  * Copyright (c) 2012 M. Warener Losh.  All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  */
  29
  30 /* $FreeBSD$ */
  31
  32 #ifndef AT91SAM9X5REG_H_
  33 #define AT91SAM9X5REG_H_
  34
  35 #ifndef AT91SAM9X25_MASTER_CLOCK
  36 #define AT91SAM9X25_MASTER_CLOCK ((18432000 * 43)/6)
  37 #endif
  38
  39 /* Chip Specific limits */
  40 #define SAM9X25_PLL_A_MIN_IN_FREQ         2000000 /*   2 Mhz */
  41 #define SAM9X25_PLL_A_MAX_IN_FREQ        32000000 /*  32 Mhz */
  42 #define SAM9X25_PLL_A_MIN_OUT_FREQ      400000000 /* 400 Mhz */
  43 #define SAM9X25_PLL_A_MAX_OUT_FREQ      800000000 /* 800 Mhz */
  44 #define SAM9X25_PLL_A_MUL_SHIFT 16
  45 #define SAM9X25_PLL_A_MUL_MASK 0xFF
  46 #define SAM9X25_PLL_A_DIV_SHIFT 0
  47 #define SAM9X25_PLL_A_DIV_MASK 0xFF
  48
  49 #define SAM9X25_PLL_B_MIN_IN_FREQ         2000000 /*   2 Mhz */
  50 #define SAM9X25_PLL_B_MAX_IN_FREQ        32000000 /*  32 Mhz */
  51 #define SAM9X25_PLL_B_MIN_OUT_FREQ       30000000 /*  30 Mhz */
  52 #define SAM9X25_PLL_B_MAX_OUT_FREQ      100000000 /* 100 Mhz */
  53 #define SAM9X25_PLL_B_MUL_SHIFT 16
  54 #define SAM9X25_PLL_B_MUL_MASK 0x3F
  55 #define SAM9X25_PLL_B_DIV_SHIFT 0
  56 #define SAM9X25_PLL_B_DIV_MASK 0xFF
  57
  58 /*
  59  * Memory map, from datasheet :
  60  * 0x00000000 - 0x0ffffffff : Internal Memories
  61  * 0x10000000 - 0x1ffffffff : Chip Select 0
  62  * 0x20000000 - 0x2ffffffff : Chip Select 1 DDR2/LPDDR/SDR/LPSDR
  63  * 0x30000000 - 0x3ffffffff : Chip Select 2
  64  * 0x40000000 - 0x4ffffffff : Chip Select 3 NAND Flash
  65  * 0x50000000 - 0x5ffffffff : Chip Select 4
  66  * 0x60000000 - 0x6ffffffff : Chip Select 5
  67  * 0x70000000 - 0xeffffffff : Undefined (Abort)
  68  * 0xf0000000 - 0xfffffffff : Peripherals
  69  */
  70
  71 #define AT91_CHIPSELECT_0 0x10000000
  72 #define AT91_CHIPSELECT_1 0x20000000
  73 #define AT91_CHIPSELECT_2 0x30000000
  74 #define AT91_CHIPSELECT_3 0x40000000
  75 #define AT91_CHIPSELECT_4 0x50000000
  76 #define AT91_CHIPSELECT_5 0x60000000
  77
  78 #define AT91SAM9X25_EMAC_SIZE  0x4000
  79 #define AT91SAM9X25_EMAC0_BASE 0x802c000
  80 #define AT91SAM9X25_EMAC0_SIZE AT91SAM9X25_EMAC_SIZE
  81 #define AT91SAM9X25_EMAC1_BASE 0x8030000
  82 #define AT91SAM9X25_EMAC1_SIZE AT91SAM9X25_EMAC_SIZE
  83
  84 #define AT91SAM9X25_RSTC_BASE   0xffffe00
  85 #define AT91SAM9X25_RSTC_SIZE   0x10
  86
  87 /* USART*/
  88
  89 #define AT91SAM9X25_USART_SIZE  0x4000
  90 #define AT91SAM9X25_USART0_BASE 0x801c000
  91 #define AT91SAM9X25_USART0_PDC  0x801c100
  92 #define AT91SAM9X25_USART0_SIZE AT91SAM9X25_USART_SIZE
  93 #define AT91SAM9X25_USART1_BASE 0x8020000
  94 #define AT91SAM9X25_USART1_PDC  0x8020100
  95 #define AT91SAM9X25_USART1_SIZE AT91SAM9X25_USART_SIZE
  96 #define AT91SAM9X25_USART2_BASE 0x8024000
  97 #define AT91SAM9X25_USART2_PDC  0x8024100
  98 #define AT91SAM9X25_USART2_SIZE AT91SAM9X25_USART_SIZE
  99 #define AT91SAM9X25_USART3_BASE 0x8028000
 100 #define AT91SAM9X25_USART3_PDC  0x8028100
 101 #define AT91SAM9X25_USART3_SIZE AT91SAM9X25_USART_SIZE
 102
 103 /*TC*/
 104 #define AT91SAM9X25_TC0_BASE    0x8008000
 105 #define AT91SAM9X25_TC0_SIZE    0x4000
 106 #define AT91SAM9X25_TC0C0_BASE  0x8008000
 107 #define AT91SAM9X25_TC0C1_BASE  0x8008040
 108 #define AT91SAM9X25_TC0C2_BASE  0x8008080
 109
 110 #define AT91SAM9X25_TC1_BASE    0x800c000
 111 #define AT91SAM9X25_TC1_SIZE    0x4000
 112
 113 /*SPI*/
 114
 115 #define AT91SAM9X25_SPI0_BASE   0x0000000
 116
 117 #define AT91SAM9X25_SPI0_SIZE   0x4000
 118
 119 #define AT91SAM9X25_SPI1_BASE   0x0004000
 120 #define AT91SAM9X25_SPI1_SIZE   0x4000
 121
 122 /* System Registers */
 123 #define AT91SAM9X25_SYS_BASE    0xffff000
 124 #define AT91SAM9X25_SYS_SIZE    0x1000
 125
 126 #define AT91SAM9X25_MATRIX_BASE 0xfffde00
 127 #define AT91SAM9X25_MATRIX_SIZE 0x200
 128
 129 #define AT91SAM9X25_DBGU_BASE   0xffff200
 130 #define AT91SAM9X25_DBGU_SIZE   0x200
 131
 132 /*
 133  * PIO
 134  */
 135 #define AT91SAM9X25_PIOA_BASE   0xffff400
 136 #define AT91SAM9X25_PIOA_SIZE   0x200
 137 #define AT91SAM9X25_PIOB_BASE   0xffff600
 138 #define AT91SAM9X25_PIOB_SIZE   0x200
 139 #define AT91SAM9X25_PIOC_BASE   0xffff800
 140 #define AT91SAM9X25_PIOC_SIZE   0x200
 141 #define AT91SAM9X25_PIOD_BASE   0xffffa00
 142 #define AT91SAM9X25_PIOD_SIZE   0x200
 143
 144 #define AT91RM92_PMC_BASE       0xffffc00
 145 #define AT91RM92_PMC_SIZE       0x100
 146 /* IRQs :
 147  * 0: AIC
 148  * 1: System peripheral (System timer, RTC, DBGU)
 149  * 2: PIO Controller A,B
 150  * 3: PIO Controller C,D
 151  * 4: SMD Soft Modem
 152  * 5: USART 0
 153  * 6: USART 1
 154  * 7: USART 2
 155  * 8: USART 3
 156  * 9: Two-wire interface
 157  * 10: Two-wire interface
 158  * 11: Two-wire interface
 159  * 12: HSMCI Interface
 160  * 13: SPI 0
 161  * 14: SPI 1
 162  * 15: UART0
 163  * 16: UART1
 164  * 17: Timer Counter 0,1
 165  * 18: PWM
 166  * 19: ADC
 167  * 20: DMAC 0
 168  * 21: DMAC 1
 169  * 22: UHPHS - USB Host controller
 170  * 23: UDPHS - USB Device Controller
 171  * 24: EMAC0
 172  * 25: LCD controller or Image Sensor Interface
 173  * 26: HSMCI1
 174  * 27: EMAC1
 175  * 28: SSC
 176  * 29: CAN0
 177  * 30: CAN1
 178  * 31: AIC IRQ0
 179  */
 180
 181 #define AT91SAM9X25_IRQ_AIC     0
 182 #define AT91SAM9X25_IRQ_SYSTEM  1
 183 #define AT91SAM9X25_IRQ_PIOAB   2
 184 #define AT91SAM9X25_IRQ_PIOCD   3
 185 #define AT91SAM9X25_IRQ_SMD     4
 186 #define AT91SAM9X25_IRQ_USART0  5
 187 #define AT91SAM9X25_IRQ_USART1  6
 188 #define AT91SAM9X25_IRQ_USART2  7
 189 #define AT91SAM9X25_IRQ_USART3  8
 190 #define AT91SAM9X25_IRQ_TWI0    9
 191 #define AT91SAM9X25_IRQ_TWI1    10
 192 #define AT91SAM9X25_IRQ_TWI2    11
 193 #define AT91SAM9X25_IRQ_HSMCI0  12
 194 #define AT91SAM9X25_IRQ_SPI0    13
 195 #define AT91SAM9X25_IRQ_SPI1    14
 196 #define AT91SAM9X25_IRQ_UART0   15
 197 #define AT91SAM9X25_IRQ_UART1   16
 198 #define AT91SAM9X25_IRQ_TC01    17
 199 #define AT91SAM9X25_IRQ_PWM     18
 200 #define AT91SAM9X25_IRQ_ADC     19
 201 #define AT91SAM9X25_IRQ_DMAC0   20
 202 #define AT91SAM9X25_IRQ_DMAC1   21
 203 #define AT91SAM9X25_IRQ_UHPHS   22
 204 #define AT91SAM9X25_IRQ_UDPHS   23
 205 #define AT91SAM9X25_IRQ_EMAC0   24
 206 #define AT91SAM9X25_IRQ_HSMCI1  26
 207 #define AT91SAM9X25_IRQ_EMAC1   27
 208 #define AT91SAM9X25_IRQ_SSC     28
 209 #define AT91SAM9X25_IRQ_CAN0    29
 210 #define AT91SAM9X25_IRQ_CAN1    30
 211 #define AT91SAM9X25_IRQ_AICBASE 31
 212
 213 /* Alias */
 214 #define AT91SAM9X25_IRQ_DBGU    AT91SAM9X25_IRQ_SYSTEM
 215 #define AT91SAM9X25_IRQ_PMC     AT91SAM9X25_IRQ_SYSTEM
 216 #define AT91SAM9X25_IRQ_WDT     AT91SAM9X25_IRQ_SYSTEM
 217 #define AT91SAM9X25_IRQ_PIT     AT91SAM9X25_IRQ_SYSTEM
 218 #define AT91SAM9X25_IRQ_RSTC    AT91SAM9X25_IRQ_SYSTEM
 219 #define AT91SAM9X25_IRQ_OHCI    AT91SAM9X25_IRQ_UHPHS
 220 #define AT91SAM9X25_IRQ_EHCI    AT91SAM9X25_IRQ_UHPHS
 221 #define AT91SAM9X25_IRQ_PIOA    AT91SAM9X25_IRQ_PIOAB
 222 #define AT91SAM9X25_IRQ_PIOB    AT91SAM9X25_IRQ_PIOAB
 223 #define AT91SAM9X25_IRQ_PIOC    AT91SAM9X25_IRQ_PIOCD
 224 #define AT91SAM9X25_IRQ_PIOD    AT91SAM9X25_IRQ_PIOCD
 225 #define AT91SAM9X25_IRQ_NAND    (-1)
 226
 227 #define AT91SAM9X25_AIC_BASE    0xffff000
 228 #define AT91SAM9X25_AIC_SIZE    0x200
 229
 230 /* Timer */
 231
 232 #define AT91SAM9X25_WDT_BASE    0xffffd40
 233 #define AT91SAM9X25_WDT_SIZE    0x10
 234
 235 #define AT91SAM9X25_PIT_BASE    0xffffd30
 236 #define AT91SAM9X25_PIT_SIZE    0x10
 237
 238 #define AT91SAM9X25_SMC_BASE    0xfffea00
 239 #define AT91SAM9X25_SMC_SIZE    0x200
 240
 241 #define AT91SAM9X25_PMC_BASE    0xffffc00
 242 #define AT91SAM9X25_PMC_SIZE    0x100
 243
 244 #define AT91SAM9X25_UDPHS_BASE  0x803c000
 245 #define AT91SAM9X25_UDPHS_SIZE  0x4000
 246
 247 #define AT91SAM9X25_HSMCI_SIZE  0x4000
 248 #define AT91SAM9X25_HSMCI0_BASE 0x0008000
 249 #define AT91SAM9X25_HSMCI0_SIZE AT91SAM9X25_HSMCI_SIZE
 250 #define AT91SAM9X25_HSMCI1_BASE 0x000c000
 251 #define AT91SAM9X25_HSMCI1_SIZE AT91SAM9X25_HSMCI_SIZE
 252
 253 #define AT91SAM9X25_TWI_SIZE    0x4000
 254 #define AT91SAM9X25_TWI0_BASE   0xffaC000
 255 #define AT91SAM9X25_TWI0_SIZE   AT91SAM9X25_TWI_SIZE
 256 #define AT91SAM9X25_TWI1_BASE   0xffaC000
 257 #define AT91SAM9X25_TWI1_SIZE   AT91SAM9X25_TWI_SIZE
 258 #define AT91SAM9X25_TWI2_BASE   0xffaC000
 259 #define AT91SAM9X25_TWI2_SIZE   AT91SAM9X25_TWI_SIZE
 260
 261 /* XXX Needs to be carfully coordinated with
 262  * other * soc's so phyical and vm address
 263  * mapping are unique. XXX
 264  */
 265 #define AT91SAM9X25_OHCI_BASE     0xdfc00000 /* SAME as 9c40 */
 266 #define AT91SAM9X25_OHCI_PA_BASE  0x00600000
 267 #define AT91SAM9X25_OHCI_SIZE     0x00100000
 268
 269 #define AT91SAM9X25_EHCI_BASE     0xdfd00000
 270 #define AT91SAM9X25_EHCI_PA_BASE  0x00700000
 271 #define AT91SAM9X25_EHCI_SIZE     0x00100000
 272
 273 #define AT91SAM9X25_NAND_BASE     0xe0000000
 274 #define AT91SAM9X25_NAND_PA_BASE  0x40000000
 275 #define AT91SAM9X25_NAND_SIZE     0x10000000
 276
 277
 278 /* SDRAMC */
 279 #define AT91SAM9X25_SDRAMC_BASE 0xfffea00               /* SAME as SMC? */
 280 #define AT91SAM9X25_SDRAMC_MR   0x00
 281 #define AT91SAM9X25_SDRAMC_MR_MODE_NORMAL       0
 282 #define AT91SAM9X25_SDRAMC_MR_MODE_NOP  1
 283 #define AT91SAM9X25_SDRAMC_MR_MODE_PRECHARGE 2
 284 #define AT91SAM9X25_SDRAMC_MR_MODE_LOAD_MODE_REGISTER 3
 285 #define AT91SAM9X25_SDRAMC_MR_MODE_REFRESH      4
 286 #define AT91SAM9X25_SDRAMC_TR   0x04
 287 #define AT91SAM9X25_SDRAMC_CR   0x08
 288 #define AT91SAM9X25_SDRAMC_CR_NC_8              0x0
 289 #define AT91SAM9X25_SDRAMC_CR_NC_9              0x1
 290 #define AT91SAM9X25_SDRAMC_CR_NC_10     0x2
 291 #define AT91SAM9X25_SDRAMC_CR_NC_11     0x3
 292 #define AT91SAM9X25_SDRAMC_CR_NC_MASK   0x00000003
 293 #define AT91SAM9X25_SDRAMC_CR_NR_11     0x0
 294 #define AT91SAM9X25_SDRAMC_CR_NR_12     0x4
 295 #define AT91SAM9X25_SDRAMC_CR_NR_13     0x8
 296 #define AT91SAM9X25_SDRAMC_CR_NR_RES    0xc
 297 #define AT91SAM9X25_SDRAMC_CR_NR_MASK   0x0000000c
 298 #define AT91SAM9X25_SDRAMC_CR_NB_2              0x00
 299 #define AT91SAM9X25_SDRAMC_CR_NB_4              0x10
 300 #define AT91SAM9X25_SDRAMC_CR_DBW_16            0x80
 301 #define AT91SAM9X25_SDRAMC_CR_NB_MASK   0x00000010
 302 #define AT91SAM9X25_SDRAMC_CR_NCAS_MASK 0x00000060
 303 #define AT91SAM9X25_SDRAMC_CR_TWR_MASK  0x00000780
 304 #define AT91SAM9X25_SDRAMC_CR_TRC_MASK  0x00007800
 305 #define AT91SAM9X25_SDRAMC_CR_TRP_MASK  0x00078000
 306 #define AT91SAM9X25_SDRAMC_CR_TRCD_MASK 0x00780000
 307 #define AT91SAM9X25_SDRAMC_CR_TRAS_MASK 0x07800000
 308 #define AT91SAM9X25_SDRAMC_CR_TXSR_MASK 0x78000000
 309 #define AT91SAM9X25_SDRAMC_HSR  0x0c
 310 #define AT91SAM9X25_SDRAMC_LPR  0x10
 311 #define AT91SAM9X25_SDRAMC_IER  0x14
 312 #define AT91SAM9X25_SDRAMC_IDR  0x18
 313 #define AT91SAM9X25_SDRAMC_IMR  0x1c
 314 #define AT91SAM9X25_SDRAMC_ISR  0x20
 315 #define AT91SAM9X25_SDRAMC_MDR  0x24
 316
 317 #endif /* AT91SAM9X5REG_H_*/