2 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * 1) Turn on the clock in pmc? Turn off?
29 * 2) GPIO initializtion in board setup code.
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/kernel.h>
40 #include <sys/malloc.h>
41 #include <sys/module.h>
43 #include <sys/socket.h>
44 #include <sys/sockio.h>
45 #include <sys/sysctl.h>
46 #include <machine/bus.h>
48 #include <net/ethernet.h>
50 #include <net/if_arp.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
53 #include <net/if_mib.h>
54 #include <net/if_types.h>
57 #include <netinet/in.h>
58 #include <netinet/in_systm.h>
59 #include <netinet/in_var.h>
60 #include <netinet/ip.h>
64 #include <net/bpfdesc.h>
66 #include <dev/mii/mii.h>
67 #include <dev/mii/miivar.h>
68 #include <arm/at91/if_atereg.h>
70 #include "miibus_if.h"
72 #define ATE_MAX_TX_BUFFERS 2 /* We have ping-pong tx buffers */
73 #define ATE_MAX_RX_BUFFERS 64
76 * Driver-specific flags.
78 #define ATE_FLAG_DETACHING 0x01
79 #define ATE_FLAG_MULTICAST 0x02
83 struct ifnet *ifp; /* ifnet pointer */
84 struct mtx sc_mtx; /* Basically a perimeter lock */
85 device_t dev; /* Myself */
86 device_t miibus; /* My child miibus */
87 struct resource *irq_res; /* IRQ resource */
88 struct resource *mem_res; /* Memory resource */
89 struct callout tick_ch; /* Tick callout */
90 struct ifmib_iso_8802_3 mibdata; /* Stuff for network mgmt */
91 struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */
92 bus_dma_tag_t mtag; /* bus dma tag for mbufs */
94 bus_dma_tag_t rx_desc_tag;
95 bus_dmamap_t rx_desc_map;
96 bus_dmamap_t rx_map[ATE_MAX_RX_BUFFERS];
97 bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS];
98 bus_addr_t rx_desc_phys;
99 eth_rx_desc_t *rx_descs;
100 void *rx_buf[ATE_MAX_RX_BUFFERS]; /* RX buffer space */
101 void *intrhand; /* Interrupt handle */
105 int txcur; /* Current TX map pointer */
109 static inline uint32_t
110 RD4(struct ate_softc *sc, bus_size_t off)
113 return (bus_read_4(sc->mem_res, off));
117 WR4(struct ate_softc *sc, bus_size_t off, uint32_t val)
120 bus_write_4(sc->mem_res, off, val);
124 BARRIER(struct ate_softc *sc, bus_size_t off, bus_size_t len, int flags)
127 bus_barrier(sc->mem_res, off, len, flags);
130 #define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
131 #define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
132 #define ATE_LOCK_INIT(_sc) \
133 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
134 MTX_NETWORK_LOCK, MTX_DEF)
135 #define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
136 #define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
137 #define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
139 static devclass_t ate_devclass;
142 * ifnet entry points.
144 static void ateinit_locked(void *);
145 static void atestart_locked(struct ifnet *);
147 static void ateinit(void *);
148 static void atestart(struct ifnet *);
149 static void atestop(struct ate_softc *);
150 static int ateioctl(struct ifnet * ifp, u_long, caddr_t);
155 static int ate_probe(device_t dev);
156 static int ate_attach(device_t dev);
157 static int ate_detach(device_t dev);
158 static void ate_intr(void *);
163 static int ate_activate(device_t dev);
164 static void ate_deactivate(struct ate_softc *sc);
165 static int ate_ifmedia_upd(struct ifnet *ifp);
166 static void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
167 static int ate_get_mac(struct ate_softc *sc, u_char *eaddr);
168 static void ate_set_mac(struct ate_softc *sc, u_char *eaddr);
169 static void ate_rxfilter(struct ate_softc *sc);
172 * The AT91 family of products has the ethernet called EMAC. However,
173 * it isn't self identifying. It is anticipated that the parent bus
174 * code will take care to only add ate devices where they really are. As
175 * such, we do nothing here to identify the device and just set its name.
178 ate_probe(device_t dev)
181 device_set_desc(dev, "EMAC");
186 ate_attach(device_t dev)
188 struct ate_softc *sc;
189 struct ifnet *ifp = NULL;
190 struct sysctl_ctx_list *sctx;
191 struct sysctl_oid *soid;
192 u_char eaddr[ETHER_ADDR_LEN];
196 sc = device_get_softc(dev);
201 * Allocate resources.
204 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
206 if (sc->mem_res == NULL) {
207 device_printf(dev, "could not allocate memory resources.\n");
212 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
214 if (sc->irq_res == NULL) {
215 device_printf(dev, "could not allocate interrupt resources.\n");
220 err = ate_activate(dev);
224 sc->use_rmii = (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII;
227 sctx = device_get_sysctl_ctx(dev);
228 soid = device_get_sysctl_tree(dev);
229 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "rmii",
230 CTLFLAG_RD, &sc->use_rmii, 0, "rmii in use");
232 /* Calling atestop before ifp is set is OK. */
236 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0);
238 if ((err = ate_get_mac(sc, eaddr)) != 0) {
240 * No MAC address configured. Generate the random one.
244 "Generating random ethernet address.\n");
248 * Set OUI to convenient locally assigned address. 'b'
249 * is 0x62, which has the locally assigned bit set, and
250 * the broadcast/multicast bit clear.
255 eaddr[3] = (rnd >> 16) & 0xff;
256 eaddr[4] = (rnd >> 8) & 0xff;
257 eaddr[5] = rnd & 0xff;
260 sc->ifp = ifp = if_alloc(IFT_ETHER);
261 err = mii_attach(dev, &sc->miibus, ifp, ate_ifmedia_upd,
262 ate_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
264 device_printf(dev, "attaching PHYs failed\n");
269 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
270 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
271 ifp->if_capabilities |= IFCAP_VLAN_MTU;
272 ifp->if_capenable |= IFCAP_VLAN_MTU; /* The hw bits already set. */
273 ifp->if_start = atestart;
274 ifp->if_ioctl = ateioctl;
275 ifp->if_init = ateinit;
276 ifp->if_baudrate = 10000000;
277 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
278 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
279 IFQ_SET_READY(&ifp->if_snd);
281 ifp->if_linkmib = &sc->mibdata;
282 ifp->if_linkmiblen = sizeof(sc->mibdata);
283 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
284 sc->if_flags = ifp->if_flags;
286 ether_ifattach(ifp, eaddr);
289 * Activate the interrupt.
291 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE,
292 NULL, ate_intr, sc, &sc->intrhand);
294 device_printf(dev, "could not establish interrupt handler.\n");
306 ate_detach(device_t dev)
308 struct ate_softc *sc;
311 sc = device_get_softc(dev);
312 KASSERT(sc != NULL, ("[ate: %d]: sc is NULL", __LINE__));
314 if (device_is_attached(dev)) {
316 sc->flags |= ATE_FLAG_DETACHING;
319 callout_drain(&sc->tick_ch);
322 if (sc->miibus != NULL) {
323 device_delete_child(dev, sc->miibus);
326 bus_generic_detach(sc->dev);
328 if (sc->intrhand != NULL) {
329 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
336 if (sc->mem_res != NULL) {
337 bus_release_resource(dev, SYS_RES_IOPORT,
338 rman_get_rid(sc->mem_res), sc->mem_res);
341 if (sc->irq_res != NULL) {
342 bus_release_resource(dev, SYS_RES_IRQ,
343 rman_get_rid(sc->irq_res), sc->irq_res);
346 ATE_LOCK_DESTROY(sc);
351 ate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
353 struct ate_softc *sc;
357 sc = (struct ate_softc *)arg;
358 sc->rx_desc_phys = segs[0].ds_addr;
362 ate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
364 struct ate_softc *sc;
369 sc = (struct ate_softc *)arg;
373 * For the last buffer, set the wrap bit so the controller
374 * restarts from the first descriptor.
376 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE);
377 if (i == ATE_MAX_RX_BUFFERS - 1)
378 sc->rx_descs[i].addr = segs[0].ds_addr | ETH_WRAP_BIT;
380 sc->rx_descs[i].addr = segs[0].ds_addr;
381 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_POSTWRITE);
382 sc->rx_descs[i].status = 0;
383 /* Flush the memory in the mbuf */
384 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], BUS_DMASYNC_PREREAD);
388 ate_mac_hash(const uint8_t *buf)
391 for (int i = 0; i < 48; i++) {
392 index ^= ((buf[i >> 3] >> (i & 7)) & 1) << (i % 6);
398 * Compute the multicast filter for this device using the standard
399 * algorithm. I wonder why this isn't in ether somewhere as a lot
400 * of different MAC chips use this method (or the reverse the bits)
404 ate_setmcast(struct ate_softc *sc)
408 u_char *af = (u_char *) mcaf;
409 struct ifmultiaddr *ifma;
414 if ((ifp->if_flags & IFF_PROMISC) != 0)
416 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
417 WR4(sc, ETH_HSL, 0xffffffff);
418 WR4(sc, ETH_HSH, 0xffffffff);
423 * Compute the multicast hash.
428 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
429 if (ifma->ifma_addr->sa_family != AF_LINK)
431 index = ate_mac_hash(LLADDR((struct sockaddr_dl *)
433 af[index >> 3] |= 1 << (index & 7);
435 if_maddr_runlock(ifp);
438 * Write the hash to the hash register. This card can also
439 * accept unicast packets as well as multicast packets using this
440 * register for easier bridging operations, but we don't take
441 * advantage of that. Locks here are to avoid LOR with the
442 * if_maddr_rlock, but might not be strictly necessary.
444 WR4(sc, ETH_HSL, mcaf[0]);
445 WR4(sc, ETH_HSH, mcaf[1]);
446 return (mcaf[0] || mcaf[1]);
450 ate_activate(device_t dev)
452 struct ate_softc *sc;
455 sc = device_get_softc(dev);
458 * Allocate DMA tags and maps.
460 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
461 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
462 1, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, &sc->mtag);
465 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) {
466 err = bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i]);
472 * Allocate DMA tags and maps for RX.
474 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
475 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
476 1, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, &sc->rxtag);
481 * DMA tag and map for the RX descriptors.
483 err = bus_dma_tag_create(bus_get_dma_tag(dev), sizeof(eth_rx_desc_t),
484 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
485 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 1,
486 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex,
487 &sc->sc_mtx, &sc->rx_desc_tag);
490 if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs,
491 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rx_desc_map) != 0)
493 if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map,
494 sc->rx_descs, ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t),
495 ate_getaddr, sc, 0) != 0)
499 * Allocate our RX buffers. This chip has a RX structure that's filled
502 for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) {
504 if (bus_dmamem_alloc(sc->rxtag, (void **)&sc->rx_buf[i],
505 BUS_DMA_NOWAIT, &sc->rx_map[i]) != 0)
507 if (bus_dmamap_load(sc->rxtag, sc->rx_map[i], sc->rx_buf[i],
508 MCLBYTES, ate_load_rx_buf, sc, 0) != 0)
512 /* Flush the memory for the EMAC rx descriptor. */
513 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE);
514 /* Write the descriptor queue address. */
515 WR4(sc, ETH_RBQP, sc->rx_desc_phys);
523 ate_deactivate(struct ate_softc *sc)
527 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__));
528 if (sc->mtag != NULL) {
529 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) {
530 if (sc->sent_mbuf[i] != NULL) {
531 bus_dmamap_sync(sc->mtag, sc->tx_map[i],
532 BUS_DMASYNC_POSTWRITE);
533 bus_dmamap_unload(sc->mtag, sc->tx_map[i]);
534 m_freem(sc->sent_mbuf[i]);
536 bus_dmamap_destroy(sc->mtag, sc->tx_map[i]);
537 sc->sent_mbuf[i] = NULL;
538 sc->tx_map[i] = NULL;
540 bus_dma_tag_destroy(sc->mtag);
542 if (sc->rx_desc_tag != NULL) {
543 if (sc->rx_descs != NULL) {
544 if (sc->rx_desc_phys != 0) {
545 bus_dmamap_sync(sc->rx_desc_tag,
546 sc->rx_desc_map, BUS_DMASYNC_POSTREAD);
547 bus_dmamap_unload(sc->rx_desc_tag,
549 sc->rx_desc_phys = 0;
553 if (sc->rxtag != NULL) {
554 for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) {
555 if (sc->rx_buf[i] != NULL) {
556 if (sc->rx_descs[i].addr != 0) {
557 bus_dmamap_sync(sc->rxtag,
559 BUS_DMASYNC_POSTREAD);
560 bus_dmamap_unload(sc->rxtag,
562 sc->rx_descs[i].addr = 0;
564 bus_dmamem_free(sc->rxtag, sc->rx_buf[i],
566 sc->rx_buf[i] = NULL;
567 sc->rx_map[i] = NULL;
570 bus_dma_tag_destroy(sc->rxtag);
572 if (sc->rx_desc_tag != NULL) {
573 if (sc->rx_descs != NULL)
574 bus_dmamem_free(sc->rx_desc_tag, sc->rx_descs,
576 bus_dma_tag_destroy(sc->rx_desc_tag);
578 sc->rx_desc_tag = NULL;
583 * Change media according to request.
586 ate_ifmedia_upd(struct ifnet *ifp)
588 struct ate_softc *sc = ifp->if_softc;
589 struct mii_data *mii;
591 mii = device_get_softc(sc->miibus);
599 * Notify the world which media we're using.
602 ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
604 struct ate_softc *sc = ifp->if_softc;
605 struct mii_data *mii;
607 mii = device_get_softc(sc->miibus);
610 ifmr->ifm_active = mii->mii_media_active;
611 ifmr->ifm_status = mii->mii_media_status;
616 ate_stat_update(struct ate_softc *sc, int active)
621 * The speed and full/half-duplex state needs to be reflected
622 * in the ETH_CFG register.
624 reg = RD4(sc, ETH_CFG);
625 reg &= ~(ETH_CFG_SPD | ETH_CFG_FD);
626 if (IFM_SUBTYPE(active) != IFM_10_T)
628 if (active & IFM_FDX)
630 WR4(sc, ETH_CFG, reg);
636 struct ate_softc *sc = xsc;
637 struct ifnet *ifp = sc->ifp;
638 struct mii_data *mii;
643 * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask
644 * the MII if there's a link if this bit is clear. Not sure if we
645 * should do the same thing here or not.
647 ATE_ASSERT_LOCKED(sc);
648 if (sc->miibus != NULL) {
649 mii = device_get_softc(sc->miibus);
650 active = mii->mii_media_active;
652 if (mii->mii_media_status & IFM_ACTIVE &&
653 active != mii->mii_media_active)
654 ate_stat_update(sc, mii->mii_media_active);
658 * Update the stats as best we can. When we're done, clear
659 * the status counters and start over. We're supposed to read these
660 * registers often enough that they won't overflow. Hopefully
661 * once a second is often enough. Some don't map well to
662 * the dot3Stats mib, so for those we just count them as general
663 * errors. Stats for iframes, ibutes, oframes and obytes are
664 * collected elsewhere. These registers zero on a read to prevent
665 * races. For all the collision stats, also update the collision
666 * stats for the interface.
668 sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE);
669 sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE);
670 c = RD4(sc, ETH_SCOL);
671 ifp->if_collisions += c;
672 sc->mibdata.dot3StatsSingleCollisionFrames += c;
673 c = RD4(sc, ETH_MCOL);
674 sc->mibdata.dot3StatsMultipleCollisionFrames += c;
675 ifp->if_collisions += c;
676 sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE);
677 sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE);
678 c = RD4(sc, ETH_LCOL);
679 sc->mibdata.dot3StatsLateCollisions += c;
680 ifp->if_collisions += c;
681 c = RD4(sc, ETH_ECOL);
682 sc->mibdata.dot3StatsExcessiveCollisions += c;
683 ifp->if_collisions += c;
684 sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE);
685 sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR);
686 sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC);
689 * Not sure where to lump these, so count them against the errors
692 sc->ifp->if_oerrors += RD4(sc, ETH_TUE);
693 sc->ifp->if_ierrors += RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) +
697 * Schedule another timeout one second from now.
699 callout_reset(&sc->tick_ch, hz, ate_tick, sc);
703 ate_set_mac(struct ate_softc *sc, u_char *eaddr)
706 WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) |
707 (eaddr[1] << 8) | eaddr[0]);
708 WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4]));
712 ate_get_mac(struct ate_softc *sc, u_char *eaddr)
714 bus_size_t sa_low_reg[] = { ETH_SA1L, ETH_SA2L, ETH_SA3L, ETH_SA4L };
715 bus_size_t sa_high_reg[] = { ETH_SA1H, ETH_SA2H, ETH_SA3H, ETH_SA4H };
720 * The boot loader setup the MAC with an address, if one is set in
721 * the loader. Grab one MAC address from the SA[1-4][HL] registers.
723 for (i = 0; i < 4; i++) {
724 low = RD4(sc, sa_low_reg[i]);
725 high = RD4(sc, sa_high_reg[i]);
726 if ((low | (high & 0xffff)) != 0) {
727 eaddr[0] = low & 0xff;
728 eaddr[1] = (low >> 8) & 0xff;
729 eaddr[2] = (low >> 16) & 0xff;
730 eaddr[3] = (low >> 24) & 0xff;
731 eaddr[4] = high & 0xff;
732 eaddr[5] = (high >> 8) & 0xff;
742 struct ate_softc *sc = xsc;
743 struct ifnet *ifp = sc->ifp;
746 uint32_t status, reg, rx_stat;
749 status = RD4(sc, ETH_ISR);
752 if (status & ETH_ISR_RCOM) {
753 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map,
754 BUS_DMASYNC_POSTREAD);
755 while (sc->rx_descs[sc->rx_buf_ptr].addr & ETH_CPU_OWNER) {
757 sc->rx_buf_ptr = (i + 1) % ATE_MAX_RX_BUFFERS;
759 rx_stat = sc->rx_descs[i].status;
760 if ((rx_stat & ETH_LEN_MASK) == 0) {
762 device_printf(sc->dev, "ignoring bogus zero-length packet\n");
763 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map,
764 BUS_DMASYNC_PREWRITE);
765 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER;
766 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map,
767 BUS_DMASYNC_POSTWRITE);
770 /* Flush memory for mbuf so we don't get stale bytes */
771 bus_dmamap_sync(sc->rxtag, sc->rx_map[i],
772 BUS_DMASYNC_POSTREAD);
773 WR4(sc, ETH_RSR, RD4(sc, ETH_RSR));
776 * The length returned by the device includes the
777 * ethernet CRC calculation for the packet, but
778 * ifnet drivers are supposed to discard it.
780 mb = m_devget(sc->rx_buf[i],
781 (rx_stat & ETH_LEN_MASK) - ETHER_CRC_LEN,
782 ETHER_ALIGN, ifp, NULL);
783 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map,
784 BUS_DMASYNC_PREWRITE);
785 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER;
786 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map,
787 BUS_DMASYNC_POSTWRITE);
788 bus_dmamap_sync(sc->rxtag, sc->rx_map[i],
789 BUS_DMASYNC_PREREAD);
792 (*ifp->if_input)(ifp, mb);
797 if (status & ETH_ISR_TCOM) {
799 /* XXX TSR register should be cleared */
800 if (sc->sent_mbuf[0]) {
801 bus_dmamap_sync(sc->mtag, sc->tx_map[0],
802 BUS_DMASYNC_POSTWRITE);
803 bus_dmamap_unload(sc->mtag, sc->tx_map[0]);
804 m_freem(sc->sent_mbuf[0]);
806 sc->sent_mbuf[0] = NULL;
808 if (sc->sent_mbuf[1]) {
809 if (RD4(sc, ETH_TSR) & ETH_TSR_IDLE) {
810 bus_dmamap_sync(sc->mtag, sc->tx_map[1],
811 BUS_DMASYNC_POSTWRITE);
812 bus_dmamap_unload(sc->mtag, sc->tx_map[1]);
813 m_freem(sc->sent_mbuf[1]);
816 sc->sent_mbuf[0] = sc->sent_mbuf[1] = NULL;
818 sc->sent_mbuf[0] = sc->sent_mbuf[1];
819 sc->sent_mbuf[1] = NULL;
823 sc->sent_mbuf[0] = NULL;
827 * We're no longer busy, so clear the busy flag and call the
828 * start routine to xmit more packets.
830 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
831 atestart_locked(sc->ifp);
834 if (status & ETH_ISR_RBNA) {
835 /* Workaround Errata #11 */
837 device_printf(sc->dev, "RBNA workaround\n");
838 reg = RD4(sc, ETH_CTL);
839 WR4(sc, ETH_CTL, reg & ~ETH_CTL_RE);
840 BARRIER(sc, ETH_CTL, 4, BUS_SPACE_BARRIER_WRITE);
841 WR4(sc, ETH_CTL, reg | ETH_CTL_RE);
846 * Reset and initialize the chip.
849 ateinit_locked(void *xsc)
851 struct ate_softc *sc = xsc;
852 struct ifnet *ifp = sc->ifp;
853 struct mii_data *mii;
854 uint8_t eaddr[ETHER_ADDR_LEN];
857 ATE_ASSERT_LOCKED(sc);
861 * we need to turn on the EMAC clock in the pmc. With the
862 * default boot loader, this is already turned on. However, we
863 * need to think about how best to turn it on/off as the interface
864 * is brought up/down, as well as dealing with the mii bus...
866 * We also need to multiplex the pins correctly.
870 * There are two different ways that the mii bus is connected
871 * to this chip. Select the right one based on a compile-time
874 reg = RD4(sc, ETH_CFG);
878 reg &= ~ETH_CFG_RMII;
879 WR4(sc, ETH_CFG, reg);
884 * Set the chip MAC address.
886 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
887 ate_set_mac(sc, eaddr);
890 * Turn on MACs and interrupt processing.
892 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE);
893 WR4(sc, ETH_IER, ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA);
895 /* Enable big packets. */
896 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG);
899 * Set 'running' flag, and clear output active flag
900 * and attempt to start the output.
902 ifp->if_drv_flags |= IFF_DRV_RUNNING;
903 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
905 mii = device_get_softc(sc->miibus);
907 ate_stat_update(sc, mii->mii_media_active);
908 atestart_locked(ifp);
910 callout_reset(&sc->tick_ch, hz, ate_tick, sc);
914 * Dequeue packets and transmit.
917 atestart_locked(struct ifnet *ifp)
919 struct ate_softc *sc = ifp->if_softc;
920 struct mbuf *m, *mdefrag;
921 bus_dma_segment_t segs[1];
924 ATE_ASSERT_LOCKED(sc);
925 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
928 while (sc->txcur < ATE_MAX_TX_BUFFERS) {
930 * Check to see if there's room to put another packet into the
931 * xmit queue. The EMAC chip has a ping-pong buffer for xmit
932 * packets. We use OACTIVE to indicate "we can stuff more into
933 * our buffers (clear) or not (set)."
935 if (!(RD4(sc, ETH_TSR) & ETH_TSR_BNQ)) {
936 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
939 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
941 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
944 e = bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txcur], m,
947 mdefrag = m_defrag(m, M_DONTWAIT);
948 if (mdefrag == NULL) {
949 IFQ_DRV_PREPEND(&ifp->if_snd, m);
953 e = bus_dmamap_load_mbuf_sg(sc->mtag,
954 sc->tx_map[sc->txcur], m, segs, &nseg, 0);
960 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txcur],
961 BUS_DMASYNC_PREWRITE);
964 * Tell the hardware to xmit the packet.
966 WR4(sc, ETH_TAR, segs[0].ds_addr);
967 BARRIER(sc, ETH_TAR, 8, BUS_SPACE_BARRIER_WRITE);
968 WR4(sc, ETH_TCR, segs[0].ds_len);
971 * Tap off here if there is a bpf listener.
975 sc->sent_mbuf[sc->txcur] = m;
983 struct ate_softc *sc = xsc;
991 atestart(struct ifnet *ifp)
993 struct ate_softc *sc = ifp->if_softc;
996 atestart_locked(ifp);
1001 * Turn off interrupts, and stop the NIC. Can be called with sc->ifp NULL,
1005 atestop(struct ate_softc *sc)
1010 ATE_ASSERT_LOCKED(sc);
1014 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1017 callout_stop(&sc->tick_ch);
1020 * Enable some parts of the MAC that are needed always (like the
1021 * MII bus. This turns off the RE and TE bits, which will remain
1022 * off until ateinit() is called to turn them on. With RE and TE
1023 * turned off, there's no DMA to worry about after this write.
1025 WR4(sc, ETH_CTL, ETH_CTL_MPE);
1028 * Turn off all the configured options and revert to defaults.
1030 WR4(sc, ETH_CFG, ETH_CFG_CLK_32);
1033 * Turn off all the interrupts, and ack any pending ones by reading
1036 WR4(sc, ETH_IDR, 0xffffffff);
1040 * Clear out the Transmit and Receiver Status registers of any
1041 * errors they may be reporting
1043 WR4(sc, ETH_TSR, 0xffffffff);
1044 WR4(sc, ETH_RSR, 0xffffffff);
1047 * Release TX resources.
1049 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) {
1050 if (sc->sent_mbuf[i] != NULL) {
1051 bus_dmamap_sync(sc->mtag, sc->tx_map[i],
1052 BUS_DMASYNC_POSTWRITE);
1053 bus_dmamap_unload(sc->mtag, sc->tx_map[i]);
1054 m_freem(sc->sent_mbuf[i]);
1055 sc->sent_mbuf[i] = NULL;
1060 * XXX we should power down the EMAC if it isn't in use, after
1061 * putting it into loopback mode. This saves about 400uA according
1067 ate_rxfilter(struct ate_softc *sc)
1073 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__));
1074 ATE_ASSERT_LOCKED(sc);
1078 * Wipe out old filter settings.
1080 reg = RD4(sc, ETH_CFG);
1081 reg &= ~(ETH_CFG_CAF | ETH_CFG_MTI | ETH_CFG_UNI);
1083 sc->flags &= ~ATE_FLAG_MULTICAST;
1086 * Set new parameters.
1088 if ((ifp->if_flags & IFF_BROADCAST) != 0)
1089 reg &= ~ETH_CFG_NBC;
1090 if ((ifp->if_flags & IFF_PROMISC) != 0) {
1093 enabled = ate_setmcast(sc);
1096 sc->flags |= ATE_FLAG_MULTICAST;
1099 WR4(sc, ETH_CFG, reg);
1103 ateioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1105 struct ate_softc *sc = ifp->if_softc;
1106 struct mii_data *mii;
1107 struct ifreq *ifr = (struct ifreq *)data;
1108 int drv_flags, flags;
1109 int mask, error, enabled;
1112 flags = ifp->if_flags;
1113 drv_flags = ifp->if_drv_flags;
1117 if ((flags & IFF_UP) != 0) {
1118 if ((drv_flags & IFF_DRV_RUNNING) != 0) {
1119 if (((flags ^ sc->if_flags)
1120 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1123 if ((sc->flags & ATE_FLAG_DETACHING) == 0)
1126 } else if ((drv_flags & IFF_DRV_RUNNING) != 0) {
1127 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1130 sc->if_flags = flags;
1136 if ((drv_flags & IFF_DRV_RUNNING) != 0) {
1138 enabled = ate_setmcast(sc);
1139 if (enabled != (sc->flags & ATE_FLAG_MULTICAST))
1147 mii = device_get_softc(sc->miibus);
1148 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1151 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
1152 if (mask & IFCAP_VLAN_MTU) {
1154 if (ifr->ifr_reqcap & IFCAP_VLAN_MTU) {
1155 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG);
1156 ifp->if_capenable |= IFCAP_VLAN_MTU;
1158 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_BIG);
1159 ifp->if_capenable &= ~IFCAP_VLAN_MTU;
1164 error = ether_ioctl(ifp, cmd, data);
1171 ate_child_detached(device_t dev, device_t child)
1173 struct ate_softc *sc;
1175 sc = device_get_softc(dev);
1176 if (child == sc->miibus)
1181 * MII bus support routines.
1184 ate_miibus_readreg(device_t dev, int phy, int reg)
1186 struct ate_softc *sc;
1190 * XXX if we implement agressive power savings, then we need
1191 * XXX to make sure that the clock to the emac is on here
1194 sc = device_get_softc(dev);
1195 DELAY(1); /* Hangs w/o this delay really 30.5us atm */
1196 WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg));
1197 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0)
1199 val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK;
1205 ate_miibus_writereg(device_t dev, int phy, int reg, int data)
1207 struct ate_softc *sc;
1210 * XXX if we implement agressive power savings, then we need
1211 * XXX to make sure that the clock to the emac is on here
1214 sc = device_get_softc(dev);
1215 WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data));
1216 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0)
1221 static device_method_t ate_methods[] = {
1222 /* Device interface */
1223 DEVMETHOD(device_probe, ate_probe),
1224 DEVMETHOD(device_attach, ate_attach),
1225 DEVMETHOD(device_detach, ate_detach),
1228 DEVMETHOD(bus_child_detached, ate_child_detached),
1231 DEVMETHOD(miibus_readreg, ate_miibus_readreg),
1232 DEVMETHOD(miibus_writereg, ate_miibus_writereg),
1237 static driver_t ate_driver = {
1240 sizeof(struct ate_softc),
1243 DRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, 0, 0);
1244 DRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, 0, 0);
1245 MODULE_DEPEND(ate, miibus, 1, 1, 1);
1246 MODULE_DEPEND(ate, ether, 1, 1, 1);