2 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
3 * Copyright (c) 2009 Greg Ansley. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * 1) Turn on the clock in pmc? Turn off?
30 * 2) GPIO initializtion in board setup code.
33 #include "opt_platform.h"
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
38 #include <sys/param.h>
39 #include <sys/systm.h>
41 #include <sys/kernel.h>
42 #include <sys/malloc.h>
44 #include <sys/module.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
50 #include <machine/bus.h>
52 #include <net/ethernet.h>
54 #include <net/if_arp.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/if_mib.h>
58 #include <net/if_types.h>
59 #include <net/if_var.h>
62 #include <netinet/in.h>
63 #include <netinet/in_systm.h>
64 #include <netinet/in_var.h>
65 #include <netinet/ip.h>
69 #include <net/bpfdesc.h>
71 #include <dev/mii/mii.h>
72 #include <dev/mii/miivar.h>
75 #include <arm/at91/at91reg.h>
76 #include <arm/at91/at91var.h>
77 #include <arm/at91/if_atereg.h>
80 #include <dev/ofw/ofw_bus.h>
81 #include <dev/ofw/ofw_bus_subr.h>
84 #include "miibus_if.h"
87 * Driver-specific flags.
89 #define ATE_FLAG_DETACHING 0x01
90 #define ATE_FLAG_MULTICAST 0x02
93 * Old EMAC assumes whole packet fits in one buffer;
94 * new EBACB assumes all receive buffers are 128 bytes
96 #define RX_BUF_SIZE(sc) (sc->is_emacb ? 128 : MCLBYTES)
99 * EMACB has an 11 bit counter for Rx/Tx Descriptors
100 * for max total of 1024 decriptors each.
102 #define ATE_MAX_RX_DESCR 1024
103 #define ATE_MAX_TX_DESCR 1024
105 /* How many buffers to allocate */
106 #define ATE_MAX_TX_BUFFERS 4 /* We have ping-pong tx buffers */
108 /* How much memory to use for rx buffers */
109 #define ATE_RX_MEMORY (ATE_MAX_RX_DESCR * 128)
111 /* Actual number of descriptors we allocate */
112 #define ATE_NUM_RX_DESCR ATE_MAX_RX_DESCR
113 #define ATE_NUM_TX_DESCR ATE_MAX_TX_BUFFERS
115 #if ATE_NUM_TX_DESCR > ATE_MAX_TX_DESCR
116 #error "Can't have more TX buffers that descriptors"
118 #if ATE_NUM_RX_DESCR > ATE_MAX_RX_DESCR
119 #error "Can't have more RX buffers that descriptors"
122 /* Wrap indexes the same way the hardware does */
123 #define NEXT_RX_IDX(sc, cur) \
124 ((sc->rx_descs[cur].addr & ETH_WRAP_BIT) ? 0 : (cur + 1))
126 #define NEXT_TX_IDX(sc, cur) \
127 ((sc->tx_descs[cur].status & ETHB_TX_WRAP) ? 0 : (cur + 1))
131 struct ifnet *ifp; /* ifnet pointer */
132 struct mtx sc_mtx; /* Basically a perimeter lock */
133 device_t dev; /* Myself */
134 device_t miibus; /* My child miibus */
135 struct resource *irq_res; /* IRQ resource */
136 struct resource *mem_res; /* Memory resource */
137 struct callout tick_ch; /* Tick callout */
138 struct ifmib_iso_8802_3 mibdata; /* Stuff for network mgmt */
139 bus_dma_tag_t mtag; /* bus dma tag for mbufs */
140 bus_dma_tag_t rx_tag;
141 bus_dma_tag_t rx_desc_tag;
142 bus_dmamap_t rx_desc_map;
143 bus_dmamap_t rx_map[ATE_MAX_RX_DESCR];
144 bus_addr_t rx_desc_phys; /* PA of rx descriptors */
145 eth_rx_desc_t *rx_descs; /* VA of rx descriptors */
146 void *rx_buf[ATE_NUM_RX_DESCR]; /* RX buffer space */
147 int rxhead; /* Current RX map/desc index */
148 uint32_t rx_buf_size; /* Size of Rx buffers */
150 bus_dma_tag_t tx_desc_tag;
151 bus_dmamap_t tx_desc_map;
152 bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS];
153 bus_addr_t tx_desc_phys; /* PA of tx descriptors */
154 eth_tx_desc_t *tx_descs; /* VA of tx descriptors */
155 int txhead; /* Current TX map/desc index */
156 int txtail; /* Current TX map/desc index */
157 struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */
158 void *intrhand; /* Interrupt handle */
162 int is_emacb; /* SAM9x hardware version */
165 static inline uint32_t
166 RD4(struct ate_softc *sc, bus_size_t off)
169 return (bus_read_4(sc->mem_res, off));
173 WR4(struct ate_softc *sc, bus_size_t off, uint32_t val)
176 bus_write_4(sc->mem_res, off, val);
180 BARRIER(struct ate_softc *sc, bus_size_t off, bus_size_t len, int flags)
183 bus_barrier(sc->mem_res, off, len, flags);
186 #define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
187 #define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
188 #define ATE_LOCK_INIT(_sc) \
189 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
190 MTX_NETWORK_LOCK, MTX_DEF)
191 #define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
192 #define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
193 #define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
195 static devclass_t ate_devclass;
198 * ifnet entry points.
200 static void ateinit_locked(void *);
201 static void atestart_locked(struct ifnet *);
203 static void ateinit(void *);
204 static void atestart(struct ifnet *);
205 static void atestop(struct ate_softc *);
206 static int ateioctl(struct ifnet * ifp, u_long, caddr_t);
211 static int ate_probe(device_t dev);
212 static int ate_attach(device_t dev);
213 static int ate_detach(device_t dev);
214 static void ate_intr(void *);
219 static int ate_activate(device_t dev);
220 static void ate_deactivate(struct ate_softc *sc);
221 static int ate_ifmedia_upd(struct ifnet *ifp);
222 static void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
223 static int ate_get_mac(struct ate_softc *sc, u_char *eaddr);
224 static void ate_set_mac(struct ate_softc *sc, u_char *eaddr);
225 static void ate_rxfilter(struct ate_softc *sc);
227 static int ate_miibus_readreg(device_t dev, int phy, int reg);
229 static int ate_miibus_writereg(device_t dev, int phy, int reg, int data);
232 * The AT91 family of products has the ethernet interface called EMAC.
233 * However, it isn't self identifying. It is anticipated that the parent bus
234 * code will take care to only add ate devices where they really are. As
235 * such, we do nothing here to identify the device and just set its name.
236 * However, FDT makes it self-identifying.
239 ate_probe(device_t dev)
242 if (!ofw_bus_is_compatible(dev, "cdns,at91rm9200-emac") &&
243 !ofw_bus_is_compatible(dev, "cdns,emac") &&
244 !ofw_bus_is_compatible(dev, "cdns,at32ap7000-macb"))
247 device_set_desc(dev, "EMAC");
253 * We have to know if we're using MII or RMII attachment
254 * for the MACB to talk to the PHY correctly. With FDT,
255 * we must use rmii if there's a proprety phy-mode
256 * equal to "rmii". Otherwise we MII mode is used.
259 ate_set_rmii(struct ate_softc *sc)
265 node = ofw_bus_get_node(sc->dev);
266 memset(prop, 0 ,sizeof(prop));
267 len = OF_getproplen(node, "phy-mode");
270 if (OF_getprop(node, "phy-mode", prop, len) != len)
272 if (strncmp(prop, "rmii", 4) == 0)
278 * We have to know if we're using MII or RMII attachment
279 * for the MACB to talk to the PHY correctly. Without FDT,
280 * there's no good way to do this. So, if the config file
281 * has 'option AT91_ATE_USE_RMII', then we'll force RMII.
282 * Otherwise, we'll use what the bootloader setup. Either
283 * it setup RMII or MII, in which case we'll get it right,
284 * or it did nothing, and we'll fall back to MII and the
285 * option would override if present.
288 ate_set_rmii(struct ate_softc *sc)
291 /* Default to what boot rom did */
294 (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII;
297 (RD4(sc, ETHB_UIO) & ETHB_UIO_RMII) == ETHB_UIO_RMII;
299 #ifdef AT91_ATE_USE_RMII
300 /* Compile time override */
307 ate_attach(device_t dev)
309 struct ate_softc *sc;
310 struct ifnet *ifp = NULL;
311 struct sysctl_ctx_list *sctx;
312 struct sysctl_oid *soid;
313 u_char eaddr[ETHER_ADDR_LEN];
317 sc = device_get_softc(dev);
322 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
324 if (sc->mem_res == NULL) {
325 device_printf(dev, "could not allocate memory resources.\n");
330 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
332 if (sc->irq_res == NULL) {
333 device_printf(dev, "could not allocate interrupt resources.\n");
338 /* New or old version, chooses buffer size. */
340 sc->is_emacb = ofw_bus_is_compatible(dev, "cdns,at32ap7000-macb");
342 sc->is_emacb = at91_is_sam9() || at91_is_sam9xe();
344 sc->rx_buf_size = RX_BUF_SIZE(sc);
346 err = ate_activate(dev);
353 sctx = device_get_sysctl_ctx(dev);
354 soid = device_get_sysctl_tree(dev);
355 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "rmii",
356 CTLFLAG_RW, &sc->use_rmii, 0, "rmii in use");
358 /* Calling atestop before ifp is set is OK. */
362 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0);
364 if ((err = ate_get_mac(sc, eaddr)) != 0) {
365 /* No MAC address configured. Generate the random one. */
368 "Generating random ethernet address.\n");
372 * Set OUI to convenient locally assigned address. 'b'
373 * is 0x62, which has the locally assigned bit set, and
374 * the broadcast/multicast bit clear.
379 eaddr[3] = (rnd >> 16) & 0xff;
380 eaddr[4] = (rnd >> 8) & 0xff;
381 eaddr[5] = (rnd >> 0) & 0xff;
384 sc->ifp = ifp = if_alloc(IFT_ETHER);
385 err = mii_attach(dev, &sc->miibus, ifp, ate_ifmedia_upd,
386 ate_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
388 device_printf(dev, "attaching PHYs failed\n");
392 * XXX: Clear the isolate bit, or we won't get up,
393 * at least on the HL201
395 ate_miibus_writereg(dev, 0, 0, 0x3000);
398 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
399 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
400 ifp->if_capabilities |= IFCAP_VLAN_MTU;
401 ifp->if_capenable |= IFCAP_VLAN_MTU; /* The hw bits already set. */
402 ifp->if_start = atestart;
403 ifp->if_ioctl = ateioctl;
404 ifp->if_init = ateinit;
405 ifp->if_baudrate = 10000000;
406 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
407 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
408 IFQ_SET_READY(&ifp->if_snd);
409 ifp->if_linkmib = &sc->mibdata;
410 ifp->if_linkmiblen = sizeof(sc->mibdata);
411 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
412 sc->if_flags = ifp->if_flags;
414 ether_ifattach(ifp, eaddr);
416 /* Activate the interrupt. */
417 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE,
418 NULL, ate_intr, sc, &sc->intrhand);
420 device_printf(dev, "could not establish interrupt handler.\n");
432 ate_detach(device_t dev)
434 struct ate_softc *sc;
437 sc = device_get_softc(dev);
438 KASSERT(sc != NULL, ("[ate: %d]: sc is NULL", __LINE__));
440 if (device_is_attached(dev)) {
442 sc->flags |= ATE_FLAG_DETACHING;
445 callout_drain(&sc->tick_ch);
448 if (sc->miibus != NULL) {
449 device_delete_child(dev, sc->miibus);
452 bus_generic_detach(sc->dev);
454 if (sc->intrhand != NULL) {
455 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
462 if (sc->mem_res != NULL) {
463 bus_release_resource(dev, SYS_RES_IOPORT,
464 rman_get_rid(sc->mem_res), sc->mem_res);
467 if (sc->irq_res != NULL) {
468 bus_release_resource(dev, SYS_RES_IRQ,
469 rman_get_rid(sc->irq_res), sc->irq_res);
472 ATE_LOCK_DESTROY(sc);
477 ate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
482 *(bus_addr_t *)arg = segs[0].ds_addr;
486 ate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
488 struct ate_softc *sc;
492 sc = (struct ate_softc *)arg;
494 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE);
495 sc->rx_descs[sc->rxhead].addr = segs[0].ds_addr;
496 sc->rx_descs[sc->rxhead].status = 0;
497 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_POSTWRITE);
501 ate_mac_hash(const uint8_t *buf)
504 for (int i = 0; i < 48; i++) {
505 index ^= ((buf[i >> 3] >> (i & 7)) & 1) << (i % 6);
511 * Compute the multicast filter for this device.
514 ate_setmcast(struct ate_softc *sc)
518 u_char *af = (u_char *) mcaf;
519 struct ifmultiaddr *ifma;
524 if ((ifp->if_flags & IFF_PROMISC) != 0)
526 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
527 WR4(sc, ETH_HSL, 0xffffffff);
528 WR4(sc, ETH_HSH, 0xffffffff);
532 /* Compute the multicast hash. */
536 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
537 if (ifma->ifma_addr->sa_family != AF_LINK)
539 index = ate_mac_hash(LLADDR((struct sockaddr_dl *)
541 af[index >> 3] |= 1 << (index & 7);
543 if_maddr_runlock(ifp);
546 * Write the hash to the hash register. This card can also
547 * accept unicast packets as well as multicast packets using this
548 * register for easier bridging operations, but we don't take
549 * advantage of that. Locks here are to avoid LOR with the
550 * if_maddr_rlock, but might not be strictly necessary.
552 WR4(sc, ETH_HSL, mcaf[0]);
553 WR4(sc, ETH_HSH, mcaf[1]);
554 return (mcaf[0] || mcaf[1]);
558 ate_activate(device_t dev)
560 struct ate_softc *sc;
563 sc = device_get_softc(dev);
565 /* Allocate DMA tags and maps for TX mbufs */
566 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
567 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
568 1, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, &sc->mtag))
570 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) {
571 if ( bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i]))
576 /* DMA tag and map for the RX descriptors. */
577 if (bus_dma_tag_create(bus_get_dma_tag(dev), sizeof(eth_rx_desc_t),
578 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
579 ATE_NUM_RX_DESCR * sizeof(eth_rx_desc_t), 1,
580 ATE_NUM_RX_DESCR * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex,
581 &sc->sc_mtx, &sc->rx_desc_tag))
583 if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs,
584 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rx_desc_map) != 0)
586 if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map,
587 sc->rx_descs, ATE_NUM_RX_DESCR * sizeof(eth_rx_desc_t),
588 ate_getaddr, &sc->rx_desc_phys, 0) != 0)
591 /* Allocate DMA tags and maps for RX. buffers */
592 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
593 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
594 sc->rx_buf_size, 1, sc->rx_buf_size, 0,
595 busdma_lock_mutex, &sc->sc_mtx, &sc->rx_tag))
599 * Allocate our RX buffers.
600 * This chip has a RX structure that's filled in.
601 * XXX On MACB (SAM9 part) we should receive directly into mbuf
602 * to avoid the copy. XXX
605 for (sc->rxhead = 0; sc->rxhead < ATE_RX_MEMORY/sc->rx_buf_size;
607 if (bus_dmamem_alloc(sc->rx_tag,
608 (void **)&sc->rx_buf[sc->rxhead], BUS_DMA_NOWAIT,
609 &sc->rx_map[sc->rxhead]) != 0)
612 if (bus_dmamap_load(sc->rx_tag, sc->rx_map[sc->rxhead],
613 sc->rx_buf[sc->rxhead], sc->rx_buf_size,
614 ate_load_rx_buf, sc, 0) != 0) {
615 printf("bus_dmamem_load\n");
618 bus_dmamap_sync(sc->rx_tag, sc->rx_map[sc->rxhead], BUS_DMASYNC_PREREAD);
622 * For the last buffer, set the wrap bit so the controller
623 * restarts from the first descriptor.
625 sc->rx_descs[--sc->rxhead].addr |= ETH_WRAP_BIT;
628 /* Flush the memory for the EMAC rx descriptor. */
629 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE);
631 /* Write the descriptor queue address. */
632 WR4(sc, ETH_RBQP, sc->rx_desc_phys);
635 * DMA tag and map for the TX descriptors.
637 if (bus_dma_tag_create(bus_get_dma_tag(dev), sizeof(eth_tx_desc_t),
638 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
639 ATE_MAX_TX_BUFFERS * sizeof(eth_tx_desc_t), 1,
640 ATE_MAX_TX_BUFFERS * sizeof(eth_tx_desc_t), 0, busdma_lock_mutex,
641 &sc->sc_mtx, &sc->tx_desc_tag) != 0)
644 if (bus_dmamem_alloc(sc->tx_desc_tag, (void **)&sc->tx_descs,
645 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->tx_desc_map) != 0)
648 if (bus_dmamap_load(sc->tx_desc_tag, sc->tx_desc_map,
649 sc->tx_descs, ATE_MAX_TX_BUFFERS * sizeof(eth_tx_desc_t),
650 ate_getaddr, &sc->tx_desc_phys, 0) != 0)
653 /* Initialize descriptors; mark all empty */
654 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) {
655 sc->tx_descs[i].addr =0;
656 sc->tx_descs[i].status = ETHB_TX_USED;
657 sc->sent_mbuf[i] = NULL;
660 /* Mark last entry to cause wrap when indexing through */
661 sc->tx_descs[ATE_MAX_TX_BUFFERS - 1].status =
662 ETHB_TX_WRAP | ETHB_TX_USED;
664 /* Flush the memory for the EMAC tx descriptor. */
665 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, BUS_DMASYNC_PREWRITE);
667 sc->txhead = sc->txtail = 0;
669 /* Write the descriptor queue address. */
670 WR4(sc, ETHB_TBQP, sc->tx_desc_phys);
672 /* EMACB: Enable transceiver input clock */
673 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) | ETHB_UIO_CLKE);
683 ate_deactivate(struct ate_softc *sc)
687 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__));
688 if (sc->mtag != NULL) {
689 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) {
690 if (sc->sent_mbuf[i] != NULL) {
691 bus_dmamap_sync(sc->mtag, sc->tx_map[i],
692 BUS_DMASYNC_POSTWRITE);
693 bus_dmamap_unload(sc->mtag, sc->tx_map[i]);
694 m_freem(sc->sent_mbuf[i]);
696 bus_dmamap_destroy(sc->mtag, sc->tx_map[i]);
697 sc->sent_mbuf[i] = NULL;
698 sc->tx_map[i] = NULL;
700 bus_dma_tag_destroy(sc->mtag);
702 if (sc->rx_desc_tag != NULL) {
703 if (sc->rx_descs != NULL) {
704 if (sc->rx_desc_phys != 0) {
705 bus_dmamap_sync(sc->rx_desc_tag,
706 sc->rx_desc_map, BUS_DMASYNC_POSTREAD);
707 bus_dmamap_unload(sc->rx_desc_tag,
709 sc->rx_desc_phys = 0;
713 if (sc->rx_tag != NULL) {
714 for (i = 0; sc->rx_buf[i] != NULL; i++) {
715 if (sc->rx_descs[i].addr != 0) {
716 bus_dmamap_sync(sc->rx_tag,
718 BUS_DMASYNC_POSTREAD);
719 bus_dmamap_unload(sc->rx_tag,
721 sc->rx_descs[i].addr = 0;
723 bus_dmamem_free(sc->rx_tag, sc->rx_buf[i],
725 sc->rx_buf[i] = NULL;
727 bus_dma_tag_destroy(sc->rx_tag);
729 if (sc->rx_desc_tag != NULL) {
730 if (sc->rx_descs != NULL)
731 bus_dmamem_free(sc->rx_desc_tag, sc->rx_descs,
733 bus_dma_tag_destroy(sc->rx_desc_tag);
735 sc->rx_desc_tag = NULL;
739 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE);
743 * Change media according to request.
746 ate_ifmedia_upd(struct ifnet *ifp)
748 struct ate_softc *sc = ifp->if_softc;
749 struct mii_data *mii;
751 mii = device_get_softc(sc->miibus);
759 * Notify the world which media we're using.
762 ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
764 struct ate_softc *sc = ifp->if_softc;
765 struct mii_data *mii;
767 mii = device_get_softc(sc->miibus);
770 ifmr->ifm_active = mii->mii_media_active;
771 ifmr->ifm_status = mii->mii_media_status;
776 ate_stat_update(struct ate_softc *sc, int active)
781 * The speed and full/half-duplex state needs to be reflected
782 * in the ETH_CFG register.
784 reg = RD4(sc, ETH_CFG);
785 reg &= ~(ETH_CFG_SPD | ETH_CFG_FD);
786 if (IFM_SUBTYPE(active) != IFM_10_T)
788 if (active & IFM_FDX)
790 WR4(sc, ETH_CFG, reg);
796 struct ate_softc *sc = xsc;
797 struct ifnet *ifp = sc->ifp;
798 struct mii_data *mii;
803 * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask
804 * the MII if there's a link if this bit is clear. Not sure if we
805 * should do the same thing here or not.
807 ATE_ASSERT_LOCKED(sc);
808 if (sc->miibus != NULL) {
809 mii = device_get_softc(sc->miibus);
810 active = mii->mii_media_active;
812 if (mii->mii_media_status & IFM_ACTIVE &&
813 active != mii->mii_media_active)
814 ate_stat_update(sc, mii->mii_media_active);
818 * Update the stats as best we can. When we're done, clear
819 * the status counters and start over. We're supposed to read these
820 * registers often enough that they won't overflow. Hopefully
821 * once a second is often enough. Some don't map well to
822 * the dot3Stats mib, so for those we just count them as general
823 * errors. Stats for iframes, ibutes, oframes and obytes are
824 * collected elsewhere. These registers zero on a read to prevent
825 * races. For all the collision stats, also update the collision
826 * stats for the interface.
828 sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE);
829 sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE);
830 c = RD4(sc, ETH_SCOL);
831 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, c);
832 sc->mibdata.dot3StatsSingleCollisionFrames += c;
833 c = RD4(sc, ETH_MCOL);
834 sc->mibdata.dot3StatsMultipleCollisionFrames += c;
835 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, c);
836 sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE);
837 sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE);
838 c = RD4(sc, ETH_LCOL);
839 sc->mibdata.dot3StatsLateCollisions += c;
840 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, c);
841 c = RD4(sc, ETH_ECOL);
842 sc->mibdata.dot3StatsExcessiveCollisions += c;
843 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, c);
844 sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE);
845 sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR);
846 sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC);
849 * Not sure where to lump these, so count them against the errors
852 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, RD4(sc, ETH_TUE));
853 if_inc_counter(sc->ifp, IFCOUNTER_IERRORS,
854 RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) + RD4(sc, ETH_USF));
856 /* Schedule another timeout one second from now. */
857 callout_reset(&sc->tick_ch, hz, ate_tick, sc);
861 ate_set_mac(struct ate_softc *sc, u_char *eaddr)
864 WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) |
865 (eaddr[1] << 8) | eaddr[0]);
866 WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4]));
870 ate_get_mac(struct ate_softc *sc, u_char *eaddr)
872 bus_size_t sa_low_reg[] = { ETH_SA1L, ETH_SA2L, ETH_SA3L, ETH_SA4L };
873 bus_size_t sa_high_reg[] = { ETH_SA1H, ETH_SA2H, ETH_SA3H, ETH_SA4H };
878 * The boot loader may setup the MAC with an address(es), grab the
879 * first MAC address from the SA[1-4][HL] registers.
881 for (i = 0; i < 4; i++) {
882 low = RD4(sc, sa_low_reg[i]);
883 high = RD4(sc, sa_high_reg[i]);
884 if ((low | (high & 0xffff)) != 0) {
885 eaddr[0] = low & 0xff;
886 eaddr[1] = (low >> 8) & 0xff;
887 eaddr[2] = (low >> 16) & 0xff;
888 eaddr[3] = (low >> 24) & 0xff;
889 eaddr[4] = high & 0xff;
890 eaddr[5] = (high >> 8) & 0xff;
900 struct ate_softc *sc = xsc;
901 struct ifnet *ifp = sc->ifp;
903 eth_rx_desc_t *rxdhead;
904 uint32_t status, reg, idx;
905 int remain, count, done;
907 status = RD4(sc, ETH_ISR);
911 if (status & ETH_ISR_RCOM) {
912 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map,
913 BUS_DMASYNC_POSTREAD);
915 rxdhead = &sc->rx_descs[sc->rxhead];
916 while (rxdhead->addr & ETH_CPU_OWNER) {
919 * Simulate SAM9 FIRST/LAST bits for RM9200.
920 * RM9200 EMAC has only on Rx buffer per packet.
921 * But sometime we are handed a zero length packet.
923 if ((rxdhead->status & ETH_LEN_MASK) == 0)
924 rxdhead->status = 0; /* Mark error */
926 rxdhead->status |= ETH_BUF_FIRST | ETH_BUF_LAST;
929 if ((rxdhead->status & ETH_BUF_FIRST) == 0) {
930 /* Something went wrong during RX so
931 release back to EMAC all buffers of invalid packets.
934 rxdhead->addr &= ~ETH_CPU_OWNER;
935 sc->rxhead = NEXT_RX_IDX(sc, sc->rxhead);
936 rxdhead = &sc->rx_descs[sc->rxhead];
940 /* Find end of packet or start of next */
942 if ((sc->rx_descs[idx].status & ETH_BUF_LAST) == 0) {
943 idx = NEXT_RX_IDX(sc, idx);
945 while ((sc->rx_descs[idx].addr & ETH_CPU_OWNER) &&
946 ((sc->rx_descs[idx].status &
947 (ETH_BUF_FIRST|ETH_BUF_LAST))== 0))
948 idx = NEXT_RX_IDX(sc, idx);
951 /* Packet NOT yet completely in memory; we are done */
952 if ((sc->rx_descs[idx].addr & ETH_CPU_OWNER) == 0 ||
953 ((sc->rx_descs[idx].status & (ETH_BUF_FIRST|ETH_BUF_LAST))== 0))
956 /* Packets with no end descriptor are invalid. */
957 if ((sc->rx_descs[idx].status & ETH_BUF_LAST) == 0) {
958 rxdhead->status &= ~ETH_BUF_FIRST;
962 /* FCS is not coppied into mbuf. */
963 remain = (sc->rx_descs[idx].status & ETH_LEN_MASK) - 4;
965 /* Get an appropriately sized mbuf. */
966 mb = m_get2(remain + ETHER_ALIGN, M_NOWAIT, MT_DATA,
969 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1);
973 mb->m_data += ETHER_ALIGN;
974 mb->m_pkthdr.rcvif = ifp;
976 WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); /* Reset status */
978 /* Now we process the buffers that make up the packet */
981 /* Last buffer may just be 1-4 bytes of FCS so remain
982 * may be zero for last descriptor. */
984 /* Make sure we get the current bytes */
985 bus_dmamap_sync(sc->rx_tag, sc->rx_map[sc->rxhead],
986 BUS_DMASYNC_POSTREAD);
988 count = MIN(remain, sc->rx_buf_size);
990 /* XXX Performance robbing copy. Could
991 * receive directly to mbufs if not an
992 * RM9200. And even then we could likely
993 * copy just the protocol headers. XXX */
994 m_append(mb, count, sc->rx_buf[sc->rxhead]);
998 done = (rxdhead->status & ETH_BUF_LAST) != 0;
1000 /* Return the descriptor to the EMAC */
1001 rxdhead->status = 0;
1002 rxdhead->addr &= ~ETH_CPU_OWNER;
1003 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map,
1004 BUS_DMASYNC_PREWRITE);
1006 /* Move on to next descriptor with wrap */
1007 sc->rxhead = NEXT_RX_IDX(sc, sc->rxhead);
1008 rxdhead = &sc->rx_descs[sc->rxhead];
1012 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1013 (*ifp->if_input)(ifp, mb);
1018 if (status & ETH_ISR_TCOM) {
1019 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map,
1020 BUS_DMASYNC_POSTREAD);
1023 /* XXX TSR register should be cleared */
1024 if (!sc->is_emacb) {
1025 /* Simulate Transmit descriptor table */
1027 /* First packet done */
1028 if (sc->txtail < sc->txhead)
1029 sc->tx_descs[sc->txtail].status |= ETHB_TX_USED;
1031 /* Second Packet done */
1032 if (sc->txtail + 1 < sc->txhead &&
1033 RD4(sc, ETH_TSR) & ETH_TSR_IDLE)
1034 sc->tx_descs[sc->txtail + 1].status |= ETHB_TX_USED;
1037 while ((sc->tx_descs[sc->txtail].status & ETHB_TX_USED) &&
1038 sc->sent_mbuf[sc->txtail] != NULL) {
1039 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txtail],
1040 BUS_DMASYNC_POSTWRITE);
1041 bus_dmamap_unload(sc->mtag, sc->tx_map[sc->txtail]);
1042 m_freem(sc->sent_mbuf[sc->txtail]);
1043 sc->tx_descs[sc->txtail].addr = 0;
1044 sc->sent_mbuf[sc->txtail] = NULL;
1045 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1046 sc->txtail = NEXT_TX_IDX(sc, sc->txtail);
1049 /* Flush descriptors to EMAC */
1050 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, BUS_DMASYNC_PREWRITE);
1053 * We're no longer busy, so clear the busy flag and call the
1054 * start routine to xmit more packets.
1056 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1057 atestart_locked(sc->ifp);
1061 if (status & ETH_ISR_RBNA) {
1062 /* Workaround RM9200 Errata #11 */
1064 device_printf(sc->dev, "RBNA workaround\n");
1065 reg = RD4(sc, ETH_CTL);
1066 WR4(sc, ETH_CTL, reg & ~ETH_CTL_RE);
1067 BARRIER(sc, ETH_CTL, 4, BUS_SPACE_BARRIER_WRITE);
1068 WR4(sc, ETH_CTL, reg | ETH_CTL_RE);
1071 /* XXX need to work around SAM9260 errata 43.2.4.1:
1072 * disable the mac, reset tx buffer, enable mac on TUND */
1076 * Reset and initialize the chip.
1079 ateinit_locked(void *xsc)
1081 struct ate_softc *sc = xsc;
1082 struct ifnet *ifp = sc->ifp;
1083 struct mii_data *mii;
1084 uint8_t eaddr[ETHER_ADDR_LEN];
1087 ATE_ASSERT_LOCKED(sc);
1091 * we need to turn on the EMAC clock in the pmc. With the
1092 * default boot loader, this is already turned on. However, we
1093 * need to think about how best to turn it on/off as the interface
1094 * is brought up/down, as well as dealing with the mii bus...
1096 * We also need to multiplex the pins correctly (in board_xxx.c).
1100 * There are two different ways that the mii bus is connected
1101 * to this chip mii or rmii.
1103 if (!sc->is_emacb) {
1105 reg = RD4(sc, ETH_CFG);
1107 reg |= ETH_CFG_RMII;
1109 reg &= ~ETH_CFG_RMII;
1110 WR4(sc, ETH_CFG, reg);
1113 reg = ETHB_UIO_CLKE;
1114 reg |= (sc->use_rmii) ? ETHB_UIO_RMII : 0;
1115 WR4(sc, ETHB_UIO, reg);
1121 * Set the chip MAC address.
1123 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
1124 ate_set_mac(sc, eaddr);
1126 /* Make sure we know state of TX queue */
1127 sc->txhead = sc->txtail = 0;
1129 /* Write the descriptor queue address. */
1130 WR4(sc, ETHB_TBQP, sc->tx_desc_phys);
1134 * Turn on MACs and interrupt processing.
1136 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE);
1137 WR4(sc, ETH_IER, ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA);
1139 /* Enable big packets. */
1140 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG);
1143 * Set 'running' flag, and clear output active flag
1144 * and attempt to start the output.
1146 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1147 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1149 mii = device_get_softc(sc->miibus);
1151 ate_stat_update(sc, mii->mii_media_active);
1152 atestart_locked(ifp);
1154 callout_reset(&sc->tick_ch, hz, ate_tick, sc);
1158 * Dequeue packets and transmit.
1161 atestart_locked(struct ifnet *ifp)
1163 struct ate_softc *sc = ifp->if_softc;
1164 struct mbuf *m, *mdefrag;
1165 bus_dma_segment_t segs[1];
1168 ATE_ASSERT_LOCKED(sc);
1169 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1172 while (sc->tx_descs[sc->txhead].status & ETHB_TX_USED) {
1174 * Check to see if there's room to put another packet into the
1175 * xmit queue. The old EMAC version has a ping-pong buffer for
1176 * xmit packets. We use OACTIVE to indicate "we can stuff more
1177 * into our buffers (clear) or not (set)."
1179 /* RM9200 has only two hardware entries */
1180 if (!sc->is_emacb && (RD4(sc, ETH_TSR) & ETH_TSR_BNQ) == 0) {
1181 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1185 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1189 e = bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txhead], m,
1192 mdefrag = m_defrag(m, M_NOWAIT);
1193 if (mdefrag == NULL) {
1194 IFQ_DRV_PREPEND(&ifp->if_snd, m);
1198 e = bus_dmamap_load_mbuf_sg(sc->mtag,
1199 sc->tx_map[sc->txhead], m, segs, &nseg, 0);
1207 * There's a small race between the loop in ate_intr finishing
1208 * and the check above to see if the packet was finished, as well
1209 * as when atestart gets called via other paths. Lose the race
1210 * gracefully and free the mbuf...
1212 if (sc->sent_mbuf[sc->txhead] != NULL) {
1213 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txtail],
1214 BUS_DMASYNC_POSTWRITE);
1215 bus_dmamap_unload(sc->mtag, sc->tx_map[sc->txtail]);
1216 m_free(sc->sent_mbuf[sc->txhead]);
1217 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1220 sc->sent_mbuf[sc->txhead] = m;
1222 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txhead],
1223 BUS_DMASYNC_PREWRITE);
1225 /* Tell the hardware to xmit the packet. */
1226 if (!sc->is_emacb) {
1227 WR4(sc, ETH_TAR, segs[0].ds_addr);
1228 BARRIER(sc, ETH_TAR, 4, BUS_SPACE_BARRIER_WRITE);
1229 WR4(sc, ETH_TCR, segs[0].ds_len);
1231 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map,
1232 BUS_DMASYNC_POSTWRITE);
1233 sc->tx_descs[sc->txhead].addr = segs[0].ds_addr;
1234 sc->tx_descs[sc->txhead].status = segs[0].ds_len |
1235 (sc->tx_descs[sc->txhead].status & ETHB_TX_WRAP) |
1237 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map,
1238 BUS_DMASYNC_PREWRITE);
1239 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETHB_CTL_TGO);
1241 sc->txhead = NEXT_TX_IDX(sc, sc->txhead);
1243 /* Tap off here if there is a bpf listener. */
1247 if ((sc->tx_descs[sc->txhead].status & ETHB_TX_USED) == 0)
1248 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1254 struct ate_softc *sc = xsc;
1262 atestart(struct ifnet *ifp)
1264 struct ate_softc *sc = ifp->if_softc;
1267 atestart_locked(ifp);
1272 * Turn off interrupts, and stop the NIC. Can be called with sc->ifp NULL,
1276 atestop(struct ate_softc *sc)
1281 ATE_ASSERT_LOCKED(sc);
1284 //ifp->if_timer = 0;
1285 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1288 callout_stop(&sc->tick_ch);
1291 * Enable some parts of the MAC that are needed always (like the
1292 * MII bus. This turns off the RE and TE bits, which will remain
1293 * off until ateinit() is called to turn them on. With RE and TE
1294 * turned off, there's no DMA to worry about after this write.
1296 WR4(sc, ETH_CTL, ETH_CTL_MPE);
1299 * Turn off all the configured options and revert to defaults.
1302 /* Make sure thate the MDIO clk is less than
1303 * 2.5 Mhz. Can no longer default to /32 since
1304 * SAM9 family may have MCK > 80 Mhz */
1305 if (at91_master_clock <= 2000000)
1306 WR4(sc, ETH_CFG, ETH_CFG_CLK_8);
1307 else if (at91_master_clock <= 4000000)
1308 WR4(sc, ETH_CFG, ETH_CFG_CLK_16);
1309 else if (at91_master_clock <= 800000)
1310 WR4(sc, ETH_CFG, ETH_CFG_CLK_32);
1312 WR4(sc, ETH_CFG, ETH_CFG_CLK_64);
1315 * Turn off all the interrupts, and ack any pending ones by reading
1318 WR4(sc, ETH_IDR, 0xffffffff);
1322 * Clear out the Transmit and Receiver Status registers of any
1323 * errors they may be reporting
1325 WR4(sc, ETH_TSR, 0xffffffff);
1326 WR4(sc, ETH_RSR, 0xffffffff);
1328 /* Release TX resources. */
1329 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) {
1330 if (sc->sent_mbuf[i] != NULL) {
1331 bus_dmamap_sync(sc->mtag, sc->tx_map[i],
1332 BUS_DMASYNC_POSTWRITE);
1333 bus_dmamap_unload(sc->mtag, sc->tx_map[i]);
1334 m_freem(sc->sent_mbuf[i]);
1335 sc->sent_mbuf[i] = NULL;
1339 /* Turn off transeiver input clock */
1341 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE);
1344 * XXX we should power down the EMAC if it isn't in use, after
1345 * putting it into loopback mode. This saves about 400uA according
1351 ate_rxfilter(struct ate_softc *sc)
1357 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__));
1358 ATE_ASSERT_LOCKED(sc);
1361 /* Wipe out old filter settings. */
1362 reg = RD4(sc, ETH_CFG);
1363 reg &= ~(ETH_CFG_CAF | ETH_CFG_MTI | ETH_CFG_UNI);
1365 sc->flags &= ~ATE_FLAG_MULTICAST;
1367 /* Set new parameters. */
1368 if ((ifp->if_flags & IFF_BROADCAST) != 0)
1369 reg &= ~ETH_CFG_NBC;
1370 if ((ifp->if_flags & IFF_PROMISC) != 0) {
1373 enabled = ate_setmcast(sc);
1376 sc->flags |= ATE_FLAG_MULTICAST;
1379 WR4(sc, ETH_CFG, reg);
1383 ateioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1385 struct ate_softc *sc = ifp->if_softc;
1386 struct mii_data *mii;
1387 struct ifreq *ifr = (struct ifreq *)data;
1388 int drv_flags, flags;
1389 int mask, error, enabled;
1392 flags = ifp->if_flags;
1393 drv_flags = ifp->if_drv_flags;
1397 if ((flags & IFF_UP) != 0) {
1398 if ((drv_flags & IFF_DRV_RUNNING) != 0) {
1399 if (((flags ^ sc->if_flags)
1400 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1403 if ((sc->flags & ATE_FLAG_DETACHING) == 0)
1406 } else if ((drv_flags & IFF_DRV_RUNNING) != 0) {
1407 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1410 sc->if_flags = flags;
1416 if ((drv_flags & IFF_DRV_RUNNING) != 0) {
1418 enabled = ate_setmcast(sc);
1419 if (enabled != (sc->flags & ATE_FLAG_MULTICAST))
1427 mii = device_get_softc(sc->miibus);
1428 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1431 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
1432 if (mask & IFCAP_VLAN_MTU) {
1434 if (ifr->ifr_reqcap & IFCAP_VLAN_MTU) {
1435 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG);
1436 ifp->if_capenable |= IFCAP_VLAN_MTU;
1438 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_BIG);
1439 ifp->if_capenable &= ~IFCAP_VLAN_MTU;
1444 error = ether_ioctl(ifp, cmd, data);
1451 ate_child_detached(device_t dev, device_t child)
1453 struct ate_softc *sc;
1455 sc = device_get_softc(dev);
1456 if (child == sc->miibus)
1461 * MII bus support routines.
1464 ate_miibus_readreg(device_t dev, int phy, int reg)
1466 struct ate_softc *sc;
1470 * XXX if we implement aggressive power savings, then we need
1471 * XXX to make sure that the clock to the emac is on here
1474 sc = device_get_softc(dev);
1475 DELAY(1); /* Hangs w/o this delay really 30.5us atm */
1476 WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg));
1477 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0)
1479 val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK;
1485 ate_miibus_writereg(device_t dev, int phy, int reg, int data)
1487 struct ate_softc *sc;
1490 * XXX if we implement aggressive power savings, then we need
1491 * XXX to make sure that the clock to the emac is on here
1494 sc = device_get_softc(dev);
1495 WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data));
1496 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0)
1501 static device_method_t ate_methods[] = {
1502 /* Device interface */
1503 DEVMETHOD(device_probe, ate_probe),
1504 DEVMETHOD(device_attach, ate_attach),
1505 DEVMETHOD(device_detach, ate_detach),
1508 DEVMETHOD(bus_child_detached, ate_child_detached),
1511 DEVMETHOD(miibus_readreg, ate_miibus_readreg),
1512 DEVMETHOD(miibus_writereg, ate_miibus_writereg),
1517 static driver_t ate_driver = {
1520 sizeof(struct ate_softc),
1524 DRIVER_MODULE(ate, simplebus, ate_driver, ate_devclass, NULL, NULL);
1526 DRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, NULL, NULL);
1528 DRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, NULL, NULL);
1529 MODULE_DEPEND(ate, miibus, 1, 1, 1);
1530 MODULE_DEPEND(ate, ether, 1, 1, 1);