2 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
3 * Copyright (c) 2009 Greg Ansley. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * 1) Turn on the clock in pmc? Turn off?
30 * 2) GPIO initializtion in board setup code.
33 #include "opt_platform.h"
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
38 #include <sys/param.h>
39 #include <sys/systm.h>
41 #include <sys/kernel.h>
42 #include <sys/malloc.h>
44 #include <sys/module.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
50 #include <machine/bus.h>
52 #include <net/ethernet.h>
54 #include <net/if_arp.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/if_mib.h>
58 #include <net/if_types.h>
59 #include <net/if_var.h>
62 #include <netinet/in.h>
63 #include <netinet/in_systm.h>
64 #include <netinet/in_var.h>
65 #include <netinet/ip.h>
69 #include <net/bpfdesc.h>
71 #include <dev/mii/mii.h>
72 #include <dev/mii/miivar.h>
75 #include <arm/at91/at91reg.h>
76 #include <arm/at91/at91var.h>
77 #include <arm/at91/if_atereg.h>
80 #include <dev/fdt/fdt_common.h>
81 #include <dev/ofw/ofw_bus.h>
82 #include <dev/ofw/ofw_bus_subr.h>
85 #include "miibus_if.h"
88 * Driver-specific flags.
90 #define ATE_FLAG_DETACHING 0x01
91 #define ATE_FLAG_MULTICAST 0x02
94 * Old EMAC assumes whole packet fits in one buffer;
95 * new EBACB assumes all receive buffers are 128 bytes
97 #define RX_BUF_SIZE(sc) (sc->is_emacb ? 128 : MCLBYTES)
100 * EMACB has an 11 bit counter for Rx/Tx Descriptors
101 * for max total of 1024 decriptors each.
103 #define ATE_MAX_RX_DESCR 1024
104 #define ATE_MAX_TX_DESCR 1024
106 /* How many buffers to allocate */
107 #define ATE_MAX_TX_BUFFERS 4 /* We have ping-pong tx buffers */
109 /* How much memory to use for rx buffers */
110 #define ATE_RX_MEMORY (ATE_MAX_RX_DESCR * 128)
112 /* Actual number of descriptors we allocate */
113 #define ATE_NUM_RX_DESCR ATE_MAX_RX_DESCR
114 #define ATE_NUM_TX_DESCR ATE_MAX_TX_BUFFERS
116 #if ATE_NUM_TX_DESCR > ATE_MAX_TX_DESCR
117 #error "Can't have more TX buffers that descriptors"
119 #if ATE_NUM_RX_DESCR > ATE_MAX_RX_DESCR
120 #error "Can't have more RX buffers that descriptors"
123 /* Wrap indexes the same way the hardware does */
124 #define NEXT_RX_IDX(sc, cur) \
125 ((sc->rx_descs[cur].addr & ETH_WRAP_BIT) ? 0 : (cur + 1))
127 #define NEXT_TX_IDX(sc, cur) \
128 ((sc->tx_descs[cur].status & ETHB_TX_WRAP) ? 0 : (cur + 1))
132 struct ifnet *ifp; /* ifnet pointer */
133 struct mtx sc_mtx; /* Basically a perimeter lock */
134 device_t dev; /* Myself */
135 device_t miibus; /* My child miibus */
136 struct resource *irq_res; /* IRQ resource */
137 struct resource *mem_res; /* Memory resource */
138 struct callout tick_ch; /* Tick callout */
139 struct ifmib_iso_8802_3 mibdata; /* Stuff for network mgmt */
140 bus_dma_tag_t mtag; /* bus dma tag for mbufs */
141 bus_dma_tag_t rx_tag;
142 bus_dma_tag_t rx_desc_tag;
143 bus_dmamap_t rx_desc_map;
144 bus_dmamap_t rx_map[ATE_MAX_RX_DESCR];
145 bus_addr_t rx_desc_phys; /* PA of rx descriptors */
146 eth_rx_desc_t *rx_descs; /* VA of rx descriptors */
147 void *rx_buf[ATE_NUM_RX_DESCR]; /* RX buffer space */
148 int rxhead; /* Current RX map/desc index */
149 uint32_t rx_buf_size; /* Size of Rx buffers */
151 bus_dma_tag_t tx_desc_tag;
152 bus_dmamap_t tx_desc_map;
153 bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS];
154 bus_addr_t tx_desc_phys; /* PA of tx descriptors */
155 eth_tx_desc_t *tx_descs; /* VA of tx descriptors */
156 int txhead; /* Current TX map/desc index */
157 int txtail; /* Current TX map/desc index */
158 struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */
159 void *intrhand; /* Interrupt handle */
163 int is_emacb; /* SAM9x hardware version */
166 static inline uint32_t
167 RD4(struct ate_softc *sc, bus_size_t off)
170 return (bus_read_4(sc->mem_res, off));
174 WR4(struct ate_softc *sc, bus_size_t off, uint32_t val)
177 bus_write_4(sc->mem_res, off, val);
181 BARRIER(struct ate_softc *sc, bus_size_t off, bus_size_t len, int flags)
184 bus_barrier(sc->mem_res, off, len, flags);
187 #define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
188 #define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
189 #define ATE_LOCK_INIT(_sc) \
190 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
191 MTX_NETWORK_LOCK, MTX_DEF)
192 #define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
193 #define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
194 #define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
196 static devclass_t ate_devclass;
199 * ifnet entry points.
201 static void ateinit_locked(void *);
202 static void atestart_locked(struct ifnet *);
204 static void ateinit(void *);
205 static void atestart(struct ifnet *);
206 static void atestop(struct ate_softc *);
207 static int ateioctl(struct ifnet * ifp, u_long, caddr_t);
212 static int ate_probe(device_t dev);
213 static int ate_attach(device_t dev);
214 static int ate_detach(device_t dev);
215 static void ate_intr(void *);
220 static int ate_activate(device_t dev);
221 static void ate_deactivate(struct ate_softc *sc);
222 static int ate_ifmedia_upd(struct ifnet *ifp);
223 static void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
224 static int ate_get_mac(struct ate_softc *sc, u_char *eaddr);
225 static void ate_set_mac(struct ate_softc *sc, u_char *eaddr);
226 static void ate_rxfilter(struct ate_softc *sc);
228 static int ate_miibus_readreg(device_t dev, int phy, int reg);
230 static int ate_miibus_writereg(device_t dev, int phy, int reg, int data);
233 * The AT91 family of products has the ethernet interface called EMAC.
234 * However, it isn't self identifying. It is anticipated that the parent bus
235 * code will take care to only add ate devices where they really are. As
236 * such, we do nothing here to identify the device and just set its name.
237 * However, FDT makes it self-identifying.
240 ate_probe(device_t dev)
243 if (!ofw_bus_is_compatible(dev, "cdns,at91rm9200-emac") &&
244 !ofw_bus_is_compatible(dev, "cdns,emac") &&
245 !ofw_bus_is_compatible(dev, "cdns,at32ap7000-macb"))
248 device_set_desc(dev, "EMAC");
254 * We have to know if we're using MII or RMII attachment
255 * for the MACB to talk to the PHY correctly. With FDT,
256 * we must use rmii if there's a proprety phy-mode
257 * equal to "rmii". Otherwise we MII mode is used.
260 ate_set_rmii(struct ate_softc *sc)
266 node = ofw_bus_get_node(sc->dev);
267 memset(prop, 0 ,sizeof(prop));
268 len = OF_getproplen(node, "phy-mode");
271 if (OF_getprop(node, "phy-mode", prop, len) != len)
273 if (strncmp(prop, "rmii", 4) == 0)
279 * We have to know if we're using MII or RMII attachment
280 * for the MACB to talk to the PHY correctly. Without FDT,
281 * there's no good way to do this. So, if the config file
282 * has 'option AT91_ATE_USE_RMII', then we'll force RMII.
283 * Otherwise, we'll use what the bootloader setup. Either
284 * it setup RMII or MII, in which case we'll get it right,
285 * or it did nothing, and we'll fall back to MII and the
286 * option would override if present.
289 ate_set_rmii(struct ate_softc *sc)
292 /* Default to what boot rom did */
295 (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII;
298 (RD4(sc, ETHB_UIO) & ETHB_UIO_RMII) == ETHB_UIO_RMII;
300 #ifdef AT91_ATE_USE_RMII
301 /* Compile time override */
308 ate_attach(device_t dev)
310 struct ate_softc *sc;
311 struct ifnet *ifp = NULL;
312 struct sysctl_ctx_list *sctx;
313 struct sysctl_oid *soid;
314 u_char eaddr[ETHER_ADDR_LEN];
318 sc = device_get_softc(dev);
323 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
325 if (sc->mem_res == NULL) {
326 device_printf(dev, "could not allocate memory resources.\n");
331 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
333 if (sc->irq_res == NULL) {
334 device_printf(dev, "could not allocate interrupt resources.\n");
339 /* New or old version, chooses buffer size. */
341 sc->is_emacb = ofw_bus_is_compatible(dev, "cdns,at32ap7000-macb");
343 sc->is_emacb = at91_is_sam9() || at91_is_sam9xe();
345 sc->rx_buf_size = RX_BUF_SIZE(sc);
347 err = ate_activate(dev);
354 sctx = device_get_sysctl_ctx(dev);
355 soid = device_get_sysctl_tree(dev);
356 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "rmii",
357 CTLFLAG_RW, &sc->use_rmii, 0, "rmii in use");
359 /* Calling atestop before ifp is set is OK. */
363 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0);
365 if ((err = ate_get_mac(sc, eaddr)) != 0) {
366 /* No MAC address configured. Generate the random one. */
369 "Generating random ethernet address.\n");
373 * Set OUI to convenient locally assigned address. 'b'
374 * is 0x62, which has the locally assigned bit set, and
375 * the broadcast/multicast bit clear.
380 eaddr[3] = (rnd >> 16) & 0xff;
381 eaddr[4] = (rnd >> 8) & 0xff;
382 eaddr[5] = (rnd >> 0) & 0xff;
385 sc->ifp = ifp = if_alloc(IFT_ETHER);
386 err = mii_attach(dev, &sc->miibus, ifp, ate_ifmedia_upd,
387 ate_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
389 device_printf(dev, "attaching PHYs failed\n");
393 * XXX: Clear the isolate bit, or we won't get up,
394 * at least on the HL201
396 ate_miibus_writereg(dev, 0, 0, 0x3000);
399 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
400 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
401 ifp->if_capabilities |= IFCAP_VLAN_MTU;
402 ifp->if_capenable |= IFCAP_VLAN_MTU; /* The hw bits already set. */
403 ifp->if_start = atestart;
404 ifp->if_ioctl = ateioctl;
405 ifp->if_init = ateinit;
406 ifp->if_baudrate = 10000000;
407 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
408 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
409 IFQ_SET_READY(&ifp->if_snd);
410 ifp->if_linkmib = &sc->mibdata;
411 ifp->if_linkmiblen = sizeof(sc->mibdata);
412 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
413 sc->if_flags = ifp->if_flags;
415 ether_ifattach(ifp, eaddr);
417 /* Activate the interrupt. */
418 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE,
419 NULL, ate_intr, sc, &sc->intrhand);
421 device_printf(dev, "could not establish interrupt handler.\n");
433 ate_detach(device_t dev)
435 struct ate_softc *sc;
438 sc = device_get_softc(dev);
439 KASSERT(sc != NULL, ("[ate: %d]: sc is NULL", __LINE__));
441 if (device_is_attached(dev)) {
443 sc->flags |= ATE_FLAG_DETACHING;
446 callout_drain(&sc->tick_ch);
449 if (sc->miibus != NULL) {
450 device_delete_child(dev, sc->miibus);
453 bus_generic_detach(sc->dev);
455 if (sc->intrhand != NULL) {
456 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
463 if (sc->mem_res != NULL) {
464 bus_release_resource(dev, SYS_RES_IOPORT,
465 rman_get_rid(sc->mem_res), sc->mem_res);
468 if (sc->irq_res != NULL) {
469 bus_release_resource(dev, SYS_RES_IRQ,
470 rman_get_rid(sc->irq_res), sc->irq_res);
473 ATE_LOCK_DESTROY(sc);
478 ate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
483 *(bus_addr_t *)arg = segs[0].ds_addr;
487 ate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
489 struct ate_softc *sc;
493 sc = (struct ate_softc *)arg;
495 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE);
496 sc->rx_descs[sc->rxhead].addr = segs[0].ds_addr;
497 sc->rx_descs[sc->rxhead].status = 0;
498 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_POSTWRITE);
502 ate_mac_hash(const uint8_t *buf)
505 for (int i = 0; i < 48; i++) {
506 index ^= ((buf[i >> 3] >> (i & 7)) & 1) << (i % 6);
512 * Compute the multicast filter for this device.
515 ate_setmcast(struct ate_softc *sc)
519 u_char *af = (u_char *) mcaf;
520 struct ifmultiaddr *ifma;
525 if ((ifp->if_flags & IFF_PROMISC) != 0)
527 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
528 WR4(sc, ETH_HSL, 0xffffffff);
529 WR4(sc, ETH_HSH, 0xffffffff);
533 /* Compute the multicast hash. */
537 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
538 if (ifma->ifma_addr->sa_family != AF_LINK)
540 index = ate_mac_hash(LLADDR((struct sockaddr_dl *)
542 af[index >> 3] |= 1 << (index & 7);
544 if_maddr_runlock(ifp);
547 * Write the hash to the hash register. This card can also
548 * accept unicast packets as well as multicast packets using this
549 * register for easier bridging operations, but we don't take
550 * advantage of that. Locks here are to avoid LOR with the
551 * if_maddr_rlock, but might not be strictly necessary.
553 WR4(sc, ETH_HSL, mcaf[0]);
554 WR4(sc, ETH_HSH, mcaf[1]);
555 return (mcaf[0] || mcaf[1]);
559 ate_activate(device_t dev)
561 struct ate_softc *sc;
564 sc = device_get_softc(dev);
566 /* Allocate DMA tags and maps for TX mbufs */
567 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
568 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
569 1, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, &sc->mtag))
571 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) {
572 if ( bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i]))
577 /* DMA tag and map for the RX descriptors. */
578 if (bus_dma_tag_create(bus_get_dma_tag(dev), sizeof(eth_rx_desc_t),
579 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
580 ATE_NUM_RX_DESCR * sizeof(eth_rx_desc_t), 1,
581 ATE_NUM_RX_DESCR * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex,
582 &sc->sc_mtx, &sc->rx_desc_tag))
584 if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs,
585 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rx_desc_map) != 0)
587 if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map,
588 sc->rx_descs, ATE_NUM_RX_DESCR * sizeof(eth_rx_desc_t),
589 ate_getaddr, &sc->rx_desc_phys, 0) != 0)
592 /* Allocate DMA tags and maps for RX. buffers */
593 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
594 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
595 sc->rx_buf_size, 1, sc->rx_buf_size, 0,
596 busdma_lock_mutex, &sc->sc_mtx, &sc->rx_tag))
600 * Allocate our RX buffers.
601 * This chip has a RX structure that's filled in.
602 * XXX On MACB (SAM9 part) we should receive directly into mbuf
603 * to avoid the copy. XXX
606 for (sc->rxhead = 0; sc->rxhead < ATE_RX_MEMORY/sc->rx_buf_size;
608 if (bus_dmamem_alloc(sc->rx_tag,
609 (void **)&sc->rx_buf[sc->rxhead], BUS_DMA_NOWAIT,
610 &sc->rx_map[sc->rxhead]) != 0)
613 if (bus_dmamap_load(sc->rx_tag, sc->rx_map[sc->rxhead],
614 sc->rx_buf[sc->rxhead], sc->rx_buf_size,
615 ate_load_rx_buf, sc, 0) != 0) {
616 printf("bus_dmamem_load\n");
619 bus_dmamap_sync(sc->rx_tag, sc->rx_map[sc->rxhead], BUS_DMASYNC_PREREAD);
623 * For the last buffer, set the wrap bit so the controller
624 * restarts from the first descriptor.
626 sc->rx_descs[--sc->rxhead].addr |= ETH_WRAP_BIT;
629 /* Flush the memory for the EMAC rx descriptor. */
630 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE);
632 /* Write the descriptor queue address. */
633 WR4(sc, ETH_RBQP, sc->rx_desc_phys);
636 * DMA tag and map for the TX descriptors.
638 if (bus_dma_tag_create(bus_get_dma_tag(dev), sizeof(eth_tx_desc_t),
639 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
640 ATE_MAX_TX_BUFFERS * sizeof(eth_tx_desc_t), 1,
641 ATE_MAX_TX_BUFFERS * sizeof(eth_tx_desc_t), 0, busdma_lock_mutex,
642 &sc->sc_mtx, &sc->tx_desc_tag) != 0)
645 if (bus_dmamem_alloc(sc->tx_desc_tag, (void **)&sc->tx_descs,
646 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->tx_desc_map) != 0)
649 if (bus_dmamap_load(sc->tx_desc_tag, sc->tx_desc_map,
650 sc->tx_descs, ATE_MAX_TX_BUFFERS * sizeof(eth_tx_desc_t),
651 ate_getaddr, &sc->tx_desc_phys, 0) != 0)
654 /* Initialize descriptors; mark all empty */
655 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) {
656 sc->tx_descs[i].addr =0;
657 sc->tx_descs[i].status = ETHB_TX_USED;
658 sc->sent_mbuf[i] = NULL;
661 /* Mark last entry to cause wrap when indexing through */
662 sc->tx_descs[ATE_MAX_TX_BUFFERS - 1].status =
663 ETHB_TX_WRAP | ETHB_TX_USED;
665 /* Flush the memory for the EMAC tx descriptor. */
666 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, BUS_DMASYNC_PREWRITE);
668 sc->txhead = sc->txtail = 0;
670 /* Write the descriptor queue address. */
671 WR4(sc, ETHB_TBQP, sc->tx_desc_phys);
673 /* EMACB: Enable transceiver input clock */
674 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) | ETHB_UIO_CLKE);
684 ate_deactivate(struct ate_softc *sc)
688 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__));
689 if (sc->mtag != NULL) {
690 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) {
691 if (sc->sent_mbuf[i] != NULL) {
692 bus_dmamap_sync(sc->mtag, sc->tx_map[i],
693 BUS_DMASYNC_POSTWRITE);
694 bus_dmamap_unload(sc->mtag, sc->tx_map[i]);
695 m_freem(sc->sent_mbuf[i]);
697 bus_dmamap_destroy(sc->mtag, sc->tx_map[i]);
698 sc->sent_mbuf[i] = NULL;
699 sc->tx_map[i] = NULL;
701 bus_dma_tag_destroy(sc->mtag);
703 if (sc->rx_desc_tag != NULL) {
704 if (sc->rx_descs != NULL) {
705 if (sc->rx_desc_phys != 0) {
706 bus_dmamap_sync(sc->rx_desc_tag,
707 sc->rx_desc_map, BUS_DMASYNC_POSTREAD);
708 bus_dmamap_unload(sc->rx_desc_tag,
710 sc->rx_desc_phys = 0;
714 if (sc->rx_tag != NULL) {
715 for (i = 0; sc->rx_buf[i] != NULL; i++) {
716 if (sc->rx_descs[i].addr != 0) {
717 bus_dmamap_sync(sc->rx_tag,
719 BUS_DMASYNC_POSTREAD);
720 bus_dmamap_unload(sc->rx_tag,
722 sc->rx_descs[i].addr = 0;
724 bus_dmamem_free(sc->rx_tag, sc->rx_buf[i],
726 sc->rx_buf[i] = NULL;
728 bus_dma_tag_destroy(sc->rx_tag);
730 if (sc->rx_desc_tag != NULL) {
731 if (sc->rx_descs != NULL)
732 bus_dmamem_free(sc->rx_desc_tag, sc->rx_descs,
734 bus_dma_tag_destroy(sc->rx_desc_tag);
736 sc->rx_desc_tag = NULL;
740 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE);
744 * Change media according to request.
747 ate_ifmedia_upd(struct ifnet *ifp)
749 struct ate_softc *sc = ifp->if_softc;
750 struct mii_data *mii;
752 mii = device_get_softc(sc->miibus);
760 * Notify the world which media we're using.
763 ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
765 struct ate_softc *sc = ifp->if_softc;
766 struct mii_data *mii;
768 mii = device_get_softc(sc->miibus);
771 ifmr->ifm_active = mii->mii_media_active;
772 ifmr->ifm_status = mii->mii_media_status;
777 ate_stat_update(struct ate_softc *sc, int active)
782 * The speed and full/half-duplex state needs to be reflected
783 * in the ETH_CFG register.
785 reg = RD4(sc, ETH_CFG);
786 reg &= ~(ETH_CFG_SPD | ETH_CFG_FD);
787 if (IFM_SUBTYPE(active) != IFM_10_T)
789 if (active & IFM_FDX)
791 WR4(sc, ETH_CFG, reg);
797 struct ate_softc *sc = xsc;
798 struct ifnet *ifp = sc->ifp;
799 struct mii_data *mii;
804 * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask
805 * the MII if there's a link if this bit is clear. Not sure if we
806 * should do the same thing here or not.
808 ATE_ASSERT_LOCKED(sc);
809 if (sc->miibus != NULL) {
810 mii = device_get_softc(sc->miibus);
811 active = mii->mii_media_active;
813 if (mii->mii_media_status & IFM_ACTIVE &&
814 active != mii->mii_media_active)
815 ate_stat_update(sc, mii->mii_media_active);
819 * Update the stats as best we can. When we're done, clear
820 * the status counters and start over. We're supposed to read these
821 * registers often enough that they won't overflow. Hopefully
822 * once a second is often enough. Some don't map well to
823 * the dot3Stats mib, so for those we just count them as general
824 * errors. Stats for iframes, ibutes, oframes and obytes are
825 * collected elsewhere. These registers zero on a read to prevent
826 * races. For all the collision stats, also update the collision
827 * stats for the interface.
829 sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE);
830 sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE);
831 c = RD4(sc, ETH_SCOL);
832 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, c);
833 sc->mibdata.dot3StatsSingleCollisionFrames += c;
834 c = RD4(sc, ETH_MCOL);
835 sc->mibdata.dot3StatsMultipleCollisionFrames += c;
836 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, c);
837 sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE);
838 sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE);
839 c = RD4(sc, ETH_LCOL);
840 sc->mibdata.dot3StatsLateCollisions += c;
841 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, c);
842 c = RD4(sc, ETH_ECOL);
843 sc->mibdata.dot3StatsExcessiveCollisions += c;
844 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, c);
845 sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE);
846 sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR);
847 sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC);
850 * Not sure where to lump these, so count them against the errors
853 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, RD4(sc, ETH_TUE));
854 if_inc_counter(sc->ifp, IFCOUNTER_IERRORS,
855 RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) + RD4(sc, ETH_USF));
857 /* Schedule another timeout one second from now. */
858 callout_reset(&sc->tick_ch, hz, ate_tick, sc);
862 ate_set_mac(struct ate_softc *sc, u_char *eaddr)
865 WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) |
866 (eaddr[1] << 8) | eaddr[0]);
867 WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4]));
871 ate_get_mac(struct ate_softc *sc, u_char *eaddr)
873 bus_size_t sa_low_reg[] = { ETH_SA1L, ETH_SA2L, ETH_SA3L, ETH_SA4L };
874 bus_size_t sa_high_reg[] = { ETH_SA1H, ETH_SA2H, ETH_SA3H, ETH_SA4H };
879 * The boot loader may setup the MAC with an address(es), grab the
880 * first MAC address from the SA[1-4][HL] registers.
882 for (i = 0; i < 4; i++) {
883 low = RD4(sc, sa_low_reg[i]);
884 high = RD4(sc, sa_high_reg[i]);
885 if ((low | (high & 0xffff)) != 0) {
886 eaddr[0] = low & 0xff;
887 eaddr[1] = (low >> 8) & 0xff;
888 eaddr[2] = (low >> 16) & 0xff;
889 eaddr[3] = (low >> 24) & 0xff;
890 eaddr[4] = high & 0xff;
891 eaddr[5] = (high >> 8) & 0xff;
901 struct ate_softc *sc = xsc;
902 struct ifnet *ifp = sc->ifp;
904 eth_rx_desc_t *rxdhead;
905 uint32_t status, reg, idx;
906 int remain, count, done;
908 status = RD4(sc, ETH_ISR);
912 if (status & ETH_ISR_RCOM) {
913 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map,
914 BUS_DMASYNC_POSTREAD);
916 rxdhead = &sc->rx_descs[sc->rxhead];
917 while (rxdhead->addr & ETH_CPU_OWNER) {
920 * Simulate SAM9 FIRST/LAST bits for RM9200.
921 * RM9200 EMAC has only on Rx buffer per packet.
922 * But sometime we are handed a zero length packet.
924 if ((rxdhead->status & ETH_LEN_MASK) == 0)
925 rxdhead->status = 0; /* Mark error */
927 rxdhead->status |= ETH_BUF_FIRST | ETH_BUF_LAST;
930 if ((rxdhead->status & ETH_BUF_FIRST) == 0) {
931 /* Something went wrong during RX so
932 release back to EMAC all buffers of invalid packets.
935 rxdhead->addr &= ~ETH_CPU_OWNER;
936 sc->rxhead = NEXT_RX_IDX(sc, sc->rxhead);
937 rxdhead = &sc->rx_descs[sc->rxhead];
941 /* Find end of packet or start of next */
943 if ((sc->rx_descs[idx].status & ETH_BUF_LAST) == 0) {
944 idx = NEXT_RX_IDX(sc, idx);
946 while ((sc->rx_descs[idx].addr & ETH_CPU_OWNER) &&
947 ((sc->rx_descs[idx].status &
948 (ETH_BUF_FIRST|ETH_BUF_LAST))== 0))
949 idx = NEXT_RX_IDX(sc, idx);
952 /* Packet NOT yet completely in memory; we are done */
953 if ((sc->rx_descs[idx].addr & ETH_CPU_OWNER) == 0 ||
954 ((sc->rx_descs[idx].status & (ETH_BUF_FIRST|ETH_BUF_LAST))== 0))
957 /* Packets with no end descriptor are invalid. */
958 if ((sc->rx_descs[idx].status & ETH_BUF_LAST) == 0) {
959 rxdhead->status &= ~ETH_BUF_FIRST;
963 /* FCS is not coppied into mbuf. */
964 remain = (sc->rx_descs[idx].status & ETH_LEN_MASK) - 4;
966 /* Get an appropriately sized mbuf. */
967 mb = m_get2(remain + ETHER_ALIGN, M_NOWAIT, MT_DATA,
970 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1);
974 mb->m_data += ETHER_ALIGN;
975 mb->m_pkthdr.rcvif = ifp;
977 WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); /* Reset status */
979 /* Now we process the buffers that make up the packet */
982 /* Last buffer may just be 1-4 bytes of FCS so remain
983 * may be zero for last descriptor. */
985 /* Make sure we get the current bytes */
986 bus_dmamap_sync(sc->rx_tag, sc->rx_map[sc->rxhead],
987 BUS_DMASYNC_POSTREAD);
989 count = MIN(remain, sc->rx_buf_size);
991 /* XXX Performance robbing copy. Could
992 * receive directly to mbufs if not an
993 * RM9200. And even then we could likely
994 * copy just the protocol headers. XXX */
995 m_append(mb, count, sc->rx_buf[sc->rxhead]);
999 done = (rxdhead->status & ETH_BUF_LAST) != 0;
1001 /* Return the descriptor to the EMAC */
1002 rxdhead->status = 0;
1003 rxdhead->addr &= ~ETH_CPU_OWNER;
1004 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map,
1005 BUS_DMASYNC_PREWRITE);
1007 /* Move on to next descriptor with wrap */
1008 sc->rxhead = NEXT_RX_IDX(sc, sc->rxhead);
1009 rxdhead = &sc->rx_descs[sc->rxhead];
1013 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1014 (*ifp->if_input)(ifp, mb);
1019 if (status & ETH_ISR_TCOM) {
1020 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map,
1021 BUS_DMASYNC_POSTREAD);
1024 /* XXX TSR register should be cleared */
1025 if (!sc->is_emacb) {
1026 /* Simulate Transmit descriptor table */
1028 /* First packet done */
1029 if (sc->txtail < sc->txhead)
1030 sc->tx_descs[sc->txtail].status |= ETHB_TX_USED;
1032 /* Second Packet done */
1033 if (sc->txtail + 1 < sc->txhead &&
1034 RD4(sc, ETH_TSR) & ETH_TSR_IDLE)
1035 sc->tx_descs[sc->txtail + 1].status |= ETHB_TX_USED;
1038 while ((sc->tx_descs[sc->txtail].status & ETHB_TX_USED) &&
1039 sc->sent_mbuf[sc->txtail] != NULL) {
1040 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txtail],
1041 BUS_DMASYNC_POSTWRITE);
1042 bus_dmamap_unload(sc->mtag, sc->tx_map[sc->txtail]);
1043 m_freem(sc->sent_mbuf[sc->txtail]);
1044 sc->tx_descs[sc->txtail].addr = 0;
1045 sc->sent_mbuf[sc->txtail] = NULL;
1046 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1047 sc->txtail = NEXT_TX_IDX(sc, sc->txtail);
1050 /* Flush descriptors to EMAC */
1051 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, BUS_DMASYNC_PREWRITE);
1054 * We're no longer busy, so clear the busy flag and call the
1055 * start routine to xmit more packets.
1057 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1058 atestart_locked(sc->ifp);
1062 if (status & ETH_ISR_RBNA) {
1063 /* Workaround RM9200 Errata #11 */
1065 device_printf(sc->dev, "RBNA workaround\n");
1066 reg = RD4(sc, ETH_CTL);
1067 WR4(sc, ETH_CTL, reg & ~ETH_CTL_RE);
1068 BARRIER(sc, ETH_CTL, 4, BUS_SPACE_BARRIER_WRITE);
1069 WR4(sc, ETH_CTL, reg | ETH_CTL_RE);
1072 /* XXX need to work around SAM9260 errata 43.2.4.1:
1073 * disable the mac, reset tx buffer, enable mac on TUND */
1077 * Reset and initialize the chip.
1080 ateinit_locked(void *xsc)
1082 struct ate_softc *sc = xsc;
1083 struct ifnet *ifp = sc->ifp;
1084 struct mii_data *mii;
1085 uint8_t eaddr[ETHER_ADDR_LEN];
1088 ATE_ASSERT_LOCKED(sc);
1092 * we need to turn on the EMAC clock in the pmc. With the
1093 * default boot loader, this is already turned on. However, we
1094 * need to think about how best to turn it on/off as the interface
1095 * is brought up/down, as well as dealing with the mii bus...
1097 * We also need to multiplex the pins correctly (in board_xxx.c).
1101 * There are two different ways that the mii bus is connected
1102 * to this chip mii or rmii.
1104 if (!sc->is_emacb) {
1106 reg = RD4(sc, ETH_CFG);
1108 reg |= ETH_CFG_RMII;
1110 reg &= ~ETH_CFG_RMII;
1111 WR4(sc, ETH_CFG, reg);
1114 reg = ETHB_UIO_CLKE;
1115 reg |= (sc->use_rmii) ? ETHB_UIO_RMII : 0;
1116 WR4(sc, ETHB_UIO, reg);
1122 * Set the chip MAC address.
1124 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
1125 ate_set_mac(sc, eaddr);
1127 /* Make sure we know state of TX queue */
1128 sc->txhead = sc->txtail = 0;
1130 /* Write the descriptor queue address. */
1131 WR4(sc, ETHB_TBQP, sc->tx_desc_phys);
1135 * Turn on MACs and interrupt processing.
1137 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE);
1138 WR4(sc, ETH_IER, ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA);
1140 /* Enable big packets. */
1141 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG);
1144 * Set 'running' flag, and clear output active flag
1145 * and attempt to start the output.
1147 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1148 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1150 mii = device_get_softc(sc->miibus);
1152 ate_stat_update(sc, mii->mii_media_active);
1153 atestart_locked(ifp);
1155 callout_reset(&sc->tick_ch, hz, ate_tick, sc);
1159 * Dequeue packets and transmit.
1162 atestart_locked(struct ifnet *ifp)
1164 struct ate_softc *sc = ifp->if_softc;
1165 struct mbuf *m, *mdefrag;
1166 bus_dma_segment_t segs[1];
1169 ATE_ASSERT_LOCKED(sc);
1170 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1173 while (sc->tx_descs[sc->txhead].status & ETHB_TX_USED) {
1175 * Check to see if there's room to put another packet into the
1176 * xmit queue. The old EMAC version has a ping-pong buffer for
1177 * xmit packets. We use OACTIVE to indicate "we can stuff more
1178 * into our buffers (clear) or not (set)."
1180 /* RM9200 has only two hardware entries */
1181 if (!sc->is_emacb && (RD4(sc, ETH_TSR) & ETH_TSR_BNQ) == 0) {
1182 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1186 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1190 e = bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txhead], m,
1193 mdefrag = m_defrag(m, M_NOWAIT);
1194 if (mdefrag == NULL) {
1195 IFQ_DRV_PREPEND(&ifp->if_snd, m);
1199 e = bus_dmamap_load_mbuf_sg(sc->mtag,
1200 sc->tx_map[sc->txhead], m, segs, &nseg, 0);
1208 * There's a small race between the loop in ate_intr finishing
1209 * and the check above to see if the packet was finished, as well
1210 * as when atestart gets called via other paths. Lose the race
1211 * gracefully and free the mbuf...
1213 if (sc->sent_mbuf[sc->txhead] != NULL) {
1214 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txtail],
1215 BUS_DMASYNC_POSTWRITE);
1216 bus_dmamap_unload(sc->mtag, sc->tx_map[sc->txtail]);
1217 m_free(sc->sent_mbuf[sc->txhead]);
1218 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1221 sc->sent_mbuf[sc->txhead] = m;
1223 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txhead],
1224 BUS_DMASYNC_PREWRITE);
1226 /* Tell the hardware to xmit the packet. */
1227 if (!sc->is_emacb) {
1228 WR4(sc, ETH_TAR, segs[0].ds_addr);
1229 BARRIER(sc, ETH_TAR, 4, BUS_SPACE_BARRIER_WRITE);
1230 WR4(sc, ETH_TCR, segs[0].ds_len);
1232 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map,
1233 BUS_DMASYNC_POSTWRITE);
1234 sc->tx_descs[sc->txhead].addr = segs[0].ds_addr;
1235 sc->tx_descs[sc->txhead].status = segs[0].ds_len |
1236 (sc->tx_descs[sc->txhead].status & ETHB_TX_WRAP) |
1238 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map,
1239 BUS_DMASYNC_PREWRITE);
1240 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETHB_CTL_TGO);
1242 sc->txhead = NEXT_TX_IDX(sc, sc->txhead);
1244 /* Tap off here if there is a bpf listener. */
1248 if ((sc->tx_descs[sc->txhead].status & ETHB_TX_USED) == 0)
1249 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1255 struct ate_softc *sc = xsc;
1263 atestart(struct ifnet *ifp)
1265 struct ate_softc *sc = ifp->if_softc;
1268 atestart_locked(ifp);
1273 * Turn off interrupts, and stop the NIC. Can be called with sc->ifp NULL,
1277 atestop(struct ate_softc *sc)
1282 ATE_ASSERT_LOCKED(sc);
1285 //ifp->if_timer = 0;
1286 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1289 callout_stop(&sc->tick_ch);
1292 * Enable some parts of the MAC that are needed always (like the
1293 * MII bus. This turns off the RE and TE bits, which will remain
1294 * off until ateinit() is called to turn them on. With RE and TE
1295 * turned off, there's no DMA to worry about after this write.
1297 WR4(sc, ETH_CTL, ETH_CTL_MPE);
1300 * Turn off all the configured options and revert to defaults.
1303 /* Make sure thate the MDIO clk is less than
1304 * 2.5 Mhz. Can no longer default to /32 since
1305 * SAM9 family may have MCK > 80 Mhz */
1306 if (at91_master_clock <= 2000000)
1307 WR4(sc, ETH_CFG, ETH_CFG_CLK_8);
1308 else if (at91_master_clock <= 4000000)
1309 WR4(sc, ETH_CFG, ETH_CFG_CLK_16);
1310 else if (at91_master_clock <= 800000)
1311 WR4(sc, ETH_CFG, ETH_CFG_CLK_32);
1313 WR4(sc, ETH_CFG, ETH_CFG_CLK_64);
1316 * Turn off all the interrupts, and ack any pending ones by reading
1319 WR4(sc, ETH_IDR, 0xffffffff);
1323 * Clear out the Transmit and Receiver Status registers of any
1324 * errors they may be reporting
1326 WR4(sc, ETH_TSR, 0xffffffff);
1327 WR4(sc, ETH_RSR, 0xffffffff);
1329 /* Release TX resources. */
1330 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) {
1331 if (sc->sent_mbuf[i] != NULL) {
1332 bus_dmamap_sync(sc->mtag, sc->tx_map[i],
1333 BUS_DMASYNC_POSTWRITE);
1334 bus_dmamap_unload(sc->mtag, sc->tx_map[i]);
1335 m_freem(sc->sent_mbuf[i]);
1336 sc->sent_mbuf[i] = NULL;
1340 /* Turn off transeiver input clock */
1342 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE);
1345 * XXX we should power down the EMAC if it isn't in use, after
1346 * putting it into loopback mode. This saves about 400uA according
1352 ate_rxfilter(struct ate_softc *sc)
1358 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__));
1359 ATE_ASSERT_LOCKED(sc);
1362 /* Wipe out old filter settings. */
1363 reg = RD4(sc, ETH_CFG);
1364 reg &= ~(ETH_CFG_CAF | ETH_CFG_MTI | ETH_CFG_UNI);
1366 sc->flags &= ~ATE_FLAG_MULTICAST;
1368 /* Set new parameters. */
1369 if ((ifp->if_flags & IFF_BROADCAST) != 0)
1370 reg &= ~ETH_CFG_NBC;
1371 if ((ifp->if_flags & IFF_PROMISC) != 0) {
1374 enabled = ate_setmcast(sc);
1377 sc->flags |= ATE_FLAG_MULTICAST;
1380 WR4(sc, ETH_CFG, reg);
1384 ateioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1386 struct ate_softc *sc = ifp->if_softc;
1387 struct mii_data *mii;
1388 struct ifreq *ifr = (struct ifreq *)data;
1389 int drv_flags, flags;
1390 int mask, error, enabled;
1393 flags = ifp->if_flags;
1394 drv_flags = ifp->if_drv_flags;
1398 if ((flags & IFF_UP) != 0) {
1399 if ((drv_flags & IFF_DRV_RUNNING) != 0) {
1400 if (((flags ^ sc->if_flags)
1401 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1404 if ((sc->flags & ATE_FLAG_DETACHING) == 0)
1407 } else if ((drv_flags & IFF_DRV_RUNNING) != 0) {
1408 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1411 sc->if_flags = flags;
1417 if ((drv_flags & IFF_DRV_RUNNING) != 0) {
1419 enabled = ate_setmcast(sc);
1420 if (enabled != (sc->flags & ATE_FLAG_MULTICAST))
1428 mii = device_get_softc(sc->miibus);
1429 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1432 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
1433 if (mask & IFCAP_VLAN_MTU) {
1435 if (ifr->ifr_reqcap & IFCAP_VLAN_MTU) {
1436 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG);
1437 ifp->if_capenable |= IFCAP_VLAN_MTU;
1439 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_BIG);
1440 ifp->if_capenable &= ~IFCAP_VLAN_MTU;
1445 error = ether_ioctl(ifp, cmd, data);
1452 ate_child_detached(device_t dev, device_t child)
1454 struct ate_softc *sc;
1456 sc = device_get_softc(dev);
1457 if (child == sc->miibus)
1462 * MII bus support routines.
1465 ate_miibus_readreg(device_t dev, int phy, int reg)
1467 struct ate_softc *sc;
1471 * XXX if we implement aggressive power savings, then we need
1472 * XXX to make sure that the clock to the emac is on here
1475 sc = device_get_softc(dev);
1476 DELAY(1); /* Hangs w/o this delay really 30.5us atm */
1477 WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg));
1478 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0)
1480 val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK;
1486 ate_miibus_writereg(device_t dev, int phy, int reg, int data)
1488 struct ate_softc *sc;
1491 * XXX if we implement aggressive power savings, then we need
1492 * XXX to make sure that the clock to the emac is on here
1495 sc = device_get_softc(dev);
1496 WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data));
1497 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0)
1502 static device_method_t ate_methods[] = {
1503 /* Device interface */
1504 DEVMETHOD(device_probe, ate_probe),
1505 DEVMETHOD(device_attach, ate_attach),
1506 DEVMETHOD(device_detach, ate_detach),
1509 DEVMETHOD(bus_child_detached, ate_child_detached),
1512 DEVMETHOD(miibus_readreg, ate_miibus_readreg),
1513 DEVMETHOD(miibus_writereg, ate_miibus_writereg),
1518 static driver_t ate_driver = {
1521 sizeof(struct ate_softc),
1525 DRIVER_MODULE(ate, simplebus, ate_driver, ate_devclass, NULL, NULL);
1527 DRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, NULL, NULL);
1529 DRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, NULL, NULL);
1530 MODULE_DEPEND(ate, miibus, 1, 1, 1);
1531 MODULE_DEPEND(ate, ether, 1, 1, 1);