2 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #ifndef ARM_AT91_IF_ATEREG_H
29 #define ARM_AT91_IF_ATEREG_H
31 /* Defines beginning ETHB_ are EMACB (newer SAM9 hardware) versions only. */
33 #define ETH_CTL 0x00 /* EMAC Control Register */
34 #define ETH_CFG 0x04 /* EMAC Configuration Register */
35 #define ETH_SR 0x08 /* EMAC STatus Register */
36 #define ETH_TAR 0x0c /* EMAC Transmit Address Register */
37 #define ETH_TCR 0x10 /* EMAC Transmit Control Register */
38 #define ETH_TSR 0x14 /* EMAC Transmit Status Register */
39 #define ETH_RBQP 0x18 /* EMAC Receive Buffer Queue Pointer */
40 #define ETHB_TBQP 0x1c /* reserved */
41 #define ETH_RSR 0x20 /* EMAC Receive Status Register */
42 #define ETH_ISR 0x24 /* EMAC Interrupt Status Register */
43 #define ETH_IER 0x28 /* EMAC Interrupt Enable Register */
44 #define ETH_IDR 0x2c /* EMAC Interrupt Disable Register */
45 #define ETH_IMR 0x30 /* EMAC Interrupt Mask Register */
46 #define ETH_MAN 0x34 /* EMAC PHY Maintenance Register */
49 #define ETH_FRA 0x40 /* Frames Transmitted OK Register */
50 #define ETH_SCOL 0x44 /* Single Collision Frame Register */
51 #define ETH_MCOL 0x48 /* Multiple Collision Frame Register */
52 #define ETH_OK 0x4c /* Frames Received OK Register */
53 #define ETH_SEQE 0x50 /* Frame Check Sequence Error Reg */
54 #define ETH_ALE 0x54 /* Alignment Error Register */
55 #define ETH_DTE 0x58 /* Deferred Transmittion Frame Reg */
56 #define ETH_LCOL 0x5c /* Late Collision Register */
57 #define ETH_ECOL 0x60 /* Excessive Collision Register */
58 #define ETH_TUE 0x64 /* Transmit Underrun Error Register */
59 #define ETH_CSE 0x68 /* Carrier Sense Error Register */
60 #define ETH_DRFC 0x6c /* Discarded RX Frame Register */
61 #define ETH_ROV 0x68 /* Receive Overrun Register */
62 #define ETH_CDE 0x64 /* Code Error Register */
63 #define ETH_ELR 0x78 /* Excessive Length Error Register */
64 #define ETH_RJB 0x7c /* Receive Jabber Register */
65 #define ETH_USF 0x80 /* Undersize Frame Register */
66 #define ETH_SQEE 0x84 /* SQE Test Error Register */
69 #define ETH_HSL 0x90 /* EMAC Hash Address Low [31:0] */
70 #define ETH_HSH 0x94 /* EMAC Hash Address High [63:32] */
71 #define ETH_SA1L 0x98 /* EMAC Specific Address 1 Low */
72 #define ETH_SA1H 0x9c /* EMAC Specific Address 1 High */
73 #define ETH_SA2L 0xa0 /* EMAC Specific Address 2 Low */
74 #define ETH_SA2H 0xa4 /* EMAC Specific Address 2 High */
75 #define ETH_SA3L 0xa8 /* EMAC Specific Address 3 Low */
76 #define ETH_SA3H 0xac /* EMAC Specific Address 3 High */
77 #define ETH_SA4L 0xb0 /* EMAC Specific Address 4 Low */
78 #define ETH_SA4H 0xb4 /* EMAC Specific Address 4 High */
79 #define ETHB_TID 0xb8 /* EMAC Type ID Checking */
80 #define ETHB_UIO 0xC0 /* EMAC User I/O Reg */
84 #define ETH_CTL_LB (1U << 0) /* LB: Loopback */
85 #define ETH_CTL_LBL (1U << 1) /* LBL: Loopback Local */
86 #define ETH_CTL_RE (1U << 2) /* RE: Receive Enable */
87 #define ETH_CTL_TE (1U << 3) /* TE: Transmit Enable */
88 #define ETH_CTL_MPE (1U << 4) /* MPE: Management Port Enable */
89 #define ETH_CTL_CSR (1U << 5) /* CSR: Clear Statistics Registers */
90 #define ETH_CTL_ISR (1U << 6) /* ISR: Incremenet Statistics Regs */
91 #define ETH_CTL_WES (1U << 7) /* WES: Write Enable Statistics regs */
92 #define ETH_CTL_BP (1U << 8) /* BP: Back Pressure */
94 #define ETHB_CTL_TGO (1U << 9) /* TGO: Transmitter Start */
95 #define ETHB_CTL_TSTP (1U << 10) /* TSTP: Transmitter Stop */
98 #define ETH_CFG_SPD (1U << 0) /* SPD: Speed 1 == 100: 0 == 10 */
99 #define ETH_CFG_FD (1U << 1) /* FD: Full duplex */
100 #define ETH_CFG_BR (1U << 2) /* BR: Bit Rate (optional?) */
102 #define ETH_CFG_CAF (1U << 4) /* CAF: Copy All Frames */
103 #define ETH_CFG_NBC (1U << 5) /* NBC: No Broadcast */
104 #define ETH_CFG_MTI (1U << 6) /* MTI: Multicast Hash Enable */
105 #define ETH_CFG_UNI (1U << 7) /* UNI: Unicast Hash Enable */
106 #define ETH_CFG_BIG (1U << 8) /* BIG: Receive 1522 Bytes */
107 #define ETH_CFG_EAE (1U << 9) /* EAE: External Address Match En */
108 #define ETH_CFG_CLK_8 (0U << 10) /* CLK: Clock / 8 */
109 #define ETH_CFG_CLK_16 (1U << 10) /* CLK: Clock / 16 */
110 #define ETH_CFG_CLK_32 (2U << 10) /* CLK: Clock / 32 */
111 #define ETH_CFG_CLK_64 (3U << 10) /* CLK: Clock / 64 */
112 #define ETH_CFG_RTY (1U << 12) /* RTY: Retry Test*/
113 #define ETH_CFG_RMII (1U << 13) /* RMII: Reduce MII */
115 #define ETHB_CFG_JBO (1U << 3) /* JBO: Jumbo Frames */
116 #define ETHB_CFG_PAE (1U << 13) /* PAE: Pause Enable */
117 #define ETHB_CFG_RBOF_0 (0U << 14) /* RBOF: Rx Buffer Offset */
118 #define ETHB_CFG_RBOF_1 (1U << 14) /* RBOF: Rx Buffer Offset */
119 #define ETHB_CFG_RBOF_2 (3U << 14) /* RBOF: Rx Buffer Offset */
120 #define ETHB_CFG_RBOF_3 (3U << 14) /* RBOF: Rx Buffer Offset */
121 #define ETHB_CFG_RCLE (1U << 16) /* RCLE: Rx Length Check Enable */
122 #define ETHB_CFG_DRFC (1U << 17) /* DRFC: Discard Rx FCS */
123 #define ETHB_CFG_RHD (1U << 18) /* RHD: RX TX'ed frame in half-duplex */
124 #define ETHB_CFG_IFCS (1U << 19) /* IFCS: Ignore bad RX FCS */
127 #define ETH_SR_LINK (1U << 0) /* Reserved! */
128 #define ETH_SR_MDIO (1U << 1) /* MDIO pin status */
129 #define ETH_SR_IDLE (1U << 2) /* IDLE (PHY logic) */
132 #define ETH_TCR_NCRC (1U << 15) /* NCRC: No CRC */
135 #define ETH_TSR_OVR (1U << 0) /* OVR: Ethernet Transmit Overrun */
136 #define ETH_TSR_COL (1U << 1) /* COL: Collision Occurred */
137 #define ETH_TSR_RLE (1U << 2) /* RLE: Retry Limit Exceeded */
138 #define ETH_TSR_IDLE (1U << 3) /* IDLE: Transmitter Idle */
139 #define ETH_TSR_BNQ (1U << 4) /* BNQ: Enet Tran Buff not Queued */
140 #define ETH_TSR_COMP (1U << 5) /* COMP: Transmit Complete */
141 #define ETH_TSR_UND (1U << 6) /* UND: Transmit Underrun */
142 #define ETH_TSR_WR_MASK (0x67) /* write 1 to clear bits */
145 #define ETH_RSR_BNA (1U << 0) /* BNA: Buffer Not Available */
146 #define ETH_RSR_REC (1U << 1) /* REC: Frame Received */
147 #define ETH_RSR_OVR (1U << 2) /* OVR: RX Overrun */
150 #define ETH_ISR_DONE (1U << 0) /* DONE: Management Done */
151 #define ETH_ISR_RCOM (1U << 1) /* RCOM: Receive Complete */
152 #define ETH_ISR_RBNA (1U << 2) /* RBNA: Receive Buffer Not Avail */
153 #define ETH_ISR_TOVR (1U << 3) /* TOVR: Transmit Buffer Overrun */
154 #define ETH_ISR_TUND (1U << 4) /* TUND: Transmit Buffer Underrun */
155 #define ETH_ISR_RTRY (1U << 5) /* RTRY: Retry Limit */
156 #define ETH_ISR_TBRE (1U << 6) /* TBRE: Trasnmit Buffer Reg empty */
157 #define ETH_ISR_TCOM (1U << 7) /* TCOM: Transmit Complete */
158 #define ETH_ISR_TIDLE (1U << 8) /* TIDLE: Transmit Idle */
159 #define ETH_ISR_LINK (1U << 9) /* LINK: Link pin delta (optional) */
160 #define ETH_ISR_ROVR (1U << 10) /* ROVR: RX Overrun */
161 #define ETH_ISR_ABT (1U << 11) /* ABT: Abort */
164 #define ETHB_UIO_RMII (1U << 0) /* RMII: Reduce MII */
165 #define ETHB_UIO_CLKE (1U << 1) /* CLKE: Clock Enable */
168 #define ETH_MAN_BITS 0x40020000 /* HIGH and CODE bits */
169 #define ETH_MAN_READ (2U << 28)
170 #define ETH_MAN_WRITE (1U << 28)
171 #define ETH_MAN_PHYA_BIT 23
172 #define ETH_MAN_REGA_BIT 18
173 #define ETH_MAN_VALUE_MASK 0xffffU
174 #define ETH_MAN_REG_WR(phy, reg, val) \
175 (ETH_MAN_BITS | ETH_MAN_WRITE | ((phy) << ETH_MAN_PHYA_BIT) | \
176 ((reg) << ETH_MAN_REGA_BIT) | ((val) & ETH_MAN_VALUE_MASK))
177 #define ETH_MAN_REG_RD(phy, reg) \
178 (ETH_MAN_BITS | ETH_MAN_READ | ((phy) << ETH_MAN_PHYA_BIT) | \
179 ((reg) << ETH_MAN_REGA_BIT))
183 #define ETH_CPU_OWNER (1U << 0)
184 #define ETH_WRAP_BIT (1U << 1)
185 #define ETH_ADR_MASK ~(EHT_CPU_OWNER | ETH_WRAP_BIT)
187 #define ETH_LEN_MASK 0x7ff
188 #define ETH_BUF_FIRST (1U << 14) /* Packet matched addr 4 */
189 #define ETH_BUF_LAST (1U << 15) /* Packet matched addr 4 */
190 #define ETH_MAC_LOCAL_4 (1U << 23) /* Packet matched addr 4 */
191 #define ETH_MAC_LOCAL_3 (1U << 24) /* Packet matched addr 3 */
192 #define ETH_MAC_LOCAL_2 (1U << 25) /* Packet matched addr 2 */
193 #define ETH_MAC_LOCAL_1 (1U << 26) /* Packet matched addr 1 */
194 #define ETH_MAC_UNK (1U << 27) /* Unknown source address RFU */
195 #define ETH_MAC_EXT (1U << 28) /* External Address */
196 #define ETH_MAC_UCAST (1U << 29) /* Unicast hash match */
197 #define ETH_MAC_MCAST (1U << 30) /* Multicast hash match */
198 #define ETH_MAC_ONES (1U << 31) /* Global all ones bcast addr */
204 #define ETHB_TX_LEN_MASK 0x7ff
205 #define ETHB_TX_BUF_LAST (1U << 15) /* Last buffer in packet */
206 #define ETHB_TX_NOCRC (1U << 16) /* Don't xmit CRC*/
207 #define ETHB_TX_BUFE (1U << 27) /* Buffers exhausted mid frame */
208 #define ETHB_TX_TUND (1U << 28) /* Transmit Underrun */
209 #define ETHB_TX_RTRYE (1U << 29) /* Re-try limit exceeded */
210 #define ETHB_TX_WRAP (1U << 30) /* Last descritor in list */
211 #define ETHB_TX_USED (1U << 31) /* Packet Transmitted */
214 #endif /* ARM_AT91_IF_ATEREG_H */