2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2005 M. Warner Losh
5 * Copyright (c) 2005 Olivier Houchard
6 * Copyright (c) 2012 Ian Lepore
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
41 #include <machine/bus.h>
43 #include <dev/uart/uart.h>
44 #include <dev/uart/uart_cpu.h>
46 #include <dev/uart/uart_cpu_fdt.h>
48 #include <dev/uart/uart_bus.h>
49 #include <arm/at91/at91_usartreg.h>
50 #include <arm/at91/at91_pdcreg.h>
51 #include <arm/at91/at91_piovar.h>
52 #include <arm/at91/at91_pioreg.h>
53 #include <arm/at91/at91rm92reg.h>
54 #include <arm/at91/at91var.h>
58 #define DEFAULT_RCLK at91_master_clock
59 #define USART_DEFAULT_FIFO_BYTES 128
61 #define USART_DCE_CHANGE_BITS (USART_CSR_CTSIC | USART_CSR_DCDIC | \
62 USART_CSR_DSRIC | USART_CSR_RIIC)
65 * High-level UART interface.
67 struct at91_usart_rx {
73 struct at91_usart_softc {
74 struct uart_softc base;
79 #define HAS_TIMEOUT 0x1
80 #define USE_RTS0_WORKAROUND 0x2
82 struct at91_usart_rx ping_pong[2];
83 struct at91_usart_rx *ping;
84 struct at91_usart_rx *pong;
87 #define RD4(bas, reg) \
88 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
89 #define WR4(bas, reg, value) \
90 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
92 #define SIGCHG(c, i, s, d) \
95 i |= (i & s) ? s : s | d; \
97 i = (i & s) ? (i & ~s) | d : i; \
101 #define BAUD2DIVISOR(b) \
102 ((((DEFAULT_RCLK * 10) / ((b) * 16)) + 5) / 10)
105 * Low-level UART interface.
107 static int at91_usart_probe(struct uart_bas *bas);
108 static void at91_usart_init(struct uart_bas *bas, int, int, int, int);
109 static void at91_usart_term(struct uart_bas *bas);
110 static void at91_usart_putc(struct uart_bas *bas, int);
111 static int at91_usart_rxready(struct uart_bas *bas);
112 static int at91_usart_getc(struct uart_bas *bas, struct mtx *hwmtx);
114 extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
117 at91_usart_param(struct uart_bas *bas, int baudrate, int databits,
118 int stopbits, int parity)
123 * Assume 3-wire RS-232 configuration.
124 * XXX Not sure how uart will present the other modes to us, so
125 * XXX they are unimplemented. maybe ioctl?
127 mr = USART_MR_MODE_NORMAL;
128 mr |= USART_MR_USCLKS_MCK; /* Assume MCK */
131 * Or in the databits requested
134 mr &= ~USART_MR_MODE9;
137 mr |= USART_MR_CHRL_5BITS;
140 mr |= USART_MR_CHRL_6BITS;
143 mr |= USART_MR_CHRL_7BITS;
146 mr |= USART_MR_CHRL_8BITS;
149 mr |= USART_MR_CHRL_8BITS | USART_MR_MODE9;
159 case UART_PARITY_NONE:
160 mr |= USART_MR_PAR_NONE;
162 case UART_PARITY_ODD:
163 mr |= USART_MR_PAR_ODD;
165 case UART_PARITY_EVEN:
166 mr |= USART_MR_PAR_EVEN;
168 case UART_PARITY_MARK:
169 mr |= USART_MR_PAR_MARK;
171 case UART_PARITY_SPACE:
172 mr |= USART_MR_PAR_SPACE;
179 * Or in the stop bits. Note: The hardware supports 1.5 stop
180 * bits in async mode, but there's no way to specify that
181 * AFAICT. Instead, rely on the convention documented at
182 * http://www.lammertbies.nl/comm/info/RS-232_specs.html which
183 * states that 1.5 stop bits are used for 5 bit bytes and
184 * 2 stop bits only for longer bytes.
187 mr |= USART_MR_NBSTOP_1;
188 else if (databits > 5)
189 mr |= USART_MR_NBSTOP_2;
191 mr |= USART_MR_NBSTOP_1_5;
194 * We want normal plumbing mode too, none of this fancy
195 * loopback or echo mode.
197 mr |= USART_MR_CHMODE_NORMAL;
199 mr &= ~USART_MR_MSBF; /* lsb first */
200 mr &= ~USART_MR_CKLO_SCK; /* Don't drive SCK */
202 WR4(bas, USART_MR, mr);
205 * Set the baud rate (only if we know our master clock rate)
207 if (DEFAULT_RCLK != 0)
208 WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate));
211 * Set the receive timeout based on the baud rate. The idea is to
212 * compromise between being responsive on an interactive connection and
213 * giving a bulk data sender a bit of time to queue up a new buffer
214 * without mistaking it for a stopping point in the transmission. For
215 * 19.2kbps and below, use 20 * bit time (2 characters). For faster
216 * connections use 500 microseconds worth of bits.
218 if (baudrate <= 19200)
219 WR4(bas, USART_RTOR, 20);
221 WR4(bas, USART_RTOR, baudrate / 2000);
222 WR4(bas, USART_CR, USART_CR_STTTO);
224 /* XXX Need to take possible synchronous mode into account */
228 static struct uart_ops at91_usart_ops = {
229 .probe = at91_usart_probe,
230 .init = at91_usart_init,
231 .term = at91_usart_term,
232 .putc = at91_usart_putc,
233 .rxready = at91_usart_rxready,
234 .getc = at91_usart_getc,
239 * Early printf support. This assumes that we have the SoC "system" devices
240 * mapped into AT91_BASE. To use this before we adjust the boostrap tables,
241 * you'll need to define SOCDEV_VA to be 0xdc000000 and SOCDEV_PA to be
242 * 0xfc000000 in your config file where you define EARLY_PRINTF
244 volatile uint32_t *at91_dbgu = (volatile uint32_t *)(AT91_BASE + AT91_DBGU0);
250 while (!(at91_dbgu[USART_CSR / 4] & USART_CSR_TXRDY))
252 at91_dbgu[USART_THR / 4] = c;
255 early_putc_t * early_putc = eputc;
259 at91_usart_probe(struct uart_bas *bas)
262 /* We know that this is always here */
267 * Initialize this device for use as a console.
270 at91_usart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
275 if (early_putc != NULL) {
276 printf("Early printf yielding control to the real console.\n");
282 * This routine is called multiple times, sometimes right after writing
283 * some output, and the last byte is still shifting out. If that's the
284 * case delay briefly before resetting, but don't loop on TXRDY because
285 * we don't want to hang here forever if the hardware is in a bad state.
287 if (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY))
290 at91_usart_param(bas, baudrate, databits, stopbits, parity);
292 /* Reset the rx and tx buffers and turn on rx and tx */
293 WR4(bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX);
294 WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
295 WR4(bas, USART_IDR, 0xffffffff);
299 * Free resources now that we're no longer the console. This appears to
300 * be never called, and I'm unsure quite what to do if I am called.
303 at91_usart_term(struct uart_bas *bas)
310 * Put a character of console output (so we do it here polling rather than
314 at91_usart_putc(struct uart_bas *bas, int c)
317 while (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY))
319 WR4(bas, USART_THR, c);
323 * Check for a character available.
326 at91_usart_rxready(struct uart_bas *bas)
329 return ((RD4(bas, USART_CSR) & USART_CSR_RXRDY) != 0 ? 1 : 0);
333 * Block waiting for a character.
336 at91_usart_getc(struct uart_bas *bas, struct mtx *hwmtx)
341 while (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY)) {
346 c = RD4(bas, USART_RHR) & 0xff;
351 static int at91_usart_bus_probe(struct uart_softc *sc);
352 static int at91_usart_bus_attach(struct uart_softc *sc);
353 static int at91_usart_bus_flush(struct uart_softc *, int);
354 static int at91_usart_bus_getsig(struct uart_softc *);
355 static int at91_usart_bus_ioctl(struct uart_softc *, int, intptr_t);
356 static int at91_usart_bus_ipend(struct uart_softc *);
357 static int at91_usart_bus_param(struct uart_softc *, int, int, int, int);
358 static int at91_usart_bus_receive(struct uart_softc *);
359 static int at91_usart_bus_setsig(struct uart_softc *, int);
360 static int at91_usart_bus_transmit(struct uart_softc *);
361 static void at91_usart_bus_grab(struct uart_softc *);
362 static void at91_usart_bus_ungrab(struct uart_softc *);
364 static kobj_method_t at91_usart_methods[] = {
365 KOBJMETHOD(uart_probe, at91_usart_bus_probe),
366 KOBJMETHOD(uart_attach, at91_usart_bus_attach),
367 KOBJMETHOD(uart_flush, at91_usart_bus_flush),
368 KOBJMETHOD(uart_getsig, at91_usart_bus_getsig),
369 KOBJMETHOD(uart_ioctl, at91_usart_bus_ioctl),
370 KOBJMETHOD(uart_ipend, at91_usart_bus_ipend),
371 KOBJMETHOD(uart_param, at91_usart_bus_param),
372 KOBJMETHOD(uart_receive, at91_usart_bus_receive),
373 KOBJMETHOD(uart_setsig, at91_usart_bus_setsig),
374 KOBJMETHOD(uart_transmit, at91_usart_bus_transmit),
375 KOBJMETHOD(uart_grab, at91_usart_bus_grab),
376 KOBJMETHOD(uart_ungrab, at91_usart_bus_ungrab),
382 at91_usart_bus_probe(struct uart_softc *sc)
386 value = USART_DEFAULT_FIFO_BYTES;
387 resource_int_value(device_get_name(sc->sc_dev),
388 device_get_unit(sc->sc_dev), "fifo_bytes", &value);
389 value = roundup2(value, arm_dcache_align);
390 sc->sc_txfifosz = value;
391 sc->sc_rxfifosz = value;
397 at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
402 *(bus_addr_t *)arg = segs[0].ds_addr;
406 at91_usart_requires_rts0_workaround(struct uart_softc *sc)
411 unit = device_get_unit(sc->sc_dev);
414 * On the rm9200 chips, the PA21/RTS0 pin is not correctly wired to the
415 * usart device interally (so-called 'erratum 39', but it's 41.14 in rev
416 * I of the manual). This prevents use of the hardware flow control
417 * feature in the usart itself. It also means that if we are to
418 * implement RTS/CTS flow via the tty layer logic, we must use pin PA21
419 * as a gpio and manually manipulate it in at91_usart_bus_setsig(). We
420 * can only safely do so if we've been given permission via a hint,
421 * otherwise we might manipulate a pin that's attached to who-knows-what
422 * and Bad Things could happen.
424 if (at91_is_rm92() && unit == 1) {
426 resource_int_value(device_get_name(sc->sc_dev), unit,
427 "use_rts0_workaround", &value);
429 at91_pio_use_gpio(AT91RM92_PIOA_BASE, AT91C_PIO_PA21);
430 at91_pio_gpio_output(AT91RM92_PIOA_BASE,
432 at91_pio_use_periph_a(AT91RM92_PIOA_BASE,
441 at91_usart_bus_attach(struct uart_softc *sc)
445 struct at91_usart_softc *atsc;
447 atsc = (struct at91_usart_softc *)sc;
449 if (at91_usart_requires_rts0_workaround(sc))
450 atsc->flags |= USE_RTS0_WORKAROUND;
453 * See if we have a TIMEOUT bit. We disable all interrupts as
454 * a side effect. Boot loaders may have enabled them. Since
455 * a TIMEOUT interrupt can't happen without other setup, the
456 * apparent race here can't actually happen.
458 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
459 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT);
460 if (RD4(&sc->sc_bas, USART_IMR) & USART_CSR_TIMEOUT)
461 atsc->flags |= HAS_TIMEOUT;
462 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
465 * Allocate transmit DMA tag and map. We allow a transmit buffer
466 * to be any size, but it must map to a single contiguous physical
469 err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
470 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
471 BUS_SPACE_MAXSIZE_32BIT, 1, BUS_SPACE_MAXSIZE_32BIT, 0, NULL,
472 NULL, &atsc->tx_tag);
475 err = bus_dmamap_create(atsc->tx_tag, 0, &atsc->tx_map);
478 if (bus_dmamap_load(atsc->tx_tag, atsc->tx_map, sc->sc_txbuf,
479 sc->sc_txfifosz, at91_getaddr, &atsc->tx_paddr, 0) != 0)
482 if (atsc->flags & HAS_TIMEOUT) {
484 * Allocate receive DMA tags, maps, and buffers.
485 * The receive buffers should be aligned to arm_dcache_align,
486 * otherwise partial cache line flushes on every receive
487 * interrupt are pretty much guaranteed.
489 err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),
490 arm_dcache_align, 0, BUS_SPACE_MAXADDR_32BIT,
491 BUS_SPACE_MAXADDR, NULL, NULL, sc->sc_rxfifosz, 1,
492 sc->sc_rxfifosz, BUS_DMA_ALLOCNOW, NULL, NULL,
496 for (i = 0; i < 2; i++) {
497 err = bus_dmamem_alloc(atsc->rx_tag,
498 (void **)&atsc->ping_pong[i].buffer,
499 BUS_DMA_NOWAIT, &atsc->ping_pong[i].map);
502 err = bus_dmamap_load(atsc->rx_tag,
503 atsc->ping_pong[i].map,
504 atsc->ping_pong[i].buffer, sc->sc_rxfifosz,
505 at91_getaddr, &atsc->ping_pong[i].pa, 0);
508 bus_dmamap_sync(atsc->rx_tag, atsc->ping_pong[i].map,
509 BUS_DMASYNC_PREREAD);
511 atsc->ping = &atsc->ping_pong[0];
512 atsc->pong = &atsc->ping_pong[1];
515 /* Turn on rx and tx */
516 DELAY(1000); /* Give pending character a chance to drain. */
517 WR4(&sc->sc_bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX);
518 WR4(&sc->sc_bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
521 * Setup the PDC to receive data. We use the ping-pong buffers
522 * so that we can more easily bounce between the two and so that
523 * we get an interrupt 1/2 way through the software 'fifo' we have
526 if (atsc->flags & HAS_TIMEOUT) {
527 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
528 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
529 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
530 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
531 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
534 * Set the receive timeout to be 1.5 character times
537 WR4(&sc->sc_bas, USART_RTOR, 15);
538 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
539 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT |
540 USART_CSR_RXBUFF | USART_CSR_ENDRX);
542 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY);
544 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXBRK | USART_DCE_CHANGE_BITS);
546 /* Prime sc->hwsig with the initial hw line states. */
547 at91_usart_bus_getsig(sc);
554 at91_usart_bus_transmit(struct uart_softc *sc)
556 struct at91_usart_softc *atsc;
560 atsc = (struct at91_usart_softc *)sc;
561 uart_lock(sc->sc_hwmtx);
562 bus_dmamap_sync(atsc->tx_tag, atsc->tx_map, BUS_DMASYNC_PREWRITE);
565 * Setup the PDC to transfer the data and interrupt us when it
566 * is done. We've already requested the interrupt.
568 WR4(&sc->sc_bas, PDC_TPR, atsc->tx_paddr);
569 WR4(&sc->sc_bas, PDC_TCR, sc->sc_txdatasz);
570 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_TXTEN);
571 WR4(&sc->sc_bas, USART_IER, USART_CSR_ENDTX);
572 uart_unlock(sc->sc_hwmtx);
577 at91_usart_bus_setsig(struct uart_softc *sc, int sig)
579 uint32_t new, old, cr;
580 struct at91_usart_softc *atsc;
582 atsc = (struct at91_usart_softc *)sc;
588 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR);
590 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS);
591 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
595 cr |= USART_CR_DTREN;
597 cr |= USART_CR_DTRDIS;
599 cr |= USART_CR_RTSEN;
601 cr |= USART_CR_RTSDIS;
603 uart_lock(sc->sc_hwmtx);
604 WR4(&sc->sc_bas, USART_CR, cr);
605 if (atsc->flags & USE_RTS0_WORKAROUND) {
606 /* Signal is active-low. */
608 at91_pio_gpio_clear(AT91RM92_PIOA_BASE, AT91C_PIO_PA21);
610 at91_pio_gpio_set(AT91RM92_PIOA_BASE,AT91C_PIO_PA21);
612 uart_unlock(sc->sc_hwmtx);
618 at91_usart_bus_receive(struct uart_softc *sc)
625 at91_usart_bus_param(struct uart_softc *sc, int baudrate, int databits,
626 int stopbits, int parity)
629 return (at91_usart_param(&sc->sc_bas, baudrate, databits, stopbits,
634 at91_rx_put(struct uart_softc *sc, int key)
638 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE)
639 kdb_alt_break(key, &sc->sc_altbrk);
641 uart_rx_put(sc, key);
645 at91_usart_bus_ipend(struct uart_softc *sc)
647 struct at91_usart_softc *atsc;
648 struct at91_usart_rx *p;
653 atsc = (struct at91_usart_softc *)sc;
654 uart_lock(sc->sc_hwmtx);
655 csr = RD4(&sc->sc_bas, USART_CSR);
657 if (csr & USART_CSR_OVRE) {
658 WR4(&sc->sc_bas, USART_CR, USART_CR_RSTSTA);
659 ipend |= SER_INT_OVERRUN;
662 if (csr & USART_DCE_CHANGE_BITS)
663 ipend |= SER_INT_SIGCHG;
665 if (csr & USART_CSR_ENDTX) {
666 bus_dmamap_sync(atsc->tx_tag, atsc->tx_map,
667 BUS_DMASYNC_POSTWRITE);
669 if (csr & (USART_CSR_TXRDY | USART_CSR_ENDTX)) {
671 ipend |= SER_INT_TXIDLE;
672 WR4(&sc->sc_bas, USART_IDR, csr & (USART_CSR_TXRDY |
677 * Due to the contraints of the DMA engine present in the
678 * atmel chip, I can't just say I have a rx interrupt pending
679 * and do all the work elsewhere. I need to look at the CSR
680 * bits right now and do things based on them to avoid races.
682 if (atsc->flags & HAS_TIMEOUT) {
683 if (csr & USART_CSR_RXBUFF) {
685 * We have a buffer overflow. Consume data from ping
686 * and give it back to the hardware before worrying
687 * about pong, to minimze data loss. Insert an overrun
688 * marker after the contents of the pong buffer.
690 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS);
691 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
692 BUS_DMASYNC_POSTREAD);
693 for (i = 0; i < sc->sc_rxfifosz; i++)
694 at91_rx_put(sc, atsc->ping->buffer[i]);
695 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
696 BUS_DMASYNC_PREREAD);
697 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
698 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
699 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
700 bus_dmamap_sync(atsc->rx_tag, atsc->pong->map,
701 BUS_DMASYNC_POSTREAD);
702 for (i = 0; i < sc->sc_rxfifosz; i++)
703 at91_rx_put(sc, atsc->pong->buffer[i]);
704 uart_rx_put(sc, UART_STAT_OVERRUN);
705 bus_dmamap_sync(atsc->rx_tag, atsc->pong->map,
706 BUS_DMASYNC_PREREAD);
707 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
708 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
709 ipend |= SER_INT_RXREADY;
710 } else if (csr & USART_CSR_ENDRX) {
712 * Consume data from ping of ping pong buffer, but leave
713 * current pong in place, as it has become the new ping.
714 * We need to copy data and setup the old ping as the
715 * new pong when we're done.
717 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
718 BUS_DMASYNC_POSTREAD);
719 for (i = 0; i < sc->sc_rxfifosz; i++)
720 at91_rx_put(sc, atsc->ping->buffer[i]);
722 atsc->ping = atsc->pong;
724 bus_dmamap_sync(atsc->rx_tag, atsc->pong->map,
725 BUS_DMASYNC_PREREAD);
726 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
727 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
728 ipend |= SER_INT_RXREADY;
729 } else if (csr & USART_CSR_TIMEOUT) {
731 * On a timeout, one of the following applies:
732 * 1. Two empty buffers. The last received byte exactly
733 * filled a buffer, causing an ENDTX that got
734 * processed earlier; no new bytes have arrived.
735 * 2. Ping buffer contains some data and pong is empty.
736 * This should be the most common timeout condition.
737 * 3. Ping buffer is full and pong is now being filled.
738 * This is exceedingly rare; it can happen only if
739 * the ping buffer is almost full when a timeout is
740 * signaled, and then dataflow resumes and the ping
741 * buffer filled up between the time we read the
742 * status register above and the point where the
743 * RXTDIS takes effect here. Yes, it can happen.
744 * Because dataflow can resume at any time following a
745 * timeout (it may have already resumed before we get
746 * here), it's important to minimize the time the PDC is
747 * disabled -- just long enough to take the ping buffer
748 * out of service (so we can consume it) and install the
749 * pong buffer as the active one. Note that in case 3
750 * the hardware has already done the ping-pong swap.
752 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS);
753 if (RD4(&sc->sc_bas, PDC_RNCR) == 0) {
754 len = sc->sc_rxfifosz;
756 len = sc->sc_rxfifosz - RD4(&sc->sc_bas, PDC_RCR);
757 WR4(&sc->sc_bas, PDC_RPR, atsc->pong->pa);
758 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
759 WR4(&sc->sc_bas, PDC_RNCR, 0);
761 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
762 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
763 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
764 BUS_DMASYNC_POSTREAD);
765 for (i = 0; i < len; i++)
766 at91_rx_put(sc, atsc->ping->buffer[i]);
767 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
768 BUS_DMASYNC_PREREAD);
770 atsc->ping = atsc->pong;
772 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
773 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
774 ipend |= SER_INT_RXREADY;
776 } else if (csr & USART_CSR_RXRDY) {
778 * We have another charater in a device that doesn't support
779 * timeouts, so we do it one character at a time.
781 at91_rx_put(sc, RD4(&sc->sc_bas, USART_RHR) & 0xff);
782 ipend |= SER_INT_RXREADY;
785 if (csr & USART_CSR_RXBRK) {
786 ipend |= SER_INT_BREAK;
787 WR4(&sc->sc_bas, USART_CR, USART_CR_RSTSTA);
789 uart_unlock(sc->sc_hwmtx);
794 at91_usart_bus_flush(struct uart_softc *sc, int what)
801 at91_usart_bus_getsig(struct uart_softc *sc)
803 uint32_t csr, new, old, sig;
806 * Note that the atmel channel status register DCE status bits reflect
807 * the electrical state of the lines, not the logical state. Since they
808 * are logically active-low signals, we invert the tests here.
813 csr = RD4(&sc->sc_bas, USART_CSR);
814 SIGCHG(!(csr & USART_CSR_DSR), sig, SER_DSR, SER_DDSR);
815 SIGCHG(!(csr & USART_CSR_CTS), sig, SER_CTS, SER_DCTS);
816 SIGCHG(!(csr & USART_CSR_DCD), sig, SER_DCD, SER_DDCD);
817 SIGCHG(!(csr & USART_CSR_RI), sig, SER_RI, SER_DRI);
818 new = sig & ~SER_MASK_DELTA;
819 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
825 at91_usart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
829 case UART_IOCTL_BREAK:
830 case UART_IOCTL_IFLOW:
831 case UART_IOCTL_OFLOW:
833 case UART_IOCTL_BAUD:
834 /* only if we know our master clock rate */
835 if (DEFAULT_RCLK != 0)
836 WR4(&sc->sc_bas, USART_BRGR,
837 BAUD2DIVISOR(*(int *)data));
845 at91_usart_bus_grab(struct uart_softc *sc)
848 uart_lock(sc->sc_hwmtx);
849 WR4(&sc->sc_bas, USART_IDR, USART_CSR_RXRDY);
850 uart_unlock(sc->sc_hwmtx);
854 at91_usart_bus_ungrab(struct uart_softc *sc)
857 uart_lock(sc->sc_hwmtx);
858 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY);
859 uart_unlock(sc->sc_hwmtx);
862 struct uart_class at91_usart_class = {
865 sizeof(struct at91_usart_softc),
866 .uc_ops = &at91_usart_ops,
871 static struct ofw_compat_data compat_data[] = {
872 {"atmel,at91rm9200-usart",(uintptr_t)&at91_usart_class},
873 {"atmel,at91sam9260-usart",(uintptr_t)&at91_usart_class},
874 {NULL, (uintptr_t)NULL},
876 UART_FDT_CLASS_AND_DEVICE(compat_data);