2 * Copyright (c) 2005 M. Warner Losh
3 * Copyright (c) 2005 Olivier Houchard
4 * Copyright (c) 2012 Ian Lepore
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
39 #include <machine/bus.h>
41 #include <dev/uart/uart.h>
42 #include <dev/uart/uart_cpu.h>
44 #include <dev/uart/uart_cpu_fdt.h>
46 #include <dev/uart/uart_bus.h>
47 #include <arm/at91/at91_usartreg.h>
48 #include <arm/at91/at91_pdcreg.h>
49 #include <arm/at91/at91_piovar.h>
50 #include <arm/at91/at91_pioreg.h>
51 #include <arm/at91/at91rm92reg.h>
52 #include <arm/at91/at91var.h>
56 #define DEFAULT_RCLK at91_master_clock
57 #define USART_DEFAULT_FIFO_BYTES 128
59 #define USART_DCE_CHANGE_BITS (USART_CSR_CTSIC | USART_CSR_DCDIC | \
60 USART_CSR_DSRIC | USART_CSR_RIIC)
63 * High-level UART interface.
65 struct at91_usart_rx {
71 struct at91_usart_softc {
72 struct uart_softc base;
77 #define HAS_TIMEOUT 0x1
78 #define USE_RTS0_WORKAROUND 0x2
80 struct at91_usart_rx ping_pong[2];
81 struct at91_usart_rx *ping;
82 struct at91_usart_rx *pong;
85 #define RD4(bas, reg) \
86 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
87 #define WR4(bas, reg, value) \
88 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
90 #define SIGCHG(c, i, s, d) \
93 i |= (i & s) ? s : s | d; \
95 i = (i & s) ? (i & ~s) | d : i; \
99 #define BAUD2DIVISOR(b) \
100 ((((DEFAULT_RCLK * 10) / ((b) * 16)) + 5) / 10)
103 * Low-level UART interface.
105 static int at91_usart_probe(struct uart_bas *bas);
106 static void at91_usart_init(struct uart_bas *bas, int, int, int, int);
107 static void at91_usart_term(struct uart_bas *bas);
108 static void at91_usart_putc(struct uart_bas *bas, int);
109 static int at91_usart_rxready(struct uart_bas *bas);
110 static int at91_usart_getc(struct uart_bas *bas, struct mtx *hwmtx);
112 extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
115 at91_usart_param(struct uart_bas *bas, int baudrate, int databits,
116 int stopbits, int parity)
121 * Assume 3-wire RS-232 configuration.
122 * XXX Not sure how uart will present the other modes to us, so
123 * XXX they are unimplemented. maybe ioctl?
125 mr = USART_MR_MODE_NORMAL;
126 mr |= USART_MR_USCLKS_MCK; /* Assume MCK */
129 * Or in the databits requested
132 mr &= ~USART_MR_MODE9;
135 mr |= USART_MR_CHRL_5BITS;
138 mr |= USART_MR_CHRL_6BITS;
141 mr |= USART_MR_CHRL_7BITS;
144 mr |= USART_MR_CHRL_8BITS;
147 mr |= USART_MR_CHRL_8BITS | USART_MR_MODE9;
157 case UART_PARITY_NONE:
158 mr |= USART_MR_PAR_NONE;
160 case UART_PARITY_ODD:
161 mr |= USART_MR_PAR_ODD;
163 case UART_PARITY_EVEN:
164 mr |= USART_MR_PAR_EVEN;
166 case UART_PARITY_MARK:
167 mr |= USART_MR_PAR_MARK;
169 case UART_PARITY_SPACE:
170 mr |= USART_MR_PAR_SPACE;
177 * Or in the stop bits. Note: The hardware supports 1.5 stop
178 * bits in async mode, but there's no way to specify that
179 * AFAICT. Instead, rely on the convention documented at
180 * http://www.lammertbies.nl/comm/info/RS-232_specs.html which
181 * states that 1.5 stop bits are used for 5 bit bytes and
182 * 2 stop bits only for longer bytes.
185 mr |= USART_MR_NBSTOP_1;
186 else if (databits > 5)
187 mr |= USART_MR_NBSTOP_2;
189 mr |= USART_MR_NBSTOP_1_5;
192 * We want normal plumbing mode too, none of this fancy
193 * loopback or echo mode.
195 mr |= USART_MR_CHMODE_NORMAL;
197 mr &= ~USART_MR_MSBF; /* lsb first */
198 mr &= ~USART_MR_CKLO_SCK; /* Don't drive SCK */
200 WR4(bas, USART_MR, mr);
203 * Set the baud rate (only if we know our master clock rate)
205 if (DEFAULT_RCLK != 0)
206 WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate));
209 * Set the receive timeout based on the baud rate. The idea is to
210 * compromise between being responsive on an interactive connection and
211 * giving a bulk data sender a bit of time to queue up a new buffer
212 * without mistaking it for a stopping point in the transmission. For
213 * 19.2kbps and below, use 20 * bit time (2 characters). For faster
214 * connections use 500 microseconds worth of bits.
216 if (baudrate <= 19200)
217 WR4(bas, USART_RTOR, 20);
219 WR4(bas, USART_RTOR, baudrate / 2000);
220 WR4(bas, USART_CR, USART_CR_STTTO);
222 /* XXX Need to take possible synchronous mode into account */
226 static struct uart_ops at91_usart_ops = {
227 .probe = at91_usart_probe,
228 .init = at91_usart_init,
229 .term = at91_usart_term,
230 .putc = at91_usart_putc,
231 .rxready = at91_usart_rxready,
232 .getc = at91_usart_getc,
237 * Early printf support. This assumes that we have the SoC "system" devices
238 * mapped into AT91_BASE. To use this before we adjust the boostrap tables,
239 * you'll need to define SOCDEV_VA to be 0xdc000000 and SOCDEV_PA to be
240 * 0xfc000000 in your config file where you define EARLY_PRINTF
242 volatile uint32_t *at91_dbgu = (volatile uint32_t *)(AT91_BASE + AT91_DBGU0);
248 while (!(at91_dbgu[USART_CSR / 4] & USART_CSR_TXRDY))
250 at91_dbgu[USART_THR / 4] = c;
253 early_putc_t * early_putc = eputc;
257 at91_usart_probe(struct uart_bas *bas)
260 /* We know that this is always here */
265 * Initialize this device for use as a console.
268 at91_usart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
273 if (early_putc != NULL) {
274 printf("Early printf yielding control to the real console.\n");
280 * This routine is called multiple times, sometimes right after writing
281 * some output, and the last byte is still shifting out. If that's the
282 * case delay briefly before resetting, but don't loop on TXRDY because
283 * we don't want to hang here forever if the hardware is in a bad state.
285 if (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY))
288 at91_usart_param(bas, baudrate, databits, stopbits, parity);
290 /* Reset the rx and tx buffers and turn on rx and tx */
291 WR4(bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX);
292 WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
293 WR4(bas, USART_IDR, 0xffffffff);
297 * Free resources now that we're no longer the console. This appears to
298 * be never called, and I'm unsure quite what to do if I am called.
301 at91_usart_term(struct uart_bas *bas)
308 * Put a character of console output (so we do it here polling rather than
312 at91_usart_putc(struct uart_bas *bas, int c)
315 while (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY))
317 WR4(bas, USART_THR, c);
321 * Check for a character available.
324 at91_usart_rxready(struct uart_bas *bas)
327 return ((RD4(bas, USART_CSR) & USART_CSR_RXRDY) != 0 ? 1 : 0);
331 * Block waiting for a character.
334 at91_usart_getc(struct uart_bas *bas, struct mtx *hwmtx)
339 while (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY)) {
344 c = RD4(bas, USART_RHR) & 0xff;
349 static int at91_usart_bus_probe(struct uart_softc *sc);
350 static int at91_usart_bus_attach(struct uart_softc *sc);
351 static int at91_usart_bus_flush(struct uart_softc *, int);
352 static int at91_usart_bus_getsig(struct uart_softc *);
353 static int at91_usart_bus_ioctl(struct uart_softc *, int, intptr_t);
354 static int at91_usart_bus_ipend(struct uart_softc *);
355 static int at91_usart_bus_param(struct uart_softc *, int, int, int, int);
356 static int at91_usart_bus_receive(struct uart_softc *);
357 static int at91_usart_bus_setsig(struct uart_softc *, int);
358 static int at91_usart_bus_transmit(struct uart_softc *);
359 static void at91_usart_bus_grab(struct uart_softc *);
360 static void at91_usart_bus_ungrab(struct uart_softc *);
362 static kobj_method_t at91_usart_methods[] = {
363 KOBJMETHOD(uart_probe, at91_usart_bus_probe),
364 KOBJMETHOD(uart_attach, at91_usart_bus_attach),
365 KOBJMETHOD(uart_flush, at91_usart_bus_flush),
366 KOBJMETHOD(uart_getsig, at91_usart_bus_getsig),
367 KOBJMETHOD(uart_ioctl, at91_usart_bus_ioctl),
368 KOBJMETHOD(uart_ipend, at91_usart_bus_ipend),
369 KOBJMETHOD(uart_param, at91_usart_bus_param),
370 KOBJMETHOD(uart_receive, at91_usart_bus_receive),
371 KOBJMETHOD(uart_setsig, at91_usart_bus_setsig),
372 KOBJMETHOD(uart_transmit, at91_usart_bus_transmit),
373 KOBJMETHOD(uart_grab, at91_usart_bus_grab),
374 KOBJMETHOD(uart_ungrab, at91_usart_bus_ungrab),
380 at91_usart_bus_probe(struct uart_softc *sc)
384 value = USART_DEFAULT_FIFO_BYTES;
385 resource_int_value(device_get_name(sc->sc_dev),
386 device_get_unit(sc->sc_dev), "fifo_bytes", &value);
387 value = roundup2(value, arm_dcache_align);
388 sc->sc_txfifosz = value;
389 sc->sc_rxfifosz = value;
395 at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
400 *(bus_addr_t *)arg = segs[0].ds_addr;
404 at91_usart_requires_rts0_workaround(struct uart_softc *sc)
409 unit = device_get_unit(sc->sc_dev);
412 * On the rm9200 chips, the PA21/RTS0 pin is not correctly wired to the
413 * usart device interally (so-called 'erratum 39', but it's 41.14 in rev
414 * I of the manual). This prevents use of the hardware flow control
415 * feature in the usart itself. It also means that if we are to
416 * implement RTS/CTS flow via the tty layer logic, we must use pin PA21
417 * as a gpio and manually manipulate it in at91_usart_bus_setsig(). We
418 * can only safely do so if we've been given permission via a hint,
419 * otherwise we might manipulate a pin that's attached to who-knows-what
420 * and Bad Things could happen.
422 if (at91_is_rm92() && unit == 1) {
424 resource_int_value(device_get_name(sc->sc_dev), unit,
425 "use_rts0_workaround", &value);
427 at91_pio_use_gpio(AT91RM92_PIOA_BASE, AT91C_PIO_PA21);
428 at91_pio_gpio_output(AT91RM92_PIOA_BASE,
430 at91_pio_use_periph_a(AT91RM92_PIOA_BASE,
439 at91_usart_bus_attach(struct uart_softc *sc)
443 struct at91_usart_softc *atsc;
445 atsc = (struct at91_usart_softc *)sc;
447 if (at91_usart_requires_rts0_workaround(sc))
448 atsc->flags |= USE_RTS0_WORKAROUND;
451 * See if we have a TIMEOUT bit. We disable all interrupts as
452 * a side effect. Boot loaders may have enabled them. Since
453 * a TIMEOUT interrupt can't happen without other setup, the
454 * apparent race here can't actually happen.
456 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
457 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT);
458 if (RD4(&sc->sc_bas, USART_IMR) & USART_CSR_TIMEOUT)
459 atsc->flags |= HAS_TIMEOUT;
460 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
463 * Allocate transmit DMA tag and map. We allow a transmit buffer
464 * to be any size, but it must map to a single contiguous physical
467 err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
468 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
469 BUS_SPACE_MAXSIZE_32BIT, 1, BUS_SPACE_MAXSIZE_32BIT, 0, NULL,
470 NULL, &atsc->tx_tag);
473 err = bus_dmamap_create(atsc->tx_tag, 0, &atsc->tx_map);
476 if (bus_dmamap_load(atsc->tx_tag, atsc->tx_map, sc->sc_txbuf,
477 sc->sc_txfifosz, at91_getaddr, &atsc->tx_paddr, 0) != 0)
480 if (atsc->flags & HAS_TIMEOUT) {
482 * Allocate receive DMA tags, maps, and buffers.
483 * The receive buffers should be aligned to arm_dcache_align,
484 * otherwise partial cache line flushes on every receive
485 * interrupt are pretty much guaranteed.
487 err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),
488 arm_dcache_align, 0, BUS_SPACE_MAXADDR_32BIT,
489 BUS_SPACE_MAXADDR, NULL, NULL, sc->sc_rxfifosz, 1,
490 sc->sc_rxfifosz, BUS_DMA_ALLOCNOW, NULL, NULL,
494 for (i = 0; i < 2; i++) {
495 err = bus_dmamem_alloc(atsc->rx_tag,
496 (void **)&atsc->ping_pong[i].buffer,
497 BUS_DMA_NOWAIT, &atsc->ping_pong[i].map);
500 err = bus_dmamap_load(atsc->rx_tag,
501 atsc->ping_pong[i].map,
502 atsc->ping_pong[i].buffer, sc->sc_rxfifosz,
503 at91_getaddr, &atsc->ping_pong[i].pa, 0);
506 bus_dmamap_sync(atsc->rx_tag, atsc->ping_pong[i].map,
507 BUS_DMASYNC_PREREAD);
509 atsc->ping = &atsc->ping_pong[0];
510 atsc->pong = &atsc->ping_pong[1];
513 /* Turn on rx and tx */
514 DELAY(1000); /* Give pending character a chance to drain. */
515 WR4(&sc->sc_bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX);
516 WR4(&sc->sc_bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
519 * Setup the PDC to receive data. We use the ping-pong buffers
520 * so that we can more easily bounce between the two and so that
521 * we get an interrupt 1/2 way through the software 'fifo' we have
524 if (atsc->flags & HAS_TIMEOUT) {
525 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
526 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
527 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
528 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
529 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
532 * Set the receive timeout to be 1.5 character times
535 WR4(&sc->sc_bas, USART_RTOR, 15);
536 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
537 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT |
538 USART_CSR_RXBUFF | USART_CSR_ENDRX);
540 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY);
542 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXBRK | USART_DCE_CHANGE_BITS);
544 /* Prime sc->hwsig with the initial hw line states. */
545 at91_usart_bus_getsig(sc);
552 at91_usart_bus_transmit(struct uart_softc *sc)
554 struct at91_usart_softc *atsc;
558 atsc = (struct at91_usart_softc *)sc;
559 uart_lock(sc->sc_hwmtx);
560 bus_dmamap_sync(atsc->tx_tag, atsc->tx_map, BUS_DMASYNC_PREWRITE);
563 * Setup the PDC to transfer the data and interrupt us when it
564 * is done. We've already requested the interrupt.
566 WR4(&sc->sc_bas, PDC_TPR, atsc->tx_paddr);
567 WR4(&sc->sc_bas, PDC_TCR, sc->sc_txdatasz);
568 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_TXTEN);
569 WR4(&sc->sc_bas, USART_IER, USART_CSR_ENDTX);
570 uart_unlock(sc->sc_hwmtx);
575 at91_usart_bus_setsig(struct uart_softc *sc, int sig)
577 uint32_t new, old, cr;
578 struct at91_usart_softc *atsc;
580 atsc = (struct at91_usart_softc *)sc;
586 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR);
588 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS);
589 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
593 cr |= USART_CR_DTREN;
595 cr |= USART_CR_DTRDIS;
597 cr |= USART_CR_RTSEN;
599 cr |= USART_CR_RTSDIS;
601 uart_lock(sc->sc_hwmtx);
602 WR4(&sc->sc_bas, USART_CR, cr);
603 if (atsc->flags & USE_RTS0_WORKAROUND) {
604 /* Signal is active-low. */
606 at91_pio_gpio_clear(AT91RM92_PIOA_BASE, AT91C_PIO_PA21);
608 at91_pio_gpio_set(AT91RM92_PIOA_BASE,AT91C_PIO_PA21);
610 uart_unlock(sc->sc_hwmtx);
616 at91_usart_bus_receive(struct uart_softc *sc)
623 at91_usart_bus_param(struct uart_softc *sc, int baudrate, int databits,
624 int stopbits, int parity)
627 return (at91_usart_param(&sc->sc_bas, baudrate, databits, stopbits,
632 at91_rx_put(struct uart_softc *sc, int key)
636 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE)
637 kdb_alt_break(key, &sc->sc_altbrk);
639 uart_rx_put(sc, key);
643 at91_usart_bus_ipend(struct uart_softc *sc)
645 struct at91_usart_softc *atsc;
646 struct at91_usart_rx *p;
651 atsc = (struct at91_usart_softc *)sc;
652 uart_lock(sc->sc_hwmtx);
653 csr = RD4(&sc->sc_bas, USART_CSR);
655 if (csr & USART_CSR_OVRE) {
656 WR4(&sc->sc_bas, USART_CR, USART_CR_RSTSTA);
657 ipend |= SER_INT_OVERRUN;
660 if (csr & USART_DCE_CHANGE_BITS)
661 ipend |= SER_INT_SIGCHG;
663 if (csr & USART_CSR_ENDTX) {
664 bus_dmamap_sync(atsc->tx_tag, atsc->tx_map,
665 BUS_DMASYNC_POSTWRITE);
667 if (csr & (USART_CSR_TXRDY | USART_CSR_ENDTX)) {
669 ipend |= SER_INT_TXIDLE;
670 WR4(&sc->sc_bas, USART_IDR, csr & (USART_CSR_TXRDY |
675 * Due to the contraints of the DMA engine present in the
676 * atmel chip, I can't just say I have a rx interrupt pending
677 * and do all the work elsewhere. I need to look at the CSR
678 * bits right now and do things based on them to avoid races.
680 if (atsc->flags & HAS_TIMEOUT) {
681 if (csr & USART_CSR_RXBUFF) {
683 * We have a buffer overflow. Consume data from ping
684 * and give it back to the hardware before worrying
685 * about pong, to minimze data loss. Insert an overrun
686 * marker after the contents of the pong buffer.
688 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS);
689 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
690 BUS_DMASYNC_POSTREAD);
691 for (i = 0; i < sc->sc_rxfifosz; i++)
692 at91_rx_put(sc, atsc->ping->buffer[i]);
693 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
694 BUS_DMASYNC_PREREAD);
695 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
696 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
697 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
698 bus_dmamap_sync(atsc->rx_tag, atsc->pong->map,
699 BUS_DMASYNC_POSTREAD);
700 for (i = 0; i < sc->sc_rxfifosz; i++)
701 at91_rx_put(sc, atsc->pong->buffer[i]);
702 uart_rx_put(sc, UART_STAT_OVERRUN);
703 bus_dmamap_sync(atsc->rx_tag, atsc->pong->map,
704 BUS_DMASYNC_PREREAD);
705 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
706 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
707 ipend |= SER_INT_RXREADY;
708 } else if (csr & USART_CSR_ENDRX) {
710 * Consume data from ping of ping pong buffer, but leave
711 * current pong in place, as it has become the new ping.
712 * We need to copy data and setup the old ping as the
713 * new pong when we're done.
715 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
716 BUS_DMASYNC_POSTREAD);
717 for (i = 0; i < sc->sc_rxfifosz; i++)
718 at91_rx_put(sc, atsc->ping->buffer[i]);
720 atsc->ping = atsc->pong;
722 bus_dmamap_sync(atsc->rx_tag, atsc->pong->map,
723 BUS_DMASYNC_PREREAD);
724 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
725 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
726 ipend |= SER_INT_RXREADY;
727 } else if (csr & USART_CSR_TIMEOUT) {
729 * On a timeout, one of the following applies:
730 * 1. Two empty buffers. The last received byte exactly
731 * filled a buffer, causing an ENDTX that got
732 * processed earlier; no new bytes have arrived.
733 * 2. Ping buffer contains some data and pong is empty.
734 * This should be the most common timeout condition.
735 * 3. Ping buffer is full and pong is now being filled.
736 * This is exceedingly rare; it can happen only if
737 * the ping buffer is almost full when a timeout is
738 * signaled, and then dataflow resumes and the ping
739 * buffer filled up between the time we read the
740 * status register above and the point where the
741 * RXTDIS takes effect here. Yes, it can happen.
742 * Because dataflow can resume at any time following a
743 * timeout (it may have already resumed before we get
744 * here), it's important to minimize the time the PDC is
745 * disabled -- just long enough to take the ping buffer
746 * out of service (so we can consume it) and install the
747 * pong buffer as the active one. Note that in case 3
748 * the hardware has already done the ping-pong swap.
750 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS);
751 if (RD4(&sc->sc_bas, PDC_RNCR) == 0) {
752 len = sc->sc_rxfifosz;
754 len = sc->sc_rxfifosz - RD4(&sc->sc_bas, PDC_RCR);
755 WR4(&sc->sc_bas, PDC_RPR, atsc->pong->pa);
756 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
757 WR4(&sc->sc_bas, PDC_RNCR, 0);
759 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
760 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
761 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
762 BUS_DMASYNC_POSTREAD);
763 for (i = 0; i < len; i++)
764 at91_rx_put(sc, atsc->ping->buffer[i]);
765 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
766 BUS_DMASYNC_PREREAD);
768 atsc->ping = atsc->pong;
770 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
771 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
772 ipend |= SER_INT_RXREADY;
774 } else if (csr & USART_CSR_RXRDY) {
776 * We have another charater in a device that doesn't support
777 * timeouts, so we do it one character at a time.
779 at91_rx_put(sc, RD4(&sc->sc_bas, USART_RHR) & 0xff);
780 ipend |= SER_INT_RXREADY;
783 if (csr & USART_CSR_RXBRK) {
784 ipend |= SER_INT_BREAK;
785 WR4(&sc->sc_bas, USART_CR, USART_CR_RSTSTA);
787 uart_unlock(sc->sc_hwmtx);
792 at91_usart_bus_flush(struct uart_softc *sc, int what)
799 at91_usart_bus_getsig(struct uart_softc *sc)
801 uint32_t csr, new, old, sig;
804 * Note that the atmel channel status register DCE status bits reflect
805 * the electrical state of the lines, not the logical state. Since they
806 * are logically active-low signals, we invert the tests here.
811 csr = RD4(&sc->sc_bas, USART_CSR);
812 SIGCHG(!(csr & USART_CSR_DSR), sig, SER_DSR, SER_DDSR);
813 SIGCHG(!(csr & USART_CSR_CTS), sig, SER_CTS, SER_DCTS);
814 SIGCHG(!(csr & USART_CSR_DCD), sig, SER_DCD, SER_DDCD);
815 SIGCHG(!(csr & USART_CSR_RI), sig, SER_RI, SER_DRI);
816 new = sig & ~SER_MASK_DELTA;
817 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
823 at91_usart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
827 case UART_IOCTL_BREAK:
828 case UART_IOCTL_IFLOW:
829 case UART_IOCTL_OFLOW:
831 case UART_IOCTL_BAUD:
832 /* only if we know our master clock rate */
833 if (DEFAULT_RCLK != 0)
834 WR4(&sc->sc_bas, USART_BRGR,
835 BAUD2DIVISOR(*(int *)data));
843 at91_usart_bus_grab(struct uart_softc *sc)
846 uart_lock(sc->sc_hwmtx);
847 WR4(&sc->sc_bas, USART_IDR, USART_CSR_RXRDY);
848 uart_unlock(sc->sc_hwmtx);
852 at91_usart_bus_ungrab(struct uart_softc *sc)
855 uart_lock(sc->sc_hwmtx);
856 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY);
857 uart_unlock(sc->sc_hwmtx);
860 struct uart_class at91_usart_class = {
863 sizeof(struct at91_usart_softc),
864 .uc_ops = &at91_usart_ops,
869 static struct ofw_compat_data compat_data[] = {
870 {"atmel,at91rm9200-usart",(uintptr_t)&at91_usart_class},
871 {"atmel,at91sam9260-usart",(uintptr_t)&at91_usart_class},
872 {NULL, (uintptr_t)NULL},
874 UART_FDT_CLASS_AND_DEVICE(compat_data);