2 * Copyright (c) 2005 M. Warner Losh
3 * Copyright (c) 2005 Olivier Houchard
4 * Copyright (c) 2012 Ian Lepore
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
39 #include <machine/bus.h>
41 #include <dev/uart/uart.h>
42 #include <dev/uart/uart_cpu.h>
43 #include <dev/uart/uart_bus.h>
44 #include <arm/at91/at91_usartreg.h>
45 #include <arm/at91/at91_pdcreg.h>
46 #include <arm/at91/at91_piovar.h>
47 #include <arm/at91/at91_pioreg.h>
48 #include <arm/at91/at91rm92reg.h>
49 #include <arm/at91/at91var.h>
53 #define DEFAULT_RCLK at91_master_clock
54 #define USART_DEFAULT_FIFO_BYTES 128
56 #define USART_DCE_CHANGE_BITS (USART_CSR_CTSIC | USART_CSR_DCDIC | \
57 USART_CSR_DSRIC | USART_CSR_RIIC)
60 * High-level UART interface.
62 struct at91_usart_rx {
68 struct at91_usart_softc {
69 struct uart_softc base;
73 #define HAS_TIMEOUT 0x1
74 #define USE_RTS0_WORKAROUND 0x2
76 struct at91_usart_rx ping_pong[2];
77 struct at91_usart_rx *ping;
78 struct at91_usart_rx *pong;
81 #define RD4(bas, reg) \
82 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
83 #define WR4(bas, reg, value) \
84 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
86 #define SIGCHG(c, i, s, d) \
89 i |= (i & s) ? s : s | d; \
91 i = (i & s) ? (i & ~s) | d : i; \
95 #define BAUD2DIVISOR(b) \
96 ((((DEFAULT_RCLK * 10) / ((b) * 16)) + 5) / 10)
99 * Low-level UART interface.
101 static int at91_usart_probe(struct uart_bas *bas);
102 static void at91_usart_init(struct uart_bas *bas, int, int, int, int);
103 static void at91_usart_term(struct uart_bas *bas);
104 static void at91_usart_putc(struct uart_bas *bas, int);
105 static int at91_usart_rxready(struct uart_bas *bas);
106 static int at91_usart_getc(struct uart_bas *bas, struct mtx *hwmtx);
108 extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
111 at91_usart_param(struct uart_bas *bas, int baudrate, int databits,
112 int stopbits, int parity)
117 * Assume 3-wire RS-232 configuration.
118 * XXX Not sure how uart will present the other modes to us, so
119 * XXX they are unimplemented. maybe ioctl?
121 mr = USART_MR_MODE_NORMAL;
122 mr |= USART_MR_USCLKS_MCK; /* Assume MCK */
125 * Or in the databits requested
128 mr &= ~USART_MR_MODE9;
131 mr |= USART_MR_CHRL_5BITS;
134 mr |= USART_MR_CHRL_6BITS;
137 mr |= USART_MR_CHRL_7BITS;
140 mr |= USART_MR_CHRL_8BITS;
143 mr |= USART_MR_CHRL_8BITS | USART_MR_MODE9;
153 case UART_PARITY_NONE:
154 mr |= USART_MR_PAR_NONE;
156 case UART_PARITY_ODD:
157 mr |= USART_MR_PAR_ODD;
159 case UART_PARITY_EVEN:
160 mr |= USART_MR_PAR_EVEN;
162 case UART_PARITY_MARK:
163 mr |= USART_MR_PAR_MARK;
165 case UART_PARITY_SPACE:
166 mr |= USART_MR_PAR_SPACE;
173 * Or in the stop bits. Note: The hardware supports 1.5 stop
174 * bits in async mode, but there's no way to specify that
175 * AFAICT. Instead, rely on the convention documented at
176 * http://www.lammertbies.nl/comm/info/RS-232_specs.html which
177 * states that 1.5 stop bits are used for 5 bit bytes and
178 * 2 stop bits only for longer bytes.
181 mr |= USART_MR_NBSTOP_1;
182 else if (databits > 5)
183 mr |= USART_MR_NBSTOP_2;
185 mr |= USART_MR_NBSTOP_1_5;
188 * We want normal plumbing mode too, none of this fancy
189 * loopback or echo mode.
191 mr |= USART_MR_CHMODE_NORMAL;
193 mr &= ~USART_MR_MSBF; /* lsb first */
194 mr &= ~USART_MR_CKLO_SCK; /* Don't drive SCK */
196 WR4(bas, USART_MR, mr);
199 * Set the baud rate (only if we know our master clock rate)
201 if (DEFAULT_RCLK != 0)
202 WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate));
205 * Set the receive timeout based on the baud rate. The idea is to
206 * compromise between being responsive on an interactive connection and
207 * giving a bulk data sender a bit of time to queue up a new buffer
208 * without mistaking it for a stopping point in the transmission. For
209 * 19.2kbps and below, use 20 * bit time (2 characters). For faster
210 * connections use 500 microseconds worth of bits.
212 if (baudrate <= 19200)
213 WR4(bas, USART_RTOR, 20);
215 WR4(bas, USART_RTOR, baudrate / 2000);
216 WR4(bas, USART_CR, USART_CR_STTTO);
218 /* XXX Need to take possible synchronous mode into account */
222 static struct uart_ops at91_usart_ops = {
223 .probe = at91_usart_probe,
224 .init = at91_usart_init,
225 .term = at91_usart_term,
226 .putc = at91_usart_putc,
227 .rxready = at91_usart_rxready,
228 .getc = at91_usart_getc,
233 * Early printf support. This assumes that we have the SoC "system" devices
234 * mapped into AT91_BASE. To use this before we adjust the boostrap tables,
235 * you'll need to define SOCDEV_VA to be 0xdc000000 and SOCDEV_PA to be
236 * 0xfc000000 in your config file where you define EARLY_PRINTF
238 volatile uint32_t *at91_dbgu = (volatile uint32_t *)(AT91_BASE + AT91_DBGU0);
244 while (!(at91_dbgu[USART_CSR / 4] & USART_CSR_TXRDY))
246 at91_dbgu[USART_THR / 4] = c;
249 early_putc_t * early_putc = eputc;
253 at91_usart_probe(struct uart_bas *bas)
256 /* We know that this is always here */
261 * Initialize this device for use as a console.
264 at91_usart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
269 if (early_putc != NULL) {
270 printf("Early printf yielding control to the real console.\n");
276 * This routine is called multiple times, sometimes right after writing
277 * some output, and the last byte is still shifting out. If that's the
278 * case delay briefly before resetting, but don't loop on TXRDY because
279 * we don't want to hang here forever if the hardware is in a bad state.
281 if (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY))
284 at91_usart_param(bas, baudrate, databits, stopbits, parity);
286 /* Reset the rx and tx buffers and turn on rx and tx */
287 WR4(bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX);
288 WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
289 WR4(bas, USART_IDR, 0xffffffff);
293 * Free resources now that we're no longer the console. This appears to
294 * be never called, and I'm unsure quite what to do if I am called.
297 at91_usart_term(struct uart_bas *bas)
304 * Put a character of console output (so we do it here polling rather than
308 at91_usart_putc(struct uart_bas *bas, int c)
311 while (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY))
313 WR4(bas, USART_THR, c);
317 * Check for a character available.
320 at91_usart_rxready(struct uart_bas *bas)
323 return ((RD4(bas, USART_CSR) & USART_CSR_RXRDY) != 0 ? 1 : 0);
327 * Block waiting for a character.
330 at91_usart_getc(struct uart_bas *bas, struct mtx *hwmtx)
335 while (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY)) {
340 c = RD4(bas, USART_RHR) & 0xff;
345 static int at91_usart_bus_probe(struct uart_softc *sc);
346 static int at91_usart_bus_attach(struct uart_softc *sc);
347 static int at91_usart_bus_flush(struct uart_softc *, int);
348 static int at91_usart_bus_getsig(struct uart_softc *);
349 static int at91_usart_bus_ioctl(struct uart_softc *, int, intptr_t);
350 static int at91_usart_bus_ipend(struct uart_softc *);
351 static int at91_usart_bus_param(struct uart_softc *, int, int, int, int);
352 static int at91_usart_bus_receive(struct uart_softc *);
353 static int at91_usart_bus_setsig(struct uart_softc *, int);
354 static int at91_usart_bus_transmit(struct uart_softc *);
355 static void at91_usart_bus_grab(struct uart_softc *);
356 static void at91_usart_bus_ungrab(struct uart_softc *);
358 static kobj_method_t at91_usart_methods[] = {
359 KOBJMETHOD(uart_probe, at91_usart_bus_probe),
360 KOBJMETHOD(uart_attach, at91_usart_bus_attach),
361 KOBJMETHOD(uart_flush, at91_usart_bus_flush),
362 KOBJMETHOD(uart_getsig, at91_usart_bus_getsig),
363 KOBJMETHOD(uart_ioctl, at91_usart_bus_ioctl),
364 KOBJMETHOD(uart_ipend, at91_usart_bus_ipend),
365 KOBJMETHOD(uart_param, at91_usart_bus_param),
366 KOBJMETHOD(uart_receive, at91_usart_bus_receive),
367 KOBJMETHOD(uart_setsig, at91_usart_bus_setsig),
368 KOBJMETHOD(uart_transmit, at91_usart_bus_transmit),
369 KOBJMETHOD(uart_grab, at91_usart_bus_grab),
370 KOBJMETHOD(uart_ungrab, at91_usart_bus_ungrab),
376 at91_usart_bus_probe(struct uart_softc *sc)
380 value = USART_DEFAULT_FIFO_BYTES;
381 resource_int_value(device_get_name(sc->sc_dev),
382 device_get_unit(sc->sc_dev), "fifo_bytes", &value);
383 value = roundup2(value, arm_dcache_align);
384 sc->sc_txfifosz = value;
385 sc->sc_rxfifosz = value;
391 at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
396 *(bus_addr_t *)arg = segs[0].ds_addr;
400 at91_usart_requires_rts0_workaround(struct uart_softc *sc)
405 unit = device_get_unit(sc->sc_dev);
408 * On the rm9200 chips, the PA21/RTS0 pin is not correctly wired to the
409 * usart device interally (so-called 'erratum 39', but it's 41.14 in rev
410 * I of the manual). This prevents use of the hardware flow control
411 * feature in the usart itself. It also means that if we are to
412 * implement RTS/CTS flow via the tty layer logic, we must use pin PA21
413 * as a gpio and manually manipulate it in at91_usart_bus_setsig(). We
414 * can only safely do so if we've been given permission via a hint,
415 * otherwise we might manipulate a pin that's attached to who-knows-what
416 * and Bad Things could happen.
418 if (at91_is_rm92() && unit == 1) {
420 resource_int_value(device_get_name(sc->sc_dev), unit,
421 "use_rts0_workaround", &value);
423 at91_pio_use_gpio(AT91RM92_PIOA_BASE, AT91C_PIO_PA21);
424 at91_pio_gpio_output(AT91RM92_PIOA_BASE,
426 at91_pio_use_periph_a(AT91RM92_PIOA_BASE,
435 at91_usart_bus_attach(struct uart_softc *sc)
439 struct at91_usart_softc *atsc;
441 atsc = (struct at91_usart_softc *)sc;
443 if (at91_usart_requires_rts0_workaround(sc))
444 atsc->flags |= USE_RTS0_WORKAROUND;
447 * See if we have a TIMEOUT bit. We disable all interrupts as
448 * a side effect. Boot loaders may have enabled them. Since
449 * a TIMEOUT interrupt can't happen without other setup, the
450 * apparent race here can't actually happen.
452 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
453 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT);
454 if (RD4(&sc->sc_bas, USART_IMR) & USART_CSR_TIMEOUT)
455 atsc->flags |= HAS_TIMEOUT;
456 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
459 * Allocate transmit DMA tag and map. We allow a transmit buffer
460 * to be any size, but it must map to a single contiguous physical
463 err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
464 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
465 BUS_SPACE_MAXSIZE_32BIT, 1, BUS_SPACE_MAXSIZE_32BIT, 0, NULL,
466 NULL, &atsc->tx_tag);
469 err = bus_dmamap_create(atsc->tx_tag, 0, &atsc->tx_map);
473 if (atsc->flags & HAS_TIMEOUT) {
475 * Allocate receive DMA tags, maps, and buffers.
476 * The receive buffers should be aligned to arm_dcache_align,
477 * otherwise partial cache line flushes on every receive
478 * interrupt are pretty much guaranteed.
480 err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),
481 arm_dcache_align, 0, BUS_SPACE_MAXADDR_32BIT,
482 BUS_SPACE_MAXADDR, NULL, NULL, sc->sc_rxfifosz, 1,
483 sc->sc_rxfifosz, BUS_DMA_ALLOCNOW, NULL, NULL,
487 for (i = 0; i < 2; i++) {
488 err = bus_dmamem_alloc(atsc->rx_tag,
489 (void **)&atsc->ping_pong[i].buffer,
490 BUS_DMA_NOWAIT, &atsc->ping_pong[i].map);
493 err = bus_dmamap_load(atsc->rx_tag,
494 atsc->ping_pong[i].map,
495 atsc->ping_pong[i].buffer, sc->sc_rxfifosz,
496 at91_getaddr, &atsc->ping_pong[i].pa, 0);
499 bus_dmamap_sync(atsc->rx_tag, atsc->ping_pong[i].map,
500 BUS_DMASYNC_PREREAD);
502 atsc->ping = &atsc->ping_pong[0];
503 atsc->pong = &atsc->ping_pong[1];
506 /* Turn on rx and tx */
507 DELAY(1000); /* Give pending character a chance to drain. */
508 WR4(&sc->sc_bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX);
509 WR4(&sc->sc_bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
512 * Setup the PDC to receive data. We use the ping-pong buffers
513 * so that we can more easily bounce between the two and so that
514 * we get an interrupt 1/2 way through the software 'fifo' we have
517 if (atsc->flags & HAS_TIMEOUT) {
518 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
519 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
520 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
521 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
522 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
525 * Set the receive timeout to be 1.5 character times
528 WR4(&sc->sc_bas, USART_RTOR, 15);
529 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
530 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT |
531 USART_CSR_RXBUFF | USART_CSR_ENDRX);
533 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY);
535 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXBRK | USART_DCE_CHANGE_BITS);
537 /* Prime sc->hwsig with the initial hw line states. */
538 at91_usart_bus_getsig(sc);
545 at91_usart_bus_transmit(struct uart_softc *sc)
548 struct at91_usart_softc *atsc;
552 atsc = (struct at91_usart_softc *)sc;
553 uart_lock(sc->sc_hwmtx);
554 if (bus_dmamap_load(atsc->tx_tag, atsc->tx_map, sc->sc_txbuf,
555 sc->sc_txdatasz, at91_getaddr, &addr, 0) != 0) {
559 bus_dmamap_sync(atsc->tx_tag, atsc->tx_map, BUS_DMASYNC_PREWRITE);
562 * Setup the PDC to transfer the data and interrupt us when it
563 * is done. We've already requested the interrupt.
565 WR4(&sc->sc_bas, PDC_TPR, addr);
566 WR4(&sc->sc_bas, PDC_TCR, sc->sc_txdatasz);
567 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_TXTEN);
568 WR4(&sc->sc_bas, USART_IER, USART_CSR_ENDTX);
570 uart_unlock(sc->sc_hwmtx);
575 at91_usart_bus_setsig(struct uart_softc *sc, int sig)
577 uint32_t new, old, cr;
578 struct at91_usart_softc *atsc;
580 atsc = (struct at91_usart_softc *)sc;
586 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR);
588 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS);
589 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
593 cr |= USART_CR_DTREN;
595 cr |= USART_CR_DTRDIS;
597 cr |= USART_CR_RTSEN;
599 cr |= USART_CR_RTSDIS;
601 uart_lock(sc->sc_hwmtx);
602 WR4(&sc->sc_bas, USART_CR, cr);
603 if (atsc->flags & USE_RTS0_WORKAROUND) {
604 /* Signal is active-low. */
606 at91_pio_gpio_clear(AT91RM92_PIOA_BASE, AT91C_PIO_PA21);
608 at91_pio_gpio_set(AT91RM92_PIOA_BASE,AT91C_PIO_PA21);
610 uart_unlock(sc->sc_hwmtx);
616 at91_usart_bus_receive(struct uart_softc *sc)
623 at91_usart_bus_param(struct uart_softc *sc, int baudrate, int databits,
624 int stopbits, int parity)
627 return (at91_usart_param(&sc->sc_bas, baudrate, databits, stopbits,
632 at91_rx_put(struct uart_softc *sc, int key)
636 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE)
637 kdb_alt_break(key, &sc->sc_altbrk);
639 uart_rx_put(sc, key);
643 at91_usart_bus_ipend(struct uart_softc *sc)
645 struct at91_usart_softc *atsc;
646 struct at91_usart_rx *p;
651 atsc = (struct at91_usart_softc *)sc;
652 uart_lock(sc->sc_hwmtx);
653 csr = RD4(&sc->sc_bas, USART_CSR);
655 if (csr & USART_CSR_OVRE) {
656 WR4(&sc->sc_bas, USART_CR, USART_CR_RSTSTA);
657 ipend |= SER_INT_OVERRUN;
660 if (csr & USART_DCE_CHANGE_BITS)
661 ipend |= SER_INT_SIGCHG;
663 if (csr & USART_CSR_ENDTX) {
664 bus_dmamap_sync(atsc->tx_tag, atsc->tx_map,
665 BUS_DMASYNC_POSTWRITE);
666 bus_dmamap_unload(atsc->tx_tag, atsc->tx_map);
668 if (csr & (USART_CSR_TXRDY | USART_CSR_ENDTX)) {
670 ipend |= SER_INT_TXIDLE;
671 WR4(&sc->sc_bas, USART_IDR, csr & (USART_CSR_TXRDY |
676 * Due to the contraints of the DMA engine present in the
677 * atmel chip, I can't just say I have a rx interrupt pending
678 * and do all the work elsewhere. I need to look at the CSR
679 * bits right now and do things based on them to avoid races.
681 if (atsc->flags & HAS_TIMEOUT) {
682 if (csr & USART_CSR_RXBUFF) {
684 * We have a buffer overflow. Consume data from ping
685 * and give it back to the hardware before worrying
686 * about pong, to minimze data loss. Insert an overrun
687 * marker after the contents of the pong buffer.
689 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS);
690 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
691 BUS_DMASYNC_POSTREAD);
692 for (i = 0; i < sc->sc_rxfifosz; i++)
693 at91_rx_put(sc, atsc->ping->buffer[i]);
694 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
695 BUS_DMASYNC_PREREAD);
696 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
697 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
698 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
699 bus_dmamap_sync(atsc->rx_tag, atsc->pong->map,
700 BUS_DMASYNC_POSTREAD);
701 for (i = 0; i < sc->sc_rxfifosz; i++)
702 at91_rx_put(sc, atsc->pong->buffer[i]);
703 uart_rx_put(sc, UART_STAT_OVERRUN);
704 bus_dmamap_sync(atsc->rx_tag, atsc->pong->map,
705 BUS_DMASYNC_PREREAD);
706 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
707 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
708 ipend |= SER_INT_RXREADY;
709 } else if (csr & USART_CSR_ENDRX) {
711 * Consume data from ping of ping pong buffer, but leave
712 * current pong in place, as it has become the new ping.
713 * We need to copy data and setup the old ping as the
714 * new pong when we're done.
716 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
717 BUS_DMASYNC_POSTREAD);
718 for (i = 0; i < sc->sc_rxfifosz; i++)
719 at91_rx_put(sc, atsc->ping->buffer[i]);
721 atsc->ping = atsc->pong;
723 bus_dmamap_sync(atsc->rx_tag, atsc->pong->map,
724 BUS_DMASYNC_PREREAD);
725 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
726 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
727 ipend |= SER_INT_RXREADY;
728 } else if (csr & USART_CSR_TIMEOUT) {
730 * On a timeout, one of the following applies:
731 * 1. Two empty buffers. The last received byte exactly
732 * filled a buffer, causing an ENDTX that got
733 * processed earlier; no new bytes have arrived.
734 * 2. Ping buffer contains some data and pong is empty.
735 * This should be the most common timeout condition.
736 * 3. Ping buffer is full and pong is now being filled.
737 * This is exceedingly rare; it can happen only if
738 * the ping buffer is almost full when a timeout is
739 * signaled, and then dataflow resumes and the ping
740 * buffer filled up between the time we read the
741 * status register above and the point where the
742 * RXTDIS takes effect here. Yes, it can happen.
743 * Because dataflow can resume at any time following a
744 * timeout (it may have already resumed before we get
745 * here), it's important to minimize the time the PDC is
746 * disabled -- just long enough to take the ping buffer
747 * out of service (so we can consume it) and install the
748 * pong buffer as the active one. Note that in case 3
749 * the hardware has already done the ping-pong swap.
751 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS);
752 if (RD4(&sc->sc_bas, PDC_RNCR) == 0) {
753 len = sc->sc_rxfifosz;
755 len = sc->sc_rxfifosz - RD4(&sc->sc_bas, PDC_RCR);
756 WR4(&sc->sc_bas, PDC_RPR, atsc->pong->pa);
757 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
758 WR4(&sc->sc_bas, PDC_RNCR, 0);
760 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
761 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
762 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
763 BUS_DMASYNC_POSTREAD);
764 for (i = 0; i < len; i++)
765 at91_rx_put(sc, atsc->ping->buffer[i]);
766 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
767 BUS_DMASYNC_PREREAD);
769 atsc->ping = atsc->pong;
771 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
772 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
773 ipend |= SER_INT_RXREADY;
775 } else if (csr & USART_CSR_RXRDY) {
777 * We have another charater in a device that doesn't support
778 * timeouts, so we do it one character at a time.
780 at91_rx_put(sc, RD4(&sc->sc_bas, USART_RHR) & 0xff);
781 ipend |= SER_INT_RXREADY;
784 if (csr & USART_CSR_RXBRK) {
785 ipend |= SER_INT_BREAK;
786 WR4(&sc->sc_bas, USART_CR, USART_CR_RSTSTA);
788 uart_unlock(sc->sc_hwmtx);
793 at91_usart_bus_flush(struct uart_softc *sc, int what)
800 at91_usart_bus_getsig(struct uart_softc *sc)
802 uint32_t csr, new, old, sig;
805 * Note that the atmel channel status register DCE status bits reflect
806 * the electrical state of the lines, not the logical state. Since they
807 * are logically active-low signals, we invert the tests here.
812 csr = RD4(&sc->sc_bas, USART_CSR);
813 SIGCHG(!(csr & USART_CSR_DSR), sig, SER_DSR, SER_DDSR);
814 SIGCHG(!(csr & USART_CSR_CTS), sig, SER_CTS, SER_DCTS);
815 SIGCHG(!(csr & USART_CSR_DCD), sig, SER_DCD, SER_DDCD);
816 SIGCHG(!(csr & USART_CSR_RI), sig, SER_RI, SER_DRI);
817 new = sig & ~SER_MASK_DELTA;
818 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
824 at91_usart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
828 case UART_IOCTL_BREAK:
829 case UART_IOCTL_IFLOW:
830 case UART_IOCTL_OFLOW:
832 case UART_IOCTL_BAUD:
833 /* only if we know our master clock rate */
834 if (DEFAULT_RCLK != 0)
835 WR4(&sc->sc_bas, USART_BRGR,
836 BAUD2DIVISOR(*(int *)data));
844 at91_usart_bus_grab(struct uart_softc *sc)
847 uart_lock(sc->sc_hwmtx);
848 WR4(&sc->sc_bas, USART_IDR, USART_CSR_RXRDY);
849 uart_unlock(sc->sc_hwmtx);
853 at91_usart_bus_ungrab(struct uart_softc *sc)
856 uart_lock(sc->sc_hwmtx);
857 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY);
858 uart_unlock(sc->sc_hwmtx);
861 struct uart_class at91_usart_class = {
864 sizeof(struct at91_usart_softc),
865 .uc_ops = &at91_usart_ops,