2 * Copyright (c) 2005 M. Warner Losh
3 * Copyright (c) 2005 Olivier Houchard
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include "opt_comconsole.h"
33 #include <sys/param.h>
34 #include <sys/systm.h>
39 #include <machine/bus.h>
41 #include <dev/uart/uart.h>
42 #include <dev/uart/uart_cpu.h>
43 #include <dev/uart/uart_bus.h>
44 #include <arm/at91/at91rm92reg.h>
45 #include <arm/at91/at91_usartreg.h>
46 #include <arm/at91/at91_pdcreg.h>
54 #define uart_lock(x) mtx_lock_spin(&(x))
55 #define uart_unlock(x) mtx_unlock_spin(&(x))
56 #define DEFAULT_RCLK AT91C_MASTER_CLOCK
57 #define USART_BUFFER_SIZE 128
60 * High-level UART interface.
62 struct at91_usart_rx {
64 uint8_t buffer[USART_BUFFER_SIZE];
68 struct at91_usart_softc {
69 struct uart_softc base;
70 bus_dma_tag_t dmatag; /* bus dma tag for mbufs */
74 struct at91_usart_rx ping_pong[2];
75 struct at91_usart_rx *ping;
76 struct at91_usart_rx *pong;
79 #define RD4(bas, reg) \
80 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
81 #define WR4(bas, reg, value) \
82 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
84 #define SIGCHG(c, i, s, d) \
87 i |= (i & s) ? s : s | d; \
89 i = (i & s) ? (i & ~s) | d : i; \
93 #define BAUD2DIVISOR(b) \
94 ((((DEFAULT_RCLK * 10) / ((b) * 16)) + 5) / 10)
97 * Low-level UART interface.
99 static int at91_usart_probe(struct uart_bas *bas);
100 static void at91_usart_init(struct uart_bas *bas, int, int, int, int);
101 static void at91_usart_term(struct uart_bas *bas);
102 static void at91_usart_putc(struct uart_bas *bas, int);
103 static int at91_usart_poll(struct uart_bas *bas);
104 static int at91_usart_getc(struct uart_bas *bas);
106 extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
109 at91_usart_param(struct uart_bas *bas, int baudrate, int databits,
110 int stopbits, int parity)
115 * Assume 3-write RS-232 configuration.
116 * XXX Not sure how uart will present the other modes to us, so
117 * XXX they are unimplemented. maybe ioctl?
119 mr = USART_MR_MODE_NORMAL;
120 mr |= USART_MR_USCLKS_MCK; /* Assume MCK */
123 * Or in the databits requested
126 mr &= ~USART_MR_MODE9;
129 mr |= USART_MR_CHRL_5BITS;
132 mr |= USART_MR_CHRL_6BITS;
135 mr |= USART_MR_CHRL_7BITS;
138 mr |= USART_MR_CHRL_8BITS;
141 mr |= USART_MR_CHRL_8BITS | USART_MR_MODE9;
151 case UART_PARITY_NONE:
152 mr |= USART_MR_PAR_NONE;
154 case UART_PARITY_ODD:
155 mr |= USART_MR_PAR_ODD;
157 case UART_PARITY_EVEN:
158 mr |= USART_MR_PAR_EVEN;
160 case UART_PARITY_MARK:
161 mr |= USART_MR_PAR_MARK;
163 case UART_PARITY_SPACE:
164 mr |= USART_MR_PAR_SPACE;
171 * Or in the stop bits. Note: The hardware supports 1.5 stop
172 * bits in async mode, but there's no way to specify that
173 * AFAICT. Instead, rely on the convention documented at
174 * http://www.lammertbies.nl/comm/info/RS-232_specs.html which
175 * states that 1.5 stop bits are used for 5 bit bytes and
176 * 2 stop bits only for longer bytes.
179 mr |= USART_MR_NBSTOP_1;
180 else if (databits > 5)
181 mr |= USART_MR_NBSTOP_2;
183 mr |= USART_MR_NBSTOP_1_5;
186 * We want normal plumbing mode too, none of this fancy
187 * loopback or echo mode.
189 mr |= USART_MR_CHMODE_NORMAL;
191 mr &= ~USART_MR_MSBF; /* lsb first */
192 mr &= ~USART_MR_CKLO_SCK; /* Don't drive SCK */
194 WR4(bas, USART_MR, mr);
199 WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate));
201 /* XXX Need to take possible synchronous mode into account */
205 struct uart_ops at91_usart_ops = {
206 .probe = at91_usart_probe,
207 .init = at91_usart_init,
208 .term = at91_usart_term,
209 .putc = at91_usart_putc,
210 .poll = at91_usart_poll,
211 .getc = at91_usart_getc,
215 at91_usart_probe(struct uart_bas *bas)
217 /* We know that this is always here */
222 * Initialize this device for use as a console.
225 at91_usart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
229 at91_usart_param(bas, baudrate, databits, stopbits, parity);
231 /* Reset the rx and tx buffers and turn on rx and tx */
232 WR4(bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX);
233 WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
234 WR4(bas, USART_IDR, 0xffffffff);
238 * Free resources now that we're no longer the console. This appears to
239 * be never called, and I'm unsure quite what to do if I am called.
242 at91_usart_term(struct uart_bas *bas)
248 * Put a character of console output (so we do it here polling rather than
252 at91_usart_putc(struct uart_bas *bas, int c)
255 while (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY))
257 WR4(bas, USART_THR, c);
261 * Poll for a character available
264 at91_usart_poll(struct uart_bas *bas)
267 if (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY))
269 return (RD4(bas, USART_RHR) & 0xff);
273 * Block waiting for a character.
276 at91_usart_getc(struct uart_bas *bas)
280 while (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY))
282 c = RD4(bas, USART_RHR);
287 static int at91_usart_bus_probe(struct uart_softc *sc);
288 static int at91_usart_bus_attach(struct uart_softc *sc);
289 static int at91_usart_bus_flush(struct uart_softc *, int);
290 static int at91_usart_bus_getsig(struct uart_softc *);
291 static int at91_usart_bus_ioctl(struct uart_softc *, int, intptr_t);
292 static int at91_usart_bus_ipend(struct uart_softc *);
293 static int at91_usart_bus_param(struct uart_softc *, int, int, int, int);
294 static int at91_usart_bus_receive(struct uart_softc *);
295 static int at91_usart_bus_setsig(struct uart_softc *, int);
296 static int at91_usart_bus_transmit(struct uart_softc *);
298 static kobj_method_t at91_usart_methods[] = {
299 KOBJMETHOD(uart_probe, at91_usart_bus_probe),
300 KOBJMETHOD(uart_attach, at91_usart_bus_attach),
301 KOBJMETHOD(uart_flush, at91_usart_bus_flush),
302 KOBJMETHOD(uart_getsig, at91_usart_bus_getsig),
303 KOBJMETHOD(uart_ioctl, at91_usart_bus_ioctl),
304 KOBJMETHOD(uart_ipend, at91_usart_bus_ipend),
305 KOBJMETHOD(uart_param, at91_usart_bus_param),
306 KOBJMETHOD(uart_receive, at91_usart_bus_receive),
307 KOBJMETHOD(uart_setsig, at91_usart_bus_setsig),
308 KOBJMETHOD(uart_transmit, at91_usart_bus_transmit),
314 at91_usart_bus_probe(struct uart_softc *sc)
319 #ifndef SKYEYE_WORKAROUNDS
321 at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
325 *(bus_addr_t *)arg = segs[0].ds_addr;
330 at91_usart_bus_attach(struct uart_softc *sc)
334 struct at91_usart_softc *atsc;
336 atsc = (struct at91_usart_softc *)sc;
339 * See if we have a TIMEOUT bit. We disable all interrupts as
340 * a side effect. Boot loaders may have enabled them. Since
341 * a TIMEOUT interrupt can't happen without other setup, the
342 * apparent race here can't actually happen.
344 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
345 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT);
346 if (RD4(&sc->sc_bas, USART_IMR) & USART_CSR_TIMEOUT)
347 atsc->flags |= HAS_TIMEOUT;
348 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
350 sc->sc_txfifosz = USART_BUFFER_SIZE;
351 sc->sc_rxfifosz = USART_BUFFER_SIZE;
355 * Allocate DMA tags and maps
357 err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
358 BUS_SPACE_MAXADDR, NULL, NULL, USART_BUFFER_SIZE, 1,
359 USART_BUFFER_SIZE, BUS_DMA_ALLOCNOW, NULL, NULL, &atsc->dmatag);
362 err = bus_dmamap_create(atsc->dmatag, 0, &atsc->tx_map);
365 if (atsc->flags & HAS_TIMEOUT) {
366 for (i = 0; i < 2; i++) {
367 err = bus_dmamap_create(atsc->dmatag, 0,
368 &atsc->ping_pong[i].map);
371 err = bus_dmamap_load(atsc->dmatag,
372 atsc->ping_pong[i].map,
373 atsc->ping_pong[i].buffer, sc->sc_rxfifosz,
374 at91_getaddr, &atsc->ping_pong[i].pa, 0);
377 bus_dmamap_sync(atsc->dmatag, atsc->ping_pong[i].map,
378 BUS_DMASYNC_PREREAD);
380 atsc->ping = &atsc->ping_pong[0];
381 atsc->pong = &atsc->ping_pong[1];
385 * Prime the pump with the RX buffer. We use two 64 byte bounce
386 * buffers here to avoid data overflow.
389 /* Turn on rx and tx */
390 cr = USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX;
391 WR4(&sc->sc_bas, USART_CR, cr);
392 WR4(&sc->sc_bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
395 * Setup the PDC to receive data. We use the ping-pong buffers
396 * so that we can more easily bounce between the two and so that
397 * we get an interrupt 1/2 way through the software 'fifo' we have
400 if (atsc->flags & HAS_TIMEOUT) {
401 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
402 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
403 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
404 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
405 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
407 /* Set the receive timeout to be 1.5 character times. */
408 WR4(&sc->sc_bas, USART_RTOR, 12);
409 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
410 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT |
411 USART_CSR_RXBUFF | USART_CSR_ENDRX);
413 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY);
415 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXBRK);
422 at91_usart_bus_transmit(struct uart_softc *sc)
424 #ifndef SKYEYE_WORKAROUNDS
427 struct at91_usart_softc *atsc;
429 atsc = (struct at91_usart_softc *)sc;
430 #ifndef SKYEYE_WORKAROUNDS
431 if (bus_dmamap_load(atsc->dmatag, atsc->tx_map, sc->sc_txbuf,
432 sc->sc_txdatasz, at91_getaddr, &addr, 0) != 0)
434 bus_dmamap_sync(atsc->dmatag, atsc->tx_map, BUS_DMASYNC_PREWRITE);
437 uart_lock(sc->sc_hwmtx);
439 #ifndef SKYEYE_WORKAROUNDS
441 * Setup the PDC to transfer the data and interrupt us when it
442 * is done. We've already requested the interrupt.
444 WR4(&sc->sc_bas, PDC_TPR, addr);
445 WR4(&sc->sc_bas, PDC_TCR, sc->sc_txdatasz);
446 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_TXTEN);
447 WR4(&sc->sc_bas, USART_IER, USART_CSR_ENDTX);
448 uart_unlock(sc->sc_hwmtx);
450 for (int i = 0; i < sc->sc_txdatasz; i++)
451 at91_usart_putc(&sc->sc_bas, sc->sc_txbuf[i]);
453 * XXX: Gross hack : Skyeye doesn't raise an interrupt once the
454 * transfer is done, so simulate it.
456 WR4(&sc->sc_bas, USART_IER, USART_CSR_TXRDY);
461 at91_usart_bus_setsig(struct uart_softc *sc, int sig)
463 uint32_t new, old, cr;
464 struct uart_bas *bas;
470 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR);
472 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS);
473 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
475 uart_lock(sc->sc_hwmtx);
478 cr |= USART_CR_DTREN;
480 cr |= USART_CR_DTRDIS;
482 cr |= USART_CR_RTSEN;
484 cr |= USART_CR_RTSDIS;
485 WR4(bas, USART_CR, cr);
486 uart_unlock(sc->sc_hwmtx);
490 at91_usart_bus_receive(struct uart_softc *sc)
496 at91_usart_bus_param(struct uart_softc *sc, int baudrate, int databits,
497 int stopbits, int parity)
500 return (at91_usart_param(&sc->sc_bas, baudrate, databits, stopbits,
506 at91_rx_put(struct uart_softc *sc, int key)
508 #if defined(KDB) && defined(ALT_BREAK_TO_DEBUGGER)
509 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) {
510 if (kdb_alt_break(key, &sc->sc_altbrk))
511 kdb_enter("Break sequence to console");
514 uart_rx_put(sc, key);
518 at91_usart_bus_ipend(struct uart_softc *sc)
520 int csr = RD4(&sc->sc_bas, USART_CSR);
521 int ipend = 0, i, len;
522 struct at91_usart_softc *atsc;
523 struct at91_usart_rx *p;
525 atsc = (struct at91_usart_softc *)sc;
526 if (csr & USART_CSR_ENDTX) {
527 bus_dmamap_sync(atsc->dmatag, atsc->tx_map,
528 BUS_DMASYNC_POSTWRITE);
529 bus_dmamap_unload(atsc->dmatag, atsc->tx_map);
531 uart_lock(sc->sc_hwmtx);
532 if (csr & USART_CSR_TXRDY) {
534 ipend |= UART_IPEND_TXIDLE;
535 WR4(&sc->sc_bas, USART_IDR, USART_CSR_TXRDY);
537 if (csr & USART_CSR_ENDTX) {
539 ipend |= UART_IPEND_TXIDLE;
540 WR4(&sc->sc_bas, USART_IDR, USART_CSR_ENDTX);
544 * Due to the contraints of the DMA engine present in the
545 * atmel chip, I can't just say I have a rx interrupt pending
546 * and do all the work elsewhere. I need to look at the CSR
547 * bits right now and do things based on them to avoid races.
549 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXBUFF)) {
550 // Have a buffer overflow. Copy all data from both
551 // ping and pong. Insert overflow character. Reset
552 // ping and pong and re-enable the PDC to receive
554 bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
555 BUS_DMASYNC_POSTREAD);
556 bus_dmamap_sync(atsc->dmatag, atsc->pong->map,
557 BUS_DMASYNC_POSTREAD);
558 for (i = 0; i < sc->sc_rxfifosz; i++)
559 at91_rx_put(sc, atsc->ping->buffer[i]);
560 for (i = 0; i < sc->sc_rxfifosz; i++)
561 at91_rx_put(sc, atsc->pong->buffer[i]);
562 at91_rx_put(sc, UART_STAT_OVERRUN);
563 csr &= ~(USART_CSR_ENDRX | USART_CSR_TIMEOUT);
564 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
565 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
566 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
567 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
568 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
569 ipend |= UART_IPEND_RXREADY;
571 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_ENDRX)) {
572 // Shuffle data from 'ping' of ping pong buffer, but
573 // leave current 'pong' in place, as it has become the
574 // new 'ping'. We need to copy data and setup the old
575 // 'ping' as the new 'pong' when we're done.
576 bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
577 BUS_DMASYNC_POSTREAD);
578 for (i = 0; i < sc->sc_rxfifosz; i++)
579 at91_rx_put(sc, atsc->ping->buffer[i]);
581 atsc->ping = atsc->pong;
583 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
584 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
585 ipend |= UART_IPEND_RXREADY;
587 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_TIMEOUT)) {
588 // We have one partial buffer. We need to stop the
589 // PDC, get the number of characters left and from
590 // that compute number of valid characters. We then
591 // need to reset ping and pong and reenable the PDC.
592 // Not sure if there's a race here at fast baud rates
593 // we need to worry about.
594 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS);
595 bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
596 BUS_DMASYNC_POSTREAD);
597 len = sc->sc_rxfifosz - RD4(&sc->sc_bas, PDC_RCR);
598 for (i = 0; i < len; i++)
599 at91_rx_put(sc, atsc->ping->buffer[i]);
600 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
601 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
602 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
603 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
604 ipend |= UART_IPEND_RXREADY;
606 if (!(atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXRDY)) {
607 // We have another charater in a device that doesn't support
608 // timeouts, so we do it one character at a time.
609 at91_rx_put(sc, RD4(&sc->sc_bas, USART_RHR) & 0xff);
610 ipend |= UART_IPEND_RXREADY;
613 if (csr & USART_CSR_RXBRK) {
614 unsigned int cr = USART_CR_RSTSTA;
616 ipend |= UART_IPEND_BREAK;
617 WR4(&sc->sc_bas, USART_CR, cr);
619 uart_unlock(sc->sc_hwmtx);
623 at91_usart_bus_flush(struct uart_softc *sc, int what)
629 at91_usart_bus_getsig(struct uart_softc *sc)
634 uart_lock(sc->sc_hwmtx);
635 csr = RD4(&sc->sc_bas, USART_CSR);
637 if (csr & USART_CSR_CTS)
639 if (csr & USART_CSR_DCD)
641 if (csr & USART_CSR_DSR)
643 if (csr & USART_CSR_RI)
645 new = sig & ~UART_SIGMASK_DELTA;
647 uart_unlock(sc->sc_hwmtx);
652 at91_usart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
655 case UART_IOCTL_BREAK:
656 case UART_IOCTL_IFLOW:
657 case UART_IOCTL_OFLOW:
659 case UART_IOCTL_BAUD:
660 WR4(&sc->sc_bas, USART_BRGR, BAUD2DIVISOR(*(int *)data));
665 struct uart_class at91_usart_class = {
668 sizeof(struct at91_usart_softc),
670 .uc_rclk = DEFAULT_RCLK