2 * Copyright (c) 2005 M. Warner Losh
3 * Copyright (c) 2005 Olivier Houchard
4 * Copyright (c) 2012 Ian Lepore
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
39 #include <machine/bus.h>
41 #include <dev/uart/uart.h>
42 #include <dev/uart/uart_cpu.h>
43 #include <dev/uart/uart_bus.h>
44 #include <arm/at91/at91_usartreg.h>
45 #include <arm/at91/at91_pdcreg.h>
46 #include <arm/at91/at91_piovar.h>
47 #include <arm/at91/at91_pioreg.h>
48 #include <arm/at91/at91rm92reg.h>
49 #include <arm/at91/at91var.h>
53 #define DEFAULT_RCLK at91_master_clock
54 #define USART_DEFAULT_FIFO_BYTES 128
56 #define USART_DCE_CHANGE_BITS (USART_CSR_CTSIC | USART_CSR_DCDIC | \
57 USART_CSR_DSRIC | USART_CSR_RIIC)
60 * High-level UART interface.
62 struct at91_usart_rx {
68 struct at91_usart_softc {
69 struct uart_softc base;
73 #define HAS_TIMEOUT 0x1
74 #define USE_RTS0_WORKAROUND 0x2
75 #define NEEDS_RXRDY 0x4
77 struct at91_usart_rx ping_pong[2];
78 struct at91_usart_rx *ping;
79 struct at91_usart_rx *pong;
82 #define RD4(bas, reg) \
83 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
84 #define WR4(bas, reg, value) \
85 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
87 #define SIGCHG(c, i, s, d) \
90 i |= (i & s) ? s : s | d; \
92 i = (i & s) ? (i & ~s) | d : i; \
96 #define BAUD2DIVISOR(b) \
97 ((((DEFAULT_RCLK * 10) / ((b) * 16)) + 5) / 10)
100 * Low-level UART interface.
102 static int at91_usart_probe(struct uart_bas *bas);
103 static void at91_usart_init(struct uart_bas *bas, int, int, int, int);
104 static void at91_usart_term(struct uart_bas *bas);
105 static void at91_usart_putc(struct uart_bas *bas, int);
106 static int at91_usart_rxready(struct uart_bas *bas);
107 static int at91_usart_getc(struct uart_bas *bas, struct mtx *hwmtx);
109 extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
112 at91_usart_param(struct uart_bas *bas, int baudrate, int databits,
113 int stopbits, int parity)
118 * Assume 3-wire RS-232 configuration.
119 * XXX Not sure how uart will present the other modes to us, so
120 * XXX they are unimplemented. maybe ioctl?
122 mr = USART_MR_MODE_NORMAL;
123 mr |= USART_MR_USCLKS_MCK; /* Assume MCK */
126 * Or in the databits requested
129 mr &= ~USART_MR_MODE9;
132 mr |= USART_MR_CHRL_5BITS;
135 mr |= USART_MR_CHRL_6BITS;
138 mr |= USART_MR_CHRL_7BITS;
141 mr |= USART_MR_CHRL_8BITS;
144 mr |= USART_MR_CHRL_8BITS | USART_MR_MODE9;
154 case UART_PARITY_NONE:
155 mr |= USART_MR_PAR_NONE;
157 case UART_PARITY_ODD:
158 mr |= USART_MR_PAR_ODD;
160 case UART_PARITY_EVEN:
161 mr |= USART_MR_PAR_EVEN;
163 case UART_PARITY_MARK:
164 mr |= USART_MR_PAR_MARK;
166 case UART_PARITY_SPACE:
167 mr |= USART_MR_PAR_SPACE;
174 * Or in the stop bits. Note: The hardware supports 1.5 stop
175 * bits in async mode, but there's no way to specify that
176 * AFAICT. Instead, rely on the convention documented at
177 * http://www.lammertbies.nl/comm/info/RS-232_specs.html which
178 * states that 1.5 stop bits are used for 5 bit bytes and
179 * 2 stop bits only for longer bytes.
182 mr |= USART_MR_NBSTOP_1;
183 else if (databits > 5)
184 mr |= USART_MR_NBSTOP_2;
186 mr |= USART_MR_NBSTOP_1_5;
189 * We want normal plumbing mode too, none of this fancy
190 * loopback or echo mode.
192 mr |= USART_MR_CHMODE_NORMAL;
194 mr &= ~USART_MR_MSBF; /* lsb first */
195 mr &= ~USART_MR_CKLO_SCK; /* Don't drive SCK */
197 WR4(bas, USART_MR, mr);
200 * Set the baud rate (only if we know our master clock rate)
202 if (DEFAULT_RCLK != 0)
203 WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate));
206 * Set the receive timeout based on the baud rate. The idea is to
207 * compromise between being responsive on an interactive connection and
208 * giving a bulk data sender a bit of time to queue up a new buffer
209 * without mistaking it for a stopping point in the transmission. For
210 * 19.2kbps and below, use 20 * bit time (2 characters). For faster
211 * connections use 500 microseconds worth of bits.
213 if (baudrate <= 19200)
214 WR4(bas, USART_RTOR, 20);
216 WR4(bas, USART_RTOR, baudrate / 2000);
217 WR4(bas, USART_CR, USART_CR_STTTO);
219 /* XXX Need to take possible synchronous mode into account */
223 static struct uart_ops at91_usart_ops = {
224 .probe = at91_usart_probe,
225 .init = at91_usart_init,
226 .term = at91_usart_term,
227 .putc = at91_usart_putc,
228 .rxready = at91_usart_rxready,
229 .getc = at91_usart_getc,
233 at91_usart_probe(struct uart_bas *bas)
236 /* We know that this is always here */
241 * Initialize this device for use as a console.
244 at91_usart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
248 at91_usart_param(bas, baudrate, databits, stopbits, parity);
250 /* Reset the rx and tx buffers and turn on rx and tx */
251 WR4(bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX);
252 WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
253 WR4(bas, USART_IDR, 0xffffffff);
257 * Free resources now that we're no longer the console. This appears to
258 * be never called, and I'm unsure quite what to do if I am called.
261 at91_usart_term(struct uart_bas *bas)
268 * Put a character of console output (so we do it here polling rather than
272 at91_usart_putc(struct uart_bas *bas, int c)
275 while (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY))
277 WR4(bas, USART_THR, c);
281 * Check for a character available.
284 at91_usart_rxready(struct uart_bas *bas)
287 return ((RD4(bas, USART_CSR) & USART_CSR_RXRDY) != 0 ? 1 : 0);
291 * Block waiting for a character.
294 at91_usart_getc(struct uart_bas *bas, struct mtx *hwmtx)
299 while (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY)) {
304 c = RD4(bas, USART_RHR) & 0xff;
309 static int at91_usart_bus_probe(struct uart_softc *sc);
310 static int at91_usart_bus_attach(struct uart_softc *sc);
311 static int at91_usart_bus_flush(struct uart_softc *, int);
312 static int at91_usart_bus_getsig(struct uart_softc *);
313 static int at91_usart_bus_ioctl(struct uart_softc *, int, intptr_t);
314 static int at91_usart_bus_ipend(struct uart_softc *);
315 static int at91_usart_bus_param(struct uart_softc *, int, int, int, int);
316 static int at91_usart_bus_receive(struct uart_softc *);
317 static int at91_usart_bus_setsig(struct uart_softc *, int);
318 static int at91_usart_bus_transmit(struct uart_softc *);
320 static kobj_method_t at91_usart_methods[] = {
321 KOBJMETHOD(uart_probe, at91_usart_bus_probe),
322 KOBJMETHOD(uart_attach, at91_usart_bus_attach),
323 KOBJMETHOD(uart_flush, at91_usart_bus_flush),
324 KOBJMETHOD(uart_getsig, at91_usart_bus_getsig),
325 KOBJMETHOD(uart_ioctl, at91_usart_bus_ioctl),
326 KOBJMETHOD(uart_ipend, at91_usart_bus_ipend),
327 KOBJMETHOD(uart_param, at91_usart_bus_param),
328 KOBJMETHOD(uart_receive, at91_usart_bus_receive),
329 KOBJMETHOD(uart_setsig, at91_usart_bus_setsig),
330 KOBJMETHOD(uart_transmit, at91_usart_bus_transmit),
336 at91_usart_bus_probe(struct uart_softc *sc)
340 value = USART_DEFAULT_FIFO_BYTES;
341 resource_int_value(device_get_name(sc->sc_dev),
342 device_get_unit(sc->sc_dev), "fifo_bytes", &value);
343 value = roundup2(value, arm_dcache_align);
344 sc->sc_txfifosz = value;
345 sc->sc_rxfifosz = value;
351 at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
356 *(bus_addr_t *)arg = segs[0].ds_addr;
360 at91_usart_requires_rts0_workaround(struct uart_softc *sc)
365 unit = device_get_unit(sc->sc_dev);
368 * On the rm9200 chips, the PA21/RTS0 pin is not correctly wired to the
369 * usart device interally (so-called 'erratum 39', but it's 41.14 in rev
370 * I of the manual). This prevents use of the hardware flow control
371 * feature in the usart itself. It also means that if we are to
372 * implement RTS/CTS flow via the tty layer logic, we must use pin PA21
373 * as a gpio and manually manipulate it in at91_usart_bus_setsig(). We
374 * can only safely do so if we've been given permission via a hint,
375 * otherwise we might manipulate a pin that's attached to who-knows-what
376 * and Bad Things could happen.
378 if (at91_is_rm92() && unit == 1) {
380 resource_int_value(device_get_name(sc->sc_dev), unit,
381 "use_rts0_workaround", &value);
383 at91_pio_use_gpio(AT91RM92_PIOA_BASE, AT91C_PIO_PA21);
384 at91_pio_gpio_output(AT91RM92_PIOA_BASE,
386 at91_pio_use_periph_a(AT91RM92_PIOA_BASE,
395 at91_usart_bus_attach(struct uart_softc *sc)
400 struct at91_usart_softc *atsc;
402 atsc = (struct at91_usart_softc *)sc;
404 if (at91_usart_requires_rts0_workaround(sc))
405 atsc->flags |= USE_RTS0_WORKAROUND;
408 * See if we have a TIMEOUT bit. We disable all interrupts as
409 * a side effect. Boot loaders may have enabled them. Since
410 * a TIMEOUT interrupt can't happen without other setup, the
411 * apparent race here can't actually happen.
413 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
414 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT);
415 if (RD4(&sc->sc_bas, USART_IMR) & USART_CSR_TIMEOUT)
416 atsc->flags |= HAS_TIMEOUT;
417 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
420 * Allocate transmit DMA tag and map. We allow a transmit buffer
421 * to be any size, but it must map to a single contiguous physical
424 err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
425 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
426 BUS_SPACE_MAXSIZE_32BIT, 1, BUS_SPACE_MAXSIZE_32BIT, 0, NULL,
427 NULL, &atsc->tx_tag);
430 err = bus_dmamap_create(atsc->tx_tag, 0, &atsc->tx_map);
434 if (atsc->flags & HAS_TIMEOUT) {
436 * Allocate receive DMA tags, maps, and buffers.
437 * The receive buffers should be aligned to arm_dcache_align,
438 * otherwise partial cache line flushes on every receive
439 * interrupt are pretty much guaranteed.
441 err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),
442 arm_dcache_align, 0, BUS_SPACE_MAXADDR_32BIT,
443 BUS_SPACE_MAXADDR, NULL, NULL, sc->sc_rxfifosz, 1,
444 sc->sc_rxfifosz, BUS_DMA_ALLOCNOW, NULL, NULL,
448 for (i = 0; i < 2; i++) {
449 err = bus_dmamem_alloc(atsc->rx_tag,
450 (void **)&atsc->ping_pong[i].buffer,
451 BUS_DMA_NOWAIT, &atsc->ping_pong[i].map);
454 err = bus_dmamap_load(atsc->rx_tag,
455 atsc->ping_pong[i].map,
456 atsc->ping_pong[i].buffer, sc->sc_rxfifosz,
457 at91_getaddr, &atsc->ping_pong[i].pa, 0);
460 bus_dmamap_sync(atsc->rx_tag, atsc->ping_pong[i].map,
461 BUS_DMASYNC_PREREAD);
463 atsc->ping = &atsc->ping_pong[0];
464 atsc->pong = &atsc->ping_pong[1];
467 /* Turn on rx and tx */
468 cr = USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX;
469 WR4(&sc->sc_bas, USART_CR, cr);
470 WR4(&sc->sc_bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
473 * Setup the PDC to receive data. We use the ping-pong buffers
474 * so that we can more easily bounce between the two and so that
475 * we get an interrupt 1/2 way through the software 'fifo' we have
478 if (atsc->flags & HAS_TIMEOUT) {
479 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
480 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
481 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
482 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
483 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
486 * Set the receive timeout to be 1.5 character times
489 WR4(&sc->sc_bas, USART_RTOR, 15);
490 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
491 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT |
492 USART_CSR_RXBUFF | USART_CSR_ENDRX);
495 * Defer turning on the RXRDY bit until we're opened. This is to make the
496 * mountroot prompt work before we've opened the console. This is a workaround
497 * for not being able to change the UART interface for the 10.0 release.
499 atsc->flags |= NEEDS_RXRDY;
500 /* WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY); */
502 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXBRK | USART_DCE_CHANGE_BITS);
504 /* Prime sc->hwsig with the initial hw line states. */
505 at91_usart_bus_getsig(sc);
512 at91_usart_bus_transmit(struct uart_softc *sc)
515 struct at91_usart_softc *atsc;
519 atsc = (struct at91_usart_softc *)sc;
520 uart_lock(sc->sc_hwmtx);
521 if (bus_dmamap_load(atsc->tx_tag, atsc->tx_map, sc->sc_txbuf,
522 sc->sc_txdatasz, at91_getaddr, &addr, 0) != 0) {
526 bus_dmamap_sync(atsc->tx_tag, atsc->tx_map, BUS_DMASYNC_PREWRITE);
529 * Setup the PDC to transfer the data and interrupt us when it
530 * is done. We've already requested the interrupt.
532 WR4(&sc->sc_bas, PDC_TPR, addr);
533 WR4(&sc->sc_bas, PDC_TCR, sc->sc_txdatasz);
534 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_TXTEN);
535 WR4(&sc->sc_bas, USART_IER, USART_CSR_ENDTX);
537 uart_unlock(sc->sc_hwmtx);
542 at91_usart_bus_setsig(struct uart_softc *sc, int sig)
544 uint32_t new, old, cr;
545 struct at91_usart_softc *atsc;
547 atsc = (struct at91_usart_softc *)sc;
553 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR);
555 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS);
556 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
560 cr |= USART_CR_DTREN;
562 cr |= USART_CR_DTRDIS;
564 cr |= USART_CR_RTSEN;
566 cr |= USART_CR_RTSDIS;
568 uart_lock(sc->sc_hwmtx);
569 WR4(&sc->sc_bas, USART_CR, cr);
570 if (atsc->flags & USE_RTS0_WORKAROUND) {
571 /* Signal is active-low. */
573 at91_pio_gpio_clear(AT91RM92_PIOA_BASE, AT91C_PIO_PA21);
575 at91_pio_gpio_set(AT91RM92_PIOA_BASE,AT91C_PIO_PA21);
577 uart_unlock(sc->sc_hwmtx);
583 at91_usart_bus_receive(struct uart_softc *sc)
590 at91_usart_bus_param(struct uart_softc *sc, int baudrate, int databits,
591 int stopbits, int parity)
594 return (at91_usart_param(&sc->sc_bas, baudrate, databits, stopbits,
599 at91_rx_put(struct uart_softc *sc, int key)
603 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE)
604 kdb_alt_break(key, &sc->sc_altbrk);
606 uart_rx_put(sc, key);
610 at91_usart_bus_ipend(struct uart_softc *sc)
612 struct at91_usart_softc *atsc;
613 struct at91_usart_rx *p;
618 atsc = (struct at91_usart_softc *)sc;
619 uart_lock(sc->sc_hwmtx);
620 csr = RD4(&sc->sc_bas, USART_CSR);
622 /* Kludge -- Enable the RXRDY we deferred in attach */
623 if (sc->sc_opened && (atsc->flags & NEEDS_RXRDY)) {
624 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY);
625 atsc->flags &= ~NEEDS_RXRDY;
628 if (csr & USART_CSR_OVRE) {
629 WR4(&sc->sc_bas, USART_CR, USART_CR_RSTSTA);
630 ipend |= SER_INT_OVERRUN;
633 if (csr & USART_DCE_CHANGE_BITS)
634 ipend |= SER_INT_SIGCHG;
636 if (csr & USART_CSR_ENDTX) {
637 bus_dmamap_sync(atsc->tx_tag, atsc->tx_map,
638 BUS_DMASYNC_POSTWRITE);
639 bus_dmamap_unload(atsc->tx_tag, atsc->tx_map);
641 if (csr & (USART_CSR_TXRDY | USART_CSR_ENDTX)) {
643 ipend |= SER_INT_TXIDLE;
644 WR4(&sc->sc_bas, USART_IDR, csr & (USART_CSR_TXRDY |
649 * Due to the contraints of the DMA engine present in the
650 * atmel chip, I can't just say I have a rx interrupt pending
651 * and do all the work elsewhere. I need to look at the CSR
652 * bits right now and do things based on them to avoid races.
654 if (atsc->flags & HAS_TIMEOUT) {
655 if (csr & USART_CSR_RXBUFF) {
657 * We have a buffer overflow. Consume data from ping
658 * and give it back to the hardware before worrying
659 * about pong, to minimze data loss. Insert an overrun
660 * marker after the contents of the pong buffer.
662 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS);
663 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
664 BUS_DMASYNC_POSTREAD);
665 for (i = 0; i < sc->sc_rxfifosz; i++)
666 at91_rx_put(sc, atsc->ping->buffer[i]);
667 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
668 BUS_DMASYNC_PREREAD);
669 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
670 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
671 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
672 bus_dmamap_sync(atsc->rx_tag, atsc->pong->map,
673 BUS_DMASYNC_POSTREAD);
674 for (i = 0; i < sc->sc_rxfifosz; i++)
675 at91_rx_put(sc, atsc->pong->buffer[i]);
676 uart_rx_put(sc, UART_STAT_OVERRUN);
677 bus_dmamap_sync(atsc->rx_tag, atsc->pong->map,
678 BUS_DMASYNC_PREREAD);
679 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
680 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
681 ipend |= SER_INT_RXREADY;
682 } else if (csr & USART_CSR_ENDRX) {
684 * Consume data from ping of ping pong buffer, but leave
685 * current pong in place, as it has become the new ping.
686 * We need to copy data and setup the old ping as the
687 * new pong when we're done.
689 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
690 BUS_DMASYNC_POSTREAD);
691 for (i = 0; i < sc->sc_rxfifosz; i++)
692 at91_rx_put(sc, atsc->ping->buffer[i]);
694 atsc->ping = atsc->pong;
696 bus_dmamap_sync(atsc->rx_tag, atsc->pong->map,
697 BUS_DMASYNC_PREREAD);
698 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
699 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
700 ipend |= SER_INT_RXREADY;
701 } else if (csr & USART_CSR_TIMEOUT) {
703 * On a timeout, one of the following applies:
704 * 1. Two empty buffers. The last received byte exactly
705 * filled a buffer, causing an ENDTX that got
706 * processed earlier; no new bytes have arrived.
707 * 2. Ping buffer contains some data and pong is empty.
708 * This should be the most common timeout condition.
709 * 3. Ping buffer is full and pong is now being filled.
710 * This is exceedingly rare; it can happen only if
711 * the ping buffer is almost full when a timeout is
712 * signaled, and then dataflow resumes and the ping
713 * buffer filled up between the time we read the
714 * status register above and the point where the
715 * RXTDIS takes effect here. Yes, it can happen.
716 * Because dataflow can resume at any time following a
717 * timeout (it may have already resumed before we get
718 * here), it's important to minimize the time the PDC is
719 * disabled -- just long enough to take the ping buffer
720 * out of service (so we can consume it) and install the
721 * pong buffer as the active one. Note that in case 3
722 * the hardware has already done the ping-pong swap.
724 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS);
725 if (RD4(&sc->sc_bas, PDC_RNCR) == 0) {
726 len = sc->sc_rxfifosz;
728 len = sc->sc_rxfifosz - RD4(&sc->sc_bas, PDC_RCR);
729 WR4(&sc->sc_bas, PDC_RPR, atsc->pong->pa);
730 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
731 WR4(&sc->sc_bas, PDC_RNCR, 0);
733 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
734 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
735 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
736 BUS_DMASYNC_POSTREAD);
737 for (i = 0; i < len; i++)
738 at91_rx_put(sc, atsc->ping->buffer[i]);
739 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
740 BUS_DMASYNC_PREREAD);
742 atsc->ping = atsc->pong;
744 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
745 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
746 ipend |= SER_INT_RXREADY;
748 } else if (csr & USART_CSR_RXRDY) {
750 * We have another charater in a device that doesn't support
751 * timeouts, so we do it one character at a time.
753 at91_rx_put(sc, RD4(&sc->sc_bas, USART_RHR) & 0xff);
754 ipend |= SER_INT_RXREADY;
757 if (csr & USART_CSR_RXBRK) {
758 ipend |= SER_INT_BREAK;
759 WR4(&sc->sc_bas, USART_CR, USART_CR_RSTSTA);
761 uart_unlock(sc->sc_hwmtx);
766 at91_usart_bus_flush(struct uart_softc *sc, int what)
773 at91_usart_bus_getsig(struct uart_softc *sc)
775 uint32_t csr, new, old, sig;
778 * Note that the atmel channel status register DCE status bits reflect
779 * the electrical state of the lines, not the logical state. Since they
780 * are logically active-low signals, we invert the tests here.
785 csr = RD4(&sc->sc_bas, USART_CSR);
786 SIGCHG(!(csr & USART_CSR_DSR), sig, SER_DSR, SER_DDSR);
787 SIGCHG(!(csr & USART_CSR_CTS), sig, SER_CTS, SER_DCTS);
788 SIGCHG(!(csr & USART_CSR_DCD), sig, SER_DCD, SER_DDCD);
789 SIGCHG(!(csr & USART_CSR_RI), sig, SER_RI, SER_DRI);
790 new = sig & ~SER_MASK_DELTA;
791 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
797 at91_usart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
801 case UART_IOCTL_BREAK:
802 case UART_IOCTL_IFLOW:
803 case UART_IOCTL_OFLOW:
805 case UART_IOCTL_BAUD:
806 /* only if we know our master clock rate */
807 if (DEFAULT_RCLK != 0)
808 WR4(&sc->sc_bas, USART_BRGR,
809 BAUD2DIVISOR(*(int *)data));
815 struct uart_class at91_usart_class = {
818 sizeof(struct at91_usart_softc),
819 .uc_ops = &at91_usart_ops,